[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/regbase/cpu_info.h b/mcu/interface/driver/regbase/cpu_info.h
new file mode 100644
index 0000000..cd00f32
--- /dev/null
+++ b/mcu/interface/driver/regbase/cpu_info.h
@@ -0,0 +1,22 @@
+#ifndef __CPU_INFO_H__
+#define __CPU_INFO_H__
+
+#undef SYS_MCU_NUM_CORE
+#undef SYS_MCU_NUM_VPE
+#undef SYS_MCU_NUM_TC
+#undef SYS_MCU_GIC_EXIST
+#undef SYS_MCU_TYPE_MR2
+
+#if defined(__MD93__)
+ #include "md93/cpu_info_md93.h"
+#elif defined(__MD95__)
+ #include "md95/cpu_info_md95.h"
+#elif defined(__MD97__)
+ #include "md97/cpu_info_md97.h"
+#elif defined(__MD97P__)
+ #include "md97p/cpu_info_md97p.h"
+#else
+ #error "ERROR in cpu_info define (cpu_info.h)"
+#endif
+
+#endif /* __CPU_INFO_H__ */
diff --git a/mcu/interface/driver/regbase/mase3g_reg_base.h b/mcu/interface/driver/regbase/mase3g_reg_base.h
new file mode 100644
index 0000000..4963adf
--- /dev/null
+++ b/mcu/interface/driver/regbase/mase3g_reg_base.h
@@ -0,0 +1,223 @@
+#ifndef __MASE_REG_BASE_H__
+#define __MASE_REG_BASE_H__
+
+/* This is a regbase file for MASE cosim */
+/* If you want to define regbase, please undef it first to avoid duplicated definiation in general regbase file */
+/* All register base including Normal/Device/SO type in general regbase file will be driected to dummy register */
+
+#define MDSYS_PERI_ACC_TYPE_MASK (0xF0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0x80000000)
+#define DEV_REG_BASE(addr) ((addr & ~MDSYS_PERI_ACC_TYPE_MASK) | MDSYS_PERI_DEVICE_TYPE)
+
+/* redefine reg base in general regbase file */
+#undef BASE_MADDR_MDCIRQ
+#define BASE_MADDR_MDCIRQ (0xF0070000)
+#undef BASE_ADDR_MDCIRQ
+#define BASE_ADDR_MDCIRQ DEV_REG_BASE(BASE_MADDR_MDCIRQ)
+
+#undef BASE_MADDR_L2ULSBDMA
+#define BASE_MADDR_L2ULSBDMA (0xF0800000)
+#undef BASE_ADDR_L2ULSBDMA
+#define BASE_ADDR_L2ULSBDMA DEV_REG_BASE(BASE_MADDR_L2ULSBDMA)
+
+#undef BASE_MADDR_L2ULHBDMA
+#define BASE_MADDR_L2ULHBDMA (0xF0810000)
+#undef BASE_ADDR_L2ULHBDMA
+#define BASE_ADDR_L2ULHBDMA DEV_REG_BASE(BASE_MADDR_L2ULHBDMA)
+
+#undef BASE_MADDR_L2DLSBDMA
+#define BASE_MADDR_L2DLSBDMA (0xF0820000)
+#undef BASE_ADDR_L2DLSBDMA
+#define BASE_ADDR_L2DLSBDMA DEV_REG_BASE(BASE_MADDR_L2DLSBDMA)
+
+#undef BASE_MADDR_L2DLHBDMA
+#define BASE_MADDR_L2DLHBDMA (0xF0830000)
+#undef BASE_ADDR_L2DLHBDMA
+#define BASE_ADDR_L2DLHBDMA DEV_REG_BASE(BASE_MADDR_L2DLHBDMA)
+
+#undef BASE_MADDR_L2MBIST
+#define BASE_MADDR_L2MBIST (0xF0840000)
+#undef BASE_ADDR_L2MBIST
+#define BASE_ADDR_L2MBIST DEV_REG_BASE(BASE_MADDR_L2MBIST)
+
+#undef BASE_MADDR_L2PSEUPHY
+#define BASE_MADDR_L2PSEUPHY (0xF0850000)
+#undef BASE_ADDR_L2PSEUPHY
+#define BASE_ADDR_L2PSEUPHY DEV_REG_BASE(BASE_MADDR_L2PSEUPHY)
+
+#undef BASE_MADDR_L2HWLOG
+#define BASE_MADDR_L2HWLOG (0xF0858000)
+#undef BASE_ADDR_L2HWLOG
+#define BASE_ADDR_L2HWLOG DEV_REG_BASE(BASE_MADDR_L2HWLOG)
+
+#undef BASE_MADDR_L2SOINDMA
+#define BASE_MADDR_L2SOINDMA (0xF0860000)
+#undef BASE_ADDR_L2SOINDMA
+#define BASE_ADDR_L2SOINDMA DEV_REG_BASE(BASE_MADDR_L2SOINDMA)
+
+#undef BASE_MADDR_L2SOOUTDMA
+#define BASE_MADDR_L2SOOUTDMA (0xF0870000)
+#undef BASE_ADDR_L2SOOUTDMA
+#define BASE_ADDR_L2SOOUTDMA DEV_REG_BASE(BASE_MADDR_L2SOOUTDMA)
+
+#undef BASE_MADDR_L2ULLMAC
+#define BASE_MADDR_L2ULLMAC (0xF0880000)
+#undef BASE_ADDR_L2ULLMAC
+#define BASE_ADDR_L2ULLMAC DEV_REG_BASE(BASE_MADDR_L2ULLMAC)
+
+#undef BASE_MADDR_L2DLLMAC
+#define BASE_MADDR_L2DLLMAC (0xF0890000)
+#undef BASE_ADDR_L2DLLMAC
+#define BASE_ADDR_L2DLLMAC DEV_REG_BASE(BASE_MADDR_L2DLLMAC)
+
+#undef BASE_MADDR_L2CALMAC
+#define BASE_MADDR_L2CALMAC (0xF0898000)
+#undef BASE_ADDR_L2CALMAC
+#define BASE_ADDR_L2CALMAC DEV_REG_BASE(BASE_MADDR_L2CALMAC)
+
+#undef BASE_MADDR_L2ULFIFOMNG
+#define BASE_MADDR_L2ULFIFOMNG (0xF08A0000)
+#undef BASE_ADDR_L2ULFIFOMNG
+#define BASE_ADDR_L2ULFIFOMNG DEV_REG_BASE(BASE_MADDR_L2ULFIFOMNG)
+
+#undef BASE_MADDR_L2DLFIFOMNG
+#define BASE_MADDR_L2DLFIFOMNG (0xF08A4000)
+#undef BASE_ADDR_L2DLFIFOMNG
+#define BASE_ADDR_L2DLFIFOMNG DEV_REG_BASE(BASE_MADDR_L2DLFIFOMNG)
+
+#undef BASE_MADDR_L2SOFIFOMNG
+#define BASE_MADDR_L2SOFIFOMNG (0xF08A8000)
+#undef BASE_ADDR_L2SOFIFOMNG
+#define BASE_ADDR_L2SOFIFOMNG DEV_REG_BASE(BASE_MADDR_L2SOFIFOMNG)
+
+#undef BASE_MADDR_L2SEC
+#define BASE_MADDR_L2SEC (0xF08B0000)
+#undef BASE_ADDR_L2SEC
+#define BASE_ADDR_L2SEC DEV_REG_BASE(BASE_MADDR_L2SEC)
+
+#undef BASE_MADDR_L2ULSECCTL
+#define BASE_MADDR_L2ULSECCTL (0xF08B4000)
+#undef BASE_ADDR_L2ULSECCTL
+#define BASE_ADDR_L2ULSECCTL DEV_REG_BASE(BASE_MADDR_L2ULSECCTL)
+
+#undef BASE_MADDR_L2DLSECCTL
+#define BASE_MADDR_L2DLSECCTL (0xF08B8000)
+#undef BASE_ADDR_L2DLSECCTL
+#define BASE_ADDR_L2DLSECCTL DEV_REG_BASE(BASE_MADDR_L2DLSECCTL)
+
+#undef BASE_MADDR_L2SOSECCTL
+#define BASE_MADDR_L2SOSECCTL (0xF08BC000)
+#undef BASE_ADDR_L2SOSECCTL
+#define BASE_ADDR_L2SOSECCTL DEV_REG_BASE(BASE_MADDR_L2SOSECCTL)
+
+#undef BASE_MADDR_L2MISC
+#define BASE_MADDR_L2MISC (0xF08C0000)
+#undef BASE_ADDR_L2MISC
+#define BASE_ADDR_L2MISC DEV_REG_BASE(BASE_MADDR_L2MISC)
+
+#undef BASE_MADDR_L2DBGMON
+#define BASE_MADDR_L2DBGMON (0xF08D0000)
+#undef BASE_ADDR_L2DBGMON
+#define BASE_ADDR_L2DBGMON DEV_REG_BASE(BASE_MADDR_L2DBGMON)
+
+#undef BASE_MADDR_L2ULBUFMNG
+#define BASE_MADDR_L2ULBUFMNG (0xF08E0000)
+#undef BASE_ADDR_L2ULBUFMNG
+#define BASE_ADDR_L2ULBUFMNG DEV_REG_BASE(BASE_MADDR_L2ULBUFMNG)
+
+#undef BASE_MADDR_L2DLBUFMNG
+#define BASE_MADDR_L2DLBUFMNG (0xF08F0000)
+#undef BASE_ADDR_L2DLBUFMNG
+#define BASE_ADDR_L2DLBUFMNG DEV_REG_BASE(BASE_MADDR_L2DLBUFMNG)
+
+
+#define BASE_ADDR_SIMCTRL (0xFFFF1000)
+#define BASE_ADDR_HSL (0xFFFF2000)
+
+#define DUMMY_PERI_base (0x82030000)
+#define DUMMY_2G_base (0xA0000000)
+#define DUMMY_3G_base (0xA0000000)
+
+/* Stephen 2014:
+ * ARM7 shall not be used.
+ * Thus, put MASE modem register here
+ */
+#define BASE_ADDR_BSI (0xE0000000)
+#define BASE_ADDR_BPI (0xE0010000)
+#define BASE_ADDR_DPA_BC (0xE0020000)
+
+#define BASE_ADDR_DPA_RLC (0xE0100000)
+#define BASE_ADDR_DPA_MAC (0xE0110000)
+#define BASE_ADDR_UPA (0xE0120000)
+#define BASE_ADDR_H_RXBRP (0xE0130000)
+#define BASE_ADDR_RXBRP (0xE0140000)
+#define BASE_ADDR_TXBRP (0xE0150000)
+#define BASE_ADDR_H_TXBRP (0xE0160000)
+#define BASE_ADDR_TXCRP (0xE0170000)
+
+#define BASE_ADDR_RXSRP (0xE0200000)
+#define BASE_ADDR_RAKE_0 (0xE0210000)
+#define BASE_ADDR_SEARCHER (0xE0220000)
+#define BASE_ADDR_LOG3G (0xE0230000)
+
+#define BASE_ADDR_BFE (0xE0300000)
+#define BASE_ADDR_MDCIRQ (0xE0310000) // BAES_ADDR_MD_GIPL_IPE_PV
+// remember to sync to cwr_hw_define.h INT_CONTROLLER_BASE
+#define BASE_ADDR_DBG (0xE0320000)
+#define BASE_ADDR_TDMA (0xE0330000)
+#define BASE_ADDR_AFC (0xE0340000)
+#define BASE_ADDR_AUXADC (0xE0350000)
+
+#define BASE_MADDR_PFC (0xE0400000)
+#define BASE_MADDR_PFCEN (BASE_MADDR_PFC)
+#define BASE_MADDR_PFCDE (BASE_MADDR_PFC + 0x4000)
+
+/* Although some of the following address are not used in SW load
+ * They shall sync to the cpp/hpp file in C model
+ * Defined here is just to check with HW ESL memory map table
+ */
+#define BAES_ADDR_SIM_CTRL (0xE0500000)
+#define BAES_ADDR_TEST_CFG (0xE0510000)
+// #define BAES_ADDR_MD_GIPL_IPE_PV (0xE0520000)
+#define BAES_ADDR_UL1_HSDPA (0xE0530000)
+#define BAES_ADDR_UMTS_TIMER (0xE0540000)
+#define BAES_ADDR_TRACE_MODULE (0xE0550000) // remember to sync to cwr_hw_define.h TRACE_MODULE_BASE
+#define BAES_ADDR_PFC_MODEL (0xE0560000)
+#define BAES_ADDR_USB_MODEL (0xE0570000)
+
+#define BASE_ADDR_EMI_DUMMY_CFG (0xE0580000)
+
+// Stephen: The following 2 address is set in 'Memory Map Table' of ESL Platform
+#define BAES_ADDR_LMU_MEM (0xE0600000)
+#define BAES_ADDR_NV2STUB (0xE0610000)
+
+#define BASE_MADDR_MDCIRQ (0xF0810000)
+
+#define RTR_base (DUMMY_PERI_base + 0x41500)
+#define RAKE_base (BASE_ADDR_RAKE_0)
+#define CIRQ_base (BASE_ADDR_MDCIRQ)
+
+#define BASE_MEM_TYPE_STRONGLY_ORDER (0x00000000) /* 0xF0000000 */
+
+/*AP GPIO*/
+#define GPIO_base (0xA0005000)
+
+
+/* Sync address as HW platform */
+#undef UPA_base
+#define UPA_base (BASE_ADDR_UPA)
+
+#undef HSUPA_base
+#define HSUPA_base (BASE_ADDR_UPA)
+
+#undef UPA_SRAM_base
+#define UPA_SRAM_base (BASE_MADDR_HSPAL2_UPA_SRAM) // Same as original
+
+#undef DPA_MAC_base
+#define DPA_MAC_base (BASE_ADDR_DPA_MAC)
+
+#undef DPA_RLC_base
+#define DPA_RLC_base (BASE_ADDR_DPA_RLC)
+
+
+#endif /* end of __MASE_REG_BASE_H__ */
diff --git a/mcu/interface/driver/regbase/mase4g_reg_base.h b/mcu/interface/driver/regbase/mase4g_reg_base.h
new file mode 100644
index 0000000..68fd8de
--- /dev/null
+++ b/mcu/interface/driver/regbase/mase4g_reg_base.h
@@ -0,0 +1,149 @@
+#ifndef __MASE_REG_BASE_H__
+#define __MASE_REG_BASE_H__
+
+/* This is a regbase file for MASE cosim */
+/* If you want to define regbase, please undef it first to avoid duplicated definiation in general regbase file */
+/* All register base including Normal/Device/SO type in general regbase file will be driected to dummy register */
+
+#undef MDSYS_PERI_ACC_TYPE_MASK
+#define MDSYS_PERI_ACC_TYPE_MASK (0xF0000000)
+#undef MDSYS_PERI_DEVICE_TYPE
+#define MDSYS_PERI_DEVICE_TYPE (0xF0000000)
+#define DEV_REG_BASE(addr) ((addr & ~MDSYS_PERI_ACC_TYPE_MASK) | MDSYS_PERI_DEVICE_TYPE)
+
+#undef BASE_MADDR_MDCIRQ
+#define BASE_MADDR_MDCIRQ (0xF0070000)
+#undef BASE_ADDR_MDCIRQ
+#define BASE_ADDR_MDCIRQ DEV_REG_BASE(BASE_MADDR_MDCIRQ)
+
+#undef BASE_MADDR_L2ULSBDMA
+#define BASE_MADDR_L2ULSBDMA (0xF0800000)
+#undef BASE_ADDR_L2ULSBDMA
+#define BASE_ADDR_L2ULSBDMA DEV_REG_BASE(BASE_MADDR_L2ULSBDMA)
+
+#undef BASE_MADDR_L2ULHBDMA
+#define BASE_MADDR_L2ULHBDMA (0xF0810000)
+#undef BASE_ADDR_L2ULHBDMA
+#define BASE_ADDR_L2ULHBDMA DEV_REG_BASE(BASE_MADDR_L2ULHBDMA)
+
+#undef BASE_MADDR_L2DLSBDMA
+#define BASE_MADDR_L2DLSBDMA (0xF0820000)
+#undef BASE_ADDR_L2DLSBDMA
+#define BASE_ADDR_L2DLSBDMA DEV_REG_BASE(BASE_MADDR_L2DLSBDMA)
+
+#undef BASE_MADDR_L2DLHBDMA
+#define BASE_MADDR_L2DLHBDMA (0xF0830000)
+#undef BASE_ADDR_L2DLHBDMA
+#define BASE_ADDR_L2DLHBDMA DEV_REG_BASE(BASE_MADDR_L2DLHBDMA)
+
+#undef BASE_MADDR_L2MBIST
+#define BASE_MADDR_L2MBIST (0xF0840000)
+#undef BASE_ADDR_L2MBIST
+#define BASE_ADDR_L2MBIST DEV_REG_BASE(BASE_MADDR_L2MBIST)
+
+#undef BASE_MADDR_L2PSEUPHY
+#define BASE_MADDR_L2PSEUPHY (0xF0850000)
+#undef BASE_ADDR_L2PSEUPHY
+#define BASE_ADDR_L2PSEUPHY DEV_REG_BASE(BASE_MADDR_L2PSEUPHY)
+
+#undef BASE_MADDR_L2HWLOG
+#define BASE_MADDR_L2HWLOG (0xF0858000)
+#undef BASE_ADDR_L2HWLOG
+#define BASE_ADDR_L2HWLOG DEV_REG_BASE(BASE_MADDR_L2HWLOG)
+
+#undef BASE_MADDR_L2SOINDMA
+#define BASE_MADDR_L2SOINDMA (0xF0860000)
+#undef BASE_ADDR_L2SOINDMA
+#define BASE_ADDR_L2SOINDMA DEV_REG_BASE(BASE_MADDR_L2SOINDMA)
+
+#undef BASE_MADDR_L2SOOUTDMA
+#define BASE_MADDR_L2SOOUTDMA (0xF0870000)
+#undef BASE_ADDR_L2SOOUTDMA
+#define BASE_ADDR_L2SOOUTDMA DEV_REG_BASE(BASE_MADDR_L2SOOUTDMA)
+
+#undef BASE_MADDR_L2ULLMAC
+#define BASE_MADDR_L2ULLMAC (0xF0880000)
+#undef BASE_ADDR_L2ULLMAC
+#define BASE_ADDR_L2ULLMAC DEV_REG_BASE(BASE_MADDR_L2ULLMAC)
+
+#undef BASE_MADDR_L2ULLMAC_CH0
+#define BASE_MADDR_L2ULLMAC_CH0 (0xF0880000)
+#undef BASE_ADDR_L2ULLMAC_CH0
+#define BASE_ADDR_L2ULLMAC_CH0 DEV_REG_BASE(BASE_MADDR_L2ULLMAC_CH0)
+
+#undef BASE_MADDR_L2ULLMAC_CH1
+#define BASE_MADDR_L2ULLMAC_CH1 (0xF0888000)
+#undef BASE_ADDR_L2ULLMAC_CH1
+#define BASE_ADDR_L2ULLMAC_CH1 DEV_REG_BASE(BASE_MADDR_L2ULLMAC_CH1)
+
+#undef BASE_MADDR_L2DLLMAC
+#define BASE_MADDR_L2DLLMAC (0xF0890000)
+#undef BASE_ADDR_L2DLLMAC
+#define BASE_ADDR_L2DLLMAC DEV_REG_BASE(BASE_MADDR_L2DLLMAC)
+
+#undef BASE_MADDR_L2CALMAC
+#define BASE_MADDR_L2CALMAC (0xF0898000)
+#undef BASE_ADDR_L2CALMAC
+#define BASE_ADDR_L2CALMAC DEV_REG_BASE(BASE_MADDR_L2CALMAC)
+
+#undef BASE_MADDR_L2ULFIFOMNG
+#define BASE_MADDR_L2ULFIFOMNG (0xF08A0000)
+#undef BASE_ADDR_L2ULFIFOMNG
+#define BASE_ADDR_L2ULFIFOMNG DEV_REG_BASE(BASE_MADDR_L2ULFIFOMNG)
+
+#undef BASE_MADDR_L2DLFIFOMNG
+#define BASE_MADDR_L2DLFIFOMNG (0xF08A4000)
+#undef BASE_ADDR_L2DLFIFOMNG
+#define BASE_ADDR_L2DLFIFOMNG DEV_REG_BASE(BASE_MADDR_L2DLFIFOMNG)
+
+#undef BASE_MADDR_L2SOFIFOMNG
+#define BASE_MADDR_L2SOFIFOMNG (0xF08A8000)
+#undef BASE_ADDR_L2SOFIFOMNG
+#define BASE_ADDR_L2SOFIFOMNG DEV_REG_BASE(BASE_MADDR_L2SOFIFOMNG)
+
+#undef BASE_MADDR_L2SEC
+#define BASE_MADDR_L2SEC (0xF08B0000)
+#undef BASE_ADDR_L2SEC
+#define BASE_ADDR_L2SEC DEV_REG_BASE(BASE_MADDR_L2SEC)
+
+#undef BASE_MADDR_L2ULSECCTL
+#define BASE_MADDR_L2ULSECCTL (0xF08B4000)
+#undef BASE_ADDR_L2ULSECCTL
+#define BASE_ADDR_L2ULSECCTL DEV_REG_BASE(BASE_MADDR_L2ULSECCTL)
+
+#undef BASE_MADDR_L2DLSECCTL
+#define BASE_MADDR_L2DLSECCTL (0xF08B8000)
+#undef BASE_ADDR_L2DLSECCTL
+#define BASE_ADDR_L2DLSECCTL DEV_REG_BASE(BASE_MADDR_L2DLSECCTL)
+
+#undef BASE_MADDR_L2SOSECCTL
+#define BASE_MADDR_L2SOSECCTL (0xF08BC000)
+#undef BASE_ADDR_L2SOSECCTL
+#define BASE_ADDR_L2SOSECCTL DEV_REG_BASE(BASE_MADDR_L2SOSECCTL)
+
+#undef BASE_MADDR_L2MISC
+#define BASE_MADDR_L2MISC (0xF08C0000)
+#undef BASE_ADDR_L2MISC
+#define BASE_ADDR_L2MISC DEV_REG_BASE(BASE_MADDR_L2MISC)
+
+#undef BASE_MADDR_L2DBGMON
+#define BASE_MADDR_L2DBGMON (0xF08D0000)
+#undef BASE_ADDR_L2DBGMON
+#define BASE_ADDR_L2DBGMON DEV_REG_BASE(BASE_MADDR_L2DBGMON)
+
+#undef BASE_MADDR_L2ULBUFMNG
+#define BASE_MADDR_L2ULBUFMNG (0xF08E0000)
+#undef BASE_ADDR_L2ULBUFMNG
+#define BASE_ADDR_L2ULBUFMNG DEV_REG_BASE(BASE_MADDR_L2ULBUFMNG)
+
+#undef BASE_MADDR_L2DLBUFMNG
+#define BASE_MADDR_L2DLBUFMNG (0xF08F0000)
+#undef BASE_ADDR_L2DLBUFMNG
+#define BASE_ADDR_L2DLBUFMNG DEV_REG_BASE(BASE_MADDR_L2DLBUFMNG)
+
+
+#define BASE_ADDR_SIMCTRL (0xFFFF1000)
+#define BASE_ADDR_HSL (0xFFFF2000)
+
+
+#endif /* end of __MASE_REG_BASE_H__ */
diff --git a/mcu/interface/driver/regbase/md93/cpu_info_MT6763.h b/mcu/interface/driver/regbase/md93/cpu_info_MT6763.h
new file mode 100644
index 0000000..f861ae6
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/cpu_info_MT6763.h
@@ -0,0 +1,12 @@
+#ifndef __CPU_INFO_MT6763_H__
+#define __CPU_INFO_MT6763_H__
+
+#define SYS_MCU_NUM_CORE (2)
+#define SYS_MCU_NUM_VPE (4)
+#define SYS_MCU_NUM_TC (8)
+
+#define SYS_MCU_GIC_EXIST (0)
+
+#define SYS_MCU_TYPE_MR2
+
+#endif /* __CPU_INFO_MT6763_H__ */
diff --git a/mcu/interface/driver/regbase/md93/cpu_info_md93.h b/mcu/interface/driver/regbase/md93/cpu_info_md93.h
new file mode 100644
index 0000000..7182611
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/cpu_info_md93.h
@@ -0,0 +1,10 @@
+#ifndef __CPU_INFO_MD93_H__
+#define __CPU_INFO_MD93_H__
+
+#if defined(MT6763) || defined(MT6739) || defined(MT6771)
+# include "cpu_info_MT6763.h"
+#else
+# warning "unknown MDMCU version"
+#endif
+
+#endif /* __CPU_INFO_MD93_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6739.h b/mcu/interface/driver/regbase/md93/reg_base_MT6739.h
new file mode 100644
index 0000000..9c0dabf
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6739.h
@@ -0,0 +1,1385 @@
+#ifndef __REG_BASE_MT6739_H__
+#define __REG_BASE_MT6739_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+#endif /* end of __REG_BASE_MT6739_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6739_FPGA.h b/mcu/interface/driver/regbase/md93/reg_base_MT6739_FPGA.h
new file mode 100644
index 0000000..0765d9b
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6739_FPGA.h
@@ -0,0 +1,1685 @@
+#ifndef __REG_BASE_MT6739_FPGA_H__
+#define __REG_BASE_MT6739_FPGA_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+//AP register
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+
+
+#endif /* end of __REG_BASE_MT6739_FPGA_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6739_username.h b/mcu/interface/driver/regbase/md93/reg_base_MT6739_username.h
new file mode 100644
index 0000000..8615f5d
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6739_username.h
@@ -0,0 +1,275 @@
+#ifndef __REG_BASE_MT6739_USERNAME_H__
+#define __REG_BASE_MT6739_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MCD/WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_NADDR_PCCIF0_AP (0xD0209000)
+#define BASE_NADDR_PCCIF0_MD (0xD020A000)
+#define BASE_NADDR_PCCIF1_AP (0xD020B000)
+#define BASE_NADDR_PCCIF1_MD (0xD020C000)
+#define BASE_ADDR_PCCIF0_AP (0xD0209000)
+#define BASE_ADDR_PCCIF0_MD (0xD020A000)
+#define BASE_ADDR_PCCIF1_AP (0xD020B000)
+#define BASE_ADDR_PCCIF1_MD (0xD020C000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+// MTK/WSD/OSS8/ME9 Thomas Chen
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_NADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_WCN_AHB_SLAVE (0xD8000000)
+
+// MTK/WSP/SE7/SD10 Guo-Huei Chang
+#define BASE_MADDR_AP_SYSTIMER (0xC0017000)
+#define BASE_NADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_ADDR_AP_SYSTIMER (0xD0017000)
+
+// MTK/WSP/SE7/SD10 Ying Hsu
+#define BASE_MADDR_DVFSRC (0xC0012000)
+#define BASE_MADDR_SPM_VMODEM (0xC000F000)
+#define BASE_NADDR_DVFSRC (0xD0012000)
+#define BASE_NADDR_SPM_VMODEM (0xD000F000)
+#define BASE_ADDR_DVFSRC (0xD0012000)
+#define BASE_ADDR_SPM_VMODEM (0xD000F000)
+
+// MTK/WSP/SE7/SD10 Jim Chou
+#define BASE_MADDR_SPM_PCM (0xC0006000)
+#define BASE_NADDR_SPM_PCM (0xD0006000)
+#define BASE_ADDR_SPM_PCM (0xD0006000)
+
+// MTK/WSP/SE7/SD10 Chao-Kai Yu
+#define BASE_MADDR_INFRASYS_CONFIG_REGS (0xC0001000)
+#define BASE_MADDR_APMIXEDSYS (0xC000C000)
+#define BASE_MADDR_AUXADC (0xC1001000)
+#define BASE_MADDR_AP_PTP (0xC100B000)
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define BASE_NADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_NADDR_APMIXEDSYS (0xD000C000)
+#define BASE_NADDR_AUXADC (0xD1001000)
+#define BASE_NADDR_AP_PTP (0xD100B000)
+#define BASE_NADDR_AES_TOP0 (0xD0016000)
+#define BASE_ADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_ADDR_APMIXEDSYS (0xD000C000)
+#define BASE_ADDR_AUXADC (0xD1001000)
+#define BASE_ADDR_AP_PTP (0xD100B000)
+#define BASE_ADDR_AES_TOP0 (0xD0016000)
+
+// MTK/WSP/SE7/SD8 CW Wang
+#define BASE_AP_CLDMA_TOP_MD (0XC021C800)
+
+// MSHC/WCT/SE1/SE9 Shelley Liu
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// SE7/SD3 RaymondWT
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C00000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WCS/SSE/SS3 Ruta Lin
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+// MD Log DMA
+#define BASE_MADDR_MDLOGDMA (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_MDLOGDMA (BASE_ADDR_MDGDMA)
+// MD L1_GDMA
+#define BASE_MADDR_L1GDMA_1 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_1 (BASE_ADDR_MDGDMA)
+#define BASE_MADDR_L1GDMA_2 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_2 (BASE_ADDR_MDGDMA)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6739_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6761.h b/mcu/interface/driver/regbase/md93/reg_base_MT6761.h
new file mode 100644
index 0000000..617d9b0
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6761.h
@@ -0,0 +1,1388 @@
+#ifndef __REG_BASE_MT6761_H__
+#define __REG_BASE_MT6761_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+#endif /* end of __REG_BASE_MT6761_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6761_FPGA.h b/mcu/interface/driver/regbase/md93/reg_base_MT6761_FPGA.h
new file mode 100644
index 0000000..e847497
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6761_FPGA.h
@@ -0,0 +1,1685 @@
+#ifndef __REG_BASE_MT6761_FPGA_H__
+#define __REG_BASE_MT6761_FPGA_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+//AP register
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+
+
+#endif /* end of __REG_BASE_MT6761_FPGA_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6761_username.h b/mcu/interface/driver/regbase/md93/reg_base_MT6761_username.h
new file mode 100644
index 0000000..4ded3e3
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6761_username.h
@@ -0,0 +1,266 @@
+#ifndef __REG_BASE_MT6761_USERNAME_H__
+#define __REG_BASE_MT6761_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MCD/WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_NADDR_PCCIF0_AP (0xD0209000)
+#define BASE_NADDR_PCCIF0_MD (0xD020A000)
+#define BASE_NADDR_PCCIF1_AP (0xD020B000)
+#define BASE_NADDR_PCCIF1_MD (0xD020C000)
+#define BASE_ADDR_PCCIF0_AP (0xD0209000)
+#define BASE_ADDR_PCCIF0_MD (0xD020A000)
+#define BASE_ADDR_PCCIF1_AP (0xD020B000)
+#define BASE_ADDR_PCCIF1_MD (0xD020C000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+// MTK/WSD/OSS8/ME9 Thomas Chen
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_NADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_WCN_AHB_SLAVE (0xD8000000)
+
+// MTK/WSP/SE7/SD10 Guo-Huei Chang
+#define BASE_MADDR_AP_SYSTIMER (0xC0017000)
+#define BASE_NADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_ADDR_AP_SYSTIMER (0xD0017000)
+
+// MTK/WSP/SE7/SD10 Ying Hsu
+#define BASE_MADDR_DVFSRC (0xC0012000)
+#define BASE_MADDR_SPM_VMODEM (0xC000F000)
+#define BASE_NADDR_DVFSRC (0xD0012000)
+#define BASE_NADDR_SPM_VMODEM (0xD000F000)
+#define BASE_ADDR_DVFSRC (0xD0012000)
+#define BASE_ADDR_SPM_VMODEM (0xD000F000)
+
+// MTK/WSP/SE7/SD10 Jim Chou
+#define BASE_MADDR_SPM_PCM (0xC0006000)
+#define BASE_NADDR_SPM_PCM (0xD0006000)
+#define BASE_ADDR_SPM_PCM (0xD0006000)
+
+// MTK/WSP/SE7/SD10 Holmes Lin
+#define BASE_MADDR_INFRASYS_CONFIG_REGS (0xC0001000)
+#define BASE_MADDR_APMIXEDSYS (0xC000C000)
+#define BASE_MADDR_AUXADC (0xC1001000)
+#define BASE_MADDR_AP_PTP (0xC100B000)
+#define BASE_NADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_NADDR_APMIXEDSYS (0xD000C000)
+#define BASE_NADDR_AUXADC (0xD1001000)
+#define BASE_NADDR_AP_PTP (0xD100B000)
+#define BASE_ADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_ADDR_APMIXEDSYS (0xD000C000)
+#define BASE_ADDR_AUXADC (0xD1001000)
+#define BASE_ADDR_AP_PTP (0xD100B000)
+
+// MTK/WSP/SE7/SD8 CW Wang
+#define BASE_AP_CLDMA_TOP_MD (0XC021C800)
+
+// MSHC/WCT/SE1/SE9 Shelley Liu
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C50000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WCS/SSE/SS3 Ruta Lin
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6761_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6763.h b/mcu/interface/driver/regbase/md93/reg_base_MT6763.h
new file mode 100644
index 0000000..63a9ed3
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6763.h
@@ -0,0 +1,1384 @@
+#ifndef __REG_BASE_MT6763_H__
+#define __REG_BASE_MT6763_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+#endif /* end of __REG_BASE_MT6763_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6763_FPGA.h b/mcu/interface/driver/regbase/md93/reg_base_MT6763_FPGA.h
new file mode 100644
index 0000000..8fef46e
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6763_FPGA.h
@@ -0,0 +1,1684 @@
+#ifndef __REG_BASE_MT6763_FPGA_H__
+#define __REG_BASE_MT6763_FPGA_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+//AP register
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+
+
+#endif /* end of __REG_BASE_MT6763_FPGA_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6763_username.h b/mcu/interface/driver/regbase/md93/reg_base_MT6763_username.h
new file mode 100644
index 0000000..8459e60
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6763_username.h
@@ -0,0 +1,273 @@
+#ifndef __REG_BASE_MT6763_USERNAME_H__
+#define __REG_BASE_MT6763_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1F40000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1F40000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1F40000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MCD/WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_NADDR_PCCIF0_AP (0xD0209000)
+#define BASE_NADDR_PCCIF0_MD (0xD020A000)
+#define BASE_NADDR_PCCIF1_AP (0xD020B000)
+#define BASE_NADDR_PCCIF1_MD (0xD020C000)
+#define BASE_ADDR_PCCIF0_AP (0xD0209000)
+#define BASE_ADDR_PCCIF0_MD (0xD020A000)
+#define BASE_ADDR_PCCIF1_AP (0xD020B000)
+#define BASE_ADDR_PCCIF1_MD (0xD020C000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_NADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_WCN_AHB_SLAVE (0xD8000000)
+
+// MTK/WSP/SE7/SD10 Guo-Huei Chang
+#define BASE_MADDR_AP_SYSTIMER (0xC0017000)
+#define BASE_NADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_ADDR_AP_SYSTIMER (0xD0017000)
+
+// MTK/WSP/SE7/SD10 Ying Hsu
+#define BASE_MADDR_DVFSRC (0xC0012000)
+#define BASE_MADDR_SPM_VMODEM (0xC000F000)
+#define BASE_NADDR_DVFSRC (0xD0012000)
+#define BASE_NADDR_SPM_VMODEM (0xD000F000)
+#define BASE_ADDR_DVFSRC (0xD0012000)
+#define BASE_ADDR_SPM_VMODEM (0xD000F000)
+
+// MTK/WSP/SE7/SD10 Jim Chou
+#define BASE_MADDR_SPM_PCM (0xC0006000)
+#define BASE_NADDR_SPM_PCM (0xD0006000)
+#define BASE_ADDR_SPM_PCM (0xD0006000)
+
+// MTK/WSP/SE7/SD10 Chao-Kai Yu
+#define BASE_MADDR_INFRASYS_CONFIG_REGS (0xC0001000)
+#define BASE_MADDR_APMIXEDSYS (0xC000C000)
+#define BASE_MADDR_AUXADC (0xC1001000)
+#define BASE_MADDR_AP_PTP (0xC100B000)
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define BASE_NADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_NADDR_APMIXEDSYS (0xD000C000)
+#define BASE_NADDR_AUXADC (0xD1001000)
+#define BASE_NADDR_AP_PTP (0xD100B000)
+#define BASE_NADDR_AES_TOP0 (0xD0016000)
+#define BASE_ADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_ADDR_APMIXEDSYS (0xD000C000)
+#define BASE_ADDR_AUXADC (0xD1001000)
+#define BASE_ADDR_AP_PTP (0xD100B000)
+#define BASE_ADDR_AES_TOP0 (0xD0016000)
+
+// MTK/WSP/SE7/SD8 CW Wang
+#define BASE_AP_CLDMA_TOP_MD (0XC021C800)
+
+// MSHC/WCT/SE1/SE9 Shelley Liu
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// AP side base address
+// SE7/SD3 RaymondWT
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1F10000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WCS/SSE/SS3 Ruta Lin
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+// MD Log DMA
+#define BASE_MADDR_MDLOGDMA (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_MDLOGDMA (BASE_ADDR_MDGDMA)
+// MD L1_GDMA
+#define BASE_MADDR_L1GDMA_1 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_1 (BASE_ADDR_MDGDMA)
+#define BASE_MADDR_L1GDMA_2 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_2 (BASE_ADDR_MDGDMA)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6739_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6765.h b/mcu/interface/driver/regbase/md93/reg_base_MT6765.h
new file mode 100644
index 0000000..6a7dc6e
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6765.h
@@ -0,0 +1,1388 @@
+#ifndef __REG_BASE_MT6765_H__
+#define __REG_BASE_MT6765_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+#endif /* end of __REG_BASE_MT6765_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6765_FPGA.h b/mcu/interface/driver/regbase/md93/reg_base_MT6765_FPGA.h
new file mode 100644
index 0000000..d19db56
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6765_FPGA.h
@@ -0,0 +1,1685 @@
+#ifndef __REG_BASE_MT6765_FPGA_H__
+#define __REG_BASE_MT6765_FPGA_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+//AP register
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+
+
+#endif /* end of __REG_BASE_MT6765_FPGA_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6765_username.h b/mcu/interface/driver/regbase/md93/reg_base_MT6765_username.h
new file mode 100644
index 0000000..b493945
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6765_username.h
@@ -0,0 +1,266 @@
+#ifndef __REG_BASE_MT6765_USERNAME_H__
+#define __REG_BASE_MT6765_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MCD/WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_NADDR_PCCIF0_AP (0xD0209000)
+#define BASE_NADDR_PCCIF0_MD (0xD020A000)
+#define BASE_NADDR_PCCIF1_AP (0xD020B000)
+#define BASE_NADDR_PCCIF1_MD (0xD020C000)
+#define BASE_ADDR_PCCIF0_AP (0xD0209000)
+#define BASE_ADDR_PCCIF0_MD (0xD020A000)
+#define BASE_ADDR_PCCIF1_AP (0xD020B000)
+#define BASE_ADDR_PCCIF1_MD (0xD020C000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+// MTK/WSD/OSS8/ME9 Thomas Chen
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_NADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_WCN_AHB_SLAVE (0xD8000000)
+
+// MTK/WSP/SE7/SD10 Guo-Huei Chang
+#define BASE_MADDR_AP_SYSTIMER (0xC0017000)
+#define BASE_NADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_ADDR_AP_SYSTIMER (0xD0017000)
+
+// MTK/WSP/SE7/SD10 Ying Hsu
+#define BASE_MADDR_DVFSRC (0xC0012000)
+#define BASE_MADDR_SPM_VMODEM (0xC000F000)
+#define BASE_NADDR_DVFSRC (0xD0012000)
+#define BASE_NADDR_SPM_VMODEM (0xD000F000)
+#define BASE_ADDR_DVFSRC (0xD0012000)
+#define BASE_ADDR_SPM_VMODEM (0xD000F000)
+
+// MTK/WSP/SE7/SD10 Jim Chou
+#define BASE_MADDR_SPM_PCM (0xC0006000)
+#define BASE_NADDR_SPM_PCM (0xD0006000)
+#define BASE_ADDR_SPM_PCM (0xD0006000)
+
+// MTK/WSP/SE7/SD10 Holmes Lin
+#define BASE_MADDR_INFRASYS_CONFIG_REGS (0xC0001000)
+#define BASE_MADDR_APMIXEDSYS (0xC000C000)
+#define BASE_MADDR_AUXADC (0xC1001000)
+#define BASE_MADDR_AP_PTP (0xC100B000)
+#define BASE_NADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_NADDR_APMIXEDSYS (0xD000C000)
+#define BASE_NADDR_AUXADC (0xD1001000)
+#define BASE_NADDR_AP_PTP (0xD100B000)
+#define BASE_ADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_ADDR_APMIXEDSYS (0xD000C000)
+#define BASE_ADDR_AUXADC (0xD1001000)
+#define BASE_ADDR_AP_PTP (0xD100B000)
+
+// MTK/WSP/SE7/SD8 CW Wang
+#define BASE_AP_CLDMA_TOP_MD (0XC021C800)
+
+// MSHC/WCT/SE1/SE9 Shelley Liu
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C50000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WCS/SSE/SS3 Ruta Lin
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6765_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6771.h b/mcu/interface/driver/regbase/md93/reg_base_MT6771.h
new file mode 100644
index 0000000..d3df65b
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6771.h
@@ -0,0 +1,1385 @@
+#ifndef __REG_BASE_MT6771_H__
+#define __REG_BASE_MT6771_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+#endif /* end of __REG_BASE_MT6771_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6771_FPGA.h b/mcu/interface/driver/regbase/md93/reg_base_MT6771_FPGA.h
new file mode 100644
index 0000000..d61514b
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6771_FPGA.h
@@ -0,0 +1,1685 @@
+#ifndef __REG_BASE_MT6771_FPGA_H__
+#define __REG_BASE_MT6771_FPGA_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_ADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+
+//AP register
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+
+
+#endif /* end of __REG_BASE_MT6771_FPGA_H__ */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_MT6771_username.h b/mcu/interface/driver/regbase/md93/reg_base_MT6771_username.h
new file mode 100644
index 0000000..aa957b1
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_MT6771_username.h
@@ -0,0 +1,266 @@
+#ifndef __REG_BASE_MT6771_USERNAME_H__
+#define __REG_BASE_MT6771_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MCD/WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_NADDR_PCCIF0_AP (0xD0209000)
+#define BASE_NADDR_PCCIF0_MD (0xD020A000)
+#define BASE_NADDR_PCCIF1_AP (0xD020B000)
+#define BASE_NADDR_PCCIF1_MD (0xD020C000)
+#define BASE_ADDR_PCCIF0_AP (0xD0209000)
+#define BASE_ADDR_PCCIF0_MD (0xD020A000)
+#define BASE_ADDR_PCCIF1_AP (0xD020B000)
+#define BASE_ADDR_PCCIF1_MD (0xD020C000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+// MTK/WSD/OSS8/ME9 Thomas Chen
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_NADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_WCN_AHB_SLAVE (0xD8000000)
+
+// MTK/WSP/SE7/SD10 Guo-Huei Chang
+#define BASE_MADDR_AP_SYSTIMER (0xC0017000)
+#define BASE_NADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_ADDR_AP_SYSTIMER (0xD0017000)
+
+// MTK/WSP/SE7/SD10 Ying Hsu
+#define BASE_MADDR_DVFSRC (0xC0012000)
+#define BASE_MADDR_SPM_VMODEM (0xC000F000)
+#define BASE_NADDR_DVFSRC (0xD0012000)
+#define BASE_NADDR_SPM_VMODEM (0xD000F000)
+#define BASE_ADDR_DVFSRC (0xD0012000)
+#define BASE_ADDR_SPM_VMODEM (0xD000F000)
+
+// MTK/WSP/SE7/SD10 Jim Chou
+#define BASE_MADDR_SPM_PCM (0xC0006000)
+#define BASE_NADDR_SPM_PCM (0xD0006000)
+#define BASE_ADDR_SPM_PCM (0xD0006000)
+
+// MTK/WSP/SE7/SD10 Holmes Lin
+#define BASE_MADDR_INFRASYS_CONFIG_REGS (0xC0001000)
+#define BASE_MADDR_APMIXEDSYS (0xC000C000)
+#define BASE_MADDR_AUXADC (0xC1001000)
+#define BASE_MADDR_AP_PTP (0xC100B000)
+#define BASE_NADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_NADDR_APMIXEDSYS (0xD000C000)
+#define BASE_NADDR_AUXADC (0xD1001000)
+#define BASE_NADDR_AP_PTP (0xD100B000)
+#define BASE_ADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_ADDR_APMIXEDSYS (0xD000C000)
+#define BASE_ADDR_AUXADC (0xD1001000)
+#define BASE_ADDR_AP_PTP (0xD100B000)
+
+// MTK/WSP/SE7/SD8 CW Wang
+#define BASE_AP_CLDMA_TOP_MD (0XC021C800)
+
+// MSHC/WCT/SE1/SE9 Shelley Liu
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// SE7/SD3 RaymondWT
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1F10000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WCS/SSE/SS3 Ruta Lin
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6771_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md93/reg_base_md93.h b/mcu/interface/driver/regbase/md93/reg_base_md93.h
new file mode 100644
index 0000000..1476bb0
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_md93.h
@@ -0,0 +1,116 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * reg_base_md93.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for chipset register base and global configuration registers
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _REG_BASE_MD93_H
+#define _REG_BASE_MD93_H
+
+#if defined(MT6763)
+ #ifdef __FPGA__
+ #include "reg_base_MT6763_FPGA.h"
+ #else
+ #include "reg_base_MT6763.h"
+ #endif /*__FPGA__*/
+#elif defined(MT6739)
+ #ifdef __FPGA__
+ #include "reg_base_MT6739_FPGA.h"
+ #else
+ #include "reg_base_MT6739.h"
+ #endif /*__FPGA__*/
+#elif defined(MT6771)
+ #ifdef __FPGA__
+ #include "reg_base_MT6771_FPGA.h"
+ #else
+ #include "reg_base_MT6771.h"
+ #endif /*__FPGA__*/
+#elif defined(MT6765)
+ #ifdef __FPGA__
+ #include "reg_base_MT6765_FPGA.h"
+ #else
+ #include "reg_base_MT6765.h"
+ #endif /*__FPGA__*/
+#elif defined(MT6761)
+ #ifdef __FPGA__
+ #include "reg_base_MT6761_FPGA.h"
+ #else
+ #include "reg_base_MT6761.h"
+ #endif /*__FPGA__*/
+#else
+ # warning "unknown MDMCU version"
+#endif
+
+#endif /* !_REG_BASE_MD93_H */
+
diff --git a/mcu/interface/driver/regbase/md93/reg_base_username_md93.h b/mcu/interface/driver/regbase/md93/reg_base_username_md93.h
new file mode 100644
index 0000000..51d24bf
--- /dev/null
+++ b/mcu/interface/driver/regbase/md93/reg_base_username_md93.h
@@ -0,0 +1,21 @@
+#ifndef __REG_BASE_USERNAME_MD93_H__
+#define __REG_BASE_USERNAME_MD93_H__
+
+/* This header file only includes product specific header files.
+ * Please add your reg base difinitions to correct product specific file. */
+
+#if defined(MT6763)
+ #include "reg_base_MT6763_username.h"
+#elif defined(MT6739)
+ #include "reg_base_MT6739_username.h"
+#elif defined(MT6771)
+ #include "reg_base_MT6771_username.h"
+#elif defined(MT6765)
+ #include "reg_base_MT6765_username.h"
+#elif defined(MT6761)
+ #include "reg_base_MT6761_username.h"
+#else
+ # warning "unknown MDMCU version"
+#endif
+
+#endif /* end of __REG_BASE_USERNAME_MD93_H__ */
diff --git a/mcu/interface/driver/regbase/md95/cpu_info_MT6295M.h b/mcu/interface/driver/regbase/md95/cpu_info_MT6295M.h
new file mode 100644
index 0000000..e00464f
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/cpu_info_MT6295M.h
@@ -0,0 +1,16 @@
+#ifndef __CPU_INFO_MT6295M_H__
+#define __CPU_INFO_MT6295M_H__
+
+#if defined(__MD95_IS_2CORES__)
+#define SYS_MCU_NUM_CORE (2)
+#define SYS_MCU_NUM_VPE (4)
+#define SYS_MCU_NUM_TC (8)
+#else
+#define SYS_MCU_NUM_CORE (3)
+#define SYS_MCU_NUM_VPE (6)
+#define SYS_MCU_NUM_TC (12)
+#endif
+
+#define SYS_MCU_GIC_EXIST (0)
+
+#endif /* __CPU_INFO_MT6295M_H__ */
diff --git a/mcu/interface/driver/regbase/md95/cpu_info_md95.h b/mcu/interface/driver/regbase/md95/cpu_info_md95.h
new file mode 100644
index 0000000..2203031
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/cpu_info_md95.h
@@ -0,0 +1,10 @@
+#ifndef __CPU_INFO_MD95_H__
+#define __CPU_INFO_MD95_H__
+
+#if defined(MT6295M) || defined(MT3967) || defined(MT6779) || defined(MT6785)
+# include "cpu_info_MT6295M.h"
+#else
+# error "unknown MDMCU version"
+#endif
+
+#endif /* __CPU_INFO_MD95_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT3967.h b/mcu/interface/driver/regbase/md95/reg_base_MT3967.h
new file mode 100644
index 0000000..c2caabe
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT3967.h
@@ -0,0 +1,1511 @@
+#ifndef __REG_BASE_MT3967_H__
+#define __REG_BASE_MT3967_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6295_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6295
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): (V) RXDFESYS
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_1 (0xA7030000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_2 (0xA7040000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_3 (0xA7050000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_4 (0xA7060000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_5 (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MRSG_1 (0xA7120000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDPERI_CORE2_MEM_CONFIG (0xA01DA000)
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MML2_CFG_SRAM (0xA060D000)
+#define BASE_MADDR_MML2_RDMA_SRAM_L (0xA060E000)
+#define BASE_MADDR_MML2_RDMA_SRAM_H (0xA060F000)
+#define BASE_MADDR_MML2_DLCH_QP_APB (0xA0610000)
+#define BASE_MADDR_MML2_DLCH_RDMA (0xA0611000)
+#define BASE_MADDR_MML2_DLCH_CIPHER (0xA0612000)
+#define BASE_MADDR_MML2_IPF_UL (0xA0614000)
+#define BASE_MADDR_MML2_IPF_DL (0xA0615000)
+#define BASE_MADDR_MML2_IPF_HPCNAT (0xA0616000)
+#define BASE_MADDR_MML2_IPF_PN (0xA0617000)
+#define BASE_MADDR_MML2_ROHC (0xA0618000)
+#define BASE_MADDR_MML2_IPF_SRAM (0xA061D000)
+#define BASE_MADDR_MML2_WDMA_SRAM_L (0xA061E000)
+#define BASE_MADDR_MML2_WDMA_SRAM_H (0xA061F000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A10000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED2 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED3 (0xA0A50000)
+// (5): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1300000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA1400000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (6): mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+// (7): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_VU_SM_0 (0xA6121000)
+#define BASE_MADDR_MODEML1_AO_VU_SM_1 (0xA6122000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA6200000)
+#define BASE_MADDR_MODEML1_AO_C1X_EVENTGEN (0xA6210000)
+#define BASE_MADDR_MODEML1_AO_CDO_EVENTGEN (0xA6220000)
+#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+#define BASE_MADDR_MODEML1_AO_LTE_EVENTGEN (0xA6240000)
+#define BASE_MADDR_MODEML1_AO_TDD_EVENTGEN (0xA6250000)
+#define BASE_MADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xA6260000)
+#define BASE_MADDR_MODEML1_AO_MD_BUCK_CTRL (0xA6270000)
+// (8): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_RESERVED0 (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_RESERVED1 (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_RESERVED2 (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MBIST_CR (0xABB30000)
+// (9): TXSYS
+#define BASE_MADDR_TXSYS_TXBSRP (0xA8000000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_MEM_PM (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_BUS_INTF (0xA8220800)
+#define BASE_MADDR_TXSYS_TPC_EXTIF (0xA8221000)
+#define BASE_MADDR_TXSYS_TPC_TRG (0xA8221800)
+#define BASE_MADDR_TXSYS_TPC_GCCORE (0xA8224000)
+#define BASE_MADDR_TXSYS_TPC_DMA (0xA8225000)
+#define BASE_MADDR_TXSYS_TPC_MEM_TQ (0xA8226000)
+#define BASE_MADDR_TXSYS_TPC_MEM_DM (0xA8228000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_2 (0xA8380000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXET_1 (0xA8420000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_AMSC (0xA84A0000)
+#define BASE_MADDR_TXSYS_AMSC_1 (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_2 (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA8500000)
+// (10): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7880000)
+// (11): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+// (12): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xAC354000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (13): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_1 (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_PERI (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTE_CE (0xAD321000)
+#define BASE_MADDR_BRP_LTE_CE_TOP_1 (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DEMOD_TOP_REG (0xAD333000)
+#define BASE_MADDR_BRP_DEMOD (0xAD334000)
+#define BASE_MADDR_BRP_DEMOD_TOP_1 (0xAD335000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (15): Eiger APMD Remap
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_1 (0xB7030000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_2 (0xB7040000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_3 (0xB7050000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_4 (0xB7060000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_5 (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MRSG_1 (0xB7120000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDPERI_CORE2_MEM_CONFIG (0xB01DA000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MML2_CFG_SRAM (0xB060D000)
+#define BASE_NADDR_MML2_RDMA_SRAM_L (0xB060E000)
+#define BASE_NADDR_MML2_RDMA_SRAM_H (0xB060F000)
+#define BASE_NADDR_MML2_DLCH_QP_APB (0xB0610000)
+#define BASE_NADDR_MML2_DLCH_RDMA (0xB0611000)
+#define BASE_NADDR_MML2_DLCH_CIPHER (0xB0612000)
+#define BASE_NADDR_MML2_IPF_UL (0xB0614000)
+#define BASE_NADDR_MML2_IPF_DL (0xB0615000)
+#define BASE_NADDR_MML2_IPF_HPCNAT (0xB0616000)
+#define BASE_NADDR_MML2_IPF_PN (0xB0617000)
+#define BASE_NADDR_MML2_ROHC (0xB0618000)
+#define BASE_NADDR_MML2_IPF_SRAM (0xB061D000)
+#define BASE_NADDR_MML2_WDMA_SRAM_L (0xB061E000)
+#define BASE_NADDR_MML2_WDMA_SRAM_H (0xB061F000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A10000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED2 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED3 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1300000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB1400000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_VU_SM_0 (0xB6121000)
+#define BASE_NADDR_MODEML1_AO_VU_SM_1 (0xB6122000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB6200000)
+#define BASE_NADDR_MODEML1_AO_C1X_EVENTGEN (0xB6210000)
+#define BASE_NADDR_MODEML1_AO_CDO_EVENTGEN (0xB6220000)
+#define BASE_NADDR_MODEML1_AO_FDD_EVENTGEN (0xB6230000)
+#define BASE_NADDR_MODEML1_AO_LTE_EVENTGEN (0xB6240000)
+#define BASE_NADDR_MODEML1_AO_TDD_EVENTGEN (0xB6250000)
+#define BASE_NADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xB6260000)
+#define BASE_NADDR_MODEML1_AO_MD_BUCK_CTRL (0xB6270000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_RESERVED0 (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_RESERVED1 (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_RESERVED2 (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MBIST_CR (0xBBB30000)
+#define BASE_NADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_MEM_PM (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_BUS_INTF (0xB8220800)
+#define BASE_NADDR_TXSYS_TPC_EXTIF (0xB8221000)
+#define BASE_NADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_NADDR_TXSYS_TPC_GCCORE (0xB8224000)
+#define BASE_NADDR_TXSYS_TPC_DMA (0xB8225000)
+#define BASE_NADDR_TXSYS_TPC_MEM_TQ (0xB8226000)
+#define BASE_NADDR_TXSYS_TPC_MEM_DM (0xB8228000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_2 (0xB8380000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXET_1 (0xB8420000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_AMSC (0xB84A0000)
+#define BASE_NADDR_TXSYS_AMSC_1 (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_2 (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB8500000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBC354000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_1 (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_PERI (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTE_CE (0xBD321000)
+#define BASE_NADDR_BRP_LTE_CE_TOP_1 (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DEMOD_TOP_REG (0xBD333000)
+#define BASE_NADDR_BRP_DEMOD (0xBD334000)
+#define BASE_NADDR_BRP_DEMOD_TOP_1 (0xBD335000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_1 (0xB7030000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_2 (0xB7040000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_3 (0xB7050000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_4 (0xB7060000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_5 (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MRSG_1 (0xB7120000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDPERI_CORE2_MEM_CONFIG (0xB01DA000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MML2_CFG_SRAM (0xB060D000)
+#define BASE_ADDR_MML2_RDMA_SRAM_L (0xB060E000)
+#define BASE_ADDR_MML2_RDMA_SRAM_H (0xB060F000)
+#define BASE_ADDR_MML2_DLCH_QP_APB (0xB0610000)
+#define BASE_ADDR_MML2_DLCH_RDMA (0xB0611000)
+#define BASE_ADDR_MML2_DLCH_CIPHER (0xB0612000)
+#define BASE_ADDR_MML2_IPF_UL (0xB0614000)
+#define BASE_ADDR_MML2_IPF_DL (0xB0615000)
+#define BASE_ADDR_MML2_IPF_HPCNAT (0xB0616000)
+#define BASE_ADDR_MML2_IPF_PN (0xB0617000)
+#define BASE_ADDR_MML2_ROHC (0xB0618000)
+#define BASE_ADDR_MML2_IPF_SRAM (0xB061D000)
+#define BASE_ADDR_MML2_WDMA_SRAM_L (0xB061E000)
+#define BASE_ADDR_MML2_WDMA_SRAM_H (0xB061F000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A10000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED2 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED3 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1300000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB1400000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_VU_SM_0 (0xB6121000)
+#define BASE_ADDR_MODEML1_AO_VU_SM_1 (0xB6122000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB6200000)
+#define BASE_ADDR_MODEML1_AO_C1X_EVENTGEN (0xB6210000)
+#define BASE_ADDR_MODEML1_AO_CDO_EVENTGEN (0xB6220000)
+#define BASE_ADDR_MODEML1_AO_FDD_EVENTGEN (0xB6230000)
+#define BASE_ADDR_MODEML1_AO_LTE_EVENTGEN (0xB6240000)
+#define BASE_ADDR_MODEML1_AO_TDD_EVENTGEN (0xB6250000)
+#define BASE_ADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xB6260000)
+#define BASE_ADDR_MODEML1_AO_MD_BUCK_CTRL (0xB6270000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_RESERVED0 (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_RESERVED1 (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_RESERVED2 (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MBIST_CR (0xBBB30000)
+#define BASE_ADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_MEM_PM (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_BUS_INTF (0xB8220800)
+#define BASE_ADDR_TXSYS_TPC_EXTIF (0xB8221000)
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TPC_GCCORE (0xB8224000)
+#define BASE_ADDR_TXSYS_TPC_DMA (0xB8225000)
+#define BASE_ADDR_TXSYS_TPC_MEM_TQ (0xB8226000)
+#define BASE_ADDR_TXSYS_TPC_MEM_DM (0xB8228000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_2 (0xB8380000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXET_1 (0xB8420000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_AMSC (0xB84A0000)
+#define BASE_ADDR_TXSYS_AMSC_1 (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_2 (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB8500000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBC354000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_1 (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_PERI (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTE_CE (0xBD321000)
+#define BASE_ADDR_BRP_LTE_CE_TOP_1 (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DEMOD_TOP_REG (0xBD333000)
+#define BASE_ADDR_BRP_DEMOD (0xBD334000)
+#define BASE_ADDR_BRP_DEMOD_TOP_1 (0xBD335000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6295_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED2
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED3
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBSRP
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED2
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED3
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBSRP
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED2
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED3
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBSRP
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBSRP
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBSRP
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBSRP
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT3967_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT3967_username.h b/mcu/interface/driver/regbase/md95/reg_base_MT3967_username.h
new file mode 100644
index 0000000..d8e2000
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT3967_username.h
@@ -0,0 +1,164 @@
+#ifndef __REG_BASE_MT3967_USERNAME_H__
+#define __REG_BASE_MT3967_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+/* Please add your register by yourself, EX:
+
+// WCS/SSE/SS2 owner
+#define BASE_XXXX_XXXXXXXX (0xXXXXXXXX)
+
+*/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+//WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+
+// SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+//End of AP registers
+
+// SSE/SS3 I-Chun Liu
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// WSP/RSD/DSD Tony Yuan
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+
+/****************************
+* MD registers *
+*****************************/
+/* Please add your register by yourself, EX:
+
+// WCS/SSE/SS2 owner
+#define BASE_XXXX_XXXXXXXX (0xXXXXXXXX)
+
+*/
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+
+//WCS/SD/SP3 Johnason Lee
+#define AMSC_REG_BASE (0xB3700000)
+#define AMSC_TQ_SRAM_REG_BASE (0xB84A8000)
+
+// WCS/SE2/CS15 Leon Yeh
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC0007000)
+#define BASE_NADDR_APRGU (0xD0007000)
+#define BASE_ADDR_APRGU (0xD0007000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000) //For BT
+
+
+// WSP/SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+//WCS/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/MSP/MSP7 Tzu-Han Hsu
+#define PATCH_base (0xA6FC0000)
+#define SHAREG2_base (BASE_MADDR_MD2GSYS_SHARE_D1) //(L1_BASE_MADDR_SHARE_D1) //the same as L1_BASE_MADDR_SHARE_D1
+#define DPRAM_CPU_base (BASE_MADDR_MD2GSYS_IDMA_DM) //(L1_BASE_MADDR_DM_IDMA) //FIXIT: the same as L1_BASE_MADDR_DM_IDMA
+#define IDMA_base (BASE_MADDR_MD2GSYS_IDMA_CM) //(L1_BASE_MADDR_CM_IDMA) //FIXIT: the same as L1_BASE_MADDR_CM_IDMA
+
+//WCS/MDD/DE3 Vesa Savela
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// WCS/SSE/SS3 Chia-Fu Lee
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+// WCS/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WSP/SE7/SD10 Che-Wei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+// WSP/SE7/SD10 Guo-Huei Chang, for VMODEM & MD_SRAM SW workaround
+#define BASE_INFRA_AO_SLEEP_CONTROLER (0xC0006000)
+
+// WSP/SE7/SD3 Hsin-Hao Huang, for DPMAIF
+#define BASE_AP_DPMAIF_TOP_MD (0xC022C000)
+#define BASE_AP_DPMAIF_PD_BASE (0xC022D000)
+
+//WCS/SE2/BSD Tom-CT Wu temp for EMI bus hang
+#define BASE_RXDFE_MODEM_TEMP (0xA7000000)
+#define BASE_CS_MODEM_TEMP (0xA7830000)
+#define BASE_ML1AO_BUS_MODEM_TEMP (0xA61C0000)
+#define BASE_TXSBRP_MAS_BUS0_MODEM_TEMP (0xA8180000)
+#define BASE_TXSBRP_MAS_BUS1_MODEM_TEMP (0xA8500000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT3967_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT6295M.h b/mcu/interface/driver/regbase/md95/reg_base_MT6295M.h
new file mode 100644
index 0000000..edce5ae
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT6295M.h
@@ -0,0 +1,1465 @@
+#ifndef __REG_BASE_MT6763_H__
+#define __REG_BASE_MT6763_H__
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6293
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F800000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): AP View
+// (4): (V) RXDFESYSY
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_LTE_EVENTGEN (0xA7030000)
+#define BASE_MADDR_RXDFESYS_FDD_EVENTGEN (0xA7040000)
+#define BASE_MADDR_RXDFESYS_TDD_EVENTGEN (0xA7050000)
+#define BASE_MADDR_RXDFESYS_C1X_EVENTGEN (0xA7060000)
+#define BASE_MADDR_RXDFESYS_CDO_EVENTGEN (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MM_EVENTGEN (0xA7120000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+// (5): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDSBC_KEY_CONFIG (0xA01D7000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_BUS (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MDINFRA_FCS (0xA0A10000)
+#define BASE_MADDR_MDINFRA_GCU (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A50000)
+// (6): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1200000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (7): mdcoresys
+//#define BASE_ADDR__MML2 (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+// (8): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+// (9): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAM_DFE_DUMP (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_MBIST_CONFIG (0xAB818000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_SCQ_VDSP_DMA (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_SCQ0_VU_SM (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ0_MD32_TBUF (0xAB950000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_SCQ1_VU_SM (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MD32_TBUF (0xAB950000)
+// (10): TXSYS
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_1 (0xA8220000)
+#define BASE_MADDR_TXSYS_TPC_2 (0xA8240000)
+#define BASE_MADDR_TXSYS_TPC_3 (0xA8260000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TPC_4 (0xA8380000)
+#define BASE_MADDR_TXSYS_TPC_5 (0xA83A0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_C1X_TTR (0xA84A0000)
+#define BASE_MADDR_TXSYS_CDO_TTR (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+// (11): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7880000)
+// (12): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_RESERVED0 (0xA6D00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_RESERVED1 (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_RESERVED2 (0xA6F50000)
+#define BASE_MADDR_MD2GSYS_RESERVED3 (0xA6F60000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_RESERVED4 (0xA6F80000)
+#define BASE_MADDR_MD2GSYS_RESERVED5 (0xA6F90000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_RESERVED6 (0xA6FD0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+#define BASE_MADDR_MD2GSYS_RESERVED7 (0xA6FF0000)
+// (13): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (14): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_BRP_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_RSLT (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_DMC_MEMSLP (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTECE_OC1_REG (0xAD321000)
+#define BASE_MADDR_BRP_LTECE_OC2_REG (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MDMCU (0x1FC00000)
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_IA_PDA_MON (0xA0210000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG (0xA0230000)
+#define BASE_MADDR_MDMCU_MCUMMU (0xA0300000)
+#define BASE_MADDR_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG (0xA0330000)
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xA0340000)
+#define BASE_MADDR_MDMCU_ELM (0xA0350000)
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xA0360000)
+#define BASE_MADDR_MDMCU_MV20E100 (0xA1000000)
+#define BASE_MADDR_MDMCU_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_MDMCU_USIP_INT_DBG (0xA1080000)
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF (0xA1100000)
+#define BASE_MADDR_MDMCU_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG (0xA1180000)
+#define BASE_MADDR_MDMCU_DSPLOG_4PB (0xA1620000)
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG (0xA1650000)
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_NADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_NADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_NADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_NADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_NADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_NADDR_TXSYS_TXBRP_CC0 (0xB8000000)
+#define BASE_NADDR_TXSYS_TXBRP_CC1 (0xB8080000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_NADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_NADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_NADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_NADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_NADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_NADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_NADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_NADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_NADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_NADDR_MDMCU_ELM (0xB0350000)
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_NADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_NADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_NADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_NADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_LTE_EVENTGEN (0xB7030000)
+#define BASE_ADDR_RXDFESYS_FDD_EVENTGEN (0xB7040000)
+#define BASE_ADDR_RXDFESYS_TDD_EVENTGEN (0xB7050000)
+#define BASE_ADDR_RXDFESYS_C1X_EVENTGEN (0xB7060000)
+#define BASE_ADDR_RXDFESYS_CDO_EVENTGEN (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_SRAM (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDSBC_KEY_CONFIG (0xB01D7000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_BUS (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MDINFRA_FCS (0xB0A10000)
+#define BASE_ADDR_MDINFRA_GCU (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1200000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_MBIST_CONFIG (0xBB818000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_SCQ_VDSP_DMA (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_SCQ0_VU_SM (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ0_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_SCQ1_VU_SM (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MD32_TBUF (0xBB950000)
+#define BASE_ADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_1 (0xB8220000)
+#define BASE_ADDR_TXSYS_TPC_2 (0xB8240000)
+#define BASE_ADDR_TXSYS_TPC_3 (0xB8260000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TPC_4 (0xB8380000)
+#define BASE_ADDR_TXSYS_TPC_5 (0xB83A0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_C1X_TTR (0xB84A0000)
+#define BASE_ADDR_TXSYS_CDO_TTR (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_RESERVED0 (0xB6D00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_RESERVED1 (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_RESERVED2 (0xB6F50000)
+#define BASE_ADDR_MD2GSYS_RESERVED3 (0xB6F60000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_RESERVED4 (0xB6F80000)
+#define BASE_ADDR_MD2GSYS_RESERVED5 (0xB6F90000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_RESERVED6 (0xB6FD0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_MD2GSYS_RESERVED7 (0xB6FF0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_BRP_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_RSLT (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_DMC_MEMSLP (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTECE_OC1_REG (0xBD321000)
+#define BASE_ADDR_BRP_LTECE_OC2_REG (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_IA_PDA_MON (0xB0210000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG (0xB0230000)
+#define BASE_ADDR_MDMCU_MCUMMU (0xB0300000)
+#define BASE_ADDR_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG (0xB0330000)
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF (0xB0340000)
+#define BASE_ADDR_MDMCU_ELM (0xB0350000)
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF (0xB0360000)
+#define BASE_ADDR_MDMCU_MV20E100 (0xB1000000)
+#define BASE_ADDR_MDMCU_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_MDMCU_USIP_INT_DBG (0xB1080000)
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF (0xB1100000)
+#define BASE_ADDR_MDMCU_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG (0xB1180000)
+#define BASE_ADDR_MDMCU_DSPLOG_4PB (0xB1620000)
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG (0xB1650000)
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6293_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDMCU_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_BUS
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_FCS
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_GCU
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDM BASE_NADDR_MDINFRA_BUS
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_FCS
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_GCU
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRX_P2P_TX
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBRP_CC0
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+//AP register
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1F40000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_MADDR_EFUSE (0xC1F10000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_MADDR_AP_SYSTIMER (0xC0017000)
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+#define BASE_MADDR_DVFSRC (0xC0012000)
+#define BASE_MADDR_SPM_VMODEM (0xC000F000)
+#define BASE_MADDR_SPM_PCM (0xC0006000)
+#define BASE_MADDR_INFRASYS_CONFIG_REGS (0xC0001000)
+#define BASE_MADDR_APMIXEDSYS (0xC000C000)
+#define BASE_MADDR_AUXADC (0xC1001000)
+#define BASE_MADDR_AP_PTP (0xC100B000)
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+
+#define BASE_AP_CLDMA_TOP_MD (0XC021C800)
+
+
+
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1F40000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_PCCIF0_AP (0xD0209000)
+#define BASE_NADDR_PCCIF0_MD (0xD020A000)
+#define BASE_NADDR_PCCIF1_AP (0xD020B000)
+#define BASE_NADDR_PCCIF1_MD (0xD020C000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_EFUSE (0xD1F10000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_NADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_NADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_NADDR_DVFSRC (0xD0012000)
+#define BASE_NADDR_SPM_VMODEM (0xD000F000)
+#define BASE_NADDR_SPM_PCM (0xD0006000)
+#define BASE_NADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_NADDR_APMIXEDSYS (0xD000C000)
+#define BASE_NADDR_AUXADC (0xD1001000)
+#define BASE_NADDR_AP_PTP (0xD100B000)
+#define BASE_NADDR_AES_TOP0 (0xD0016000)
+
+
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1F40000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_PCCIF0_AP (0xD0209000)
+#define BASE_ADDR_PCCIF0_MD (0xD020A000)
+#define BASE_ADDR_PCCIF1_AP (0xD020B000)
+#define BASE_ADDR_PCCIF1_MD (0xD020C000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_EFUSE (0xD1F10000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AP_SYSTIMER (0xD0017000)
+#define BASE_ADDR_WCN_AHB_SLAVE (0xD8000000)
+#define BASE_ADDR_DVFSRC (0xD0012000)
+#define BASE_ADDR_SPM_VMODEM (0xD000F000)
+#define BASE_ADDR_SPM_PCM (0xD0006000)
+#define BASE_ADDR_INFRASYS_CONFIG_REGS (0xD0001000)
+#define BASE_ADDR_APMIXEDSYS (0xD000C000)
+#define BASE_ADDR_AUXADC (0xD1001000)
+#define BASE_ADDR_AP_PTP (0xD100B000)
+#define BASE_ADDR_AES_TOP0 (0xD0016000)
+
+
+
+#endif /* end of __REG_BASE_MT6763_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT6295M_FPGA.h b/mcu/interface/driver/regbase/md95/reg_base_MT6295M_FPGA.h
new file mode 100644
index 0000000..879e76e
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT6295M_FPGA.h
@@ -0,0 +1,1511 @@
+#ifndef __REG_BASE_MT6295_FPGA_H__
+#define __REG_BASE_MT6295_FPGA_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6295_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6295
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): (V) RXDFESYS
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_1 (0xA7030000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_2 (0xA7040000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_3 (0xA7050000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_4 (0xA7060000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_5 (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MRSG_1 (0xA7120000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDPERI_CORE2_MEM_CONFIG (0xA01DA000)
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MML2_CFG_SRAM (0xA060D000)
+#define BASE_MADDR_MML2_RDMA_SRAM_L (0xA060E000)
+#define BASE_MADDR_MML2_RDMA_SRAM_H (0xA060F000)
+#define BASE_MADDR_MML2_DLCH_QP_APB (0xA0610000)
+#define BASE_MADDR_MML2_DLCH_RDMA (0xA0611000)
+#define BASE_MADDR_MML2_DLCH_CIPHER (0xA0612000)
+#define BASE_MADDR_MML2_IPF_UL (0xA0614000)
+#define BASE_MADDR_MML2_IPF_DL (0xA0615000)
+#define BASE_MADDR_MML2_IPF_HPCNAT (0xA0616000)
+#define BASE_MADDR_MML2_IPF_PN (0xA0617000)
+#define BASE_MADDR_MML2_ROHC (0xA0618000)
+#define BASE_MADDR_MML2_IPF_SRAM (0xA061D000)
+#define BASE_MADDR_MML2_WDMA_SRAM_L (0xA061E000)
+#define BASE_MADDR_MML2_WDMA_SRAM_H (0xA061F000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A10000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED2 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED3 (0xA0A50000)
+// (5): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1300000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA1400000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (6): mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+// (7): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_VU_SM_0 (0xA6121000)
+#define BASE_MADDR_MODEML1_AO_VU_SM_1 (0xA6122000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA6200000)
+#define BASE_MADDR_MODEML1_AO_C1X_EVENTGEN (0xA6210000)
+#define BASE_MADDR_MODEML1_AO_CDO_EVENTGEN (0xA6220000)
+#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+#define BASE_MADDR_MODEML1_AO_LTE_EVENTGEN (0xA6240000)
+#define BASE_MADDR_MODEML1_AO_TDD_EVENTGEN (0xA6250000)
+#define BASE_MADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xA6260000)
+#define BASE_MADDR_MODEML1_AO_MD_BUCK_CTRL (0xA6270000)
+// (8): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_RESERVED0 (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_RESERVED1 (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_RESERVED2 (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MBIST_CR (0xABB30000)
+// (9): TXSYS
+#define BASE_MADDR_TXSYS_TXBSRP (0xA8000000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_MEM_PM (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_BUS_INTF (0xA8220800)
+#define BASE_MADDR_TXSYS_TPC_EXTIF (0xA8221000)
+#define BASE_MADDR_TXSYS_TPC_TRG (0xA8221800)
+#define BASE_MADDR_TXSYS_TPC_GCCORE (0xA8224000)
+#define BASE_MADDR_TXSYS_TPC_DMA (0xA8225000)
+#define BASE_MADDR_TXSYS_TPC_MEM_TQ (0xA8226000)
+#define BASE_MADDR_TXSYS_TPC_MEM_DM (0xA8228000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_2 (0xA8380000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXET_1 (0xA8420000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_AMSC (0xA84A0000)
+#define BASE_MADDR_TXSYS_AMSC_1 (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_2 (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA8500000)
+// (10): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7880000)
+// (11): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+// (12): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xAC354000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (13): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_1 (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_PERI (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTE_CE (0xAD321000)
+#define BASE_MADDR_BRP_LTE_CE_TOP_1 (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DEMOD_TOP_REG (0xAD333000)
+#define BASE_MADDR_BRP_DEMOD (0xAD334000)
+#define BASE_MADDR_BRP_DEMOD_TOP_1 (0xAD335000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (15): Eiger APMD Remap
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_1 (0xB7030000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_2 (0xB7040000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_3 (0xB7050000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_4 (0xB7060000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_5 (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MRSG_1 (0xB7120000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDPERI_CORE2_MEM_CONFIG (0xB01DA000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MML2_CFG_SRAM (0xB060D000)
+#define BASE_NADDR_MML2_RDMA_SRAM_L (0xB060E000)
+#define BASE_NADDR_MML2_RDMA_SRAM_H (0xB060F000)
+#define BASE_NADDR_MML2_DLCH_QP_APB (0xB0610000)
+#define BASE_NADDR_MML2_DLCH_RDMA (0xB0611000)
+#define BASE_NADDR_MML2_DLCH_CIPHER (0xB0612000)
+#define BASE_NADDR_MML2_IPF_UL (0xB0614000)
+#define BASE_NADDR_MML2_IPF_DL (0xB0615000)
+#define BASE_NADDR_MML2_IPF_HPCNAT (0xB0616000)
+#define BASE_NADDR_MML2_IPF_PN (0xB0617000)
+#define BASE_NADDR_MML2_ROHC (0xB0618000)
+#define BASE_NADDR_MML2_IPF_SRAM (0xB061D000)
+#define BASE_NADDR_MML2_WDMA_SRAM_L (0xB061E000)
+#define BASE_NADDR_MML2_WDMA_SRAM_H (0xB061F000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A10000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED2 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED3 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1300000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB1400000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_VU_SM_0 (0xB6121000)
+#define BASE_NADDR_MODEML1_AO_VU_SM_1 (0xB6122000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB6200000)
+#define BASE_NADDR_MODEML1_AO_C1X_EVENTGEN (0xB6210000)
+#define BASE_NADDR_MODEML1_AO_CDO_EVENTGEN (0xB6220000)
+#define BASE_NADDR_MODEML1_AO_FDD_EVENTGEN (0xB6230000)
+#define BASE_NADDR_MODEML1_AO_LTE_EVENTGEN (0xB6240000)
+#define BASE_NADDR_MODEML1_AO_TDD_EVENTGEN (0xB6250000)
+#define BASE_NADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xB6260000)
+#define BASE_NADDR_MODEML1_AO_MD_BUCK_CTRL (0xB6270000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_RESERVED0 (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_RESERVED1 (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_RESERVED2 (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MBIST_CR (0xBBB30000)
+#define BASE_NADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_MEM_PM (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_BUS_INTF (0xB8220800)
+#define BASE_NADDR_TXSYS_TPC_EXTIF (0xB8221000)
+#define BASE_NADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_NADDR_TXSYS_TPC_GCCORE (0xB8224000)
+#define BASE_NADDR_TXSYS_TPC_DMA (0xB8225000)
+#define BASE_NADDR_TXSYS_TPC_MEM_TQ (0xB8226000)
+#define BASE_NADDR_TXSYS_TPC_MEM_DM (0xB8228000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_2 (0xB8380000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXET_1 (0xB8420000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_AMSC (0xB84A0000)
+#define BASE_NADDR_TXSYS_AMSC_1 (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_2 (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB8500000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBC354000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_1 (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_PERI (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTE_CE (0xBD321000)
+#define BASE_NADDR_BRP_LTE_CE_TOP_1 (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DEMOD_TOP_REG (0xBD333000)
+#define BASE_NADDR_BRP_DEMOD (0xBD334000)
+#define BASE_NADDR_BRP_DEMOD_TOP_1 (0xBD335000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_1 (0xB7030000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_2 (0xB7040000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_3 (0xB7050000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_4 (0xB7060000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_5 (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MRSG_1 (0xB7120000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDPERI_CORE2_MEM_CONFIG (0xB01DA000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MML2_CFG_SRAM (0xB060D000)
+#define BASE_ADDR_MML2_RDMA_SRAM_L (0xB060E000)
+#define BASE_ADDR_MML2_RDMA_SRAM_H (0xB060F000)
+#define BASE_ADDR_MML2_DLCH_QP_APB (0xB0610000)
+#define BASE_ADDR_MML2_DLCH_RDMA (0xB0611000)
+#define BASE_ADDR_MML2_DLCH_CIPHER (0xB0612000)
+#define BASE_ADDR_MML2_IPF_UL (0xB0614000)
+#define BASE_ADDR_MML2_IPF_DL (0xB0615000)
+#define BASE_ADDR_MML2_IPF_HPCNAT (0xB0616000)
+#define BASE_ADDR_MML2_IPF_PN (0xB0617000)
+#define BASE_ADDR_MML2_ROHC (0xB0618000)
+#define BASE_ADDR_MML2_IPF_SRAM (0xB061D000)
+#define BASE_ADDR_MML2_WDMA_SRAM_L (0xB061E000)
+#define BASE_ADDR_MML2_WDMA_SRAM_H (0xB061F000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A10000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED2 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED3 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1300000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB1400000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_VU_SM_0 (0xB6121000)
+#define BASE_ADDR_MODEML1_AO_VU_SM_1 (0xB6122000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB6200000)
+#define BASE_ADDR_MODEML1_AO_C1X_EVENTGEN (0xB6210000)
+#define BASE_ADDR_MODEML1_AO_CDO_EVENTGEN (0xB6220000)
+#define BASE_ADDR_MODEML1_AO_FDD_EVENTGEN (0xB6230000)
+#define BASE_ADDR_MODEML1_AO_LTE_EVENTGEN (0xB6240000)
+#define BASE_ADDR_MODEML1_AO_TDD_EVENTGEN (0xB6250000)
+#define BASE_ADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xB6260000)
+#define BASE_ADDR_MODEML1_AO_MD_BUCK_CTRL (0xB6270000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_RESERVED0 (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_RESERVED1 (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_RESERVED2 (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MBIST_CR (0xBBB30000)
+#define BASE_ADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_MEM_PM (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_BUS_INTF (0xB8220800)
+#define BASE_ADDR_TXSYS_TPC_EXTIF (0xB8221000)
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TPC_GCCORE (0xB8224000)
+#define BASE_ADDR_TXSYS_TPC_DMA (0xB8225000)
+#define BASE_ADDR_TXSYS_TPC_MEM_TQ (0xB8226000)
+#define BASE_ADDR_TXSYS_TPC_MEM_DM (0xB8228000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_2 (0xB8380000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXET_1 (0xB8420000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_AMSC (0xB84A0000)
+#define BASE_ADDR_TXSYS_AMSC_1 (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_2 (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB8500000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBC354000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_1 (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_PERI (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTE_CE (0xBD321000)
+#define BASE_ADDR_BRP_LTE_CE_TOP_1 (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DEMOD_TOP_REG (0xBD333000)
+#define BASE_ADDR_BRP_DEMOD (0xBD334000)
+#define BASE_ADDR_BRP_DEMOD_TOP_1 (0xBD335000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6295_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED2
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED3
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBSRP
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED2
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED3
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBSRP
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED2
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED3
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBSRP
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBSRP
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBSRP
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBSRP
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6295_FPGA_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT6295M_FPGA_username.h b/mcu/interface/driver/regbase/md95/reg_base_MT6295M_FPGA_username.h
new file mode 100644
index 0000000..1372fba
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT6295M_FPGA_username.h
@@ -0,0 +1,498 @@
+#ifndef __REG_BASE_MT6295M_USERNAME_H__
+#define __REG_BASE_MT6295M_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+// SE7/SD3 RaymondWT
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1F10000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 James Pan & Clint Chang request (Gen 95)
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+// tmp workaroud
+// since def in reg_base_MT6295M.h and reg_base_MT6295M_FPGA.h are different
+#define BASE_ADDR_BRAM_BIGRAM_GLOBAL_CON (BASE_ADDR_BRAM_BIGRAMSYS_GLOBAL_CON)
+
+// SE2/CS10 FI Chu. Temp workaround, wait for EL1D DFE_DUMP owner: Chun-An Chen confirmation
+#define BASE_ADDR_BRAM_BIGRAM_DFE_DUMP (0xBB800000)
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+// MD Log DMA
+#define BASE_MADDR_MDLOGDMA (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_MDLOGDMA (BASE_ADDR_MDGDMA)
+// MD L1_GDMA
+#define BASE_MADDR_L1GDMA_1 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_1 (BASE_ADDR_MDGDMA)
+#define BASE_MADDR_L1GDMA_2 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_2 (BASE_ADDR_MDGDMA)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+// WCT1/SE2/CS17 Shivanand, for temp build issue
+#define BASE_MADDR_FDD_EVENTGEN (0xA6230000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+#define BASE_MADDR_RXDFESYS_CONFIG (0xA7010000)
+
+// WCS/SE2/CS1 YW Lee for MT6295M FPGA temp build
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+
+//WCS/SD/SP3 Owen Hsieh
+#define AMSC_REG_BASE (0xB3700000)
+#define AMSC_TQ_SRAM_REG_BASE (0xB84A8000)
+
+//WCS/SE2/BSD Tom-CT Wu temp for EMI bus hang
+#define BASE_RXDFE_MODEM_TEMP (0xA7000000)
+#define BASE_CS_MODEM_TEMP (0xA7830000)
+#define BASE_ML1AO_BUS_MODEM_TEMP (0xA61C0000)
+#define BASE_TXSBRP_MAS_BUS0_MODEM_TEMP (0xA8180000)
+#define BASE_TXSBRP_MAS_BUS1_MODEM_TEMP (0xA8500000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6295M_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT6295M_username.h b/mcu/interface/driver/regbase/md95/reg_base_MT6295M_username.h
new file mode 100644
index 0000000..32b708e
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT6295M_username.h
@@ -0,0 +1,498 @@
+#ifndef __REG_BASE_MT6295M_USERNAME_H__
+#define __REG_BASE_MT6295M_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+#define BASE_MADDR_APMCU_MISC (0xC0000000)
+#define BASE_MADDR_APMCU_MBIST (0xC0100000)
+#define BASE_MADDR_APMCUBUSMON (0xC0200000)
+#define BASE_MADDR_USB20_MAC (0xC1000000)
+#define BASE_MADDR_MSDC_0 (0xC1200000)
+#define BASE_MADDR_SPI_AHB (0xC1300000)
+#define BASE_MADDR_SPI_SF (0xC1340000)
+#define BASE_MADDR_APINFRA_APB_1 (0xC1400000)
+#define BASE_MADDR_APINFRA_APB_2 (0xC1500000)
+#define BASE_MADDR_MSDC_1 (0xC1600000)
+#define BASE_MADDR_MSDC_C2K (0xC1700000)
+#define BASE_MADDR_MEMAPB (0xC3000000)
+#define BASE_MADDR_USB20_PHY (0xC3100000)
+#define BASE_MADDR_U3PHY0 (0xC3300000)
+#define BASE_MADDR_U3PHY1 (0xC3400000)
+#define BASE_MADDR_APPERI_APB_1 (0xC3500000)
+#define BASE_MADDR_APPERI_APB_2 (0xC3600000)
+#define BASE_MADDR_APPERI_APB_3 (0xC3700000)
+#define BASE_MADDR_U3MAC0 (0xC3800000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_MADDR_NFI_MD (0xC1400000)
+#define BASE_MADDR_NFI_AP (0xC1410000)
+#define BASE_MADDR_AP_IPSEC (0xC1420000)
+#define BASE_MADDR_APGDMA (0xC1430000)
+#define BASE_MADDR_PFC_EN (0xC1440000)
+#define BASE_MADDR_APINFRA_MISC (0xC1440000)
+#define BASE_MADDR_HIF (0xC1450000)
+#define BASE_MADDR_APPAXIMON0 (0xC1460000)
+#define BASE_MADDR_APPAHBMON0 (0xC1464000)
+#define BASE_MADDR_APUART1 (0xC1470000)
+#define BASE_MADDR_APUART2 (0xC1480000)
+#define BASE_MADDR_APCLDMAIN (0xC1490000)
+#define BASE_MADDR_APCLDMAOUT (0xC1490400)
+#define BASE_MADDR_APCLDMAMISC (0xC1490800)
+#define BASE_MADDR_MDCLDMAIN (0xC14A0000)
+#define BASE_MADDR_MDCLDMAOUT (0xC14A0400)
+#define BASE_MADDR_MDCLDMAMISC (0xC14A0800)
+#define BASE_MADDR_APINFRA_MBIST (0xC14B0000)
+#define BASE_MADDR_TRNG (0xC14C0000)
+#define BASE_MADDR_THERM_CTRL (0xC14D0000)
+#define BASE_MADDR_APSYS_MBIST (0xC14E0000)
+#define BASE_MADDR_PCCIF0_AP (0xC1500000)
+#define BASE_MADDR_PCCIF0_MD (0xC1510000)
+#define BASE_MADDR_PCCIF1_AP (0xC1520000)
+#define BASE_MADDR_PCCIF1_MD (0xC1530000)
+#define BASE_MADDR_PCCIF2_AP (0xC1540000)
+#define BASE_MADDR_PCCIF2_MD (0xC1550000)
+#define BASE_MADDR_PCCIF3_AP (0xC1560000)
+#define BASE_MADDR_PCCIF3_MD (0xC1570000)
+#define BASE_MADDR_EMI (0xC3000000)
+#define BASE_MADDR_DRAMC (0xC3010000)
+#define BASE_MADDR_DDRPHY (0xC3020000)
+#define BASE_MADDR_SRAMROM (0xC3030000)
+#define BASE_MADDR_MEMSYSCORE_MISC (0xC3040000)
+#define BASE_MADDR_MEMSYSCORE_MBIST (0xC3050000)
+#define BASE_MADDR_MEMINFRA_DMA_SMI (0xC3060000)
+#define BASE_MADDR_MEMINFRA_MCU_SMI (0xC3070000)
+#define BASE_MADDR_MEMSYSAOREG_MISC (0xC3080000)
+#define BASE_MADDR_NFI_AO (0xC3500000)
+#define BASE_MADDR_NLI_ARB (0xC3510000)
+#define BASE_MADDR_APUART0 (0xC3520000)
+#define BASE_MADDR_APLED (0xC3530000)
+#define BASE_MADDR_SEJ (0xC3540000)
+#define BASE_MADDR_APCLDMAIN_AO (0xC3550000)
+#define BASE_MADDR_APCLDMAOUT_AO (0xC3550400)
+#define BASE_MADDR_APCLDMAMISC_AO (0xC3550800)
+#define BASE_MADDR_MDCLDMAIN_AO (0xC3560000)
+#define BASE_MADDR_MDCLDMAOUT_AO (0xC3560400)
+#define BASE_MADDR_MDCLDMAMISC_AO (0xC3560800)
+#define BASE_MADDR_APGPTM (0xC3570000)
+#define BASE_MADDR_SDIO (0xC3580000)
+#define BASE_MADDR_PMIC_BSI (0xC3590000)
+#define BASE_MADDR_RTC (0xC35A0000)
+#define BASE_MADDR_MODEM_TEMP_SHARE (0xC3680000)
+#define BASE_MADDR_AP_GPIOMUX (0xC3600000)
+#define BASE_MADDR_APCFGCTL (0xC3620000)
+#define BASE_MADDR_APOSTIMER (0xC3630000)
+#define BASE_MADDR_APTOPSM (0xC3640000)
+#define BASE_MADDR_APMISC (0xC3650000)
+#define BASE_MADDR_APDBGMON (0xC3660000)
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_MADDR_APSYS_CLKCTL (0xC3690000)
+#define BASE_MADDR_APDBGSYS (0xC36C0000)
+#define BASE_MADDR_APCTI (0xC36E8000)
+#define BASE_MADDR_EFUSE (0xC3700000)
+#define BASE_MADDR_IOMUX0 (0xC3710000)
+#define BASE_MADDR_IOMUX1 (0xC3720000)
+#define BASE_MADDR_IOMUX2 (0xC3730000)
+#define BASE_MADDR_APTOP_PLLMIXED (0xC3740000)
+#define BASE_MADDR_APTOP_CLKSW (0xC3750000)
+#define BASE_MADDR_TSTCTL (0xC3760000)
+#define BASE_MADDR_TOPDBGMON (0xC3770000)
+#define BASE_MADDR_AUXADC (0xC3780000)
+#define BASE_MADDR_TOPMBIST (0xC3790000)
+#define BASE_MADDR_APTOP_GLBCON (0xC37A0000)
+#define BASE_NADDR_APMCU_MISC (0xD0000000)
+#define BASE_NADDR_APMCU_MBIST (0xD0100000)
+#define BASE_NADDR_APMCUBUSMON (0xD0200000)
+#define BASE_NADDR_USB20_MAC (0xD1000000)
+#define BASE_NADDR_MSDC_0 (0xD1200000)
+#define BASE_NADDR_SPI_AHB (0xD1300000)
+#define BASE_NADDR_SPI_SF (0xD1340000)
+#define BASE_NADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_NADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_NADDR_MSDC_1 (0xD1600000)
+#define BASE_NADDR_MSDC_C2K (0xD1700000)
+#define BASE_NADDR_MEMAPB (0xD3000000)
+#define BASE_NADDR_USB20_PHY (0xD3100000)
+#define BASE_NADDR_U3PHY0 (0xD3300000)
+#define BASE_NADDR_U3PHY1 (0xD3400000)
+#define BASE_NADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_NADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_NADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_NADDR_U3MAC0 (0xD3800000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_NADDR_NFI_MD (0xD1400000)
+#define BASE_NADDR_NFI_AP (0xD1410000)
+#define BASE_NADDR_AP_IPSEC (0xD1420000)
+#define BASE_NADDR_APGDMA (0xD1430000)
+#define BASE_NADDR_PFC_EN (0xD1440000)
+#define BASE_NADDR_APINFRA_MISC (0xD1440000)
+#define BASE_NADDR_HIF (0xD1450000)
+#define BASE_NADDR_APPAXIMON0 (0xD1460000)
+#define BASE_NADDR_APPAHBMON0 (0xD1464000)
+#define BASE_NADDR_APUART1 (0xD1470000)
+#define BASE_NADDR_APUART2 (0xD1480000)
+#define BASE_NADDR_APCLDMAIN (0xD1490000)
+#define BASE_NADDR_APCLDMAOUT (0xD1490400)
+#define BASE_NADDR_APCLDMAMISC (0xD1490800)
+#define BASE_NADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_NADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_NADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_NADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_NADDR_TRNG (0xD14C0000)
+#define BASE_NADDR_THERM_CTRL (0xD14D0000)
+#define BASE_NADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_NADDR_PCCIF0_AP (0xD1500000)
+#define BASE_NADDR_PCCIF0_MD (0xD1510000)
+#define BASE_NADDR_PCCIF1_AP (0xD1520000)
+#define BASE_NADDR_PCCIF1_MD (0xD1530000)
+#define BASE_NADDR_PCCIF2_AP (0xD1540000)
+#define BASE_NADDR_PCCIF2_MD (0xD1550000)
+#define BASE_NADDR_PCCIF3_AP (0xD1560000)
+#define BASE_NADDR_PCCIF3_MD (0xD1570000)
+#define BASE_NADDR_EMI (0xD3000000)
+#define BASE_NADDR_DRAMC (0xD3010000)
+#define BASE_NADDR_DDRPHY (0xD3020000)
+#define BASE_NADDR_SRAMROM (0xD3030000)
+#define BASE_NADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_NADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_NADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_NADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_NADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_NADDR_NFI_AO (0xD3500000)
+#define BASE_NADDR_NLI_ARB (0xD3510000)
+#define BASE_NADDR_APUART0 (0xD3520000)
+#define BASE_NADDR_APLED (0xD3530000)
+#define BASE_NADDR_SEJ (0xD3540000)
+#define BASE_NADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_NADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_NADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_NADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_NADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_NADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_NADDR_APGPTM (0xD3570000)
+#define BASE_NADDR_SDIO (0xD3580000)
+#define BASE_NADDR_PMIC_BSI (0xD3590000)
+#define BASE_NADDR_RTC (0xD35A0000)
+#define BASE_NADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_NADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_NADDR_APCFGCTL (0xD3620000)
+#define BASE_NADDR_APOSTIMER (0xD3630000)
+#define BASE_NADDR_APTOPSM (0xD3640000)
+#define BASE_NADDR_APMISC (0xD3650000)
+#define BASE_NADDR_APDBGMON (0xD3660000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_NADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_NADDR_APDBGSYS (0xD36C0000)
+#define BASE_NADDR_APCTI (0xD36E8000)
+#define BASE_NADDR_EFUSE (0xD3700000)
+#define BASE_NADDR_IOMUX0 (0xD3710000)
+#define BASE_NADDR_IOMUX1 (0xD3720000)
+#define BASE_NADDR_IOMUX2 (0xD3730000)
+#define BASE_NADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_NADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_NADDR_TSTCTL (0xD3760000)
+#define BASE_NADDR_TOPDBGMON (0xD3770000)
+#define BASE_NADDR_AUXADC (0xD3780000)
+#define BASE_NADDR_TOPMBIST (0xD3790000)
+#define BASE_NADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_ADDR_APMCU_MISC (0xD0000000)
+#define BASE_ADDR_APMCU_MBIST (0xD0100000)
+#define BASE_ADDR_APMCUBUSMON (0xD0200000)
+#define BASE_ADDR_USB20_MAC (0xD1000000)
+#define BASE_ADDR_MSDC_0 (0xD1200000)
+#define BASE_ADDR_SPI_AHB (0xD1300000)
+#define BASE_ADDR_SPI_SF (0xD1340000)
+#define BASE_ADDR_APINFRA_APB_1 (0xD1400000)
+#define BASE_ADDR_APINFRA_APB_2 (0xD1500000)
+#define BASE_ADDR_MSDC_1 (0xD1600000)
+#define BASE_ADDR_MSDC_C2K (0xD1700000)
+#define BASE_ADDR_MEMAPB (0xD3000000)
+#define BASE_ADDR_USB20_PHY (0xD3100000)
+#define BASE_ADDR_U3PHY0 (0xD3300000)
+#define BASE_ADDR_U3PHY1 (0xD3400000)
+#define BASE_ADDR_APPERI_APB_1 (0xD3500000)
+#define BASE_ADDR_APPERI_APB_2 (0xD3600000)
+#define BASE_ADDR_APPERI_APB_3 (0xD3700000)
+#define BASE_ADDR_U3MAC0 (0xD3800000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_NFI_MD (0xD1400000)
+#define BASE_ADDR_NFI_AP (0xD1410000)
+#define BASE_ADDR_AP_IPSEC (0xD1420000)
+#define BASE_ADDR_APGDMA (0xD1430000)
+#define BASE_ADDR_PFC_EN (0xD1440000)
+#define BASE_ADDR_APINFRA_MISC (0xD1440000)
+#define BASE_ADDR_HIF (0xD1450000)
+#define BASE_ADDR_APPAXIMON0 (0xD1460000)
+#define BASE_ADDR_APPAHBMON0 (0xD1464000)
+#define BASE_ADDR_APUART1 (0xD1470000)
+#define BASE_ADDR_APUART2 (0xD1480000)
+#define BASE_ADDR_APCLDMAIN (0xD1490000)
+#define BASE_ADDR_APCLDMAOUT (0xD1490400)
+#define BASE_ADDR_APCLDMAMISC (0xD1490800)
+#define BASE_ADDR_MDCLDMAIN (0xD14A0000)
+#define BASE_ADDR_MDCLDMAOUT (0xD14A0400)
+#define BASE_ADDR_MDCLDMAMISC (0xD14A0800)
+#define BASE_ADDR_APINFRA_MBIST (0xD14B0000)
+#define BASE_ADDR_TRNG (0xD14C0000)
+#define BASE_ADDR_THERM_CTRL (0xD14D0000)
+#define BASE_ADDR_APSYS_MBIST (0xD14E0000)
+#define BASE_ADDR_PCCIF0_AP (0xD1500000)
+#define BASE_ADDR_PCCIF0_MD (0xD1510000)
+#define BASE_ADDR_PCCIF1_AP (0xD1520000)
+#define BASE_ADDR_PCCIF1_MD (0xD1530000)
+#define BASE_ADDR_PCCIF2_AP (0xD1540000)
+#define BASE_ADDR_PCCIF2_MD (0xD1550000)
+#define BASE_ADDR_PCCIF3_AP (0xD1560000)
+#define BASE_ADDR_PCCIF3_MD (0xD1570000)
+#define BASE_ADDR_EMI (0xD3000000)
+#define BASE_ADDR_DRAMC (0xD3010000)
+#define BASE_ADDR_DDRPHY (0xD3020000)
+#define BASE_ADDR_SRAMROM (0xD3030000)
+#define BASE_ADDR_MEMSYSCORE_MISC (0xD3040000)
+#define BASE_ADDR_MEMSYSCORE_MBIST (0xD3050000)
+#define BASE_ADDR_MEMINFRA_DMA_SMI (0xD3060000)
+#define BASE_ADDR_MEMINFRA_MCU_SMI (0xD3070000)
+#define BASE_ADDR_MEMSYSAOREG_MISC (0xD3080000)
+#define BASE_ADDR_NFI_AO (0xD3500000)
+#define BASE_ADDR_NLI_ARB (0xD3510000)
+#define BASE_ADDR_APUART0 (0xD3520000)
+#define BASE_ADDR_APLED (0xD3530000)
+#define BASE_ADDR_SEJ (0xD3540000)
+#define BASE_ADDR_APCLDMAIN_AO (0xD3550000)
+#define BASE_ADDR_APCLDMAOUT_AO (0xD3550400)
+#define BASE_ADDR_APCLDMAMISC_AO (0xD3550800)
+#define BASE_ADDR_MDCLDMAIN_AO (0xD3560000)
+#define BASE_ADDR_MDCLDMAOUT_AO (0xD3560400)
+#define BASE_ADDR_MDCLDMAMISC_AO (0xD3560800)
+#define BASE_ADDR_APGPTM (0xD3570000)
+#define BASE_ADDR_SDIO (0xD3580000)
+#define BASE_ADDR_PMIC_BSI (0xD3590000)
+#define BASE_ADDR_RTC (0xD35A0000)
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD3680000)
+#define BASE_ADDR_AP_GPIOMUX (0xD3600000)
+#define BASE_ADDR_APCFGCTL (0xD3620000)
+#define BASE_ADDR_APOSTIMER (0xD3630000)
+#define BASE_ADDR_APTOPSM (0xD3640000)
+#define BASE_ADDR_APMISC (0xD3650000)
+#define BASE_ADDR_APDBGMON (0xD3660000)
+#define BASE_ADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APSYS_CLKCTL (0xD3690000)
+#define BASE_ADDR_APDBGSYS (0xD36C0000)
+#define BASE_ADDR_APCTI (0xD36E8000)
+#define BASE_ADDR_EFUSE (0xD3700000)
+#define BASE_ADDR_IOMUX0 (0xD3710000)
+#define BASE_ADDR_IOMUX1 (0xD3720000)
+#define BASE_ADDR_IOMUX2 (0xD3730000)
+#define BASE_ADDR_APTOP_PLLMIXED (0xD3740000)
+#define BASE_ADDR_APTOP_CLKSW (0xD3750000)
+#define BASE_ADDR_TSTCTL (0xD3760000)
+#define BASE_ADDR_TOPDBGMON (0xD3770000)
+#define BASE_ADDR_AUXADC (0xD3780000)
+#define BASE_ADDR_TOPMBIST (0xD3790000)
+#define BASE_ADDR_APTOP_GLBCON (0xD37A0000)
+#define BASE_MADDR_AUDIO (0xC1220000)
+#define BASE_NADDR_AUDIO (0xD1220000)
+#define BASE_ADDR_AUDIO (0xD1220000)
+
+#define BASE_AP_CLDMA_AO_UL (0xC3554000)
+#define BASE_AP_CLDMA_AO_DL (0xC3554400)
+#define BASE_AP_CLDMA_AO_MISC (0xC3554800)
+#define BASE_AP_CLDMA_TOP_UL (0xC149B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC149B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC149B800)
+#define BASE_AP_CLDMA_TOP_MD (0xC14AC800)
+
+// SE7/SD3 RaymondWT
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1F10000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+
+// SE7/SD3 Chao-Hung Hsu
+#define TEC_BASEADDR (0xCFFFFFFF0)
+
+// WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_AP_EMI_CONFIG (0xC0219000)
+
+// WCS/SSE/SS3 Chia-Fu Lee & WCS/SSE/SS2 Linson Du
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+#if !defined(__FPGA__)
+// WSP/SE7/SD8 CW Wang, for CLDMA
+#define BASE_AP_CLDMA_AO_UL (0xC0014000)
+#define BASE_AP_CLDMA_AO_DL (0xC0014400)
+#define BASE_AP_CLDMA_AO_MISC (0xC0014800)
+#define BASE_AP_CLDMA_TOP_UL (0xC021B000)
+#define BASE_AP_CLDMA_TOP_DL (0xC021B400)
+#define BASE_AP_CLDMA_TOP_AP (0xC021B800)
+#endif
+
+// WSP/SE7/SD3 Hsin-Hao Huang, for DPMAIF
+#define BASE_AP_DPMAIF_TOP_MD (0xC022C000)
+#define BASE_AP_DPMAIF_PD_BASE (0xC022D000)
+
+// WSP/SE7/SD10 Guo-Huei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WCT1/SE1/SE9 Shelley.Liu Move to el1d_reg_gen93m17.h
+//#define MODEM_TEMP_SHARE_REG_BASE (0xD0018000)
+
+//End of AP registers
+
+
+/****************************
+* MD registers *
+*****************************/
+
+// SE7/SS1 Yen-Tsung Cheng
+#define BASE_ADDR_DFESYS_1 (0xB3000000)
+#define BASE_MADDR_DFESYS_1 (0xA3000000)
+
+// SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+// SE2/CS15 James Pan & Clint Chang request (Gen 95)
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+
+//WCT1/SE2/CS3 Rick Wu, temp workaround for build error
+#define L1_BASE_MADDR_L1INFRA_CONF (0xA6800000)
+#define L1_BASE_MADDR_FCS (0xA6810000)
+
+//SE2/CS3 GL1 Sy.Yeh
+#define FCS2G_base (BASE_MADDR_MDINFRA_FCS)
+
+
+// SE7/SS2 Alan-TL Lin
+/* PDA Monitor Base Address */
+#define BASE_ADDR_MDPCMON (BASE_ADDR_MDMCU_PDAMON)
+#define BASE_MADDR_MDPCMON (BASE_MADDR_MDMCU_PDAMON)
+
+// SE7/SS2 YH Peng
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+// SE7/SD3 Grass Chang
+#define MDSYS_PERI_ACC_TYPE_MASK (0xA0000000)
+#define MDSYS_PERI_DEVICE_TYPE (0xB0000000)
+
+// SE7/SD3 Yi-Chih
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//#define BASE_MADDR_WCN_AHB_SLAVE (0xA8000000) //For BT
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (0xA6FC0000) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+/* WCT1/SSE/SS2 Alan-TL Lin */
+// PDA Monitor
+#define BASE_NBADDR_PDAMON (BASE_MADDR_MDMCU_PDAMON)
+#define BASE_BADDR_PDAMON (BASE_ADDR_MDMCU_PDAMON)
+// MD Log DMA
+#define BASE_MADDR_MDLOGDMA (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_MDLOGDMA (BASE_ADDR_MDGDMA)
+// MD L1_GDMA
+#define BASE_MADDR_L1GDMA_1 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_1 (BASE_ADDR_MDGDMA)
+#define BASE_MADDR_L1GDMA_2 (BASE_MADDR_MDGDMA)
+#define BASE_ADDR_L1GDMA_2 (BASE_ADDR_MDGDMA)
+
+// WCT1/SSE/SS2 I-Chun Liu
+#define BASE_MADDR_MDPERISYS_MDCIRQ (0x1E004000)
+
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCT1/SE2/CS6 Max Weng, temp workaround for build error (resue FDD_TIMER's base)
+#if defined(L1_SIM)
+#define L1_BASE_MADDR_DFE0_CMIF (0xAF010000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xAF020000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xAF040000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xAF070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xAF080000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xAF090000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xAF0A0000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xAF0B0000)
+#else
+#define L1_BASE_MADDR_DFE0_CMIF (0xA6070000)
+#define L1_BASE_MADDR_RXBRP_CDIF (0xA6070000)
+#define L1_BASE_MADDR_DFESYS0_CFG (0xA6070000)
+#define L1_BASE_MADDR_EQ1_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ2_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_EQ3_CONFIG (0xA6070000)
+#define BASE_MADDR_BRPSYS_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_RAKESYS_MEM_CONFIG (BASE_MADDR_RAKESYS||0x00210000)
+#define BASE_MADDR_RAKESYS_CONFIG (BASE_MADDR_RAKESYS||0x00200000)
+#define L1_BASE_MADDR_RXBRP_BRPSYS_AO_CONFIG (0xA6070000)
+#define L1_BASE_MADDR_CSTXB_CONFIG (0xA6070000)
+#endif
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//WCT/SE2/CS9 Paul, for temp build pass.
+#define L1_BASE_MADDR_DFE0_WTL_RX_FC (0xA7F90000)
+#define L1_BASE_MADDR_DFE1_WTL_RX_FC (0xA3790000)
+#define L1_BASE_MADDR_DFE0_WTL_TXDFE (0xA7F40000)
+#define L1_BASE_MADDR_DFE1_WTL_TXDFE (0xA3740000)
+
+//WCT/SE2/CS9 Neil, for temp build pass
+#define L1_BASE_MADDR_DFE0_WL_TXIRQ (0xA7F70000)
+
+//WCT1/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WCT1/SE2/CS7 Aman, for temp build issue
+#define L1_BASE_MADDR_MDL1_CONF (0xA60F0000)
+
+// WCT1/SE2/CS17 Shivanand, for temp build issue
+#define BASE_MADDR_FDD_EVENTGEN (0xA6230000)
+#define BASE_MADDR_BRAM_BIGRAM_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_TXSYS_TXBRP_CC0 (0xA8000000)
+#define BASE_MADDR_TXSYS_TXBRP_CC1 (0xA8080000)
+
+// WCS/SE2/CS1 YW Lee for MT6295M FPGA temp build
+#define BASE_NADDR_RXDFESYS_MM_EVENTGEN (0xB7120000)
+
+
+//WCS/SD/SP3 Owen Hsieh
+#define AMSC_REG_BASE (0xB3700000)
+#define AMSC_TQ_SRAM_REG_BASE (0xB84A8000)
+
+//WCS/SE2/BSD Tom-CT Wu temp for EMI bus hang
+#define BASE_RXDFE_MODEM_TEMP (0xA7000000)
+#define BASE_CS_MODEM_TEMP (0xA7830000)
+#define BASE_ML1AO_BUS_MODEM_TEMP (0xA61C0000)
+#define BASE_TXSBRP_MAS_BUS0_MODEM_TEMP (0xA8180000)
+#define BASE_TXSBRP_MAS_BUS1_MODEM_TEMP (0xA8500000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6295M_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT6779.h b/mcu/interface/driver/regbase/md95/reg_base_MT6779.h
new file mode 100644
index 0000000..d4b9dec
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT6779.h
@@ -0,0 +1,1511 @@
+#ifndef __REG_BASE_MT6779_H__
+#define __REG_BASE_MT6779_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6295_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+// (0): Top_MT6295
+// (1): E+S+L2+B
+#define BASE_ADDR_MDCORESYS_SPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_LSRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_BTSLV (0x9FE00000)
+// (2): v6
+// (3): (V) RXDFESYS
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_1 (0xA7030000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_2 (0xA7040000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_3 (0xA7050000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_4 (0xA7060000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA_5 (0xA7070000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_MRSG_1 (0xA7120000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xA7410000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_MDSYS Partition
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS1 (0xA0080000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS2 (0xA0090000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS3 (0xA00A0000)
+#define BASE_MADDR_MDPERI_MD_DBGSYS4 (0xA00B0000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_USIP0_MEM_CONFIG (0xA01D0000)
+#define BASE_MADDR_MDPERI_CORE0_MEM_CONFIG (0xA01D2000)
+#define BASE_MADDR_MDPERI_CORE1_MEM_CONFIG (0xA01D3000)
+#define BASE_MADDR_MDPERI_MDCORE_MEM_CONFIG (0xA01D4000)
+#define BASE_MADDR_MDPERI_MDINFRA_MEM_CONFIG (0xA01D5000)
+#define BASE_MADDR_MDPERI_MDMEMSLP_CONFIG (0xA01D6000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xA01D8000)
+#define BASE_MADDR_MDPERI_MDMML2_MEM_CONFIG (0xA01D9000)
+#define BASE_MADDR_MDPERI_CORE2_MEM_CONFIG (0xA01DA000)
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_MDSMICFG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_MD_INFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+#define BASE_MADDR_MML2_QUEUE_PROCESSOR (0xA0600000)
+#define BASE_MADDR_MML2_METADATA_MANAGER (0xA0601000)
+#define BASE_MADDR_MML2_VRB_MANAGER (0xA0602000)
+#define BASE_MADDR_MML2_MMU (0xA0603000)
+#define BASE_MADDR_MML2_DMA_RD (0xA0604000)
+#define BASE_MADDR_MML2_DMA_WR (0xA0605000)
+#define BASE_MADDR_MML2_LHIF (0xA0606000)
+#define BASE_MADDR_MML2_CIPHER (0xA0607000)
+#define BASE_MADDR_MML2_DL_LMAC (0xA0608000)
+#define BASE_MADDR_MML2_HARQ_CTRL (0xA0609000)
+#define BASE_MADDR_MML2_SRAM_WRAP (0xA060A000)
+#define BASE_MADDR_MML2_CFG (0xA060B000)
+#define BASE_MADDR_MML2_BYC (0xA060C000)
+#define BASE_MADDR_MML2_CFG_SRAM (0xA060D000)
+#define BASE_MADDR_MML2_RDMA_SRAM_L (0xA060E000)
+#define BASE_MADDR_MML2_RDMA_SRAM_H (0xA060F000)
+#define BASE_MADDR_MML2_DLCH_QP_APB (0xA0610000)
+#define BASE_MADDR_MML2_DLCH_RDMA (0xA0611000)
+#define BASE_MADDR_MML2_DLCH_CIPHER (0xA0612000)
+#define BASE_MADDR_MML2_IPF_UL (0xA0614000)
+#define BASE_MADDR_MML2_IPF_DL (0xA0615000)
+#define BASE_MADDR_MML2_IPF_HPCNAT (0xA0616000)
+#define BASE_MADDR_MML2_IPF_PN (0xA0617000)
+#define BASE_MADDR_MML2_ROHC (0xA0618000)
+#define BASE_MADDR_MML2_IPF_SRAM (0xA061D000)
+#define BASE_MADDR_MML2_WDMA_SRAM_L (0xA061E000)
+#define BASE_MADDR_MML2_WDMA_SRAM_H (0xA061F000)
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A10000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A20000)
+#define BASE_MADDR_MDINFRA_RESERVED2 (0xA0A40000)
+#define BASE_MADDR_MDINFRA_RESERVED3 (0xA0A50000)
+// (5): (V) uSIP PERI
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA1000000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA1040000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA1080000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA1100000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA1140000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA1180000)
+#define BASE_MADDR_USIP_RESERVED0 (0xA1300000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA1400000)
+#define BASE_MADDR_USIP_CONFG (0xA1600000)
+#define BASE_MADDR_USIP_MBIST_CONFG (0xA1610000)
+#define BASE_MADDR_USIP_DSPLOG (0xA1620000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA1630000)
+#define BASE_MADDR_USIP_MD_AFE (0xA1640000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA1650000)
+//#define BASE_MADDR_USIP_DVFS_CTRL__RESERVED_ (0xA1660000)
+#define BASE_MADDR_USIP_RESERVED1 (0xA1670000)
+#define BASE_MADDR_USIP_RESERVED2 (0xA1680000)
+#define BASE_MADDR_USIP_PERI_RESERVED3 (0xA1700000)
+// (6): mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0x50000000)
+#define BASE_ADDR_MDCORESYS_IA_MBB3_INTEGRATION (0x9F800000)
+#define BASE_ADDR_MDCORESYS_MDL1_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+// (7): (V) MODEML1 AO
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA6000000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xA6010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA6020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA6030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA6040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA6050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA6060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA6070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA6080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA6090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA60A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA60B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA60C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA60D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA60E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA60F0000)
+#define BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS (0xA6100000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA6110000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xA6120000)
+#define BASE_MADDR_MODEML1_AO_VU_SM_0 (0xA6121000)
+#define BASE_MADDR_MODEML1_AO_VU_SM_1 (0xA6122000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xA6130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA6140000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_1 (0xA6150000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_2 (0xA6160000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_3 (0xA6170000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA6180000)
+#define BASE_MADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xA6190000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA61A0000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA61B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA61C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA61D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA61E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA61F0000)
+#define BASE_MADDR_MODEML1_AO_RESERVED0 (0xA6200000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA6200000)
+#define BASE_MADDR_MODEML1_AO_C1X_EVENTGEN (0xA6210000)
+#define BASE_MADDR_MODEML1_AO_CDO_EVENTGEN (0xA6220000)
+#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+#define BASE_MADDR_MODEML1_AO_LTE_EVENTGEN (0xA6240000)
+#define BASE_MADDR_MODEML1_AO_TDD_EVENTGEN (0xA6250000)
+#define BASE_MADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xA6260000)
+#define BASE_MADDR_MODEML1_AO_MD_BUCK_CTRL (0xA6270000)
+// (8): MAP_INR PARTITION
+#define BASE_MADDR_BRAM_BIGRAM_MEM (0xA9000000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_PM (0xA9800000)
+#define BASE_MADDR_BRAM_SCQ_SHARED_DM (0xA9A00000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_PM (0xAA000000)
+#define BASE_MADDR_BRAM_SCQ0_LOCAL_DM (0xAA200000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_PM (0xAA400000)
+#define BASE_MADDR_BRAM_SCQ1_LOCAL_DM (0xAA600000)
+#define BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xAB800000)
+#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BRAM_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BRAM_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BRAM_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BRAM_SCQ_HW_SCHEDULER (0xAB900000)
+#define BASE_MADDR_BRAM_SCQ_SEMAPHORE (0xAB910000)
+#define BASE_MADDR_BRAM_RESERVED0 (0xAB920000)
+#define BASE_MADDR_BRAM_SCQ_GLOBAL_CON (0xAB930000)
+#define BASE_MADDR_BRAM_SCQ_MBIST_CR (0xAB940000)
+#define BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB (0xABA00000)
+#define BASE_MADDR_BRAM_SCQ0_VU_CR (0xABA10000)
+#define BASE_MADDR_BRAM_RESERVED1 (0xABA20000)
+#define BASE_MADDR_BRAM_SCQ0_MBIST_CR (0xABA30000)
+#define BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB (0xABB00000)
+#define BASE_MADDR_BRAM_SCQ1_VU_CR (0xABB10000)
+#define BASE_MADDR_BRAM_RESERVED2 (0xABB20000)
+#define BASE_MADDR_BRAM_SCQ1_MBIST_CR (0xABB30000)
+// (9): TXSYS
+#define BASE_MADDR_TXSYS_TXBSRP (0xA8000000)
+#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+#define BASE_MADDR_TXSYS_TXBRP_BUS_CONFIG (0xA8180000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG0 (0xA8198000)
+#define BASE_MADDR_TXSYS_TPC (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_MEM_PM (0xA8200000)
+#define BASE_MADDR_TXSYS_TPC_BUS_INTF (0xA8220800)
+#define BASE_MADDR_TXSYS_TPC_EXTIF (0xA8221000)
+#define BASE_MADDR_TXSYS_TPC_TRG (0xA8221800)
+#define BASE_MADDR_TXSYS_TPC_GCCORE (0xA8224000)
+#define BASE_MADDR_TXSYS_TPC_DMA (0xA8225000)
+#define BASE_MADDR_TXSYS_TPC_MEM_TQ (0xA8226000)
+#define BASE_MADDR_TXSYS_TPC_MEM_DM (0xA8228000)
+#define BASE_MADDR_TXSYS_TXDFE_BB (0xA8300000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_1 (0xA8340000)
+#define BASE_MADDR_TXSYS_TXDFE_BB_2 (0xA8380000)
+#define BASE_MADDR_TXSYS_TXDFE_RF (0xA83C0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_1 (0xA83D0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_2 (0xA83E0000)
+#define BASE_MADDR_TXSYS_TXDFE_RF_3 (0xA83F0000)
+#define BASE_MADDR_TXSYS_TXET (0xA8400000)
+#define BASE_MADDR_TXSYS_TXET_1 (0xA8420000)
+#define BASE_MADDR_TXSYS_TXK (0xA8440000)
+#define BASE_MADDR_TXSYS_TXK_1 (0xA8450000)
+#define BASE_MADDR_TXSYS_TXK_2 (0xA8460000)
+#define BASE_MADDR_TXSYS_TXK_3 (0xA8470000)
+#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+#define BASE_MADDR_TXSYS_TDD_TTR (0xA8490000)
+#define BASE_MADDR_TXSYS_AMSC (0xA84A0000)
+#define BASE_MADDR_TXSYS_AMSC_1 (0xA84B0000)
+#define BASE_MADDR_TXSYS_LTE_TTR (0xA84C0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_1 (0xA84D0000)
+#define BASE_MADDR_TXSYS_LTE_TTR_2 (0xA84E0000)
+#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+#define BASE_MADDR_TXSYS_MBIST_CONFIG1 (0xA84F8000)
+#define BASE_MADDR_TXSYS_TXDFE_BUS_CONFIG (0xA8500000)
+// (10): (V) CSSYSY
+#define BASE_MADDR_CSSYS_CS (0xA7800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA7810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA7820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA7830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA7840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA7850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA7860000)
+#define BASE_MADDR_CSSYS_CS_WT_1 (0xA7870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA7880000)
+// (11): (V) MD2GSYS
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA6800000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA6900000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA6A00000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA6C00000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA6F00000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA6F10000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA6F20000)
+#define BASE_MADDR_MD2GSYS_APC (0xA6F30000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA6F40000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA6F70000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA6FA0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA6FB0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA6FC0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA6FE0000)
+// (12): MAP_RAKESYS
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xAC000000)
+#define BASE_MADDR_RAKESYS_RAKE_QLIC (0xAC010000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xAC020000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xAC030000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xAC040000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xAC050000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xAC060000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xAC070000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xAC080000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xAC090000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xAC0A0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xAC0F0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xAC100000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xAC110000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xAC200000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xAC210000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xAC300000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xAC340000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xAC350000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xAC351000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xAC354000)
+#define BASE_MADDR_RAKESYS_CMIF (0xAC358000)
+#define BASE_MADDR_RAKESYS_PM (0xAC380000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xAC390000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_1 (0xAC3A0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_2 (0xAC3B0000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB_3 (0xAC3C0000)
+#define BASE_MADDR_RAKESYS_DM (0xAC3D0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xAC3E0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB_1 (0xAC3F0000)
+// (13): MAP_BRPSYS
+#define BASE_MADDR_BRP_RXBRP_MBIST_CONFIG (0xAD000000)
+#define BASE_MADDR_BRP_DMC_MBIST (0xAD010000)
+#define BASE_MADDR_BRP_RXBRP_W_DRM (0xAD020000)
+#define BASE_MADDR_BRP_RXBRP_W_R99_WRAP (0xAD030000)
+#define BASE_MADDR_BRP_RXBRP_C_1XRTT (0xAD040000)
+#define BASE_MADDR_BRP_RXBRP_C_CORR_SER (0xAD050000)
+#define BASE_MADDR_BRP_RXBRP_WT_BCH (0xAD060000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DVIT (0xAD070000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TRACE (0xAD100000)
+#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_TUR (0xAD120000)
+#define BASE_MADDR_BRP_RXBRP_WTL_CVIT (0xAD130000)
+#define BASE_MADDR_BRP_RXBRP_WTL_HARQ_BUF (0xAD140000)
+#define BASE_MADDR_BRP_RXBRP_WCT_DMA (0xAD150000)
+#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+#define BASE_MADDR_BRP_RXBRP_WT_HARQ (0xAD170000)
+#define BASE_MADDR_BRP_RXBRP_WT_CDRM (0xAD180000)
+#define BASE_MADDR_BRP_RXBRP_W_CORR (0xAD200000)
+#define BASE_MADDR_BRP_RXBRP_W_TXIF (0xAD210000)
+#define BASE_MADDR_BRP_RXBRP_W_HSRM (0xAD220000)
+#define BASE_MADDR_BRP_RXBRP_C_EVDO (0xAD230000)
+#define BASE_MADDR_BRP_RXBRP_L_DBRP (0xAD240000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP (0xAD250000)
+#define BASE_MADDR_BRP_RXBRP_L_HARQ (0xAD260000)
+#define BASE_MADDR_BRP_RXBRP_L_REBRP (0xAD270000)
+#define BASE_MADDR_BRP_RXBRP_L_RBMAP (0xAD280000)
+#define BASE_MADDR_BRP_RXBRP_L_DCI_PARSER (0xAD290000)
+#define BASE_MADDR_BRP_RXBRP_L_CBRP_1 (0xAD2A0000)
+#define BASE_MADDR_BRP_RXBRP_WCTL_ECTRL (0xAD2B0000)
+#define BASE_MADDR_BRP_DMC (0xAD300000)
+#define BASE_MADDR_BRP_DMC_PERI (0xAD310000)
+#define BASE_MADDR_BRP_DMC_LTE_CE (0xAD320000)
+#define BASE_MADDR_BRP_LTE_CE (0xAD321000)
+#define BASE_MADDR_BRP_LTE_CE_TOP_1 (0xAD322000)
+#define BASE_MADDR_BRP_DMC_DEMOD (0xAD330000)
+#define BASE_MADDR_BRP_DEMOD_TOP_REG (0xAD333000)
+#define BASE_MADDR_BRP_DEMOD (0xAD334000)
+#define BASE_MADDR_BRP_DEMOD_TOP_1 (0xAD335000)
+#define BASE_MADDR_BRP_DMC_MIMO (0xAD340000)
+#define BASE_MADDR_BRP_DMC_PWR_MEAS (0xAD350000)
+// (15): Eiger APMD Remap
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_1 (0xB7030000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_2 (0xB7040000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_3 (0xB7050000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_4 (0xB7060000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA_5 (0xB7070000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_MRSG_1 (0xB7120000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xB7410000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_NADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_NADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_NADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_NADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_NADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_NADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_NADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_NADDR_MDPERI_CORE2_MEM_CONFIG (0xB01DA000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_NADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_NADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_NADDR_MML2_MMU (0xB0603000)
+#define BASE_NADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_NADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_NADDR_MML2_LHIF (0xB0606000)
+#define BASE_NADDR_MML2_CIPHER (0xB0607000)
+#define BASE_NADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_NADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_NADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_NADDR_MML2_CFG (0xB060B000)
+#define BASE_NADDR_MML2_BYC (0xB060C000)
+#define BASE_NADDR_MML2_CFG_SRAM (0xB060D000)
+#define BASE_NADDR_MML2_RDMA_SRAM_L (0xB060E000)
+#define BASE_NADDR_MML2_RDMA_SRAM_H (0xB060F000)
+#define BASE_NADDR_MML2_DLCH_QP_APB (0xB0610000)
+#define BASE_NADDR_MML2_DLCH_RDMA (0xB0611000)
+#define BASE_NADDR_MML2_DLCH_CIPHER (0xB0612000)
+#define BASE_NADDR_MML2_IPF_UL (0xB0614000)
+#define BASE_NADDR_MML2_IPF_DL (0xB0615000)
+#define BASE_NADDR_MML2_IPF_HPCNAT (0xB0616000)
+#define BASE_NADDR_MML2_IPF_PN (0xB0617000)
+#define BASE_NADDR_MML2_ROHC (0xB0618000)
+#define BASE_NADDR_MML2_IPF_SRAM (0xB061D000)
+#define BASE_NADDR_MML2_WDMA_SRAM_L (0xB061E000)
+#define BASE_NADDR_MML2_WDMA_SRAM_H (0xB061F000)
+#define BASE_NADDR_MDINFRA_RESERVED0 (0xB0A10000)
+#define BASE_NADDR_MDINFRA_RESERVED1 (0xB0A20000)
+#define BASE_NADDR_MDINFRA_RESERVED2 (0xB0A40000)
+#define BASE_NADDR_MDINFRA_RESERVED3 (0xB0A50000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_NADDR_USIP_RESERVED0 (0xB1300000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB1400000)
+#define BASE_NADDR_USIP_CONFG (0xB1600000)
+#define BASE_NADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_NADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_NADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_NADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_NADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_NADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_NADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS (0xB6100000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB6110000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xB6120000)
+#define BASE_NADDR_MODEML1_AO_VU_SM_0 (0xB6121000)
+#define BASE_NADDR_MODEML1_AO_VU_SM_1 (0xB6122000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_NADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_NADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB6200000)
+#define BASE_NADDR_MODEML1_AO_C1X_EVENTGEN (0xB6210000)
+#define BASE_NADDR_MODEML1_AO_CDO_EVENTGEN (0xB6220000)
+#define BASE_NADDR_MODEML1_AO_FDD_EVENTGEN (0xB6230000)
+#define BASE_NADDR_MODEML1_AO_LTE_EVENTGEN (0xB6240000)
+#define BASE_NADDR_MODEML1_AO_TDD_EVENTGEN (0xB6250000)
+#define BASE_NADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xB6260000)
+#define BASE_NADDR_MODEML1_AO_MD_BUCK_CTRL (0xB6270000)
+#define BASE_NADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_NADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_NADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_NADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_NADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_NADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_NADDR_BRAM_RESERVED0 (0xBB920000)
+#define BASE_NADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_NADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_NADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_NADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_NADDR_BRAM_RESERVED1 (0xBBA20000)
+#define BASE_NADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_NADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_NADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_NADDR_BRAM_RESERVED2 (0xBBB20000)
+#define BASE_NADDR_BRAM_SCQ1_MBIST_CR (0xBBB30000)
+#define BASE_NADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_NADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_NADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_NADDR_TXSYS_TPC (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_MEM_PM (0xB8200000)
+#define BASE_NADDR_TXSYS_TPC_BUS_INTF (0xB8220800)
+#define BASE_NADDR_TXSYS_TPC_EXTIF (0xB8221000)
+#define BASE_NADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_NADDR_TXSYS_TPC_GCCORE (0xB8224000)
+#define BASE_NADDR_TXSYS_TPC_DMA (0xB8225000)
+#define BASE_NADDR_TXSYS_TPC_MEM_TQ (0xB8226000)
+#define BASE_NADDR_TXSYS_TPC_MEM_DM (0xB8228000)
+#define BASE_NADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_NADDR_TXSYS_TXDFE_BB_2 (0xB8380000)
+#define BASE_NADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_NADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_NADDR_TXSYS_TXET (0xB8400000)
+#define BASE_NADDR_TXSYS_TXET_1 (0xB8420000)
+#define BASE_NADDR_TXSYS_TXK (0xB8440000)
+#define BASE_NADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_NADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_NADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_NADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_NADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_NADDR_TXSYS_AMSC (0xB84A0000)
+#define BASE_NADDR_TXSYS_AMSC_1 (0xB84B0000)
+#define BASE_NADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_NADDR_TXSYS_LTE_TTR_2 (0xB84E0000)
+#define BASE_NADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_NADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_NADDR_TXSYS_TXDFE_BUS_CONFIG (0xB8500000)
+#define BASE_NADDR_CSSYS_CS (0xB7800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB7850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_NADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB7880000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_NADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_NADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBC354000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_NADDR_RAKESYS_PM (0xBC380000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_NADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_NADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_NADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_NADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_NADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_NADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_NADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_NADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_NADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_NADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_NADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_NADDR_BRP_RXBRP_WCT_DMA (0xBD150000)
+#define BASE_NADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_NADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_NADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_NADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_NADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_NADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_NADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_NADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_NADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_NADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_NADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_NADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_NADDR_BRP_RXBRP_L_CBRP_1 (0xBD2A0000)
+#define BASE_NADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_NADDR_BRP_DMC (0xBD300000)
+#define BASE_NADDR_BRP_DMC_PERI (0xBD310000)
+#define BASE_NADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_NADDR_BRP_LTE_CE (0xBD321000)
+#define BASE_NADDR_BRP_LTE_CE_TOP_1 (0xBD322000)
+#define BASE_NADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_NADDR_BRP_DEMOD_TOP_REG (0xBD333000)
+#define BASE_NADDR_BRP_DEMOD (0xBD334000)
+#define BASE_NADDR_BRP_DEMOD_TOP_1 (0xBD335000)
+#define BASE_NADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_NADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_1 (0xB7030000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_2 (0xB7040000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_3 (0xB7050000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_4 (0xB7060000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA_5 (0xB7070000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_MRSG_1 (0xB7120000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM_1 (0xB7410000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS1 (0xB0080000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS2 (0xB0090000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS3 (0xB00A0000)
+#define BASE_ADDR_MDPERI_MD_DBGSYS4 (0xB00B0000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_USIP0_MEM_CONFIG (0xB01D0000)
+#define BASE_ADDR_MDPERI_CORE0_MEM_CONFIG (0xB01D2000)
+#define BASE_ADDR_MDPERI_CORE1_MEM_CONFIG (0xB01D3000)
+#define BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG (0xB01D4000)
+#define BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG (0xB01D5000)
+#define BASE_ADDR_MDPERI_MDMEMSLP_CONFIG (0xB01D6000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG (0xB01D8000)
+#define BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG (0xB01D9000)
+#define BASE_ADDR_MDPERI_CORE2_MEM_CONFIG (0xB01DA000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_MDSMICFG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_MD_INFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MML2_QUEUE_PROCESSOR (0xB0600000)
+#define BASE_ADDR_MML2_METADATA_MANAGER (0xB0601000)
+#define BASE_ADDR_MML2_VRB_MANAGER (0xB0602000)
+#define BASE_ADDR_MML2_MMU (0xB0603000)
+#define BASE_ADDR_MML2_DMA_RD (0xB0604000)
+#define BASE_ADDR_MML2_DMA_WR (0xB0605000)
+#define BASE_ADDR_MML2_LHIF (0xB0606000)
+#define BASE_ADDR_MML2_CIPHER (0xB0607000)
+#define BASE_ADDR_MML2_DL_LMAC (0xB0608000)
+#define BASE_ADDR_MML2_HARQ_CTRL (0xB0609000)
+#define BASE_ADDR_MML2_SRAM_WRAP (0xB060A000)
+#define BASE_ADDR_MML2_CFG (0xB060B000)
+#define BASE_ADDR_MML2_BYC (0xB060C000)
+#define BASE_ADDR_MML2_CFG_SRAM (0xB060D000)
+#define BASE_ADDR_MML2_RDMA_SRAM_L (0xB060E000)
+#define BASE_ADDR_MML2_RDMA_SRAM_H (0xB060F000)
+#define BASE_ADDR_MML2_DLCH_QP_APB (0xB0610000)
+#define BASE_ADDR_MML2_DLCH_RDMA (0xB0611000)
+#define BASE_ADDR_MML2_DLCH_CIPHER (0xB0612000)
+#define BASE_ADDR_MML2_IPF_UL (0xB0614000)
+#define BASE_ADDR_MML2_IPF_DL (0xB0615000)
+#define BASE_ADDR_MML2_IPF_HPCNAT (0xB0616000)
+#define BASE_ADDR_MML2_IPF_PN (0xB0617000)
+#define BASE_ADDR_MML2_ROHC (0xB0618000)
+#define BASE_ADDR_MML2_IPF_SRAM (0xB061D000)
+#define BASE_ADDR_MML2_WDMA_SRAM_L (0xB061E000)
+#define BASE_ADDR_MML2_WDMA_SRAM_H (0xB061F000)
+#define BASE_ADDR_MDINFRA_RESERVED0 (0xB0A10000)
+#define BASE_ADDR_MDINFRA_RESERVED1 (0xB0A20000)
+#define BASE_ADDR_MDINFRA_RESERVED2 (0xB0A40000)
+#define BASE_ADDR_MDINFRA_RESERVED3 (0xB0A50000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB1000000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB1040000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB1080000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB1100000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB1140000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB1180000)
+#define BASE_ADDR_USIP_RESERVED0 (0xB1300000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB1400000)
+#define BASE_ADDR_USIP_CONFG (0xB1600000)
+#define BASE_ADDR_USIP_MBIST_CONFG (0xB1610000)
+#define BASE_ADDR_USIP_DSPLOG (0xB1620000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB1630000)
+#define BASE_ADDR_USIP_MD_AFE (0xB1640000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB1650000)
+//#define BASE_ADDR_USIP_DVFS_CTRL__RESERVED_ (0xB1660000)
+#define BASE_ADDR_USIP_RESERVED1 (0xB1670000)
+#define BASE_ADDR_USIP_RESERVED2 (0xB1680000)
+#define BASE_ADDR_USIP_PERI_RESERVED3 (0xB1700000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_ERR_HANDLE (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB6000000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL (0xB6010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB6020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB6030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB6040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB6050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB6060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB6070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB6080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB6090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB60A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB60B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB60C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB60D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB60E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB60F0000)
+#define BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS (0xB6100000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB6110000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG (0xB6120000)
+#define BASE_ADDR_MODEML1_AO_VU_SM_0 (0xB6121000)
+#define BASE_ADDR_MODEML1_AO_VU_SM_1 (0xB6122000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL (0xB6130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB6140000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_1 (0xB6150000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_2 (0xB6160000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_3 (0xB6170000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB6180000)
+#define BASE_ADDR_MODEML1_AO_ABBMIX_PKR_P2P_TX (0xB6190000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB61A0000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB61B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB61C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB61D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB61E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB61F0000)
+#define BASE_ADDR_MODEML1_AO_RESERVED0 (0xB6200000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB6200000)
+#define BASE_ADDR_MODEML1_AO_C1X_EVENTGEN (0xB6210000)
+#define BASE_ADDR_MODEML1_AO_CDO_EVENTGEN (0xB6220000)
+#define BASE_ADDR_MODEML1_AO_FDD_EVENTGEN (0xB6230000)
+#define BASE_ADDR_MODEML1_AO_LTE_EVENTGEN (0xB6240000)
+#define BASE_ADDR_MODEML1_AO_TDD_EVENTGEN (0xB6250000)
+#define BASE_ADDR_MODEML1_AO_MDMCU_DVFS_CTRL (0xB6260000)
+#define BASE_ADDR_MODEML1_AO_MD_BUCK_CTRL (0xB6270000)
+#define BASE_ADDR_BRAM_BIGRAM_MEM (0xB9000000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_PM (0xB9800000)
+#define BASE_ADDR_BRAM_SCQ_SHARED_DM (0xB9A00000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_PM (0xBA000000)
+#define BASE_ADDR_BRAM_SCQ0_LOCAL_DM (0xBA200000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_PM (0xBA400000)
+#define BASE_ADDR_BRAM_SCQ1_LOCAL_DM (0xBA600000)
+#define BASE_ADDR_BRAM_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_ADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BRAM_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BRAM_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BRAM_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BRAM_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BRAM_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BRAM_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BRAM_SCQ_HW_SCHEDULER (0xBB900000)
+#define BASE_ADDR_BRAM_SCQ_SEMAPHORE (0xBB910000)
+#define BASE_ADDR_BRAM_RESERVED0 (0xBB920000)
+#define BASE_ADDR_BRAM_SCQ_GLOBAL_CON (0xBB930000)
+#define BASE_ADDR_BRAM_SCQ_MBIST_CR (0xBB940000)
+#define BASE_ADDR_BRAM_SCQ0_DSPLOG_1PB (0xBBA00000)
+#define BASE_ADDR_BRAM_SCQ0_VU_CR (0xBBA10000)
+#define BASE_ADDR_BRAM_RESERVED1 (0xBBA20000)
+#define BASE_ADDR_BRAM_SCQ0_MBIST_CR (0xBBA30000)
+#define BASE_ADDR_BRAM_SCQ1_DSPLOG_1PB (0xBBB00000)
+#define BASE_ADDR_BRAM_SCQ1_VU_CR (0xBBB10000)
+#define BASE_ADDR_BRAM_RESERVED2 (0xBBB20000)
+#define BASE_ADDR_BRAM_SCQ1_MBIST_CR (0xBBB30000)
+#define BASE_ADDR_TXSYS_TXBSRP (0xB8000000)
+#define BASE_ADDR_TXSYS_TXCRP (0xB8100000)
+#define BASE_ADDR_TXSYS_TXBRP_BUS_CONFIG (0xB8180000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG0 (0xB8190000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG0 (0xB8198000)
+#define BASE_ADDR_TXSYS_TPC (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_MEM_PM (0xB8200000)
+#define BASE_ADDR_TXSYS_TPC_BUS_INTF (0xB8220800)
+#define BASE_ADDR_TXSYS_TPC_EXTIF (0xB8221000)
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TPC_GCCORE (0xB8224000)
+#define BASE_ADDR_TXSYS_TPC_DMA (0xB8225000)
+#define BASE_ADDR_TXSYS_TPC_MEM_TQ (0xB8226000)
+#define BASE_ADDR_TXSYS_TPC_MEM_DM (0xB8228000)
+#define BASE_ADDR_TXSYS_TXDFE_BB (0xB8300000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_1 (0xB8340000)
+#define BASE_ADDR_TXSYS_TXDFE_BB_2 (0xB8380000)
+#define BASE_ADDR_TXSYS_TXDFE_RF (0xB83C0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_1 (0xB83D0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_2 (0xB83E0000)
+#define BASE_ADDR_TXSYS_TXDFE_RF_3 (0xB83F0000)
+#define BASE_ADDR_TXSYS_TXET (0xB8400000)
+#define BASE_ADDR_TXSYS_TXET_1 (0xB8420000)
+#define BASE_ADDR_TXSYS_TXK (0xB8440000)
+#define BASE_ADDR_TXSYS_TXK_1 (0xB8450000)
+#define BASE_ADDR_TXSYS_TXK_2 (0xB8460000)
+#define BASE_ADDR_TXSYS_TXK_3 (0xB8470000)
+#define BASE_ADDR_TXSYS_FDD_TTR (0xB8480000)
+#define BASE_ADDR_TXSYS_TDD_TTR (0xB8490000)
+#define BASE_ADDR_TXSYS_AMSC (0xB84A0000)
+#define BASE_ADDR_TXSYS_AMSC_1 (0xB84B0000)
+#define BASE_ADDR_TXSYS_LTE_TTR (0xB84C0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_1 (0xB84D0000)
+#define BASE_ADDR_TXSYS_LTE_TTR_2 (0xB84E0000)
+#define BASE_ADDR_TXSYS_GLB_CON_CONFIG1 (0xB84F0000)
+#define BASE_ADDR_TXSYS_MBIST_CONFIG1 (0xB84F8000)
+#define BASE_ADDR_TXSYS_TXDFE_BUS_CONFIG (0xB8500000)
+#define BASE_ADDR_CSSYS_CS (0xB7800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB7810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB7820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB7830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB7840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB7850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB7860000)
+#define BASE_ADDR_CSSYS_CS_WT_1 (0xB7870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB7880000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB6800000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB6900000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB6A00000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB6C00000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB6F00000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB6F10000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB6F20000)
+#define BASE_ADDR_MD2GSYS_APC (0xB6F30000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB6F40000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB6F70000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB6FA0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB6FB0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB6FC0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB6FE0000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBC000000)
+#define BASE_ADDR_RAKESYS_RAKE_QLIC (0xBC010000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBC020000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBC030000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBC040000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBC050000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBC060000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBC070000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBC080000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBC090000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBC0A0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBC0F0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBC100000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBC110000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBC200000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBC210000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBC300000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBC340000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBC350000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBC351000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBC354000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBC358000)
+#define BASE_ADDR_RAKESYS_PM (0xBC380000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBC390000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_1 (0xBC3A0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_2 (0xBC3B0000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB_3 (0xBC3C0000)
+#define BASE_ADDR_RAKESYS_DM (0xBC3D0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBC3E0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB_1 (0xBC3F0000)
+#define BASE_ADDR_BRP_RXBRP_MBIST_CONFIG (0xBD000000)
+#define BASE_ADDR_BRP_DMC_MBIST (0xBD010000)
+#define BASE_ADDR_BRP_RXBRP_W_DRM (0xBD020000)
+#define BASE_ADDR_BRP_RXBRP_W_R99_WRAP (0xBD030000)
+#define BASE_ADDR_BRP_RXBRP_C_1XRTT (0xBD040000)
+#define BASE_ADDR_BRP_RXBRP_C_CORR_SER (0xBD050000)
+#define BASE_ADDR_BRP_RXBRP_WT_BCH (0xBD060000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DVIT (0xBD070000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TRACE (0xBD100000)
+#define BASE_ADDR_BRP_RXBRP_GLOBAL_CON (0xBD110000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_TUR (0xBD120000)
+#define BASE_ADDR_BRP_RXBRP_WTL_CVIT (0xBD130000)
+#define BASE_ADDR_BRP_RXBRP_WTL_HARQ_BUF (0xBD140000)
+#define BASE_ADDR_BRP_RXBRP_WCT_DMA (0xBD150000)
+#define BASE_ADDR_BRP_RXBRP_BUS_CONFIG (0xBD160000)
+#define BASE_ADDR_BRP_RXBRP_WT_HARQ (0xBD170000)
+#define BASE_ADDR_BRP_RXBRP_WT_CDRM (0xBD180000)
+#define BASE_ADDR_BRP_RXBRP_W_CORR (0xBD200000)
+#define BASE_ADDR_BRP_RXBRP_W_TXIF (0xBD210000)
+#define BASE_ADDR_BRP_RXBRP_W_HSRM (0xBD220000)
+#define BASE_ADDR_BRP_RXBRP_C_EVDO (0xBD230000)
+#define BASE_ADDR_BRP_RXBRP_L_DBRP (0xBD240000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP (0xBD250000)
+#define BASE_ADDR_BRP_RXBRP_L_HARQ (0xBD260000)
+#define BASE_ADDR_BRP_RXBRP_L_REBRP (0xBD270000)
+#define BASE_ADDR_BRP_RXBRP_L_RBMAP (0xBD280000)
+#define BASE_ADDR_BRP_RXBRP_L_DCI_PARSER (0xBD290000)
+#define BASE_ADDR_BRP_RXBRP_L_CBRP_1 (0xBD2A0000)
+#define BASE_ADDR_BRP_RXBRP_WCTL_ECTRL (0xBD2B0000)
+#define BASE_ADDR_BRP_DMC (0xBD300000)
+#define BASE_ADDR_BRP_DMC_PERI (0xBD310000)
+#define BASE_ADDR_BRP_DMC_LTE_CE (0xBD320000)
+#define BASE_ADDR_BRP_LTE_CE (0xBD321000)
+#define BASE_ADDR_BRP_LTE_CE_TOP_1 (0xBD322000)
+#define BASE_ADDR_BRP_DMC_DEMOD (0xBD330000)
+#define BASE_ADDR_BRP_DEMOD_TOP_REG (0xBD333000)
+#define BASE_ADDR_BRP_DEMOD (0xBD334000)
+#define BASE_ADDR_BRP_DEMOD_TOP_1 (0xBD335000)
+#define BASE_ADDR_BRP_DMC_MIMO (0xBD340000)
+#define BASE_ADDR_BRP_DMC_PWR_MEAS (0xBD350000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6295_MemoryMap.xls
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_LSRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MD_DBGSYS1
+#define BASE_MADDR_DBGSYS_2 BASE_MADDR_MDPERI_MD_DBGSYS2
+#define BASE_MADDR_DBGSYS_3 BASE_MADDR_MDPERI_MD_DBGSYS3
+#define BASE_MADDR_DBGSYS_4 BASE_MADDR_MDPERI_MD_DBGSYS4
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_MML2_METADATA_MANAGER
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG
+#define BASE_MADDR_FCS BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_GCU BASE_MADDR_MDINFRA_RESERVED1
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED2
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED3
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_TXSYS_TXBSRP
+#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_NADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_NADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_NADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_NADDR_FCS BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_NADDR_GCU BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_NADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED2
+#define BASE_NADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED3
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_TXSYS_TXBSRP
+#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_DBGSYS_1 BASE_NADDR_MDPERI_MD_DBGSYS1
+#define BASE_ADDR_DBGSYS_2 BASE_NADDR_MDPERI_MD_DBGSYS2
+#define BASE_ADDR_DBGSYS_3 BASE_NADDR_MDPERI_MD_DBGSYS3
+#define BASE_ADDR_DBGSYS_4 BASE_NADDR_MDPERI_MD_DBGSYS4
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_MML2_METADATA_MANAGER
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_MML2_CFG
+#define BASE_ADDR_FCS BASE_NADDR_MDINFRA_RESERVED0
+#define BASE_ADDR_GCU BASE_NADDR_MDINFRA_RESERVED1
+#define BASE_ADDR_UEA_UIA_1 BASE_NADDR_MDINFRA_RESERVED2
+#define BASE_ADDR_UEA_UIA_0 BASE_NADDR_MDINFRA_RESERVED3
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_TXSYS_TXBSRP
+#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_MADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_MADDR_ABB_MIXEDSYS BASE_MADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_TXSYS_TXBSRP
+#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_NADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_NADDR_ABB_MIXEDSYS BASE_NADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_TXSYS_TXBSRP
+#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define BASE_ADDR_MODEML1_AO_WCT_P2P_TX_PARALLEL BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_ADDR_ABB_MIXEDSYS BASE_ADDR_MODEML1_AO_ABB_MIXEDSYS
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_TXSYS_TXBSRP
+#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+#define BASE_MADDR_MML2_QP_MEM (0xA0600800)
+#define BASE_NADDR_MML2_QP_MEM (0xB0600800)
+#define BASE_ADDR_MML2_QP_MEM (0xB0600800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA0601800)
+#define BASE_NADDR_MML2_META_MEM (0xB0601800)
+#define BASE_ADDR_MML2_META_MEM (0xB0601800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_BSI_MM_3
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_BSI_MM_3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_BSI_MM_2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_BSI_MM_2
+
+#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6779_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_MT6779_username.h b/mcu/interface/driver/regbase/md95/reg_base_MT6779_username.h
new file mode 100644
index 0000000..0a348f5
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_MT6779_username.h
@@ -0,0 +1,165 @@
+#ifndef __REG_BASE_MT6779_USERNAME_H__
+#define __REG_BASE_MT6779_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+/* Please add your register by yourself, EX:
+
+// WCS/SSE/SS2 owner
+#define BASE_XXXX_XXXXXXXX (0xXXXXXXXX)
+
+*/
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+#define BASE_NADDR_APMCU_MISC (0xD000D000)
+#define BASE_ADDR_APMCU_MISC (0xD000D000)
+
+//WSP/SE7/SD6 Alva Li
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+
+// SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+//#define BASE_MADDR_AO_SEJ (BASE_MADDR_SEJ)
+//End of AP registers
+
+// SSE/SS3 I-Chun Liu
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+
+// WSP/RSD/DSD Tony Yuan
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+
+/****************************
+* MD registers *
+*****************************/
+/* Please add your register by yourself, EX:
+
+// WCS/SSE/SS2 owner
+#define BASE_XXXX_XXXXXXXX (0xXXXXXXXX)
+
+*/
+
+// MCD/WSP/SE7/SD9 Gang Lei
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+
+//WCS/SD/SP3 Johnason Lee
+#define AMSC_REG_BASE (0xB3700000)
+#define AMSC_TQ_SRAM_REG_BASE (0xB84A8000)
+
+// WCS/SE2/CS15 Leon Yeh
+#define MODEM_TOPSM_base (L1_BASE_MADDR_MODEM_TOPSM)
+#define TDMA_SLP_base (L1_BASE_MADDR_TDMA_SLP)
+#define FDD_SLP_base (L1_BASE_MADDR_FDD_SLP)
+#define LTE_SLP_base (L1_BASE_MADDR_LTE_SLP)
+
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC0007000)
+#define BASE_NADDR_APRGU (0xD0007000)
+#define BASE_ADDR_APRGU (0xD0007000)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+#define UART3_base (BASE_MADDR_MDUART2)
+
+// WSD/OSS8/ME9 Thomas Chen
+#define AFE_BASE (0xA1640000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA6FA0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA1600000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000) //For BT
+
+
+// WSP/SE7/SD3 Ansel Liao
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+//WCS/SSE/SS3 I-Chun Liu
+#define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/MSP/MSP7 Tzu-Han Hsu
+#define PATCH_base (0xA6FC0000)
+#define SHAREG2_base (BASE_MADDR_MD2GSYS_SHARE_D1) //(L1_BASE_MADDR_SHARE_D1) //the same as L1_BASE_MADDR_SHARE_D1
+#define DPRAM_CPU_base (BASE_MADDR_MD2GSYS_IDMA_DM) //(L1_BASE_MADDR_DM_IDMA) //FIXIT: the same as L1_BASE_MADDR_DM_IDMA
+#define IDMA_base (BASE_MADDR_MD2GSYS_IDMA_CM) //(L1_BASE_MADDR_CM_IDMA) //FIXIT: the same as L1_BASE_MADDR_CM_IDMA
+
+//WCS/MDD/DE3 Vesa Savela
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// WCS/SSE/SS3 Chia-Fu Lee
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+// WCS/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_SPM (0xC0006000)
+
+// WSP/SE7/SD10 Che-Wei Chang, for Wall Clock
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+// WSP/SE7/SD10 Guo-Huei Chang, for VMODEM & MD_SRAM SW workaround
+#define BASE_INFRA_AO_SLEEP_CONTROLER (0xC0006000)
+
+// WSP/SE7/SD3 Hsin-Hao Huang, for DPMAIF
+#define BASE_AP_DPMAIF_TOP_MD (0xC022C000)
+#define BASE_AP_DPMAIF_PD_BASE (0xC022D000)
+
+//WCS/SE2/BSD Tom-CT Wu temp for EMI bus hang
+#define BASE_RXDFE_MODEM_TEMP (0xA7000000)
+#define BASE_CS_MODEM_TEMP (0xA7830000)
+#define BASE_ML1AO_BUS_MODEM_TEMP (0xA61C0000)
+#define BASE_TXSBRP_MAS_BUS0_MODEM_TEMP (0xA8180000)
+#define BASE_TXSBRP_MAS_BUS1_MODEM_TEMP (0xA8500000)
+
+//End of MD registers
+#endif /* end of __REG_BASE_MT6779_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md95/reg_base_md95.h b/mcu/interface/driver/regbase/md95/reg_base_md95.h
new file mode 100644
index 0000000..05c6ed0
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_md95.h
@@ -0,0 +1,103 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * reg_base_md95.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for chipset register base and global configuration registers
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _REG_BASE_MD95_H
+#define _REG_BASE_MD95_H
+
+#if defined(MT6295M)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MT6295M_FPGA.h"
+ #else
+ #error "unknown MDMCU version"//#include "reg_base_MT6295M.h"
+ #endif /*__FPGA__*/
+#elif defined(MT3967)/* 95 E1 */
+ #include "reg_base_MT3967.h"
+#elif defined(MT6779)/* 95 E2 */
+ #include "reg_base_MT6779.h"
+#else
+ #error "unknown MDMCU version"
+#endif
+
+#endif /* !_REG_BASE_MD95_H */
+
diff --git a/mcu/interface/driver/regbase/md95/reg_base_username_md95.h b/mcu/interface/driver/regbase/md95/reg_base_username_md95.h
new file mode 100644
index 0000000..8f85636
--- /dev/null
+++ b/mcu/interface/driver/regbase/md95/reg_base_username_md95.h
@@ -0,0 +1,21 @@
+#ifndef __REG_BASE_USERNAME_MD95_H__
+#define __REG_BASE_USERNAME_MD95_H__
+
+/* This header file only includes product specific header files.
+ * Please add your reg base difinitions to correct product specific file. */
+
+#if defined(MT6295M)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MT6295M_FPGA_username.h"
+ #else/* not FPGA */
+ #include "reg_base_MT6295M_username.h"
+ #endif
+#elif defined(MT3967)/* 95 E1 */
+ #include "reg_base_MT3967_username.h"
+#elif defined(MT6779)/* 95 E2 */
+ #include "reg_base_MT6779_username.h"
+#else
+ #error "unknown MDMCU version"
+#endif
+
+#endif /* end of __REG_BASE_USERNAME_MD95_H__ */
diff --git a/mcu/interface/driver/regbase/md97/cpu_info_MT6297_I7200.h b/mcu/interface/driver/regbase/md97/cpu_info_MT6297_I7200.h
new file mode 100644
index 0000000..f75b4d6
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/cpu_info_MT6297_I7200.h
@@ -0,0 +1,20 @@
+#ifndef __CPU_INFO_MT6297_H__
+#define __CPU_INFO_MT6297_H__
+
+#if defined(__MD97_IS_2CORES__)
+
+#define SYS_MCU_NUM_CORE (2)
+#define SYS_MCU_NUM_VPE (6)
+#define SYS_MCU_NUM_TC (12)
+
+#else
+
+#define SYS_MCU_NUM_CORE (4)
+#define SYS_MCU_NUM_VPE (12)
+#define SYS_MCU_NUM_TC (24)
+
+#endif
+
+#define SYS_MCU_GIC_EXIST (0)
+
+#endif /* __CPU_INFO_MT6297_H__ */
diff --git a/mcu/interface/driver/regbase/md97/cpu_info_MT6297_IA.h b/mcu/interface/driver/regbase/md97/cpu_info_MT6297_IA.h
new file mode 100644
index 0000000..ad0495e
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/cpu_info_MT6297_IA.h
@@ -0,0 +1,11 @@
+#ifndef __CPU_INFO_MT6297_H__
+#define __CPU_INFO_MT6297_H__
+
+#define SYS_MCU_NUM_CORE (4)
+#define SYS_MCU_NUM_VPE (8)
+#define SYS_MCU_NUM_TC (24)
+
+#define SYS_MCU_GIC_EXIST (0)
+
+#endif /* __CPU_INFO_MT6297_H__ */
+
diff --git a/mcu/interface/driver/regbase/md97/cpu_info_md97.h b/mcu/interface/driver/regbase/md97/cpu_info_md97.h
new file mode 100644
index 0000000..4bfbe21
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/cpu_info_md97.h
@@ -0,0 +1,14 @@
+#ifndef __CPU_INFO_MD97_H__
+#define __CPU_INFO_MD97_H__
+
+#if defined(MT6297) || defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ #if defined(MT6297_IA)
+ #include "cpu_info_MT6297_IA.h"
+ #else
+ #include "cpu_info_MT6297_I7200.h"
+ #endif
+#else
+ #error "unknown MDMCU version"
+#endif
+
+#endif /* __CPU_INFO_MD97_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_CHIP10992.h b/mcu/interface/driver/regbase/md97/reg_base_CHIP10992.h
new file mode 100644
index 0000000..89bc68c
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_CHIP10992.h
@@ -0,0 +1,2883 @@
+#ifndef __REG_BASE_CHIP10992_H__
+#define __REG_BASE_CHIP10992_H__
+
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_CHIP10992_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_CHIP10992_username.h b/mcu/interface/driver/regbase/md97/reg_base_CHIP10992_username.h
new file mode 100644
index 0000000..9a9b3fb
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_CHIP10992_username.h
@@ -0,0 +1,197 @@
+#ifndef __REG_BASE_CHIP10992_USERNAME_H__
+#define __REG_BASE_CHIP10992_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/MPE2/SD15 Flamingo Wang
+#define CLDMA0_MD_BASE (0xC021E000)
+#define CLDMA0_AP_BASE (0xC021D000)
+#define CLDMA1_MD_BASE (0xC0220000)
+#define CLDMA1_AP_BASE (0xC021F000)
+#define CLDMA0_AO_MD_BASE (0xC004A000)
+#define CLDMA0_AO_AP_BASE (0xC0049000)
+#define CLDMA1_AO_MD_BASE (0xC004C000)
+#define CLDMA1_AO_AP_BASE (0xC004B000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1EC0000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+#define BASE_MADDR_PCCIF5_AP (0xC025C000)
+#define BASE_MADDR_PCCIF5_MD (0xC025D000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Jeter Chen
+#define PMIF_SPMI_BASE (0xC0026000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+#define PMIF_SPMI_P_BASE (0xC0027000)
+#define SPMI_MST_P_BASE (0xC0028000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+#define BASE_INFRA_AO_AP2MD_APMCU_STATUS_IRQ_CLEAR (0xC0001BCC)
+#define BASE_INFRA_AO_AP2MD_APMCU_CURRENT_STATUS (0xC0001BD0)
+
+//WSP/MPE2/SD3 Cindy Tu
+#define BASE_PCIE_MAC (0xC1280000)
+#define BASE_PCIE_PHY (0xC1E40000)
+#define BASE_SPM (0xC0006000)
+
+//WSP/MPE2/SD3 Cody Lee
+#define BASE_INFRA_AO_SLEEP_CTRL (0xC0006000)
+#define BASE_INFRA_AO_TOPRGU (0xC0007000)
+
+//WSP/MPE2/SD3 Bernie Chang
+#define BASE_MHCCIF_RC (0xC0024000)
+#define BASE_MHCCIF_EP (0xC0025000)
+
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E30000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E30000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E30000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_CHIP10992_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6297.h b/mcu/interface/driver/regbase/md97/reg_base_MT6297.h
new file mode 100644
index 0000000..7c9eda5
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6297.h
@@ -0,0 +1,3003 @@
+#ifndef __REG_BASE_MT6297_H__
+#define __REG_BASE_MT6297_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6297_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM_A (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_IA_BTSLV (0x9FF00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MCUSYS_MBIST_CONFIG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_SEMAPHORE (0xA405C400)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+#define BASE_MADDR_MCORE1_CBSCHEDULER (0xA445C000)
+#define BASE_MADDR_MCORE1_SEMAPHORE (0xA445C400)
+#define BASE_MADDR_MCORE1_EINTC (0xA445C800)
+#define BASE_MADDR_MCORE1_CLK_CTRL (0xA44A0040)
+#define BASE_MADDR_MCORE1_DSPRSTCTRL (0xA44A0100)
+#define BASE_MADDR_MCORE1_MML1_DSPRSTCTRL (0xA44A0140)
+#define BASE_MADDR_MCORE1_MC1_DSPRSTCTRL2 (0xA44A0180)
+#define BASE_MADDR_MCORE1_MC1_DSPRSTCTRL3 (0xA44A01C0)
+#define BASE_MADDR_MCORE1_D2D (0xA44A1800)
+#define BASE_MADDR_MCORE1_PMU (0xA44A1C00)
+#define BASE_MADDR_MCORE1_L0_I__CONFIG (0xA44C0000)
+#define BASE_MADDR_MCORE1_MML1_DSPSIL0C_TOP_1 (0xA44C1000)
+#define BASE_MADDR_MCORE1_MML1_DSPSIL0C_TOP_2 (0xA44C2000)
+#define BASE_MADDR_MCORE1_MML1_DSPSIL0C_TOP_3 (0xA44C3000)
+#define BASE_MADDR_MCORE1_L1_I__CONFIG (0xA44C4000)
+#define BASE_MADDR_MCORE1_DBUS_CFG (0xA44C5000)
+#define BASE_MADDR_MCORE1_DEBUG_FLAG_MON (0xA44C6000)
+#define BASE_MADDR_MCORE1_MISC (0xA44C6400)
+#define BASE_MADDR_MCORE1_DSPLOG (0xA44C6800)
+#define BASE_MADDR_MCORE1_SMT_CTI (0xA44C6C00)
+#define BASE_MADDR_MCORE1_BUS_RECORDER (0xA44C7000)
+#define BASE_MADDR_MCORE1_DBGC (0xA44C7800)
+#define BASE_MADDR_MCORE1_L1_D__CFG (0xA44C8000)
+#define BASE_MADDR_MCORE1_L0_D__CONFIG (0xA44CA000)
+#define BASE_MADDR_MCORE1_DATA_CACHE_1 (0xA44CA100)
+#define BASE_MADDR_MCORE1_DATA_CACHE_2 (0xA44CA200)
+#define BASE_MADDR_MCORE1_DATA_CACHE_3 (0xA44CA300)
+#define BASE_MADDR_MCORE1_DSP_TIMER0 (0xA44CA400)
+#define BASE_MADDR_MCORE1_DSP_TIMER1 (0xA44CA410)
+#define BASE_MADDR_MCORE1_DSP_TIMER2 (0xA44CA420)
+#define BASE_MADDR_MCORE1_DSP_TIMER3 (0xA44CA430)
+#define BASE_MADDR_MCORE1_MBIST_CFG (0xA44CB000)
+#define BASE_MADDR_MCORE1_DELSEL_CFG (0xA44CB400)
+#define BASE_MADDR_MCORE1_REPAIR_CFG (0xA44CB800)
+#define BASE_MADDR_MCORE1_MCCKCTL (0xA44CBC00)
+#define BASE_MADDR_MCORE1_THREAD0_LOCAL_ICM (0xA4500000)
+#define BASE_MADDR_MCORE1_THREAD1_LOCAL_ICM (0xA4520000)
+#define BASE_MADDR_MCORE1_THREAD2_LOCAL_ICM (0xA4540000)
+#define BASE_MADDR_MCORE1_THREAD3_LOCAL_ICM (0xA4560000)
+#define BASE_MADDR_MCORE1_THREAD0_CORE_CR (0xA4580000)
+#define BASE_MADDR_MCORE1_MML1_DSPMCORE_TOP_CORE_SMT (0xA4590000)
+#define BASE_MADDR_MCORE1_THREAD1_CORE_CR (0xA45A0000)
+#define BASE_MADDR_MCORE1_THREAD2_CORE_CR (0xA45B0000)
+#define BASE_MADDR_MCORE1_THREAD3_CORE_CR (0xA45C0000)
+#define BASE_MADDR_MCORE1_L1_I_TCM (0xA45E0000)
+#define BASE_MADDR_MCORE1_MSP_DBGMEM (0xA4600000)
+#define BASE_MADDR_MCORE1_L1_D__TCM (0xA4780000)
+#define BASE_MADDR_MCORE1_MML1_DSPSDL1C (0xA47C0000)
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH3_L1MC__CR (0xA5053000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_TH3_BLAZE (0xA5057000)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_TH3_L1MC__MEM (0xA5090000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSL2C (0xA4C00000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER1 (0xA4C20000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1 (0xA4CA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_AO_SRAM (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4D80000)
+#define BASE_MADDR_MCOREPERI_INFRA_RSTCTRL (0xA4D88000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4D90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MBIST_CFG (0xA4D98000)
+#define BASE_MADDR_MCOREPERI_INFRA_BUS_CR (0xA4DA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4DA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA4DB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA4DB0400)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO (0xA4DB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO (0xA4DC0000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO (0xA4DC8000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4DD8000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_GLBCON (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_RSTCTRL (0xA4E88000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_DBGMON_WRAP (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_MBIST_CONFIG (0xA4E98000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_DELSEL_CFG_WRAP (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_ABUSMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_ELM (0xA4F20000)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA4DD0000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA4DD0400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA4DD0600)
+#define BASE_MADDR_VCORESIL2CSYS_DSPSL2C (0xA5C00000)
+#define BASE_MADDR_VCORESIL2CSYS_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCORESIL2CSYS_ABUS_CR (0xA5C20000)
+#define BASE_MADDR_VCORESIL2CSYS_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCORESIL2CSYS_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCORESIL2CSYS_RSTCTRL (0xA5C90000)
+#define BASE_MADDR_VCORESIL2CSYS_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCORESIL2CSYS_MBIST_CFG (0xA5CB0000)
+#define BASE_MADDR_VCORESIL2CSYS_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCORESIL2CSYS_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCORESIL2CSYS_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCSI_NR_HGRX (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_MBIST_CFG_WRAP (0xA6F10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RSTCTL (0xA6F18000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_BUSRECORDER1_MCORESYS_BUSRECORDER1 (0xA0645800)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA0649800)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A000)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064A400)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064A440)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064A480)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064A4C0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064A500)
+#define BASE_MADDR_MCORE1_CORE_MCORE1_CORE (0xA064C000)
+#define BASE_MADDR_MCORE1_DBUS_MCORE1_DBUS (0xA064D000)
+#define BASE_MADDR_MCORE1_PMU_MCORE1_PMU (0xA064D800)
+#define BASE_MADDR_MCORE1_BUS_RECORDER_MCORE1_BUS_RECORDER (0xA064E000)
+#define BASE_MADDR_MCORE1_CONFIG_TH0____________MCORE1_CONFIG_TH0 (0xA064E400)
+#define BASE_MADDR_MCORE1_CONFIG_TH1____________MCORE1_CONFIG_TH1 (0xA064E440)
+#define BASE_MADDR_MCORE1_CONFIG_TH2____________MCORE1_CONFIG_TH2 (0xA064E480)
+#define BASE_MADDR_MCORE1_CONFIG_TH3____________MCORE1_CONFIG_TH3 (0xA064E4C0)
+#define BASE_MADDR_MCORE1_DEBUG_FLAG_MON_MCORE1_DEBUG_FLAG_MON (0xA064E500)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0651800)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652000)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652400)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652440)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652480)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA06524C0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652500)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_VCOREHRAM_AO_DBGMON_VCOREHRAM_AO_DBGMON (0xA0653800)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_PERICK_ABUS_SIL2CSYS_PERICK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PERICK_DBUS_SIL2CSYS_PERICK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RESERVED2 (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_MBIST_CFG_WRAP (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_MBIST_CONFIG (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MCOREPERI_INFRA (0xA4DB8000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_CONFIG0 (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_CONFIG1 (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_CORE (0xA9420000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_CORE_1 (0xA9430000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_CONFIG (0xA9C50000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP_1 (0xAA003000)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_MBIST_CFG_WRAP (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_EMPTY1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_MBIST_CFG (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR_INNER (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_PBCH (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_DEBUG_CR (0xAAC70000)
+// (30): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_CONFIG (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (31): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABC13000)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC14000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_4 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (32): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (33): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_A_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM_A (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MCUSYS_MBIST_CONFIG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_SEMAPHORE (0xB405C400)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_MCORE1_CBSCHEDULER (0xB445C000)
+#define BASE_NADDR_MCORE1_SEMAPHORE (0xB445C400)
+#define BASE_NADDR_MCORE1_EINTC (0xB445C800)
+#define BASE_NADDR_MCORE1_CLK_CTRL (0xB44A0040)
+#define BASE_NADDR_MCORE1_DSPRSTCTRL (0xB44A0100)
+#define BASE_NADDR_MCORE1_MML1_DSPRSTCTRL (0xB44A0140)
+#define BASE_NADDR_MCORE1_MC1_DSPRSTCTRL2 (0xB44A0180)
+#define BASE_NADDR_MCORE1_MC1_DSPRSTCTRL3 (0xB44A01C0)
+#define BASE_NADDR_MCORE1_D2D (0xB44A1800)
+#define BASE_NADDR_MCORE1_PMU (0xB44A1C00)
+#define BASE_NADDR_MCORE1_L0_I__CONFIG (0xB44C0000)
+#define BASE_NADDR_MCORE1_MML1_DSPSIL0C_TOP_1 (0xB44C1000)
+#define BASE_NADDR_MCORE1_MML1_DSPSIL0C_TOP_2 (0xB44C2000)
+#define BASE_NADDR_MCORE1_MML1_DSPSIL0C_TOP_3 (0xB44C3000)
+#define BASE_NADDR_MCORE1_L1_I__CONFIG (0xB44C4000)
+#define BASE_NADDR_MCORE1_DBUS_CFG (0xB44C5000)
+#define BASE_NADDR_MCORE1_DEBUG_FLAG_MON (0xB44C6000)
+#define BASE_NADDR_MCORE1_MISC (0xB44C6400)
+#define BASE_NADDR_MCORE1_DSPLOG (0xB44C6800)
+#define BASE_NADDR_MCORE1_SMT_CTI (0xB44C6C00)
+#define BASE_NADDR_MCORE1_BUS_RECORDER (0xB44C7000)
+#define BASE_NADDR_MCORE1_DBGC (0xB44C7800)
+#define BASE_NADDR_MCORE1_L1_D__CFG (0xB44C8000)
+#define BASE_NADDR_MCORE1_L0_D__CONFIG (0xB44CA000)
+#define BASE_NADDR_MCORE1_DATA_CACHE_1 (0xB44CA100)
+#define BASE_NADDR_MCORE1_DATA_CACHE_2 (0xB44CA200)
+#define BASE_NADDR_MCORE1_DATA_CACHE_3 (0xB44CA300)
+#define BASE_NADDR_MCORE1_DSP_TIMER0 (0xB44CA400)
+#define BASE_NADDR_MCORE1_DSP_TIMER1 (0xB44CA410)
+#define BASE_NADDR_MCORE1_DSP_TIMER2 (0xB44CA420)
+#define BASE_NADDR_MCORE1_DSP_TIMER3 (0xB44CA430)
+#define BASE_NADDR_MCORE1_MBIST_CFG (0xB44CB000)
+#define BASE_NADDR_MCORE1_DELSEL_CFG (0xB44CB400)
+#define BASE_NADDR_MCORE1_REPAIR_CFG (0xB44CB800)
+#define BASE_NADDR_MCORE1_MCCKCTL (0xB44CBC00)
+#define BASE_NADDR_MCORE1_THREAD0_LOCAL_ICM (0xB4500000)
+#define BASE_NADDR_MCORE1_THREAD1_LOCAL_ICM (0xB4520000)
+#define BASE_NADDR_MCORE1_THREAD2_LOCAL_ICM (0xB4540000)
+#define BASE_NADDR_MCORE1_THREAD3_LOCAL_ICM (0xB4560000)
+#define BASE_NADDR_MCORE1_THREAD0_CORE_CR (0xB4580000)
+#define BASE_NADDR_MCORE1_MML1_DSPMCORE_TOP_CORE_SMT (0xB4590000)
+#define BASE_NADDR_MCORE1_THREAD1_CORE_CR (0xB45A0000)
+#define BASE_NADDR_MCORE1_THREAD2_CORE_CR (0xB45B0000)
+#define BASE_NADDR_MCORE1_THREAD3_CORE_CR (0xB45C0000)
+#define BASE_NADDR_MCORE1_L1_I_TCM (0xB45E0000)
+#define BASE_NADDR_MCORE1_MSP_DBGMEM (0xB4600000)
+#define BASE_NADDR_MCORE1_L1_D__TCM (0xB4780000)
+#define BASE_NADDR_MCORE1_MML1_DSPSDL1C (0xB47C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH3_L1MC__CR (0xB5053000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_TH3_BLAZE (0xB5057000)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_TH3_L1MC__MEM (0xB5090000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSL2C (0xB4C00000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER1 (0xB4C20000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1 (0xB4CA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_AO_SRAM (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4D80000)
+#define BASE_NADDR_MCOREPERI_INFRA_RSTCTRL (0xB4D88000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4D90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MBIST_CFG (0xB4D98000)
+#define BASE_NADDR_MCOREPERI_INFRA_BUS_CR (0xB4DA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4DA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB4DB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB4DB0400)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO (0xB4DB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO (0xB4DC0000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO (0xB4DC8000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4DD8000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_GLBCON (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_RSTCTRL (0xB4E88000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_DBGMON_WRAP (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_MBIST_CONFIG (0xB4E98000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_DELSEL_CFG_WRAP (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_ABUSMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_ELM (0xB4F20000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB4DD0000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB4DD0400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB4DD0600)
+#define BASE_NADDR_VCORESIL2CSYS_DSPSL2C (0xB5C00000)
+#define BASE_NADDR_VCORESIL2CSYS_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCORESIL2CSYS_ABUS_CR (0xB5C20000)
+#define BASE_NADDR_VCORESIL2CSYS_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCORESIL2CSYS_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCORESIL2CSYS_RSTCTRL (0xB5C90000)
+#define BASE_NADDR_VCORESIL2CSYS_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCORESIL2CSYS_MBIST_CFG (0xB5CB0000)
+#define BASE_NADDR_VCORESIL2CSYS_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCORESIL2CSYS_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCORESIL2CSYS_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCSI_NR_HGRX (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_MBIST_CFG_WRAP (0xB6F10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RSTCTL (0xB6F18000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_BUSRECORDER1_MCORESYS_BUSRECORDER1 (0xB0645800)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB0649800)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A000)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064A400)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064A440)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064A480)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064A4C0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064A500)
+#define BASE_NADDR_MCORE1_CORE_MCORE1_CORE (0xB064C000)
+#define BASE_NADDR_MCORE1_DBUS_MCORE1_DBUS (0xB064D000)
+#define BASE_NADDR_MCORE1_PMU_MCORE1_PMU (0xB064D800)
+#define BASE_NADDR_MCORE1_BUS_RECORDER_MCORE1_BUS_RECORDER (0xB064E000)
+#define BASE_NADDR_MCORE1_CONFIG_TH0____________MCORE1_CONFIG_TH0 (0xB064E400)
+#define BASE_NADDR_MCORE1_CONFIG_TH1____________MCORE1_CONFIG_TH1 (0xB064E440)
+#define BASE_NADDR_MCORE1_CONFIG_TH2____________MCORE1_CONFIG_TH2 (0xB064E480)
+#define BASE_NADDR_MCORE1_CONFIG_TH3____________MCORE1_CONFIG_TH3 (0xB064E4C0)
+#define BASE_NADDR_MCORE1_DEBUG_FLAG_MON_MCORE1_DEBUG_FLAG_MON (0xB064E500)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0651800)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652000)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652400)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652440)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652480)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB06524C0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652500)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_VCOREHRAM_AO_DBGMON_VCOREHRAM_AO_DBGMON (0xB0653800)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_PERICK_ABUS_SIL2CSYS_PERICK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PERICK_DBUS_SIL2CSYS_PERICK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RESERVED2 (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_MBIST_CFG_WRAP (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_MBIST_CONFIG (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MCOREPERI_INFRA (0xB4DB8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_CONFIG0 (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_CONFIG1 (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_CORE (0xB9420000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_CORE_1 (0xB9430000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_CONFIG (0xB9C50000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP_1 (0xBA003000)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_MBIST_CFG_WRAP (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_EMPTY1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_MBIST_CFG (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_INNER (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_PBCH (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_DEBUG_CR (0xBAC70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBC13000)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC14000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_4 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_A_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM_A (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MCUSYS_MBIST_CONFIG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_SEMAPHORE (0xB405C400)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_MCORE1_CBSCHEDULER (0xB445C000)
+#define BASE_ADDR_MCORE1_SEMAPHORE (0xB445C400)
+#define BASE_ADDR_MCORE1_EINTC (0xB445C800)
+#define BASE_ADDR_MCORE1_CLK_CTRL (0xB44A0040)
+#define BASE_ADDR_MCORE1_DSPRSTCTRL (0xB44A0100)
+#define BASE_ADDR_MCORE1_MML1_DSPRSTCTRL (0xB44A0140)
+#define BASE_ADDR_MCORE1_MC1_DSPRSTCTRL2 (0xB44A0180)
+#define BASE_ADDR_MCORE1_MC1_DSPRSTCTRL3 (0xB44A01C0)
+#define BASE_ADDR_MCORE1_D2D (0xB44A1800)
+#define BASE_ADDR_MCORE1_PMU (0xB44A1C00)
+#define BASE_ADDR_MCORE1_L0_I__CONFIG (0xB44C0000)
+#define BASE_ADDR_MCORE1_MML1_DSPSIL0C_TOP_1 (0xB44C1000)
+#define BASE_ADDR_MCORE1_MML1_DSPSIL0C_TOP_2 (0xB44C2000)
+#define BASE_ADDR_MCORE1_MML1_DSPSIL0C_TOP_3 (0xB44C3000)
+#define BASE_ADDR_MCORE1_L1_I__CONFIG (0xB44C4000)
+#define BASE_ADDR_MCORE1_DBUS_CFG (0xB44C5000)
+#define BASE_ADDR_MCORE1_DEBUG_FLAG_MON (0xB44C6000)
+#define BASE_ADDR_MCORE1_MISC (0xB44C6400)
+#define BASE_ADDR_MCORE1_DSPLOG (0xB44C6800)
+#define BASE_ADDR_MCORE1_SMT_CTI (0xB44C6C00)
+#define BASE_ADDR_MCORE1_BUS_RECORDER (0xB44C7000)
+#define BASE_ADDR_MCORE1_DBGC (0xB44C7800)
+#define BASE_ADDR_MCORE1_L1_D__CFG (0xB44C8000)
+#define BASE_ADDR_MCORE1_L0_D__CONFIG (0xB44CA000)
+#define BASE_ADDR_MCORE1_DATA_CACHE_1 (0xB44CA100)
+#define BASE_ADDR_MCORE1_DATA_CACHE_2 (0xB44CA200)
+#define BASE_ADDR_MCORE1_DATA_CACHE_3 (0xB44CA300)
+#define BASE_ADDR_MCORE1_DSP_TIMER0 (0xB44CA400)
+#define BASE_ADDR_MCORE1_DSP_TIMER1 (0xB44CA410)
+#define BASE_ADDR_MCORE1_DSP_TIMER2 (0xB44CA420)
+#define BASE_ADDR_MCORE1_DSP_TIMER3 (0xB44CA430)
+#define BASE_ADDR_MCORE1_MBIST_CFG (0xB44CB000)
+#define BASE_ADDR_MCORE1_DELSEL_CFG (0xB44CB400)
+#define BASE_ADDR_MCORE1_REPAIR_CFG (0xB44CB800)
+#define BASE_ADDR_MCORE1_MCCKCTL (0xB44CBC00)
+#define BASE_ADDR_MCORE1_THREAD0_LOCAL_ICM (0xB4500000)
+#define BASE_ADDR_MCORE1_THREAD1_LOCAL_ICM (0xB4520000)
+#define BASE_ADDR_MCORE1_THREAD2_LOCAL_ICM (0xB4540000)
+#define BASE_ADDR_MCORE1_THREAD3_LOCAL_ICM (0xB4560000)
+#define BASE_ADDR_MCORE1_THREAD0_CORE_CR (0xB4580000)
+#define BASE_ADDR_MCORE1_MML1_DSPMCORE_TOP_CORE_SMT (0xB4590000)
+#define BASE_ADDR_MCORE1_THREAD1_CORE_CR (0xB45A0000)
+#define BASE_ADDR_MCORE1_THREAD2_CORE_CR (0xB45B0000)
+#define BASE_ADDR_MCORE1_THREAD3_CORE_CR (0xB45C0000)
+#define BASE_ADDR_MCORE1_L1_I_TCM (0xB45E0000)
+#define BASE_ADDR_MCORE1_MSP_DBGMEM (0xB4600000)
+#define BASE_ADDR_MCORE1_L1_D__TCM (0xB4780000)
+#define BASE_ADDR_MCORE1_MML1_DSPSDL1C (0xB47C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH3_L1MC__CR (0xB5053000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_TH3_BLAZE (0xB5057000)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_TH3_L1MC__MEM (0xB5090000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSL2C (0xB4C00000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER1 (0xB4C20000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1 (0xB4CA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_AO_SRAM (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4D80000)
+#define BASE_ADDR_MCOREPERI_INFRA_RSTCTRL (0xB4D88000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4D90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MBIST_CFG (0xB4D98000)
+#define BASE_ADDR_MCOREPERI_INFRA_BUS_CR (0xB4DA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4DA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB4DB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB4DB0400)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO (0xB4DB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO (0xB4DC0000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO (0xB4DC8000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4DD8000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_GLBCON (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_RSTCTRL (0xB4E88000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_DBGMON_WRAP (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_MBIST_CONFIG (0xB4E98000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_DELSEL_CFG_WRAP (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_ABUSMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_ELM (0xB4F20000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB4DD0000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB4DD0400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB4DD0600)
+#define BASE_ADDR_VCORESIL2CSYS_DSPSL2C (0xB5C00000)
+#define BASE_ADDR_VCORESIL2CSYS_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCORESIL2CSYS_ABUS_CR (0xB5C20000)
+#define BASE_ADDR_VCORESIL2CSYS_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCORESIL2CSYS_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCORESIL2CSYS_RSTCTRL (0xB5C90000)
+#define BASE_ADDR_VCORESIL2CSYS_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCORESIL2CSYS_MBIST_CFG (0xB5CB0000)
+#define BASE_ADDR_VCORESIL2CSYS_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCORESIL2CSYS_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCORESIL2CSYS_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCSI_NR_HGRX (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_MBIST_CFG_WRAP (0xB6F10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RSTCTL (0xB6F18000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_BUSRECORDER1_MCORESYS_BUSRECORDER1 (0xB0645800)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB0649800)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A000)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064A400)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064A440)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064A480)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064A4C0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064A500)
+#define BASE_ADDR_MCORE1_CORE_MCORE1_CORE (0xB064C000)
+#define BASE_ADDR_MCORE1_DBUS_MCORE1_DBUS (0xB064D000)
+#define BASE_ADDR_MCORE1_PMU_MCORE1_PMU (0xB064D800)
+#define BASE_ADDR_MCORE1_BUS_RECORDER_MCORE1_BUS_RECORDER (0xB064E000)
+#define BASE_ADDR_MCORE1_CONFIG_TH0____________MCORE1_CONFIG_TH0 (0xB064E400)
+#define BASE_ADDR_MCORE1_CONFIG_TH1____________MCORE1_CONFIG_TH1 (0xB064E440)
+#define BASE_ADDR_MCORE1_CONFIG_TH2____________MCORE1_CONFIG_TH2 (0xB064E480)
+#define BASE_ADDR_MCORE1_CONFIG_TH3____________MCORE1_CONFIG_TH3 (0xB064E4C0)
+#define BASE_ADDR_MCORE1_DEBUG_FLAG_MON_MCORE1_DEBUG_FLAG_MON (0xB064E500)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0651800)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652000)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652400)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652440)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652480)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB06524C0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652500)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_VCOREHRAM_AO_DBGMON_VCOREHRAM_AO_DBGMON (0xB0653800)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_PERICK_ABUS_SIL2CSYS_PERICK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PERICK_DBUS_SIL2CSYS_PERICK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RESERVED2 (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_MBIST_CFG_WRAP (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_MBIST_CONFIG (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MCOREPERI_INFRA (0xB4DB8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_CONFIG0 (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_CONFIG1 (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_CORE (0xB9420000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_CORE_1 (0xB9430000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_CONFIG (0xB9C50000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP_1 (0xBA003000)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_MBIST_CFG_WRAP (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_EMPTY1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_MBIST_CFG (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_INNER (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_PBCH (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_DEBUG_CR (0xBAC70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBC13000)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC14000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_4 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6297_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6297_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6297_FPGA.h b/mcu/interface/driver/regbase/md97/reg_base_MT6297_FPGA.h
new file mode 100644
index 0000000..4d4467c
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6297_FPGA.h
@@ -0,0 +1,3003 @@
+#ifndef __REG_BASE_MT6297_FPGA_H__
+#define __REG_BASE_MT6297_FPGA_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from 6297_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM_A (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_MD_BOOTSLAVE_TOP_AXI (0x9FE00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_IA_BTSLV (0x9FF00000)
+#define BASE_MADDR_MDMCU_ABM (0xA0200000)
+#define BASE_MADDR_MDMCU_PDA_MONITER (0xA0210000)
+#define BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xA0220000)
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA0230000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MCUSYS_MBIST_CONFIG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_SEMAPHORE (0xA405C400)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+#define BASE_MADDR_MCORE1_CBSCHEDULER (0xA445C000)
+#define BASE_MADDR_MCORE1_SEMAPHORE (0xA445C400)
+#define BASE_MADDR_MCORE1_EINTC (0xA445C800)
+#define BASE_MADDR_MCORE1_CLK_CTRL (0xA44A0040)
+#define BASE_MADDR_MCORE1_DSPRSTCTRL (0xA44A0100)
+#define BASE_MADDR_MCORE1_MML1_DSPRSTCTRL (0xA44A0140)
+#define BASE_MADDR_MCORE1_MC1_DSPRSTCTRL2 (0xA44A0180)
+#define BASE_MADDR_MCORE1_MC1_DSPRSTCTRL3 (0xA44A01C0)
+#define BASE_MADDR_MCORE1_D2D (0xA44A1800)
+#define BASE_MADDR_MCORE1_PMU (0xA44A1C00)
+#define BASE_MADDR_MCORE1_L0_I__CONFIG (0xA44C0000)
+#define BASE_MADDR_MCORE1_MML1_DSPSIL0C_TOP_1 (0xA44C1000)
+#define BASE_MADDR_MCORE1_MML1_DSPSIL0C_TOP_2 (0xA44C2000)
+#define BASE_MADDR_MCORE1_MML1_DSPSIL0C_TOP_3 (0xA44C3000)
+#define BASE_MADDR_MCORE1_L1_I__CONFIG (0xA44C4000)
+#define BASE_MADDR_MCORE1_DBUS_CFG (0xA44C5000)
+#define BASE_MADDR_MCORE1_DEBUG_FLAG_MON (0xA44C6000)
+#define BASE_MADDR_MCORE1_MISC (0xA44C6400)
+#define BASE_MADDR_MCORE1_DSPLOG (0xA44C6800)
+#define BASE_MADDR_MCORE1_SMT_CTI (0xA44C6C00)
+#define BASE_MADDR_MCORE1_BUS_RECORDER (0xA44C7000)
+#define BASE_MADDR_MCORE1_DBGC (0xA44C7800)
+#define BASE_MADDR_MCORE1_L1_D__CFG (0xA44C8000)
+#define BASE_MADDR_MCORE1_L0_D__CONFIG (0xA44CA000)
+#define BASE_MADDR_MCORE1_DATA_CACHE_1 (0xA44CA100)
+#define BASE_MADDR_MCORE1_DATA_CACHE_2 (0xA44CA200)
+#define BASE_MADDR_MCORE1_DATA_CACHE_3 (0xA44CA300)
+#define BASE_MADDR_MCORE1_DSP_TIMER0 (0xA44CA400)
+#define BASE_MADDR_MCORE1_DSP_TIMER1 (0xA44CA410)
+#define BASE_MADDR_MCORE1_DSP_TIMER2 (0xA44CA420)
+#define BASE_MADDR_MCORE1_DSP_TIMER3 (0xA44CA430)
+#define BASE_MADDR_MCORE1_MBIST_CFG (0xA44CB000)
+#define BASE_MADDR_MCORE1_DELSEL_CFG (0xA44CB400)
+#define BASE_MADDR_MCORE1_REPAIR_CFG (0xA44CB800)
+#define BASE_MADDR_MCORE1_MCCKCTL (0xA44CBC00)
+#define BASE_MADDR_MCORE1_THREAD0_LOCAL_ICM (0xA4500000)
+#define BASE_MADDR_MCORE1_THREAD1_LOCAL_ICM (0xA4520000)
+#define BASE_MADDR_MCORE1_THREAD2_LOCAL_ICM (0xA4540000)
+#define BASE_MADDR_MCORE1_THREAD3_LOCAL_ICM (0xA4560000)
+#define BASE_MADDR_MCORE1_THREAD0_CORE_CR (0xA4580000)
+#define BASE_MADDR_MCORE1_MML1_DSPMCORE_TOP_CORE_SMT (0xA4590000)
+#define BASE_MADDR_MCORE1_THREAD1_CORE_CR (0xA45A0000)
+#define BASE_MADDR_MCORE1_THREAD2_CORE_CR (0xA45B0000)
+#define BASE_MADDR_MCORE1_THREAD3_CORE_CR (0xA45C0000)
+#define BASE_MADDR_MCORE1_L1_I_TCM (0xA45E0000)
+#define BASE_MADDR_MCORE1_MSP_DBGMEM (0xA4600000)
+#define BASE_MADDR_MCORE1_L1_D__TCM (0xA4780000)
+#define BASE_MADDR_MCORE1_MML1_DSPSDL1C (0xA47C0000)
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH3_L1MC__CR (0xA5053000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_TH3_BLAZE (0xA5057000)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_TH3_L1MC__MEM (0xA5090000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSL2C (0xA4C00000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER1 (0xA4C20000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1 (0xA4CA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_AO_SRAM (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4D80000)
+#define BASE_MADDR_MCOREPERI_INFRA_RSTCTRL (0xA4D88000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4D90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MBIST_CFG (0xA4D98000)
+#define BASE_MADDR_MCOREPERI_INFRA_BUS_CR (0xA4DA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4DA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA4DB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA4DB0400)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO (0xA4DB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO (0xA4DC0000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO (0xA4DC8000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4DD8000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_GLBCON (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_RSTCTRL (0xA4E88000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_DBGMON_WRAP (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_MBIST_CONFIG (0xA4E98000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_DELSEL_CFG_WRAP (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_ABUSMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_ELM (0xA4F20000)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA4DD0000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA4DD0400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA4DD0600)
+#define BASE_MADDR_VCORESIL2CSYS_DSPSL2C (0xA5C00000)
+#define BASE_MADDR_VCORESIL2CSYS_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCORESIL2CSYS_ABUS_CR (0xA5C20000)
+#define BASE_MADDR_VCORESIL2CSYS_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCORESIL2CSYS_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCORESIL2CSYS_RSTCTRL (0xA5C90000)
+#define BASE_MADDR_VCORESIL2CSYS_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCORESIL2CSYS_MBIST_CFG (0xA5CB0000)
+#define BASE_MADDR_VCORESIL2CSYS_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCORESIL2CSYS_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCORESIL2CSYS_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCSI_NR_HGRX (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_MBIST_CFG_WRAP (0xA6F10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RSTCTL (0xA6F18000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_BUSRECORDER1_MCORESYS_BUSRECORDER1 (0xA0645800)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA0649800)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A000)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064A400)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064A440)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064A480)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064A4C0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064A500)
+#define BASE_MADDR_MCORE1_CORE_MCORE1_CORE (0xA064C000)
+#define BASE_MADDR_MCORE1_DBUS_MCORE1_DBUS (0xA064D000)
+#define BASE_MADDR_MCORE1_PMU_MCORE1_PMU (0xA064D800)
+#define BASE_MADDR_MCORE1_BUS_RECORDER_MCORE1_BUS_RECORDER (0xA064E000)
+#define BASE_MADDR_MCORE1_CONFIG_TH0____________MCORE1_CONFIG_TH0 (0xA064E400)
+#define BASE_MADDR_MCORE1_CONFIG_TH1____________MCORE1_CONFIG_TH1 (0xA064E440)
+#define BASE_MADDR_MCORE1_CONFIG_TH2____________MCORE1_CONFIG_TH2 (0xA064E480)
+#define BASE_MADDR_MCORE1_CONFIG_TH3____________MCORE1_CONFIG_TH3 (0xA064E4C0)
+#define BASE_MADDR_MCORE1_DEBUG_FLAG_MON_MCORE1_DEBUG_FLAG_MON (0xA064E500)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0651800)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652000)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652400)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652440)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652480)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA06524C0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652500)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_VCOREHRAM_AO_DBGMON_VCOREHRAM_AO_DBGMON (0xA0653800)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_PERICK_ABUS_SIL2CSYS_PERICK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PERICK_DBUS_SIL2CSYS_PERICK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RESERVED2 (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_MBIST_CFG_WRAP (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_MBIST_CONFIG (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MCOREPERI_INFRA (0xA4DB8000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_CONFIG0 (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_CONFIG1 (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_CORE (0xA9420000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_CORE_1 (0xA9430000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_CONFIG (0xA9C50000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP_1 (0xAA003000)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_MBIST_CFG_WRAP (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_EMPTY1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_MBIST_CFG (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR_INNER (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_PBCH (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_DEBUG_CR (0xAAC70000)
+// (30): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_CONFIG (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (31): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABC13000)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC14000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_4 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (32): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (33): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_CONFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_A_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM_A (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_ABM (0xB0200000)
+#define BASE_NADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MCUSYS_MBIST_CONFIG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_SEMAPHORE (0xB405C400)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_MCORE1_CBSCHEDULER (0xB445C000)
+#define BASE_NADDR_MCORE1_SEMAPHORE (0xB445C400)
+#define BASE_NADDR_MCORE1_EINTC (0xB445C800)
+#define BASE_NADDR_MCORE1_CLK_CTRL (0xB44A0040)
+#define BASE_NADDR_MCORE1_DSPRSTCTRL (0xB44A0100)
+#define BASE_NADDR_MCORE1_MML1_DSPRSTCTRL (0xB44A0140)
+#define BASE_NADDR_MCORE1_MC1_DSPRSTCTRL2 (0xB44A0180)
+#define BASE_NADDR_MCORE1_MC1_DSPRSTCTRL3 (0xB44A01C0)
+#define BASE_NADDR_MCORE1_D2D (0xB44A1800)
+#define BASE_NADDR_MCORE1_PMU (0xB44A1C00)
+#define BASE_NADDR_MCORE1_L0_I__CONFIG (0xB44C0000)
+#define BASE_NADDR_MCORE1_MML1_DSPSIL0C_TOP_1 (0xB44C1000)
+#define BASE_NADDR_MCORE1_MML1_DSPSIL0C_TOP_2 (0xB44C2000)
+#define BASE_NADDR_MCORE1_MML1_DSPSIL0C_TOP_3 (0xB44C3000)
+#define BASE_NADDR_MCORE1_L1_I__CONFIG (0xB44C4000)
+#define BASE_NADDR_MCORE1_DBUS_CFG (0xB44C5000)
+#define BASE_NADDR_MCORE1_DEBUG_FLAG_MON (0xB44C6000)
+#define BASE_NADDR_MCORE1_MISC (0xB44C6400)
+#define BASE_NADDR_MCORE1_DSPLOG (0xB44C6800)
+#define BASE_NADDR_MCORE1_SMT_CTI (0xB44C6C00)
+#define BASE_NADDR_MCORE1_BUS_RECORDER (0xB44C7000)
+#define BASE_NADDR_MCORE1_DBGC (0xB44C7800)
+#define BASE_NADDR_MCORE1_L1_D__CFG (0xB44C8000)
+#define BASE_NADDR_MCORE1_L0_D__CONFIG (0xB44CA000)
+#define BASE_NADDR_MCORE1_DATA_CACHE_1 (0xB44CA100)
+#define BASE_NADDR_MCORE1_DATA_CACHE_2 (0xB44CA200)
+#define BASE_NADDR_MCORE1_DATA_CACHE_3 (0xB44CA300)
+#define BASE_NADDR_MCORE1_DSP_TIMER0 (0xB44CA400)
+#define BASE_NADDR_MCORE1_DSP_TIMER1 (0xB44CA410)
+#define BASE_NADDR_MCORE1_DSP_TIMER2 (0xB44CA420)
+#define BASE_NADDR_MCORE1_DSP_TIMER3 (0xB44CA430)
+#define BASE_NADDR_MCORE1_MBIST_CFG (0xB44CB000)
+#define BASE_NADDR_MCORE1_DELSEL_CFG (0xB44CB400)
+#define BASE_NADDR_MCORE1_REPAIR_CFG (0xB44CB800)
+#define BASE_NADDR_MCORE1_MCCKCTL (0xB44CBC00)
+#define BASE_NADDR_MCORE1_THREAD0_LOCAL_ICM (0xB4500000)
+#define BASE_NADDR_MCORE1_THREAD1_LOCAL_ICM (0xB4520000)
+#define BASE_NADDR_MCORE1_THREAD2_LOCAL_ICM (0xB4540000)
+#define BASE_NADDR_MCORE1_THREAD3_LOCAL_ICM (0xB4560000)
+#define BASE_NADDR_MCORE1_THREAD0_CORE_CR (0xB4580000)
+#define BASE_NADDR_MCORE1_MML1_DSPMCORE_TOP_CORE_SMT (0xB4590000)
+#define BASE_NADDR_MCORE1_THREAD1_CORE_CR (0xB45A0000)
+#define BASE_NADDR_MCORE1_THREAD2_CORE_CR (0xB45B0000)
+#define BASE_NADDR_MCORE1_THREAD3_CORE_CR (0xB45C0000)
+#define BASE_NADDR_MCORE1_L1_I_TCM (0xB45E0000)
+#define BASE_NADDR_MCORE1_MSP_DBGMEM (0xB4600000)
+#define BASE_NADDR_MCORE1_L1_D__TCM (0xB4780000)
+#define BASE_NADDR_MCORE1_MML1_DSPSDL1C (0xB47C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH3_L1MC__CR (0xB5053000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_TH3_BLAZE (0xB5057000)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_TH3_L1MC__MEM (0xB5090000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSL2C (0xB4C00000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER1 (0xB4C20000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1 (0xB4CA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_AO_SRAM (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4D80000)
+#define BASE_NADDR_MCOREPERI_INFRA_RSTCTRL (0xB4D88000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4D90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MBIST_CFG (0xB4D98000)
+#define BASE_NADDR_MCOREPERI_INFRA_BUS_CR (0xB4DA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4DA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB4DB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB4DB0400)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO (0xB4DB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO (0xB4DC0000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO (0xB4DC8000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4DD8000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_GLBCON (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_RSTCTRL (0xB4E88000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_DBGMON_WRAP (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_MBIST_CONFIG (0xB4E98000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCORESYS_DELSEL_CFG_WRAP (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_ABUSMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_ELM (0xB4F20000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB4DD0000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB4DD0400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB4DD0600)
+#define BASE_NADDR_VCORESIL2CSYS_DSPSL2C (0xB5C00000)
+#define BASE_NADDR_VCORESIL2CSYS_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCORESIL2CSYS_ABUS_CR (0xB5C20000)
+#define BASE_NADDR_VCORESIL2CSYS_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCORESIL2CSYS_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCORESIL2CSYS_RSTCTRL (0xB5C90000)
+#define BASE_NADDR_VCORESIL2CSYS_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCORESIL2CSYS_MBIST_CFG (0xB5CB0000)
+#define BASE_NADDR_VCORESIL2CSYS_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCORESIL2CSYS_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCORESIL2CSYS_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCSI_NR_HGRX (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_MBIST_CFG_WRAP (0xB6F10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RSTCTL (0xB6F18000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_BUSRECORDER1_MCORESYS_BUSRECORDER1 (0xB0645800)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB0649800)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A000)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064A400)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064A440)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064A480)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064A4C0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064A500)
+#define BASE_NADDR_MCORE1_CORE_MCORE1_CORE (0xB064C000)
+#define BASE_NADDR_MCORE1_DBUS_MCORE1_DBUS (0xB064D000)
+#define BASE_NADDR_MCORE1_PMU_MCORE1_PMU (0xB064D800)
+#define BASE_NADDR_MCORE1_BUS_RECORDER_MCORE1_BUS_RECORDER (0xB064E000)
+#define BASE_NADDR_MCORE1_CONFIG_TH0____________MCORE1_CONFIG_TH0 (0xB064E400)
+#define BASE_NADDR_MCORE1_CONFIG_TH1____________MCORE1_CONFIG_TH1 (0xB064E440)
+#define BASE_NADDR_MCORE1_CONFIG_TH2____________MCORE1_CONFIG_TH2 (0xB064E480)
+#define BASE_NADDR_MCORE1_CONFIG_TH3____________MCORE1_CONFIG_TH3 (0xB064E4C0)
+#define BASE_NADDR_MCORE1_DEBUG_FLAG_MON_MCORE1_DEBUG_FLAG_MON (0xB064E500)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0651800)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652000)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652400)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652440)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652480)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB06524C0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652500)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_VCOREHRAM_AO_DBGMON_VCOREHRAM_AO_DBGMON (0xB0653800)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_PERICK_ABUS_SIL2CSYS_PERICK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PERICK_DBUS_SIL2CSYS_PERICK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RESERVED2 (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_MBIST_CFG_WRAP (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_MBIST_CONFIG (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MCOREPERI_INFRA (0xB4DB8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_CONFIG0 (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_CONFIG1 (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_CORE (0xB9420000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_CORE_1 (0xB9430000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_CONFIG (0xB9C50000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP_1 (0xBA003000)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_MBIST_CFG_WRAP (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_EMPTY1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_MBIST_CFG (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_INNER (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_PBCH (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_DEBUG_CR (0xBAC70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBC13000)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC14000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_4 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_CONFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_A_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM_A (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_ABM (0xB0200000)
+#define BASE_ADDR_MDMCU_PDA_MONITER (0xB0210000)
+#define BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG (0xB0220000)
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB0230000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MCUSYS_MBIST_CONFIG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_SEMAPHORE (0xB405C400)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_MCORE1_CBSCHEDULER (0xB445C000)
+#define BASE_ADDR_MCORE1_SEMAPHORE (0xB445C400)
+#define BASE_ADDR_MCORE1_EINTC (0xB445C800)
+#define BASE_ADDR_MCORE1_CLK_CTRL (0xB44A0040)
+#define BASE_ADDR_MCORE1_DSPRSTCTRL (0xB44A0100)
+#define BASE_ADDR_MCORE1_MML1_DSPRSTCTRL (0xB44A0140)
+#define BASE_ADDR_MCORE1_MC1_DSPRSTCTRL2 (0xB44A0180)
+#define BASE_ADDR_MCORE1_MC1_DSPRSTCTRL3 (0xB44A01C0)
+#define BASE_ADDR_MCORE1_D2D (0xB44A1800)
+#define BASE_ADDR_MCORE1_PMU (0xB44A1C00)
+#define BASE_ADDR_MCORE1_L0_I__CONFIG (0xB44C0000)
+#define BASE_ADDR_MCORE1_MML1_DSPSIL0C_TOP_1 (0xB44C1000)
+#define BASE_ADDR_MCORE1_MML1_DSPSIL0C_TOP_2 (0xB44C2000)
+#define BASE_ADDR_MCORE1_MML1_DSPSIL0C_TOP_3 (0xB44C3000)
+#define BASE_ADDR_MCORE1_L1_I__CONFIG (0xB44C4000)
+#define BASE_ADDR_MCORE1_DBUS_CFG (0xB44C5000)
+#define BASE_ADDR_MCORE1_DEBUG_FLAG_MON (0xB44C6000)
+#define BASE_ADDR_MCORE1_MISC (0xB44C6400)
+#define BASE_ADDR_MCORE1_DSPLOG (0xB44C6800)
+#define BASE_ADDR_MCORE1_SMT_CTI (0xB44C6C00)
+#define BASE_ADDR_MCORE1_BUS_RECORDER (0xB44C7000)
+#define BASE_ADDR_MCORE1_DBGC (0xB44C7800)
+#define BASE_ADDR_MCORE1_L1_D__CFG (0xB44C8000)
+#define BASE_ADDR_MCORE1_L0_D__CONFIG (0xB44CA000)
+#define BASE_ADDR_MCORE1_DATA_CACHE_1 (0xB44CA100)
+#define BASE_ADDR_MCORE1_DATA_CACHE_2 (0xB44CA200)
+#define BASE_ADDR_MCORE1_DATA_CACHE_3 (0xB44CA300)
+#define BASE_ADDR_MCORE1_DSP_TIMER0 (0xB44CA400)
+#define BASE_ADDR_MCORE1_DSP_TIMER1 (0xB44CA410)
+#define BASE_ADDR_MCORE1_DSP_TIMER2 (0xB44CA420)
+#define BASE_ADDR_MCORE1_DSP_TIMER3 (0xB44CA430)
+#define BASE_ADDR_MCORE1_MBIST_CFG (0xB44CB000)
+#define BASE_ADDR_MCORE1_DELSEL_CFG (0xB44CB400)
+#define BASE_ADDR_MCORE1_REPAIR_CFG (0xB44CB800)
+#define BASE_ADDR_MCORE1_MCCKCTL (0xB44CBC00)
+#define BASE_ADDR_MCORE1_THREAD0_LOCAL_ICM (0xB4500000)
+#define BASE_ADDR_MCORE1_THREAD1_LOCAL_ICM (0xB4520000)
+#define BASE_ADDR_MCORE1_THREAD2_LOCAL_ICM (0xB4540000)
+#define BASE_ADDR_MCORE1_THREAD3_LOCAL_ICM (0xB4560000)
+#define BASE_ADDR_MCORE1_THREAD0_CORE_CR (0xB4580000)
+#define BASE_ADDR_MCORE1_MML1_DSPMCORE_TOP_CORE_SMT (0xB4590000)
+#define BASE_ADDR_MCORE1_THREAD1_CORE_CR (0xB45A0000)
+#define BASE_ADDR_MCORE1_THREAD2_CORE_CR (0xB45B0000)
+#define BASE_ADDR_MCORE1_THREAD3_CORE_CR (0xB45C0000)
+#define BASE_ADDR_MCORE1_L1_I_TCM (0xB45E0000)
+#define BASE_ADDR_MCORE1_MSP_DBGMEM (0xB4600000)
+#define BASE_ADDR_MCORE1_L1_D__TCM (0xB4780000)
+#define BASE_ADDR_MCORE1_MML1_DSPSDL1C (0xB47C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH3_L1MC__CR (0xB5053000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_TH3_BLAZE (0xB5057000)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_TH3_L1MC__MEM (0xB5090000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSL2C (0xB4C00000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER1 (0xB4C20000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1 (0xB4CA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_AO_SRAM (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4D80000)
+#define BASE_ADDR_MCOREPERI_INFRA_RSTCTRL (0xB4D88000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4D90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MBIST_CFG (0xB4D98000)
+#define BASE_ADDR_MCOREPERI_INFRA_BUS_CR (0xB4DA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4DA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB4DB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB4DB0400)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO (0xB4DB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO (0xB4DC0000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO (0xB4DC8000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4DD8000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_GLBCON (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_RSTCTRL (0xB4E88000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_DBGMON_WRAP (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_MBIST_CONFIG (0xB4E98000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCORESYS_DELSEL_CFG_WRAP (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_ABUSMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_ELM (0xB4F20000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB4DD0000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB4DD0400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB4DD0600)
+#define BASE_ADDR_VCORESIL2CSYS_DSPSL2C (0xB5C00000)
+#define BASE_ADDR_VCORESIL2CSYS_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCORESIL2CSYS_ABUS_CR (0xB5C20000)
+#define BASE_ADDR_VCORESIL2CSYS_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCORESIL2CSYS_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCORESIL2CSYS_RSTCTRL (0xB5C90000)
+#define BASE_ADDR_VCORESIL2CSYS_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCORESIL2CSYS_MBIST_CFG (0xB5CB0000)
+#define BASE_ADDR_VCORESIL2CSYS_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCORESIL2CSYS_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCORESIL2CSYS_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCSI_NR_HGRX (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_MBIST_CFG_WRAP (0xB6F10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RSTCTL (0xB6F18000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_BUSRECORDER1_MCORESYS_BUSRECORDER1 (0xB0645800)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB0649800)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A000)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064A400)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064A440)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064A480)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064A4C0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064A500)
+#define BASE_ADDR_MCORE1_CORE_MCORE1_CORE (0xB064C000)
+#define BASE_ADDR_MCORE1_DBUS_MCORE1_DBUS (0xB064D000)
+#define BASE_ADDR_MCORE1_PMU_MCORE1_PMU (0xB064D800)
+#define BASE_ADDR_MCORE1_BUS_RECORDER_MCORE1_BUS_RECORDER (0xB064E000)
+#define BASE_ADDR_MCORE1_CONFIG_TH0____________MCORE1_CONFIG_TH0 (0xB064E400)
+#define BASE_ADDR_MCORE1_CONFIG_TH1____________MCORE1_CONFIG_TH1 (0xB064E440)
+#define BASE_ADDR_MCORE1_CONFIG_TH2____________MCORE1_CONFIG_TH2 (0xB064E480)
+#define BASE_ADDR_MCORE1_CONFIG_TH3____________MCORE1_CONFIG_TH3 (0xB064E4C0)
+#define BASE_ADDR_MCORE1_DEBUG_FLAG_MON_MCORE1_DEBUG_FLAG_MON (0xB064E500)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0651800)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652000)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652400)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652440)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652480)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB06524C0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652500)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_VCOREHRAM_AO_DBGMON_VCOREHRAM_AO_DBGMON (0xB0653800)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_PERICK_ABUS_SIL2CSYS_PERICK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PERICK_DBUS_SIL2CSYS_PERICK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RESERVED2 (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_MBIST_CFG_WRAP (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_MBIST_CONFIG (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MCOREPERI_INFRA (0xB4DB8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_CONFIG0 (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_CONFIG1 (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_CORE (0xB9420000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_CORE_1 (0xB9430000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_CONFIG (0xB9C50000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_CC_MBIST_WRAP_1 (0xBA003000)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_MBIST_CFG_WRAP (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_EMPTY1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_MBIST_CFG (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_INNER (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_PBCH (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_DEBUG_CR (0xBAC70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_CONFIG (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBC13000)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC14000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_4 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_CONFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from 6297_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6297_FPGA_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6297_FPGA_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6297_FPGA_username.h
new file mode 100644
index 0000000..a5215cc
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6297_FPGA_username.h
@@ -0,0 +1,158 @@
+#ifndef __REG_BASE_MT6297_FPGA_USERNAME_H__
+#define __REG_BASE_MT6297_FPGA_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+//WCS/SSE/SS2 Linson Du
+//#define BASE_ADDR_MDINFRA_ELM 0xB0350000
+//#define BASE_ADDR_MCUSYS_ELM_EMI 0xB0350000
+#define BASE_ADDR_MDINFRA_ELM BASE_ADDR_MDINFRA_ELM_A
+//#define BASE_ADDR_MCUSYS_ELM_EMI BASE_ADDR_MDINFRA_ELM_B
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6297_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6297_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6297_username.h
new file mode 100644
index 0000000..83e1a3f
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6297_username.h
@@ -0,0 +1,174 @@
+#ifndef __REG_BASE_MT6297_USERNAME_H__
+#define __REG_BASE_MT6297_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+
+#define BASE_MADDR_MHCCIF_MD (0xC0028000)
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define BASE_MADDR_APMCU_MISC (0xC000D000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WSP/MPE2/SD3 Cindy Tu
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+#define BASE_INFRA_AO_SLEEP_CTRL (0xC0006000)
+#define BASE_INFRA_AO_TOPRGU (0xC0007000)
+
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+//WCS/SSE/SS2 Linson Du
+//#define BASE_ADDR_MDINFRA_ELM 0xB0350000
+//#define BASE_ADDR_MCUSYS_ELM_EMI 0xB0350000
+#define BASE_ADDR_MDINFRA_ELM BASE_ADDR_MDINFRA_ELM_A
+//#define BASE_ADDR_MCUSYS_ELM_EMI BASE_ADDR_MDINFRA_ELM_B
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F60000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F60000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1F60000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6297_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6833.h b/mcu/interface/driver/regbase/md97/reg_base_MT6833.h
new file mode 100644
index 0000000..7ba57e0
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6833.h
@@ -0,0 +1,2882 @@
+#ifndef __REG_BASE_MT6833_H__
+#define __REG_BASE_MT6833_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+//////////////////////////////MT6833//////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6833_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6833_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6833_username.h
new file mode 100644
index 0000000..901dbaa
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6833_username.h
@@ -0,0 +1,183 @@
+#ifndef __REG_BASE_MT6833_USERNAME_H__
+#define __REG_BASE_MT6833_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+#define BASE_MADDR_PCCIF5_AP (0xC025C000)
+#define BASE_MADDR_PCCIF5_MD (0xC025D000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define PMIF_SPMI_BASE (0xC0027000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+#define PMIF_SPMI_P_BASE (0xC0024000)
+#define SPMI_MST_P_BASE (0xC0025000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+#define BASE_INFRA_AO_AP2MD_APMCU_STATUS_IRQ_CLEAR (0xC0001BCC)
+#define BASE_INFRA_AO_AP2MD_APMCU_CURRENT_STATUS (0xC0001BD0)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1E40000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1E40000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1E40000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6833_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6853.h b/mcu/interface/driver/regbase/md97/reg_base_MT6853.h
new file mode 100644
index 0000000..05d0859
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6853.h
@@ -0,0 +1,2882 @@
+#ifndef __REG_BASE_MT6853_H__
+#define __REG_BASE_MT6853_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6853_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6853_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6853_username.h
new file mode 100644
index 0000000..26ac8ce
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6853_username.h
@@ -0,0 +1,181 @@
+#ifndef __REG_BASE_MT6853_USERNAME_H__
+#define __REG_BASE_MT6853_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/MPE2/SD15 Flamingo Wang
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+#define BASE_MADDR_PCCIF5_AP (0xC025C000)
+#define BASE_MADDR_PCCIF5_MD (0xC025D000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define PMIF_SPMI_BASE (0xC0027000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+#define PMIF_SPMI_P_BASE (0xC0024000)
+#define SPMI_MST_P_BASE (0xC0025000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Chris Chi
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+#define BASE_INFRA_AO_AP2MD_APMCU_STATUS_IRQ_CLEAR (0xC0001BCC)
+#define BASE_INFRA_AO_AP2MD_APMCU_CURRENT_STATUS (0xC0001BD0)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Chia-Han Wu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Chen-Yu Wang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6853_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6873.h b/mcu/interface/driver/regbase/md97/reg_base_MT6873.h
new file mode 100644
index 0000000..e53dd09
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6873.h
@@ -0,0 +1,2882 @@
+#ifndef __REG_BASE_MT6873_H__
+#define __REG_BASE_MT6873_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6873_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6873_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6873_username.h
new file mode 100644
index 0000000..b9ae3bb
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6873_username.h
@@ -0,0 +1,181 @@
+#ifndef __REG_BASE_MT6873_USERNAME_H__
+#define __REG_BASE_MT6873_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+#define BASE_MADDR_PCCIF5_AP (0xC025C000)
+#define BASE_MADDR_PCCIF5_MD (0xC025D000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define PMIF_SPMI_BASE (0xC0027000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+#define BASE_INFRA_AO_AP2MD_APMCU_STATUS_IRQ_CLEAR (0xC0001BCC)
+#define BASE_INFRA_AO_AP2MD_APMCU_CURRENT_STATUS (0xC0001BD0)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6873_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6877.h b/mcu/interface/driver/regbase/md97/reg_base_MT6877.h
new file mode 100644
index 0000000..807ba39
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6877.h
@@ -0,0 +1,2882 @@
+#ifndef __REG_BASE_MT6877_H__
+#define __REG_BASE_MT6877_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+//////////////////////////////MT6877//////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6877_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6877_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6877_username.h
new file mode 100644
index 0000000..d78a44c
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6877_username.h
@@ -0,0 +1,183 @@
+#ifndef __REG_BASE_MT6877_USERNAME_H__
+#define __REG_BASE_MT6877_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1F10000)
+
+//WCT/PCT/PCT2 Yi-Cheng Wang
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+#define BASE_MADDR_PCCIF5_AP (0xC025C000)
+#define BASE_MADDR_PCCIF5_MD (0xC025D000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define PMIF_SPMI_BASE (0xC0027000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+#define PMIF_SPMI_P_BASE (0xC0024000)
+#define SPMI_MST_P_BASE (0xC0025000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCT/PCT/PCT2 Chris Chi
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+#define BASE_INFRA_AO_AP2MD_APMCU_STATUS_IRQ_CLEAR (0xC0001BCC)
+#define BASE_INFRA_AO_AP2MD_APMCU_CURRENT_STATUS (0xC0001BD0)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCT/PCT/PCT2 Jacky Wang
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1E40000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1E40000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1E40000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6877_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6885.h b/mcu/interface/driver/regbase/md97/reg_base_MT6885.h
new file mode 100644
index 0000000..bbeeb14
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6885.h
@@ -0,0 +1,2882 @@
+#ifndef __REG_BASE_MT6885_FPGA_H__
+#define __REG_BASE_MT6885_FPGA_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6297_FPGA_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6885_FPGA.h b/mcu/interface/driver/regbase/md97/reg_base_MT6885_FPGA.h
new file mode 100644
index 0000000..bbeeb14
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6885_FPGA.h
@@ -0,0 +1,2882 @@
+#ifndef __REG_BASE_MT6885_FPGA_H__
+#define __REG_BASE_MT6885_FPGA_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+/* temp fix for missing base address definition */
+#define MT6297_E2_CC0_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG
+#define MT6297_E2_CC1_TXBSRP_APB_CONFIG_DRBASE BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6297_FPGA_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6885_FPGA_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6885_FPGA_username.h
new file mode 100644
index 0000000..75cb93a
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6885_FPGA_username.h
@@ -0,0 +1,172 @@
+#ifndef __REG_BASE_MT6297_FPGA_USERNAME_H__
+#define __REG_BASE_MT6297_FPGA_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define PMIF_SPMI_BASE (0xC0027000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F60000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F60000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1F60000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6297_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_MT6885_username.h b/mcu/interface/driver/regbase/md97/reg_base_MT6885_username.h
new file mode 100644
index 0000000..37985d6
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_MT6885_username.h
@@ -0,0 +1,179 @@
+#ifndef __REG_BASE_MT6297_FPGA_USERNAME_H__
+#define __REG_BASE_MT6297_FPGA_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+#define BASE_MADDR_PCCIF2_AP (0xC023C000)
+#define BASE_MADDR_PCCIF2_MD (0xC023D000)
+#define BASE_MADDR_PCCIF4_AP (0xC024C000)
+#define BASE_MADDR_PCCIF4_MD (0xC024D000)
+#define BASE_MADDR_PCCIF5_AP (0xC025C000)
+#define BASE_MADDR_PCCIF5_MD (0xC025D000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+// MTK/WSD/OSS1/SS10 Argus Lin
+#define PMIF_SPMI_BASE (0xC0027000)
+#define SPMI_MST_BASE (0xC0029000)
+#define BASE_INFRA_AO_TOPCKGEN (0xC0000000)
+#define BASE_INFRA_AO_CONFIG (0xC0001000)
+
+// MTK/WSD/OSS1/SS10 Brian-py Chen
+#define PMIF_SPI_BASE (0xC0026000)
+#define PMICSPI_MST_BASE (0xC0028000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+#define BASE_MADDR_WCN_AHB_SLAVE (0xC8000000)
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6297_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_PETRUS_FPGA.h b/mcu/interface/driver/regbase/md97/reg_base_PETRUS_FPGA.h
new file mode 100644
index 0000000..e3a270f
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_PETRUS_FPGA.h
@@ -0,0 +1,2879 @@
+#ifndef __REG_BASE_MT6885_FPGA_H__
+#define __REG_BASE_MT6885_FPGA_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (4): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (5): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_MISC_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_SMI_B_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xA04D0000)
+#define BASE_MADDR_MDINFRA_RSI_CONFIG (0xA04E0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_ELM_B (0xA0530000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (6): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_USPRAM (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM0 (0x9F100000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM0 (0x9F200000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM1 (0x9F300000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM1 (0x9F400000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM2 (0x9F500000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM2 (0x9F600000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_ISPRAM3 (0x9F700000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_DSPRAM3 (0x9F800000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FA00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FB00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xA02C0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xA0341000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xA0342000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xA0343000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_BUSMPU_INFRA (0xA0370000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_MDMCU_RSI (0xA03A0000)
+// (7): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_USIP2_ITCM (0xA0A00000)
+#define BASE_MADDR_USIP_USIP2_DTCM (0xA0A40000)
+#define BASE_MADDR_USIP_USIP2_DEBUG (0xA0A80000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (8): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+// (9): MAP_MCORE0
+#define BASE_MADDR_MCORE0_CBSCHEDULER (0xA405C000)
+#define BASE_MADDR_MCORE0_EINTC (0xA405C800)
+#define BASE_MADDR_MCORE0_CLK_CTRL (0xA40A0040)
+#define BASE_MADDR_MCORE0_DSPRSTCTRL (0xA40A0100)
+#define BASE_MADDR_MCORE0_MML1_DSPRSTCTRL (0xA40A0140)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL2 (0xA40A0180)
+#define BASE_MADDR_MCORE0_MC0_DSPRSTCTRL3 (0xA40A01C0)
+#define BASE_MADDR_MCORE0_D2D (0xA40A1800)
+#define BASE_MADDR_MCORE0_PMU (0xA40A1C00)
+#define BASE_MADDR_MCORE0_L0_I__CONFIG (0xA40C0000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xA40C1000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xA40C2000)
+#define BASE_MADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xA40C3000)
+#define BASE_MADDR_MCORE0_L1_I__CONFIG (0xA40C4000)
+#define BASE_MADDR_MCORE0_DBUS_CFG (0xA40C5000)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON (0xA40C6000)
+#define BASE_MADDR_MCORE0_MISC (0xA40C6400)
+#define BASE_MADDR_MCORE0_DSPLOG (0xA40C6800)
+#define BASE_MADDR_MCORE0_SMT_CTI (0xA40C6C00)
+#define BASE_MADDR_MCORE0_BUS_RECORDER (0xA40C7000)
+#define BASE_MADDR_MCORE0_DBGC (0xA40C7800)
+#define BASE_MADDR_MCORE0_L1_D__CFG (0xA40C8000)
+#define BASE_MADDR_MCORE0_L0_D__CONFIG (0xA40CA000)
+#define BASE_MADDR_MCORE0_DATA_CACHE_1 (0xA40CA100)
+#define BASE_MADDR_MCORE0_DATA_CACHE_2 (0xA40CA200)
+#define BASE_MADDR_MCORE0_DATA_CACHE_3 (0xA40CA300)
+#define BASE_MADDR_MCORE0_DSP_TIMER0 (0xA40CA400)
+#define BASE_MADDR_MCORE0_DSP_TIMER1 (0xA40CA410)
+#define BASE_MADDR_MCORE0_DSP_TIMER2 (0xA40CA420)
+#define BASE_MADDR_MCORE0_DSP_TIMER3 (0xA40CA430)
+#define BASE_MADDR_MCORE0_MBIST_CFG (0xA40CB000)
+#define BASE_MADDR_MCORE0_DELSEL_CFG (0xA40CB400)
+#define BASE_MADDR_MCORE0_REPAIR_CFG (0xA40CB800)
+#define BASE_MADDR_MCORE0_MCCKCTL (0xA40CBC00)
+#define BASE_MADDR_MCORE0_THREAD0_LOCAL_ICM (0xA4100000)
+#define BASE_MADDR_MCORE0_THREAD1_LOCAL_ICM (0xA4120000)
+#define BASE_MADDR_MCORE0_THREAD2_LOCAL_ICM (0xA4140000)
+#define BASE_MADDR_MCORE0_THREAD3_LOCAL_ICM (0xA4160000)
+#define BASE_MADDR_MCORE0_THREAD0_CORE_CR (0xA4180000)
+#define BASE_MADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xA4190000)
+#define BASE_MADDR_MCORE0_THREAD1_CORE_CR (0xA41A0000)
+#define BASE_MADDR_MCORE0_THREAD2_CORE_CR (0xA41B0000)
+#define BASE_MADDR_MCORE0_THREAD3_CORE_CR (0xA41C0000)
+#define BASE_MADDR_MCORE0_L1_I_TCM (0xA41E0000)
+#define BASE_MADDR_MCORE0_MSP_DBGMEM (0xA4200000)
+#define BASE_MADDR_MCORE0_L1_D__TCM (0xA4380000)
+#define BASE_MADDR_MCORE0_MML1_DSPSDL1C (0xA43C0000)
+// (10): MAP_MCORE1
+// (11): MAP_VCORE
+#define BASE_MADDR_VCORE_TH0_L1MC__CR (0xA5050000)
+#define BASE_MADDR_VCORE_TH1_L1MC__CR (0xA5051000)
+#define BASE_MADDR_VCORE_TH2_L1MC__CR (0xA5052000)
+#define BASE_MADDR_VCORE_TH0_BLAZE (0xA5054000)
+#define BASE_MADDR_VCORE_TH1_BLAZE (0xA5055000)
+#define BASE_MADDR_VCORE_TH2_BLAZE (0xA5056000)
+#define BASE_MADDR_VCORE_EINTC (0xA505C800)
+#define BASE_MADDR_VCORE_TH0_L1MC__MEM (0xA5060000)
+#define BASE_MADDR_VCORE_TH1_L1MC__MEM (0xA5070000)
+#define BASE_MADDR_VCORE_TH2_L1MC__MEM (0xA5080000)
+#define BASE_MADDR_VCORE_CLK_CTRL (0xA50A0040)
+#define BASE_MADDR_VCORE_DSPRSTCTRL (0xA50A0100)
+#define BASE_MADDR_VCORE_D2D (0xA50A1800)
+#define BASE_MADDR_VCORE_PMU (0xA50A1C00)
+#define BASE_MADDR_VCORE_SLV_SCHEDULER (0xA50B0000)
+#define BASE_MADDR_VCORE_HLSU (0xA50B0400)
+#define BASE_MADDR_VCORE_L0_I__CONFIG (0xA50C0000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xA50C1000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xA50C2000)
+#define BASE_MADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xA50C3000)
+#define BASE_MADDR_VCORE_L1_I__CONFIG (0xA50C4000)
+#define BASE_MADDR_VCORE_DBUS_CFG (0xA50C5000)
+#define BASE_MADDR_VCORE_DEBUG_FLAG_MON (0xA50C6000)
+#define BASE_MADDR_VCORE_MISC (0xA50C6400)
+#define BASE_MADDR_VCORE_DSPLOG (0xA50C6800)
+#define BASE_MADDR_VCORE_SMT_CTI (0xA50C6C00)
+#define BASE_MADDR_VCORE_BUS_RECORDER (0xA50C7000)
+#define BASE_MADDR_VCORE_DBGC (0xA50C7800)
+#define BASE_MADDR_VCORE_L1_D__CFG (0xA50C8000)
+#define BASE_MADDR_VCORE_L0_D__CONFIG (0xA50CA000)
+#define BASE_MADDR_VCORE_DATA_CACHE_1 (0xA50CA100)
+#define BASE_MADDR_VCORE_DATA_CACHE_2 (0xA50CA200)
+#define BASE_MADDR_VCORE_DATA_CACHE_3 (0xA50CA300)
+#define BASE_MADDR_VCORE_DSP_TIMER0 (0xA50CA400)
+#define BASE_MADDR_VCORE_DSP_TIMER1 (0xA50CA410)
+#define BASE_MADDR_VCORE_DSP_TIMER2 (0xA50CA420)
+#define BASE_MADDR_VCORE_DSP_TIMER3 (0xA50CA430)
+#define BASE_MADDR_VCORE_MBIST_CFG (0xA50CB000)
+#define BASE_MADDR_VCORE_DELSEL_CFG (0xA50CB400)
+#define BASE_MADDR_VCORE_REPAIR_CFG (0xA50CB800)
+#define BASE_MADDR_VCORE_VCCKCTL (0xA50CBC00)
+#define BASE_MADDR_VCORE_THREAD0_LOCAL_ICM (0xA5100000)
+#define BASE_MADDR_VCORE_THREAD1_LOCAL_ICM (0xA5120000)
+#define BASE_MADDR_VCORE_THREAD2_LOCAL_ICM (0xA5140000)
+#define BASE_MADDR_VCORE_THREAD3_LOCAL_ICM (0xA5160000)
+#define BASE_MADDR_VCORE_THREAD0_CORE_CR (0xA5180000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xA5190000)
+#define BASE_MADDR_VCORE_THREAD1_CORE_CR (0xA51A0000)
+#define BASE_MADDR_VCORE_THREAD2_CORE_CR (0xA51B0000)
+#define BASE_MADDR_VCORE_THREAD3_CORE_CR (0xA51C0000)
+#define BASE_MADDR_VCORE_L1_I_TCM (0xA51E0000)
+#define BASE_MADDR_VCORE_MSP_DBGMEM (0xA5200000)
+#define BASE_MADDR_VCORE_L1_D__TCM (0xA5380000)
+#define BASE_MADDR_VCORE_MML1_DSPSDL1C (0xA53C0000)
+// (12): MAP_mcoreperi_infra
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_CR (0xA4C08000)
+#define BASE_MADDR_MCOREPERI_INFRA_ABUS_CR (0xA4C10000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xA4C18000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xA4C40000)
+#define BASE_MADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xA4C48000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xA4C48800)
+#define BASE_MADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xA4C48C00)
+#define BASE_MADDR_MCOREPERI_INFRA_SHAREDM (0xA4C80000)
+#define BASE_MADDR_MCOREPERI_INFRA_CSIF (0xA4CFA000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM0 (0xA4D00000)
+#define BASE_MADDR_MCOREPERI_INFRA_L2TCM1 (0xA4D40000)
+#define BASE_MADDR_MCOREPERI_INFRA_BTDMA (0xA4E00000)
+#define BASE_MADDR_MCOREPERI_INFRA_USTIMER (0xA4E08000)
+#define BASE_MADDR_MCOREPERI_INFRA_CLKCTRL (0xA4E80000)
+#define BASE_MADDR_MCOREPERI_INFRA_DBGMON (0xA4E90000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xA4EA0000)
+#define BASE_MADDR_MCOREPERI_INFRA_DELSEL_CFG (0xA4EA8000)
+#define BASE_MADDR_MCOREPERI_INFRA_REPAIR_CFG (0xA4EB0000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xA4EB8000)
+#define BASE_MADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xA4F00000)
+#define BASE_MADDR_MCOREPERI_INFRA_AXIMON (0xA4F10000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xA8300000)
+#define BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xA8300400)
+// (13): MAP_vcoresil2csys
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xA8310600)
+#define BASE_MADDR_VCOREAO_DBUS_CR (0xA5C10000)
+#define BASE_MADDR_VCOREAO_BUSRECORDER (0xA5C30000)
+#define BASE_MADDR_VCOREAO_L2TCM (0xA5C40000)
+#define BASE_MADDR_VCOREAO_CLKCTRL (0xA5C80000)
+#define BASE_MADDR_VCOREAO_ABUS_CR (0xA5C90000)
+#define BASE_MADDR_VCOREAO_DBGMON (0xA5CA0000)
+#define BASE_MADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xA5CC0000)
+#define BASE_MADDR_VCOREAO_DELSEL_CFG (0xA5CD0000)
+#define BASE_MADDR_VCOREAO_REPAIR_CFG (0xA5CE0000)
+// (14): MAP_hramsys
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK (0xA6000000)
+#define BASE_MADDR_HRAM_MML1_HRAM_ITC (0xA6E00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HMU (0xA6E08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xA6E10000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xA6E80000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xA6E88000)
+#define BASE_MADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xA6E90000)
+#define BASE_MADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xA6EA0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xA6EA8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xA6EB0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_SLP_CTRL (0xA6EB8000)
+#define BASE_MADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xA6EC0000)
+#define BASE_MADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xA6F00000)
+#define BASE_MADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xA6F08000)
+#define BASE_MADDR_HRAM_MML1_HRAM_GLBCON (0xA6F20000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xA6F28000)
+#define BASE_MADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xA6F30000)
+// (15): MAP_Dbgsys
+#define BASE_MADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xA0602000)
+#define BASE_MADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKCTL_REG_REGBANK (0xA0603800)
+#define BASE_MADDR_USIP0_0_USIP0 (0xA0604000)
+#define BASE_MADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xA0604400)
+#define BASE_MADDR_USIP0_1_USIP0 (0xA0604C00)
+#define BASE_MADDR_USIP1_0_USIP1 (0xA0605000)
+#define BASE_MADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xA0605400)
+#define BASE_MADDR_USIP1_1_USIP1 (0xA0605C00)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA0608000)
+#define BASE_MADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xA0609000)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA060C000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA060D000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA060E000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA0610000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA0611000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA0612000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA0613000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0614000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0615000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0616000)
+#define BASE_MADDR_IA_PDA_MON_IA_PDA_MON_REG (0xA0619000)
+#define BASE_MADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xA061B800)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA061C000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xA061E800)
+#define BASE_MADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xA061F000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0620000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0621000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA0622000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA0623000)
+#define BASE_MADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xA0628000)
+#define BASE_MADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xA0629000)
+#define BASE_MADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xA062A000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32ERK (0xA062C000)
+#define BASE_MADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xA062C100)
+#define BASE_MADDR_SHAOLIN_CM2_CM2_APB (0xA0630000)
+#define BASE_MADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xA0631000)
+#define BASE_MADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xA0632000)
+#define BASE_MADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xA0633000)
+#define BASE_MADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xA0634000)
+#define BASE_MADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xA0638000)
+#define BASE_MADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xA0639000)
+#define BASE_MADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xA063A000)
+#define BASE_MADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xA0640000)
+#define BASE_MADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xA0641000)
+#define BASE_MADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xA0641800)
+#define BASE_MADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xA0642000)
+#define BASE_MADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xA0642800)
+#define BASE_MADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xA0643000)
+#define BASE_MADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xA0643800)
+#define BASE_MADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xA0644800)
+#define BASE_MADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xA0645000)
+#define BASE_MADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xA0646000)
+#define BASE_MADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xA0647000)
+#define BASE_MADDR_MCORE0_CORE_MCORE0_CORE (0xA0648000)
+#define BASE_MADDR_MCORE0_DBUS_MCORE0_DBUS (0xA0649000)
+#define BASE_MADDR_MCORE0_PMU_MCORE0_PMU (0xA064A000)
+#define BASE_MADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xA064A800)
+#define BASE_MADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xA064AC00)
+#define BASE_MADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xA064AC40)
+#define BASE_MADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xA064AC80)
+#define BASE_MADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xA064ACC0)
+#define BASE_MADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xA064AD00)
+#define BASE_MADDR_VCORE0_CORE_VCORE0_CORE (0xA0650000)
+#define BASE_MADDR_VCORE0_DBUS_VCORE0_DBUS (0xA0651000)
+#define BASE_MADDR_VCORE0_PMU_VCORE0_PMU (0xA0652000)
+#define BASE_MADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xA0652800)
+#define BASE_MADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xA0652C00)
+#define BASE_MADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xA0652C40)
+#define BASE_MADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xA0652C80)
+#define BASE_MADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xA0652CC0)
+#define BASE_MADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xA0652D00)
+#define BASE_MADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xA0653000)
+#define BASE_MADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xA0654000)
+#define BASE_MADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xA0654400)
+#define BASE_MADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xA0654C00)
+#define BASE_MADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xA0655000)
+#define BASE_MADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xA0655800)
+#define BASE_MADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xA0656000)
+#define BASE_MADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xA0656400)
+#define BASE_MADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xA0656800)
+// (16): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA7001000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7002000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7003000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7004000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xA7005000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA7006000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xA7007000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7009000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xA700B000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA700D000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA700F000)
+// (17): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (18): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xA7970000)
+// (19): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xA8320000)
+// (20): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xA8111000)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xA8112000)
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xA8113000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xA8300400)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xA8310000)
+#define BASE_MADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xA8310400)
+#define BASE_MADDR_MODEML1_AO_VU_SM_CONFIG (0xA8310600)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xA8310680)
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xA8310700)
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xA8320000)
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xA8330000)
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xA8340000)
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xA8350000)
+// (21): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_BFE_2ND (0xA8740000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_BFE (0xA87E0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (22): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG4 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG5 (0xA8B00000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG6 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_LTE_TTR3 (0xA8B70000)
+#define BASE_MADDR_DFESYS_LTE_TTR4 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_D_GDMA_0 (0xA8E00000)
+#define BASE_MADDR_DFESYS_D_GDMA_1 (0xA8E10000)
+#define BASE_MADDR_DFESYS_D_GDMA_2 (0xA8E20000)
+#define BASE_MADDR_DFESYS_D_GDMA_3 (0xA8E30000)
+#define BASE_MADDR_DFESYS_D_GDMA_4 (0xA8E40000)
+#define BASE_MADDR_DFESYS_D_GDMA_5 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA8EA0000)
+// (23): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (24): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (25): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_MTRK (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+// (26): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA001000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xAA001020)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA002000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xAA003000)
+#define BASE_MADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xAA003020)
+// (27): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_RESERVED0 (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_SHR_POOL (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT1 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL (0xAA490000)
+#define BASE_MADDR_CM_NR_DVTCRC (0xAA4A0000)
+#define BASE_MADDR_CM_NR_PBCH_DVTCRC (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_DMP (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_HBUSPROT0 (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xAA4E0000)
+#define BASE_MADDR_CM_NR_MML1_HBUS_MI (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xAA510000)
+#define BASE_MADDR_CM_NR_RESERVED1 (0xAA520000)
+#define BASE_MADDR_CM_NR_RESERVED2 (0xAA530000)
+#define BASE_MADDR_CM_NR_RESERVED3 (0xAA540000)
+#define BASE_MADDR_CM_NR_RESERVED4 (0xAA550000)
+#define BASE_MADDR_CM_NR_RESERVED5 (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xAA570000)
+// (28): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+// (29): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC70000)
+// (30): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xAAE70000)
+// (31): MAP_bigram0
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+// (32): MAP_inr0
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (33): MAP_rxbrp0
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_RXBRP_BUS_CONFIG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_DMC_LTE_CE (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_1 (0xACB22000)
+#define BASE_MADDR_RXBRP0_LTE_CE_TOP_2 (0xACB23000)
+#define BASE_MADDR_RXBRP0_DMC_DEMOD (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_1 (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_REG_2 (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (34): MAP_rake0
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_NADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_NADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_NADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_NADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_NADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_NADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_NADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_NADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_NADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_NADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_NADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_NADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_NADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_NADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_NADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_NADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_NADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_NADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_NADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_NADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_NADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_NADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_NADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_NADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_NADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_NADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_NADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_NADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_NADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_NADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_NADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_NADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_NADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_NADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_NADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_NADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_NADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_NADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_NADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_NADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_NADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_NADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_NADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_NADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_NADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_NADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_NADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_NADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_NADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_NADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_NADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_NADDR_VCORE_EINTC (0xB505C800)
+#define BASE_NADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_NADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_NADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_NADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_NADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_NADDR_VCORE_D2D (0xB50A1800)
+#define BASE_NADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_NADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_NADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_NADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_NADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_NADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_NADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_NADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_NADDR_VCORE_MISC (0xB50C6400)
+#define BASE_NADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_NADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_NADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_NADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_NADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_NADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_NADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_NADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_NADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_NADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_NADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_NADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_NADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_NADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_NADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_NADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_NADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_NADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_NADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_NADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_NADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_NADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_NADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_NADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_NADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_NADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_NADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_NADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_NADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_NADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_NADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_NADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_NADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_NADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_NADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_NADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_NADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_NADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_NADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_NADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_NADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_NADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_NADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_NADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_NADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_NADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_NADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_NADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_NADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_NADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_NADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_NADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_NADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_NADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_NADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_NADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_NADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_NADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_NADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_NADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_NADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_NADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_NADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_NADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_NADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_NADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_NADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_NADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_NADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_NADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_NADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_NADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_NADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_NADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_NADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_NADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_NADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_NADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_NADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_NADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_NADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_NADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_NADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_NADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_NADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_NADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_NADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_NADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_NADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_NADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_NADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_NADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_NADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_NADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_NADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_NADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_NADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_NADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_NADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_NADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_NADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_NADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_NADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_NADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_NADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_NADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_NADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_NADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_NADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_NADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_NADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_NADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_NADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_NADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_NADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_NADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_NADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_NADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_NADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_NADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_NADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_NADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_NADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_NADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_NADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_NADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_NADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_NADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_NADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_NADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_NADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_NADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_NADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_NADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_NADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_NADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_NADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_NADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_NADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_NADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_NADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_CONFIG_ADR_IF (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_MISC_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_SMI_B_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2SUB_INFRA_CONFIG (0xB04D0000)
+#define BASE_ADDR_MDINFRA_RSI_CONFIG (0xB04E0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_ELM_B (0xB0530000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_ABM (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_COIFNG (0xB02C0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_DELSEL_CFG (0xB0341000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CORE_DELSEL_CFG (0xB0342000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_CM2_DELSEL_CFG (0xB0343000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_BUSMPU_INFRA (0xB0370000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_MDMCU_RSI (0xB03A0000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_USIP2_ITCM (0xB0A00000)
+#define BASE_ADDR_USIP_USIP2_DTCM (0xB0A40000)
+#define BASE_ADDR_USIP_USIP2_DEBUG (0xB0A80000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_MCORE0_CBSCHEDULER (0xB405C000)
+#define BASE_ADDR_MCORE0_EINTC (0xB405C800)
+#define BASE_ADDR_MCORE0_CLK_CTRL (0xB40A0040)
+#define BASE_ADDR_MCORE0_DSPRSTCTRL (0xB40A0100)
+#define BASE_ADDR_MCORE0_MML1_DSPRSTCTRL (0xB40A0140)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL2 (0xB40A0180)
+#define BASE_ADDR_MCORE0_MC0_DSPRSTCTRL3 (0xB40A01C0)
+#define BASE_ADDR_MCORE0_D2D (0xB40A1800)
+#define BASE_ADDR_MCORE0_PMU (0xB40A1C00)
+#define BASE_ADDR_MCORE0_L0_I__CONFIG (0xB40C0000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_1 (0xB40C1000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_2 (0xB40C2000)
+#define BASE_ADDR_MCORE0_MML1_DSPSIL0C_TOP_3 (0xB40C3000)
+#define BASE_ADDR_MCORE0_L1_I__CONFIG (0xB40C4000)
+#define BASE_ADDR_MCORE0_DBUS_CFG (0xB40C5000)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON (0xB40C6000)
+#define BASE_ADDR_MCORE0_MISC (0xB40C6400)
+#define BASE_ADDR_MCORE0_DSPLOG (0xB40C6800)
+#define BASE_ADDR_MCORE0_SMT_CTI (0xB40C6C00)
+#define BASE_ADDR_MCORE0_BUS_RECORDER (0xB40C7000)
+#define BASE_ADDR_MCORE0_DBGC (0xB40C7800)
+#define BASE_ADDR_MCORE0_L1_D__CFG (0xB40C8000)
+#define BASE_ADDR_MCORE0_L0_D__CONFIG (0xB40CA000)
+#define BASE_ADDR_MCORE0_DATA_CACHE_1 (0xB40CA100)
+#define BASE_ADDR_MCORE0_DATA_CACHE_2 (0xB40CA200)
+#define BASE_ADDR_MCORE0_DATA_CACHE_3 (0xB40CA300)
+#define BASE_ADDR_MCORE0_DSP_TIMER0 (0xB40CA400)
+#define BASE_ADDR_MCORE0_DSP_TIMER1 (0xB40CA410)
+#define BASE_ADDR_MCORE0_DSP_TIMER2 (0xB40CA420)
+#define BASE_ADDR_MCORE0_DSP_TIMER3 (0xB40CA430)
+#define BASE_ADDR_MCORE0_MBIST_CFG (0xB40CB000)
+#define BASE_ADDR_MCORE0_DELSEL_CFG (0xB40CB400)
+#define BASE_ADDR_MCORE0_REPAIR_CFG (0xB40CB800)
+#define BASE_ADDR_MCORE0_MCCKCTL (0xB40CBC00)
+#define BASE_ADDR_MCORE0_THREAD0_LOCAL_ICM (0xB4100000)
+#define BASE_ADDR_MCORE0_THREAD1_LOCAL_ICM (0xB4120000)
+#define BASE_ADDR_MCORE0_THREAD2_LOCAL_ICM (0xB4140000)
+#define BASE_ADDR_MCORE0_THREAD3_LOCAL_ICM (0xB4160000)
+#define BASE_ADDR_MCORE0_THREAD0_CORE_CR (0xB4180000)
+#define BASE_ADDR_MCORE0_MML1_DSPMCORE_TOP_CORE_SMT (0xB4190000)
+#define BASE_ADDR_MCORE0_THREAD1_CORE_CR (0xB41A0000)
+#define BASE_ADDR_MCORE0_THREAD2_CORE_CR (0xB41B0000)
+#define BASE_ADDR_MCORE0_THREAD3_CORE_CR (0xB41C0000)
+#define BASE_ADDR_MCORE0_L1_I_TCM (0xB41E0000)
+#define BASE_ADDR_MCORE0_MSP_DBGMEM (0xB4200000)
+#define BASE_ADDR_MCORE0_L1_D__TCM (0xB4380000)
+#define BASE_ADDR_MCORE0_MML1_DSPSDL1C (0xB43C0000)
+#define BASE_ADDR_VCORE_TH0_L1MC__CR (0xB5050000)
+#define BASE_ADDR_VCORE_TH1_L1MC__CR (0xB5051000)
+#define BASE_ADDR_VCORE_TH2_L1MC__CR (0xB5052000)
+#define BASE_ADDR_VCORE_TH0_BLAZE (0xB5054000)
+#define BASE_ADDR_VCORE_TH1_BLAZE (0xB5055000)
+#define BASE_ADDR_VCORE_TH2_BLAZE (0xB5056000)
+#define BASE_ADDR_VCORE_EINTC (0xB505C800)
+#define BASE_ADDR_VCORE_TH0_L1MC__MEM (0xB5060000)
+#define BASE_ADDR_VCORE_TH1_L1MC__MEM (0xB5070000)
+#define BASE_ADDR_VCORE_TH2_L1MC__MEM (0xB5080000)
+#define BASE_ADDR_VCORE_CLK_CTRL (0xB50A0040)
+#define BASE_ADDR_VCORE_DSPRSTCTRL (0xB50A0100)
+#define BASE_ADDR_VCORE_D2D (0xB50A1800)
+#define BASE_ADDR_VCORE_PMU (0xB50A1C00)
+#define BASE_ADDR_VCORE_SLV_SCHEDULER (0xB50B0000)
+#define BASE_ADDR_VCORE_HLSU (0xB50B0400)
+#define BASE_ADDR_VCORE_L0_I__CONFIG (0xB50C0000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_1 (0xB50C1000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_2 (0xB50C2000)
+#define BASE_ADDR_VCORE_MML1_DSPSIL0C_TOP_3 (0xB50C3000)
+#define BASE_ADDR_VCORE_L1_I__CONFIG (0xB50C4000)
+#define BASE_ADDR_VCORE_DBUS_CFG (0xB50C5000)
+#define BASE_ADDR_VCORE_DEBUG_FLAG_MON (0xB50C6000)
+#define BASE_ADDR_VCORE_MISC (0xB50C6400)
+#define BASE_ADDR_VCORE_DSPLOG (0xB50C6800)
+#define BASE_ADDR_VCORE_SMT_CTI (0xB50C6C00)
+#define BASE_ADDR_VCORE_BUS_RECORDER (0xB50C7000)
+#define BASE_ADDR_VCORE_DBGC (0xB50C7800)
+#define BASE_ADDR_VCORE_L1_D__CFG (0xB50C8000)
+#define BASE_ADDR_VCORE_L0_D__CONFIG (0xB50CA000)
+#define BASE_ADDR_VCORE_DATA_CACHE_1 (0xB50CA100)
+#define BASE_ADDR_VCORE_DATA_CACHE_2 (0xB50CA200)
+#define BASE_ADDR_VCORE_DATA_CACHE_3 (0xB50CA300)
+#define BASE_ADDR_VCORE_DSP_TIMER0 (0xB50CA400)
+#define BASE_ADDR_VCORE_DSP_TIMER1 (0xB50CA410)
+#define BASE_ADDR_VCORE_DSP_TIMER2 (0xB50CA420)
+#define BASE_ADDR_VCORE_DSP_TIMER3 (0xB50CA430)
+#define BASE_ADDR_VCORE_MBIST_CFG (0xB50CB000)
+#define BASE_ADDR_VCORE_DELSEL_CFG (0xB50CB400)
+#define BASE_ADDR_VCORE_REPAIR_CFG (0xB50CB800)
+#define BASE_ADDR_VCORE_VCCKCTL (0xB50CBC00)
+#define BASE_ADDR_VCORE_THREAD0_LOCAL_ICM (0xB5100000)
+#define BASE_ADDR_VCORE_THREAD1_LOCAL_ICM (0xB5120000)
+#define BASE_ADDR_VCORE_THREAD2_LOCAL_ICM (0xB5140000)
+#define BASE_ADDR_VCORE_THREAD3_LOCAL_ICM (0xB5160000)
+#define BASE_ADDR_VCORE_THREAD0_CORE_CR (0xB5180000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE_SMT (0xB5190000)
+#define BASE_ADDR_VCORE_THREAD1_CORE_CR (0xB51A0000)
+#define BASE_ADDR_VCORE_THREAD2_CORE_CR (0xB51B0000)
+#define BASE_ADDR_VCORE_THREAD3_CORE_CR (0xB51C0000)
+#define BASE_ADDR_VCORE_L1_I_TCM (0xB51E0000)
+#define BASE_ADDR_VCORE_MSP_DBGMEM (0xB5200000)
+#define BASE_ADDR_VCORE_L1_D__TCM (0xB5380000)
+#define BASE_ADDR_VCORE_MML1_DSPSDL1C (0xB53C0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_CR (0xB4C08000)
+#define BASE_ADDR_MCOREPERI_INFRA_ABUS_CR (0xB4C10000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBUS_BUSRECORDER0 (0xB4C18000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSEMAPHORE (0xB4C40000)
+#define BASE_ADDR_MCOREPERI_INFRA_DSPSCHEDULER (0xB4C48000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_DSPM2VSCHEDULER (0xB4C48800)
+#define BASE_ADDR_MCOREPERI_INFRA_MCORESYS_DSPM2VSCHEDULER2 (0xB4C48C00)
+#define BASE_ADDR_MCOREPERI_INFRA_SHAREDM (0xB4C80000)
+#define BASE_ADDR_MCOREPERI_INFRA_CSIF (0xB4CFA000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM0 (0xB4D00000)
+#define BASE_ADDR_MCOREPERI_INFRA_L2TCM1 (0xB4D40000)
+#define BASE_ADDR_MCOREPERI_INFRA_BTDMA (0xB4E00000)
+#define BASE_ADDR_MCOREPERI_INFRA_USTIMER (0xB4E08000)
+#define BASE_ADDR_MCOREPERI_INFRA_CLKCTRL (0xB4E80000)
+#define BASE_ADDR_MCOREPERI_INFRA_DBGMON (0xB4E90000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_PERICK_ABUS_REG (0xB4EA0000)
+#define BASE_ADDR_MCOREPERI_INFRA_DELSEL_CFG (0xB4EA8000)
+#define BASE_ADDR_MCOREPERI_INFRA_REPAIR_CFG (0xB4EB0000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MCOREPERI_DBUS2_MPERIDBUS2_REG_INST (0xB4EB8000)
+#define BASE_ADDR_MCOREPERI_INFRA_MML1_MPERI_BUSCK_ABUS_REG (0xB4F00000)
+#define BASE_ADDR_MCOREPERI_INFRA_AXIMON (0xB4F10000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM (0xB8300000)
+#define BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_DBGMON (0xB8310600)
+#define BASE_ADDR_VCOREAO_DBUS_CR (0xB5C10000)
+#define BASE_ADDR_VCOREAO_BUSRECORDER (0xB5C30000)
+#define BASE_ADDR_VCOREAO_L2TCM (0xB5C40000)
+#define BASE_ADDR_VCOREAO_CLKCTRL (0xB5C80000)
+#define BASE_ADDR_VCOREAO_ABUS_CR (0xB5C90000)
+#define BASE_ADDR_VCOREAO_DBGMON (0xB5CA0000)
+#define BASE_ADDR_VCOREAO_MML1_VPERI_PMUCK_ABUS_REG (0xB5CC0000)
+#define BASE_ADDR_VCOREAO_DELSEL_CFG (0xB5CD0000)
+#define BASE_ADDR_VCOREAO_REPAIR_CFG (0xB5CE0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK (0xB6000000)
+#define BASE_ADDR_HRAM_MML1_HRAM_ITC (0xB6E00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HMU (0xB6E08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMCK_ABUS_REG (0xB6E10000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXDDM_NR_HGRX (0xB6E80000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXCPC_NR_HGRX (0xB6E88000)
+#define BASE_ADDR_HRAM_MML1_HRAM_VCORE0_NR_HGRX (0xB6E90000)
+#define BASE_ADDR_HRAM_MML1_HRAM_RXT2F_NR_HGRX (0xB6EA0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CS_NR_HGRX (0xB6EA8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_CM_NR_HGRX (0xB6EB0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_SLP_CTRL (0xB6EB8000)
+#define BASE_ADDR_HRAM_MML1_HRAM_IRQ_CTRL (0xB6EC0000)
+#define BASE_ADDR_HRAM_MML1_HRAM_HRAMBUSCK_ABUS_REG (0xB6F00000)
+#define BASE_ADDR_HRAM_MML1_HRAM_DBGMON_WRAP (0xB6F08000)
+#define BASE_ADDR_HRAM_MML1_HRAM_GLBCON (0xB6F20000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_DELSEL_CFG_WRAP (0xB6F28000)
+#define BASE_ADDR_HRAM_MML1_HRAM_BRICK_TOP_REPAIR_CFG_WRAP (0xB6F30000)
+#define BASE_ADDR_DAP_2ND_ROM_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REGBANK_MDPERISYS_MISC_REGBANK (0xB0602000)
+#define BASE_ADDR_DBGMON_PAR_TOP_DBGMON_PAR (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKCTL_REG_REGBANK (0xB0603800)
+#define BASE_ADDR_USIP0_0_USIP0 (0xB0604000)
+#define BASE_ADDR_USIP0_INT_DBG_USIP0_INT_DBG (0xB0604400)
+#define BASE_ADDR_USIP0_1_USIP0 (0xB0604C00)
+#define BASE_ADDR_USIP1_0_USIP1 (0xB0605000)
+#define BASE_ADDR_USIP1_INT_DBG_USIP1_INT_DBG (0xB0605400)
+#define BASE_ADDR_USIP1_1_USIP1 (0xB0605C00)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB0608000)
+#define BASE_ADDR_MDINFRA_MISC_MDINFRA_MISC_REG (0xB0609000)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB060C000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB060D000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB060E000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB0610000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB0611000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB0612000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB0613000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0614000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0615000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0616000)
+#define BASE_ADDR_IA_PDA_MON_IA_PDA_MON_REG (0xB0619000)
+#define BASE_ADDR_IA_DEBUG_PERI_MISC_IA_DEBUG_PERI_MISC_REG_WRAPPER (0xB061B800)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB061C000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_MISC_SHAOLIN_DEBUG_PERI_MISC_REG_WRAPPER (0xB061E800)
+#define BASE_ADDR_SHAOLIN_BUS_CONFIG_SHAOLIN_BUS_CONFIG (0xB061F000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0620000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0621000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB0622000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB0623000)
+#define BASE_ADDR_BUSCFG_MODEML1_AO_BUS_CONFIG (0xB0628000)
+#define BASE_ADDR_MDL1_TOPSM_MODEML1_AO_BUS_CONFIG (0xB0629000)
+#define BASE_ADDR_RFSLPC_MODEML1_AO_BUS_CONFIG (0xB062A000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32ERK (0xB062C000)
+#define BASE_ADDR_____RAKE_BUSDBG_STATUS_DBGAPB_BUS_STATUS (0xB062C100)
+#define BASE_ADDR_SHAOLIN_CM2_CM2_APB (0xB0630000)
+#define BASE_ADDR_SHAOLIN_CORE0__TPZ_BIU_EJT_APB (0xB0631000)
+#define BASE_ADDR_SHAOLIN_CORE1_TPZ_BIU_EJT_APB (0xB0632000)
+#define BASE_ADDR_SHAOLIN_CORE2__TPZ_BIU_EJT_APB (0xB0633000)
+#define BASE_ADDR_SHAOLIN_CORE3_TPZ_BIU_EJT_APB (0xB0634000)
+#define BASE_ADDR_MDMCU_BUSMON_AXIMON_HCLK_DOMAIN_0 (0xB0638000)
+#define BASE_ADDR_MDMCU_BUS_CONFIG_MDMCU_BUS_CONFIG (0xB0639000)
+#define BASE_ADDR_USIP_BUS_CONFIG_USIP_BUS_CONFIG_REG (0xB063A000)
+#define BASE_ADDR_MCOREINFRA_BUSMON_MCOREINFRA_BUSMON (0xB0640000)
+#define BASE_ADDR_MCOREINFRA_ABUS_MCOREINFRA_ABUS (0xB0641000)
+#define BASE_ADDR_MCOREINFRA_DBGMON_MCOREINFRA_DBGMON (0xB0641800)
+#define BASE_ADDR_MCORESYS_DBGMON_MCORESYS_DBGMON (0xB0642000)
+#define BASE_ADDR_MCORESYS_MCOREBUSCK_ABUS_MCORESYS_MCOREBUSCK_ABUS (0xB0642800)
+#define BASE_ADDR_MCORESYS_MCORECK_ABUS_MCORESYS_MCORECK_ABUS (0xB0643000)
+#define BASE_ADDR_MCORESYS_PERICK_ABUS_MCORESYS_PERICK_ABUS (0xB0643800)
+#define BASE_ADDR_MCORESYS_PERICK_DBUS_MCORESYS_PERICK_DBUS (0xB0644800)
+#define BASE_ADDR_MCORESYS_BUSRECORDER0_MCORESYS_BUSRECORDER0 (0xB0645000)
+#define BASE_ADDR_MCORESYS_MCORECK_DBUS_MCORESYS_MCORECK_DBUS (0xB0646000)
+#define BASE_ADDR_MCORESYS_BUSMON_MCORESYS_BUSMON (0xB0647000)
+#define BASE_ADDR_MCORE0_CORE_MCORE0_CORE (0xB0648000)
+#define BASE_ADDR_MCORE0_DBUS_MCORE0_DBUS (0xB0649000)
+#define BASE_ADDR_MCORE0_PMU_MCORE0_PMU (0xB064A000)
+#define BASE_ADDR_MCORE0_BUS_RECORDER_MCORE0_BUS_RECORDER (0xB064A800)
+#define BASE_ADDR_MCORE0_CONFIG_TH0____________MCORE0_CONFIG_TH0 (0xB064AC00)
+#define BASE_ADDR_MCORE0_CONFIG_TH1____________MCORE0_CONFIG_TH1 (0xB064AC40)
+#define BASE_ADDR_MCORE0_CONFIG_TH2____________MCORE0_CONFIG_TH2 (0xB064AC80)
+#define BASE_ADDR_MCORE0_CONFIG_TH3____________MCORE0_CONFIG_TH3 (0xB064ACC0)
+#define BASE_ADDR_MCORE0_DEBUG_FLAG_MON_MCORE0_DEBUG_FLAG_MON (0xB064AD00)
+#define BASE_ADDR_VCORE0_CORE_VCORE0_CORE (0xB0650000)
+#define BASE_ADDR_VCORE0_DBUS_VCORE0_DBUS (0xB0651000)
+#define BASE_ADDR_VCORE0_PMU_VCORE0_PMU (0xB0652000)
+#define BASE_ADDR_VCORE0_BUS_RECORDER_VCORE0_BUS_RECORDER (0xB0652800)
+#define BASE_ADDR_VCORE0_CONFIG_TH0____________VCORE0_CONFIG_TH0 (0xB0652C00)
+#define BASE_ADDR_VCORE0_CONFIG_TH1____________VCORE0_CONFIG_TH1 (0xB0652C40)
+#define BASE_ADDR_VCORE0_CONFIG_TH2____________VCORE0_CONFIG_TH2 (0xB0652C80)
+#define BASE_ADDR_VCORE0_CONFIG_TH3____________VCORE0_CONFIG_TH3 (0xB0652CC0)
+#define BASE_ADDR_VCORE0_DEBUG_FLAG_MON_VCORE0_DEBUG_FLAG_MON (0xB0652D00)
+#define BASE_ADDR_VCOREHRAM_AO_CR_VCOREHRAM_AO_CR (0xB0653000)
+#define BASE_ADDR_SIL2CSYS_DBGMON_SIL2CSYS_DBGMON (0xB0654000)
+#define BASE_ADDR_SIL2CSYS_VCORECK_ABUS_SIL2CSYS_VCORECK_ABUS (0xB0654400)
+#define BASE_ADDR_SIL2CSYS_PMUCK_ABUS_SIL2CSYS_PMUCK_ABUS (0xB0654C00)
+#define BASE_ADDR_SIL2CSYS_BUSRECORDER_SIL2CSYS_BUSRECORDER (0xB0655000)
+#define BASE_ADDR_SIL2CSYS_PMUCK_DBUS_SIL2CSYS_PMUCK_DBUS (0xB0655800)
+#define BASE_ADDR_HRAMSYS_DBGMON_HRAMSYS_DBGMON (0xB0656000)
+#define BASE_ADDR_HRAMSYS_HRAMCK_ABUS_HRAMSYS_HRAMCK_ABUS (0xB0656400)
+#define BASE_ADDR_HRAMSYS_HRAMBUSCK_ABUS_HRAMSYS_HRAMBUSCK_ABUS (0xB0656800)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB7001000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7002000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7003000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7004000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_DELSEL_CFG (0xB7005000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB7006000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CAT_REPAIR_CFG (0xB7007000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7009000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP (0xB700B000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCEPP_TOP_1 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB700D000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB700F000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_BUS_CONFIG_REG (0xB7970000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_PAR_AO_FROM_MODEML1_AO (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 (0xB8111000)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 (0xB8112000)
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG (0xB8113000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM1 (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_U_MCORE_PAR_AO_CR (0xB8300400)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM (0xB8310000)
+#define BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_CR (0xB8310400)
+#define BASE_ADDR_MODEML1_AO_VU_SM_CONFIG (0xB8310600)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_VCOREHRAM_VU_SM_1 (0xB8310680)
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_2 (0xB8310700)
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG (0xB8320000)
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG (0xB8330000)
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG (0xB8340000)
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG (0xB8350000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_BFE_2ND (0xB8740000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_BFE (0xB87E0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_MBIST_DELSEL_CFG_WRAP (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG4 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG5 (0xB8B00000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG6 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_LTE_TTR3 (0xB8B70000)
+#define BASE_ADDR_DFESYS_LTE_TTR4 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_D_GDMA_0 (0xB8E00000)
+#define BASE_ADDR_DFESYS_D_GDMA_1 (0xB8E10000)
+#define BASE_ADDR_DFESYS_D_GDMA_2 (0xB8E20000)
+#define BASE_ADDR_DFESYS_D_GDMA_3 (0xB8E30000)
+#define BASE_ADDR_DFESYS_D_GDMA_4 (0xB8E40000)
+#define BASE_ADDR_DFESYS_D_GDMA_5 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGRF_2T4R_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB8EA0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_MTRK (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA001000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG_WRAP (0xBA001020)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA002000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_DELSEL_CFG_WRAP (0xBA003000)
+#define BASE_ADDR_TXSYS_NR_TXNR_SUBSYS_MBIST_CAT_REPAIR_CFG (0xBA003020)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_RESERVED0 (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_SHR_POOL (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT1 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL (0xBA490000)
+#define BASE_ADDR_CM_NR_DVTCRC (0xBA4A0000)
+#define BASE_ADDR_CM_NR_PBCH_DVTCRC (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_DMP (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_HBUSPROT0 (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_SHR_POOL (0xBA4E0000)
+#define BASE_ADDR_CM_NR_MML1_HBUS_MI (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_REPAIR_CFG (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_DELSEL_CFG_WRAP (0xBA510000)
+#define BASE_ADDR_CM_NR_RESERVED1 (0xBA520000)
+#define BASE_ADDR_CM_NR_RESERVED2 (0xBA530000)
+#define BASE_ADDR_CM_NR_RESERVED3 (0xBA540000)
+#define BASE_ADDR_CM_NR_RESERVED4 (0xBA550000)
+#define BASE_ADDR_CM_NR_RESERVED5 (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_BUS_CONFIG_REG (0xBA570000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_DELSEL_CFG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_MBIST_CFG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC70000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_5 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_6 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_RXBRP_BUS_CONFIG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_DMC_LTE_CE (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_1 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_LTE_CE_TOP_2 (0xBCB23000)
+#define BASE_ADDR_RXBRP0_DMC_DEMOD (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_1 (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_REG_2 (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from Petrus_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+////#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_ADDR_MML2_MCU_MMU
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+//#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+//#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+//#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDMCU_MCUSYS_MBIST_CONFIG
+//#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+////#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_PDA_MONITER
+//#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+//#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_PDA_MONITER
+//#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDMCU_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_NADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MT6297_FPGA_H__ */
\ No newline at end of file
diff --git a/mcu/interface/driver/regbase/md97/reg_base_PETRUS_FPGA_username.h b/mcu/interface/driver/regbase/md97/reg_base_PETRUS_FPGA_username.h
new file mode 100644
index 0000000..3776580
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_PETRUS_FPGA_username.h
@@ -0,0 +1,163 @@
+#ifndef __REG_BASE_MT6297_FPGA_USERNAME_H__
+#define __REG_BASE_MT6297_FPGA_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F60000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F60000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1F60000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MT6297_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97/reg_base_md97.h b/mcu/interface/driver/regbase/md97/reg_base_md97.h
new file mode 100644
index 0000000..ae028ec
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_md97.h
@@ -0,0 +1,180 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * reg_base_md97.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for chipset register base and global configuration registers
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _REG_BASE_MD97_H
+#define _REG_BASE_MD97_H
+
+#if defined(MT6297)
+ #ifdef __FPGA__
+ #include "reg_base_MT6297_FPGA.h"
+ #else
+ #include "reg_base_MT6297.h"
+ #endif /*__FPGA__*/
+#elif defined(MT6885)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MT6885_FPGA.h"
+ #else
+ #include "reg_base_MT6885.h"
+ #endif /*__FPGA__*/
+#elif defined(MT6873)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6873.h"
+ #endif
+#elif defined(MT6853)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6853.h"
+ #endif
+#elif defined(MT6833)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6833.h"
+ #endif
+#elif defined(MT6877)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6877.h"
+ #endif
+#elif defined(CHIP10992)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_CHIP10992.h"
+ #endif
+#else
+ #error "unknown project"
+#endif
+
+#endif /* !_REG_BASE_MD97_H */
+
diff --git a/mcu/interface/driver/regbase/md97/reg_base_username_md97.h b/mcu/interface/driver/regbase/md97/reg_base_username_md97.h
new file mode 100644
index 0000000..1fd6d03
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97/reg_base_username_md97.h
@@ -0,0 +1,53 @@
+#ifndef __REG_BASE_USERNAME_MD97_H__
+#define __REG_BASE_USERNAME_MD97_H__
+
+/* This header file only includes product specific header files.
+ * Please add your reg base difinitions to correct product specific file. */
+
+#if defined(MT6297)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MT6297_FPGA_username.h"
+ #else/* not FPGA */
+ #include "reg_base_MT6297_username.h"
+ #endif
+#elif defined(MT6885)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MT6885_FPGA_username.h"
+ #else/* not FPGA */
+ #include "reg_base_MT6885_username.h"
+ #endif
+#elif defined(MT6873)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6873_username.h"
+ #endif
+#elif defined(MT6853)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6853_username.h"
+ #endif
+#elif defined(MT6833)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6833_username.h"
+ #endif
+#elif defined(MT6877)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_MT6877_username.h"
+ #endif
+#elif defined(CHIP10992)/* only for FPGA */
+ #ifdef __FPGA__
+ #error "unknown project(defined FPGA)"
+ #else/* not FPGA */
+ #include "reg_base_CHIP10992_username.h"
+ #endif
+#else
+ #error "unknown project"
+#endif
+
+#endif /* end of __REG_BASE_USERNAME_MD97_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/cpu_info_MT6297_I7200.h b/mcu/interface/driver/regbase/md97p/cpu_info_MT6297_I7200.h
new file mode 100644
index 0000000..f75b4d6
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/cpu_info_MT6297_I7200.h
@@ -0,0 +1,20 @@
+#ifndef __CPU_INFO_MT6297_H__
+#define __CPU_INFO_MT6297_H__
+
+#if defined(__MD97_IS_2CORES__)
+
+#define SYS_MCU_NUM_CORE (2)
+#define SYS_MCU_NUM_VPE (6)
+#define SYS_MCU_NUM_TC (12)
+
+#else
+
+#define SYS_MCU_NUM_CORE (4)
+#define SYS_MCU_NUM_VPE (12)
+#define SYS_MCU_NUM_TC (24)
+
+#endif
+
+#define SYS_MCU_GIC_EXIST (0)
+
+#endif /* __CPU_INFO_MT6297_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/cpu_info_md97p.h b/mcu/interface/driver/regbase/md97p/cpu_info_md97p.h
new file mode 100644
index 0000000..a831d85
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/cpu_info_md97p.h
@@ -0,0 +1,10 @@
+#ifndef __CPU_INFO_MD97P_H__
+#define __CPU_INFO_MD97P_H__
+
+#if defined(MERCURY)
+ #include "cpu_info_MT6297_I7200.h"
+#else
+ #error "unknown MDMCU version"
+#endif
+
+#endif /* __CPU_INFO_MD97P_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/reg_base_MERCURY.h b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY.h
new file mode 100644
index 0000000..1b89e75
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY.h
@@ -0,0 +1,5266 @@
+#ifndef __BASE_REG_H__
+#define __BASE_REG_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from MMW_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): Lookup table
+// (4): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (5): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MDL1_MODEM_TOPSM_PROTECT (0xA0080000)
+#define BASE_MADDR_MDPERI_COMDMA (0xA0090000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_MDRXSYS_SRAM_AO (0xA0190000)
+#define BASE_MADDR_MDPERI_VU_SM_CONGIF_0 (0xA0191000)
+#define BASE_MADDR_MDPERI_VU_SM_CONGIF_1 (0xA0192000)
+#define BASE_MADDR_MDPERI_MDRXAO_CONFIG (0xA0193000)
+#define BASE_MADDR_MDPERI_RESERVED0 (0xA0194000)
+#define BASE_MADDR_MDPERI_BRP_SRAM_AO (0xA01A0000)
+#define BASE_MADDR_MDPERI_NRL2_SRAM_AO (0xA01B0000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_SRAM_AO (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (6): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_BUS2X_REG (0xA0440000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_SHAOLIN_SEMAPHORE (0xA0460000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_BUS4X_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_HW_LOG (0xA0500000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0540000)
+#define BASE_MADDR_MDINFRA_TRACE_NR_TOP_1 (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (7): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_RESERVED0 (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FE00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FF00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_AO_MISC_CTRL (0xA0260000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_SRAM_AO (0xA0270000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_MEM_DELSEL_CFG (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_MEM_DELSEL_CFG (0xA0281000)
+#define BASE_MADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE1_MEM_DELSEL_CFG (0xA0282000)
+#define BASE_MADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE2_MEM_DELSEL_CFG (0xA0283000)
+#define BASE_MADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE3_MEM_DELSEL_CFG (0xA0284000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_CONFIG (0xA02C0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__BUSMPU_INFRA (0xA02D0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_COREBUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_IA_MACRO_DELSEL_ADR_IF (0xA03B0000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MBIST_MDCORE_FOR_CFG_DELSEL_CFG_WRAP (0xA03B1000)
+// (8): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_MBIST_REPAIR_TOP_CFG_WRAP (0xA0D10000)
+#define BASE_MADDR_USIP_MBIST_DELSEL_TOP_CFG_WRAP (0xA0D20000)
+#define BASE_MADDR_USIP_USIPCORE_BUS_CONFIG (0xA0D30000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (9): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_UL_CIPHER_CONFIG (0xA2014000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_1 (0xA2036000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_2 (0xA2037000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG_SRAM (0xA2038000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_4 (0xA2039000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_ST (0xA203A000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_0 (0xA203B000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_1 (0xA203C000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_2 (0xA203D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_3 (0xA203E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_4 (0xA203F000)
+#define BASE_MADDR_NRL2_NRL2_DL_META_AGG (0xA2040000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC2 (0xA2041000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC3 (0xA2042000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC4 (0xA2043000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC5 (0xA2044000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC6 (0xA2045000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC7 (0xA2046000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC8 (0xA2047000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_PPRO (0xA2048000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC2 (0xA2049000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC3 (0xA204A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC4 (0xA204B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC5 (0xA204C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC6 (0xA204D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC7 (0xA204E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC8 (0xA204F000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_PPRO (0xA2050000)
+#define BASE_MADDR_NRL2_NRL2_BUS_CFG (0xA2051000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_PPRO_QP (0xA2052000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_0 (0xA2053000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_1 (0xA2054000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_2 (0xA2055000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_3 (0xA2056000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_4 (0xA2057000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_5 (0xA2058000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_6 (0xA2059000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_7 (0xA205A000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_8 (0xA205B000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC0 (0xA205C000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC1 (0xA205D000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC2 (0xA205E000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC3 (0xA205F000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC4 (0xA2060000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC5 (0xA2061000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC6 (0xA2062000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC7 (0xA2063000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC8 (0xA2064000)
+// (10): MAP_MCORE_Program_private
+#define BASE_ADDR_MCORE_L1ITCM (0x00000000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0 (0x01400000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1 (0x01440000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2 (0x01480000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3 (0x014C0000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0_MIRROR1 (0x01500000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1_MIRROR1 (0x01540000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2_MIRROR1 (0x01580000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3_MIRROR1 (0x015C0000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0_MIRROR2 (0x01600000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1_MIRROR2 (0x01640000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2_MIRROR2 (0x01680000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3_MIRROR2 (0x016C0000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0_MIRROR3 (0x01700000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1_MIRROR3 (0x01740000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2_MIRROR3 (0x01780000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3_MIRROR3 (0x017C0000)
+// (11): MAP_MCORE_Data_private
+#define BASE_ADDR_MCORE_SONIC (0x00040000)
+#define BASE_ADDR_MCORE_L0I_CACHE (0x00050000)
+#define BASE_ADDR_MCORE_L0D_CACHE (0x00051000)
+#define BASE_ADDR_MCORE_TIMER (0x00052000)
+#define BASE_ADDR_MCORE_EXCTRL (0x00053000)
+#define BASE_ADDR_MCORE_PC_MONITOR (0x00054000)
+#define BASE_ADDR_MCORE_PROFILING_UNIT (0x00055000)
+#define BASE_ADDR_MCORE_MBIST_CONFIG (0x00056000)
+#define BASE_ADDR_MCORE_MCORE_CRIT_DBUS_REG (0x00057000)
+#define BASE_ADDR_MCORE_L1I_CACHE (0x00100000)
+#define BASE_ADDR_MCORE_L1D_CACHE (0x00101000)
+#define BASE_ADDR_MCORE_CLKCTRL (0x00102000)
+#define BASE_ADDR_MCORE_SHARED_EXCTRL (0x00103000)
+#define BASE_ADDR_MCORE_L1_PROFILING_UNIT (0x00104000)
+#define BASE_ADDR_MCORE_A2D_32 (0x00105000)
+#define BASE_ADDR_MCORE_A2D_128 (0x00106000)
+#define BASE_ADDR_MCORE_D2D (0x00107000)
+#define BASE_ADDR_MCORE_D2A (0x00108000)
+#define BASE_ADDR_MCORE_MCORE_TOP_DBUS_REG (0x00109000)
+#define BASE_ADDR_MCORE_MML1_DSPISRD (0x00180000)
+#define BASE_ADDR_MCORE_MML1_DSPDBGC0 (0x00181000)
+#define BASE_ADDR_MCORE_MML1_DSPDBGC1 (0x00182000)
+#define BASE_ADDR_MCORE_MML1_DSPCTIWRAP (0x00183000)
+#define BASE_ADDR_MCORE_THREAD0_SONIC (0x00200000)
+#define BASE_ADDR_MCORE_THREAD0_L0I_CACHE (0x00210000)
+#define BASE_ADDR_MCORE_THREAD0_L0D_CACHE (0x00211000)
+#define BASE_ADDR_MCORE_THREAD0_TIMER (0x00212000)
+#define BASE_ADDR_MCORE_THREAD0_EXCTRL (0x00213000)
+#define BASE_ADDR_MCORE_THREAD0_PC_MONITOR (0x00214000)
+#define BASE_ADDR_MCORE_THREAD0_PROFILING_UNIT (0x00215000)
+#define BASE_ADDR_MCORE_THREAD0_MBIST_CONFIG (0x00216000)
+#define BASE_ADDR_MCORE_THREAD0_DBUS_REG (0x00217000)
+#define BASE_ADDR_MCORE_THREAD1_SONIC (0x00220000)
+#define BASE_ADDR_MCORE_THREAD1_L0I_CACHE (0x00230000)
+#define BASE_ADDR_MCORE_THREAD1_L0D_CACHE (0x00231000)
+#define BASE_ADDR_MCORE_THREAD1_TIMER (0x00232000)
+#define BASE_ADDR_MCORE_THREAD1_EXCTRL (0x00233000)
+#define BASE_ADDR_MCORE_THREAD1_PC_MONITOR (0x00234000)
+#define BASE_ADDR_MCORE_THREAD1_PROFILING_UNIT (0x00235000)
+#define BASE_ADDR_MCORE_THREAD1_MBIST_CONFIG (0x00236000)
+#define BASE_ADDR_MCORE_THREAD1_DBUS_REG (0x00237000)
+#define BASE_ADDR_MCORE_THREAD2_SONIC (0x00240000)
+#define BASE_ADDR_MCORE_THREAD2_L0I_CACHE (0x00250000)
+#define BASE_ADDR_MCORE_THREAD2_L0D_CACHE (0x00251000)
+#define BASE_ADDR_MCORE_THREAD2_TIMER (0x00252000)
+#define BASE_ADDR_MCORE_THREAD2_EXCTRL (0x00253000)
+#define BASE_ADDR_MCORE_THREAD2_PC_MONITOR (0x00254000)
+#define BASE_ADDR_MCORE_THREAD2_PROFILING_UNIT (0x00255000)
+#define BASE_ADDR_MCORE_THREAD2_MBIST_CONFIG (0x00256000)
+#define BASE_ADDR_MCORE_THREAD2_DBUS_REG (0x00257000)
+#define BASE_ADDR_MCORE_THREAD3_SONIC (0x00260000)
+#define BASE_ADDR_MCORE_THREAD3_L0I_CACHE (0x00270000)
+#define BASE_ADDR_MCORE_THREAD3_L0D_CACHE (0x00271000)
+#define BASE_ADDR_MCORE_THREAD3_TIMER (0x00272000)
+#define BASE_ADDR_MCORE_THREAD3_EXCTRL (0x00273000)
+#define BASE_ADDR_MCORE_THREAD3_PC_MONITOR (0x00274000)
+#define BASE_ADDR_MCORE_THREAD3_PROFILING_UNIT (0x00275000)
+#define BASE_ADDR_MCORE_THREAD3_MBIST_CONFIG (0x00276000)
+#define BASE_ADDR_MCORE_THREAD3_DBUS_REG (0x00277000)
+#define BASE_ADDR_MCORE_THREAD4_SONIC (0x00280000)
+#define BASE_ADDR_MCORE_THREAD4_L0I_CACHE (0x00290000)
+#define BASE_ADDR_MCORE_THREAD4_L0D_CACHE (0x00291000)
+#define BASE_ADDR_MCORE_THREAD4_TIMER (0x00292000)
+#define BASE_ADDR_MCORE_THREAD4_EXCTRL (0x00293000)
+#define BASE_ADDR_MCORE_THREAD4_PC_MONITOR (0x00294000)
+#define BASE_ADDR_MCORE_THREAD4_PROFILING_UNIT (0x00295000)
+#define BASE_ADDR_MCORE_THREAD4_MBIST_CONFIG (0x00296000)
+#define BASE_ADDR_MCORE_THREAD4_DBUS_REG (0x00297000)
+#define BASE_ADDR_MCORE_THREAD5_SONIC (0x002A0000)
+#define BASE_ADDR_MCORE_THREAD5_L0I_CACHE (0x002B0000)
+#define BASE_ADDR_MCORE_THREAD5_L0D_CACHE (0x002B1000)
+#define BASE_ADDR_MCORE_THREAD5_TIMER (0x002B2000)
+#define BASE_ADDR_MCORE_THREAD5_EXCTRL (0x002B3000)
+#define BASE_ADDR_MCORE_THREAD5_PC_MONITOR (0x002B4000)
+#define BASE_ADDR_MCORE_THREAD5_PROFILING_UNIT (0x002B5000)
+#define BASE_ADDR_MCORE_THREAD5_MBIST_CONFIG (0x002B6000)
+#define BASE_ADDR_MCORE_THREAD5_DBUS_REG (0x002B7000)
+#define BASE_ADDR_MCORE_THREAD6_SONIC (0x002C0000)
+#define BASE_ADDR_MCORE_THREAD6_L0I_CACHE (0x002D0000)
+#define BASE_ADDR_MCORE_THREAD6_L0D_CACHE (0x002D1000)
+#define BASE_ADDR_MCORE_THREAD6_TIMER (0x002D2000)
+#define BASE_ADDR_MCORE_THREAD6_EXCTRL (0x002D3000)
+#define BASE_ADDR_MCORE_THREAD6_PC_MONITOR (0x002D4000)
+#define BASE_ADDR_MCORE_THREAD6_PROFILING_UNIT (0x002D5000)
+#define BASE_ADDR_MCORE_THREAD6_MBIST_CONFIG (0x002D6000)
+#define BASE_ADDR_MCORE_THREAD6_DBUS_REG (0x002D7000)
+#define BASE_ADDR_MCORE_THREAD7_SONIC (0x002E0000)
+#define BASE_ADDR_MCORE_THREAD7_L0I_CACHE (0x002F0000)
+#define BASE_ADDR_MCORE_THREAD7_L0D_CACHE (0x002F1000)
+#define BASE_ADDR_MCORE_THREAD7_TIMER (0x002F2000)
+#define BASE_ADDR_MCORE_THREAD7_EXCTRL (0x002F3000)
+#define BASE_ADDR_MCORE_THREAD7_PC_MONITOR (0x002F4000)
+#define BASE_ADDR_MCORE_THREAD7_PROFILING_UNIT (0x002F5000)
+#define BASE_ADDR_MCORE_THREAD7_MBIST_CONFIG (0x002F6000)
+#define BASE_ADDR_MCORE_THREAD7_DBUS_REG (0x002F7000)
+#define BASE_ADDR_MCORE_THREAD8_SONIC (0x00300000)
+#define BASE_ADDR_MCORE_THREAD8_L0I_CACHE (0x00310000)
+#define BASE_ADDR_MCORE_THREAD8_L0D_CACHE (0x00311000)
+#define BASE_ADDR_MCORE_THREAD8_TIMER (0x00312000)
+#define BASE_ADDR_MCORE_THREAD8_EXCTRL (0x00313000)
+#define BASE_ADDR_MCORE_THREAD8_PC_MONITOR (0x00314000)
+#define BASE_ADDR_MCORE_THREAD8_PROFILING_UNIT (0x00315000)
+#define BASE_ADDR_MCORE_THREAD8_MBIST_CONFIG (0x00316000)
+#define BASE_ADDR_MCORE_THREAD8_DBUS_REG (0x00317000)
+#define BASE_ADDR_MCORE_THREAD9_SONIC (0x00320000)
+#define BASE_ADDR_MCORE_THREAD9_L0I_CACHE (0x00330000)
+#define BASE_ADDR_MCORE_THREAD9_L0D_CACHE (0x00331000)
+#define BASE_ADDR_MCORE_THREAD9_TIMER (0x00332000)
+#define BASE_ADDR_MCORE_THREAD9_EXCTRL (0x00333000)
+#define BASE_ADDR_MCORE_THREAD9_PC_MONITOR (0x00334000)
+#define BASE_ADDR_MCORE_THREAD9_PROFILING_UNIT (0x00335000)
+#define BASE_ADDR_MCORE_THREAD9_MBIST_CONFIG (0x00336000)
+#define BASE_ADDR_MCORE_THREAD9_DBUS_REG (0x00337000)
+#define BASE_ADDR_MCORE_THREAD10_SONIC (0x00340000)
+#define BASE_ADDR_MCORE_THREAD10_L0I_CACHE (0x00350000)
+#define BASE_ADDR_MCORE_THREAD10_L0D_CACHE (0x00351000)
+#define BASE_ADDR_MCORE_THREAD10_TIMER (0x00352000)
+#define BASE_ADDR_MCORE_THREAD10_EXCTRL (0x00353000)
+#define BASE_ADDR_MCORE_THREAD10_PC_MONITOR (0x00354000)
+#define BASE_ADDR_MCORE_THREAD10_PROFILING_UNIT (0x00355000)
+#define BASE_ADDR_MCORE_THREAD10_MBIST_CONFIG (0x00356000)
+#define BASE_ADDR_MCORE_THREAD10_DBUS_REG (0x00357000)
+#define BASE_ADDR_MCORE_THREAD11_SONIC (0x00360000)
+#define BASE_ADDR_MCORE_THREAD11_L0I_CACHE (0x00370000)
+#define BASE_ADDR_MCORE_THREAD11_L0D_CACHE (0x00371000)
+#define BASE_ADDR_MCORE_THREAD11_TIMER (0x00372000)
+#define BASE_ADDR_MCORE_THREAD11_EXCTRL (0x00373000)
+#define BASE_ADDR_MCORE_THREAD11_PC_MONITOR (0x00374000)
+#define BASE_ADDR_MCORE_THREAD11_PROFILING_UNIT (0x00375000)
+#define BASE_ADDR_MCORE_THREAD11_MBIST_CONFIG (0x00376000)
+#define BASE_ADDR_MCORE_THREAD11_DBUS_REG (0x00377000)
+#define BASE_ADDR_MCORE_THREAD12_SONIC (0x00380000)
+#define BASE_ADDR_MCORE_THREAD12_L0I_CACHE (0x00390000)
+#define BASE_ADDR_MCORE_THREAD12_L0D_CACHE (0x00391000)
+#define BASE_ADDR_MCORE_THREAD12_TIMER (0x00392000)
+#define BASE_ADDR_MCORE_THREAD12_EXCTRL (0x00393000)
+#define BASE_ADDR_MCORE_THREAD12_PC_MONITOR (0x00394000)
+#define BASE_ADDR_MCORE_THREAD12_PROFILING_UNIT (0x00395000)
+#define BASE_ADDR_MCORE_THREAD12_MBIST_CONFIG (0x00396000)
+#define BASE_ADDR_MCORE_THREAD12_DBUS_REG (0x00397000)
+#define BASE_ADDR_MCORE_THREAD13_SONIC (0x003A0000)
+#define BASE_ADDR_MCORE_THREAD13_L0I_CACHE (0x003B0000)
+#define BASE_ADDR_MCORE_THREAD13_L0D_CACHE (0x003B1000)
+#define BASE_ADDR_MCORE_THREAD13_TIMER (0x003B2000)
+#define BASE_ADDR_MCORE_THREAD13_EXCTRL (0x003B3000)
+#define BASE_ADDR_MCORE_THREAD13_PC_MONITOR (0x003B4000)
+#define BASE_ADDR_MCORE_THREAD13_PROFILING_UNIT (0x003B5000)
+#define BASE_ADDR_MCORE_THREAD13_MBIST_CONFIG (0x003B6000)
+#define BASE_ADDR_MCORE_THREAD13_DBUS_REG (0x003B7000)
+#define BASE_ADDR_MCORE_THREAD14_SONIC (0x003C0000)
+#define BASE_ADDR_MCORE_THREAD14_L0I_CACHE (0x003D0000)
+#define BASE_ADDR_MCORE_THREAD14_L0D_CACHE (0x003D1000)
+#define BASE_ADDR_MCORE_THREAD14_TIMER (0x003D2000)
+#define BASE_ADDR_MCORE_THREAD14_EXCTRL (0x003D3000)
+#define BASE_ADDR_MCORE_THREAD14_PC_MONITOR (0x003D4000)
+#define BASE_ADDR_MCORE_THREAD14_PROFILING_UNIT (0x003D5000)
+#define BASE_ADDR_MCORE_THREAD14_MBIST_CONFIG (0x003D6000)
+#define BASE_ADDR_MCORE_THREAD14_DBUS_REG (0x003D7000)
+#define BASE_ADDR_MCORE_THREAD15_SONIC (0x003E0000)
+#define BASE_ADDR_MCORE_THREAD15_L0I_CACHE (0x003F0000)
+#define BASE_ADDR_MCORE_THREAD15_L0D_CACHE (0x003F1000)
+#define BASE_ADDR_MCORE_THREAD15_TIMER (0x003F2000)
+#define BASE_ADDR_MCORE_THREAD15_EXCTRL (0x003F3000)
+#define BASE_ADDR_MCORE_THREAD15_PC_MONITOR (0x003F4000)
+#define BASE_ADDR_MCORE_THREAD15_PROFILING_UNIT (0x003F5000)
+#define BASE_ADDR_MCORE_THREAD15_MBIST_CONFIG (0x003F6000)
+#define BASE_ADDR_MCORE_THREAD15_DBUS_REG (0x003F7000)
+#define BASE_ADDR_MCORE_MML1_DSPM2VSCHEDULER (0x00800000)
+#define BASE_ADDR_MCORE_MML1_MPERI_DSPCK_ABUS_REG (0x00801000)
+#define BASE_ADDR_MCORE_MPERI_DBUS3 (0x00802000)
+#define BASE_ADDR_MCORE_DSPM2DDMSCHEDULER (0x00804000)
+#define BASE_ADDR_MCORE_MML1_DSPCSIF (0x00810000)
+#define BASE_ADDR_MCORE_MML1_DSPMCORELOG (0x00811000)
+#define BASE_ADDR_MCORE_MML1_MPERI_DSPCORECK_ABUS_REG (0x00813000)
+#define BASE_ADDR_MCORE_MPERI_DBUS1 (0x00814000)
+#define BASE_ADDR_MCORE_DBUS_AXI2DBUS (0x00816000)
+#define BASE_ADDR_MCORE_MML1_DSPBUSRECORDER (0x00817000)
+#define BASE_ADDR_MCORE_MML1_DSPUSTIMER (0x00818000)
+#define BASE_ADDR_MCORE_MCORE_PROFILING_UNIT (0x00819000)
+#define BASE_ADDR_MCORE_MPPT (0x0081A000)
+#define BASE_ADDR_MCORE_MML1_DSPBTDMA (0x00821000)
+#define BASE_ADDR_MCORE_MML1_DSPSWLA (0x00822000)
+#define BASE_ADDR_MCORE_MPERI_DBUS2 (0x00823000)
+#define BASE_ADDR_MCORE_GLBCON (0x00830000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_DBGMON_WRAP (0x00831000)
+#define BASE_ADDR_MCORE_MML1_MPERI_PERICK_ABUS_REG (0x00832000)
+#define BASE_ADDR_MCORE_ABUSMON (0x00833000)
+#define BASE_ADDR_MCORE_MML1_DSP_COMDMA (0x00834000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_MBIST_CONFIG (0x00840000)
+#define BASE_ADDR_MCORE_MML1_DSP_MSPDBGMEN (0x00F00000)
+#define BASE_ADDR_MCORE_L1DTCM (0x01000000)
+#define BASE_ADDR_MCORE_L1DTCM_MIRROR1 (0x01100000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM (0x01400000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1 (0x01440000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2 (0x01480000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3 (0x014C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM (0x014FC000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM0 (0x01500000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1_1 (0x01540000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2_1 (0x01580000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3_1 (0x015C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM_MIRROR1 (0x015FC000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM0_1 (0x01600000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1_2 (0x01640000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2_2 (0x01680000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3_2 (0x016C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM_MIRROR2 (0x016FC000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM0_2 (0x01700000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1_3 (0x01740000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2_3 (0x01780000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3_3 (0x017C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM_MIRROR3 (0x017FC000)
+// (12): MAP_MCORE_global
+#define BASE_MADDR_MCORE_MSYS_DSPM2VSCHEDULER (0xA4000000)
+#define BASE_MADDR_MCORE_MPERI_DSPCK_ABUS_REG (0xA4001000)
+#define BASE_MADDR_MCORE_MPERI_DBUS3_APB2DBUSCR_INST (0xA4002000)
+#define BASE_MADDR_MCORE_MML1_DSPM2DDMSCHEDULER (0xA4004000)
+#define BASE_MADDR_MCORE_MSYS_DSPCSIF (0xA4010000)
+#define BASE_MADDR_MCORE_MSYS_DSPMCORELOG (0xA4011000)
+#define BASE_MADDR_MCORE_MML1_DSPCBSCHEDULER (0xA4012000)
+#define BASE_MADDR_MCORE_MPERI_DSPCORECK_ABUS_REG (0xA4013000)
+#define BASE_MADDR_MCORE_MPERI_DBUS1_APB2DBUSCR_INST (0xA4014000)
+#define BASE_MADDR_MCORE_MPERI_A2D (0xA4016000)
+#define BASE_MADDR_MCORE_MPERI_DBUSRECORDER (0xA4017000)
+#define BASE_MADDR_MCORE_MSYS_DSPUSTIMER (0xA4018000)
+#define BASE_MADDR_MCORE_MSYS_PROFILING (0xA4019000)
+#define BASE_MADDR_MCORE_MML1_DSPMPPT (0xA401A000)
+#define BASE_MADDR_MCORE_MSYS_DSPBTDMA (0xA4021000)
+#define BASE_MADDR_MCORE_MSYS_DSPSWLA (0xA4022000)
+#define BASE_MADDR_MCORE_MPERI_DBUS2_APB2DBUSCR_INST (0xA4023000)
+#define BASE_MADDR_MCORE_MSYSY_GLBCON (0xA4030000)
+#define BASE_MADDR_MCORE_MSYS_DBGMON (0xA4031000)
+#define BASE_MADDR_MCORE_MPERI_PERICK_ABUS_REG (0xA4032000)
+#define BASE_MADDR_MCORE_MML1_MCOREPERI_ABUSMON (0xA4033000)
+#define BASE_MADDR_MCORE_MSYS_COMDMA (0xA4034000)
+#define BASE_MADDR_MCORE_MSYS_MBIST_CAT (0xA4040000)
+#define BASE_MADDR_MCORE_MCORE_L1_CACHE (0xA4100000)
+#define BASE_MADDR_MCORE_MCORE0_L1D_CACHE (0xA4101000)
+#define BASE_MADDR_MCORE_MCORE_CLKCTRL (0xA4102000)
+#define BASE_MADDR_MCORE_MCORE_EXCEPTION_CONTROLLER (0xA4103000)
+#define BASE_MADDR_MCORE_MCORE0_L1_PROFILING_UNIT (0xA4104000)
+#define BASE_MADDR_MCORE_MCORE_A2D (0xA4105000)
+#define BASE_MADDR_MCORE_MCORE0_A2D_128 (0xA4106000)
+#define BASE_MADDR_MCORE_MCORE_D2D (0xA4107000)
+#define BASE_MADDR_MCORE_MCORE_D2A (0xA4108000)
+#define BASE_MADDR_MCORE_DBUS_REG (0xA4109000)
+#define BASE_MADDR_MCORE_MSYS_ISRD (0xA4180000)
+#define BASE_MADDR_MCORE_MML1_DSPEINTC (0xA4181000)
+#define BASE_MADDR_MCORE_MSYS_DSPDBGC1 (0xA4182000)
+#define BASE_MADDR_MCORE_MSYS_DSPCTIWRAP (0xA4183000)
+#define BASE_MADDR_MCORE_MCORE_CORE (0xA4200000)
+#define BASE_MADDR_MCORE_MCORE_L0I_CACHE (0xA4210000)
+#define BASE_MADDR_MCORE_MCORE_DATA_CACHE (0xA4211000)
+#define BASE_MADDR_MCORE_MCORE_TIMER (0xA4212000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD0_EXCTRL (0xA4213000)
+#define BASE_MADDR_MCORE_MCORE_PC_MONITOR (0xA4214000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD0_PROFILING_UNIT (0xA4215000)
+#define BASE_MADDR_MCORE_MCORE_MBIST_CONFIG_WRAP (0xA4216000)
+#define BASE_MADDR_MCORE_MCORE_MCORE_CRIT_DBUS (0xA4217000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_SONIC (0xA4220000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_L0I_CACHE (0xA4230000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_L0D_CACHE (0xA4231000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_TIMER (0xA4232000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_EXCTRL (0xA4233000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_PC_MONITOR (0xA4234000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_PROFILING_UNIT (0xA4235000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_MBIST_CONFIG (0xA4236000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_DBUS_REG (0xA4237000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_SONIC (0xA4240000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_L0I_CACHE (0xA4250000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_L0D_CACHE (0xA4251000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_TIMER (0xA4252000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_EXCTRL (0xA4253000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_PC_MONITOR (0xA4254000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_PROFILING_UNIT (0xA4255000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_MBIST_CONFIG (0xA4256000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_DBUS_REG (0xA4257000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_SONIC (0xA4260000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_L0I_CACHE (0xA4270000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_L0D_CACHE (0xA4271000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_TIMER (0xA4272000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_EXCTRL (0xA4273000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_PC_MONITOR (0xA4274000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_PROFILING_UNIT (0xA4275000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_MBIST_CONFIG (0xA4276000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_DBUS_REG (0xA4277000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_SONIC (0xA4280000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_L0I_CACHE (0xA4290000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_L0D_CACHE (0xA4291000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_TIMER (0xA4292000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_EXCTRL (0xA4293000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_PC_MONITOR (0xA4294000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_PROFILING_UNIT (0xA4295000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_MBIST_CONFIG (0xA4296000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_DBUS_REG (0xA4297000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_SONIC (0xA42A0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_L0I_CACHE (0xA42B0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_L0D_CACHE (0xA42B1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_TIMER (0xA42B2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_EXCTRL (0xA42B3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_PC_MONITOR (0xA42B4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_PROFILING_UNIT (0xA42B5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_MBIST_CONFIG (0xA42B6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_DBUS_REG (0xA42B7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_SONIC (0xA42C0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_L0I_CACHE (0xA42D0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_L0D_CACHE (0xA42D1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_TIMER (0xA42D2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_EXCTRL (0xA42D3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_PC_MONITOR (0xA42D4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_PROFILING_UNIT (0xA42D5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_MBIST_CONFIG (0xA42D6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_DBUS_REG (0xA42D7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_SONIC (0xA42E0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_L0I_CACHE (0xA42F0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_L0D_CACHE (0xA42F1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_TIMER (0xA42F2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_EXCTRL (0xA42F3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_PC_MONITOR (0xA42F4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_PROFILING_UNIT (0xA42F5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_MBIST_CONFIG (0xA42F6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_DBUS_REG (0xA42F7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_SONIC (0xA4300000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_L0I_CACHE (0xA4310000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_L0D_CACHE (0xA4311000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_TIMER (0xA4312000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_EXCTRL (0xA4313000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_PC_MONITOR (0xA4314000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_PROFILING_UNIT (0xA4315000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_MBIST_CONFIG (0xA4316000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_DBUS_REG (0xA4317000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_SONIC (0xA4320000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_L0I_CACHE (0xA4330000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_L0D_CACHE (0xA4331000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_TIMER (0xA4332000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_EXCTRL (0xA4333000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_PC_MONITOR (0xA4334000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_PROFILING_UNIT (0xA4335000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_MBIST_CONFIG (0xA4336000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_DBUS_REG (0xA4337000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_SONIC (0xA4340000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_L0I_CACHE (0xA4350000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_L0D_CACHE (0xA4351000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_TIMER (0xA4352000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_EXCTRL (0xA4353000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_PC_MONITOR (0xA4354000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_PROFILING_UNIT (0xA4355000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_MBIST_CONFIG (0xA4356000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_DBUS_REG (0xA4357000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_SONIC (0xA4360000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_L0I_CACHE (0xA4370000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_L0D_CACHE (0xA4371000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_TIMER (0xA4372000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_EXCTRL (0xA4373000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_PC_MONITOR (0xA4374000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_PROFILING_UNIT (0xA4375000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_MBIST_CONFIG (0xA4376000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_DBUS_REG (0xA4377000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_SONIC (0xA4380000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_L0I_CACHE (0xA4390000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_L0D_CACHE (0xA4391000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_TIMER (0xA4392000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_EXCTRL (0xA4393000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_PC_MONITOR (0xA4394000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_PROFILING_UNIT (0xA4395000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_MBIST_CONFIG (0xA4396000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_DBUS_REG (0xA4397000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_SONIC (0xA43A0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_L0I_CACHE (0xA43B0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_L0D_CACHE (0xA43B1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_TIMER (0xA43B2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_EXCTRL (0xA43B3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_PC_MONITOR (0xA43B4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_PROFILING_UNIT (0xA43B5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_MBIST_CONFIG (0xA43B6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_DBUS_REG (0xA43B7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_SONIC (0xA43C0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_L0I_CACHE (0xA43D0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_L0D_CACHE (0xA43D1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_TIMER (0xA43D2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_EXCTRL (0xA43D3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_PC_MONITOR (0xA43D4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_PROFILING_UNIT (0xA43D5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_MBIST_CONFIG (0xA43D6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_DBUS_REG (0xA43D7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_SONIC (0xA43E0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_L0I_CACHE (0xA43F0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_L0D_CACHE (0xA43F1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_TIMER (0xA43F2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_EXCTRL (0xA43F3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_PC_MONITOR (0xA43F4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_PROFILING_UNIT (0xA43F5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_MBIST_CONFIG (0xA43F6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_DBUS_REG (0xA43F7000)
+#define BASE_MADDR_MCORE_MCORE0_L1I_CACHE (0xA4800000)
+#define BASE_MADDR_MCORE_MCORE0_L1D_CACHE_1 (0xA4900000)
+#define BASE_MADDR_MCORE_THREAD0_ICM (0xA4A00000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD0_SONIC_RESERVED0 (0xA4A04000)
+#define BASE_MADDR_MCORE_THREAD1_ICM (0xA4A10000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_SONIC_RESERVED1 (0xA4A14000)
+#define BASE_MADDR_MCORE_THREAD2_ICM (0xA4A20000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_SONIC_RESERVED2 (0xA4A24000)
+#define BASE_MADDR_MCORE_THREAD3_ICM (0xA4A30000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_SONIC_RESERVED3 (0xA4A34000)
+#define BASE_MADDR_MCORE_THREAD4_ICM (0xA4A40000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_SONIC_RESERVED4 (0xA4A44000)
+#define BASE_MADDR_MCORE_THREAD5_ICM (0xA4A50000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_SONIC_RESERVED5 (0xA4A54000)
+#define BASE_MADDR_MCORE_THREAD6_ICM (0xA4A60000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_SONIC_RESERVED6 (0xA4A64000)
+#define BASE_MADDR_MCORE_THREAD7_ICM (0xA4A70000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_SONIC_RESERVED7 (0xA4A74000)
+#define BASE_MADDR_MCORE_THREAD8_ICM (0xA4A80000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_SONIC_RESERVED8 (0xA4A84000)
+#define BASE_MADDR_MCORE_THREAD9_ICM (0xA4A90000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_SONIC_RESERVED9 (0xA4A94000)
+#define BASE_MADDR_MCORE_THREAD10_ICM (0xA4AA0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_SONIC_RESERVED10 (0xA4AA4000)
+#define BASE_MADDR_MCORE_THREAD11_ICM (0xA4AB0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_SONIC_RESERVED11 (0xA4AB4000)
+#define BASE_MADDR_MCORE_THREAD12_ICM (0xA4AC0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_SONIC_RESERVED12 (0xA4AC4000)
+#define BASE_MADDR_MCORE_THREAD13_ICM (0xA4AD0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_SONIC_RESERVED13 (0xA4AD4000)
+#define BASE_MADDR_MCORE_THREAD14_ICM (0xA4AE0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_SONIC_RESERVED14 (0xA4AE4000)
+#define BASE_MADDR_MCORE_THREAD15_ICM (0xA4AF0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_SONIC_RESERVED15 (0xA4AF4000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM0 (0xA4F00000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM1 (0xA4F40000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM2 (0xA4F80000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM3 (0xA4FC0000)
+#define BASE_MADDR_MCORE_MML1_MCORESYS_SHDM (0xA4FFC000)
+// (13): MAP_VCORE_Program_private
+#define BASE_ADDR_VCORE_L1ITCM (0x00000000)
+// (14): MAP_VCORE_Data_private
+#define BASE_ADDR_VCORE_SONIC_BACKUP (0x00000000)
+#define BASE_ADDR_VCORE_SONIC (0x00040000)
+#define BASE_ADDR_VCORE_L0I_CACHE (0x00050000)
+#define BASE_ADDR_VCORE_L0D_CACHE (0x00051000)
+#define BASE_ADDR_VCORE_TIMER (0x00052000)
+#define BASE_ADDR_VCORE_EXCTRL (0x00053000)
+#define BASE_ADDR_VCORE_PC_MONITOR (0x00054000)
+#define BASE_ADDR_VCORE_VCORE_TOP_PROFILING_UNIT (0x00055000)
+#define BASE_ADDR_VCORE_VMEM_MEM (0x00060000)
+#define BASE_ADDR_VCORE_BLAZE (0x00070000)
+#define BASE_ADDR_VCORE_VMEM_CFG (0x00071000)
+#define BASE_ADDR_VCORE_HLSU (0x00072000)
+#define BASE_ADDR_VCORE_VU_PROFILING_UNIT (0x00073000)
+#define BASE_ADDR_VCORE_MBIST_CONFIG (0x00074000)
+#define BASE_ADDR_VCORE_VU_DBUS_REG (0x00075000)
+#define BASE_ADDR_VCORE_L1I_CACHE (0x00100000)
+#define BASE_ADDR_VCORE_L1D_CACHE (0x00101000)
+#define BASE_ADDR_VCORE_CLKCTRL (0x00102000)
+#define BASE_ADDR_VCORE_SHARED_EXCTRL (0x00103000)
+#define BASE_ADDR_VCORE_L1_PROFILING_UNIT (0x00104000)
+#define BASE_ADDR_VCORE_A2D_32 (0x00105000)
+#define BASE_ADDR_VCORE_A2D_128 (0x00106000)
+#define BASE_ADDR_VCORE_D2D (0x00107000)
+#define BASE_ADDR_VCORE_VCORE_TOP_DBUS_REG (0x00108000)
+#define BASE_ADDR_VCORE_MML1_DSPDBGC0 (0x00180000)
+#define BASE_ADDR_VCORE_MML1_DSPDBGC1 (0x00181000)
+#define BASE_ADDR_VCORE_MML1_DSPCTIWRAP (0x00182000)
+#define BASE_ADDR_VCORE_THREAD0_SONIC (0x00200000)
+#define BASE_ADDR_VCORE_THREAD0_L0I_CACHE (0x00210000)
+#define BASE_ADDR_VCORE_THREAD0_L0D_CACHE (0x00211000)
+#define BASE_ADDR_VCORE_THREAD0_TIMER (0x00212000)
+#define BASE_ADDR_VCORE_THREAD0_EXCTRL (0x00213000)
+#define BASE_ADDR_VCORE_THREAD0_PC_MONITOR (0x00214000)
+#define BASE_ADDR_VCORE_THREAD0_PROFILING_UNIT (0x00215000)
+#define BASE_ADDR_VCORE_VU0_VMEM_MEM (0x00220000)
+#define BASE_ADDR_VCORE_VU0_BLAZE (0x00230000)
+#define BASE_ADDR_VCORE_VU0_VMEM_CFG (0x00231000)
+#define BASE_ADDR_VCORE_VU0_HLSU (0x00232000)
+#define BASE_ADDR_VCORE_VU0_PROFILING_UNIT (0x00233000)
+#define BASE_ADDR_VCORE_VU0_MBIST_CONFIG (0x00234000)
+#define BASE_ADDR_VCORE_VU0_DBUS_REG (0x00235000)
+#define BASE_ADDR_VCORE_THREAD1_SONIC (0x00240000)
+#define BASE_ADDR_VCORE_THREAD1_L0I_CACHE (0x00250000)
+#define BASE_ADDR_VCORE_THREAD1_L0D_CACHE (0x00251000)
+#define BASE_ADDR_VCORE_THREAD1_TIMER (0x00252000)
+#define BASE_ADDR_VCORE_THREAD1_EXCTRL (0x00253000)
+#define BASE_ADDR_VCORE_THREAD1_PC_MONITOR (0x00254000)
+#define BASE_ADDR_VCORE_THREAD1_PROFILING_UNIT (0x00255000)
+#define BASE_ADDR_VCORE_VU1_VMEM_MEM (0x00260000)
+#define BASE_ADDR_VCORE_VU1_BLAZE (0x00270000)
+#define BASE_ADDR_VCORE_VU1_VMEM_CFG (0x00271000)
+#define BASE_ADDR_VCORE_VU1_HLSU (0x00272000)
+#define BASE_ADDR_VCORE_VU1_PROFILING_UNIT (0x00273000)
+#define BASE_ADDR_VCORE_VU1_MBIST_CONFIG (0x00274000)
+#define BASE_ADDR_VCORE_VU1_DBUS_REG (0x00275000)
+#define BASE_ADDR_VCORE_THREAD2_SONIC (0x00280000)
+#define BASE_ADDR_VCORE_THREAD2_L0I_CACHE (0x00290000)
+#define BASE_ADDR_VCORE_THREAD2_L0D_CACHE (0x00291000)
+#define BASE_ADDR_VCORE_THREAD2_TIMER (0x00292000)
+#define BASE_ADDR_VCORE_THREAD2_EXCTRL (0x00293000)
+#define BASE_ADDR_VCORE_THREAD2_PC_MONITOR (0x00294000)
+#define BASE_ADDR_VCORE_THREAD2_PROFILING_UNIT (0x00295000)
+#define BASE_ADDR_VCORE_VU2_VMEM_MEM (0x002A0000)
+#define BASE_ADDR_VCORE_VU2_BLAZE (0x002B0000)
+#define BASE_ADDR_VCORE_VU2_VMEM_CFG (0x002B1000)
+#define BASE_ADDR_VCORE_VU2_HLSU (0x002B2000)
+#define BASE_ADDR_VCORE_VU2_PROFILING_UNIT (0x002B3000)
+#define BASE_ADDR_VCORE_VU2_MBIST_CONFIG (0x002B4000)
+#define BASE_ADDR_VCORE_VU2_DBUS_REG (0x002B5000)
+#define BASE_ADDR_VCORE_THREAD3_SONIC (0x002C0000)
+#define BASE_ADDR_VCORE_THREAD3_L0I_CACHE (0x002D0000)
+#define BASE_ADDR_VCORE_THREAD3_L0D_CACHE (0x002D1000)
+#define BASE_ADDR_VCORE_THREAD3_TIMER (0x002D2000)
+#define BASE_ADDR_VCORE_THREAD3_EXCTRL (0x002D3000)
+#define BASE_ADDR_VCORE_THREAD3_PC_MONITOR (0x002D4000)
+#define BASE_ADDR_VCORE_THREAD3_PROFILING_UNIT (0x002D5000)
+#define BASE_ADDR_VCORE_VU3_VMEM_MEM (0x002E0000)
+#define BASE_ADDR_VCORE_VU3_BLAZE (0x002F0000)
+#define BASE_ADDR_VCORE_VU3_VMEM_CFG (0x002F1000)
+#define BASE_ADDR_VCORE_VU3_HLSU (0x002F2000)
+#define BASE_ADDR_VCORE_VU3_PROFILING_UNIT (0x002F3000)
+#define BASE_ADDR_VCORE_VU3_MBIST_CONFIG (0x002F4000)
+#define BASE_ADDR_VCORE_VU3_DBUS_REG (0x002F5000)
+#define BASE_ADDR_VCORE_THREAD4_SONIC (0x00300000)
+#define BASE_ADDR_VCORE_THREAD4_L0I_CACHE (0x00310000)
+#define BASE_ADDR_VCORE_THREAD4_L0D_CACHE (0x00311000)
+#define BASE_ADDR_VCORE_THREAD4_TIMER (0x00312000)
+#define BASE_ADDR_VCORE_THREAD4_EXCTRL (0x00313000)
+#define BASE_ADDR_VCORE_THREAD4_PC_MONITOR (0x00314000)
+#define BASE_ADDR_VCORE_THREAD4_PROFILING_UNIT (0x00315000)
+#define BASE_ADDR_VCORE_VU4_VMEM_MEM (0x00320000)
+#define BASE_ADDR_VCORE_VU4_BLAZE (0x00330000)
+#define BASE_ADDR_VCORE_VU4_VMEM_CFG (0x00331000)
+#define BASE_ADDR_VCORE_VU4_HLSU (0x00332000)
+#define BASE_ADDR_VCORE_VU4_PROFILING_UNIT (0x00333000)
+#define BASE_ADDR_VCORE_VU4_MBIST_CONFIG (0x00334000)
+#define BASE_ADDR_VCORE_VU4_DBUS_REG (0x00335000)
+#define BASE_ADDR_VCORE_THREAD5_SONIC (0x00340000)
+#define BASE_ADDR_VCORE_THREAD5_L0I_CACHE (0x00350000)
+#define BASE_ADDR_VCORE_THREAD5_L0D_CACHE (0x00351000)
+#define BASE_ADDR_VCORE_THREAD5_TIMER (0x00352000)
+#define BASE_ADDR_VCORE_THREAD5_EXCTRL (0x00353000)
+#define BASE_ADDR_VCORE_THREAD5_PC_MONITOR (0x00354000)
+#define BASE_ADDR_VCORE_THREAD5_PROFILING_UNIT (0x00355000)
+#define BASE_ADDR_VCORE_VU5_VMEM_MEM (0x00360000)
+#define BASE_ADDR_VCORE_VU5_BLAZE (0x00370000)
+#define BASE_ADDR_VCORE_VU5_VMEM_CFG (0x00371000)
+#define BASE_ADDR_VCORE_VU5_HLSU (0x00372000)
+#define BASE_ADDR_VCORE_VU5_PROFILING_UNIT (0x00373000)
+#define BASE_ADDR_VCORE_VU5_MBIST_CONFIG (0x00374000)
+#define BASE_ADDR_VCORE_VU5_DBUS_REG (0x00375000)
+#define BASE_ADDR_VCORE_THREAD6_SONIC (0x00380000)
+#define BASE_ADDR_VCORE_THREAD6_L0I_CACHE (0x00390000)
+#define BASE_ADDR_VCORE_THREAD6_L0D_CACHE (0x00391000)
+#define BASE_ADDR_VCORE_THREAD6_TIMER (0x00392000)
+#define BASE_ADDR_VCORE_THREAD6_EXCTRL (0x00393000)
+#define BASE_ADDR_VCORE_THREAD6_PC_MONITOR (0x00394000)
+#define BASE_ADDR_VCORE_THREAD6_PROFILING_UNIT (0x00395000)
+#define BASE_ADDR_VCORE_VU6_VMEM_MEM (0x003A0000)
+#define BASE_ADDR_VCORE_VU6_BLAZE (0x003B0000)
+#define BASE_ADDR_VCORE_VU6_VMEM_CFG (0x003B1000)
+#define BASE_ADDR_VCORE_VU6_HLSU (0x003B2000)
+#define BASE_ADDR_VCORE_VU6_PROFILING_UNIT (0x003B3000)
+#define BASE_ADDR_VCORE_VU6_MBIST_CONFIG (0x003B4000)
+#define BASE_ADDR_VCORE_VU6_DBUS_REG (0x003B5000)
+#define BASE_ADDR_VCORE_THREAD7_SONIC (0x003C0000)
+#define BASE_ADDR_VCORE_THREAD7_L0I_CACHE (0x003D0000)
+#define BASE_ADDR_VCORE_THREAD7_L0D_CACHE (0x003D1000)
+#define BASE_ADDR_VCORE_THREAD7_TIMER (0x003D2000)
+#define BASE_ADDR_VCORE_THREAD7_EXCTRL (0x003D3000)
+#define BASE_ADDR_VCORE_THREAD7_PC_MONITOR (0x003D4000)
+#define BASE_ADDR_VCORE_THREAD7_PROFILING_UNIT (0x003D5000)
+#define BASE_ADDR_VCORE_VU7_VMEM_MEM (0x003E0000)
+#define BASE_ADDR_VCORE_VU7_BLAZE (0x003F0000)
+#define BASE_ADDR_VCORE_VU7_VMEM_CFG (0x003F1000)
+#define BASE_ADDR_VCORE_VU7_HLSU (0x003F2000)
+#define BASE_ADDR_VCORE_VU7_PROFILING_UNIT (0x003F3000)
+#define BASE_ADDR_VCORE_VU7_MBIST_CONFIG (0x003F4000)
+#define BASE_ADDR_VCORE_VU7_DBUS_REG (0x003F5000)
+#define BASE_ADDR_VCORE_MML1_DSPSLVSCHEDULER (0x00800000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORELOG (0x00801000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_VU2GRAM (0x00802000)
+#define BASE_ADDR_VCORE_VPERI_DBUS1 (0x00803000)
+#define BASE_ADDR_VCORE_DBUS_AXI2DBUS (0x00804000)
+#define BASE_ADDR_VCORE_MML1_DSPBUSRECORDER (0x00805000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_DBGMON_WRAP (0x00806000)
+#define BASE_ADDR_VCORE_VCORESYS_TOP_GLOBAL_CON (0x00807000)
+#define BASE_ADDR_VCORE_MML1_VPERI_DSPCORECK_ABUS_REG (0x00808000)
+#define BASE_ADDR_VCORE_MML1_DSPSWLA (0x00810000)
+#define BASE_ADDR_VCORE_VPERI_DBUS2 (0x00811000)
+#define BASE_ADDR_VCORE_MML1_VPERI_PERICK_ABUS_REG (0x00814000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_MBIST_CAT_MBIST_TOP_CFG (0x00820000)
+#define BASE_ADDR_VCORE_MML1_DSP_MSPDBGMEN (0x00F00000)
+#define BASE_ADDR_VCORE_L1DTCM (0x01000000)
+// (15): MAP_VCORE_global
+#define BASE_MADDR_VCORE_VSYS_DSPSLVSCHEDULER (0xA5000000)
+#define BASE_MADDR_VCORE_VSYS_DSPVCORELOG (0xA5001000)
+#define BASE_MADDR_VCORE_VSYS_VU2GRAM (0xA5002000)
+#define BASE_MADDR_VCORE_VPERI_DBUS1_APB2DBUSCR_INST (0xA5003000)
+#define BASE_MADDR_VCORE_VPERI_A2D (0xA5004000)
+#define BASE_MADDR_VCORE_VPERI_DBUSRECORDER (0xA5005000)
+#define BASE_MADDR_VCORE_VSYS_DBGMON (0xA5006000)
+#define BASE_MADDR_VCORE_VSYS_GLBCON (0xA5007000)
+#define BASE_MADDR_VCORE_VPERI_DSPCORECK_ABUS_REG (0xA5008000)
+#define BASE_MADDR_VCORE_VSYS_SWLA (0xA5010000)
+#define BASE_MADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST (0xA5011000)
+#define BASE_MADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST_1 (0xA5011100)
+#define BASE_MADDR_VCORE_VPERI_PERICK_ABUS_REG (0xA5014000)
+#define BASE_MADDR_VCORE_MBIST_CAT_BUS_DECODER (0xA5020000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_L1_CACHE (0xA5100000)
+#define BASE_MADDR_VCORE_VCORE0_L1D_CACHE (0xA5101000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CLKCTRL (0xA5102000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_EXCEPTION_CONTROLLER (0xA5103000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_PROFILING_UNIT (0xA5104000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_A2D (0xA5105000)
+#define BASE_MADDR_VCORE_VCORE0_A2D_128 (0xA5106000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_D2D (0xA5107000)
+#define BASE_MADDR_VCORE_DBUS_REG (0xA5108000)
+#define BASE_MADDR_VCORE_MML1_DSPEINTC (0xA5180000)
+#define BASE_MADDR_VCORE_VSYS_DSPDBGC1 (0xA5181000)
+#define BASE_MADDR_VCORE_VSYS_DSPCTIWRAP (0xA5182000)
+#define BASE_MADDR_VCORE_VSYS_DSPCTIWRAP_1 (0xA5182020)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE (0xA5200000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_L0I_CACHE (0xA5210000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_DATA_CACHE (0xA5211000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_TIMER (0xA5212000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD0_EXCTRL (0xA5213000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_PC_MONITOR (0xA5214000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD0_PROFILING_UNIT (0xA5215000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_L1 (0xA5220000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_BLAZE (0xA5230000)
+#define BASE_MADDR_VCORE_VCORE0_VU0_VMEM_CFG (0xA5231000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_HLSU (0xA5232000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_PROFILING_UNIT (0xA5233000)
+#define BASE_MADDR_VCORE_VCORE_VU_MBIST_CONFIG (0xA5234000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_VCORE_VU_DBUS (0xA5235000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_SONIC (0xA5240000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_L0I_CACHE (0xA5250000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_L0D_CACHE (0xA5251000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_TIMER (0xA5252000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_EXCTRL (0xA5253000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_PC_MONITOR (0xA5254000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_PROFILING_UNIT (0xA5255000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_VMEM_MEM (0xA5260000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_BLAZE (0xA5270000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_VMEM_CFG (0xA5271000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_HLSU (0xA5272000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_PROFILING_UNIT (0xA5273000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_MBIST_CONFIG (0xA5274000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_DBUS_REG (0xA5275000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_SONIC (0xA5280000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_L0I_CACHE (0xA5290000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_L0D_CACHE (0xA5291000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_TIMER (0xA5292000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_EXCTRL (0xA5293000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_PC_MONITOR (0xA5294000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_PROFILING_UNIT (0xA5295000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_VMEM_MEM (0xA52A0000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_BLAZE (0xA52B0000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_VMEM_CFG (0xA52B1000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_HLSU (0xA52B2000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_PROFILING_UNIT (0xA52B3000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_MBIST_CONFIG (0xA52B4000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_DBUS_REG (0xA52B5000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_SONIC (0xA52C0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_L0I_CACHE (0xA52D0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_L0D_CACHE (0xA52D1000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_TIMER (0xA52D2000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_EXCTRL (0xA52D3000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_PC_MONITOR (0xA52D4000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_PROFILING_UNIT (0xA52D5000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_VMEM_MEM (0xA52E0000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_BLAZE (0xA52F0000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_VMEM_CFG (0xA52F1000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_HLSU (0xA52F2000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_PROFILING_UNIT (0xA52F3000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_MBIST_CONFIG (0xA52F4000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_DBUS_REG (0xA52F5000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_SONIC (0xA5300000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_L0I_CACHE (0xA5310000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_L0D_CACHE (0xA5311000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_TIMER (0xA5312000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_EXCTRL (0xA5313000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_PC_MONITOR (0xA5314000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_PROFILING_UNIT (0xA5315000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_VMEM_MEM (0xA5320000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_BLAZE (0xA5330000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_VMEM_CFG (0xA5331000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_HLSU (0xA5332000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_PROFILING_UNIT (0xA5333000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_MBIST_CONFIG (0xA5334000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_DBUS_REG (0xA5335000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_SONIC (0xA5340000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_L0I_CACHE (0xA5350000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_L0D_CACHE (0xA5351000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_TIMER (0xA5352000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_EXCTRL (0xA5353000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_PC_MONITOR (0xA5354000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_PROFILING_UNIT (0xA5355000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_VMEM_MEM (0xA5360000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_BLAZE (0xA5370000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_VMEM_CFG (0xA5371000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_HLSU (0xA5372000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_PROFILING_UNIT (0xA5373000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_MBIST_CONFIG (0xA5374000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_DBUS_REG (0xA5375000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_SONIC (0xA5380000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_L0I_CACHE (0xA5390000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_L0D_CACHE (0xA5391000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_TIMER (0xA5392000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_EXCTRL (0xA5393000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_PC_MONITOR (0xA5394000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_PROFILING_UNIT (0xA5395000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_VMEM_MEM (0xA53A0000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_BLAZE (0xA53B0000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_VMEM_CFG (0xA53B1000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_HLSU (0xA53B2000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_PROFILING_UNIT (0xA53B3000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_MBIST_CONFIG (0xA53B4000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_DBUS_REG (0xA53B5000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_SONIC (0xA53C0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_L0I_CACHE (0xA53D0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_L0D_CACHE (0xA53D1000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_TIMER (0xA53D2000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_EXCTRL (0xA53D3000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_PC_MONITOR (0xA53D4000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_PROFILING_UNIT (0xA53D5000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_VMEM_MEM (0xA53E0000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_BLAZE (0xA53F0000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_VMEM_CFG (0xA53F1000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_HLSU (0xA53F2000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_PROFILING_UNIT (0xA53F3000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_MBIST_CONFIG (0xA53F4000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_DBUS_REG (0xA53F5000)
+#define BASE_MADDR_VCORE_VCORE0_L1I_CACHE (0xA5800000)
+#define BASE_MADDR_VCORE_VCORE0_L1D_CACHE_1 (0xA5900000)
+#define BASE_MADDR_VCORE_THREAD0_ICM (0xA5A00000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD0_SONIC_RESERVED0 (0xA5A04000)
+#define BASE_MADDR_VCORE_THREAD1_ICM (0xA5A10000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_SONIC_RESERVED1 (0xA5A14000)
+#define BASE_MADDR_VCORE_THREAD2_ICM (0xA5A20000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_SONIC_RESERVED2 (0xA5A24000)
+#define BASE_MADDR_VCORE_THREAD3_ICM (0xA5A30000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_SONIC_RESERVED3 (0xA5A34000)
+#define BASE_MADDR_VCORE_THREAD4_ICM (0xA5A40000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_SONIC_RESERVED4 (0xA5A44000)
+#define BASE_MADDR_VCORE_THREAD5_ICM (0xA5A50000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_SONIC_RESERVED5 (0xA5A54000)
+#define BASE_MADDR_VCORE_THREAD6_ICM (0xA5A60000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_SONIC_RESERVED6 (0xA5A64000)
+#define BASE_MADDR_VCORE_THREAD7_ICM (0xA5A70000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_SONIC_RESERVED7 (0xA5A74000)
+// (16): MAP_gramsys
+#define BASE_MADDR_GRAM_GRAM_BRIDGE (0xA6000000)
+#define BASE_MADDR_GRAM_GRAM_GLBCON (0xA6F00000)
+#define BASE_MADDR_GRAM_GRAMSYS_MBIST_MBIST_TOP_CFG (0xA6F10000)
+#define BASE_MADDR_GRAM_GRAM_BRIDGE_REG (0xA6F20000)
+#define BASE_MADDR_GRAM_GRAM_REG (0xA6F30000)
+#define BASE_MADDR_GRAM_GRAM_BUS_CONFIG (0xA6F40000)
+// (17): MAP_Dbgsys
+#define BASE_MADDR_2ND_ROM_TABLE_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REG_MDPERISYS_MISC_REG (0xA0602000)
+#define BASE_MADDR_MD_DBGMON_MD_DBGMON (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKTL_MDPERI_CLKTL (0xA0603800)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA0604000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA0605000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA0606000)
+#define BASE_MADDR_TOPSM_PROTECT_MDL1_MODEM_TOPSM_PROTECT (0xA060B000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA060C000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA060D000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA060E000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA060F000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0610000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0611000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0612000)
+#define BASE_MADDR_RAKE_BUS_INTF_RAKESYS_BUS_DBGAPB_INTF (0xA0614000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32 (0xA0616000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0618000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0619000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA061A000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA061B000)
+#define BASE_MADDR_BIGRAM_BUS_INTF_BIGRAM_BUS_INTF (0xA061C000)
+#define BASE_MADDR_INR_BUS_INTF_INR_BUS_INTF (0xA061E000)
+#define BASE_MADDR_USIP0_USIP0 (0xA0620000)
+#define BASE_MADDR_USIP1_USIP1 (0xA0621000)
+#define BASE_MADDR_USIPCORE_BUS_INTF_USIPCORE_BUS_INTF (0xA0622000)
+#define BASE_MADDR_L2SRAM_L2SRAM (0xA0624000)
+#define BASE_MADDR_MDMCU_BUS_INTF_VDNR__MDMCU_BUS_INTF (0xA0628000)
+#define BASE_MADDR_MDMCU_COREBUS_INTF_VDNR__MDMCU_COREBUS_INTF (0xA062A000)
+#define BASE_MADDR_MDMCU_BUSMON_MDMCU_BUSMON (0xA062C000)
+#define BASE_MADDR_MDMCU_USIP_BUS_INTF_MDMCU_USIP_BUS_INTF (0xA062D000)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA0630000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_SHAOLIN_DEBUG_PERI (0xA0633000)
+#define BASE_MADDR_SHAOLIN_MACRO_BUS_INTF_VDNR__SHAOLIN_MACRO_BUS_INTF (0xA0634000)
+#define BASE_MADDR_SHAOLIN_BUSMPU_SHAOLIN_BUSMPU (0xA0636000)
+#define BASE_MADDR_SHAOLIN_CM2_SHAOLIN_CM2 (0xA0637000)
+#define BASE_MADDR_SHAOLIN_CORE0__SHAOLIN_CORE0 (0xA0638000)
+#define BASE_MADDR_SHAOLIN_CORE1_SHAOLIN_CORE1 (0xA0639000)
+#define BASE_MADDR_SHAOLIN_CORE2__SHAOLIN_CORE2 (0xA063A000)
+#define BASE_MADDR_SHAOLIN_CORE3_SHAOLIN_CORE3 (0xA063B000)
+#define BASE_MADDR_MDINFRA_BUS4X_REG_MDINFRA_BUS4X_REG (0xA063C000)
+#define BASE_MADDR_MDINFRA_BUS2X_REG_MDINFRA_BUS2X_REG (0xA063D000)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA063E000)
+#define BASE_MADDR_NRL2_BUS_INTF_NRL2_BUS_INTF (0xA0640000)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_RXCPC_NR_DBGAPB_MAS_BUS_INTF (0xA0642000)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2 (0xA0642800)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_RXCPC_NR_DBGAPB_SLV_BUS_INTF (0xA0643000)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2 (0xA0643800)
+#define BASE_MADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF (0xA0644000)
+#define BASE_MADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF_1 (0xA0645000)
+#define BASE_MADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF (0xA0646000)
+#define BASE_MADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF_1 (0xA0647000)
+#define BASE_MADDR_MDAO_MAS_BUS_CK_DBG_MDAO_MAS_BUS_CK_DBG (0xA0648000)
+#define BASE_MADDR_MDAO_SLV_BUS_CK_DBG_MDAO_SLV_BUS_CK_DBG (0xA0649000)
+#define BASE_MADDR_MD_DVFS_TOP_CK_DBG_MD_DVFS_TOP_CK_DBG (0xA0649800)
+#define BASE_MADDR_MDL1_TOPSM_MDL1_TOPSM (0xA064A000)
+#define BASE_MADDR_RFSLPC_RFSLPC (0xA064B000)
+#define BASE_MADDR_MD2G_BUS_MD2G_BUS (0xA064C000)
+#define BASE_MADDR_CSSYS_BUS_CK_DBG_CSSYS_BUS_CK_DBG (0xA064E000)
+#define BASE_MADDR_CSSYS_BUS_DIV2_CK_DBG_CSSYS_BUS_DIV2_CK_DBG (0xA064E800)
+#define BASE_MADDR_MDAO_BUS_CK_DBG_MDAO_BUS_CK_DBG (0xA064F000)
+#define BASE_MADDR_VCORE_TOP_TH0_SONIC_VCORE (0xA0650000)
+#define BASE_MADDR_VCORE_TOP_TH0_PC_MONITOR_VCORE (0xA0650400)
+#define BASE_MADDR_VCORE_TOP_TH0_VUDBUS_VCORE (0xA0650480)
+#define BASE_MADDR_VCORE_TOP_TH1_SONIC_VCORE (0xA0650600)
+#define BASE_MADDR_VCORE_TOP_TH1_PC_MONITOR_VCORE (0xA0650A00)
+#define BASE_MADDR_VCORE_TOP_TH1_VUDBUS_VCORE (0xA0650A80)
+#define BASE_MADDR_VCORE_TOP_TH2_SONIC_VCORE (0xA0650C00)
+#define BASE_MADDR_VCORE_TOP_TH2_PC_MONITOR_VCORE (0xA0651000)
+#define BASE_MADDR_VCORE_TOP_TH2_VUDBUS_VCORE (0xA0651080)
+#define BASE_MADDR_VCORE_TOP_TH3_SONIC_VCORE (0xA0651200)
+#define BASE_MADDR_VCORE_TOP_TH3_PC_MONITOR_VCORE (0xA0651600)
+#define BASE_MADDR_VCORE_TOP_TH3_VUDBUS_VCORE (0xA0651680)
+#define BASE_MADDR_VCORE_TOP_TH4_SONIC_VCORE (0xA0651800)
+#define BASE_MADDR_VCORE_TOP_TH4_PC_MONITOR_VCORE (0xA0651C00)
+#define BASE_MADDR_VCORE_TOP_TH4_VUDBUS_VCORE (0xA0651C80)
+#define BASE_MADDR_VCORE_TOP_TH5_SONIC_VCORE (0xA0651E00)
+#define BASE_MADDR_VCORE_TOP_TH5_PC_MONITOR_VCORE (0xA0652200)
+#define BASE_MADDR_VCORE_TOP_TH5_VUDBUS_VCORE (0xA0652280)
+#define BASE_MADDR_VCORE_TOP_TH6_SONIC_VCORE (0xA0652400)
+#define BASE_MADDR_VCORE_TOP_TH6_PC_MONITOR_VCORE (0xA0652800)
+#define BASE_MADDR_VCORE_TOP_TH6_VUDBUS_VCORE (0xA0652880)
+#define BASE_MADDR_VCORE_TOP_TH7_SONIC_VCORE (0xA0652A00)
+#define BASE_MADDR_VCORE_TOP_TH7_PC_MONITOR_VCORE (0xA0652E00)
+#define BASE_MADDR_VCORE_TOP_TH7_VUDBUS_VCORE (0xA0652E80)
+#define BASE_MADDR_VCORE_TOP_L1_DBUS_VCORE (0xA0653000)
+#define BASE_MADDR_VCORE_TOP_A2D32_VCORE (0xA0654000)
+#define BASE_MADDR_VCORE_TOP_A2D128_VCORE (0xA0654080)
+#define BASE_MADDR_VCORECK_ABUS_VCORECK_ABUS (0xA0655000)
+#define BASE_MADDR_VCORE_DIV2CK_ABUS_VCORE_DIV2CK_ABUS (0xA0655800)
+#define BASE_MADDR_VCORE_CK_DBUS_VCORE_CK_DBUS (0xA0656000)
+#define BASE_MADDR_VCORE_DIV2CK_DBUS_VCORE_DIV2CK_DBUS (0xA0656800)
+#define BASE_MADDR_BUS_RECORDER_BUS_RECORDER (0xA0657000)
+#define BASE_MADDR_VPERIA2D_DBGAPB_VPERIA2D_DBGAPB (0xA0657800)
+#define BASE_MADDR_DEBUG_MONITOR_FOR_DBG_FLAG_MML1_DSPVCORE_DBGMON_WRAP (0xA0657880)
+#define BASE_MADDR_VCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_VCORE_MML1_DSPCTIWRAP (0xA0657900)
+#define BASE_MADDR_VCORE_PAR_AO_CR_VCORE_PAR_AO_CR (0xA0657A00)
+#define BASE_MADDR_GRAM_PERI_GRAM_PERI (0xA0658000)
+#define BASE_MADDR_MCORE0_TOP_TH0_SONIC_MCORE0 (0xA0660000)
+#define BASE_MADDR_MCORE0_TOP_TH0_PC_MONITOR_MCORE0 (0xA0660400)
+#define BASE_MADDR_MCORE0_TOP_TH0_VUDBUS_MCORE0 (0xA0660480)
+#define BASE_MADDR_MCORE0_TOP_TH1_SONIC_MCORE0 (0xA0660600)
+#define BASE_MADDR_MCORE0_TOP_TH1_PC_MONITOR_MCORE0 (0xA0660A00)
+#define BASE_MADDR_MCORE0_TOP_TH1_VUDBUS_MCORE0 (0xA0660A80)
+#define BASE_MADDR_MCORE0_TOP_TH2_SONIC_MCORE0 (0xA0660C00)
+#define BASE_MADDR_MCORE0_TOP_TH2_PC_MONITOR_MCORE0 (0xA0661000)
+#define BASE_MADDR_MCORE0_TOP_TH2_VUDBUS_MCORE0 (0xA0661080)
+#define BASE_MADDR_MCORE0_TOP_TH3_SONIC_MCORE0 (0xA0661200)
+#define BASE_MADDR_MCORE0_TOP_TH3_PC_MONITOR_MCORE0 (0xA0661600)
+#define BASE_MADDR_MCORE0_TOP_TH3_VUDBUS_MCORE0 (0xA0661680)
+#define BASE_MADDR_MCORE0_TOP_TH4_SONIC_MCORE0 (0xA0661800)
+#define BASE_MADDR_MCORE0_TOP_TH4_PC_MONITOR_MCORE0 (0xA0661C00)
+#define BASE_MADDR_MCORE0_TOP_TH4_VUDBUS_MCORE0 (0xA0661C80)
+#define BASE_MADDR_MCORE0_TOP_TH5_SONIC_MCORE0 (0xA0661E00)
+#define BASE_MADDR_MCORE0_TOP_TH5_PC_MONITOR_MCORE0 (0xA0662200)
+#define BASE_MADDR_MCORE0_TOP_TH5_VUDBUS_MCORE0 (0xA0662280)
+#define BASE_MADDR_MCORE0_TOP_TH6_SONIC_MCORE0 (0xA0662400)
+#define BASE_MADDR_MCORE0_TOP_TH6_PC_MONITOR_MCORE0 (0xA0662800)
+#define BASE_MADDR_MCORE0_TOP_TH6_VUDBUS_MCORE0 (0xA0662880)
+#define BASE_MADDR_MCORE0_TOP_TH7_SONIC_MCORE0 (0xA0662A00)
+#define BASE_MADDR_MCORE0_TOP_TH7_PC_MONITOR_MCORE0 (0xA0662E00)
+#define BASE_MADDR_MCORE0_TOP_TH7_VUDBUS_MCORE0 (0xA0662E80)
+#define BASE_MADDR_MCORE0_TOP_TH8_SONIC_MCORE0 (0xA0663000)
+#define BASE_MADDR_MCORE0_TOP_TH8_PC_MONITOR_MCORE0 (0xA0663400)
+#define BASE_MADDR_MCORE0_TOP_TH8_VUDBUS_MCORE0 (0xA0663480)
+#define BASE_MADDR_MCORE0_TOP_TH9_SONIC_MCORE0 (0xA0663600)
+#define BASE_MADDR_MCORE0_TOP_TH9_PC_MONITOR_MCORE0 (0xA0663A00)
+#define BASE_MADDR_MCORE0_TOP_TH9_VUDBUS_MCORE0 (0xA0663A80)
+#define BASE_MADDR_MCORE0_TOP_TH10_SONIC_MCORE0 (0xA0663C00)
+#define BASE_MADDR_MCORE0_TOP_TH10_PC_MONITOR_MCORE0 (0xA0664000)
+#define BASE_MADDR_MCORE0_TOP_TH10_VUDBUS_MCORE0 (0xA0664080)
+#define BASE_MADDR_MCORE0_TOP_TH11_SONIC_MCORE0 (0xA0664200)
+#define BASE_MADDR_MCORE0_TOP_TH11_PC_MONITOR_MCORE0 (0xA0664600)
+#define BASE_MADDR_MCORE0_TOP_TH11_VUDBUS_MCORE0 (0xA0664680)
+#define BASE_MADDR_MCORE0_TOP_TH12_SONIC_MCORE0 (0xA0664800)
+#define BASE_MADDR_MCORE0_TOP_TH12_PC_MONITOR_MCORE0 (0xA0664C00)
+#define BASE_MADDR_MCORE0_TOP_TH12_VUDBUS_MCORE0 (0xA0664C80)
+#define BASE_MADDR_MCORE0_TOP_TH13_SONIC_MCORE0 (0xA0664E00)
+#define BASE_MADDR_MCORE0_TOP_TH13_PC_MONITOR_MCORE0 (0xA0665200)
+#define BASE_MADDR_MCORE0_TOP_TH13_VUDBUS_MCORE0 (0xA0665280)
+#define BASE_MADDR_MCORE0_TOP_TH14_SONIC_MCORE0 (0xA0665400)
+#define BASE_MADDR_MCORE0_TOP_TH14_PC_MONITOR_MCORE0 (0xA0665800)
+#define BASE_MADDR_MCORE0_TOP_TH14_VUDBUS_MCORE0 (0xA0665880)
+#define BASE_MADDR_MCORE0_TOP_TH15_SONIC_MCORE0 (0xA0665A00)
+#define BASE_MADDR_MCORE0_TOP_TH15_PC_MONITOR_MCORE0 (0xA0665E00)
+#define BASE_MADDR_MCORE0_TOP_TH15_VUDBUS_MCORE0 (0xA0665E80)
+#define BASE_MADDR_MCORE0_TOP_L1DBUS_MCORE0 (0xA0666000)
+#define BASE_MADDR_MCORE0_TOP_L1I_CACHE_MCORE0 (0xA0667000)
+#define BASE_MADDR_MCORE0_TOP_L1D_CACHE_MCORE0 (0xA0667200)
+#define BASE_MADDR_MCORE0_TOP_A2D32_MCORE0 (0xA0667400)
+#define BASE_MADDR_MCORE0_TOP_A2D128_MCORE0 (0xA0667480)
+#define BASE_MADDR_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB (0xA0670000)
+#define BASE_MADDR_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB (0xA0671000)
+#define BASE_MADDR_MML1_MPERI_PERICK_ABUS_REG_DBGAPB_MML1_MPERI_PERICK_ABUS_REG_DBGAPB (0xA0672000)
+#define BASE_MADDR_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB (0xA0673000)
+#define BASE_MADDR_MML1_MPERI_DSPCK_DBUS_REG_DBG_MML1_MPERI_DSPCK_DBUS_REG_DBG (0xA0674000)
+#define BASE_MADDR_MML1_MPERI_PERICK_DBUS_REG_DBG_MML1_MPERI_PERICK_DBUS_REG_DBG (0xA0675000)
+#define BASE_MADDR_MML1_MCOREPERI_ABUSMON_TOP_DBG_MML1_MCOREPERI_ABUSMON_TOP_DBG (0xA0676000)
+#define BASE_MADDR_MML1_MPERI_DBUSRECORDER_DBG_MML1_MPERI_DBUSRECORDER_DBG (0xA0677000)
+#define BASE_MADDR_MPERIA2D_DBGAPB_MPERIA2D_DBGAPB (0xA0678000)
+#define BASE_MADDR_MML1_MCORESYS_DBGMON_WRAP_MML1_MCORESYS_DBGMON_WRAP (0xA0679000)
+#define BASE_MADDR_MML1_MPERI_DSPCORECK_DBUS_REG_DBG_MML1_MPERI_DSPCORECK_DBUS_REG_DBG (0xA067A000)
+#define BASE_MADDR_CMCS_MAS_MDTOP_BUS4X_CK_REG_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xA0680000)
+#define BASE_MADDR_CMCS_SLV_MDTOP_BUS4X_CK_REG_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xA0681000)
+#define BASE_MADDR_CM_CS_BUS_CK_REG_MML1_CM_CS_BUS_CK_ABUS_REG (0xA0682000)
+#define BASE_MADDR_CS_NR_BUS_CK_REG_MML1_CS_NR_BUS_CK_ABUS_REG (0xA0683000)
+#define BASE_MADDR_CMCS_NR_CM_NR_CK_REG_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xA0684000)
+#define BASE_MADDR_CM_NR_MDTOP_BUS4X_CK_REG_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xA0685000)
+#define BASE_MADDR_CMCS_NR_RXTFC_NR_CK_REG_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xA0686000)
+#define BASE_MADDR_RXTFC_MDTOP_BUS4X_CK_REG_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xA0687000)
+#define BASE_MADDR_CMCS_NR_RXTDB_NR_CK_REG_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xA0688000)
+#define BASE_MADDR_RXTDB_MDTOP_BUS4X_CK_REG_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xA0689000)
+#define BASE_MADDR_CMCS_NR_RXTDB_PBCH_NR_CK_REG_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xA068A000)
+#define BASE_MADDR_RXTDB_PBCH_MDTOP_BUS4X_CK_REG_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xA068B000)
+#define BASE_MADDR_TX_NR_MAS_TXBSRP_NR_CK_REG_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xA0690000)
+#define BASE_MADDR_TX_NR_MAS_MDTOP_BUS4X_CK_REG_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xA0691000)
+#define BASE_MADDR_TX_NR_SLV_TXBSRP_NR_CK_REG_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xA0692000)
+#define BASE_MADDR_TX_NR_SLV_MDTOP_BUS4X_CK_REG_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xA0693000)
+#define BASE_MADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF (0xA0694000)
+#define BASE_MADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF_1 (0xA0696000)
+#define BASE_MADDR_DFESYS_BUS_INTF_DFESYS_MAS_BUS_CONFIG_REAL (0xA0698000)
+#define BASE_MADDR_DFESYS_BUS_INTF_DFESYS_SLV_BUS_CONFIG (0xA069A000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_BUS_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xA069C000)
+#define BASE_MADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xA069D000)
+#define BASE_MADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xA069F0000)
+#define BASE_MADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xA069F8000)
+#define BASE_MADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TXDFE_468M_CK_ABUS_REG (0xA06A0000)
+#define BASE_MADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TPC_468M_CK_ABUS_REG (0xA06A3000)
+#define BASE_MADDR_MMW_RXDFE_BUS_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xA06A4000)
+#define BASE_MADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xA06A5000)
+#define BASE_MADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xA06A7000)
+// (18): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RESERVED2 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_EGID (0xA7010000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_EGOC (0xA7012000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7014000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7016000)
+#define BASE_MADDR_RXDDM_NR_RESERVED3 (0xA7018000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_STIME_LOG (0xA701A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MDCC (0xA701C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA701E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7020000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA7022000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCE (0xA7024000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_PP (0xA7026000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA7028000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA702A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA702C000)
+#define BASE_MADDR_RXDDM_NR_MML1_RXDDM_CK_ABUS_REG (0xA702E000)
+#define BASE_MADDR_RXDDM_NR_MML1_RXDDM_HALF_CK_ABUS_REG (0xA7030000)
+#define BASE_MADDR_RXDDM_NR_SLOT_RNTI (0xA7200000)
+#define BASE_MADDR_RXDDM_NR_RESERVED4 (0xA7201000)
+#define BASE_MADDR_RXDDM_NR_SYM (0xA7220000)
+#define BASE_MADDR_RXDDM_NR_RESERVED5 (0xA7228000)
+#define BASE_MADDR_RXDDM_NR_MASK_TYPE0 (0xA7240000)
+#define BASE_MADDR_RXDDM_NR_MASK_TYPE1 (0xA7260000)
+// (19): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (20): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED_0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED_1 (0xA7960000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_EMI_CK_ABUS_REG (0xA7970000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_EMI_HALF_CK_ABUS_REG (0xA7980000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_SD_CK_ABUS_REG (0xA7990000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_SD_HALF_CK_ABUS_REG (0xA79A0000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_CK_ABUS_REG (0xA79B0000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_HALF_CK_ABUS_REG (0xA79C0000)
+// (21): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_M_CK_ABUS_REG (0xA7C0C000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_M_HALF_CK_ABUS_REG (0xA7C0E000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_CK_ABUS_REG (0xA7C10000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_HALF_CK_ABUS_REG (0xA7C12000)
+#define BASE_MADDR_RXCPC_NR_RESERVED0 (0xA7C14000)
+#define BASE_MADDR_RXCPC_NR_RESERVED1 (0xA7C16000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CFG_SP (0xA7C20000)
+// (22): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MD_DVFS_TOP_CONFIG (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_MIPI (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MAS_BUS_CONFIG (0xA8160000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_DFESYS_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MMW_TXDFE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MODEML1_AO_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MODEML1_AO_MD_CLKSW (0xA0150000)
+// (23): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (24): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_RESERVED1 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_RESERVED2 (0xA8B00000)
+#define BASE_MADDR_DFESYS_RESERVED3 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_RESERVED4 (0xA8B70000)
+#define BASE_MADDR_DFESYS_RESERVED5 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_DFE_COMDMA (0xA8E00000)
+#define BASE_MADDR_DFESYS_RESERVED6 (0xA8E10000)
+#define BASE_MADDR_DFESYS_RESERVED7 (0xA8E20000)
+#define BASE_MADDR_DFESYS_RESERVED8 (0xA8E30000)
+#define BASE_MADDR_DFESYS_RESERVED9 (0xA8E40000)
+#define BASE_MADDR_DFESYS_RESERVED10 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED11 (0xA8EA0000)
+#define BASE_MADDR_DFESYS_MAS_BUS_INTF (0xA8EB0000)
+#define BASE_MADDR_DFESYS_SLV_BUS_INTF (0xA8EC0000)
+// (25): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (26): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CSSYS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CSSYS_BUS_DIV2_CONFIG (0xA9838000)
+#define BASE_MADDR_CSSYS_MDAO_BUS_CONFIG (0xA983C000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (27): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_SCN_RPT (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+#define BASE_MADDR_CS_NR_CM_CS_BUS_CONFIG (0xA9C60000)
+// (28): MAP_cm_cs_nr_ao
+#define BASE_MADDR_CMCS_PAR_AO_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xADC00000)
+#define BASE_MADDR_CMCS_PAR_AO_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xADC10000)
+#define BASE_MADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG (0xADC20000)
+#define BASE_MADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG (0xADC30000)
+#define BASE_MADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG (0xADC40000)
+#define BASE_MADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO (0xADC50000)
+#define BASE_MADDR_CMCS_PAR_AO_MCORE_PAR_AO_REG (0xADC50400)
+#define BASE_MADDR_CMCS_PAR_AO_U_VCORE_PAR_WRAP_SRAM_AO (0xADC60000)
+#define BASE_MADDR_CMCS_PAR_AO_U_VCORE_PAR_AO_CR (0xADC60400)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_0_SM_CONFIG (0xADC60600)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_1_SM_CONFIG (0xADC60680)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_2_SM_CONFIG (0xADC60700)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_3_SM_CONFIG (0xADC60780)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_4_SM_CONFIG (0xADC60800)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_5_SM_CONFIG (0xADC60880)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_6_SM_CONFIG (0xADC60900)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_7_SM_CONFIG (0xADC60980)
+#define BASE_MADDR_CMCS_PAR_AO_U_GRAM_MEM_CONFIG (0xADC70000)
+#define BASE_MADDR_CMCS_PAR_AO_U_TX_NR_MEM_CONFIG (0xADC80000)
+#define BASE_MADDR_CMCS_PAR_AO_U_CMCS_NR_MEM_CONFIG (0xADC90000)
+#define BASE_MADDR_CMCS_PAR_AO_U_CMCS_PAR_AO_CONFIG_REG (0xADCA0000)
+// (29): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xAA008000)
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xAA010000)
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xAA018000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA020000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA030000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_2 (0xAA040000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_3 (0xAA050000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_4 (0xAA060000)
+#define BASE_MADDR_TXSYS_NR_TXBSRP_GLB_APB_CONFIG (0xAA070000)
+#define BASE_MADDR_TXSYS_NR_TXBSRP_BIT_CONTROLLER (0xAA080000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA100000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG (0xAA101000)
+#define BASE_MADDR_TXSYS_NR_RESERVED0 (0xAA102000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_PAR_AO_CONFIG_REG (0xAA10C000)
+#define BASE_MADDR_TXSYS_NR_RESERVED1 (0xAA10D000)
+#define BASE_MADDR_TXSYS_NR_RESERVED2 (0xAA10E000)
+// (30): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_WRAP (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_0 (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_DVTCRC (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_1 (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_DVTCRC_1 (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_1 (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_2 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB_SSS (0xAA490000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB_SSS (0xAA4A0000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP_SSS (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT_SSS (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_SSS (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL_SSS (0xAA4E0000)
+#define BASE_MADDR_CM_NR_CM_NR_DVTCRC_SSS (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB_CSIRS (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB_CSIRS (0xAA510000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP_CSIRS (0xAA520000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT_CSIRS (0xAA530000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_CSIRS (0xAA540000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL_CSIRS (0xAA550000)
+#define BASE_MADDR_CM_NR_CM_NR_DVTCRC_CSIRS (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_3 (0xAA570000)
+#define BASE_MADDR_CM_NR_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xAA580000)
+#define BASE_MADDR_CM_NR_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xAA590000)
+// (31): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED1 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+#define BASE_MADDR_RXTFC_RESERVED2 (0xAA870000)
+#define BASE_MADDR_RXTFC_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xAA880000)
+#define BASE_MADDR_RXTFC_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xAA890000)
+// (32): Sheet42
+// (33): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_3 (0xAAC70000)
+#define BASE_MADDR_RXTDB_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xAAC80000)
+#define BASE_MADDR_RXTDB_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xAAC90000)
+// (34): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE70000)
+// (35): MAP_bigram
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BUS_CONFIG (0xAB880000)
+#define BASE_MADDR_BIGRAM0_INR_SLV_BUS_CONFIG (0xAB890000)
+// (36): MAP_inr
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (37): MAP_rxbrp
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST_CONFIG (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_MAS_HALF_CK_ABUS_REG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_MAS_CK_ABUS_REG (0xAC990000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_SLV_HALF_CK_ABUS_REG (0xAC9A0000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_SLV_CK_ABUS_REG (0xAC9B0000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_LTE_CE_SC (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE_OC1 (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_OC2 (0xACB22000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_PDSCH (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_PDCCH (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_EPDCCH (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_PBCH (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (38): MAP_rake
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+// (39): MAP_mmw_rf_ctrl
+#define BASE_MADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_SRAM_CTRL_AO (0xAD000000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_MMW_DBB_CTRLACNT (0xAD001000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_GLOBAL_CON_AO (0xAD002000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_RESERVED0 (0xAD003000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xAD010000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RFAC (0xAD020000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CM_DATA_INTF (0xAD040000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_EVENTGEN (0xAD050000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED1 (0xAD060000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xAD080000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_LOG (0xAD090000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_COMDMA (0xAD0A0000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_CONTROLLER (0xAD0B0000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD (0xAD0B8000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_1 (0xAD0B8100)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_2 (0xAD0B8200)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED2 (0xAD0B8300)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_MBIST (0xAD0B9000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_GLOBAL_CON (0xAD0BA000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED3 (0xAD0BB000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_CM_COMM_REG (0xAD0F8000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG (0xAD0F8400)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_1 (0xAD0F8800)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_2 (0xAD0F8C00)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED4 (0xAD0F9000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_TOP (0xAD100000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_LOG (0xAD108000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_SCH (0xAD110000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xAD120000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED5 (0xAD130000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BPI (0xAD180000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_DIGRF_MIPI_M (0xAD190000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_TOP (0xAD200000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SCH (0xAD210000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI0 (0xAD218000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI1 (0xAD219000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI2 (0xAD21A000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI3 (0xAD21B000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI4 (0xAD21C000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI5 (0xAD21D000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI6 (0xAD21E000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI7 (0xAD21F000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xAD220000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED6 (0xAD230000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED7 (0xAD300000)
+// (40): MAP_mmw_txdfe
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_RESERVED0 (0xAD400000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_RESERVED1 (0xAD640000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TOP_CTRL (0xAD410000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_TXK (0xAD420000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_GLOBAL_CON (0xAD430000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BUS_CONFIG (0xAD440000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_MBIST_CONFIG_CAT (0xAD450000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TX_ACNT_TICK_GEN (0xAD460000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TQ (0xAD470000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR (0xAD480000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_1 (0xAD490000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_2 (0xAD4A0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_3 (0xAD4B0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_4 (0xAD4C0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_5 (0xAD4D0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_6 (0xAD4E0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_7 (0xAD4F0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D (0xAD500000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_1 (0xAD510000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_2 (0xAD520000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_3 (0xAD530000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_4 (0xAD540000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_5 (0xAD550000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_6 (0xAD560000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_7 (0xAD570000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_8 (0xAD580000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_9 (0xAD590000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_A (0xAD5A0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF (0xAD5B0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_1 (0xAD5C0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_2 (0xAD5D0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_3 (0xAD5E0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_ABB_MIXEDSYS (0xAD5F0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MRX_DATA_DUMP (0xAD600000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_PCC_BB (0xAD610000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_U_MMW_PCC_BB_TOP_1 (0xAD620000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_LOG (0xAD660000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE0_COMDMA (0xAD670000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE1_COMDMA (0xAD680000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MML1_MMW_TPC_468M_CK_ABUS_REG (0xAD690000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_TPC_M (0xAD700000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_TPC_M_1 (0xAD780000)
+// (41): MAP_mmw_rxdfe
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER (0xAD800000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER_RESERVED0 (0xAD804000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_EVTGEN (0xAD808000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_SLPC (0xAD80C000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_RESERVED1 (0xAD810000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_PAR_WRAP_SRAM_AO (0xAD820000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_CONFIG_AO_REG (0xAD821000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX0 (0xAD828000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX1 (0xAD829000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX2 (0xAD82A000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX3 (0xAD82B000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX0 (0xAD82C000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX1 (0xAD82D000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_SYS (0xAD82E000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xAD830000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CONFIG_REG (0xAD840000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MBIST_CAT_MBIST_TOP_CFG (0xAD844000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xAD850000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_RXDFE_BB_NR_MMW_DM_SEL_WRAP (0xAD860000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CS_SEL_WRAP (0xAD870000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_CMSEL_MMW (0xAD880000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_CMIPG_MMW (0xAD888000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_LOG (0xAD890000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MRSG (0xAD8A0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE0_COMDMA (0xAD8C0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_DMA_DESCRT (0xAD8D0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_0 (0xAD8F0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_1 (0xAD8F8000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_0 (0xAD900000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_0 (0xAD920000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_1 (0xAD920200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_2 (0xAD920400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_3 (0xAD920600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_4 (0xAD920800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_5 (0xAD920A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_6 (0xAD920C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_7 (0xAD920E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_0 (0xAD922000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_1 (0xAD922200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_2 (0xAD922400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_3 (0xAD922600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_4 (0xAD922800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_5 (0xAD922A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_6 (0xAD922C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_7 (0xAD922E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ1 (0xAD924000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_WM (0xAD92A000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TOT_PATT (0xAD92E000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_2 (0xAD940000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_2 (0xAD960000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_1 (0xAD980000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_0 (0xAD9A0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_1 (0xAD9A0200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_2 (0xAD9A0400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_3 (0xAD9A0600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_4 (0xAD9A0800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_5 (0xAD9A0A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_6 (0xAD9A0C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_7 (0xAD9A0E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_0 (0xAD9A2000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_1 (0xAD9A2200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_2 (0xAD9A2400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_3 (0xAD9A2600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_4 (0xAD9A2800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_5 (0xAD9A2A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_6 (0xAD9A2C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_7 (0xAD9A2E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ1 (0xAD9A4000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_WM (0xAD9AA000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TOT_PATT (0xAD9AE000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_MBIST_CONFIG (0xAD9C0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_GLBCON (0xAD9F0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_SET (0xADA00000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_HEADER (0xADA04000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_STATUS (0xADA08000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_P_REG (0xADA10000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_L_REG (0xADA20000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_IMM_REG (0xADA30000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_P_REG (0xADA40000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_L_REG (0xADA50000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CS_AGC (0xADA60000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_468 (0xADA70000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_52 (0xADA71000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_0 (0xADA71800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_1 (0xADA71C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC (0xADA80000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_1 (0xADA84000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_2 (0xADA88000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_3 (0xADA90000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_4 (0xADAA0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_5 (0xADAB0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_6 (0xADAC0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_7 (0xADAD0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_8 (0xADAE0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_468 (0xADAF0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_52 (0xADAF1000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_0 (0xADAF1800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_1 (0xADAF1C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xADAFF000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_DM (0xADB00000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD0_PM (0xADBA0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD1_PM (0xADBB0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_COREDBG (0xADBD0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_GC_PM (0xADBE0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE1_COMDMA (0xADBFE000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ADC_TEST_ARBITOR (0xADBFF000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MDL1_MODEM_TOPSM_PROTECT (0xB0080000)
+#define BASE_NADDR_MDPERI_COMDMA (0xB0090000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_MDRXSYS_SRAM_AO (0xB0190000)
+#define BASE_NADDR_MDPERI_VU_SM_CONGIF_0 (0xB0191000)
+#define BASE_NADDR_MDPERI_VU_SM_CONGIF_1 (0xB0192000)
+#define BASE_NADDR_MDPERI_MDRXAO_CONFIG (0xB0193000)
+#define BASE_NADDR_MDPERI_RESERVED0 (0xB0194000)
+#define BASE_NADDR_MDPERI_BRP_SRAM_AO (0xB01A0000)
+#define BASE_NADDR_MDPERI_NRL2_SRAM_AO (0xB01B0000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_SRAM_AO (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_BUS2X_REG (0xB0440000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_SHAOLIN_SEMAPHORE (0xB0460000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_BUS4X_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_HW_LOG (0xB0500000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0540000)
+#define BASE_NADDR_MDINFRA_TRACE_NR_TOP_1 (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_AO_MISC_CTRL (0xB0260000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_SRAM_AO (0xB0270000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_MEM_DELSEL_CFG (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_MEM_DELSEL_CFG (0xB0281000)
+#define BASE_NADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE1_MEM_DELSEL_CFG (0xB0282000)
+#define BASE_NADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE2_MEM_DELSEL_CFG (0xB0283000)
+#define BASE_NADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE3_MEM_DELSEL_CFG (0xB0284000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_CONFIG (0xB02C0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__BUSMPU_INFRA (0xB02D0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_COREBUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_IA_MACRO_DELSEL_ADR_IF (0xB03B0000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MBIST_MDCORE_FOR_CFG_DELSEL_CFG_WRAP (0xB03B1000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_MBIST_REPAIR_TOP_CFG_WRAP (0xB0D10000)
+#define BASE_NADDR_USIP_MBIST_DELSEL_TOP_CFG_WRAP (0xB0D20000)
+#define BASE_NADDR_USIP_USIPCORE_BUS_CONFIG (0xB0D30000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_UL_CIPHER_CONFIG (0xB2014000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_1 (0xB2036000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_2 (0xB2037000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG_SRAM (0xB2038000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_4 (0xB2039000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_ST (0xB203A000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_0 (0xB203B000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_1 (0xB203C000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_2 (0xB203D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_3 (0xB203E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_4 (0xB203F000)
+#define BASE_NADDR_NRL2_NRL2_DL_META_AGG (0xB2040000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC2 (0xB2041000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC3 (0xB2042000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC4 (0xB2043000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC5 (0xB2044000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC6 (0xB2045000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC7 (0xB2046000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC8 (0xB2047000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_PPRO (0xB2048000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC2 (0xB2049000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC3 (0xB204A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC4 (0xB204B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC5 (0xB204C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC6 (0xB204D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC7 (0xB204E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC8 (0xB204F000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_PPRO (0xB2050000)
+#define BASE_NADDR_NRL2_NRL2_BUS_CFG (0xB2051000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_PPRO_QP (0xB2052000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_0 (0xB2053000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_1 (0xB2054000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_2 (0xB2055000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_3 (0xB2056000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_4 (0xB2057000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_5 (0xB2058000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_6 (0xB2059000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_7 (0xB205A000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_8 (0xB205B000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC0 (0xB205C000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC1 (0xB205D000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC2 (0xB205E000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC3 (0xB205F000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC4 (0xB2060000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC5 (0xB2061000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC6 (0xB2062000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC7 (0xB2063000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC8 (0xB2064000)
+#define BASE_NADDR_MCORE_MSYS_DSPM2VSCHEDULER (0xB4000000)
+#define BASE_NADDR_MCORE_MPERI_DSPCK_ABUS_REG (0xB4001000)
+#define BASE_NADDR_MCORE_MPERI_DBUS3_APB2DBUSCR_INST (0xB4002000)
+#define BASE_NADDR_MCORE_MML1_DSPM2DDMSCHEDULER (0xB4004000)
+#define BASE_NADDR_MCORE_MSYS_DSPCSIF (0xB4010000)
+#define BASE_NADDR_MCORE_MSYS_DSPMCORELOG (0xB4011000)
+#define BASE_NADDR_MCORE_MML1_DSPCBSCHEDULER (0xB4012000)
+#define BASE_NADDR_MCORE_MPERI_DSPCORECK_ABUS_REG (0xB4013000)
+#define BASE_NADDR_MCORE_MPERI_DBUS1_APB2DBUSCR_INST (0xB4014000)
+#define BASE_NADDR_MCORE_MPERI_A2D (0xB4016000)
+#define BASE_NADDR_MCORE_MPERI_DBUSRECORDER (0xB4017000)
+#define BASE_NADDR_MCORE_MSYS_DSPUSTIMER (0xB4018000)
+#define BASE_NADDR_MCORE_MSYS_PROFILING (0xB4019000)
+#define BASE_NADDR_MCORE_MML1_DSPMPPT (0xB401A000)
+#define BASE_NADDR_MCORE_MSYS_DSPBTDMA (0xB4021000)
+#define BASE_NADDR_MCORE_MSYS_DSPSWLA (0xB4022000)
+#define BASE_NADDR_MCORE_MPERI_DBUS2_APB2DBUSCR_INST (0xB4023000)
+#define BASE_NADDR_MCORE_MSYSY_GLBCON (0xB4030000)
+#define BASE_NADDR_MCORE_MSYS_DBGMON (0xB4031000)
+#define BASE_NADDR_MCORE_MPERI_PERICK_ABUS_REG (0xB4032000)
+#define BASE_NADDR_MCORE_MML1_MCOREPERI_ABUSMON (0xB4033000)
+#define BASE_NADDR_MCORE_MSYS_COMDMA (0xB4034000)
+#define BASE_NADDR_MCORE_MSYS_MBIST_CAT (0xB4040000)
+#define BASE_NADDR_MCORE_MCORE_L1_CACHE (0xB4100000)
+#define BASE_NADDR_MCORE_MCORE0_L1D_CACHE (0xB4101000)
+#define BASE_NADDR_MCORE_MCORE_CLKCTRL (0xB4102000)
+#define BASE_NADDR_MCORE_MCORE_EXCEPTION_CONTROLLER (0xB4103000)
+#define BASE_NADDR_MCORE_MCORE0_L1_PROFILING_UNIT (0xB4104000)
+#define BASE_NADDR_MCORE_MCORE_A2D (0xB4105000)
+#define BASE_NADDR_MCORE_MCORE0_A2D_128 (0xB4106000)
+#define BASE_NADDR_MCORE_MCORE_D2D (0xB4107000)
+#define BASE_NADDR_MCORE_MCORE_D2A (0xB4108000)
+#define BASE_NADDR_MCORE_DBUS_REG (0xB4109000)
+#define BASE_NADDR_MCORE_MSYS_ISRD (0xB4180000)
+#define BASE_NADDR_MCORE_MML1_DSPEINTC (0xB4181000)
+#define BASE_NADDR_MCORE_MSYS_DSPDBGC1 (0xB4182000)
+#define BASE_NADDR_MCORE_MSYS_DSPCTIWRAP (0xB4183000)
+#define BASE_NADDR_MCORE_MCORE_CORE (0xB4200000)
+#define BASE_NADDR_MCORE_MCORE_L0I_CACHE (0xB4210000)
+#define BASE_NADDR_MCORE_MCORE_DATA_CACHE (0xB4211000)
+#define BASE_NADDR_MCORE_MCORE_TIMER (0xB4212000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD0_EXCTRL (0xB4213000)
+#define BASE_NADDR_MCORE_MCORE_PC_MONITOR (0xB4214000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD0_PROFILING_UNIT (0xB4215000)
+#define BASE_NADDR_MCORE_MCORE_MBIST_CONFIG_WRAP (0xB4216000)
+#define BASE_NADDR_MCORE_MCORE_MCORE_CRIT_DBUS (0xB4217000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_SONIC (0xB4220000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_L0I_CACHE (0xB4230000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_L0D_CACHE (0xB4231000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_TIMER (0xB4232000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_EXCTRL (0xB4233000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_PC_MONITOR (0xB4234000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_PROFILING_UNIT (0xB4235000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_MBIST_CONFIG (0xB4236000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_DBUS_REG (0xB4237000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_SONIC (0xB4240000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_L0I_CACHE (0xB4250000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_L0D_CACHE (0xB4251000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_TIMER (0xB4252000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_EXCTRL (0xB4253000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_PC_MONITOR (0xB4254000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_PROFILING_UNIT (0xB4255000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_MBIST_CONFIG (0xB4256000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_DBUS_REG (0xB4257000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_SONIC (0xB4260000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_L0I_CACHE (0xB4270000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_L0D_CACHE (0xB4271000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_TIMER (0xB4272000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_EXCTRL (0xB4273000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_PC_MONITOR (0xB4274000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_PROFILING_UNIT (0xB4275000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_MBIST_CONFIG (0xB4276000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_DBUS_REG (0xB4277000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_SONIC (0xB4280000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_L0I_CACHE (0xB4290000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_L0D_CACHE (0xB4291000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_TIMER (0xB4292000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_EXCTRL (0xB4293000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_PC_MONITOR (0xB4294000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_PROFILING_UNIT (0xB4295000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_MBIST_CONFIG (0xB4296000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_DBUS_REG (0xB4297000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_SONIC (0xB42A0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_L0I_CACHE (0xB42B0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_L0D_CACHE (0xB42B1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_TIMER (0xB42B2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_EXCTRL (0xB42B3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_PC_MONITOR (0xB42B4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_PROFILING_UNIT (0xB42B5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_MBIST_CONFIG (0xB42B6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_DBUS_REG (0xB42B7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_SONIC (0xB42C0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_L0I_CACHE (0xB42D0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_L0D_CACHE (0xB42D1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_TIMER (0xB42D2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_EXCTRL (0xB42D3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_PC_MONITOR (0xB42D4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_PROFILING_UNIT (0xB42D5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_MBIST_CONFIG (0xB42D6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_DBUS_REG (0xB42D7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_SONIC (0xB42E0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_L0I_CACHE (0xB42F0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_L0D_CACHE (0xB42F1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_TIMER (0xB42F2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_EXCTRL (0xB42F3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_PC_MONITOR (0xB42F4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_PROFILING_UNIT (0xB42F5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_MBIST_CONFIG (0xB42F6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_DBUS_REG (0xB42F7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_SONIC (0xB4300000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_L0I_CACHE (0xB4310000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_L0D_CACHE (0xB4311000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_TIMER (0xB4312000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_EXCTRL (0xB4313000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_PC_MONITOR (0xB4314000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_PROFILING_UNIT (0xB4315000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_MBIST_CONFIG (0xB4316000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_DBUS_REG (0xB4317000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_SONIC (0xB4320000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_L0I_CACHE (0xB4330000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_L0D_CACHE (0xB4331000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_TIMER (0xB4332000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_EXCTRL (0xB4333000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_PC_MONITOR (0xB4334000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_PROFILING_UNIT (0xB4335000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_MBIST_CONFIG (0xB4336000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_DBUS_REG (0xB4337000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_SONIC (0xB4340000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_L0I_CACHE (0xB4350000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_L0D_CACHE (0xB4351000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_TIMER (0xB4352000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_EXCTRL (0xB4353000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_PC_MONITOR (0xB4354000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_PROFILING_UNIT (0xB4355000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_MBIST_CONFIG (0xB4356000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_DBUS_REG (0xB4357000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_SONIC (0xB4360000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_L0I_CACHE (0xB4370000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_L0D_CACHE (0xB4371000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_TIMER (0xB4372000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_EXCTRL (0xB4373000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_PC_MONITOR (0xB4374000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_PROFILING_UNIT (0xB4375000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_MBIST_CONFIG (0xB4376000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_DBUS_REG (0xB4377000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_SONIC (0xB4380000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_L0I_CACHE (0xB4390000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_L0D_CACHE (0xB4391000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_TIMER (0xB4392000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_EXCTRL (0xB4393000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_PC_MONITOR (0xB4394000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_PROFILING_UNIT (0xB4395000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_MBIST_CONFIG (0xB4396000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_DBUS_REG (0xB4397000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_SONIC (0xB43A0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_L0I_CACHE (0xB43B0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_L0D_CACHE (0xB43B1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_TIMER (0xB43B2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_EXCTRL (0xB43B3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_PC_MONITOR (0xB43B4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_PROFILING_UNIT (0xB43B5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_MBIST_CONFIG (0xB43B6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_DBUS_REG (0xB43B7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_SONIC (0xB43C0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_L0I_CACHE (0xB43D0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_L0D_CACHE (0xB43D1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_TIMER (0xB43D2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_EXCTRL (0xB43D3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_PC_MONITOR (0xB43D4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_PROFILING_UNIT (0xB43D5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_MBIST_CONFIG (0xB43D6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_DBUS_REG (0xB43D7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_SONIC (0xB43E0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_L0I_CACHE (0xB43F0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_L0D_CACHE (0xB43F1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_TIMER (0xB43F2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_EXCTRL (0xB43F3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_PC_MONITOR (0xB43F4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_PROFILING_UNIT (0xB43F5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_MBIST_CONFIG (0xB43F6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_DBUS_REG (0xB43F7000)
+#define BASE_NADDR_MCORE_MCORE0_L1I_CACHE (0xB4800000)
+#define BASE_NADDR_MCORE_MCORE0_L1D_CACHE_1 (0xB4900000)
+#define BASE_NADDR_MCORE_THREAD0_ICM (0xB4A00000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD0_SONIC_RESERVED0 (0xB4A04000)
+#define BASE_NADDR_MCORE_THREAD1_ICM (0xB4A10000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_SONIC_RESERVED1 (0xB4A14000)
+#define BASE_NADDR_MCORE_THREAD2_ICM (0xB4A20000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_SONIC_RESERVED2 (0xB4A24000)
+#define BASE_NADDR_MCORE_THREAD3_ICM (0xB4A30000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_SONIC_RESERVED3 (0xB4A34000)
+#define BASE_NADDR_MCORE_THREAD4_ICM (0xB4A40000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_SONIC_RESERVED4 (0xB4A44000)
+#define BASE_NADDR_MCORE_THREAD5_ICM (0xB4A50000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_SONIC_RESERVED5 (0xB4A54000)
+#define BASE_NADDR_MCORE_THREAD6_ICM (0xB4A60000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_SONIC_RESERVED6 (0xB4A64000)
+#define BASE_NADDR_MCORE_THREAD7_ICM (0xB4A70000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_SONIC_RESERVED7 (0xB4A74000)
+#define BASE_NADDR_MCORE_THREAD8_ICM (0xB4A80000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_SONIC_RESERVED8 (0xB4A84000)
+#define BASE_NADDR_MCORE_THREAD9_ICM (0xB4A90000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_SONIC_RESERVED9 (0xB4A94000)
+#define BASE_NADDR_MCORE_THREAD10_ICM (0xB4AA0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_SONIC_RESERVED10 (0xB4AA4000)
+#define BASE_NADDR_MCORE_THREAD11_ICM (0xB4AB0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_SONIC_RESERVED11 (0xB4AB4000)
+#define BASE_NADDR_MCORE_THREAD12_ICM (0xB4AC0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_SONIC_RESERVED12 (0xB4AC4000)
+#define BASE_NADDR_MCORE_THREAD13_ICM (0xB4AD0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_SONIC_RESERVED13 (0xB4AD4000)
+#define BASE_NADDR_MCORE_THREAD14_ICM (0xB4AE0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_SONIC_RESERVED14 (0xB4AE4000)
+#define BASE_NADDR_MCORE_THREAD15_ICM (0xB4AF0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_SONIC_RESERVED15 (0xB4AF4000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM0 (0xB4F00000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM1 (0xB4F40000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM2 (0xB4F80000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM3 (0xB4FC0000)
+#define BASE_NADDR_MCORE_MML1_MCORESYS_SHDM (0xB4FFC000)
+#define BASE_NADDR_VCORE_VSYS_DSPSLVSCHEDULER (0xB5000000)
+#define BASE_NADDR_VCORE_VSYS_DSPVCORELOG (0xB5001000)
+#define BASE_NADDR_VCORE_VSYS_VU2GRAM (0xB5002000)
+#define BASE_NADDR_VCORE_VPERI_DBUS1_APB2DBUSCR_INST (0xB5003000)
+#define BASE_NADDR_VCORE_VPERI_A2D (0xB5004000)
+#define BASE_NADDR_VCORE_VPERI_DBUSRECORDER (0xB5005000)
+#define BASE_NADDR_VCORE_VSYS_DBGMON (0xB5006000)
+#define BASE_NADDR_VCORE_VSYS_GLBCON (0xB5007000)
+#define BASE_NADDR_VCORE_VPERI_DSPCORECK_ABUS_REG (0xB5008000)
+#define BASE_NADDR_VCORE_VSYS_SWLA (0xB5010000)
+#define BASE_NADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST (0xB5011000)
+#define BASE_NADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST_1 (0xB5011100)
+#define BASE_NADDR_VCORE_VPERI_PERICK_ABUS_REG (0xB5014000)
+#define BASE_NADDR_VCORE_MBIST_CAT_BUS_DECODER (0xB5020000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_L1_CACHE (0xB5100000)
+#define BASE_NADDR_VCORE_VCORE0_L1D_CACHE (0xB5101000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CLKCTRL (0xB5102000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_EXCEPTION_CONTROLLER (0xB5103000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_PROFILING_UNIT (0xB5104000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_A2D (0xB5105000)
+#define BASE_NADDR_VCORE_VCORE0_A2D_128 (0xB5106000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_D2D (0xB5107000)
+#define BASE_NADDR_VCORE_DBUS_REG (0xB5108000)
+#define BASE_NADDR_VCORE_MML1_DSPEINTC (0xB5180000)
+#define BASE_NADDR_VCORE_VSYS_DSPDBGC1 (0xB5181000)
+#define BASE_NADDR_VCORE_VSYS_DSPCTIWRAP (0xB5182000)
+#define BASE_NADDR_VCORE_VSYS_DSPCTIWRAP_1 (0xB5182020)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE (0xB5200000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_L0I_CACHE (0xB5210000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_DATA_CACHE (0xB5211000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_TIMER (0xB5212000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD0_EXCTRL (0xB5213000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_PC_MONITOR (0xB5214000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD0_PROFILING_UNIT (0xB5215000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_L1 (0xB5220000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_BLAZE (0xB5230000)
+#define BASE_NADDR_VCORE_VCORE0_VU0_VMEM_CFG (0xB5231000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_HLSU (0xB5232000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_PROFILING_UNIT (0xB5233000)
+#define BASE_NADDR_VCORE_VCORE_VU_MBIST_CONFIG (0xB5234000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_VCORE_VU_DBUS (0xB5235000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_SONIC (0xB5240000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_L0I_CACHE (0xB5250000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_L0D_CACHE (0xB5251000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_TIMER (0xB5252000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_EXCTRL (0xB5253000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_PC_MONITOR (0xB5254000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_PROFILING_UNIT (0xB5255000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_VMEM_MEM (0xB5260000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_BLAZE (0xB5270000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_VMEM_CFG (0xB5271000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_HLSU (0xB5272000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_PROFILING_UNIT (0xB5273000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_MBIST_CONFIG (0xB5274000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_DBUS_REG (0xB5275000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_SONIC (0xB5280000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_L0I_CACHE (0xB5290000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_L0D_CACHE (0xB5291000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_TIMER (0xB5292000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_EXCTRL (0xB5293000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_PC_MONITOR (0xB5294000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_PROFILING_UNIT (0xB5295000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_VMEM_MEM (0xB52A0000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_BLAZE (0xB52B0000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_VMEM_CFG (0xB52B1000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_HLSU (0xB52B2000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_PROFILING_UNIT (0xB52B3000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_MBIST_CONFIG (0xB52B4000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_DBUS_REG (0xB52B5000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_SONIC (0xB52C0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_L0I_CACHE (0xB52D0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_L0D_CACHE (0xB52D1000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_TIMER (0xB52D2000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_EXCTRL (0xB52D3000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_PC_MONITOR (0xB52D4000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_PROFILING_UNIT (0xB52D5000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_VMEM_MEM (0xB52E0000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_BLAZE (0xB52F0000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_VMEM_CFG (0xB52F1000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_HLSU (0xB52F2000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_PROFILING_UNIT (0xB52F3000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_MBIST_CONFIG (0xB52F4000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_DBUS_REG (0xB52F5000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_SONIC (0xB5300000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_L0I_CACHE (0xB5310000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_L0D_CACHE (0xB5311000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_TIMER (0xB5312000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_EXCTRL (0xB5313000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_PC_MONITOR (0xB5314000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_PROFILING_UNIT (0xB5315000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_VMEM_MEM (0xB5320000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_BLAZE (0xB5330000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_VMEM_CFG (0xB5331000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_HLSU (0xB5332000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_PROFILING_UNIT (0xB5333000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_MBIST_CONFIG (0xB5334000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_DBUS_REG (0xB5335000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_SONIC (0xB5340000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_L0I_CACHE (0xB5350000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_L0D_CACHE (0xB5351000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_TIMER (0xB5352000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_EXCTRL (0xB5353000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_PC_MONITOR (0xB5354000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_PROFILING_UNIT (0xB5355000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_VMEM_MEM (0xB5360000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_BLAZE (0xB5370000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_VMEM_CFG (0xB5371000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_HLSU (0xB5372000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_PROFILING_UNIT (0xB5373000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_MBIST_CONFIG (0xB5374000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_DBUS_REG (0xB5375000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_SONIC (0xB5380000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_L0I_CACHE (0xB5390000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_L0D_CACHE (0xB5391000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_TIMER (0xB5392000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_EXCTRL (0xB5393000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_PC_MONITOR (0xB5394000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_PROFILING_UNIT (0xB5395000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_VMEM_MEM (0xB53A0000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_BLAZE (0xB53B0000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_VMEM_CFG (0xB53B1000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_HLSU (0xB53B2000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_PROFILING_UNIT (0xB53B3000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_MBIST_CONFIG (0xB53B4000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_DBUS_REG (0xB53B5000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_SONIC (0xB53C0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_L0I_CACHE (0xB53D0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_L0D_CACHE (0xB53D1000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_TIMER (0xB53D2000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_EXCTRL (0xB53D3000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_PC_MONITOR (0xB53D4000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_PROFILING_UNIT (0xB53D5000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_VMEM_MEM (0xB53E0000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_BLAZE (0xB53F0000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_VMEM_CFG (0xB53F1000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_HLSU (0xB53F2000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_PROFILING_UNIT (0xB53F3000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_MBIST_CONFIG (0xB53F4000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_DBUS_REG (0xB53F5000)
+#define BASE_NADDR_VCORE_VCORE0_L1I_CACHE (0xB5800000)
+#define BASE_NADDR_VCORE_VCORE0_L1D_CACHE_1 (0xB5900000)
+#define BASE_NADDR_VCORE_THREAD0_ICM (0xB5A00000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD0_SONIC_RESERVED0 (0xB5A04000)
+#define BASE_NADDR_VCORE_THREAD1_ICM (0xB5A10000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_SONIC_RESERVED1 (0xB5A14000)
+#define BASE_NADDR_VCORE_THREAD2_ICM (0xB5A20000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_SONIC_RESERVED2 (0xB5A24000)
+#define BASE_NADDR_VCORE_THREAD3_ICM (0xB5A30000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_SONIC_RESERVED3 (0xB5A34000)
+#define BASE_NADDR_VCORE_THREAD4_ICM (0xB5A40000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_SONIC_RESERVED4 (0xB5A44000)
+#define BASE_NADDR_VCORE_THREAD5_ICM (0xB5A50000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_SONIC_RESERVED5 (0xB5A54000)
+#define BASE_NADDR_VCORE_THREAD6_ICM (0xB5A60000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_SONIC_RESERVED6 (0xB5A64000)
+#define BASE_NADDR_VCORE_THREAD7_ICM (0xB5A70000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_SONIC_RESERVED7 (0xB5A74000)
+#define BASE_NADDR_GRAM_GRAM_BRIDGE (0xB6000000)
+#define BASE_NADDR_GRAM_GRAM_GLBCON (0xB6F00000)
+#define BASE_NADDR_GRAM_GRAMSYS_MBIST_MBIST_TOP_CFG (0xB6F10000)
+#define BASE_NADDR_GRAM_GRAM_BRIDGE_REG (0xB6F20000)
+#define BASE_NADDR_GRAM_GRAM_REG (0xB6F30000)
+#define BASE_NADDR_GRAM_GRAM_BUS_CONFIG (0xB6F40000)
+#define BASE_NADDR_2ND_ROM_TABLE_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REG_MDPERISYS_MISC_REG (0xB0602000)
+#define BASE_NADDR_MD_DBGMON_MD_DBGMON (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKTL_MDPERI_CLKTL (0xB0603800)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB0604000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB0605000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB0606000)
+#define BASE_NADDR_TOPSM_PROTECT_MDL1_MODEM_TOPSM_PROTECT (0xB060B000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB060C000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB060D000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB060E000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB060F000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0610000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0611000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0612000)
+#define BASE_NADDR_RAKE_BUS_INTF_RAKESYS_BUS_DBGAPB_INTF (0xB0614000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32 (0xB0616000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0618000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0619000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB061A000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB061B000)
+#define BASE_NADDR_BIGRAM_BUS_INTF_BIGRAM_BUS_INTF (0xB061C000)
+#define BASE_NADDR_INR_BUS_INTF_INR_BUS_INTF (0xB061E000)
+#define BASE_NADDR_USIP0_USIP0 (0xB0620000)
+#define BASE_NADDR_USIP1_USIP1 (0xB0621000)
+#define BASE_NADDR_USIPCORE_BUS_INTF_USIPCORE_BUS_INTF (0xB0622000)
+#define BASE_NADDR_L2SRAM_L2SRAM (0xB0624000)
+#define BASE_NADDR_MDMCU_BUS_INTF_VDNR__MDMCU_BUS_INTF (0xB0628000)
+#define BASE_NADDR_MDMCU_COREBUS_INTF_VDNR__MDMCU_COREBUS_INTF (0xB062A000)
+#define BASE_NADDR_MDMCU_BUSMON_MDMCU_BUSMON (0xB062C000)
+#define BASE_NADDR_MDMCU_USIP_BUS_INTF_MDMCU_USIP_BUS_INTF (0xB062D000)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB0630000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_SHAOLIN_DEBUG_PERI (0xB0633000)
+#define BASE_NADDR_SHAOLIN_MACRO_BUS_INTF_VDNR__SHAOLIN_MACRO_BUS_INTF (0xB0634000)
+#define BASE_NADDR_SHAOLIN_BUSMPU_SHAOLIN_BUSMPU (0xB0636000)
+#define BASE_NADDR_SHAOLIN_CM2_SHAOLIN_CM2 (0xB0637000)
+#define BASE_NADDR_SHAOLIN_CORE0__SHAOLIN_CORE0 (0xB0638000)
+#define BASE_NADDR_SHAOLIN_CORE1_SHAOLIN_CORE1 (0xB0639000)
+#define BASE_NADDR_SHAOLIN_CORE2__SHAOLIN_CORE2 (0xB063A000)
+#define BASE_NADDR_SHAOLIN_CORE3_SHAOLIN_CORE3 (0xB063B000)
+#define BASE_NADDR_MDINFRA_BUS4X_REG_MDINFRA_BUS4X_REG (0xB063C000)
+#define BASE_NADDR_MDINFRA_BUS2X_REG_MDINFRA_BUS2X_REG (0xB063D000)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB063E000)
+#define BASE_NADDR_NRL2_BUS_INTF_NRL2_BUS_INTF (0xB0640000)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_RXCPC_NR_DBGAPB_MAS_BUS_INTF (0xB0642000)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2 (0xB0642800)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_RXCPC_NR_DBGAPB_SLV_BUS_INTF (0xB0643000)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2 (0xB0643800)
+#define BASE_NADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF (0xB0644000)
+#define BASE_NADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF_1 (0xB0645000)
+#define BASE_NADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF (0xB0646000)
+#define BASE_NADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF_1 (0xB0647000)
+#define BASE_NADDR_MDAO_MAS_BUS_CK_DBG_MDAO_MAS_BUS_CK_DBG (0xB0648000)
+#define BASE_NADDR_MDAO_SLV_BUS_CK_DBG_MDAO_SLV_BUS_CK_DBG (0xB0649000)
+#define BASE_NADDR_MD_DVFS_TOP_CK_DBG_MD_DVFS_TOP_CK_DBG (0xB0649800)
+#define BASE_NADDR_MDL1_TOPSM_MDL1_TOPSM (0xB064A000)
+#define BASE_NADDR_RFSLPC_RFSLPC (0xB064B000)
+#define BASE_NADDR_MD2G_BUS_MD2G_BUS (0xB064C000)
+#define BASE_NADDR_CSSYS_BUS_CK_DBG_CSSYS_BUS_CK_DBG (0xB064E000)
+#define BASE_NADDR_CSSYS_BUS_DIV2_CK_DBG_CSSYS_BUS_DIV2_CK_DBG (0xB064E800)
+#define BASE_NADDR_MDAO_BUS_CK_DBG_MDAO_BUS_CK_DBG (0xB064F000)
+#define BASE_NADDR_VCORE_TOP_TH0_SONIC_VCORE (0xB0650000)
+#define BASE_NADDR_VCORE_TOP_TH0_PC_MONITOR_VCORE (0xB0650400)
+#define BASE_NADDR_VCORE_TOP_TH0_VUDBUS_VCORE (0xB0650480)
+#define BASE_NADDR_VCORE_TOP_TH1_SONIC_VCORE (0xB0650600)
+#define BASE_NADDR_VCORE_TOP_TH1_PC_MONITOR_VCORE (0xB0650A00)
+#define BASE_NADDR_VCORE_TOP_TH1_VUDBUS_VCORE (0xB0650A80)
+#define BASE_NADDR_VCORE_TOP_TH2_SONIC_VCORE (0xB0650C00)
+#define BASE_NADDR_VCORE_TOP_TH2_PC_MONITOR_VCORE (0xB0651000)
+#define BASE_NADDR_VCORE_TOP_TH2_VUDBUS_VCORE (0xB0651080)
+#define BASE_NADDR_VCORE_TOP_TH3_SONIC_VCORE (0xB0651200)
+#define BASE_NADDR_VCORE_TOP_TH3_PC_MONITOR_VCORE (0xB0651600)
+#define BASE_NADDR_VCORE_TOP_TH3_VUDBUS_VCORE (0xB0651680)
+#define BASE_NADDR_VCORE_TOP_TH4_SONIC_VCORE (0xB0651800)
+#define BASE_NADDR_VCORE_TOP_TH4_PC_MONITOR_VCORE (0xB0651C00)
+#define BASE_NADDR_VCORE_TOP_TH4_VUDBUS_VCORE (0xB0651C80)
+#define BASE_NADDR_VCORE_TOP_TH5_SONIC_VCORE (0xB0651E00)
+#define BASE_NADDR_VCORE_TOP_TH5_PC_MONITOR_VCORE (0xB0652200)
+#define BASE_NADDR_VCORE_TOP_TH5_VUDBUS_VCORE (0xB0652280)
+#define BASE_NADDR_VCORE_TOP_TH6_SONIC_VCORE (0xB0652400)
+#define BASE_NADDR_VCORE_TOP_TH6_PC_MONITOR_VCORE (0xB0652800)
+#define BASE_NADDR_VCORE_TOP_TH6_VUDBUS_VCORE (0xB0652880)
+#define BASE_NADDR_VCORE_TOP_TH7_SONIC_VCORE (0xB0652A00)
+#define BASE_NADDR_VCORE_TOP_TH7_PC_MONITOR_VCORE (0xB0652E00)
+#define BASE_NADDR_VCORE_TOP_TH7_VUDBUS_VCORE (0xB0652E80)
+#define BASE_NADDR_VCORE_TOP_L1_DBUS_VCORE (0xB0653000)
+#define BASE_NADDR_VCORE_TOP_A2D32_VCORE (0xB0654000)
+#define BASE_NADDR_VCORE_TOP_A2D128_VCORE (0xB0654080)
+#define BASE_NADDR_VCORECK_ABUS_VCORECK_ABUS (0xB0655000)
+#define BASE_NADDR_VCORE_DIV2CK_ABUS_VCORE_DIV2CK_ABUS (0xB0655800)
+#define BASE_NADDR_VCORE_CK_DBUS_VCORE_CK_DBUS (0xB0656000)
+#define BASE_NADDR_VCORE_DIV2CK_DBUS_VCORE_DIV2CK_DBUS (0xB0656800)
+#define BASE_NADDR_BUS_RECORDER_BUS_RECORDER (0xB0657000)
+#define BASE_NADDR_VPERIA2D_DBGAPB_VPERIA2D_DBGAPB (0xB0657800)
+#define BASE_NADDR_DEBUG_MONITOR_FOR_DBG_FLAG_MML1_DSPVCORE_DBGMON_WRAP (0xB0657880)
+#define BASE_NADDR_VCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_VCORE_MML1_DSPCTIWRAP (0xB0657900)
+#define BASE_NADDR_VCORE_PAR_AO_CR_VCORE_PAR_AO_CR (0xB0657A00)
+#define BASE_NADDR_GRAM_PERI_GRAM_PERI (0xB0658000)
+#define BASE_NADDR_MCORE0_TOP_TH0_SONIC_MCORE0 (0xB0660000)
+#define BASE_NADDR_MCORE0_TOP_TH0_PC_MONITOR_MCORE0 (0xB0660400)
+#define BASE_NADDR_MCORE0_TOP_TH0_VUDBUS_MCORE0 (0xB0660480)
+#define BASE_NADDR_MCORE0_TOP_TH1_SONIC_MCORE0 (0xB0660600)
+#define BASE_NADDR_MCORE0_TOP_TH1_PC_MONITOR_MCORE0 (0xB0660A00)
+#define BASE_NADDR_MCORE0_TOP_TH1_VUDBUS_MCORE0 (0xB0660A80)
+#define BASE_NADDR_MCORE0_TOP_TH2_SONIC_MCORE0 (0xB0660C00)
+#define BASE_NADDR_MCORE0_TOP_TH2_PC_MONITOR_MCORE0 (0xB0661000)
+#define BASE_NADDR_MCORE0_TOP_TH2_VUDBUS_MCORE0 (0xB0661080)
+#define BASE_NADDR_MCORE0_TOP_TH3_SONIC_MCORE0 (0xB0661200)
+#define BASE_NADDR_MCORE0_TOP_TH3_PC_MONITOR_MCORE0 (0xB0661600)
+#define BASE_NADDR_MCORE0_TOP_TH3_VUDBUS_MCORE0 (0xB0661680)
+#define BASE_NADDR_MCORE0_TOP_TH4_SONIC_MCORE0 (0xB0661800)
+#define BASE_NADDR_MCORE0_TOP_TH4_PC_MONITOR_MCORE0 (0xB0661C00)
+#define BASE_NADDR_MCORE0_TOP_TH4_VUDBUS_MCORE0 (0xB0661C80)
+#define BASE_NADDR_MCORE0_TOP_TH5_SONIC_MCORE0 (0xB0661E00)
+#define BASE_NADDR_MCORE0_TOP_TH5_PC_MONITOR_MCORE0 (0xB0662200)
+#define BASE_NADDR_MCORE0_TOP_TH5_VUDBUS_MCORE0 (0xB0662280)
+#define BASE_NADDR_MCORE0_TOP_TH6_SONIC_MCORE0 (0xB0662400)
+#define BASE_NADDR_MCORE0_TOP_TH6_PC_MONITOR_MCORE0 (0xB0662800)
+#define BASE_NADDR_MCORE0_TOP_TH6_VUDBUS_MCORE0 (0xB0662880)
+#define BASE_NADDR_MCORE0_TOP_TH7_SONIC_MCORE0 (0xB0662A00)
+#define BASE_NADDR_MCORE0_TOP_TH7_PC_MONITOR_MCORE0 (0xB0662E00)
+#define BASE_NADDR_MCORE0_TOP_TH7_VUDBUS_MCORE0 (0xB0662E80)
+#define BASE_NADDR_MCORE0_TOP_TH8_SONIC_MCORE0 (0xB0663000)
+#define BASE_NADDR_MCORE0_TOP_TH8_PC_MONITOR_MCORE0 (0xB0663400)
+#define BASE_NADDR_MCORE0_TOP_TH8_VUDBUS_MCORE0 (0xB0663480)
+#define BASE_NADDR_MCORE0_TOP_TH9_SONIC_MCORE0 (0xB0663600)
+#define BASE_NADDR_MCORE0_TOP_TH9_PC_MONITOR_MCORE0 (0xB0663A00)
+#define BASE_NADDR_MCORE0_TOP_TH9_VUDBUS_MCORE0 (0xB0663A80)
+#define BASE_NADDR_MCORE0_TOP_TH10_SONIC_MCORE0 (0xB0663C00)
+#define BASE_NADDR_MCORE0_TOP_TH10_PC_MONITOR_MCORE0 (0xB0664000)
+#define BASE_NADDR_MCORE0_TOP_TH10_VUDBUS_MCORE0 (0xB0664080)
+#define BASE_NADDR_MCORE0_TOP_TH11_SONIC_MCORE0 (0xB0664200)
+#define BASE_NADDR_MCORE0_TOP_TH11_PC_MONITOR_MCORE0 (0xB0664600)
+#define BASE_NADDR_MCORE0_TOP_TH11_VUDBUS_MCORE0 (0xB0664680)
+#define BASE_NADDR_MCORE0_TOP_TH12_SONIC_MCORE0 (0xB0664800)
+#define BASE_NADDR_MCORE0_TOP_TH12_PC_MONITOR_MCORE0 (0xB0664C00)
+#define BASE_NADDR_MCORE0_TOP_TH12_VUDBUS_MCORE0 (0xB0664C80)
+#define BASE_NADDR_MCORE0_TOP_TH13_SONIC_MCORE0 (0xB0664E00)
+#define BASE_NADDR_MCORE0_TOP_TH13_PC_MONITOR_MCORE0 (0xB0665200)
+#define BASE_NADDR_MCORE0_TOP_TH13_VUDBUS_MCORE0 (0xB0665280)
+#define BASE_NADDR_MCORE0_TOP_TH14_SONIC_MCORE0 (0xB0665400)
+#define BASE_NADDR_MCORE0_TOP_TH14_PC_MONITOR_MCORE0 (0xB0665800)
+#define BASE_NADDR_MCORE0_TOP_TH14_VUDBUS_MCORE0 (0xB0665880)
+#define BASE_NADDR_MCORE0_TOP_TH15_SONIC_MCORE0 (0xB0665A00)
+#define BASE_NADDR_MCORE0_TOP_TH15_PC_MONITOR_MCORE0 (0xB0665E00)
+#define BASE_NADDR_MCORE0_TOP_TH15_VUDBUS_MCORE0 (0xB0665E80)
+#define BASE_NADDR_MCORE0_TOP_L1DBUS_MCORE0 (0xB0666000)
+#define BASE_NADDR_MCORE0_TOP_L1I_CACHE_MCORE0 (0xB0667000)
+#define BASE_NADDR_MCORE0_TOP_L1D_CACHE_MCORE0 (0xB0667200)
+#define BASE_NADDR_MCORE0_TOP_A2D32_MCORE0 (0xB0667400)
+#define BASE_NADDR_MCORE0_TOP_A2D128_MCORE0 (0xB0667480)
+#define BASE_NADDR_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB (0xB0670000)
+#define BASE_NADDR_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB (0xB0671000)
+#define BASE_NADDR_MML1_MPERI_PERICK_ABUS_REG_DBGAPB_MML1_MPERI_PERICK_ABUS_REG_DBGAPB (0xB0672000)
+#define BASE_NADDR_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB (0xB0673000)
+#define BASE_NADDR_MML1_MPERI_DSPCK_DBUS_REG_DBG_MML1_MPERI_DSPCK_DBUS_REG_DBG (0xB0674000)
+#define BASE_NADDR_MML1_MPERI_PERICK_DBUS_REG_DBG_MML1_MPERI_PERICK_DBUS_REG_DBG (0xB0675000)
+#define BASE_NADDR_MML1_MCOREPERI_ABUSMON_TOP_DBG_MML1_MCOREPERI_ABUSMON_TOP_DBG (0xB0676000)
+#define BASE_NADDR_MML1_MPERI_DBUSRECORDER_DBG_MML1_MPERI_DBUSRECORDER_DBG (0xB0677000)
+#define BASE_NADDR_MPERIA2D_DBGAPB_MPERIA2D_DBGAPB (0xB0678000)
+#define BASE_NADDR_MML1_MCORESYS_DBGMON_WRAP_MML1_MCORESYS_DBGMON_WRAP (0xB0679000)
+#define BASE_NADDR_MML1_MPERI_DSPCORECK_DBUS_REG_DBG_MML1_MPERI_DSPCORECK_DBUS_REG_DBG (0xB067A000)
+#define BASE_NADDR_CMCS_MAS_MDTOP_BUS4X_CK_REG_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0680000)
+#define BASE_NADDR_CMCS_SLV_MDTOP_BUS4X_CK_REG_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0681000)
+#define BASE_NADDR_CM_CS_BUS_CK_REG_MML1_CM_CS_BUS_CK_ABUS_REG (0xB0682000)
+#define BASE_NADDR_CS_NR_BUS_CK_REG_MML1_CS_NR_BUS_CK_ABUS_REG (0xB0683000)
+#define BASE_NADDR_CMCS_NR_CM_NR_CK_REG_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xB0684000)
+#define BASE_NADDR_CM_NR_MDTOP_BUS4X_CK_REG_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xB0685000)
+#define BASE_NADDR_CMCS_NR_RXTFC_NR_CK_REG_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xB0686000)
+#define BASE_NADDR_RXTFC_MDTOP_BUS4X_CK_REG_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xB0687000)
+#define BASE_NADDR_CMCS_NR_RXTDB_NR_CK_REG_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xB0688000)
+#define BASE_NADDR_RXTDB_MDTOP_BUS4X_CK_REG_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xB0689000)
+#define BASE_NADDR_CMCS_NR_RXTDB_PBCH_NR_CK_REG_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xB068A000)
+#define BASE_NADDR_RXTDB_PBCH_MDTOP_BUS4X_CK_REG_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xB068B000)
+#define BASE_NADDR_TX_NR_MAS_TXBSRP_NR_CK_REG_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xB0690000)
+#define BASE_NADDR_TX_NR_MAS_MDTOP_BUS4X_CK_REG_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0691000)
+#define BASE_NADDR_TX_NR_SLV_TXBSRP_NR_CK_REG_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xB0692000)
+#define BASE_NADDR_TX_NR_SLV_MDTOP_BUS4X_CK_REG_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0693000)
+#define BASE_NADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF (0xB0694000)
+#define BASE_NADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF_1 (0xB0696000)
+#define BASE_NADDR_DFESYS_BUS_INTF_DFESYS_MAS_BUS_CONFIG_REAL (0xB0698000)
+#define BASE_NADDR_DFESYS_BUS_INTF_DFESYS_SLV_BUS_CONFIG (0xB069A000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_BUS_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xB069C000)
+#define BASE_NADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xB069D000)
+#define BASE_NADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xB069F0000)
+#define BASE_NADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xB069F8000)
+#define BASE_NADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TXDFE_468M_CK_ABUS_REG (0xB06A0000)
+#define BASE_NADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TPC_468M_CK_ABUS_REG (0xB06A3000)
+#define BASE_NADDR_MMW_RXDFE_BUS_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xB06A4000)
+#define BASE_NADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xB06A5000)
+#define BASE_NADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xB06A7000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RESERVED2 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_EGID (0xB7010000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_EGOC (0xB7012000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7014000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7016000)
+#define BASE_NADDR_RXDDM_NR_RESERVED3 (0xB7018000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_STIME_LOG (0xB701A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MDCC (0xB701C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB701E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7020000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB7022000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCE (0xB7024000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_PP (0xB7026000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB7028000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB702A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB702C000)
+#define BASE_NADDR_RXDDM_NR_MML1_RXDDM_CK_ABUS_REG (0xB702E000)
+#define BASE_NADDR_RXDDM_NR_MML1_RXDDM_HALF_CK_ABUS_REG (0xB7030000)
+#define BASE_NADDR_RXDDM_NR_SLOT_RNTI (0xB7200000)
+#define BASE_NADDR_RXDDM_NR_RESERVED4 (0xB7201000)
+#define BASE_NADDR_RXDDM_NR_SYM (0xB7220000)
+#define BASE_NADDR_RXDDM_NR_RESERVED5 (0xB7228000)
+#define BASE_NADDR_RXDDM_NR_MASK_TYPE0 (0xB7240000)
+#define BASE_NADDR_RXDDM_NR_MASK_TYPE1 (0xB7260000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED_0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED_1 (0xB7960000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_EMI_CK_ABUS_REG (0xB7970000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_EMI_HALF_CK_ABUS_REG (0xB7980000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_SD_CK_ABUS_REG (0xB7990000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_SD_HALF_CK_ABUS_REG (0xB79A0000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_CK_ABUS_REG (0xB79B0000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_HALF_CK_ABUS_REG (0xB79C0000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_M_CK_ABUS_REG (0xB7C0C000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_M_HALF_CK_ABUS_REG (0xB7C0E000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_CK_ABUS_REG (0xB7C10000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_HALF_CK_ABUS_REG (0xB7C12000)
+#define BASE_NADDR_RXCPC_NR_RESERVED0 (0xB7C14000)
+#define BASE_NADDR_RXCPC_NR_RESERVED1 (0xB7C16000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CFG_SP (0xB7C20000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MD_DVFS_TOP_CONFIG (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_MIPI (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MAS_BUS_CONFIG (0xB8160000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_DFESYS_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MMW_TXDFE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MODEML1_AO_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MODEML1_AO_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_RESERVED1 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_RESERVED2 (0xB8B00000)
+#define BASE_NADDR_DFESYS_RESERVED3 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_RESERVED4 (0xB8B70000)
+#define BASE_NADDR_DFESYS_RESERVED5 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_DFE_COMDMA (0xB8E00000)
+#define BASE_NADDR_DFESYS_RESERVED6 (0xB8E10000)
+#define BASE_NADDR_DFESYS_RESERVED7 (0xB8E20000)
+#define BASE_NADDR_DFESYS_RESERVED8 (0xB8E30000)
+#define BASE_NADDR_DFESYS_RESERVED9 (0xB8E40000)
+#define BASE_NADDR_DFESYS_RESERVED10 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED11 (0xB8EA0000)
+#define BASE_NADDR_DFESYS_MAS_BUS_INTF (0xB8EB0000)
+#define BASE_NADDR_DFESYS_SLV_BUS_INTF (0xB8EC0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CSSYS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CSSYS_BUS_DIV2_CONFIG (0xB9838000)
+#define BASE_NADDR_CSSYS_MDAO_BUS_CONFIG (0xB983C000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_SCN_RPT (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_CS_NR_CM_CS_BUS_CONFIG (0xB9C60000)
+#define BASE_NADDR_CMCS_PAR_AO_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBDC00000)
+#define BASE_NADDR_CMCS_PAR_AO_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBDC10000)
+#define BASE_NADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG (0xBDC20000)
+#define BASE_NADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG (0xBDC30000)
+#define BASE_NADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG (0xBDC40000)
+#define BASE_NADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO (0xBDC50000)
+#define BASE_NADDR_CMCS_PAR_AO_MCORE_PAR_AO_REG (0xBDC50400)
+#define BASE_NADDR_CMCS_PAR_AO_U_VCORE_PAR_WRAP_SRAM_AO (0xBDC60000)
+#define BASE_NADDR_CMCS_PAR_AO_U_VCORE_PAR_AO_CR (0xBDC60400)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_0_SM_CONFIG (0xBDC60600)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_1_SM_CONFIG (0xBDC60680)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_2_SM_CONFIG (0xBDC60700)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_3_SM_CONFIG (0xBDC60780)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_4_SM_CONFIG (0xBDC60800)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_5_SM_CONFIG (0xBDC60880)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_6_SM_CONFIG (0xBDC60900)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_7_SM_CONFIG (0xBDC60980)
+#define BASE_NADDR_CMCS_PAR_AO_U_GRAM_MEM_CONFIG (0xBDC70000)
+#define BASE_NADDR_CMCS_PAR_AO_U_TX_NR_MEM_CONFIG (0xBDC80000)
+#define BASE_NADDR_CMCS_PAR_AO_U_CMCS_NR_MEM_CONFIG (0xBDC90000)
+#define BASE_NADDR_CMCS_PAR_AO_U_CMCS_PAR_AO_CONFIG_REG (0xBDCA0000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xBA008000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBA010000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xBA018000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA020000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA030000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_2 (0xBA040000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_3 (0xBA050000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_4 (0xBA060000)
+#define BASE_NADDR_TXSYS_NR_TXBSRP_GLB_APB_CONFIG (0xBA070000)
+#define BASE_NADDR_TXSYS_NR_TXBSRP_BIT_CONTROLLER (0xBA080000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA100000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG (0xBA101000)
+#define BASE_NADDR_TXSYS_NR_RESERVED0 (0xBA102000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_PAR_AO_CONFIG_REG (0xBA10C000)
+#define BASE_NADDR_TXSYS_NR_RESERVED1 (0xBA10D000)
+#define BASE_NADDR_TXSYS_NR_RESERVED2 (0xBA10E000)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_WRAP (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_0 (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_DVTCRC (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_1 (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_DVTCRC_1 (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_1 (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_2 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB_SSS (0xBA490000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB_SSS (0xBA4A0000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP_SSS (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT_SSS (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_SSS (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL_SSS (0xBA4E0000)
+#define BASE_NADDR_CM_NR_CM_NR_DVTCRC_SSS (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB_CSIRS (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB_CSIRS (0xBA510000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP_CSIRS (0xBA520000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT_CSIRS (0xBA530000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_CSIRS (0xBA540000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL_CSIRS (0xBA550000)
+#define BASE_NADDR_CM_NR_CM_NR_DVTCRC_CSIRS (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_3 (0xBA570000)
+#define BASE_NADDR_CM_NR_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xBA580000)
+#define BASE_NADDR_CM_NR_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xBA590000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED1 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTFC_RESERVED2 (0xBA870000)
+#define BASE_NADDR_RXTFC_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xBA880000)
+#define BASE_NADDR_RXTFC_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xBA890000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_3 (0xBAC70000)
+#define BASE_NADDR_RXTDB_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xBAC80000)
+#define BASE_NADDR_RXTDB_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xBAC90000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BUS_CONFIG (0xBB880000)
+#define BASE_NADDR_BIGRAM0_INR_SLV_BUS_CONFIG (0xBB890000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST_CONFIG (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_MAS_HALF_CK_ABUS_REG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_MAS_CK_ABUS_REG (0xBC990000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_SLV_HALF_CK_ABUS_REG (0xBC9A0000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_SLV_CK_ABUS_REG (0xBC9B0000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_LTE_CE_SC (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE_OC1 (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_OC2 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_PDSCH (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_PDCCH (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_EPDCCH (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_PBCH (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_SRAM_CTRL_AO (0xBD000000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MMW_DBB_CTRLACNT (0xBD001000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_GLOBAL_CON_AO (0xBD002000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_RESERVED0 (0xBD003000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xBD010000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RFAC (0xBD020000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CM_DATA_INTF (0xBD040000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_EVENTGEN (0xBD050000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED1 (0xBD060000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xBD080000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_LOG (0xBD090000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_COMDMA (0xBD0A0000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_CONTROLLER (0xBD0B0000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD (0xBD0B8000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_1 (0xBD0B8100)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_2 (0xBD0B8200)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED2 (0xBD0B8300)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_MBIST (0xBD0B9000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_GLOBAL_CON (0xBD0BA000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED3 (0xBD0BB000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_CM_COMM_REG (0xBD0F8000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG (0xBD0F8400)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_1 (0xBD0F8800)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_2 (0xBD0F8C00)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED4 (0xBD0F9000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_TOP (0xBD100000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_LOG (0xBD108000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_SCH (0xBD110000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xBD120000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED5 (0xBD130000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BPI (0xBD180000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_DIGRF_MIPI_M (0xBD190000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_TOP (0xBD200000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SCH (0xBD210000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI0 (0xBD218000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI1 (0xBD219000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI2 (0xBD21A000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI3 (0xBD21B000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI4 (0xBD21C000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI5 (0xBD21D000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI6 (0xBD21E000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI7 (0xBD21F000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xBD220000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED6 (0xBD230000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED7 (0xBD300000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_RESERVED0 (0xBD400000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_RESERVED1 (0xBD640000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TOP_CTRL (0xBD410000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_TXK (0xBD420000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_GLOBAL_CON (0xBD430000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BUS_CONFIG (0xBD440000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_MBIST_CONFIG_CAT (0xBD450000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TX_ACNT_TICK_GEN (0xBD460000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TQ (0xBD470000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR (0xBD480000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_1 (0xBD490000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_2 (0xBD4A0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_3 (0xBD4B0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_4 (0xBD4C0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_5 (0xBD4D0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_6 (0xBD4E0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_7 (0xBD4F0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D (0xBD500000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_1 (0xBD510000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_2 (0xBD520000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_3 (0xBD530000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_4 (0xBD540000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_5 (0xBD550000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_6 (0xBD560000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_7 (0xBD570000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_8 (0xBD580000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_9 (0xBD590000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_A (0xBD5A0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF (0xBD5B0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_1 (0xBD5C0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_2 (0xBD5D0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_3 (0xBD5E0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_ABB_MIXEDSYS (0xBD5F0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MRX_DATA_DUMP (0xBD600000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_PCC_BB (0xBD610000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_U_MMW_PCC_BB_TOP_1 (0xBD620000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_LOG (0xBD660000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE0_COMDMA (0xBD670000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE1_COMDMA (0xBD680000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MML1_MMW_TPC_468M_CK_ABUS_REG (0xBD690000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_TPC_M (0xBD700000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_TPC_M_1 (0xBD780000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER (0xBD800000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER_RESERVED0 (0xBD804000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_EVTGEN (0xBD808000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_SLPC (0xBD80C000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_RESERVED1 (0xBD810000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_PAR_WRAP_SRAM_AO (0xBD820000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_CONFIG_AO_REG (0xBD821000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX0 (0xBD828000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX1 (0xBD829000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX2 (0xBD82A000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX3 (0xBD82B000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX0 (0xBD82C000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX1 (0xBD82D000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_SYS (0xBD82E000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xBD830000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CONFIG_REG (0xBD840000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MBIST_CAT_MBIST_TOP_CFG (0xBD844000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xBD850000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_RXDFE_BB_NR_MMW_DM_SEL_WRAP (0xBD860000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CS_SEL_WRAP (0xBD870000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_CMSEL_MMW (0xBD880000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_CMIPG_MMW (0xBD888000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_LOG (0xBD890000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MRSG (0xBD8A0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE0_COMDMA (0xBD8C0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_DMA_DESCRT (0xBD8D0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_0 (0xBD8F0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_1 (0xBD8F8000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_0 (0xBD900000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_0 (0xBD920000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_1 (0xBD920200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_2 (0xBD920400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_3 (0xBD920600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_4 (0xBD920800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_5 (0xBD920A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_6 (0xBD920C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_7 (0xBD920E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_0 (0xBD922000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_1 (0xBD922200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_2 (0xBD922400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_3 (0xBD922600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_4 (0xBD922800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_5 (0xBD922A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_6 (0xBD922C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_7 (0xBD922E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ1 (0xBD924000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_WM (0xBD92A000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TOT_PATT (0xBD92E000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_2 (0xBD940000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_2 (0xBD960000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_1 (0xBD980000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_0 (0xBD9A0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_1 (0xBD9A0200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_2 (0xBD9A0400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_3 (0xBD9A0600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_4 (0xBD9A0800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_5 (0xBD9A0A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_6 (0xBD9A0C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_7 (0xBD9A0E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_0 (0xBD9A2000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_1 (0xBD9A2200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_2 (0xBD9A2400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_3 (0xBD9A2600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_4 (0xBD9A2800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_5 (0xBD9A2A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_6 (0xBD9A2C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_7 (0xBD9A2E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ1 (0xBD9A4000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_WM (0xBD9AA000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TOT_PATT (0xBD9AE000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_MBIST_CONFIG (0xBD9C0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_GLBCON (0xBD9F0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_SET (0xBDA00000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_HEADER (0xBDA04000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_STATUS (0xBDA08000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_P_REG (0xBDA10000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_L_REG (0xBDA20000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_IMM_REG (0xBDA30000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_P_REG (0xBDA40000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_L_REG (0xBDA50000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CS_AGC (0xBDA60000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_468 (0xBDA70000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_52 (0xBDA71000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_0 (0xBDA71800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_1 (0xBDA71C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC (0xBDA80000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_1 (0xBDA84000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_2 (0xBDA88000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_3 (0xBDA90000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_4 (0xBDAA0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_5 (0xBDAB0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_6 (0xBDAC0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_7 (0xBDAD0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_8 (0xBDAE0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_468 (0xBDAF0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_52 (0xBDAF1000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_0 (0xBDAF1800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_1 (0xBDAF1C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xBDAFF000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_DM (0xBDB00000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD0_PM (0xBDBA0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD1_PM (0xBDBB0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_COREDBG (0xBDBD0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_GC_PM (0xBDBE0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE1_COMDMA (0xBDBFE000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ADC_TEST_ARBITOR (0xBDBFF000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MDL1_MODEM_TOPSM_PROTECT (0xB0080000)
+#define BASE_ADDR_MDPERI_COMDMA (0xB0090000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_MDRXSYS_SRAM_AO (0xB0190000)
+#define BASE_ADDR_MDPERI_VU_SM_CONGIF_0 (0xB0191000)
+#define BASE_ADDR_MDPERI_VU_SM_CONGIF_1 (0xB0192000)
+#define BASE_ADDR_MDPERI_MDRXAO_CONFIG (0xB0193000)
+#define BASE_ADDR_MDPERI_RESERVED0 (0xB0194000)
+#define BASE_ADDR_MDPERI_BRP_SRAM_AO (0xB01A0000)
+#define BASE_ADDR_MDPERI_NRL2_SRAM_AO (0xB01B0000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_SRAM_AO (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_BUS2X_REG (0xB0440000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_SHAOLIN_SEMAPHORE (0xB0460000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_BUS4X_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_HW_LOG (0xB0500000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0540000)
+#define BASE_ADDR_MDINFRA_TRACE_NR_TOP_1 (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_AO_MISC_CTRL (0xB0260000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_SRAM_AO (0xB0270000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_MEM_DELSEL_CFG (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_MEM_DELSEL_CFG (0xB0281000)
+#define BASE_ADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE1_MEM_DELSEL_CFG (0xB0282000)
+#define BASE_ADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE2_MEM_DELSEL_CFG (0xB0283000)
+#define BASE_ADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE3_MEM_DELSEL_CFG (0xB0284000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_CONFIG (0xB02C0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__BUSMPU_INFRA (0xB02D0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_COREBUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_IA_MACRO_DELSEL_ADR_IF (0xB03B0000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MBIST_MDCORE_FOR_CFG_DELSEL_CFG_WRAP (0xB03B1000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_MBIST_REPAIR_TOP_CFG_WRAP (0xB0D10000)
+#define BASE_ADDR_USIP_MBIST_DELSEL_TOP_CFG_WRAP (0xB0D20000)
+#define BASE_ADDR_USIP_USIPCORE_BUS_CONFIG (0xB0D30000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_UL_CIPHER_CONFIG (0xB2014000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG_REG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_1 (0xB2036000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_2 (0xB2037000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG_SRAM (0xB2038000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_4 (0xB2039000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_ST (0xB203A000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_0 (0xB203B000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_1 (0xB203C000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_2 (0xB203D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_3 (0xB203E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_4 (0xB203F000)
+#define BASE_ADDR_NRL2_NRL2_DL_META_AGG (0xB2040000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC2 (0xB2041000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC3 (0xB2042000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC4 (0xB2043000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC5 (0xB2044000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC6 (0xB2045000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC7 (0xB2046000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC8 (0xB2047000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_PPRO (0xB2048000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC2 (0xB2049000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC3 (0xB204A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC4 (0xB204B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC5 (0xB204C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC6 (0xB204D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC7 (0xB204E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC8 (0xB204F000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_PPRO (0xB2050000)
+#define BASE_ADDR_NRL2_NRL2_BUS_CFG (0xB2051000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_PPRO_QP (0xB2052000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_0 (0xB2053000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_1 (0xB2054000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_2 (0xB2055000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_3 (0xB2056000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_4 (0xB2057000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_5 (0xB2058000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_6 (0xB2059000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_7 (0xB205A000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_8 (0xB205B000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC0 (0xB205C000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC1 (0xB205D000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC2 (0xB205E000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC3 (0xB205F000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC4 (0xB2060000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC5 (0xB2061000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC6 (0xB2062000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC7 (0xB2063000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC8 (0xB2064000)
+#define BASE_ADDR_MCORE_MSYS_DSPM2VSCHEDULER (0xB4000000)
+#define BASE_ADDR_MCORE_MPERI_DSPCK_ABUS_REG (0xB4001000)
+#define BASE_ADDR_MCORE_MPERI_DBUS3_APB2DBUSCR_INST (0xB4002000)
+#define BASE_ADDR_MCORE_MML1_DSPM2DDMSCHEDULER (0xB4004000)
+#define BASE_ADDR_MCORE_MSYS_DSPCSIF (0xB4010000)
+#define BASE_ADDR_MCORE_MSYS_DSPMCORELOG (0xB4011000)
+#define BASE_ADDR_MCORE_MML1_DSPCBSCHEDULER (0xB4012000)
+#define BASE_ADDR_MCORE_MPERI_DSPCORECK_ABUS_REG (0xB4013000)
+#define BASE_ADDR_MCORE_MPERI_DBUS1_APB2DBUSCR_INST (0xB4014000)
+#define BASE_ADDR_MCORE_MPERI_A2D (0xB4016000)
+#define BASE_ADDR_MCORE_MPERI_DBUSRECORDER (0xB4017000)
+#define BASE_ADDR_MCORE_MSYS_DSPUSTIMER (0xB4018000)
+#define BASE_ADDR_MCORE_MSYS_PROFILING (0xB4019000)
+#define BASE_ADDR_MCORE_MML1_DSPMPPT (0xB401A000)
+#define BASE_ADDR_MCORE_MSYS_DSPBTDMA (0xB4021000)
+#define BASE_ADDR_MCORE_MSYS_DSPSWLA (0xB4022000)
+#define BASE_ADDR_MCORE_MPERI_DBUS2_APB2DBUSCR_INST (0xB4023000)
+#define BASE_ADDR_MCORE_MSYSY_GLBCON (0xB4030000)
+#define BASE_ADDR_MCORE_MSYS_DBGMON (0xB4031000)
+#define BASE_ADDR_MCORE_MPERI_PERICK_ABUS_REG (0xB4032000)
+#define BASE_ADDR_MCORE_MML1_MCOREPERI_ABUSMON (0xB4033000)
+#define BASE_ADDR_MCORE_MSYS_COMDMA (0xB4034000)
+#define BASE_ADDR_MCORE_MSYS_MBIST_CAT (0xB4040000)
+#define BASE_ADDR_MCORE_MCORE_L1_CACHE (0xB4100000)
+#define BASE_ADDR_MCORE_MCORE0_L1D_CACHE (0xB4101000)
+#define BASE_ADDR_MCORE_MCORE_CLKCTRL (0xB4102000)
+#define BASE_ADDR_MCORE_MCORE_EXCEPTION_CONTROLLER (0xB4103000)
+#define BASE_ADDR_MCORE_MCORE0_L1_PROFILING_UNIT (0xB4104000)
+#define BASE_ADDR_MCORE_MCORE_A2D (0xB4105000)
+#define BASE_ADDR_MCORE_MCORE0_A2D_128 (0xB4106000)
+#define BASE_ADDR_MCORE_MCORE_D2D (0xB4107000)
+#define BASE_ADDR_MCORE_MCORE_D2A (0xB4108000)
+#define BASE_ADDR_MCORE_DBUS_REG (0xB4109000)
+#define BASE_ADDR_MCORE_MSYS_ISRD (0xB4180000)
+#define BASE_ADDR_MCORE_MML1_DSPEINTC (0xB4181000)
+#define BASE_ADDR_MCORE_MSYS_DSPDBGC1 (0xB4182000)
+#define BASE_ADDR_MCORE_MSYS_DSPCTIWRAP (0xB4183000)
+#define BASE_ADDR_MCORE_MCORE_CORE (0xB4200000)
+#define BASE_ADDR_MCORE_MCORE_L0I_CACHE (0xB4210000)
+#define BASE_ADDR_MCORE_MCORE_DATA_CACHE (0xB4211000)
+#define BASE_ADDR_MCORE_MCORE_TIMER (0xB4212000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD0_EXCTRL (0xB4213000)
+#define BASE_ADDR_MCORE_MCORE_PC_MONITOR (0xB4214000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD0_PROFILING_UNIT (0xB4215000)
+#define BASE_ADDR_MCORE_MCORE_MBIST_CONFIG_WRAP (0xB4216000)
+#define BASE_ADDR_MCORE_MCORE_MCORE_CRIT_DBUS (0xB4217000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_SONIC (0xB4220000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_L0I_CACHE (0xB4230000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_L0D_CACHE (0xB4231000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_TIMER (0xB4232000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_EXCTRL (0xB4233000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_PC_MONITOR (0xB4234000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_PROFILING_UNIT (0xB4235000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_MBIST_CONFIG (0xB4236000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_DBUS_REG (0xB4237000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_SONIC (0xB4240000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_L0I_CACHE (0xB4250000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_L0D_CACHE (0xB4251000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_TIMER (0xB4252000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_EXCTRL (0xB4253000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_PC_MONITOR (0xB4254000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_PROFILING_UNIT (0xB4255000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_MBIST_CONFIG (0xB4256000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_DBUS_REG (0xB4257000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_SONIC (0xB4260000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_L0I_CACHE (0xB4270000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_L0D_CACHE (0xB4271000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_TIMER (0xB4272000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_EXCTRL (0xB4273000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_PC_MONITOR (0xB4274000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_PROFILING_UNIT (0xB4275000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_MBIST_CONFIG (0xB4276000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_DBUS_REG (0xB4277000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_SONIC (0xB4280000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_L0I_CACHE (0xB4290000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_L0D_CACHE (0xB4291000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_TIMER (0xB4292000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_EXCTRL (0xB4293000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_PC_MONITOR (0xB4294000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_PROFILING_UNIT (0xB4295000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_MBIST_CONFIG (0xB4296000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_DBUS_REG (0xB4297000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_SONIC (0xB42A0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_L0I_CACHE (0xB42B0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_L0D_CACHE (0xB42B1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_TIMER (0xB42B2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_EXCTRL (0xB42B3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_PC_MONITOR (0xB42B4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_PROFILING_UNIT (0xB42B5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_MBIST_CONFIG (0xB42B6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_DBUS_REG (0xB42B7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_SONIC (0xB42C0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_L0I_CACHE (0xB42D0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_L0D_CACHE (0xB42D1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_TIMER (0xB42D2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_EXCTRL (0xB42D3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_PC_MONITOR (0xB42D4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_PROFILING_UNIT (0xB42D5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_MBIST_CONFIG (0xB42D6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_DBUS_REG (0xB42D7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_SONIC (0xB42E0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_L0I_CACHE (0xB42F0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_L0D_CACHE (0xB42F1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_TIMER (0xB42F2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_EXCTRL (0xB42F3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_PC_MONITOR (0xB42F4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_PROFILING_UNIT (0xB42F5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_MBIST_CONFIG (0xB42F6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_DBUS_REG (0xB42F7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_SONIC (0xB4300000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_L0I_CACHE (0xB4310000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_L0D_CACHE (0xB4311000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_TIMER (0xB4312000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_EXCTRL (0xB4313000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_PC_MONITOR (0xB4314000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_PROFILING_UNIT (0xB4315000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_MBIST_CONFIG (0xB4316000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_DBUS_REG (0xB4317000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_SONIC (0xB4320000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_L0I_CACHE (0xB4330000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_L0D_CACHE (0xB4331000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_TIMER (0xB4332000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_EXCTRL (0xB4333000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_PC_MONITOR (0xB4334000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_PROFILING_UNIT (0xB4335000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_MBIST_CONFIG (0xB4336000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_DBUS_REG (0xB4337000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_SONIC (0xB4340000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_L0I_CACHE (0xB4350000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_L0D_CACHE (0xB4351000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_TIMER (0xB4352000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_EXCTRL (0xB4353000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_PC_MONITOR (0xB4354000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_PROFILING_UNIT (0xB4355000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_MBIST_CONFIG (0xB4356000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_DBUS_REG (0xB4357000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_SONIC (0xB4360000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_L0I_CACHE (0xB4370000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_L0D_CACHE (0xB4371000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_TIMER (0xB4372000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_EXCTRL (0xB4373000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_PC_MONITOR (0xB4374000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_PROFILING_UNIT (0xB4375000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_MBIST_CONFIG (0xB4376000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_DBUS_REG (0xB4377000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_SONIC (0xB4380000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_L0I_CACHE (0xB4390000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_L0D_CACHE (0xB4391000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_TIMER (0xB4392000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_EXCTRL (0xB4393000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_PC_MONITOR (0xB4394000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_PROFILING_UNIT (0xB4395000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_MBIST_CONFIG (0xB4396000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_DBUS_REG (0xB4397000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_SONIC (0xB43A0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_L0I_CACHE (0xB43B0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_L0D_CACHE (0xB43B1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_TIMER (0xB43B2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_EXCTRL (0xB43B3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_PC_MONITOR (0xB43B4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_PROFILING_UNIT (0xB43B5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_MBIST_CONFIG (0xB43B6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_DBUS_REG (0xB43B7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_SONIC (0xB43C0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_L0I_CACHE (0xB43D0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_L0D_CACHE (0xB43D1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_TIMER (0xB43D2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_EXCTRL (0xB43D3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_PC_MONITOR (0xB43D4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_PROFILING_UNIT (0xB43D5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_MBIST_CONFIG (0xB43D6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_DBUS_REG (0xB43D7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_SONIC (0xB43E0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_L0I_CACHE (0xB43F0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_L0D_CACHE (0xB43F1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_TIMER (0xB43F2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_EXCTRL (0xB43F3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_PC_MONITOR (0xB43F4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_PROFILING_UNIT (0xB43F5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_MBIST_CONFIG (0xB43F6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_DBUS_REG (0xB43F7000)
+#define BASE_ADDR_MCORE_MCORE0_L1I_CACHE (0xB4800000)
+#define BASE_ADDR_MCORE_MCORE0_L1D_CACHE_1 (0xB4900000)
+#define BASE_ADDR_MCORE_THREAD0_ICM (0xB4A00000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD0_SONIC_RESERVED0 (0xB4A04000)
+#define BASE_ADDR_MCORE_THREAD1_ICM (0xB4A10000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_SONIC_RESERVED1 (0xB4A14000)
+#define BASE_ADDR_MCORE_THREAD2_ICM (0xB4A20000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_SONIC_RESERVED2 (0xB4A24000)
+#define BASE_ADDR_MCORE_THREAD3_ICM (0xB4A30000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_SONIC_RESERVED3 (0xB4A34000)
+#define BASE_ADDR_MCORE_THREAD4_ICM (0xB4A40000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_SONIC_RESERVED4 (0xB4A44000)
+#define BASE_ADDR_MCORE_THREAD5_ICM (0xB4A50000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_SONIC_RESERVED5 (0xB4A54000)
+#define BASE_ADDR_MCORE_THREAD6_ICM (0xB4A60000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_SONIC_RESERVED6 (0xB4A64000)
+#define BASE_ADDR_MCORE_THREAD7_ICM (0xB4A70000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_SONIC_RESERVED7 (0xB4A74000)
+#define BASE_ADDR_MCORE_THREAD8_ICM (0xB4A80000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_SONIC_RESERVED8 (0xB4A84000)
+#define BASE_ADDR_MCORE_THREAD9_ICM (0xB4A90000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_SONIC_RESERVED9 (0xB4A94000)
+#define BASE_ADDR_MCORE_THREAD10_ICM (0xB4AA0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_SONIC_RESERVED10 (0xB4AA4000)
+#define BASE_ADDR_MCORE_THREAD11_ICM (0xB4AB0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_SONIC_RESERVED11 (0xB4AB4000)
+#define BASE_ADDR_MCORE_THREAD12_ICM (0xB4AC0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_SONIC_RESERVED12 (0xB4AC4000)
+#define BASE_ADDR_MCORE_THREAD13_ICM (0xB4AD0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_SONIC_RESERVED13 (0xB4AD4000)
+#define BASE_ADDR_MCORE_THREAD14_ICM (0xB4AE0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_SONIC_RESERVED14 (0xB4AE4000)
+#define BASE_ADDR_MCORE_THREAD15_ICM (0xB4AF0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_SONIC_RESERVED15 (0xB4AF4000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM0 (0xB4F00000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM1 (0xB4F40000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM2 (0xB4F80000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM3 (0xB4FC0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_SHDM (0xB4FFC000)
+#define BASE_ADDR_VCORE_VSYS_DSPSLVSCHEDULER (0xB5000000)
+#define BASE_ADDR_VCORE_VSYS_DSPVCORELOG (0xB5001000)
+#define BASE_ADDR_VCORE_VSYS_VU2GRAM (0xB5002000)
+#define BASE_ADDR_VCORE_VPERI_DBUS1_APB2DBUSCR_INST (0xB5003000)
+#define BASE_ADDR_VCORE_VPERI_A2D (0xB5004000)
+#define BASE_ADDR_VCORE_VPERI_DBUSRECORDER (0xB5005000)
+#define BASE_ADDR_VCORE_VSYS_DBGMON (0xB5006000)
+#define BASE_ADDR_VCORE_VSYS_GLBCON (0xB5007000)
+#define BASE_ADDR_VCORE_VPERI_DSPCORECK_ABUS_REG (0xB5008000)
+#define BASE_ADDR_VCORE_VSYS_SWLA (0xB5010000)
+#define BASE_ADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST (0xB5011000)
+#define BASE_ADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST_1 (0xB5011100)
+#define BASE_ADDR_VCORE_VPERI_PERICK_ABUS_REG (0xB5014000)
+#define BASE_ADDR_VCORE_MBIST_CAT_BUS_DECODER (0xB5020000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_L1_CACHE (0xB5100000)
+#define BASE_ADDR_VCORE_VCORE0_L1D_CACHE (0xB5101000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CLKCTRL (0xB5102000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_EXCEPTION_CONTROLLER (0xB5103000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_PROFILING_UNIT (0xB5104000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_A2D (0xB5105000)
+#define BASE_ADDR_VCORE_VCORE0_A2D_128 (0xB5106000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_D2D (0xB5107000)
+#define BASE_ADDR_VCORE_DBUS_REG (0xB5108000)
+#define BASE_ADDR_VCORE_MML1_DSPEINTC (0xB5180000)
+#define BASE_ADDR_VCORE_VSYS_DSPDBGC1 (0xB5181000)
+#define BASE_ADDR_VCORE_VSYS_DSPCTIWRAP (0xB5182000)
+#define BASE_ADDR_VCORE_VSYS_DSPCTIWRAP_1 (0xB5182020)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE (0xB5200000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_L0I_CACHE (0xB5210000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_DATA_CACHE (0xB5211000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_TIMER (0xB5212000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD0_EXCTRL (0xB5213000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_PC_MONITOR (0xB5214000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD0_PROFILING_UNIT (0xB5215000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_L1 (0xB5220000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_BLAZE (0xB5230000)
+#define BASE_ADDR_VCORE_VCORE0_VU0_VMEM_CFG (0xB5231000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_HLSU (0xB5232000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_PROFILING_UNIT (0xB5233000)
+#define BASE_ADDR_VCORE_VCORE_VU_MBIST_CONFIG (0xB5234000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_VCORE_VU_DBUS (0xB5235000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_SONIC (0xB5240000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_L0I_CACHE (0xB5250000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_L0D_CACHE (0xB5251000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_TIMER (0xB5252000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_EXCTRL (0xB5253000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_PC_MONITOR (0xB5254000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_PROFILING_UNIT (0xB5255000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_VMEM_MEM (0xB5260000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_BLAZE (0xB5270000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_VMEM_CFG (0xB5271000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_HLSU (0xB5272000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_PROFILING_UNIT (0xB5273000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_MBIST_CONFIG (0xB5274000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_DBUS_REG (0xB5275000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_SONIC (0xB5280000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_L0I_CACHE (0xB5290000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_L0D_CACHE (0xB5291000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_TIMER (0xB5292000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_EXCTRL (0xB5293000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_PC_MONITOR (0xB5294000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_PROFILING_UNIT (0xB5295000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_VMEM_MEM (0xB52A0000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_BLAZE (0xB52B0000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_VMEM_CFG (0xB52B1000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_HLSU (0xB52B2000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_PROFILING_UNIT (0xB52B3000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_MBIST_CONFIG (0xB52B4000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_DBUS_REG (0xB52B5000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_SONIC (0xB52C0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_L0I_CACHE (0xB52D0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_L0D_CACHE (0xB52D1000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_TIMER (0xB52D2000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_EXCTRL (0xB52D3000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_PC_MONITOR (0xB52D4000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_PROFILING_UNIT (0xB52D5000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_VMEM_MEM (0xB52E0000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_BLAZE (0xB52F0000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_VMEM_CFG (0xB52F1000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_HLSU (0xB52F2000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_PROFILING_UNIT (0xB52F3000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_MBIST_CONFIG (0xB52F4000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_DBUS_REG (0xB52F5000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_SONIC (0xB5300000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_L0I_CACHE (0xB5310000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_L0D_CACHE (0xB5311000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_TIMER (0xB5312000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_EXCTRL (0xB5313000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_PC_MONITOR (0xB5314000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_PROFILING_UNIT (0xB5315000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_VMEM_MEM (0xB5320000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_BLAZE (0xB5330000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_VMEM_CFG (0xB5331000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_HLSU (0xB5332000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_PROFILING_UNIT (0xB5333000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_MBIST_CONFIG (0xB5334000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_DBUS_REG (0xB5335000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_SONIC (0xB5340000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_L0I_CACHE (0xB5350000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_L0D_CACHE (0xB5351000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_TIMER (0xB5352000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_EXCTRL (0xB5353000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_PC_MONITOR (0xB5354000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_PROFILING_UNIT (0xB5355000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_VMEM_MEM (0xB5360000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_BLAZE (0xB5370000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_VMEM_CFG (0xB5371000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_HLSU (0xB5372000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_PROFILING_UNIT (0xB5373000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_MBIST_CONFIG (0xB5374000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_DBUS_REG (0xB5375000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_SONIC (0xB5380000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_L0I_CACHE (0xB5390000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_L0D_CACHE (0xB5391000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_TIMER (0xB5392000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_EXCTRL (0xB5393000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_PC_MONITOR (0xB5394000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_PROFILING_UNIT (0xB5395000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_VMEM_MEM (0xB53A0000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_BLAZE (0xB53B0000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_VMEM_CFG (0xB53B1000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_HLSU (0xB53B2000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_PROFILING_UNIT (0xB53B3000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_MBIST_CONFIG (0xB53B4000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_DBUS_REG (0xB53B5000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_SONIC (0xB53C0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_L0I_CACHE (0xB53D0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_L0D_CACHE (0xB53D1000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_TIMER (0xB53D2000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_EXCTRL (0xB53D3000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_PC_MONITOR (0xB53D4000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_PROFILING_UNIT (0xB53D5000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_VMEM_MEM (0xB53E0000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_BLAZE (0xB53F0000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_VMEM_CFG (0xB53F1000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_HLSU (0xB53F2000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_PROFILING_UNIT (0xB53F3000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_MBIST_CONFIG (0xB53F4000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_DBUS_REG (0xB53F5000)
+#define BASE_ADDR_VCORE_VCORE0_L1I_CACHE (0xB5800000)
+#define BASE_ADDR_VCORE_VCORE0_L1D_CACHE_1 (0xB5900000)
+#define BASE_ADDR_VCORE_THREAD0_ICM (0xB5A00000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD0_SONIC_RESERVED0 (0xB5A04000)
+#define BASE_ADDR_VCORE_THREAD1_ICM (0xB5A10000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_SONIC_RESERVED1 (0xB5A14000)
+#define BASE_ADDR_VCORE_THREAD2_ICM (0xB5A20000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_SONIC_RESERVED2 (0xB5A24000)
+#define BASE_ADDR_VCORE_THREAD3_ICM (0xB5A30000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_SONIC_RESERVED3 (0xB5A34000)
+#define BASE_ADDR_VCORE_THREAD4_ICM (0xB5A40000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_SONIC_RESERVED4 (0xB5A44000)
+#define BASE_ADDR_VCORE_THREAD5_ICM (0xB5A50000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_SONIC_RESERVED5 (0xB5A54000)
+#define BASE_ADDR_VCORE_THREAD6_ICM (0xB5A60000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_SONIC_RESERVED6 (0xB5A64000)
+#define BASE_ADDR_VCORE_THREAD7_ICM (0xB5A70000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_SONIC_RESERVED7 (0xB5A74000)
+#define BASE_ADDR_GRAM_GRAM_BRIDGE (0xB6000000)
+#define BASE_ADDR_GRAM_GRAM_GLBCON (0xB6F00000)
+#define BASE_ADDR_GRAM_GRAMSYS_MBIST_MBIST_TOP_CFG (0xB6F10000)
+#define BASE_ADDR_GRAM_GRAM_BRIDGE_REG (0xB6F20000)
+#define BASE_ADDR_GRAM_GRAM_REG (0xB6F30000)
+#define BASE_ADDR_GRAM_GRAM_BUS_CONFIG (0xB6F40000)
+#define BASE_ADDR_2ND_ROM_TABLE_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REG_MDPERISYS_MISC_REG (0xB0602000)
+#define BASE_ADDR_MD_DBGMON_MD_DBGMON (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKTL_MDPERI_CLKTL (0xB0603800)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB0604000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB0605000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB0606000)
+#define BASE_ADDR_TOPSM_PROTECT_MDL1_MODEM_TOPSM_PROTECT (0xB060B000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB060C000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB060D000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB060E000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB060F000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0610000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0611000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0612000)
+#define BASE_ADDR_RAKE_BUS_INTF_RAKESYS_BUS_DBGAPB_INTF (0xB0614000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32 (0xB0616000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0618000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0619000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB061A000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB061B000)
+#define BASE_ADDR_BIGRAM_BUS_INTF_BIGRAM_BUS_INTF (0xB061C000)
+#define BASE_ADDR_INR_BUS_INTF_INR_BUS_INTF (0xB061E000)
+#define BASE_ADDR_USIP0_USIP0 (0xB0620000)
+#define BASE_ADDR_USIP1_USIP1 (0xB0621000)
+#define BASE_ADDR_USIPCORE_BUS_INTF_USIPCORE_BUS_INTF (0xB0622000)
+#define BASE_ADDR_L2SRAM_L2SRAM (0xB0624000)
+#define BASE_ADDR_MDMCU_BUS_INTF_VDNR__MDMCU_BUS_INTF (0xB0628000)
+#define BASE_ADDR_MDMCU_COREBUS_INTF_VDNR__MDMCU_COREBUS_INTF (0xB062A000)
+#define BASE_ADDR_MDMCU_BUSMON_MDMCU_BUSMON (0xB062C000)
+#define BASE_ADDR_MDMCU_USIP_BUS_INTF_MDMCU_USIP_BUS_INTF (0xB062D000)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB0630000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_SHAOLIN_DEBUG_PERI (0xB0633000)
+#define BASE_ADDR_SHAOLIN_MACRO_BUS_INTF_VDNR__SHAOLIN_MACRO_BUS_INTF (0xB0634000)
+#define BASE_ADDR_SHAOLIN_BUSMPU_SHAOLIN_BUSMPU (0xB0636000)
+#define BASE_ADDR_SHAOLIN_CM2_SHAOLIN_CM2 (0xB0637000)
+#define BASE_ADDR_SHAOLIN_CORE0__SHAOLIN_CORE0 (0xB0638000)
+#define BASE_ADDR_SHAOLIN_CORE1_SHAOLIN_CORE1 (0xB0639000)
+#define BASE_ADDR_SHAOLIN_CORE2__SHAOLIN_CORE2 (0xB063A000)
+#define BASE_ADDR_SHAOLIN_CORE3_SHAOLIN_CORE3 (0xB063B000)
+#define BASE_ADDR_MDINFRA_BUS4X_REG_MDINFRA_BUS4X_REG (0xB063C000)
+#define BASE_ADDR_MDINFRA_BUS2X_REG_MDINFRA_BUS2X_REG (0xB063D000)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB063E000)
+#define BASE_ADDR_NRL2_BUS_INTF_NRL2_BUS_INTF (0xB0640000)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_RXCPC_NR_DBGAPB_MAS_BUS_INTF (0xB0642000)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2 (0xB0642800)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_RXCPC_NR_DBGAPB_SLV_BUS_INTF (0xB0643000)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2 (0xB0643800)
+#define BASE_ADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF (0xB0644000)
+#define BASE_ADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF_1 (0xB0645000)
+#define BASE_ADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF (0xB0646000)
+#define BASE_ADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF_1 (0xB0647000)
+#define BASE_ADDR_MDAO_MAS_BUS_CK_DBG_MDAO_MAS_BUS_CK_DBG (0xB0648000)
+#define BASE_ADDR_MDAO_SLV_BUS_CK_DBG_MDAO_SLV_BUS_CK_DBG (0xB0649000)
+#define BASE_ADDR_MD_DVFS_TOP_CK_DBG_MD_DVFS_TOP_CK_DBG (0xB0649800)
+#define BASE_ADDR_MDL1_TOPSM_MDL1_TOPSM (0xB064A000)
+#define BASE_ADDR_RFSLPC_RFSLPC (0xB064B000)
+#define BASE_ADDR_MD2G_BUS_MD2G_BUS (0xB064C000)
+#define BASE_ADDR_CSSYS_BUS_CK_DBG_CSSYS_BUS_CK_DBG (0xB064E000)
+#define BASE_ADDR_CSSYS_BUS_DIV2_CK_DBG_CSSYS_BUS_DIV2_CK_DBG (0xB064E800)
+#define BASE_ADDR_MDAO_BUS_CK_DBG_MDAO_BUS_CK_DBG (0xB064F000)
+#define BASE_ADDR_VCORE_TOP_TH0_SONIC_VCORE (0xB0650000)
+#define BASE_ADDR_VCORE_TOP_TH0_PC_MONITOR_VCORE (0xB0650400)
+#define BASE_ADDR_VCORE_TOP_TH0_VUDBUS_VCORE (0xB0650480)
+#define BASE_ADDR_VCORE_TOP_TH1_SONIC_VCORE (0xB0650600)
+#define BASE_ADDR_VCORE_TOP_TH1_PC_MONITOR_VCORE (0xB0650A00)
+#define BASE_ADDR_VCORE_TOP_TH1_VUDBUS_VCORE (0xB0650A80)
+#define BASE_ADDR_VCORE_TOP_TH2_SONIC_VCORE (0xB0650C00)
+#define BASE_ADDR_VCORE_TOP_TH2_PC_MONITOR_VCORE (0xB0651000)
+#define BASE_ADDR_VCORE_TOP_TH2_VUDBUS_VCORE (0xB0651080)
+#define BASE_ADDR_VCORE_TOP_TH3_SONIC_VCORE (0xB0651200)
+#define BASE_ADDR_VCORE_TOP_TH3_PC_MONITOR_VCORE (0xB0651600)
+#define BASE_ADDR_VCORE_TOP_TH3_VUDBUS_VCORE (0xB0651680)
+#define BASE_ADDR_VCORE_TOP_TH4_SONIC_VCORE (0xB0651800)
+#define BASE_ADDR_VCORE_TOP_TH4_PC_MONITOR_VCORE (0xB0651C00)
+#define BASE_ADDR_VCORE_TOP_TH4_VUDBUS_VCORE (0xB0651C80)
+#define BASE_ADDR_VCORE_TOP_TH5_SONIC_VCORE (0xB0651E00)
+#define BASE_ADDR_VCORE_TOP_TH5_PC_MONITOR_VCORE (0xB0652200)
+#define BASE_ADDR_VCORE_TOP_TH5_VUDBUS_VCORE (0xB0652280)
+#define BASE_ADDR_VCORE_TOP_TH6_SONIC_VCORE (0xB0652400)
+#define BASE_ADDR_VCORE_TOP_TH6_PC_MONITOR_VCORE (0xB0652800)
+#define BASE_ADDR_VCORE_TOP_TH6_VUDBUS_VCORE (0xB0652880)
+#define BASE_ADDR_VCORE_TOP_TH7_SONIC_VCORE (0xB0652A00)
+#define BASE_ADDR_VCORE_TOP_TH7_PC_MONITOR_VCORE (0xB0652E00)
+#define BASE_ADDR_VCORE_TOP_TH7_VUDBUS_VCORE (0xB0652E80)
+#define BASE_ADDR_VCORE_TOP_L1_DBUS_VCORE (0xB0653000)
+#define BASE_ADDR_VCORE_TOP_A2D32_VCORE (0xB0654000)
+#define BASE_ADDR_VCORE_TOP_A2D128_VCORE (0xB0654080)
+#define BASE_ADDR_VCORECK_ABUS_VCORECK_ABUS (0xB0655000)
+#define BASE_ADDR_VCORE_DIV2CK_ABUS_VCORE_DIV2CK_ABUS (0xB0655800)
+#define BASE_ADDR_VCORE_CK_DBUS_VCORE_CK_DBUS (0xB0656000)
+#define BASE_ADDR_VCORE_DIV2CK_DBUS_VCORE_DIV2CK_DBUS (0xB0656800)
+#define BASE_ADDR_BUS_RECORDER_BUS_RECORDER (0xB0657000)
+#define BASE_ADDR_VPERIA2D_DBGAPB_VPERIA2D_DBGAPB (0xB0657800)
+#define BASE_ADDR_DEBUG_MONITOR_FOR_DBG_FLAG_MML1_DSPVCORE_DBGMON_WRAP (0xB0657880)
+#define BASE_ADDR_VCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_VCORE_MML1_DSPCTIWRAP (0xB0657900)
+#define BASE_ADDR_VCORE_PAR_AO_CR_VCORE_PAR_AO_CR (0xB0657A00)
+#define BASE_ADDR_GRAM_PERI_GRAM_PERI (0xB0658000)
+#define BASE_ADDR_MCORE0_TOP_TH0_SONIC_MCORE0 (0xB0660000)
+#define BASE_ADDR_MCORE0_TOP_TH0_PC_MONITOR_MCORE0 (0xB0660400)
+#define BASE_ADDR_MCORE0_TOP_TH0_VUDBUS_MCORE0 (0xB0660480)
+#define BASE_ADDR_MCORE0_TOP_TH1_SONIC_MCORE0 (0xB0660600)
+#define BASE_ADDR_MCORE0_TOP_TH1_PC_MONITOR_MCORE0 (0xB0660A00)
+#define BASE_ADDR_MCORE0_TOP_TH1_VUDBUS_MCORE0 (0xB0660A80)
+#define BASE_ADDR_MCORE0_TOP_TH2_SONIC_MCORE0 (0xB0660C00)
+#define BASE_ADDR_MCORE0_TOP_TH2_PC_MONITOR_MCORE0 (0xB0661000)
+#define BASE_ADDR_MCORE0_TOP_TH2_VUDBUS_MCORE0 (0xB0661080)
+#define BASE_ADDR_MCORE0_TOP_TH3_SONIC_MCORE0 (0xB0661200)
+#define BASE_ADDR_MCORE0_TOP_TH3_PC_MONITOR_MCORE0 (0xB0661600)
+#define BASE_ADDR_MCORE0_TOP_TH3_VUDBUS_MCORE0 (0xB0661680)
+#define BASE_ADDR_MCORE0_TOP_TH4_SONIC_MCORE0 (0xB0661800)
+#define BASE_ADDR_MCORE0_TOP_TH4_PC_MONITOR_MCORE0 (0xB0661C00)
+#define BASE_ADDR_MCORE0_TOP_TH4_VUDBUS_MCORE0 (0xB0661C80)
+#define BASE_ADDR_MCORE0_TOP_TH5_SONIC_MCORE0 (0xB0661E00)
+#define BASE_ADDR_MCORE0_TOP_TH5_PC_MONITOR_MCORE0 (0xB0662200)
+#define BASE_ADDR_MCORE0_TOP_TH5_VUDBUS_MCORE0 (0xB0662280)
+#define BASE_ADDR_MCORE0_TOP_TH6_SONIC_MCORE0 (0xB0662400)
+#define BASE_ADDR_MCORE0_TOP_TH6_PC_MONITOR_MCORE0 (0xB0662800)
+#define BASE_ADDR_MCORE0_TOP_TH6_VUDBUS_MCORE0 (0xB0662880)
+#define BASE_ADDR_MCORE0_TOP_TH7_SONIC_MCORE0 (0xB0662A00)
+#define BASE_ADDR_MCORE0_TOP_TH7_PC_MONITOR_MCORE0 (0xB0662E00)
+#define BASE_ADDR_MCORE0_TOP_TH7_VUDBUS_MCORE0 (0xB0662E80)
+#define BASE_ADDR_MCORE0_TOP_TH8_SONIC_MCORE0 (0xB0663000)
+#define BASE_ADDR_MCORE0_TOP_TH8_PC_MONITOR_MCORE0 (0xB0663400)
+#define BASE_ADDR_MCORE0_TOP_TH8_VUDBUS_MCORE0 (0xB0663480)
+#define BASE_ADDR_MCORE0_TOP_TH9_SONIC_MCORE0 (0xB0663600)
+#define BASE_ADDR_MCORE0_TOP_TH9_PC_MONITOR_MCORE0 (0xB0663A00)
+#define BASE_ADDR_MCORE0_TOP_TH9_VUDBUS_MCORE0 (0xB0663A80)
+#define BASE_ADDR_MCORE0_TOP_TH10_SONIC_MCORE0 (0xB0663C00)
+#define BASE_ADDR_MCORE0_TOP_TH10_PC_MONITOR_MCORE0 (0xB0664000)
+#define BASE_ADDR_MCORE0_TOP_TH10_VUDBUS_MCORE0 (0xB0664080)
+#define BASE_ADDR_MCORE0_TOP_TH11_SONIC_MCORE0 (0xB0664200)
+#define BASE_ADDR_MCORE0_TOP_TH11_PC_MONITOR_MCORE0 (0xB0664600)
+#define BASE_ADDR_MCORE0_TOP_TH11_VUDBUS_MCORE0 (0xB0664680)
+#define BASE_ADDR_MCORE0_TOP_TH12_SONIC_MCORE0 (0xB0664800)
+#define BASE_ADDR_MCORE0_TOP_TH12_PC_MONITOR_MCORE0 (0xB0664C00)
+#define BASE_ADDR_MCORE0_TOP_TH12_VUDBUS_MCORE0 (0xB0664C80)
+#define BASE_ADDR_MCORE0_TOP_TH13_SONIC_MCORE0 (0xB0664E00)
+#define BASE_ADDR_MCORE0_TOP_TH13_PC_MONITOR_MCORE0 (0xB0665200)
+#define BASE_ADDR_MCORE0_TOP_TH13_VUDBUS_MCORE0 (0xB0665280)
+#define BASE_ADDR_MCORE0_TOP_TH14_SONIC_MCORE0 (0xB0665400)
+#define BASE_ADDR_MCORE0_TOP_TH14_PC_MONITOR_MCORE0 (0xB0665800)
+#define BASE_ADDR_MCORE0_TOP_TH14_VUDBUS_MCORE0 (0xB0665880)
+#define BASE_ADDR_MCORE0_TOP_TH15_SONIC_MCORE0 (0xB0665A00)
+#define BASE_ADDR_MCORE0_TOP_TH15_PC_MONITOR_MCORE0 (0xB0665E00)
+#define BASE_ADDR_MCORE0_TOP_TH15_VUDBUS_MCORE0 (0xB0665E80)
+#define BASE_ADDR_MCORE0_TOP_L1DBUS_MCORE0 (0xB0666000)
+#define BASE_ADDR_MCORE0_TOP_L1I_CACHE_MCORE0 (0xB0667000)
+#define BASE_ADDR_MCORE0_TOP_L1D_CACHE_MCORE0 (0xB0667200)
+#define BASE_ADDR_MCORE0_TOP_A2D32_MCORE0 (0xB0667400)
+#define BASE_ADDR_MCORE0_TOP_A2D128_MCORE0 (0xB0667480)
+#define BASE_ADDR_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB (0xB0670000)
+#define BASE_ADDR_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB (0xB0671000)
+#define BASE_ADDR_MML1_MPERI_PERICK_ABUS_REG_DBGAPB_MML1_MPERI_PERICK_ABUS_REG_DBGAPB (0xB0672000)
+#define BASE_ADDR_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB (0xB0673000)
+#define BASE_ADDR_MML1_MPERI_DSPCK_DBUS_REG_DBG_MML1_MPERI_DSPCK_DBUS_REG_DBG (0xB0674000)
+#define BASE_ADDR_MML1_MPERI_PERICK_DBUS_REG_DBG_MML1_MPERI_PERICK_DBUS_REG_DBG (0xB0675000)
+#define BASE_ADDR_MML1_MCOREPERI_ABUSMON_TOP_DBG_MML1_MCOREPERI_ABUSMON_TOP_DBG (0xB0676000)
+#define BASE_ADDR_MML1_MPERI_DBUSRECORDER_DBG_MML1_MPERI_DBUSRECORDER_DBG (0xB0677000)
+#define BASE_ADDR_MPERIA2D_DBGAPB_MPERIA2D_DBGAPB (0xB0678000)
+#define BASE_ADDR_MML1_MCORESYS_DBGMON_WRAP_MML1_MCORESYS_DBGMON_WRAP (0xB0679000)
+#define BASE_ADDR_MML1_MPERI_DSPCORECK_DBUS_REG_DBG_MML1_MPERI_DSPCORECK_DBUS_REG_DBG (0xB067A000)
+#define BASE_ADDR_CMCS_MAS_MDTOP_BUS4X_CK_REG_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0680000)
+#define BASE_ADDR_CMCS_SLV_MDTOP_BUS4X_CK_REG_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0681000)
+#define BASE_ADDR_CM_CS_BUS_CK_REG_MML1_CM_CS_BUS_CK_ABUS_REG (0xB0682000)
+#define BASE_ADDR_CS_NR_BUS_CK_REG_MML1_CS_NR_BUS_CK_ABUS_REG (0xB0683000)
+#define BASE_ADDR_CMCS_NR_CM_NR_CK_REG_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xB0684000)
+#define BASE_ADDR_CM_NR_MDTOP_BUS4X_CK_REG_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xB0685000)
+#define BASE_ADDR_CMCS_NR_RXTFC_NR_CK_REG_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xB0686000)
+#define BASE_ADDR_RXTFC_MDTOP_BUS4X_CK_REG_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xB0687000)
+#define BASE_ADDR_CMCS_NR_RXTDB_NR_CK_REG_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xB0688000)
+#define BASE_ADDR_RXTDB_MDTOP_BUS4X_CK_REG_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xB0689000)
+#define BASE_ADDR_CMCS_NR_RXTDB_PBCH_NR_CK_REG_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xB068A000)
+#define BASE_ADDR_RXTDB_PBCH_MDTOP_BUS4X_CK_REG_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xB068B000)
+#define BASE_ADDR_TX_NR_MAS_TXBSRP_NR_CK_REG_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xB0690000)
+#define BASE_ADDR_TX_NR_MAS_MDTOP_BUS4X_CK_REG_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0691000)
+#define BASE_ADDR_TX_NR_SLV_TXBSRP_NR_CK_REG_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xB0692000)
+#define BASE_ADDR_TX_NR_SLV_MDTOP_BUS4X_CK_REG_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0693000)
+#define BASE_ADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF (0xB0694000)
+#define BASE_ADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF_1 (0xB0696000)
+#define BASE_ADDR_DFESYS_BUS_INTF_DFESYS_MAS_BUS_CONFIG_REAL (0xB0698000)
+#define BASE_ADDR_DFESYS_BUS_INTF_DFESYS_SLV_BUS_CONFIG (0xB069A000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_BUS_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xB069C000)
+#define BASE_ADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xB069D000)
+#define BASE_ADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xB069F0000)
+#define BASE_ADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xB069F8000)
+#define BASE_ADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TXDFE_468M_CK_ABUS_REG (0xB06A0000)
+#define BASE_ADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TPC_468M_CK_ABUS_REG (0xB06A3000)
+#define BASE_ADDR_MMW_RXDFE_BUS_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xB06A4000)
+#define BASE_ADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xB06A5000)
+#define BASE_ADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xB06A7000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RESERVED2 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_EGID (0xB7010000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_EGOC (0xB7012000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7014000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7016000)
+#define BASE_ADDR_RXDDM_NR_RESERVED3 (0xB7018000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_STIME_LOG (0xB701A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MDCC (0xB701C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB701E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7020000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB7022000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCE (0xB7024000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_PP (0xB7026000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB7028000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB702A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB702C000)
+#define BASE_ADDR_RXDDM_NR_MML1_RXDDM_CK_ABUS_REG (0xB702E000)
+#define BASE_ADDR_RXDDM_NR_MML1_RXDDM_HALF_CK_ABUS_REG (0xB7030000)
+#define BASE_ADDR_RXDDM_NR_SLOT_RNTI (0xB7200000)
+#define BASE_ADDR_RXDDM_NR_RESERVED4 (0xB7201000)
+#define BASE_ADDR_RXDDM_NR_SYM (0xB7220000)
+#define BASE_ADDR_RXDDM_NR_RESERVED5 (0xB7228000)
+#define BASE_ADDR_RXDDM_NR_MASK_TYPE0 (0xB7240000)
+#define BASE_ADDR_RXDDM_NR_MASK_TYPE1 (0xB7260000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED_0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED_1 (0xB7960000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_EMI_CK_ABUS_REG (0xB7970000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_EMI_HALF_CK_ABUS_REG (0xB7980000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_SD_CK_ABUS_REG (0xB7990000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_SD_HALF_CK_ABUS_REG (0xB79A0000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_CK_ABUS_REG (0xB79B0000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_HALF_CK_ABUS_REG (0xB79C0000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_M_CK_ABUS_REG (0xB7C0C000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_M_HALF_CK_ABUS_REG (0xB7C0E000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_CK_ABUS_REG (0xB7C10000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_HALF_CK_ABUS_REG (0xB7C12000)
+#define BASE_ADDR_RXCPC_NR_RESERVED0 (0xB7C14000)
+#define BASE_ADDR_RXCPC_NR_RESERVED1 (0xB7C16000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CFG_SP (0xB7C20000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MD_DVFS_TOP_CONFIG (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_MIPI (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MAS_BUS_CONFIG (0xB8160000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_DFESYS_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MMW_TXDFE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MODEML1_AO_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MODEML1_AO_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_RESERVED1 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_RESERVED2 (0xB8B00000)
+#define BASE_ADDR_DFESYS_RESERVED3 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_RESERVED4 (0xB8B70000)
+#define BASE_ADDR_DFESYS_RESERVED5 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_DFE_COMDMA (0xB8E00000)
+#define BASE_ADDR_DFESYS_RESERVED6 (0xB8E10000)
+#define BASE_ADDR_DFESYS_RESERVED7 (0xB8E20000)
+#define BASE_ADDR_DFESYS_RESERVED8 (0xB8E30000)
+#define BASE_ADDR_DFESYS_RESERVED9 (0xB8E40000)
+#define BASE_ADDR_DFESYS_RESERVED10 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED11 (0xB8EA0000)
+#define BASE_ADDR_DFESYS_MAS_BUS_INTF (0xB8EB0000)
+#define BASE_ADDR_DFESYS_SLV_BUS_INTF (0xB8EC0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CSSYS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CSSYS_BUS_DIV2_CONFIG (0xB9838000)
+#define BASE_ADDR_CSSYS_MDAO_BUS_CONFIG (0xB983C000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_SCN_RPT (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_CS_NR_CM_CS_BUS_CONFIG (0xB9C60000)
+#define BASE_ADDR_CMCS_PAR_AO_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBDC00000)
+#define BASE_ADDR_CMCS_PAR_AO_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBDC10000)
+#define BASE_ADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG (0xBDC20000)
+#define BASE_ADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG (0xBDC30000)
+#define BASE_ADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG (0xBDC40000)
+#define BASE_ADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO (0xBDC50000)
+#define BASE_ADDR_CMCS_PAR_AO_MCORE_PAR_AO_REG (0xBDC50400)
+#define BASE_ADDR_CMCS_PAR_AO_U_VCORE_PAR_WRAP_SRAM_AO (0xBDC60000)
+#define BASE_ADDR_CMCS_PAR_AO_U_VCORE_PAR_AO_CR (0xBDC60400)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_0_SM_CONFIG (0xBDC60600)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_1_SM_CONFIG (0xBDC60680)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_2_SM_CONFIG (0xBDC60700)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_3_SM_CONFIG (0xBDC60780)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_4_SM_CONFIG (0xBDC60800)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_5_SM_CONFIG (0xBDC60880)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_6_SM_CONFIG (0xBDC60900)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_7_SM_CONFIG (0xBDC60980)
+#define BASE_ADDR_CMCS_PAR_AO_U_GRAM_MEM_CONFIG (0xBDC70000)
+#define BASE_ADDR_CMCS_PAR_AO_U_TX_NR_MEM_CONFIG (0xBDC80000)
+#define BASE_ADDR_CMCS_PAR_AO_U_CMCS_NR_MEM_CONFIG (0xBDC90000)
+#define BASE_ADDR_CMCS_PAR_AO_U_CMCS_PAR_AO_CONFIG_REG (0xBDCA0000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xBA008000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBA010000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xBA018000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA020000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA030000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_2 (0xBA040000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_3 (0xBA050000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_4 (0xBA060000)
+#define BASE_ADDR_TXSYS_NR_TXBSRP_GLB_APB_CONFIG (0xBA070000)
+#define BASE_ADDR_TXSYS_NR_TXBSRP_BIT_CONTROLLER (0xBA080000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA100000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG (0xBA101000)
+#define BASE_ADDR_TXSYS_NR_RESERVED0 (0xBA102000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_PAR_AO_CONFIG_REG (0xBA10C000)
+#define BASE_ADDR_TXSYS_NR_RESERVED1 (0xBA10D000)
+#define BASE_ADDR_TXSYS_NR_RESERVED2 (0xBA10E000)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_WRAP (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_0 (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_DVTCRC (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_1 (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_DVTCRC_1 (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_1 (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_2 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB_SSS (0xBA490000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB_SSS (0xBA4A0000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP_SSS (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT_SSS (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_SSS (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL_SSS (0xBA4E0000)
+#define BASE_ADDR_CM_NR_CM_NR_DVTCRC_SSS (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB_CSIRS (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB_CSIRS (0xBA510000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP_CSIRS (0xBA520000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT_CSIRS (0xBA530000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_CSIRS (0xBA540000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL_CSIRS (0xBA550000)
+#define BASE_ADDR_CM_NR_CM_NR_DVTCRC_CSIRS (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_3 (0xBA570000)
+#define BASE_ADDR_CM_NR_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xBA580000)
+#define BASE_ADDR_CM_NR_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xBA590000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED1 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTFC_RESERVED2 (0xBA870000)
+#define BASE_ADDR_RXTFC_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xBA880000)
+#define BASE_ADDR_RXTFC_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xBA890000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_3 (0xBAC70000)
+#define BASE_ADDR_RXTDB_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xBAC80000)
+#define BASE_ADDR_RXTDB_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xBAC90000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BUS_CONFIG (0xBB880000)
+#define BASE_ADDR_BIGRAM0_INR_SLV_BUS_CONFIG (0xBB890000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST_CONFIG (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_MAS_HALF_CK_ABUS_REG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_MAS_CK_ABUS_REG (0xBC990000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_SLV_HALF_CK_ABUS_REG (0xBC9A0000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_SLV_CK_ABUS_REG (0xBC9B0000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_LTE_CE_SC (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE_OC1 (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_OC2 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_PDSCH (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_PDCCH (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_EPDCCH (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_PBCH (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_SRAM_CTRL_AO (0xBD000000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MMW_DBB_CTRLACNT (0xBD001000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_GLOBAL_CON_AO (0xBD002000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_RESERVED0 (0xBD003000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xBD010000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RFAC (0xBD020000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CM_DATA_INTF (0xBD040000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_EVENTGEN (0xBD050000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED1 (0xBD060000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xBD080000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_LOG (0xBD090000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_COMDMA (0xBD0A0000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_CONTROLLER (0xBD0B0000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD (0xBD0B8000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_1 (0xBD0B8100)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_2 (0xBD0B8200)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED2 (0xBD0B8300)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_MBIST (0xBD0B9000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_GLOBAL_CON (0xBD0BA000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED3 (0xBD0BB000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_CM_COMM_REG (0xBD0F8000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG (0xBD0F8400)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_1 (0xBD0F8800)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_2 (0xBD0F8C00)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED4 (0xBD0F9000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_TOP (0xBD100000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_LOG (0xBD108000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_SCH (0xBD110000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xBD120000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED5 (0xBD130000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BPI (0xBD180000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_DIGRF_MIPI_M (0xBD190000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_TOP (0xBD200000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SCH (0xBD210000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI0 (0xBD218000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI1 (0xBD219000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI2 (0xBD21A000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI3 (0xBD21B000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI4 (0xBD21C000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI5 (0xBD21D000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI6 (0xBD21E000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI7 (0xBD21F000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xBD220000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED6 (0xBD230000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED7 (0xBD300000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_RESERVED0 (0xBD400000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_RESERVED1 (0xBD640000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TOP_CTRL (0xBD410000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_TXK (0xBD420000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_GLOBAL_CON (0xBD430000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BUS_CONFIG (0xBD440000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_MBIST_CONFIG_CAT (0xBD450000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TX_ACNT_TICK_GEN (0xBD460000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TQ (0xBD470000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR (0xBD480000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_1 (0xBD490000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_2 (0xBD4A0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_3 (0xBD4B0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_4 (0xBD4C0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_5 (0xBD4D0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_6 (0xBD4E0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_7 (0xBD4F0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D (0xBD500000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_1 (0xBD510000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_2 (0xBD520000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_3 (0xBD530000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_4 (0xBD540000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_5 (0xBD550000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_6 (0xBD560000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_7 (0xBD570000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_8 (0xBD580000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_9 (0xBD590000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_A (0xBD5A0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF (0xBD5B0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_1 (0xBD5C0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_2 (0xBD5D0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_3 (0xBD5E0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_ABB_MIXEDSYS (0xBD5F0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MRX_DATA_DUMP (0xBD600000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_PCC_BB (0xBD610000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_U_MMW_PCC_BB_TOP_1 (0xBD620000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_LOG (0xBD660000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE0_COMDMA (0xBD670000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE1_COMDMA (0xBD680000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MML1_MMW_TPC_468M_CK_ABUS_REG (0xBD690000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_TPC_M (0xBD700000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_TPC_M_1 (0xBD780000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER (0xBD800000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER_RESERVED0 (0xBD804000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_EVTGEN (0xBD808000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_SLPC (0xBD80C000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_RESERVED1 (0xBD810000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_PAR_WRAP_SRAM_AO (0xBD820000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_CONFIG_AO_REG (0xBD821000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX0 (0xBD828000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX1 (0xBD829000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX2 (0xBD82A000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX3 (0xBD82B000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX0 (0xBD82C000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX1 (0xBD82D000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_SYS (0xBD82E000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xBD830000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CONFIG_REG (0xBD840000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MBIST_CAT_MBIST_TOP_CFG (0xBD844000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xBD850000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_RXDFE_BB_NR_MMW_DM_SEL_WRAP (0xBD860000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CS_SEL_WRAP (0xBD870000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_CMSEL_MMW (0xBD880000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_CMIPG_MMW (0xBD888000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_LOG (0xBD890000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MRSG (0xBD8A0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE0_COMDMA (0xBD8C0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_DMA_DESCRT (0xBD8D0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_0 (0xBD8F0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_1 (0xBD8F8000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_0 (0xBD900000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_0 (0xBD920000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_1 (0xBD920200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_2 (0xBD920400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_3 (0xBD920600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_4 (0xBD920800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_5 (0xBD920A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_6 (0xBD920C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_7 (0xBD920E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_0 (0xBD922000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_1 (0xBD922200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_2 (0xBD922400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_3 (0xBD922600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_4 (0xBD922800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_5 (0xBD922A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_6 (0xBD922C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_7 (0xBD922E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ1 (0xBD924000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_WM (0xBD92A000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TOT_PATT (0xBD92E000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_2 (0xBD940000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_2 (0xBD960000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_1 (0xBD980000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_0 (0xBD9A0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_1 (0xBD9A0200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_2 (0xBD9A0400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_3 (0xBD9A0600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_4 (0xBD9A0800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_5 (0xBD9A0A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_6 (0xBD9A0C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_7 (0xBD9A0E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_0 (0xBD9A2000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_1 (0xBD9A2200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_2 (0xBD9A2400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_3 (0xBD9A2600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_4 (0xBD9A2800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_5 (0xBD9A2A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_6 (0xBD9A2C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_7 (0xBD9A2E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ1 (0xBD9A4000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_WM (0xBD9AA000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TOT_PATT (0xBD9AE000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_MBIST_CONFIG (0xBD9C0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_GLBCON (0xBD9F0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_SET (0xBDA00000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_HEADER (0xBDA04000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_STATUS (0xBDA08000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_P_REG (0xBDA10000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_L_REG (0xBDA20000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_IMM_REG (0xBDA30000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_P_REG (0xBDA40000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_L_REG (0xBDA50000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CS_AGC (0xBDA60000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_468 (0xBDA70000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_52 (0xBDA71000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_0 (0xBDA71800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_1 (0xBDA71C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC (0xBDA80000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_1 (0xBDA84000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_2 (0xBDA88000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_3 (0xBDA90000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_4 (0xBDAA0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_5 (0xBDAB0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_6 (0xBDAC0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_7 (0xBDAD0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_8 (0xBDAE0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_468 (0xBDAF0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_52 (0xBDAF1000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_0 (0xBDAF1800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_1 (0xBDAF1C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xBDAFF000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_DM (0xBDB00000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD0_PM (0xBDBA0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD1_PM (0xBDBB0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_COREDBG (0xBDBD0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_GC_PM (0xBDBE0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE1_COMDMA (0xBDBFE000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ADC_TEST_ARBITOR (0xBDBFF000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from MMW_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 BASE_MADDR_MDPERI_VU_SM_CONGIF_0
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 BASE_NADDR_MDPERI_VU_SM_CONGIF_0
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 BASE_ADDR_MDPERI_VU_SM_CONGIF_0
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 BASE_MADDR_MDPERI_VU_SM_CONGIF_1
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 BASE_NADDR_MDPERI_VU_SM_CONGIF_1
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 BASE_ADDR_MDPERI_VU_SM_CONGIF_1
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG BASE_MADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG BASE_NADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG BASE_ADDR_MDPERI_MDRXAO_CONFIG
+//#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO
+//#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO
+//#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG BASE_MADDR_MDPERI_BRP_SRAM_AO
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG BASE_NADDR_MDPERI_BRP_SRAM_AO
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG BASE_ADDR_MDPERI_BRP_SRAM_AO
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_NADDR_MML2_METADATA_MA
+
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MDPERI_MDRXAO_CONFIG
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+////#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+////#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+////#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MDPERI_MDRXSYS_SRAM_AO
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MDPERI_MDRXSYS_SRAM_AO
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MDPERI_MDRXSYS_SRAM_AO
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+////#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+//#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+////#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+//#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+////#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+//#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MDPERI_MDRXSYS_SRAM_AO
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+//#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MDPERI_MDRXSYS_SRAM_AO
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_ADDR_MDPERI_MDRXSYS_SRAM_AO
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __BASE_REG_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_FPGA.h b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_FPGA.h
new file mode 100644
index 0000000..ba933db
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_FPGA.h
@@ -0,0 +1,5266 @@
+#ifndef __REG_BASE_MERCURY_FPGA_H__
+#define __REG_BASE_MERCURY_FPGA_H__
+
+////////////////////////////////////////////////////////////////
+//
+// BEG-- Generated from MMW_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+// (3): Lookup table
+// (4): 95 example
+#define BASE_MADDR_RXDFESYS_BUS_CONFIG (0xA7000000)
+#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DMA (0xA7020000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC (0xA7080000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC (0xA7090000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS (0xA70A0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC (0xA70B0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FC (0xA70C0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_ATIMER (0xA70D0000)
+#define BASE_MADDR_RXDFESYS_PCC (0xA70E0000)
+#define BASE_MADDR_RXDFESYS_MBIST_CONFIG (0xA70F0000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ (0xA7100000)
+#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+#define BASE_MADDR_RXDFESYS_GC_DBG (0xA7130000)
+#define BASE_MADDR_RXDFESYS_RXDFE_DUMP (0xA7140000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xA7400000)
+#define BASE_MADDR_RXDFESYS_RXDFE_MS_SRAM (0xA7420000)
+#define BASE_MADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xA7430000)
+#define BASE_MADDR_RXDFESYS_RXDFE_CQ_SRAM (0xA7440000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xA7450000)
+#define BASE_MADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xA7460000)
+// (5): MAP_mdperi_ao
+#define BASE_MADDR_MDPERI_MDCFGCTL (0xA0000000)
+#define BASE_MADDR_MDPERI_MDUART0 (0xA0010000)
+#define BASE_MADDR_MDPERI_MDGDMA (0xA0020000)
+#define BASE_MADDR_MDPERI_MDGPTM (0xA0030000)
+#define BASE_MADDR_MDPERI_USIM1 (0xA0040000)
+#define BASE_MADDR_MDPERI_USIM2 (0xA0050000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MISC_REG (0xA0060000)
+#define BASE_MADDR_MDPERI_MDCIRQ (0xA0070000)
+#define BASE_MADDR_MDPERI_MDL1_MODEM_TOPSM_PROTECT (0xA0080000)
+#define BASE_MADDR_MDPERI_COMDMA (0xA0090000)
+#define BASE_MADDR_MDPERI_PTP_THERM_CTRL (0xA00C0000)
+#define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+#define BASE_MADDR_MDPERI_MD_OSTIMER (0xA00E0000)
+#define BASE_MADDR_MDPERI_MDRGU (0xA00F0000)
+#define BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xA0100000)
+#define BASE_MADDR_MDPERI_MD_EINT (0xA0110000)
+#define BASE_MADDR_MDPERI_LOW_PWR_DBG_MON (0xA0120000)
+#define BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MDPERI_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MDPERI_MD_CLKSW (0xA0150000)
+#define BASE_MADDR_MDPERI_MDPAR_DBGMON (0xA0160000)
+#define BASE_MADDR_MDPERI_MD_PMS_CONFIG (0xA0170000)
+#define BASE_MADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xA0180000)
+#define BASE_MADDR_MDPERI_MDRXSYS_SRAM_AO (0xA0190000)
+#define BASE_MADDR_MDPERI_VU_SM_CONGIF_0 (0xA0191000)
+#define BASE_MADDR_MDPERI_VU_SM_CONGIF_1 (0xA0192000)
+#define BASE_MADDR_MDPERI_MDRXAO_CONFIG (0xA0193000)
+#define BASE_MADDR_MDPERI_RESERVED0 (0xA0194000)
+#define BASE_MADDR_MDPERI_BRP_SRAM_AO (0xA01A0000)
+#define BASE_MADDR_MDPERI_NRL2_SRAM_AO (0xA01B0000)
+#define BASE_MADDR_MDPERI_CLK_CTRL (0xA01C0000)
+#define BASE_MADDR_MDPERI_MDSYS_SRAM_AO (0xA01D0000)
+#define BASE_MADDR_MDPERI_MDDBGSYS (0xA0600000)
+// (6): MAP_mdinfra
+#define BASE_MADDR_MDINFRA_I2C (0xA0400000)
+#define BASE_MADDR_MDINFRA_SOE (0xA0410000)
+#define BASE_MADDR_MDINFRA_BUSMON (0xA0420000)
+#define BASE_MADDR_MDINFRA_MDUART1 (0xA0430000)
+#define BASE_MADDR_MDINFRA_BUS2X_REG (0xA0440000)
+#define BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xA0450000)
+#define BASE_MADDR_MDINFRA_SHAOLIN_SEMAPHORE (0xA0460000)
+#define BASE_MADDR_MDINFRA_MDM (0xA0490000)
+#define BASE_MADDR_MDINFRA_SMI_CONFIG (0xA04A0000)
+#define BASE_MADDR_MDINFRA_BUS4X_REG (0xA04B0000)
+#define BASE_MADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xA04C0000)
+#define BASE_MADDR_MDINFRA_LOG (0xA04F0000)
+#define BASE_MADDR_MDINFRA_HW_LOG (0xA0500000)
+#define BASE_MADDR_MDINFRA_ELM (0xA0520000)
+#define BASE_MADDR_MDINFRA_TRACE (0xA0540000)
+#define BASE_MADDR_MDINFRA_TRACE_NR_TOP_1 (0xA0550000)
+#define BASE_MADDR_MDINFRA_PPPHA (0xA0560000)
+#define BASE_MADDR_MDINFRA_SDF (0xA0570000)
+// (7): MAP_mdcoresys
+#define BASE_ADDR_MML2_MCU_MMU (0xE0000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_RESERVED0 (0x9F000000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM (0x9FC00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV (0x9FE00000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_SHAOLIN_BTSLV (0x9FF00000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_AO_MISC_CTRL (0xA0260000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_SRAM_AO (0xA0270000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_MEM_DELSEL_CFG (0xA0280000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_MEM_DELSEL_CFG (0xA0281000)
+#define BASE_MADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE1_MEM_DELSEL_CFG (0xA0282000)
+#define BASE_MADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE2_MEM_DELSEL_CFG (0xA0283000)
+#define BASE_MADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE3_MEM_DELSEL_CFG (0xA0284000)
+#define BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xA0290000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xA02A0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xA02A1000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xA02A2000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xA02A3000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xA02A4000)
+#define BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xA02B0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_CONFIG (0xA02C0000)
+#define BASE_MADDR_MDMCU_SHAOLIN__BUSMPU_INFRA (0xA02D0000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xA0300000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xA0301000)
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xA0302000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUSMON (0xA0310000)
+#define BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xA0320000)
+#define BASE_MADDR_MDCORESYS_MDMCU_COREBUS_INTF_CFG (0xA0330000)
+#define BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xA0340000)
+#define BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI (0xA0350000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG (0xA0360000)
+#define BASE_MADDR_MDCORESYS_MDMCU_QOS_CTRL (0xA0380000)
+#define BASE_MADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xA0390000)
+#define BASE_MADDR_MDCORESYS_IA_MACRO_DELSEL_ADR_IF (0xA03B0000)
+#define BASE_MADDR_MDCORESYS_MDCORESYS_MBIST_MDCORE_FOR_CFG_DELSEL_CFG_WRAP (0xA03B1000)
+// (8): MAP_usip
+#define BASE_MADDR_USIP_USIP0_ITCM (0xA0800000)
+#define BASE_MADDR_USIP_USIP0_DTCM (0xA0840000)
+#define BASE_MADDR_USIP_USIP0_DEBUG (0xA0880000)
+#define BASE_MADDR_USIP_USIP1_ITCM (0xA0900000)
+#define BASE_MADDR_USIP_USIP1_DTCM (0xA0940000)
+#define BASE_MADDR_USIP_USIP1_DEBUG (0xA0980000)
+#define BASE_MADDR_USIP_SLOW_TCM (0xA0C00000)
+#define BASE_MADDR_USIP_MBIST_CONFIG (0xA0D00000)
+#define BASE_MADDR_USIP_MBIST_REPAIR_TOP_CFG_WRAP (0xA0D10000)
+#define BASE_MADDR_USIP_MBIST_DELSEL_TOP_CFG_WRAP (0xA0D20000)
+#define BASE_MADDR_USIP_USIPCORE_BUS_CONFIG (0xA0D30000)
+#define BASE_MADDR_USIP_CONFG (0xA0E00000)
+#define BASE_MADDR_USIP_DSPLOG (0xA0E20000)
+#define BASE_MADDR_USIP_CROSS_CORE_CTRL (0xA0E30000)
+#define BASE_MADDR_USIP_AFE (0xA0E40000)
+#define BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xA0E50000)
+#define BASE_MADDR_USIP_SEMAPHORE (0xA0E60000)
+// (9): mml2
+#define BASE_MADDR_NRL2_NRL2_DL_UPP (0xA2000000)
+#define BASE_MADDR_NRL2_NRL2_BUS_SMI (0xA2001000)
+#define BASE_MADDR_NRL2_VRB_MNG (0xA2002000)
+#define BASE_MADDR_NRL2_NRL2_MMU (0xA2003000)
+#define BASE_MADDR_NRL2_NRL2_SRAM_WRAP (0xA2004000)
+#define BASE_MADDR_NRL2_NRL2_TOP_CFG (0xA2005000)
+#define BASE_MADDR_NRL2_NRL2_LHIF (0xA2006000)
+#define BASE_MADDR_NRL2_NRL2_IPF_UL (0xA2007000)
+#define BASE_MADDR_NRL2_NRL2_IPF_DL (0xA2008000)
+#define BASE_MADDR_NRL2_NRL2_IPF_HPCNAT (0xA2009000)
+#define BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH (0xA200A000)
+#define BASE_MADDR_NRL2_NRL2_PPHY (0xA200B000)
+#define BASE_MADDR_NRL2_ROHC (0xA200C000)
+#define BASE_MADDR_NRL2_NRL2_CPHR_NR (0xA200D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xA200E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xA200F000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP (0xA2010000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_RDMA (0xA2011000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xA2012000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xA2013000)
+#define BASE_MADDR_NRL2_NRL2_UL_CIPHER_CONFIG (0xA2014000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX (0xA2016000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF (0xA2017000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG (0xA2018000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG (0xA2018000)
+#define BASE_MADDR_NRL2_DLSYS_COPRO_ARB (0xA2019000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_NR (0xA201A000)
+#define BASE_MADDR_NRL2_NRL2_IPF_LOG (0xA201D000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_RETX (0xA201E000)
+#define BASE_MADDR_NRL2_NRL2_QP_UL_LHIF (0xA201F000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_QP (0xA2020000)
+#define BASE_MADDR_NRL2_DLSYS_4GPL_RDMA (0xA2021000)
+#define BASE_MADDR_NRL2_GEN95_QP (0xA2022000)
+#define BASE_MADDR_NRL2_GEN95_RDMA (0xA2023000)
+#define BASE_MADDR_NRL2_GEN95_CPHR (0xA2024000)
+#define BASE_MADDR_NRL2_LTEDL_LMAC (0xA2025000)
+#define BASE_MADDR_NRL2_LTEDL_HARQ (0xA2026000)
+#define BASE_MADDR_NRL2_GEN95_BYC (0xA2027000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RULE (0xA2028000)
+#define BASE_MADDR_NRL2_DLSYS_5GPL_QP (0xA2029000)
+#define BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL (0xA202A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP (0xA202B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xA202C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xA202D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xA202E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX (0xA2031000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF (0xA2032000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_GEN95 (0xA2033000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC (0xA2035000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_1 (0xA2036000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_2 (0xA2037000)
+#define BASE_MADDR_NRL2_NRL2_METADATA_MNG_SRAM (0xA2038000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_TB_MAP_4 (0xA2039000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_ST (0xA203A000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_0 (0xA203B000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_1 (0xA203C000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_2 (0xA203D000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_3 (0xA203E000)
+#define BASE_MADDR_NRL2_NRL2_DL_UPP_REASB_WB_4 (0xA203F000)
+#define BASE_MADDR_NRL2_NRL2_DL_META_AGG (0xA2040000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC2 (0xA2041000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC3 (0xA2042000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC4 (0xA2043000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC5 (0xA2044000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC6 (0xA2045000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC7 (0xA2046000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC8 (0xA2047000)
+#define BASE_MADDR_NRL2_NRL2_RDMA_UL_PPRO (0xA2048000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC2 (0xA2049000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC3 (0xA204A000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC4 (0xA204B000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC5 (0xA204C000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC6 (0xA204D000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC7 (0xA204E000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC8 (0xA204F000)
+#define BASE_MADDR_NRL2_NRL2_WDMA_UL_PPRO (0xA2050000)
+#define BASE_MADDR_NRL2_NRL2_BUS_CFG (0xA2051000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_PPRO_QP (0xA2052000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_0 (0xA2053000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_1 (0xA2054000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_2 (0xA2055000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_3 (0xA2056000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_4 (0xA2057000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_5 (0xA2058000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_6 (0xA2059000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_7 (0xA205A000)
+#define BASE_MADDR_NRL2_NRL2_NRUL_COTF_QP_8 (0xA205B000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC0 (0xA205C000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC1 (0xA205D000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC2 (0xA205E000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC3 (0xA205F000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC4 (0xA2060000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC5 (0xA2061000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC6 (0xA2062000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC7 (0xA2063000)
+#define BASE_MADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC8 (0xA2064000)
+// (10): MAP_MCORE_Program_private
+#define BASE_ADDR_MCORE_L1ITCM (0x00000000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0 (0x01400000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1 (0x01440000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2 (0x01480000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3 (0x014C0000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0_MIRROR1 (0x01500000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1_MIRROR1 (0x01540000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2_MIRROR1 (0x01580000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3_MIRROR1 (0x015C0000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0_MIRROR2 (0x01600000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1_MIRROR2 (0x01640000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2_MIRROR2 (0x01680000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3_MIRROR2 (0x016C0000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK0_MIRROR3 (0x01700000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK1_MIRROR3 (0x01740000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK2_MIRROR3 (0x01780000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM_TOP_BANK3_MIRROR3 (0x017C0000)
+// (11): MAP_MCORE_Data_private
+#define BASE_ADDR_MCORE_SONIC (0x00040000)
+#define BASE_ADDR_MCORE_L0I_CACHE (0x00050000)
+#define BASE_ADDR_MCORE_L0D_CACHE (0x00051000)
+#define BASE_ADDR_MCORE_TIMER (0x00052000)
+#define BASE_ADDR_MCORE_EXCTRL (0x00053000)
+#define BASE_ADDR_MCORE_PC_MONITOR (0x00054000)
+#define BASE_ADDR_MCORE_PROFILING_UNIT (0x00055000)
+#define BASE_ADDR_MCORE_MBIST_CONFIG (0x00056000)
+#define BASE_ADDR_MCORE_MCORE_CRIT_DBUS_REG (0x00057000)
+#define BASE_ADDR_MCORE_L1I_CACHE (0x00100000)
+#define BASE_ADDR_MCORE_L1D_CACHE (0x00101000)
+#define BASE_ADDR_MCORE_CLKCTRL (0x00102000)
+#define BASE_ADDR_MCORE_SHARED_EXCTRL (0x00103000)
+#define BASE_ADDR_MCORE_L1_PROFILING_UNIT (0x00104000)
+#define BASE_ADDR_MCORE_A2D_32 (0x00105000)
+#define BASE_ADDR_MCORE_A2D_128 (0x00106000)
+#define BASE_ADDR_MCORE_D2D (0x00107000)
+#define BASE_ADDR_MCORE_D2A (0x00108000)
+#define BASE_ADDR_MCORE_MCORE_TOP_DBUS_REG (0x00109000)
+#define BASE_ADDR_MCORE_MML1_DSPISRD (0x00180000)
+#define BASE_ADDR_MCORE_MML1_DSPDBGC0 (0x00181000)
+#define BASE_ADDR_MCORE_MML1_DSPDBGC1 (0x00182000)
+#define BASE_ADDR_MCORE_MML1_DSPCTIWRAP (0x00183000)
+#define BASE_ADDR_MCORE_THREAD0_SONIC (0x00200000)
+#define BASE_ADDR_MCORE_THREAD0_L0I_CACHE (0x00210000)
+#define BASE_ADDR_MCORE_THREAD0_L0D_CACHE (0x00211000)
+#define BASE_ADDR_MCORE_THREAD0_TIMER (0x00212000)
+#define BASE_ADDR_MCORE_THREAD0_EXCTRL (0x00213000)
+#define BASE_ADDR_MCORE_THREAD0_PC_MONITOR (0x00214000)
+#define BASE_ADDR_MCORE_THREAD0_PROFILING_UNIT (0x00215000)
+#define BASE_ADDR_MCORE_THREAD0_MBIST_CONFIG (0x00216000)
+#define BASE_ADDR_MCORE_THREAD0_DBUS_REG (0x00217000)
+#define BASE_ADDR_MCORE_THREAD1_SONIC (0x00220000)
+#define BASE_ADDR_MCORE_THREAD1_L0I_CACHE (0x00230000)
+#define BASE_ADDR_MCORE_THREAD1_L0D_CACHE (0x00231000)
+#define BASE_ADDR_MCORE_THREAD1_TIMER (0x00232000)
+#define BASE_ADDR_MCORE_THREAD1_EXCTRL (0x00233000)
+#define BASE_ADDR_MCORE_THREAD1_PC_MONITOR (0x00234000)
+#define BASE_ADDR_MCORE_THREAD1_PROFILING_UNIT (0x00235000)
+#define BASE_ADDR_MCORE_THREAD1_MBIST_CONFIG (0x00236000)
+#define BASE_ADDR_MCORE_THREAD1_DBUS_REG (0x00237000)
+#define BASE_ADDR_MCORE_THREAD2_SONIC (0x00240000)
+#define BASE_ADDR_MCORE_THREAD2_L0I_CACHE (0x00250000)
+#define BASE_ADDR_MCORE_THREAD2_L0D_CACHE (0x00251000)
+#define BASE_ADDR_MCORE_THREAD2_TIMER (0x00252000)
+#define BASE_ADDR_MCORE_THREAD2_EXCTRL (0x00253000)
+#define BASE_ADDR_MCORE_THREAD2_PC_MONITOR (0x00254000)
+#define BASE_ADDR_MCORE_THREAD2_PROFILING_UNIT (0x00255000)
+#define BASE_ADDR_MCORE_THREAD2_MBIST_CONFIG (0x00256000)
+#define BASE_ADDR_MCORE_THREAD2_DBUS_REG (0x00257000)
+#define BASE_ADDR_MCORE_THREAD3_SONIC (0x00260000)
+#define BASE_ADDR_MCORE_THREAD3_L0I_CACHE (0x00270000)
+#define BASE_ADDR_MCORE_THREAD3_L0D_CACHE (0x00271000)
+#define BASE_ADDR_MCORE_THREAD3_TIMER (0x00272000)
+#define BASE_ADDR_MCORE_THREAD3_EXCTRL (0x00273000)
+#define BASE_ADDR_MCORE_THREAD3_PC_MONITOR (0x00274000)
+#define BASE_ADDR_MCORE_THREAD3_PROFILING_UNIT (0x00275000)
+#define BASE_ADDR_MCORE_THREAD3_MBIST_CONFIG (0x00276000)
+#define BASE_ADDR_MCORE_THREAD3_DBUS_REG (0x00277000)
+#define BASE_ADDR_MCORE_THREAD4_SONIC (0x00280000)
+#define BASE_ADDR_MCORE_THREAD4_L0I_CACHE (0x00290000)
+#define BASE_ADDR_MCORE_THREAD4_L0D_CACHE (0x00291000)
+#define BASE_ADDR_MCORE_THREAD4_TIMER (0x00292000)
+#define BASE_ADDR_MCORE_THREAD4_EXCTRL (0x00293000)
+#define BASE_ADDR_MCORE_THREAD4_PC_MONITOR (0x00294000)
+#define BASE_ADDR_MCORE_THREAD4_PROFILING_UNIT (0x00295000)
+#define BASE_ADDR_MCORE_THREAD4_MBIST_CONFIG (0x00296000)
+#define BASE_ADDR_MCORE_THREAD4_DBUS_REG (0x00297000)
+#define BASE_ADDR_MCORE_THREAD5_SONIC (0x002A0000)
+#define BASE_ADDR_MCORE_THREAD5_L0I_CACHE (0x002B0000)
+#define BASE_ADDR_MCORE_THREAD5_L0D_CACHE (0x002B1000)
+#define BASE_ADDR_MCORE_THREAD5_TIMER (0x002B2000)
+#define BASE_ADDR_MCORE_THREAD5_EXCTRL (0x002B3000)
+#define BASE_ADDR_MCORE_THREAD5_PC_MONITOR (0x002B4000)
+#define BASE_ADDR_MCORE_THREAD5_PROFILING_UNIT (0x002B5000)
+#define BASE_ADDR_MCORE_THREAD5_MBIST_CONFIG (0x002B6000)
+#define BASE_ADDR_MCORE_THREAD5_DBUS_REG (0x002B7000)
+#define BASE_ADDR_MCORE_THREAD6_SONIC (0x002C0000)
+#define BASE_ADDR_MCORE_THREAD6_L0I_CACHE (0x002D0000)
+#define BASE_ADDR_MCORE_THREAD6_L0D_CACHE (0x002D1000)
+#define BASE_ADDR_MCORE_THREAD6_TIMER (0x002D2000)
+#define BASE_ADDR_MCORE_THREAD6_EXCTRL (0x002D3000)
+#define BASE_ADDR_MCORE_THREAD6_PC_MONITOR (0x002D4000)
+#define BASE_ADDR_MCORE_THREAD6_PROFILING_UNIT (0x002D5000)
+#define BASE_ADDR_MCORE_THREAD6_MBIST_CONFIG (0x002D6000)
+#define BASE_ADDR_MCORE_THREAD6_DBUS_REG (0x002D7000)
+#define BASE_ADDR_MCORE_THREAD7_SONIC (0x002E0000)
+#define BASE_ADDR_MCORE_THREAD7_L0I_CACHE (0x002F0000)
+#define BASE_ADDR_MCORE_THREAD7_L0D_CACHE (0x002F1000)
+#define BASE_ADDR_MCORE_THREAD7_TIMER (0x002F2000)
+#define BASE_ADDR_MCORE_THREAD7_EXCTRL (0x002F3000)
+#define BASE_ADDR_MCORE_THREAD7_PC_MONITOR (0x002F4000)
+#define BASE_ADDR_MCORE_THREAD7_PROFILING_UNIT (0x002F5000)
+#define BASE_ADDR_MCORE_THREAD7_MBIST_CONFIG (0x002F6000)
+#define BASE_ADDR_MCORE_THREAD7_DBUS_REG (0x002F7000)
+#define BASE_ADDR_MCORE_THREAD8_SONIC (0x00300000)
+#define BASE_ADDR_MCORE_THREAD8_L0I_CACHE (0x00310000)
+#define BASE_ADDR_MCORE_THREAD8_L0D_CACHE (0x00311000)
+#define BASE_ADDR_MCORE_THREAD8_TIMER (0x00312000)
+#define BASE_ADDR_MCORE_THREAD8_EXCTRL (0x00313000)
+#define BASE_ADDR_MCORE_THREAD8_PC_MONITOR (0x00314000)
+#define BASE_ADDR_MCORE_THREAD8_PROFILING_UNIT (0x00315000)
+#define BASE_ADDR_MCORE_THREAD8_MBIST_CONFIG (0x00316000)
+#define BASE_ADDR_MCORE_THREAD8_DBUS_REG (0x00317000)
+#define BASE_ADDR_MCORE_THREAD9_SONIC (0x00320000)
+#define BASE_ADDR_MCORE_THREAD9_L0I_CACHE (0x00330000)
+#define BASE_ADDR_MCORE_THREAD9_L0D_CACHE (0x00331000)
+#define BASE_ADDR_MCORE_THREAD9_TIMER (0x00332000)
+#define BASE_ADDR_MCORE_THREAD9_EXCTRL (0x00333000)
+#define BASE_ADDR_MCORE_THREAD9_PC_MONITOR (0x00334000)
+#define BASE_ADDR_MCORE_THREAD9_PROFILING_UNIT (0x00335000)
+#define BASE_ADDR_MCORE_THREAD9_MBIST_CONFIG (0x00336000)
+#define BASE_ADDR_MCORE_THREAD9_DBUS_REG (0x00337000)
+#define BASE_ADDR_MCORE_THREAD10_SONIC (0x00340000)
+#define BASE_ADDR_MCORE_THREAD10_L0I_CACHE (0x00350000)
+#define BASE_ADDR_MCORE_THREAD10_L0D_CACHE (0x00351000)
+#define BASE_ADDR_MCORE_THREAD10_TIMER (0x00352000)
+#define BASE_ADDR_MCORE_THREAD10_EXCTRL (0x00353000)
+#define BASE_ADDR_MCORE_THREAD10_PC_MONITOR (0x00354000)
+#define BASE_ADDR_MCORE_THREAD10_PROFILING_UNIT (0x00355000)
+#define BASE_ADDR_MCORE_THREAD10_MBIST_CONFIG (0x00356000)
+#define BASE_ADDR_MCORE_THREAD10_DBUS_REG (0x00357000)
+#define BASE_ADDR_MCORE_THREAD11_SONIC (0x00360000)
+#define BASE_ADDR_MCORE_THREAD11_L0I_CACHE (0x00370000)
+#define BASE_ADDR_MCORE_THREAD11_L0D_CACHE (0x00371000)
+#define BASE_ADDR_MCORE_THREAD11_TIMER (0x00372000)
+#define BASE_ADDR_MCORE_THREAD11_EXCTRL (0x00373000)
+#define BASE_ADDR_MCORE_THREAD11_PC_MONITOR (0x00374000)
+#define BASE_ADDR_MCORE_THREAD11_PROFILING_UNIT (0x00375000)
+#define BASE_ADDR_MCORE_THREAD11_MBIST_CONFIG (0x00376000)
+#define BASE_ADDR_MCORE_THREAD11_DBUS_REG (0x00377000)
+#define BASE_ADDR_MCORE_THREAD12_SONIC (0x00380000)
+#define BASE_ADDR_MCORE_THREAD12_L0I_CACHE (0x00390000)
+#define BASE_ADDR_MCORE_THREAD12_L0D_CACHE (0x00391000)
+#define BASE_ADDR_MCORE_THREAD12_TIMER (0x00392000)
+#define BASE_ADDR_MCORE_THREAD12_EXCTRL (0x00393000)
+#define BASE_ADDR_MCORE_THREAD12_PC_MONITOR (0x00394000)
+#define BASE_ADDR_MCORE_THREAD12_PROFILING_UNIT (0x00395000)
+#define BASE_ADDR_MCORE_THREAD12_MBIST_CONFIG (0x00396000)
+#define BASE_ADDR_MCORE_THREAD12_DBUS_REG (0x00397000)
+#define BASE_ADDR_MCORE_THREAD13_SONIC (0x003A0000)
+#define BASE_ADDR_MCORE_THREAD13_L0I_CACHE (0x003B0000)
+#define BASE_ADDR_MCORE_THREAD13_L0D_CACHE (0x003B1000)
+#define BASE_ADDR_MCORE_THREAD13_TIMER (0x003B2000)
+#define BASE_ADDR_MCORE_THREAD13_EXCTRL (0x003B3000)
+#define BASE_ADDR_MCORE_THREAD13_PC_MONITOR (0x003B4000)
+#define BASE_ADDR_MCORE_THREAD13_PROFILING_UNIT (0x003B5000)
+#define BASE_ADDR_MCORE_THREAD13_MBIST_CONFIG (0x003B6000)
+#define BASE_ADDR_MCORE_THREAD13_DBUS_REG (0x003B7000)
+#define BASE_ADDR_MCORE_THREAD14_SONIC (0x003C0000)
+#define BASE_ADDR_MCORE_THREAD14_L0I_CACHE (0x003D0000)
+#define BASE_ADDR_MCORE_THREAD14_L0D_CACHE (0x003D1000)
+#define BASE_ADDR_MCORE_THREAD14_TIMER (0x003D2000)
+#define BASE_ADDR_MCORE_THREAD14_EXCTRL (0x003D3000)
+#define BASE_ADDR_MCORE_THREAD14_PC_MONITOR (0x003D4000)
+#define BASE_ADDR_MCORE_THREAD14_PROFILING_UNIT (0x003D5000)
+#define BASE_ADDR_MCORE_THREAD14_MBIST_CONFIG (0x003D6000)
+#define BASE_ADDR_MCORE_THREAD14_DBUS_REG (0x003D7000)
+#define BASE_ADDR_MCORE_THREAD15_SONIC (0x003E0000)
+#define BASE_ADDR_MCORE_THREAD15_L0I_CACHE (0x003F0000)
+#define BASE_ADDR_MCORE_THREAD15_L0D_CACHE (0x003F1000)
+#define BASE_ADDR_MCORE_THREAD15_TIMER (0x003F2000)
+#define BASE_ADDR_MCORE_THREAD15_EXCTRL (0x003F3000)
+#define BASE_ADDR_MCORE_THREAD15_PC_MONITOR (0x003F4000)
+#define BASE_ADDR_MCORE_THREAD15_PROFILING_UNIT (0x003F5000)
+#define BASE_ADDR_MCORE_THREAD15_MBIST_CONFIG (0x003F6000)
+#define BASE_ADDR_MCORE_THREAD15_DBUS_REG (0x003F7000)
+#define BASE_ADDR_MCORE_MML1_DSPM2VSCHEDULER (0x00800000)
+#define BASE_ADDR_MCORE_MML1_MPERI_DSPCK_ABUS_REG (0x00801000)
+#define BASE_ADDR_MCORE_MPERI_DBUS3 (0x00802000)
+#define BASE_ADDR_MCORE_DSPM2DDMSCHEDULER (0x00804000)
+#define BASE_ADDR_MCORE_MML1_DSPCSIF (0x00810000)
+#define BASE_ADDR_MCORE_MML1_DSPMCORELOG (0x00811000)
+#define BASE_ADDR_MCORE_MML1_MPERI_DSPCORECK_ABUS_REG (0x00813000)
+#define BASE_ADDR_MCORE_MPERI_DBUS1 (0x00814000)
+#define BASE_ADDR_MCORE_DBUS_AXI2DBUS (0x00816000)
+#define BASE_ADDR_MCORE_MML1_DSPBUSRECORDER (0x00817000)
+#define BASE_ADDR_MCORE_MML1_DSPUSTIMER (0x00818000)
+#define BASE_ADDR_MCORE_MCORE_PROFILING_UNIT (0x00819000)
+#define BASE_ADDR_MCORE_MPPT (0x0081A000)
+#define BASE_ADDR_MCORE_MML1_DSPBTDMA (0x00821000)
+#define BASE_ADDR_MCORE_MML1_DSPSWLA (0x00822000)
+#define BASE_ADDR_MCORE_MPERI_DBUS2 (0x00823000)
+#define BASE_ADDR_MCORE_GLBCON (0x00830000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_DBGMON_WRAP (0x00831000)
+#define BASE_ADDR_MCORE_MML1_MPERI_PERICK_ABUS_REG (0x00832000)
+#define BASE_ADDR_MCORE_ABUSMON (0x00833000)
+#define BASE_ADDR_MCORE_MML1_DSP_COMDMA (0x00834000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_MBIST_CONFIG (0x00840000)
+#define BASE_ADDR_MCORE_MML1_DSP_MSPDBGMEN (0x00F00000)
+#define BASE_ADDR_MCORE_L1DTCM (0x01000000)
+#define BASE_ADDR_MCORE_L1DTCM_MIRROR1 (0x01100000)
+#define BASE_ADDR_MCORE_MML1_DSPL2TCM (0x01400000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1 (0x01440000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2 (0x01480000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3 (0x014C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM (0x014FC000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM0 (0x01500000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1_1 (0x01540000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2_1 (0x01580000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3_1 (0x015C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM_MIRROR1 (0x015FC000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM0_1 (0x01600000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1_2 (0x01640000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2_2 (0x01680000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3_2 (0x016C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM_MIRROR2 (0x016FC000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM0_2 (0x01700000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM1_3 (0x01740000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM2_3 (0x01780000)
+#define BASE_ADDR_MCORE_MSYS_D_L2TCM3_3 (0x017C0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_CPC_MEM_MIRROR3 (0x017FC000)
+// (12): MAP_MCORE_global
+#define BASE_MADDR_MCORE_MSYS_DSPM2VSCHEDULER (0xA4000000)
+#define BASE_MADDR_MCORE_MPERI_DSPCK_ABUS_REG (0xA4001000)
+#define BASE_MADDR_MCORE_MPERI_DBUS3_APB2DBUSCR_INST (0xA4002000)
+#define BASE_MADDR_MCORE_MML1_DSPM2DDMSCHEDULER (0xA4004000)
+#define BASE_MADDR_MCORE_MSYS_DSPCSIF (0xA4010000)
+#define BASE_MADDR_MCORE_MSYS_DSPMCORELOG (0xA4011000)
+#define BASE_MADDR_MCORE_MML1_DSPCBSCHEDULER (0xA4012000)
+#define BASE_MADDR_MCORE_MPERI_DSPCORECK_ABUS_REG (0xA4013000)
+#define BASE_MADDR_MCORE_MPERI_DBUS1_APB2DBUSCR_INST (0xA4014000)
+#define BASE_MADDR_MCORE_MPERI_A2D (0xA4016000)
+#define BASE_MADDR_MCORE_MPERI_DBUSRECORDER (0xA4017000)
+#define BASE_MADDR_MCORE_MSYS_DSPUSTIMER (0xA4018000)
+#define BASE_MADDR_MCORE_MSYS_PROFILING (0xA4019000)
+#define BASE_MADDR_MCORE_MML1_DSPMPPT (0xA401A000)
+#define BASE_MADDR_MCORE_MSYS_DSPBTDMA (0xA4021000)
+#define BASE_MADDR_MCORE_MSYS_DSPSWLA (0xA4022000)
+#define BASE_MADDR_MCORE_MPERI_DBUS2_APB2DBUSCR_INST (0xA4023000)
+#define BASE_MADDR_MCORE_MSYSY_GLBCON (0xA4030000)
+#define BASE_MADDR_MCORE_MSYS_DBGMON (0xA4031000)
+#define BASE_MADDR_MCORE_MPERI_PERICK_ABUS_REG (0xA4032000)
+#define BASE_MADDR_MCORE_MML1_MCOREPERI_ABUSMON (0xA4033000)
+#define BASE_MADDR_MCORE_MSYS_COMDMA (0xA4034000)
+#define BASE_MADDR_MCORE_MSYS_MBIST_CAT (0xA4040000)
+#define BASE_MADDR_MCORE_MCORE_L1_CACHE (0xA4100000)
+#define BASE_MADDR_MCORE_MCORE0_L1D_CACHE (0xA4101000)
+#define BASE_MADDR_MCORE_MCORE_CLKCTRL (0xA4102000)
+#define BASE_MADDR_MCORE_MCORE_EXCEPTION_CONTROLLER (0xA4103000)
+#define BASE_MADDR_MCORE_MCORE0_L1_PROFILING_UNIT (0xA4104000)
+#define BASE_MADDR_MCORE_MCORE_A2D (0xA4105000)
+#define BASE_MADDR_MCORE_MCORE0_A2D_128 (0xA4106000)
+#define BASE_MADDR_MCORE_MCORE_D2D (0xA4107000)
+#define BASE_MADDR_MCORE_MCORE_D2A (0xA4108000)
+#define BASE_MADDR_MCORE_DBUS_REG (0xA4109000)
+#define BASE_MADDR_MCORE_MSYS_ISRD (0xA4180000)
+#define BASE_MADDR_MCORE_MML1_DSPEINTC (0xA4181000)
+#define BASE_MADDR_MCORE_MSYS_DSPDBGC1 (0xA4182000)
+#define BASE_MADDR_MCORE_MSYS_DSPCTIWRAP (0xA4183000)
+#define BASE_MADDR_MCORE_MCORE_CORE (0xA4200000)
+#define BASE_MADDR_MCORE_MCORE_L0I_CACHE (0xA4210000)
+#define BASE_MADDR_MCORE_MCORE_DATA_CACHE (0xA4211000)
+#define BASE_MADDR_MCORE_MCORE_TIMER (0xA4212000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD0_EXCTRL (0xA4213000)
+#define BASE_MADDR_MCORE_MCORE_PC_MONITOR (0xA4214000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD0_PROFILING_UNIT (0xA4215000)
+#define BASE_MADDR_MCORE_MCORE_MBIST_CONFIG_WRAP (0xA4216000)
+#define BASE_MADDR_MCORE_MCORE_MCORE_CRIT_DBUS (0xA4217000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_SONIC (0xA4220000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_L0I_CACHE (0xA4230000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_L0D_CACHE (0xA4231000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_TIMER (0xA4232000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_EXCTRL (0xA4233000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_PC_MONITOR (0xA4234000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_PROFILING_UNIT (0xA4235000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_MBIST_CONFIG (0xA4236000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_DBUS_REG (0xA4237000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_SONIC (0xA4240000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_L0I_CACHE (0xA4250000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_L0D_CACHE (0xA4251000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_TIMER (0xA4252000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_EXCTRL (0xA4253000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_PC_MONITOR (0xA4254000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_PROFILING_UNIT (0xA4255000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_MBIST_CONFIG (0xA4256000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_DBUS_REG (0xA4257000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_SONIC (0xA4260000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_L0I_CACHE (0xA4270000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_L0D_CACHE (0xA4271000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_TIMER (0xA4272000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_EXCTRL (0xA4273000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_PC_MONITOR (0xA4274000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_PROFILING_UNIT (0xA4275000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_MBIST_CONFIG (0xA4276000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_DBUS_REG (0xA4277000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_SONIC (0xA4280000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_L0I_CACHE (0xA4290000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_L0D_CACHE (0xA4291000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_TIMER (0xA4292000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_EXCTRL (0xA4293000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_PC_MONITOR (0xA4294000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_PROFILING_UNIT (0xA4295000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_MBIST_CONFIG (0xA4296000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_DBUS_REG (0xA4297000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_SONIC (0xA42A0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_L0I_CACHE (0xA42B0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_L0D_CACHE (0xA42B1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_TIMER (0xA42B2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_EXCTRL (0xA42B3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_PC_MONITOR (0xA42B4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_PROFILING_UNIT (0xA42B5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_MBIST_CONFIG (0xA42B6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_DBUS_REG (0xA42B7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_SONIC (0xA42C0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_L0I_CACHE (0xA42D0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_L0D_CACHE (0xA42D1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_TIMER (0xA42D2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_EXCTRL (0xA42D3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_PC_MONITOR (0xA42D4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_PROFILING_UNIT (0xA42D5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_MBIST_CONFIG (0xA42D6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_DBUS_REG (0xA42D7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_SONIC (0xA42E0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_L0I_CACHE (0xA42F0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_L0D_CACHE (0xA42F1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_TIMER (0xA42F2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_EXCTRL (0xA42F3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_PC_MONITOR (0xA42F4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_PROFILING_UNIT (0xA42F5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_MBIST_CONFIG (0xA42F6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_DBUS_REG (0xA42F7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_SONIC (0xA4300000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_L0I_CACHE (0xA4310000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_L0D_CACHE (0xA4311000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_TIMER (0xA4312000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_EXCTRL (0xA4313000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_PC_MONITOR (0xA4314000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_PROFILING_UNIT (0xA4315000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_MBIST_CONFIG (0xA4316000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_DBUS_REG (0xA4317000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_SONIC (0xA4320000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_L0I_CACHE (0xA4330000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_L0D_CACHE (0xA4331000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_TIMER (0xA4332000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_EXCTRL (0xA4333000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_PC_MONITOR (0xA4334000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_PROFILING_UNIT (0xA4335000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_MBIST_CONFIG (0xA4336000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_DBUS_REG (0xA4337000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_SONIC (0xA4340000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_L0I_CACHE (0xA4350000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_L0D_CACHE (0xA4351000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_TIMER (0xA4352000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_EXCTRL (0xA4353000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_PC_MONITOR (0xA4354000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_PROFILING_UNIT (0xA4355000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_MBIST_CONFIG (0xA4356000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_DBUS_REG (0xA4357000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_SONIC (0xA4360000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_L0I_CACHE (0xA4370000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_L0D_CACHE (0xA4371000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_TIMER (0xA4372000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_EXCTRL (0xA4373000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_PC_MONITOR (0xA4374000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_PROFILING_UNIT (0xA4375000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_MBIST_CONFIG (0xA4376000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_DBUS_REG (0xA4377000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_SONIC (0xA4380000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_L0I_CACHE (0xA4390000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_L0D_CACHE (0xA4391000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_TIMER (0xA4392000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_EXCTRL (0xA4393000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_PC_MONITOR (0xA4394000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_PROFILING_UNIT (0xA4395000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_MBIST_CONFIG (0xA4396000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_DBUS_REG (0xA4397000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_SONIC (0xA43A0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_L0I_CACHE (0xA43B0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_L0D_CACHE (0xA43B1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_TIMER (0xA43B2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_EXCTRL (0xA43B3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_PC_MONITOR (0xA43B4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_PROFILING_UNIT (0xA43B5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_MBIST_CONFIG (0xA43B6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_DBUS_REG (0xA43B7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_SONIC (0xA43C0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_L0I_CACHE (0xA43D0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_L0D_CACHE (0xA43D1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_TIMER (0xA43D2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_EXCTRL (0xA43D3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_PC_MONITOR (0xA43D4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_PROFILING_UNIT (0xA43D5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_MBIST_CONFIG (0xA43D6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_DBUS_REG (0xA43D7000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_SONIC (0xA43E0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_L0I_CACHE (0xA43F0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_L0D_CACHE (0xA43F1000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_TIMER (0xA43F2000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_EXCTRL (0xA43F3000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_PC_MONITOR (0xA43F4000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_PROFILING_UNIT (0xA43F5000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_MBIST_CONFIG (0xA43F6000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_DBUS_REG (0xA43F7000)
+#define BASE_MADDR_MCORE_MCORE0_L1I_CACHE (0xA4800000)
+#define BASE_MADDR_MCORE_MCORE0_L1D_CACHE_1 (0xA4900000)
+#define BASE_MADDR_MCORE_THREAD0_ICM (0xA4A00000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD0_SONIC_RESERVED0 (0xA4A04000)
+#define BASE_MADDR_MCORE_THREAD1_ICM (0xA4A10000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD1_SONIC_RESERVED1 (0xA4A14000)
+#define BASE_MADDR_MCORE_THREAD2_ICM (0xA4A20000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD2_SONIC_RESERVED2 (0xA4A24000)
+#define BASE_MADDR_MCORE_THREAD3_ICM (0xA4A30000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD3_SONIC_RESERVED3 (0xA4A34000)
+#define BASE_MADDR_MCORE_THREAD4_ICM (0xA4A40000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD4_SONIC_RESERVED4 (0xA4A44000)
+#define BASE_MADDR_MCORE_THREAD5_ICM (0xA4A50000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD5_SONIC_RESERVED5 (0xA4A54000)
+#define BASE_MADDR_MCORE_THREAD6_ICM (0xA4A60000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD6_SONIC_RESERVED6 (0xA4A64000)
+#define BASE_MADDR_MCORE_THREAD7_ICM (0xA4A70000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD7_SONIC_RESERVED7 (0xA4A74000)
+#define BASE_MADDR_MCORE_THREAD8_ICM (0xA4A80000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD8_SONIC_RESERVED8 (0xA4A84000)
+#define BASE_MADDR_MCORE_THREAD9_ICM (0xA4A90000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD9_SONIC_RESERVED9 (0xA4A94000)
+#define BASE_MADDR_MCORE_THREAD10_ICM (0xA4AA0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD10_SONIC_RESERVED10 (0xA4AA4000)
+#define BASE_MADDR_MCORE_THREAD11_ICM (0xA4AB0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD11_SONIC_RESERVED11 (0xA4AB4000)
+#define BASE_MADDR_MCORE_THREAD12_ICM (0xA4AC0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD12_SONIC_RESERVED12 (0xA4AC4000)
+#define BASE_MADDR_MCORE_THREAD13_ICM (0xA4AD0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD13_SONIC_RESERVED13 (0xA4AD4000)
+#define BASE_MADDR_MCORE_THREAD14_ICM (0xA4AE0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD14_SONIC_RESERVED14 (0xA4AE4000)
+#define BASE_MADDR_MCORE_THREAD15_ICM (0xA4AF0000)
+#define BASE_MADDR_MCORE_MCORE0_THREAD15_SONIC_RESERVED15 (0xA4AF4000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM0 (0xA4F00000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM1 (0xA4F40000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM2 (0xA4F80000)
+#define BASE_MADDR_MCORE_MSYS_O_L2TCM3 (0xA4FC0000)
+#define BASE_MADDR_MCORE_MML1_MCORESYS_SHDM (0xA4FFC000)
+// (13): MAP_VCORE_Program_private
+#define BASE_ADDR_VCORE_L1ITCM (0x00000000)
+// (14): MAP_VCORE_Data_private
+#define BASE_ADDR_VCORE_SONIC_BACKUP (0x00000000)
+#define BASE_ADDR_VCORE_SONIC (0x00040000)
+#define BASE_ADDR_VCORE_L0I_CACHE (0x00050000)
+#define BASE_ADDR_VCORE_L0D_CACHE (0x00051000)
+#define BASE_ADDR_VCORE_TIMER (0x00052000)
+#define BASE_ADDR_VCORE_EXCTRL (0x00053000)
+#define BASE_ADDR_VCORE_PC_MONITOR (0x00054000)
+#define BASE_ADDR_VCORE_VCORE_TOP_PROFILING_UNIT (0x00055000)
+#define BASE_ADDR_VCORE_VMEM_MEM (0x00060000)
+#define BASE_ADDR_VCORE_BLAZE (0x00070000)
+#define BASE_ADDR_VCORE_VMEM_CFG (0x00071000)
+#define BASE_ADDR_VCORE_HLSU (0x00072000)
+#define BASE_ADDR_VCORE_VU_PROFILING_UNIT (0x00073000)
+#define BASE_ADDR_VCORE_MBIST_CONFIG (0x00074000)
+#define BASE_ADDR_VCORE_VU_DBUS_REG (0x00075000)
+#define BASE_ADDR_VCORE_L1I_CACHE (0x00100000)
+#define BASE_ADDR_VCORE_L1D_CACHE (0x00101000)
+#define BASE_ADDR_VCORE_CLKCTRL (0x00102000)
+#define BASE_ADDR_VCORE_SHARED_EXCTRL (0x00103000)
+#define BASE_ADDR_VCORE_L1_PROFILING_UNIT (0x00104000)
+#define BASE_ADDR_VCORE_A2D_32 (0x00105000)
+#define BASE_ADDR_VCORE_A2D_128 (0x00106000)
+#define BASE_ADDR_VCORE_D2D (0x00107000)
+#define BASE_ADDR_VCORE_VCORE_TOP_DBUS_REG (0x00108000)
+#define BASE_ADDR_VCORE_MML1_DSPDBGC0 (0x00180000)
+#define BASE_ADDR_VCORE_MML1_DSPDBGC1 (0x00181000)
+#define BASE_ADDR_VCORE_MML1_DSPCTIWRAP (0x00182000)
+#define BASE_ADDR_VCORE_THREAD0_SONIC (0x00200000)
+#define BASE_ADDR_VCORE_THREAD0_L0I_CACHE (0x00210000)
+#define BASE_ADDR_VCORE_THREAD0_L0D_CACHE (0x00211000)
+#define BASE_ADDR_VCORE_THREAD0_TIMER (0x00212000)
+#define BASE_ADDR_VCORE_THREAD0_EXCTRL (0x00213000)
+#define BASE_ADDR_VCORE_THREAD0_PC_MONITOR (0x00214000)
+#define BASE_ADDR_VCORE_THREAD0_PROFILING_UNIT (0x00215000)
+#define BASE_ADDR_VCORE_VU0_VMEM_MEM (0x00220000)
+#define BASE_ADDR_VCORE_VU0_BLAZE (0x00230000)
+#define BASE_ADDR_VCORE_VU0_VMEM_CFG (0x00231000)
+#define BASE_ADDR_VCORE_VU0_HLSU (0x00232000)
+#define BASE_ADDR_VCORE_VU0_PROFILING_UNIT (0x00233000)
+#define BASE_ADDR_VCORE_VU0_MBIST_CONFIG (0x00234000)
+#define BASE_ADDR_VCORE_VU0_DBUS_REG (0x00235000)
+#define BASE_ADDR_VCORE_THREAD1_SONIC (0x00240000)
+#define BASE_ADDR_VCORE_THREAD1_L0I_CACHE (0x00250000)
+#define BASE_ADDR_VCORE_THREAD1_L0D_CACHE (0x00251000)
+#define BASE_ADDR_VCORE_THREAD1_TIMER (0x00252000)
+#define BASE_ADDR_VCORE_THREAD1_EXCTRL (0x00253000)
+#define BASE_ADDR_VCORE_THREAD1_PC_MONITOR (0x00254000)
+#define BASE_ADDR_VCORE_THREAD1_PROFILING_UNIT (0x00255000)
+#define BASE_ADDR_VCORE_VU1_VMEM_MEM (0x00260000)
+#define BASE_ADDR_VCORE_VU1_BLAZE (0x00270000)
+#define BASE_ADDR_VCORE_VU1_VMEM_CFG (0x00271000)
+#define BASE_ADDR_VCORE_VU1_HLSU (0x00272000)
+#define BASE_ADDR_VCORE_VU1_PROFILING_UNIT (0x00273000)
+#define BASE_ADDR_VCORE_VU1_MBIST_CONFIG (0x00274000)
+#define BASE_ADDR_VCORE_VU1_DBUS_REG (0x00275000)
+#define BASE_ADDR_VCORE_THREAD2_SONIC (0x00280000)
+#define BASE_ADDR_VCORE_THREAD2_L0I_CACHE (0x00290000)
+#define BASE_ADDR_VCORE_THREAD2_L0D_CACHE (0x00291000)
+#define BASE_ADDR_VCORE_THREAD2_TIMER (0x00292000)
+#define BASE_ADDR_VCORE_THREAD2_EXCTRL (0x00293000)
+#define BASE_ADDR_VCORE_THREAD2_PC_MONITOR (0x00294000)
+#define BASE_ADDR_VCORE_THREAD2_PROFILING_UNIT (0x00295000)
+#define BASE_ADDR_VCORE_VU2_VMEM_MEM (0x002A0000)
+#define BASE_ADDR_VCORE_VU2_BLAZE (0x002B0000)
+#define BASE_ADDR_VCORE_VU2_VMEM_CFG (0x002B1000)
+#define BASE_ADDR_VCORE_VU2_HLSU (0x002B2000)
+#define BASE_ADDR_VCORE_VU2_PROFILING_UNIT (0x002B3000)
+#define BASE_ADDR_VCORE_VU2_MBIST_CONFIG (0x002B4000)
+#define BASE_ADDR_VCORE_VU2_DBUS_REG (0x002B5000)
+#define BASE_ADDR_VCORE_THREAD3_SONIC (0x002C0000)
+#define BASE_ADDR_VCORE_THREAD3_L0I_CACHE (0x002D0000)
+#define BASE_ADDR_VCORE_THREAD3_L0D_CACHE (0x002D1000)
+#define BASE_ADDR_VCORE_THREAD3_TIMER (0x002D2000)
+#define BASE_ADDR_VCORE_THREAD3_EXCTRL (0x002D3000)
+#define BASE_ADDR_VCORE_THREAD3_PC_MONITOR (0x002D4000)
+#define BASE_ADDR_VCORE_THREAD3_PROFILING_UNIT (0x002D5000)
+#define BASE_ADDR_VCORE_VU3_VMEM_MEM (0x002E0000)
+#define BASE_ADDR_VCORE_VU3_BLAZE (0x002F0000)
+#define BASE_ADDR_VCORE_VU3_VMEM_CFG (0x002F1000)
+#define BASE_ADDR_VCORE_VU3_HLSU (0x002F2000)
+#define BASE_ADDR_VCORE_VU3_PROFILING_UNIT (0x002F3000)
+#define BASE_ADDR_VCORE_VU3_MBIST_CONFIG (0x002F4000)
+#define BASE_ADDR_VCORE_VU3_DBUS_REG (0x002F5000)
+#define BASE_ADDR_VCORE_THREAD4_SONIC (0x00300000)
+#define BASE_ADDR_VCORE_THREAD4_L0I_CACHE (0x00310000)
+#define BASE_ADDR_VCORE_THREAD4_L0D_CACHE (0x00311000)
+#define BASE_ADDR_VCORE_THREAD4_TIMER (0x00312000)
+#define BASE_ADDR_VCORE_THREAD4_EXCTRL (0x00313000)
+#define BASE_ADDR_VCORE_THREAD4_PC_MONITOR (0x00314000)
+#define BASE_ADDR_VCORE_THREAD4_PROFILING_UNIT (0x00315000)
+#define BASE_ADDR_VCORE_VU4_VMEM_MEM (0x00320000)
+#define BASE_ADDR_VCORE_VU4_BLAZE (0x00330000)
+#define BASE_ADDR_VCORE_VU4_VMEM_CFG (0x00331000)
+#define BASE_ADDR_VCORE_VU4_HLSU (0x00332000)
+#define BASE_ADDR_VCORE_VU4_PROFILING_UNIT (0x00333000)
+#define BASE_ADDR_VCORE_VU4_MBIST_CONFIG (0x00334000)
+#define BASE_ADDR_VCORE_VU4_DBUS_REG (0x00335000)
+#define BASE_ADDR_VCORE_THREAD5_SONIC (0x00340000)
+#define BASE_ADDR_VCORE_THREAD5_L0I_CACHE (0x00350000)
+#define BASE_ADDR_VCORE_THREAD5_L0D_CACHE (0x00351000)
+#define BASE_ADDR_VCORE_THREAD5_TIMER (0x00352000)
+#define BASE_ADDR_VCORE_THREAD5_EXCTRL (0x00353000)
+#define BASE_ADDR_VCORE_THREAD5_PC_MONITOR (0x00354000)
+#define BASE_ADDR_VCORE_THREAD5_PROFILING_UNIT (0x00355000)
+#define BASE_ADDR_VCORE_VU5_VMEM_MEM (0x00360000)
+#define BASE_ADDR_VCORE_VU5_BLAZE (0x00370000)
+#define BASE_ADDR_VCORE_VU5_VMEM_CFG (0x00371000)
+#define BASE_ADDR_VCORE_VU5_HLSU (0x00372000)
+#define BASE_ADDR_VCORE_VU5_PROFILING_UNIT (0x00373000)
+#define BASE_ADDR_VCORE_VU5_MBIST_CONFIG (0x00374000)
+#define BASE_ADDR_VCORE_VU5_DBUS_REG (0x00375000)
+#define BASE_ADDR_VCORE_THREAD6_SONIC (0x00380000)
+#define BASE_ADDR_VCORE_THREAD6_L0I_CACHE (0x00390000)
+#define BASE_ADDR_VCORE_THREAD6_L0D_CACHE (0x00391000)
+#define BASE_ADDR_VCORE_THREAD6_TIMER (0x00392000)
+#define BASE_ADDR_VCORE_THREAD6_EXCTRL (0x00393000)
+#define BASE_ADDR_VCORE_THREAD6_PC_MONITOR (0x00394000)
+#define BASE_ADDR_VCORE_THREAD6_PROFILING_UNIT (0x00395000)
+#define BASE_ADDR_VCORE_VU6_VMEM_MEM (0x003A0000)
+#define BASE_ADDR_VCORE_VU6_BLAZE (0x003B0000)
+#define BASE_ADDR_VCORE_VU6_VMEM_CFG (0x003B1000)
+#define BASE_ADDR_VCORE_VU6_HLSU (0x003B2000)
+#define BASE_ADDR_VCORE_VU6_PROFILING_UNIT (0x003B3000)
+#define BASE_ADDR_VCORE_VU6_MBIST_CONFIG (0x003B4000)
+#define BASE_ADDR_VCORE_VU6_DBUS_REG (0x003B5000)
+#define BASE_ADDR_VCORE_THREAD7_SONIC (0x003C0000)
+#define BASE_ADDR_VCORE_THREAD7_L0I_CACHE (0x003D0000)
+#define BASE_ADDR_VCORE_THREAD7_L0D_CACHE (0x003D1000)
+#define BASE_ADDR_VCORE_THREAD7_TIMER (0x003D2000)
+#define BASE_ADDR_VCORE_THREAD7_EXCTRL (0x003D3000)
+#define BASE_ADDR_VCORE_THREAD7_PC_MONITOR (0x003D4000)
+#define BASE_ADDR_VCORE_THREAD7_PROFILING_UNIT (0x003D5000)
+#define BASE_ADDR_VCORE_VU7_VMEM_MEM (0x003E0000)
+#define BASE_ADDR_VCORE_VU7_BLAZE (0x003F0000)
+#define BASE_ADDR_VCORE_VU7_VMEM_CFG (0x003F1000)
+#define BASE_ADDR_VCORE_VU7_HLSU (0x003F2000)
+#define BASE_ADDR_VCORE_VU7_PROFILING_UNIT (0x003F3000)
+#define BASE_ADDR_VCORE_VU7_MBIST_CONFIG (0x003F4000)
+#define BASE_ADDR_VCORE_VU7_DBUS_REG (0x003F5000)
+#define BASE_ADDR_VCORE_MML1_DSPSLVSCHEDULER (0x00800000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORELOG (0x00801000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_VU2GRAM (0x00802000)
+#define BASE_ADDR_VCORE_VPERI_DBUS1 (0x00803000)
+#define BASE_ADDR_VCORE_DBUS_AXI2DBUS (0x00804000)
+#define BASE_ADDR_VCORE_MML1_DSPBUSRECORDER (0x00805000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_DBGMON_WRAP (0x00806000)
+#define BASE_ADDR_VCORE_VCORESYS_TOP_GLOBAL_CON (0x00807000)
+#define BASE_ADDR_VCORE_MML1_VPERI_DSPCORECK_ABUS_REG (0x00808000)
+#define BASE_ADDR_VCORE_MML1_DSPSWLA (0x00810000)
+#define BASE_ADDR_VCORE_VPERI_DBUS2 (0x00811000)
+#define BASE_ADDR_VCORE_MML1_VPERI_PERICK_ABUS_REG (0x00814000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_MBIST_CAT_MBIST_TOP_CFG (0x00820000)
+#define BASE_ADDR_VCORE_MML1_DSP_MSPDBGMEN (0x00F00000)
+#define BASE_ADDR_VCORE_L1DTCM (0x01000000)
+// (15): MAP_VCORE_global
+#define BASE_MADDR_VCORE_VSYS_DSPSLVSCHEDULER (0xA5000000)
+#define BASE_MADDR_VCORE_VSYS_DSPVCORELOG (0xA5001000)
+#define BASE_MADDR_VCORE_VSYS_VU2GRAM (0xA5002000)
+#define BASE_MADDR_VCORE_VPERI_DBUS1_APB2DBUSCR_INST (0xA5003000)
+#define BASE_MADDR_VCORE_VPERI_A2D (0xA5004000)
+#define BASE_MADDR_VCORE_VPERI_DBUSRECORDER (0xA5005000)
+#define BASE_MADDR_VCORE_VSYS_DBGMON (0xA5006000)
+#define BASE_MADDR_VCORE_VSYS_GLBCON (0xA5007000)
+#define BASE_MADDR_VCORE_VPERI_DSPCORECK_ABUS_REG (0xA5008000)
+#define BASE_MADDR_VCORE_VSYS_SWLA (0xA5010000)
+#define BASE_MADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST (0xA5011000)
+#define BASE_MADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST_1 (0xA5011100)
+#define BASE_MADDR_VCORE_VPERI_PERICK_ABUS_REG (0xA5014000)
+#define BASE_MADDR_VCORE_MBIST_CAT_BUS_DECODER (0xA5020000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_L1_CACHE (0xA5100000)
+#define BASE_MADDR_VCORE_VCORE0_L1D_CACHE (0xA5101000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CLKCTRL (0xA5102000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_EXCEPTION_CONTROLLER (0xA5103000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_PROFILING_UNIT (0xA5104000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_A2D (0xA5105000)
+#define BASE_MADDR_VCORE_VCORE0_A2D_128 (0xA5106000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_D2D (0xA5107000)
+#define BASE_MADDR_VCORE_DBUS_REG (0xA5108000)
+#define BASE_MADDR_VCORE_MML1_DSPEINTC (0xA5180000)
+#define BASE_MADDR_VCORE_VSYS_DSPDBGC1 (0xA5181000)
+#define BASE_MADDR_VCORE_VSYS_DSPCTIWRAP (0xA5182000)
+#define BASE_MADDR_VCORE_VSYS_DSPCTIWRAP_1 (0xA5182020)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_CORE (0xA5200000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_L0I_CACHE (0xA5210000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_DATA_CACHE (0xA5211000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_TIMER (0xA5212000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD0_EXCTRL (0xA5213000)
+#define BASE_MADDR_VCORE_MML1_DSPVCORE_TOP_PC_MONITOR (0xA5214000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD0_PROFILING_UNIT (0xA5215000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_L1 (0xA5220000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_BLAZE (0xA5230000)
+#define BASE_MADDR_VCORE_VCORE0_VU0_VMEM_CFG (0xA5231000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_HLSU (0xA5232000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_PROFILING_UNIT (0xA5233000)
+#define BASE_MADDR_VCORE_VCORE_VU_MBIST_CONFIG (0xA5234000)
+#define BASE_MADDR_VCORE_VCORE_VU_TOP_VCORE_VU_DBUS (0xA5235000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_SONIC (0xA5240000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_L0I_CACHE (0xA5250000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_L0D_CACHE (0xA5251000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_TIMER (0xA5252000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_EXCTRL (0xA5253000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_PC_MONITOR (0xA5254000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_PROFILING_UNIT (0xA5255000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_VMEM_MEM (0xA5260000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_BLAZE (0xA5270000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_VMEM_CFG (0xA5271000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_HLSU (0xA5272000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_PROFILING_UNIT (0xA5273000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_MBIST_CONFIG (0xA5274000)
+#define BASE_MADDR_VCORE_VCORE0_VU1_DBUS_REG (0xA5275000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_SONIC (0xA5280000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_L0I_CACHE (0xA5290000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_L0D_CACHE (0xA5291000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_TIMER (0xA5292000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_EXCTRL (0xA5293000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_PC_MONITOR (0xA5294000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_PROFILING_UNIT (0xA5295000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_VMEM_MEM (0xA52A0000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_BLAZE (0xA52B0000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_VMEM_CFG (0xA52B1000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_HLSU (0xA52B2000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_PROFILING_UNIT (0xA52B3000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_MBIST_CONFIG (0xA52B4000)
+#define BASE_MADDR_VCORE_VCORE0_VU2_DBUS_REG (0xA52B5000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_SONIC (0xA52C0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_L0I_CACHE (0xA52D0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_L0D_CACHE (0xA52D1000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_TIMER (0xA52D2000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_EXCTRL (0xA52D3000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_PC_MONITOR (0xA52D4000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_PROFILING_UNIT (0xA52D5000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_VMEM_MEM (0xA52E0000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_BLAZE (0xA52F0000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_VMEM_CFG (0xA52F1000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_HLSU (0xA52F2000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_PROFILING_UNIT (0xA52F3000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_MBIST_CONFIG (0xA52F4000)
+#define BASE_MADDR_VCORE_VCORE0_VU3_DBUS_REG (0xA52F5000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_SONIC (0xA5300000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_L0I_CACHE (0xA5310000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_L0D_CACHE (0xA5311000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_TIMER (0xA5312000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_EXCTRL (0xA5313000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_PC_MONITOR (0xA5314000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_PROFILING_UNIT (0xA5315000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_VMEM_MEM (0xA5320000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_BLAZE (0xA5330000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_VMEM_CFG (0xA5331000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_HLSU (0xA5332000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_PROFILING_UNIT (0xA5333000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_MBIST_CONFIG (0xA5334000)
+#define BASE_MADDR_VCORE_VCORE0_VU4_DBUS_REG (0xA5335000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_SONIC (0xA5340000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_L0I_CACHE (0xA5350000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_L0D_CACHE (0xA5351000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_TIMER (0xA5352000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_EXCTRL (0xA5353000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_PC_MONITOR (0xA5354000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_PROFILING_UNIT (0xA5355000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_VMEM_MEM (0xA5360000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_BLAZE (0xA5370000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_VMEM_CFG (0xA5371000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_HLSU (0xA5372000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_PROFILING_UNIT (0xA5373000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_MBIST_CONFIG (0xA5374000)
+#define BASE_MADDR_VCORE_VCORE0_VU5_DBUS_REG (0xA5375000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_SONIC (0xA5380000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_L0I_CACHE (0xA5390000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_L0D_CACHE (0xA5391000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_TIMER (0xA5392000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_EXCTRL (0xA5393000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_PC_MONITOR (0xA5394000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_PROFILING_UNIT (0xA5395000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_VMEM_MEM (0xA53A0000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_BLAZE (0xA53B0000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_VMEM_CFG (0xA53B1000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_HLSU (0xA53B2000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_PROFILING_UNIT (0xA53B3000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_MBIST_CONFIG (0xA53B4000)
+#define BASE_MADDR_VCORE_VCORE0_VU6_DBUS_REG (0xA53B5000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_SONIC (0xA53C0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_L0I_CACHE (0xA53D0000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_L0D_CACHE (0xA53D1000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_TIMER (0xA53D2000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_EXCTRL (0xA53D3000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_PC_MONITOR (0xA53D4000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_PROFILING_UNIT (0xA53D5000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_VMEM_MEM (0xA53E0000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_BLAZE (0xA53F0000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_VMEM_CFG (0xA53F1000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_HLSU (0xA53F2000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_PROFILING_UNIT (0xA53F3000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_MBIST_CONFIG (0xA53F4000)
+#define BASE_MADDR_VCORE_VCORE0_VU7_DBUS_REG (0xA53F5000)
+#define BASE_MADDR_VCORE_VCORE0_L1I_CACHE (0xA5800000)
+#define BASE_MADDR_VCORE_VCORE0_L1D_CACHE_1 (0xA5900000)
+#define BASE_MADDR_VCORE_THREAD0_ICM (0xA5A00000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD0_SONIC_RESERVED0 (0xA5A04000)
+#define BASE_MADDR_VCORE_THREAD1_ICM (0xA5A10000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD1_SONIC_RESERVED1 (0xA5A14000)
+#define BASE_MADDR_VCORE_THREAD2_ICM (0xA5A20000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD2_SONIC_RESERVED2 (0xA5A24000)
+#define BASE_MADDR_VCORE_THREAD3_ICM (0xA5A30000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD3_SONIC_RESERVED3 (0xA5A34000)
+#define BASE_MADDR_VCORE_THREAD4_ICM (0xA5A40000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD4_SONIC_RESERVED4 (0xA5A44000)
+#define BASE_MADDR_VCORE_THREAD5_ICM (0xA5A50000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD5_SONIC_RESERVED5 (0xA5A54000)
+#define BASE_MADDR_VCORE_THREAD6_ICM (0xA5A60000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD6_SONIC_RESERVED6 (0xA5A64000)
+#define BASE_MADDR_VCORE_THREAD7_ICM (0xA5A70000)
+#define BASE_MADDR_VCORE_VCORE0_THREAD7_SONIC_RESERVED7 (0xA5A74000)
+// (16): MAP_gramsys
+#define BASE_MADDR_GRAM_GRAM_BRIDGE (0xA6000000)
+#define BASE_MADDR_GRAM_GRAM_GLBCON (0xA6F00000)
+#define BASE_MADDR_GRAM_GRAMSYS_MBIST_MBIST_TOP_CFG (0xA6F10000)
+#define BASE_MADDR_GRAM_GRAM_BRIDGE_REG (0xA6F20000)
+#define BASE_MADDR_GRAM_GRAM_REG (0xA6F30000)
+#define BASE_MADDR_GRAM_GRAM_BUS_CONFIG (0xA6F40000)
+// (17): MAP_Dbgsys
+#define BASE_MADDR_2ND_ROM_TABLE_DAP_2ND_ROM (0xA0600000)
+#define BASE_MADDR_MDDBGSYS_DEM_DEM (0xA0601000)
+#define BASE_MADDR_MDPERISYS_MISC_REG_MDPERISYS_MISC_REG (0xA0602000)
+#define BASE_MADDR_MD_DBGMON_MD_DBGMON (0xA0603000)
+#define BASE_MADDR_MDPERI_CLKTL_MDPERI_CLKTL (0xA0603800)
+#define BASE_MADDR_IA_USIP_ECT_MD_CXCTI (0xA0604000)
+#define BASE_MADDR_VDSP_MD32_ECT_MD_CXCTI (0xA0605000)
+#define BASE_MADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xA0606000)
+#define BASE_MADDR_TOPSM_PROTECT_MDL1_MODEM_TOPSM_PROTECT (0xA060B000)
+#define BASE_MADDR_TOPSM_MDL1_MODEM_TOPSM (0xA060C000)
+#define BASE_MADDR_OSTIMER_MD_OSTIMER (0xA060D000)
+#define BASE_MADDR_RGU_MDRGU_REG (0xA060E000)
+#define BASE_MADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xA060F000)
+#define BASE_MADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xA0610000)
+#define BASE_MADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xA0611000)
+#define BASE_MADDR_MD_CLKSW_MD_CLKSW_REG (0xA0612000)
+#define BASE_MADDR_RAKE_BUS_INTF_RAKESYS_BUS_DBGAPB_INTF (0xA0614000)
+#define BASE_MADDR_RAKE_MD32_RAKE_MD32 (0xA0616000)
+#define BASE_MADDR_VDSP_1_MD32SCQ (0xA0618000)
+#define BASE_MADDR_VDSP_2_MD32SCQ (0xA0619000)
+#define BASE_MADDR_VDSP_3_MD32SCQ (0xA061A000)
+#define BASE_MADDR_VDSP_4_MD32SCQ (0xA061B000)
+#define BASE_MADDR_BIGRAM_BUS_INTF_BIGRAM_BUS_INTF (0xA061C000)
+#define BASE_MADDR_INR_BUS_INTF_INR_BUS_INTF (0xA061E000)
+#define BASE_MADDR_USIP0_USIP0 (0xA0620000)
+#define BASE_MADDR_USIP1_USIP1 (0xA0621000)
+#define BASE_MADDR_USIPCORE_BUS_INTF_USIPCORE_BUS_INTF (0xA0622000)
+#define BASE_MADDR_L2SRAM_L2SRAM (0xA0624000)
+#define BASE_MADDR_MDMCU_BUS_INTF_VDNR__MDMCU_BUS_INTF (0xA0628000)
+#define BASE_MADDR_MDMCU_COREBUS_INTF_VDNR__MDMCU_COREBUS_INTF (0xA062A000)
+#define BASE_MADDR_MDMCU_BUSMON_MDMCU_BUSMON (0xA062C000)
+#define BASE_MADDR_MDMCU_USIP_BUS_INTF_MDMCU_USIP_BUS_INTF (0xA062D000)
+#define BASE_MADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xA0630000)
+#define BASE_MADDR_SHAOLIN_DEBUG_PERI_SHAOLIN_DEBUG_PERI (0xA0633000)
+#define BASE_MADDR_SHAOLIN_MACRO_BUS_INTF_VDNR__SHAOLIN_MACRO_BUS_INTF (0xA0634000)
+#define BASE_MADDR_SHAOLIN_BUSMPU_SHAOLIN_BUSMPU (0xA0636000)
+#define BASE_MADDR_SHAOLIN_CM2_SHAOLIN_CM2 (0xA0637000)
+#define BASE_MADDR_SHAOLIN_CORE0__SHAOLIN_CORE0 (0xA0638000)
+#define BASE_MADDR_SHAOLIN_CORE1_SHAOLIN_CORE1 (0xA0639000)
+#define BASE_MADDR_SHAOLIN_CORE2__SHAOLIN_CORE2 (0xA063A000)
+#define BASE_MADDR_SHAOLIN_CORE3_SHAOLIN_CORE3 (0xA063B000)
+#define BASE_MADDR_MDINFRA_BUS4X_REG_MDINFRA_BUS4X_REG (0xA063C000)
+#define BASE_MADDR_MDINFRA_BUS2X_REG_MDINFRA_BUS2X_REG (0xA063D000)
+#define BASE_MADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xA063E000)
+#define BASE_MADDR_NRL2_BUS_INTF_NRL2_BUS_INTF (0xA0640000)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_RXCPC_NR_DBGAPB_MAS_BUS_INTF (0xA0642000)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2 (0xA0642800)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_RXCPC_NR_DBGAPB_SLV_BUS_INTF (0xA0643000)
+#define BASE_MADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2 (0xA0643800)
+#define BASE_MADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF (0xA0644000)
+#define BASE_MADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF_1 (0xA0645000)
+#define BASE_MADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF (0xA0646000)
+#define BASE_MADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF_1 (0xA0647000)
+#define BASE_MADDR_MDAO_MAS_BUS_CK_DBG_MDAO_MAS_BUS_CK_DBG (0xA0648000)
+#define BASE_MADDR_MDAO_SLV_BUS_CK_DBG_MDAO_SLV_BUS_CK_DBG (0xA0649000)
+#define BASE_MADDR_MD_DVFS_TOP_CK_DBG_MD_DVFS_TOP_CK_DBG (0xA0649800)
+#define BASE_MADDR_MDL1_TOPSM_MDL1_TOPSM (0xA064A000)
+#define BASE_MADDR_RFSLPC_RFSLPC (0xA064B000)
+#define BASE_MADDR_MD2G_BUS_MD2G_BUS (0xA064C000)
+#define BASE_MADDR_CSSYS_BUS_CK_DBG_CSSYS_BUS_CK_DBG (0xA064E000)
+#define BASE_MADDR_CSSYS_BUS_DIV2_CK_DBG_CSSYS_BUS_DIV2_CK_DBG (0xA064E800)
+#define BASE_MADDR_MDAO_BUS_CK_DBG_MDAO_BUS_CK_DBG (0xA064F000)
+#define BASE_MADDR_VCORE_TOP_TH0_SONIC_VCORE (0xA0650000)
+#define BASE_MADDR_VCORE_TOP_TH0_PC_MONITOR_VCORE (0xA0650400)
+#define BASE_MADDR_VCORE_TOP_TH0_VUDBUS_VCORE (0xA0650480)
+#define BASE_MADDR_VCORE_TOP_TH1_SONIC_VCORE (0xA0650600)
+#define BASE_MADDR_VCORE_TOP_TH1_PC_MONITOR_VCORE (0xA0650A00)
+#define BASE_MADDR_VCORE_TOP_TH1_VUDBUS_VCORE (0xA0650A80)
+#define BASE_MADDR_VCORE_TOP_TH2_SONIC_VCORE (0xA0650C00)
+#define BASE_MADDR_VCORE_TOP_TH2_PC_MONITOR_VCORE (0xA0651000)
+#define BASE_MADDR_VCORE_TOP_TH2_VUDBUS_VCORE (0xA0651080)
+#define BASE_MADDR_VCORE_TOP_TH3_SONIC_VCORE (0xA0651200)
+#define BASE_MADDR_VCORE_TOP_TH3_PC_MONITOR_VCORE (0xA0651600)
+#define BASE_MADDR_VCORE_TOP_TH3_VUDBUS_VCORE (0xA0651680)
+#define BASE_MADDR_VCORE_TOP_TH4_SONIC_VCORE (0xA0651800)
+#define BASE_MADDR_VCORE_TOP_TH4_PC_MONITOR_VCORE (0xA0651C00)
+#define BASE_MADDR_VCORE_TOP_TH4_VUDBUS_VCORE (0xA0651C80)
+#define BASE_MADDR_VCORE_TOP_TH5_SONIC_VCORE (0xA0651E00)
+#define BASE_MADDR_VCORE_TOP_TH5_PC_MONITOR_VCORE (0xA0652200)
+#define BASE_MADDR_VCORE_TOP_TH5_VUDBUS_VCORE (0xA0652280)
+#define BASE_MADDR_VCORE_TOP_TH6_SONIC_VCORE (0xA0652400)
+#define BASE_MADDR_VCORE_TOP_TH6_PC_MONITOR_VCORE (0xA0652800)
+#define BASE_MADDR_VCORE_TOP_TH6_VUDBUS_VCORE (0xA0652880)
+#define BASE_MADDR_VCORE_TOP_TH7_SONIC_VCORE (0xA0652A00)
+#define BASE_MADDR_VCORE_TOP_TH7_PC_MONITOR_VCORE (0xA0652E00)
+#define BASE_MADDR_VCORE_TOP_TH7_VUDBUS_VCORE (0xA0652E80)
+#define BASE_MADDR_VCORE_TOP_L1_DBUS_VCORE (0xA0653000)
+#define BASE_MADDR_VCORE_TOP_A2D32_VCORE (0xA0654000)
+#define BASE_MADDR_VCORE_TOP_A2D128_VCORE (0xA0654080)
+#define BASE_MADDR_VCORECK_ABUS_VCORECK_ABUS (0xA0655000)
+#define BASE_MADDR_VCORE_DIV2CK_ABUS_VCORE_DIV2CK_ABUS (0xA0655800)
+#define BASE_MADDR_VCORE_CK_DBUS_VCORE_CK_DBUS (0xA0656000)
+#define BASE_MADDR_VCORE_DIV2CK_DBUS_VCORE_DIV2CK_DBUS (0xA0656800)
+#define BASE_MADDR_BUS_RECORDER_BUS_RECORDER (0xA0657000)
+#define BASE_MADDR_VPERIA2D_DBGAPB_VPERIA2D_DBGAPB (0xA0657800)
+#define BASE_MADDR_DEBUG_MONITOR_FOR_DBG_FLAG_MML1_DSPVCORE_DBGMON_WRAP (0xA0657880)
+#define BASE_MADDR_VCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_VCORE_MML1_DSPCTIWRAP (0xA0657900)
+#define BASE_MADDR_VCORE_PAR_AO_CR_VCORE_PAR_AO_CR (0xA0657A00)
+#define BASE_MADDR_GRAM_PERI_GRAM_PERI (0xA0658000)
+#define BASE_MADDR_MCORE0_TOP_TH0_SONIC_MCORE0 (0xA0660000)
+#define BASE_MADDR_MCORE0_TOP_TH0_PC_MONITOR_MCORE0 (0xA0660400)
+#define BASE_MADDR_MCORE0_TOP_TH0_VUDBUS_MCORE0 (0xA0660480)
+#define BASE_MADDR_MCORE0_TOP_TH1_SONIC_MCORE0 (0xA0660600)
+#define BASE_MADDR_MCORE0_TOP_TH1_PC_MONITOR_MCORE0 (0xA0660A00)
+#define BASE_MADDR_MCORE0_TOP_TH1_VUDBUS_MCORE0 (0xA0660A80)
+#define BASE_MADDR_MCORE0_TOP_TH2_SONIC_MCORE0 (0xA0660C00)
+#define BASE_MADDR_MCORE0_TOP_TH2_PC_MONITOR_MCORE0 (0xA0661000)
+#define BASE_MADDR_MCORE0_TOP_TH2_VUDBUS_MCORE0 (0xA0661080)
+#define BASE_MADDR_MCORE0_TOP_TH3_SONIC_MCORE0 (0xA0661200)
+#define BASE_MADDR_MCORE0_TOP_TH3_PC_MONITOR_MCORE0 (0xA0661600)
+#define BASE_MADDR_MCORE0_TOP_TH3_VUDBUS_MCORE0 (0xA0661680)
+#define BASE_MADDR_MCORE0_TOP_TH4_SONIC_MCORE0 (0xA0661800)
+#define BASE_MADDR_MCORE0_TOP_TH4_PC_MONITOR_MCORE0 (0xA0661C00)
+#define BASE_MADDR_MCORE0_TOP_TH4_VUDBUS_MCORE0 (0xA0661C80)
+#define BASE_MADDR_MCORE0_TOP_TH5_SONIC_MCORE0 (0xA0661E00)
+#define BASE_MADDR_MCORE0_TOP_TH5_PC_MONITOR_MCORE0 (0xA0662200)
+#define BASE_MADDR_MCORE0_TOP_TH5_VUDBUS_MCORE0 (0xA0662280)
+#define BASE_MADDR_MCORE0_TOP_TH6_SONIC_MCORE0 (0xA0662400)
+#define BASE_MADDR_MCORE0_TOP_TH6_PC_MONITOR_MCORE0 (0xA0662800)
+#define BASE_MADDR_MCORE0_TOP_TH6_VUDBUS_MCORE0 (0xA0662880)
+#define BASE_MADDR_MCORE0_TOP_TH7_SONIC_MCORE0 (0xA0662A00)
+#define BASE_MADDR_MCORE0_TOP_TH7_PC_MONITOR_MCORE0 (0xA0662E00)
+#define BASE_MADDR_MCORE0_TOP_TH7_VUDBUS_MCORE0 (0xA0662E80)
+#define BASE_MADDR_MCORE0_TOP_TH8_SONIC_MCORE0 (0xA0663000)
+#define BASE_MADDR_MCORE0_TOP_TH8_PC_MONITOR_MCORE0 (0xA0663400)
+#define BASE_MADDR_MCORE0_TOP_TH8_VUDBUS_MCORE0 (0xA0663480)
+#define BASE_MADDR_MCORE0_TOP_TH9_SONIC_MCORE0 (0xA0663600)
+#define BASE_MADDR_MCORE0_TOP_TH9_PC_MONITOR_MCORE0 (0xA0663A00)
+#define BASE_MADDR_MCORE0_TOP_TH9_VUDBUS_MCORE0 (0xA0663A80)
+#define BASE_MADDR_MCORE0_TOP_TH10_SONIC_MCORE0 (0xA0663C00)
+#define BASE_MADDR_MCORE0_TOP_TH10_PC_MONITOR_MCORE0 (0xA0664000)
+#define BASE_MADDR_MCORE0_TOP_TH10_VUDBUS_MCORE0 (0xA0664080)
+#define BASE_MADDR_MCORE0_TOP_TH11_SONIC_MCORE0 (0xA0664200)
+#define BASE_MADDR_MCORE0_TOP_TH11_PC_MONITOR_MCORE0 (0xA0664600)
+#define BASE_MADDR_MCORE0_TOP_TH11_VUDBUS_MCORE0 (0xA0664680)
+#define BASE_MADDR_MCORE0_TOP_TH12_SONIC_MCORE0 (0xA0664800)
+#define BASE_MADDR_MCORE0_TOP_TH12_PC_MONITOR_MCORE0 (0xA0664C00)
+#define BASE_MADDR_MCORE0_TOP_TH12_VUDBUS_MCORE0 (0xA0664C80)
+#define BASE_MADDR_MCORE0_TOP_TH13_SONIC_MCORE0 (0xA0664E00)
+#define BASE_MADDR_MCORE0_TOP_TH13_PC_MONITOR_MCORE0 (0xA0665200)
+#define BASE_MADDR_MCORE0_TOP_TH13_VUDBUS_MCORE0 (0xA0665280)
+#define BASE_MADDR_MCORE0_TOP_TH14_SONIC_MCORE0 (0xA0665400)
+#define BASE_MADDR_MCORE0_TOP_TH14_PC_MONITOR_MCORE0 (0xA0665800)
+#define BASE_MADDR_MCORE0_TOP_TH14_VUDBUS_MCORE0 (0xA0665880)
+#define BASE_MADDR_MCORE0_TOP_TH15_SONIC_MCORE0 (0xA0665A00)
+#define BASE_MADDR_MCORE0_TOP_TH15_PC_MONITOR_MCORE0 (0xA0665E00)
+#define BASE_MADDR_MCORE0_TOP_TH15_VUDBUS_MCORE0 (0xA0665E80)
+#define BASE_MADDR_MCORE0_TOP_L1DBUS_MCORE0 (0xA0666000)
+#define BASE_MADDR_MCORE0_TOP_L1I_CACHE_MCORE0 (0xA0667000)
+#define BASE_MADDR_MCORE0_TOP_L1D_CACHE_MCORE0 (0xA0667200)
+#define BASE_MADDR_MCORE0_TOP_A2D32_MCORE0 (0xA0667400)
+#define BASE_MADDR_MCORE0_TOP_A2D128_MCORE0 (0xA0667480)
+#define BASE_MADDR_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB (0xA0670000)
+#define BASE_MADDR_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB (0xA0671000)
+#define BASE_MADDR_MML1_MPERI_PERICK_ABUS_REG_DBGAPB_MML1_MPERI_PERICK_ABUS_REG_DBGAPB (0xA0672000)
+#define BASE_MADDR_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB (0xA0673000)
+#define BASE_MADDR_MML1_MPERI_DSPCK_DBUS_REG_DBG_MML1_MPERI_DSPCK_DBUS_REG_DBG (0xA0674000)
+#define BASE_MADDR_MML1_MPERI_PERICK_DBUS_REG_DBG_MML1_MPERI_PERICK_DBUS_REG_DBG (0xA0675000)
+#define BASE_MADDR_MML1_MCOREPERI_ABUSMON_TOP_DBG_MML1_MCOREPERI_ABUSMON_TOP_DBG (0xA0676000)
+#define BASE_MADDR_MML1_MPERI_DBUSRECORDER_DBG_MML1_MPERI_DBUSRECORDER_DBG (0xA0677000)
+#define BASE_MADDR_MPERIA2D_DBGAPB_MPERIA2D_DBGAPB (0xA0678000)
+#define BASE_MADDR_MML1_MCORESYS_DBGMON_WRAP_MML1_MCORESYS_DBGMON_WRAP (0xA0679000)
+#define BASE_MADDR_MML1_MPERI_DSPCORECK_DBUS_REG_DBG_MML1_MPERI_DSPCORECK_DBUS_REG_DBG (0xA067A000)
+#define BASE_MADDR_CMCS_MAS_MDTOP_BUS4X_CK_REG_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xA0680000)
+#define BASE_MADDR_CMCS_SLV_MDTOP_BUS4X_CK_REG_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xA0681000)
+#define BASE_MADDR_CM_CS_BUS_CK_REG_MML1_CM_CS_BUS_CK_ABUS_REG (0xA0682000)
+#define BASE_MADDR_CS_NR_BUS_CK_REG_MML1_CS_NR_BUS_CK_ABUS_REG (0xA0683000)
+#define BASE_MADDR_CMCS_NR_CM_NR_CK_REG_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xA0684000)
+#define BASE_MADDR_CM_NR_MDTOP_BUS4X_CK_REG_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xA0685000)
+#define BASE_MADDR_CMCS_NR_RXTFC_NR_CK_REG_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xA0686000)
+#define BASE_MADDR_RXTFC_MDTOP_BUS4X_CK_REG_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xA0687000)
+#define BASE_MADDR_CMCS_NR_RXTDB_NR_CK_REG_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xA0688000)
+#define BASE_MADDR_RXTDB_MDTOP_BUS4X_CK_REG_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xA0689000)
+#define BASE_MADDR_CMCS_NR_RXTDB_PBCH_NR_CK_REG_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xA068A000)
+#define BASE_MADDR_RXTDB_PBCH_MDTOP_BUS4X_CK_REG_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xA068B000)
+#define BASE_MADDR_TX_NR_MAS_TXBSRP_NR_CK_REG_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xA0690000)
+#define BASE_MADDR_TX_NR_MAS_MDTOP_BUS4X_CK_REG_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xA0691000)
+#define BASE_MADDR_TX_NR_SLV_TXBSRP_NR_CK_REG_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xA0692000)
+#define BASE_MADDR_TX_NR_SLV_MDTOP_BUS4X_CK_REG_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xA0693000)
+#define BASE_MADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF (0xA0694000)
+#define BASE_MADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF_1 (0xA0696000)
+#define BASE_MADDR_DFESYS_BUS_INTF_DFESYS_MAS_BUS_CONFIG_REAL (0xA0698000)
+#define BASE_MADDR_DFESYS_BUS_INTF_DFESYS_SLV_BUS_CONFIG (0xA069A000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_BUS_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xA069C000)
+#define BASE_MADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xA069D000)
+#define BASE_MADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xA069F0000)
+#define BASE_MADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xA069F8000)
+#define BASE_MADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TXDFE_468M_CK_ABUS_REG (0xA06A0000)
+#define BASE_MADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TPC_468M_CK_ABUS_REG (0xA06A3000)
+#define BASE_MADDR_MMW_RXDFE_BUS_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xA06A4000)
+#define BASE_MADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xA06A5000)
+#define BASE_MADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xA06A7000)
+// (18): MAP_rxddm_nr
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR (0xA7000000)
+#define BASE_MADDR_RXDDM_NR_RESERVED0 (0xA7008000)
+#define BASE_MADDR_RXDDM_NR_RESERVED1 (0xA700A000)
+#define BASE_MADDR_RXDDM_NR_RESERVED2 (0xA700C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xA700E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_EGID (0xA7010000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_EGOC (0xA7012000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xA7014000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xA7016000)
+#define BASE_MADDR_RXDDM_NR_RESERVED3 (0xA7018000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_STIME_LOG (0xA701A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MDCC (0xA701C000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xA701E000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xA7020000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_ROI (0xA7022000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_DCE (0xA7024000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_PP (0xA7026000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xA7028000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_SRCH (0xA702A000)
+#define BASE_MADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xA702C000)
+#define BASE_MADDR_RXDDM_NR_MML1_RXDDM_CK_ABUS_REG (0xA702E000)
+#define BASE_MADDR_RXDDM_NR_MML1_RXDDM_HALF_CK_ABUS_REG (0xA7030000)
+#define BASE_MADDR_RXDDM_NR_SLOT_RNTI (0xA7200000)
+#define BASE_MADDR_RXDDM_NR_RESERVED4 (0xA7201000)
+#define BASE_MADDR_RXDDM_NR_SYM (0xA7220000)
+#define BASE_MADDR_RXDDM_NR_RESERVED5 (0xA7228000)
+#define BASE_MADDR_RXDDM_NR_MASK_TYPE0 (0xA7240000)
+#define BASE_MADDR_RXDDM_NR_MASK_TYPE1 (0xA7260000)
+// (19): MAP_rxcsi_nr
+#define BASE_MADDR_RXCSI_NR_NR_CSI (0xA7400000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xA7500000)
+#define BASE_MADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xA7501000)
+// (20): MAP_rxdbrp_nr
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xA7800000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xA7810000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xA7820000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xA7830000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xA7840000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xA7850000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xA7860000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xA7870000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xA7880000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DO (0xA7890000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xA78A0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xA78B0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xA78C0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xA78D0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xA78E0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xA78F0000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xA7900000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED_0 (0xA7910000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xA7920000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xA7930000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xA7940000)
+#define BASE_MADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xA7950000)
+#define BASE_MADDR_RXDBRP_NR_RESERVED_1 (0xA7960000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_EMI_CK_ABUS_REG (0xA7970000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_EMI_HALF_CK_ABUS_REG (0xA7980000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_SD_CK_ABUS_REG (0xA7990000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_SD_HALF_CK_ABUS_REG (0xA79A0000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_CK_ABUS_REG (0xA79B0000)
+#define BASE_MADDR_RXDBRP_NR_MML1_RXDBRP_HALF_CK_ABUS_REG (0xA79C0000)
+// (21): MAP_rxcpc_nr
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xA7C00000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CPC (0xA7C02000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xA7C04000)
+#define BASE_MADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xA7C06000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xA7C08000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xA7C0A000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_M_CK_ABUS_REG (0xA7C0C000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_M_HALF_CK_ABUS_REG (0xA7C0E000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_CK_ABUS_REG (0xA7C10000)
+#define BASE_MADDR_RXCPC_NR_MML1_RXCPC_HALF_CK_ABUS_REG (0xA7C12000)
+#define BASE_MADDR_RXCPC_NR_RESERVED0 (0xA7C14000)
+#define BASE_MADDR_RXCPC_NR_RESERVED1 (0xA7C16000)
+#define BASE_MADDR_RXCPC_NR_RXCPC_NR_CFG_SP (0xA7C20000)
+// (22): MAP_modeml1_ao
+#define BASE_MADDR_MODEML1_AO_MODEML1_TOPSM (0xA8000000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xA8010000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG (0xA8020000)
+#define BASE_MADDR_MODEML1_AO_TDMA_SLP (0xA8030000)
+#define BASE_MADDR_MODEML1_AO_TDD_SLP (0xA8040000)
+#define BASE_MADDR_MODEML1_AO_TDD_TIMER (0xA8050000)
+#define BASE_MADDR_MODEML1_AO_FDD_SLP (0xA8060000)
+#define BASE_MADDR_MODEML1_AO_FDD_TIMER (0xA8070000)
+#define BASE_MADDR_MODEML1_AO_LTE_SLP (0xA8080000)
+#define BASE_MADDR_MODEML1_AO_LTE_TIMER (0xA8090000)
+#define BASE_MADDR_MODEML1_AO_IDC_CTRL (0xA80A0000)
+#define BASE_MADDR_MODEML1_AO_IDC_UART (0xA80B0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_TIMER (0xA80C0000)
+#define BASE_MADDR_MODEML1_AO_C2K_1X_SLP (0xA80D0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_TIMER (0xA80E0000)
+#define BASE_MADDR_MODEML1_AO_C2K_DO_SLP (0xA80F0000)
+#define BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xA8100000)
+#define BASE_MADDR_MODEML1_AO_MD_DVFS_TOP_CONFIG (0xA8110000)
+#define BASE_MADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xA8120000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM (0xA8130000)
+#define BASE_MADDR_MODEML1_AO_BSI_MM_MIPI (0xA8140000)
+#define BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xA8150000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MAS_BUS_CONFIG (0xA8160000)
+#define BASE_MADDR_MODEML1_AO_BPI_MM (0xA8170000)
+#define BASE_MADDR_MODEML1_AO_C1X_TTR (0xA8180000)
+#define BASE_MADDR_MODEML1_AO_CDO_TTR (0xA8190000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG (0xA81A0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xA81B0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xA81B8000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_FREQM (0xA81C0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xA81D0000)
+#define BASE_MADDR_MODEML1_AO_MM_EVENTGEN (0xA81E0000)
+#define BASE_MADDR_MODEML1_AO_MDAO_SMI (0xA81F0000)
+#define BASE_MADDR_MODEML1_AO_C1XEVT (0xA8200000)
+#define BASE_MADDR_MODEML1_AO_CDOEVT (0xA8210000)
+#define BASE_MADDR_MODEML1_AO_FDDEVT (0xA8220000)
+#define BASE_MADDR_MODEML1_AO_LTEEVT (0xA8230000)
+#define BASE_MADDR_MODEML1_AO_TDDEVT (0xA8240000)
+#define BASE_MADDR_MODEML1_AO_UCNT_D (0xA8250000)
+#define BASE_MADDR_MODEML1_AO_NR_TIMER (0xA8260000)
+#define BASE_MADDR_MODEML1_AO_NR_SLP (0xA8270000)
+#define BASE_MADDR_MODEML1_AO_NR_EVENTGEN (0xA8280000)
+#define BASE_MADDR_MODEML1_AO_TDMA_TMR (0xA8290000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 (0xA82A0000)
+#define BASE_MADDR_MODEML1_AO_RF_SLP_CTRL (0xA82B0000)
+#define BASE_MADDR_MODEML1_AO_U_DFESYS_MEM_CONFIG (0xA82C0000)
+#define BASE_MADDR_MODEML1_AO_DIGRF_MIPI_1 (0xA82D0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xA82E0000)
+#define BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xA82F0000)
+#define BASE_MADDR_MODEML1_AO_U_MMW_TXDFE_MEM_CONFIG (0xA8300000)
+#define BASE_MADDR_MODEML1_AO_MD_GLOBAL_CON_DCM (0xA0130000)
+#define BASE_MADDR_MODEML1_AO_MD_PLLMIXED (0xA0140000)
+#define BASE_MADDR_MODEML1_AO_MD_CLKSW (0xA0150000)
+// (23): MAP_md2gsys
+#define BASE_MADDR_MD2GSYS_IDMA_CM (0xA8400000)
+#define BASE_MADDR_MD2GSYS_IDMA_PM (0xA8500000)
+#define BASE_MADDR_MD2GSYS_IDMA_DM (0xA8600000)
+#define BASE_MADDR_MD2GSYS_MD2G_CONFG (0xA8700000)
+#define BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG (0xA8710000)
+#define BASE_MADDR_MD2GSYS_TDMA_BASE (0xA8720000)
+#define BASE_MADDR_MD2GSYS_APC (0xA8730000)
+#define BASE_MADDR_MD2GSYS_CSD_ACC (0xA8770000)
+#define BASE_MADDR_MD2GSYS_SHARE_D1 (0xA87A0000)
+#define BASE_MADDR_MD2GSYS_IRDBG (0xA87B0000)
+#define BASE_MADDR_MD2GSYS_PATCH (0xA87C0000)
+#define BASE_MADDR_MD2GSYS_AHB2DSPIO (0xA87F0000)
+// (24): MAP_dfesys
+#define BASE_MADDR_DFESYS_TXBSRP (0xA8800000)
+#define BASE_MADDR_DFESYS_TXCRP (0xA8900000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG0 (0xA8980000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG0 (0xA8990000)
+#define BASE_MADDR_DFESYS_RESERVED0 (0xA89A0000)
+#define BASE_MADDR_DFESYS_TPC_D (0xA8A00000)
+#define BASE_MADDR_DFESYS_TXDFE_D (0xA8A80000)
+#define BASE_MADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xA8A90000)
+#define BASE_MADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xA8AA0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG0 (0xA8AB0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG1 (0xA8AC0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG2 (0xA8AD0000)
+#define BASE_MADDR_DFESYS_TXDFE_BB_REG3 (0xA8AE0000)
+#define BASE_MADDR_DFESYS_RESERVED1 (0xA8AF0000)
+#define BASE_MADDR_DFESYS_RESERVED2 (0xA8B00000)
+#define BASE_MADDR_DFESYS_RESERVED3 (0xA8B10000)
+#define BASE_MADDR_DFESYS_FDD_TTR (0xA8B20000)
+#define BASE_MADDR_DFESYS_TDD_TTR (0xA8B30000)
+#define BASE_MADDR_DFESYS_LTE_TTR (0xA8B40000)
+#define BASE_MADDR_DFESYS_LTE_TTR1 (0xA8B50000)
+#define BASE_MADDR_DFESYS_LTE_TTR2 (0xA8B60000)
+#define BASE_MADDR_DFESYS_RESERVED4 (0xA8B70000)
+#define BASE_MADDR_DFESYS_RESERVED5 (0xA8B80000)
+#define BASE_MADDR_DFESYS_NR_TTR (0xA8B90000)
+#define BASE_MADDR_DFESYS_NR_TTR1 (0xA8BA0000)
+#define BASE_MADDR_DFESYS_NR_TTR2 (0xA8BB0000)
+#define BASE_MADDR_DFESYS_NR_TTR3 (0xA8BC0000)
+#define BASE_MADDR_DFESYS_GLB_CON_CONFIG1 (0xA8BD0000)
+#define BASE_MADDR_DFESYS_MBIST_REPAIR_CFG (0xA8BE0000)
+#define BASE_MADDR_DFESYS_BUS_CONFIG1 (0xA8BF0000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES (0xA8C00000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L2 (0xA8C10000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L15 (0xA8C20000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_L1 (0xA8C30000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_MISC (0xA8C40000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_COS (0xA8C50000)
+#define BASE_MADDR_DFESYS_RXDFE_BB (0xA8C60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC0 (0xA8C70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC1 (0xA8C80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TC2 (0xA8C90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_MS (0xA8CA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_FC (0xA8CB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DUMP (0xA8CC0000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB1 (0xA8CD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CQ1 (0xA8CE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_DMA (0xA8CF0000)
+#define BASE_MADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xA8D00000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE0 (0xA8D10000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE1 (0xA8D20000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE2 (0xA8D30000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE3 (0xA8D40000)
+#define BASE_MADDR_DFESYS_RXDFE_PCC_BB0 (0xA8D50000)
+#define BASE_MADDR_DFESYS_RXDFE_MRSG_BB (0xA8D60000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE0 (0xA8D70000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_BFE1 (0xA8D80000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xA8D90000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xA8DA0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CS_SEL (0xA8DB0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xA8DC0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xA8DD0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_CORE4 (0xA8DE0000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_1 (0xA8DF0000)
+#define BASE_MADDR_DFESYS_DFE_COMDMA (0xA8E00000)
+#define BASE_MADDR_DFESYS_RESERVED6 (0xA8E10000)
+#define BASE_MADDR_DFESYS_RESERVED7 (0xA8E20000)
+#define BASE_MADDR_DFESYS_RESERVED8 (0xA8E30000)
+#define BASE_MADDR_DFESYS_RESERVED9 (0xA8E40000)
+#define BASE_MADDR_DFESYS_RESERVED10 (0xA8E50000)
+#define BASE_MADDR_DFESYS_COS_POST_WB (0xA8E60000)
+#define BASE_MADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xA8E70000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_1 (0xA8E80000)
+#define BASE_MADDR_DFESYS_DIGBB_SERDES_2 (0xA8E88000)
+#define BASE_MADDR_DFESYS_RXDFE_BB_TOP_2 (0xA8E90000)
+#define BASE_MADDR_DFESYS_RESERVED11 (0xA8EA0000)
+#define BASE_MADDR_DFESYS_MAS_BUS_INTF (0xA8EB0000)
+#define BASE_MADDR_DFESYS_SLV_BUS_INTF (0xA8EC0000)
+// (25): Serdes(A Die)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP (0xA9418000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xA941C000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xA9410000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xA9414000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xA9416000)
+#define BASE_MADDR_DIGRF_TX_TOP_TPC_A (0xA9180000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xA9400000)
+#define BASE_MADDR_DIGRF_TX_TOP_TXDFE_TQ (0xA94A0000)
+#define BASE_MADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xA94B0000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC (0xA9298000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xA9170000)
+#define BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xA92E0000)
+// (26): MAP_cssys
+#define BASE_MADDR_CSSYS_CS (0xA9800000)
+#define BASE_MADDR_CSSYS_LTE_CS (0xA9810000)
+#define BASE_MADDR_CSSYS_MBIST_CON (0xA9820000)
+#define BASE_MADDR_CSSYS_CSSYS_BUS_CONFIG (0xA9830000)
+#define BASE_MADDR_CSSYS_CSSYS_BUS_DIV2_CONFIG (0xA9838000)
+#define BASE_MADDR_CSSYS_MDAO_BUS_CONFIG (0xA983C000)
+#define BASE_MADDR_CSSYS_CS_DEBUG (0xA9840000)
+#define BASE_MADDR_CSSYS_1X_CS (0xA9850000)
+#define BASE_MADDR_CSSYS_CS_WT (0xA9860000)
+#define BASE_MADDR_CSSYS_CSSYS_CS_WT1 (0xA9870000)
+#define BASE_MADDR_CSSYS_EVDO_CS (0xA9880000)
+// (27): MAP_cs_nr
+#define BASE_MADDR_CS_NR_CS_NR_TOP_REG (0xA9C00000)
+#define BASE_MADDR_CS_NR_CS_NR_CSFSM_REG (0xA9C10000)
+#define BASE_MADDR_CS_NR_CS_NR_SCN_RPT (0xA9C20000)
+#define BASE_MADDR_CS_NR_CS_NR_HEIF_REG (0xA9C30000)
+#define BASE_MADDR_CS_NR_CS_NR_BUS_CONFIG (0xA9C40000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xA9C50000)
+#define BASE_MADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xA9C58000)
+#define BASE_MADDR_CS_NR_CM_CS_BUS_CONFIG (0xA9C60000)
+// (28): MAP_cm_cs_nr_ao
+#define BASE_MADDR_CMCS_PAR_AO_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xADC00000)
+#define BASE_MADDR_CMCS_PAR_AO_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xADC10000)
+#define BASE_MADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG (0xADC20000)
+#define BASE_MADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG (0xADC30000)
+#define BASE_MADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG (0xADC40000)
+#define BASE_MADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO (0xADC50000)
+#define BASE_MADDR_CMCS_PAR_AO_MCORE_PAR_AO_REG (0xADC50400)
+#define BASE_MADDR_CMCS_PAR_AO_U_VCORE_PAR_WRAP_SRAM_AO (0xADC60000)
+#define BASE_MADDR_CMCS_PAR_AO_U_VCORE_PAR_AO_CR (0xADC60400)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_0_SM_CONFIG (0xADC60600)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_1_SM_CONFIG (0xADC60680)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_2_SM_CONFIG (0xADC60700)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_3_SM_CONFIG (0xADC60780)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_4_SM_CONFIG (0xADC60800)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_5_SM_CONFIG (0xADC60880)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_6_SM_CONFIG (0xADC60900)
+#define BASE_MADDR_CMCS_PAR_AO_U_VU_7_SM_CONFIG (0xADC60980)
+#define BASE_MADDR_CMCS_PAR_AO_U_GRAM_MEM_CONFIG (0xADC70000)
+#define BASE_MADDR_CMCS_PAR_AO_U_TX_NR_MEM_CONFIG (0xADC80000)
+#define BASE_MADDR_CMCS_PAR_AO_U_CMCS_NR_MEM_CONFIG (0xADC90000)
+#define BASE_MADDR_CMCS_PAR_AO_U_CMCS_PAR_AO_CONFIG_REG (0xADCA0000)
+// (29): MAP_txsys_nr
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xAA000000)
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xAA008000)
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xAA010000)
+#define BASE_MADDR_TXSYS_NR_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xAA018000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xAA020000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xAA030000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_2 (0xAA040000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_3 (0xAA050000)
+#define BASE_MADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_4 (0xAA060000)
+#define BASE_MADDR_TXSYS_NR_TXBSRP_GLB_APB_CONFIG (0xAA070000)
+#define BASE_MADDR_TXSYS_NR_TXBSRP_BIT_CONTROLLER (0xAA080000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xAA100000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG (0xAA101000)
+#define BASE_MADDR_TXSYS_NR_RESERVED0 (0xAA102000)
+#define BASE_MADDR_TXSYS_NR_TX_NR_PAR_AO_CONFIG_REG (0xAA10C000)
+#define BASE_MADDR_TXSYS_NR_RESERVED1 (0xAA10D000)
+#define BASE_MADDR_TXSYS_NR_RESERVED2 (0xAA10E000)
+// (30): MAP_cm_nr
+#define BASE_MADDR_CM_NR_CM_NR_GLOBAL_CON (0xAA400000)
+#define BASE_MADDR_CM_NR_CM_NR_MBIST_WRAP (0xAA410000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_0 (0xAA420000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_DVTCRC (0xAA430000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH (0xAA440000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_1 (0xAA450000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_DVTCRC_1 (0xAA460000)
+#define BASE_MADDR_CM_NR_CM_NR_PBCH_1 (0xAA470000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_2 (0xAA480000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB_SSS (0xAA490000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB_SSS (0xAA4A0000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP_SSS (0xAA4B0000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT_SSS (0xAA4C0000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_SSS (0xAA4D0000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL_SSS (0xAA4E0000)
+#define BASE_MADDR_CM_NR_CM_NR_DVTCRC_SSS (0xAA4F0000)
+#define BASE_MADDR_CM_NR_CM_NR_TDB_CSIRS (0xAA500000)
+#define BASE_MADDR_CM_NR_CM_NR_FDB_CSIRS (0xAA510000)
+#define BASE_MADDR_CM_NR_CM_NR_RSSIRSRP_CSIRS (0xAA520000)
+#define BASE_MADDR_CM_NR_CM_NR_REPORT_CSIRS (0xAA530000)
+#define BASE_MADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_CSIRS (0xAA540000)
+#define BASE_MADDR_CM_NR_CM_NR_TD_CTRL_CSIRS (0xAA550000)
+#define BASE_MADDR_CM_NR_CM_NR_DVTCRC_CSIRS (0xAA560000)
+#define BASE_MADDR_CM_NR_CM_NR_RESERVED_3 (0xAA570000)
+#define BASE_MADDR_CM_NR_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xAA580000)
+#define BASE_MADDR_CM_NR_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xAA590000)
+// (31): MAP_rxtfc
+#define BASE_MADDR_RXTFC_RXTFC_NR (0xAA800000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_TOP_1 (0xAA810000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xAA820000)
+#define BASE_MADDR_RXTFC_RESERVED0 (0xAA830000)
+#define BASE_MADDR_RXTFC_RESERVED1 (0xAA840000)
+#define BASE_MADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xAA850000)
+#define BASE_MADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xAA860000)
+#define BASE_MADDR_RXTFC_RESERVED2 (0xAA870000)
+#define BASE_MADDR_RXTFC_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xAA880000)
+#define BASE_MADDR_RXTFC_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xAA890000)
+// (32): Sheet42
+// (33): MAP_rxtdb
+#define BASE_MADDR_RXTDB_RXTDB_NR (0xAAC00000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_1 (0xAAC10000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xAAC20000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_2 (0xAAC30000)
+#define BASE_MADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xAAC40000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xAAC50000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xAAC60000)
+#define BASE_MADDR_RXTDB_RXTDB_NR_TOP_3 (0xAAC70000)
+#define BASE_MADDR_RXTDB_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xAAC80000)
+#define BASE_MADDR_RXTDB_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xAAC90000)
+// (34): MAP_rxtdb_pbch
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR (0xAAE00000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xAAE10000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xAAE20000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xAAE30000)
+#define BASE_MADDR_RXTDB_PBCH_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xAAE40000)
+#define BASE_MADDR_RXTDB_PBCH_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xAAE50000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xAAE60000)
+#define BASE_MADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xAAE70000)
+// (35): MAP_bigram
+#define BASE_MADDR_BIGRAM0_BIGRAM_MEM (0xAB000000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xAB800000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xAB808000)
+#define BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_D2BIF (0xAB820000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_REG (0xAB830000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BRIDGE (0xAB840000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_RXT2F (0xAB850000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BR_DMA (0xAB860000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xAB870000)
+#define BASE_MADDR_BIGRAM0_BIGRAM_BUS_CONFIG (0xAB880000)
+#define BASE_MADDR_BIGRAM0_INR_SLV_BUS_CONFIG (0xAB890000)
+// (36): MAP_inr
+#define BASE_MADDR_INR0_MEM (0xABA00000)
+#define BASE_MADDR_INR0_RESERVED0 (0xABB00000)
+#define BASE_MADDR_INR0_SHARED_DM (0xABB40000)
+#define BASE_MADDR_INR0_RESERVED1 (0xABB80000)
+#define BASE_MADDR_INR0_RESERVED2 (0xABC00000)
+#define BASE_MADDR_INR0_REGISTERS (0xABC10000)
+#define BASE_MADDR_INR0_SCQ_SEMAPHORE (0xABC11000)
+#define BASE_MADDR_INR0_SCQ_GLOBAL_CON (0xABC12000)
+#define BASE_MADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xABC13000)
+#define BASE_MADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xABC13800)
+#define BASE_MADDR_INR0_VU_MBIST_DELSEL_CFG (0xABC14000)
+#define BASE_MADDR_INR0_VU_MBIST_REPAIR_CFG (0xABC14800)
+#define BASE_MADDR_INR0_RESERVED3 (0xABC15000)
+#define BASE_MADDR_INR0_RESERVED4 (0xABD00000)
+#define BASE_MADDR_INR0_LOCAL_DM (0xABE00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB (0xABE08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR (0xABE09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR (0xABE0A000)
+#define BASE_MADDR_INR0_MEM__REGISTER (0xABE0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE (0xABE0C000)
+#define BASE_MADDR_INR0_RESERVED5 (0xABE0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_1 (0xABF00000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_1 (0xABF08000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_1 (0xABF09000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_1 (0xABF0A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF (0xABF0B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_1 (0xABF0C000)
+#define BASE_MADDR_INR0_RESERVED6 (0xABF0D000)
+#define BASE_MADDR_INR0_LOCAL_DM_2 (0xAC000000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_2 (0xAC008000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_2 (0xAC009000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_2 (0xAC00A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_1 (0xAC00B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_2 (0xAC00C000)
+#define BASE_MADDR_INR0_RESERVED7 (0xAC00D000)
+#define BASE_MADDR_INR0_LOCAL_DM_3 (0xAC100000)
+#define BASE_MADDR_INR0_SCQ_DSPLOG_1PB_3 (0xAC108000)
+#define BASE_MADDR_INR0_SCQ_VU_CR_3 (0xAC109000)
+#define BASE_MADDR_INR0_SCQ_MBIST_CR_3 (0xAC10A000)
+#define BASE_MADDR_INR0_SCQ_MD32_TBUF_2 (0xAC10B000)
+#define BASE_MADDR_INR0_SCQ_DCACHE_3 (0xAC10C000)
+#define BASE_MADDR_INR0_RESERVED8 (0xAC10D000)
+#define BASE_MADDR_INR0_RESERVED9 (0xAC200000)
+// (37): MAP_rxbrp
+#define BASE_MADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xAC800000)
+#define BASE_MADDR_RXBRP0_DMC_MBIST_CONFIG (0xAC810000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_DRM (0xAC820000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_R99_WRAP (0xAC830000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_1XRTT (0xAC840000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_CORR_SER (0xAC850000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_BCH (0xAC860000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DVIT (0xAC870000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TRACE (0xAC900000)
+#define BASE_MADDR_RXBRP0_RXBRP_GLOBAL_CON (0xAC910000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_TUR (0xAC920000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_CVIT (0xAC930000)
+#define BASE_MADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xAC940000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCT_DMA (0xAC950000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_MAS_HALF_CK_ABUS_REG (0xAC960000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_HARQ (0xAC970000)
+#define BASE_MADDR_RXBRP0_RXBRP_WT_CDRM (0xAC980000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_MAS_CK_ABUS_REG (0xAC990000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_SLV_HALF_CK_ABUS_REG (0xAC9A0000)
+#define BASE_MADDR_RXBRP0_MML1_RXBRP_SLV_CK_ABUS_REG (0xAC9B0000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_CORR (0xACA00000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_TXIF (0xACA10000)
+#define BASE_MADDR_RXBRP0_RXBRP_W_HSRM (0xACA20000)
+#define BASE_MADDR_RXBRP0_RXBRP_C_EVDO (0xACA30000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DBRP (0xACA40000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP (0xACA50000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_HARQ (0xACA60000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_REBRP (0xACA70000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_RBMAP (0xACA80000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xACA90000)
+#define BASE_MADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xACAA0000)
+#define BASE_MADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xACAB0000)
+#define BASE_MADDR_RXBRP0_DMC (0xACB00000)
+#define BASE_MADDR_RXBRP0_DMC_PERI (0xACB10000)
+#define BASE_MADDR_RXBRP0_LTE_CE_SC (0xACB20000)
+#define BASE_MADDR_RXBRP0_LTE_CE_OC1 (0xACB21000)
+#define BASE_MADDR_RXBRP0_LTE_CE_OC2 (0xACB22000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_PDSCH (0xACB30000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_PDCCH (0xACB33000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_EPDCCH (0xACB34000)
+#define BASE_MADDR_RXBRP0_DEMOD_TOP_PBCH (0xACB35000)
+#define BASE_MADDR_RXBRP0_DMC_MIMO (0xACB40000)
+#define BASE_MADDR_RXBRP0_DMC_PWR_MEAS (0xACB50000)
+// (38): MAP_rake
+#define BASE_MADDR_RAKESYS_RAKE_INST_DEC (0xACC00000)
+#define BASE_MADDR_RAKESYS_RAKE_LOADER (0xACC20000)
+#define BASE_MADDR_RAKESYS_RAKE_DESP (0xACC30000)
+#define BASE_MADDR_RAKESYS_RAKE_SEEDGEN (0xACC40000)
+#define BASE_MADDR_RAKESYS_RAKE_EXT (0xACC50000)
+#define BASE_MADDR_RAKESYS_RAKE_R2B_DMA (0xACC60000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_ACC (0xACC70000)
+#define BASE_MADDR_RAKESYS_RAKE_FCE (0xACC80000)
+#define BASE_MADDR_RAKESYS_RAKE_DESIG (0xACC90000)
+#define BASE_MADDR_RAKESYS_RAKE_R2TX_DHWIF (0xACCA0000)
+#define BASE_MADDR_RAKESYS_RAKE_CPICH_INTF (0xACCF0000)
+#define BASE_MADDR_RAKESYS_RAKE_BRIF (0xACD00000)
+#define BASE_MADDR_RAKESYS_RAKE_UNITTEST (0xACD10000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON (0xACE00000)
+#define BASE_MADDR_RAKESYS_MBIST_DELSEL_CFG (0xACE10000)
+#define BASE_MADDR_RAKESYS_MBIST_REPAIR_CFG (0xACE18000)
+#define BASE_MADDR_RAKESYS_GLOBAL_CON_L1DBG (0xACF00000)
+#define BASE_MADDR_RAKESYS_DSP_SW_LOGGER (0xACF40000)
+#define BASE_MADDR_RAKESYS_CIRQ (0xACF50000)
+#define BASE_MADDR_RAKESYS_PERICTRL (0xACF51000)
+#define BASE_MADDR_RAKESYS_TRACE_BUF (0xACF54000)
+#define BASE_MADDR_RAKESYS_CMIF (0xACF58000)
+#define BASE_MADDR_RAKESYS_PM (0xACF80000)
+#define BASE_MADDR_RAKESYS_RAKE_PM_ARB (0xACF90000)
+#define BASE_MADDR_RAKESYS_PM_ARB_2 (0xACFA0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_3 (0xACFB0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_4 (0xACFC0000)
+#define BASE_MADDR_RAKESYS_DM (0xACFD0000)
+#define BASE_MADDR_RAKESYS_RAKE_DM_ARB (0xACFE0000)
+#define BASE_MADDR_RAKESYS_PM_ARB_6 (0xACFF0000)
+// (39): MAP_mmw_rf_ctrl
+#define BASE_MADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_SRAM_CTRL_AO (0xAD000000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_MMW_DBB_CTRLACNT (0xAD001000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_GLOBAL_CON_AO (0xAD002000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_RESERVED0 (0xAD003000)
+#define BASE_MADDR_MMW_RF_CTRL_AO_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xAD010000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RFAC (0xAD020000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CM_DATA_INTF (0xAD040000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_EVENTGEN (0xAD050000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED1 (0xAD060000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xAD080000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_LOG (0xAD090000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_COMDMA (0xAD0A0000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_CONTROLLER (0xAD0B0000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD (0xAD0B8000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_1 (0xAD0B8100)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_2 (0xAD0B8200)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED2 (0xAD0B8300)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_MBIST (0xAD0B9000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_GLOBAL_CON (0xAD0BA000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED3 (0xAD0BB000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_CM_COMM_REG (0xAD0F8000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG (0xAD0F8400)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_1 (0xAD0F8800)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_2 (0xAD0F8C00)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED4 (0xAD0F9000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_TOP (0xAD100000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_LOG (0xAD108000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_SCH (0xAD110000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xAD120000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED5 (0xAD130000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BPI (0xAD180000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_DIGRF_MIPI_M (0xAD190000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_TOP (0xAD200000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SCH (0xAD210000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI0 (0xAD218000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI1 (0xAD219000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI2 (0xAD21A000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI3 (0xAD21B000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI4 (0xAD21C000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI5 (0xAD21D000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI6 (0xAD21E000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI7 (0xAD21F000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xAD220000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED6 (0xAD230000)
+#define BASE_MADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED7 (0xAD300000)
+// (40): MAP_mmw_txdfe
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_RESERVED0 (0xAD400000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_RESERVED1 (0xAD640000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TOP_CTRL (0xAD410000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_TXK (0xAD420000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_GLOBAL_CON (0xAD430000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BUS_CONFIG (0xAD440000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_MBIST_CONFIG_CAT (0xAD450000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TX_ACNT_TICK_GEN (0xAD460000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TQ (0xAD470000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR (0xAD480000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_1 (0xAD490000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_2 (0xAD4A0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_3 (0xAD4B0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_4 (0xAD4C0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_5 (0xAD4D0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_6 (0xAD4E0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_7 (0xAD4F0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D (0xAD500000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_1 (0xAD510000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_2 (0xAD520000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_3 (0xAD530000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_4 (0xAD540000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_5 (0xAD550000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_6 (0xAD560000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_7 (0xAD570000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_8 (0xAD580000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_9 (0xAD590000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_A (0xAD5A0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF (0xAD5B0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_1 (0xAD5C0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_2 (0xAD5D0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_3 (0xAD5E0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_ABB_MIXEDSYS (0xAD5F0000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MRX_DATA_DUMP (0xAD600000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_PCC_BB (0xAD610000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_U_MMW_PCC_BB_TOP_1 (0xAD620000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_LOG (0xAD660000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE0_COMDMA (0xAD670000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE1_COMDMA (0xAD680000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_MML1_MMW_TPC_468M_CK_ABUS_REG (0xAD690000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_TPC_M (0xAD700000)
+#define BASE_MADDR_MMW_TXDFE_PWR_WRAP_TPC_M_1 (0xAD780000)
+// (41): MAP_mmw_rxdfe
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER (0xAD800000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER_RESERVED0 (0xAD804000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_EVTGEN (0xAD808000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_SLPC (0xAD80C000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_RESERVED1 (0xAD810000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_PAR_WRAP_SRAM_AO (0xAD820000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_CONFIG_AO_REG (0xAD821000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX0 (0xAD828000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX1 (0xAD829000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX2 (0xAD82A000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX3 (0xAD82B000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX0 (0xAD82C000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX1 (0xAD82D000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_SYS (0xAD82E000)
+#define BASE_MADDR_MMW_RXDFE_PAR_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xAD830000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CONFIG_REG (0xAD840000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MBIST_CAT_MBIST_TOP_CFG (0xAD844000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xAD850000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_RXDFE_BB_NR_MMW_DM_SEL_WRAP (0xAD860000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CS_SEL_WRAP (0xAD870000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_CMSEL_MMW (0xAD880000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_CMIPG_MMW (0xAD888000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_LOG (0xAD890000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MRSG (0xAD8A0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE0_COMDMA (0xAD8C0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_DMA_DESCRT (0xAD8D0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_0 (0xAD8F0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_1 (0xAD8F8000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_0 (0xAD900000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_0 (0xAD920000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_1 (0xAD920200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_2 (0xAD920400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_3 (0xAD920600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_4 (0xAD920800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_5 (0xAD920A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_6 (0xAD920C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_7 (0xAD920E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_0 (0xAD922000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_1 (0xAD922200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_2 (0xAD922400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_3 (0xAD922600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_4 (0xAD922800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_5 (0xAD922A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_6 (0xAD922C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_7 (0xAD922E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ1 (0xAD924000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_WM (0xAD92A000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TOT_PATT (0xAD92E000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_2 (0xAD940000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_2 (0xAD960000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_1 (0xAD980000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_0 (0xAD9A0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_1 (0xAD9A0200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_2 (0xAD9A0400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_3 (0xAD9A0600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_4 (0xAD9A0800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_5 (0xAD9A0A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_6 (0xAD9A0C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_7 (0xAD9A0E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_0 (0xAD9A2000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_1 (0xAD9A2200)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_2 (0xAD9A2400)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_3 (0xAD9A2600)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_4 (0xAD9A2800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_5 (0xAD9A2A00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_6 (0xAD9A2C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_7 (0xAD9A2E00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ1 (0xAD9A4000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_WM (0xAD9AA000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TOT_PATT (0xAD9AE000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_MBIST_CONFIG (0xAD9C0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_GLBCON (0xAD9F0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_SET (0xADA00000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_HEADER (0xADA04000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_STATUS (0xADA08000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_P_REG (0xADA10000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_L_REG (0xADA20000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_IMM_REG (0xADA30000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_P_REG (0xADA40000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_L_REG (0xADA50000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CS_AGC (0xADA60000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_468 (0xADA70000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_52 (0xADA71000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_0 (0xADA71800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_1 (0xADA71C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC (0xADA80000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_1 (0xADA84000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_2 (0xADA88000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_3 (0xADA90000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_4 (0xADAA0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_5 (0xADAB0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_6 (0xADAC0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_7 (0xADAD0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_8 (0xADAE0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_468 (0xADAF0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_52 (0xADAF1000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_0 (0xADAF1800)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_1 (0xADAF1C00)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xADAFF000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_DM (0xADB00000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD0_PM (0xADBA0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD1_PM (0xADBB0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_COREDBG (0xADBD0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_GC_PM (0xADBE0000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE1_COMDMA (0xADBFE000)
+#define BASE_MADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ADC_TEST_ARBITOR (0xADBFF000)
+ ////////////////////
+#define BASE_NADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_NADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_NADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_NADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_NADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_NADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_NADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_NADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_NADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_NADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_NADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_NADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_NADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_NADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_NADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_NADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_NADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_NADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_NADDR_MDPERI_MDL1_MODEM_TOPSM_PROTECT (0xB0080000)
+#define BASE_NADDR_MDPERI_COMDMA (0xB0090000)
+#define BASE_NADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_NADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_NADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_NADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_NADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_NADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_NADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_NADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_NADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_NADDR_MDPERI_MDRXSYS_SRAM_AO (0xB0190000)
+#define BASE_NADDR_MDPERI_VU_SM_CONGIF_0 (0xB0191000)
+#define BASE_NADDR_MDPERI_VU_SM_CONGIF_1 (0xB0192000)
+#define BASE_NADDR_MDPERI_MDRXAO_CONFIG (0xB0193000)
+#define BASE_NADDR_MDPERI_RESERVED0 (0xB0194000)
+#define BASE_NADDR_MDPERI_BRP_SRAM_AO (0xB01A0000)
+#define BASE_NADDR_MDPERI_NRL2_SRAM_AO (0xB01B0000)
+#define BASE_NADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_NADDR_MDPERI_MDSYS_SRAM_AO (0xB01D0000)
+#define BASE_NADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_NADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_NADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_NADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_NADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_NADDR_MDINFRA_BUS2X_REG (0xB0440000)
+#define BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_NADDR_MDINFRA_SHAOLIN_SEMAPHORE (0xB0460000)
+#define BASE_NADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_NADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_NADDR_MDINFRA_BUS4X_REG (0xB04B0000)
+#define BASE_NADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_NADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_NADDR_MDINFRA_HW_LOG (0xB0500000)
+#define BASE_NADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_NADDR_MDINFRA_TRACE (0xB0540000)
+#define BASE_NADDR_MDINFRA_TRACE_NR_TOP_1 (0xB0550000)
+#define BASE_NADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_NADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_AO_MISC_CTRL (0xB0260000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_SRAM_AO (0xB0270000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_MEM_DELSEL_CFG (0xB0280000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_MEM_DELSEL_CFG (0xB0281000)
+#define BASE_NADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE1_MEM_DELSEL_CFG (0xB0282000)
+#define BASE_NADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE2_MEM_DELSEL_CFG (0xB0283000)
+#define BASE_NADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE3_MEM_DELSEL_CFG (0xB0284000)
+#define BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_CONFIG (0xB02C0000)
+#define BASE_NADDR_MDMCU_SHAOLIN__BUSMPU_INFRA (0xB02D0000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_NADDR_MDCORESYS_MDMCU_COREBUS_INTF_CFG (0xB0330000)
+#define BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0340000)
+#define BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_NADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_NADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_NADDR_MDCORESYS_IA_MACRO_DELSEL_ADR_IF (0xB03B0000)
+#define BASE_NADDR_MDCORESYS_MDCORESYS_MBIST_MDCORE_FOR_CFG_DELSEL_CFG_WRAP (0xB03B1000)
+#define BASE_NADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_NADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_NADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_NADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_NADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_NADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_NADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_NADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_NADDR_USIP_MBIST_REPAIR_TOP_CFG_WRAP (0xB0D10000)
+#define BASE_NADDR_USIP_MBIST_DELSEL_TOP_CFG_WRAP (0xB0D20000)
+#define BASE_NADDR_USIP_USIPCORE_BUS_CONFIG (0xB0D30000)
+#define BASE_NADDR_USIP_CONFG (0xB0E00000)
+#define BASE_NADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_NADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_NADDR_USIP_AFE (0xB0E40000)
+#define BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_NADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_NADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_NADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_NADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_NADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_NADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_NADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_NADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_NADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_NADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_NADDR_NRL2_ROHC (0xB200C000)
+#define BASE_NADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_NADDR_NRL2_NRL2_UL_CIPHER_CONFIG (0xB2014000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG (0xB2018000)
+#define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_NADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_NADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_NADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_NADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_NADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_NADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_NADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_NADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_1 (0xB2036000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_2 (0xB2037000)
+#define BASE_NADDR_NRL2_NRL2_METADATA_MNG_SRAM (0xB2038000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_4 (0xB2039000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_ST (0xB203A000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_0 (0xB203B000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_1 (0xB203C000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_2 (0xB203D000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_3 (0xB203E000)
+#define BASE_NADDR_NRL2_NRL2_DL_UPP_REASB_WB_4 (0xB203F000)
+#define BASE_NADDR_NRL2_NRL2_DL_META_AGG (0xB2040000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC2 (0xB2041000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC3 (0xB2042000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC4 (0xB2043000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC5 (0xB2044000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC6 (0xB2045000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC7 (0xB2046000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC8 (0xB2047000)
+#define BASE_NADDR_NRL2_NRL2_RDMA_UL_PPRO (0xB2048000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC2 (0xB2049000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC3 (0xB204A000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC4 (0xB204B000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC5 (0xB204C000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC6 (0xB204D000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC7 (0xB204E000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC8 (0xB204F000)
+#define BASE_NADDR_NRL2_NRL2_WDMA_UL_PPRO (0xB2050000)
+#define BASE_NADDR_NRL2_NRL2_BUS_CFG (0xB2051000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_PPRO_QP (0xB2052000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_0 (0xB2053000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_1 (0xB2054000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_2 (0xB2055000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_3 (0xB2056000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_4 (0xB2057000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_5 (0xB2058000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_6 (0xB2059000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_7 (0xB205A000)
+#define BASE_NADDR_NRL2_NRL2_NRUL_COTF_QP_8 (0xB205B000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC0 (0xB205C000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC1 (0xB205D000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC2 (0xB205E000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC3 (0xB205F000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC4 (0xB2060000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC5 (0xB2061000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC6 (0xB2062000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC7 (0xB2063000)
+#define BASE_NADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC8 (0xB2064000)
+#define BASE_NADDR_MCORE_MSYS_DSPM2VSCHEDULER (0xB4000000)
+#define BASE_NADDR_MCORE_MPERI_DSPCK_ABUS_REG (0xB4001000)
+#define BASE_NADDR_MCORE_MPERI_DBUS3_APB2DBUSCR_INST (0xB4002000)
+#define BASE_NADDR_MCORE_MML1_DSPM2DDMSCHEDULER (0xB4004000)
+#define BASE_NADDR_MCORE_MSYS_DSPCSIF (0xB4010000)
+#define BASE_NADDR_MCORE_MSYS_DSPMCORELOG (0xB4011000)
+#define BASE_NADDR_MCORE_MML1_DSPCBSCHEDULER (0xB4012000)
+#define BASE_NADDR_MCORE_MPERI_DSPCORECK_ABUS_REG (0xB4013000)
+#define BASE_NADDR_MCORE_MPERI_DBUS1_APB2DBUSCR_INST (0xB4014000)
+#define BASE_NADDR_MCORE_MPERI_A2D (0xB4016000)
+#define BASE_NADDR_MCORE_MPERI_DBUSRECORDER (0xB4017000)
+#define BASE_NADDR_MCORE_MSYS_DSPUSTIMER (0xB4018000)
+#define BASE_NADDR_MCORE_MSYS_PROFILING (0xB4019000)
+#define BASE_NADDR_MCORE_MML1_DSPMPPT (0xB401A000)
+#define BASE_NADDR_MCORE_MSYS_DSPBTDMA (0xB4021000)
+#define BASE_NADDR_MCORE_MSYS_DSPSWLA (0xB4022000)
+#define BASE_NADDR_MCORE_MPERI_DBUS2_APB2DBUSCR_INST (0xB4023000)
+#define BASE_NADDR_MCORE_MSYSY_GLBCON (0xB4030000)
+#define BASE_NADDR_MCORE_MSYS_DBGMON (0xB4031000)
+#define BASE_NADDR_MCORE_MPERI_PERICK_ABUS_REG (0xB4032000)
+#define BASE_NADDR_MCORE_MML1_MCOREPERI_ABUSMON (0xB4033000)
+#define BASE_NADDR_MCORE_MSYS_COMDMA (0xB4034000)
+#define BASE_NADDR_MCORE_MSYS_MBIST_CAT (0xB4040000)
+#define BASE_NADDR_MCORE_MCORE_L1_CACHE (0xB4100000)
+#define BASE_NADDR_MCORE_MCORE0_L1D_CACHE (0xB4101000)
+#define BASE_NADDR_MCORE_MCORE_CLKCTRL (0xB4102000)
+#define BASE_NADDR_MCORE_MCORE_EXCEPTION_CONTROLLER (0xB4103000)
+#define BASE_NADDR_MCORE_MCORE0_L1_PROFILING_UNIT (0xB4104000)
+#define BASE_NADDR_MCORE_MCORE_A2D (0xB4105000)
+#define BASE_NADDR_MCORE_MCORE0_A2D_128 (0xB4106000)
+#define BASE_NADDR_MCORE_MCORE_D2D (0xB4107000)
+#define BASE_NADDR_MCORE_MCORE_D2A (0xB4108000)
+#define BASE_NADDR_MCORE_DBUS_REG (0xB4109000)
+#define BASE_NADDR_MCORE_MSYS_ISRD (0xB4180000)
+#define BASE_NADDR_MCORE_MML1_DSPEINTC (0xB4181000)
+#define BASE_NADDR_MCORE_MSYS_DSPDBGC1 (0xB4182000)
+#define BASE_NADDR_MCORE_MSYS_DSPCTIWRAP (0xB4183000)
+#define BASE_NADDR_MCORE_MCORE_CORE (0xB4200000)
+#define BASE_NADDR_MCORE_MCORE_L0I_CACHE (0xB4210000)
+#define BASE_NADDR_MCORE_MCORE_DATA_CACHE (0xB4211000)
+#define BASE_NADDR_MCORE_MCORE_TIMER (0xB4212000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD0_EXCTRL (0xB4213000)
+#define BASE_NADDR_MCORE_MCORE_PC_MONITOR (0xB4214000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD0_PROFILING_UNIT (0xB4215000)
+#define BASE_NADDR_MCORE_MCORE_MBIST_CONFIG_WRAP (0xB4216000)
+#define BASE_NADDR_MCORE_MCORE_MCORE_CRIT_DBUS (0xB4217000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_SONIC (0xB4220000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_L0I_CACHE (0xB4230000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_L0D_CACHE (0xB4231000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_TIMER (0xB4232000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_EXCTRL (0xB4233000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_PC_MONITOR (0xB4234000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_PROFILING_UNIT (0xB4235000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_MBIST_CONFIG (0xB4236000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_DBUS_REG (0xB4237000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_SONIC (0xB4240000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_L0I_CACHE (0xB4250000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_L0D_CACHE (0xB4251000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_TIMER (0xB4252000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_EXCTRL (0xB4253000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_PC_MONITOR (0xB4254000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_PROFILING_UNIT (0xB4255000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_MBIST_CONFIG (0xB4256000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_DBUS_REG (0xB4257000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_SONIC (0xB4260000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_L0I_CACHE (0xB4270000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_L0D_CACHE (0xB4271000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_TIMER (0xB4272000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_EXCTRL (0xB4273000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_PC_MONITOR (0xB4274000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_PROFILING_UNIT (0xB4275000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_MBIST_CONFIG (0xB4276000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_DBUS_REG (0xB4277000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_SONIC (0xB4280000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_L0I_CACHE (0xB4290000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_L0D_CACHE (0xB4291000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_TIMER (0xB4292000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_EXCTRL (0xB4293000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_PC_MONITOR (0xB4294000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_PROFILING_UNIT (0xB4295000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_MBIST_CONFIG (0xB4296000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_DBUS_REG (0xB4297000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_SONIC (0xB42A0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_L0I_CACHE (0xB42B0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_L0D_CACHE (0xB42B1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_TIMER (0xB42B2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_EXCTRL (0xB42B3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_PC_MONITOR (0xB42B4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_PROFILING_UNIT (0xB42B5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_MBIST_CONFIG (0xB42B6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_DBUS_REG (0xB42B7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_SONIC (0xB42C0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_L0I_CACHE (0xB42D0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_L0D_CACHE (0xB42D1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_TIMER (0xB42D2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_EXCTRL (0xB42D3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_PC_MONITOR (0xB42D4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_PROFILING_UNIT (0xB42D5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_MBIST_CONFIG (0xB42D6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_DBUS_REG (0xB42D7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_SONIC (0xB42E0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_L0I_CACHE (0xB42F0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_L0D_CACHE (0xB42F1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_TIMER (0xB42F2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_EXCTRL (0xB42F3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_PC_MONITOR (0xB42F4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_PROFILING_UNIT (0xB42F5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_MBIST_CONFIG (0xB42F6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_DBUS_REG (0xB42F7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_SONIC (0xB4300000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_L0I_CACHE (0xB4310000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_L0D_CACHE (0xB4311000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_TIMER (0xB4312000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_EXCTRL (0xB4313000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_PC_MONITOR (0xB4314000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_PROFILING_UNIT (0xB4315000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_MBIST_CONFIG (0xB4316000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_DBUS_REG (0xB4317000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_SONIC (0xB4320000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_L0I_CACHE (0xB4330000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_L0D_CACHE (0xB4331000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_TIMER (0xB4332000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_EXCTRL (0xB4333000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_PC_MONITOR (0xB4334000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_PROFILING_UNIT (0xB4335000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_MBIST_CONFIG (0xB4336000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_DBUS_REG (0xB4337000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_SONIC (0xB4340000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_L0I_CACHE (0xB4350000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_L0D_CACHE (0xB4351000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_TIMER (0xB4352000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_EXCTRL (0xB4353000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_PC_MONITOR (0xB4354000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_PROFILING_UNIT (0xB4355000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_MBIST_CONFIG (0xB4356000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_DBUS_REG (0xB4357000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_SONIC (0xB4360000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_L0I_CACHE (0xB4370000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_L0D_CACHE (0xB4371000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_TIMER (0xB4372000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_EXCTRL (0xB4373000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_PC_MONITOR (0xB4374000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_PROFILING_UNIT (0xB4375000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_MBIST_CONFIG (0xB4376000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_DBUS_REG (0xB4377000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_SONIC (0xB4380000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_L0I_CACHE (0xB4390000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_L0D_CACHE (0xB4391000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_TIMER (0xB4392000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_EXCTRL (0xB4393000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_PC_MONITOR (0xB4394000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_PROFILING_UNIT (0xB4395000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_MBIST_CONFIG (0xB4396000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_DBUS_REG (0xB4397000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_SONIC (0xB43A0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_L0I_CACHE (0xB43B0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_L0D_CACHE (0xB43B1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_TIMER (0xB43B2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_EXCTRL (0xB43B3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_PC_MONITOR (0xB43B4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_PROFILING_UNIT (0xB43B5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_MBIST_CONFIG (0xB43B6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_DBUS_REG (0xB43B7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_SONIC (0xB43C0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_L0I_CACHE (0xB43D0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_L0D_CACHE (0xB43D1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_TIMER (0xB43D2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_EXCTRL (0xB43D3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_PC_MONITOR (0xB43D4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_PROFILING_UNIT (0xB43D5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_MBIST_CONFIG (0xB43D6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_DBUS_REG (0xB43D7000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_SONIC (0xB43E0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_L0I_CACHE (0xB43F0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_L0D_CACHE (0xB43F1000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_TIMER (0xB43F2000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_EXCTRL (0xB43F3000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_PC_MONITOR (0xB43F4000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_PROFILING_UNIT (0xB43F5000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_MBIST_CONFIG (0xB43F6000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_DBUS_REG (0xB43F7000)
+#define BASE_NADDR_MCORE_MCORE0_L1I_CACHE (0xB4800000)
+#define BASE_NADDR_MCORE_MCORE0_L1D_CACHE_1 (0xB4900000)
+#define BASE_NADDR_MCORE_THREAD0_ICM (0xB4A00000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD0_SONIC_RESERVED0 (0xB4A04000)
+#define BASE_NADDR_MCORE_THREAD1_ICM (0xB4A10000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD1_SONIC_RESERVED1 (0xB4A14000)
+#define BASE_NADDR_MCORE_THREAD2_ICM (0xB4A20000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD2_SONIC_RESERVED2 (0xB4A24000)
+#define BASE_NADDR_MCORE_THREAD3_ICM (0xB4A30000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD3_SONIC_RESERVED3 (0xB4A34000)
+#define BASE_NADDR_MCORE_THREAD4_ICM (0xB4A40000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD4_SONIC_RESERVED4 (0xB4A44000)
+#define BASE_NADDR_MCORE_THREAD5_ICM (0xB4A50000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD5_SONIC_RESERVED5 (0xB4A54000)
+#define BASE_NADDR_MCORE_THREAD6_ICM (0xB4A60000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD6_SONIC_RESERVED6 (0xB4A64000)
+#define BASE_NADDR_MCORE_THREAD7_ICM (0xB4A70000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD7_SONIC_RESERVED7 (0xB4A74000)
+#define BASE_NADDR_MCORE_THREAD8_ICM (0xB4A80000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD8_SONIC_RESERVED8 (0xB4A84000)
+#define BASE_NADDR_MCORE_THREAD9_ICM (0xB4A90000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD9_SONIC_RESERVED9 (0xB4A94000)
+#define BASE_NADDR_MCORE_THREAD10_ICM (0xB4AA0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD10_SONIC_RESERVED10 (0xB4AA4000)
+#define BASE_NADDR_MCORE_THREAD11_ICM (0xB4AB0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD11_SONIC_RESERVED11 (0xB4AB4000)
+#define BASE_NADDR_MCORE_THREAD12_ICM (0xB4AC0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD12_SONIC_RESERVED12 (0xB4AC4000)
+#define BASE_NADDR_MCORE_THREAD13_ICM (0xB4AD0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD13_SONIC_RESERVED13 (0xB4AD4000)
+#define BASE_NADDR_MCORE_THREAD14_ICM (0xB4AE0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD14_SONIC_RESERVED14 (0xB4AE4000)
+#define BASE_NADDR_MCORE_THREAD15_ICM (0xB4AF0000)
+#define BASE_NADDR_MCORE_MCORE0_THREAD15_SONIC_RESERVED15 (0xB4AF4000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM0 (0xB4F00000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM1 (0xB4F40000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM2 (0xB4F80000)
+#define BASE_NADDR_MCORE_MSYS_O_L2TCM3 (0xB4FC0000)
+#define BASE_NADDR_MCORE_MML1_MCORESYS_SHDM (0xB4FFC000)
+#define BASE_NADDR_VCORE_VSYS_DSPSLVSCHEDULER (0xB5000000)
+#define BASE_NADDR_VCORE_VSYS_DSPVCORELOG (0xB5001000)
+#define BASE_NADDR_VCORE_VSYS_VU2GRAM (0xB5002000)
+#define BASE_NADDR_VCORE_VPERI_DBUS1_APB2DBUSCR_INST (0xB5003000)
+#define BASE_NADDR_VCORE_VPERI_A2D (0xB5004000)
+#define BASE_NADDR_VCORE_VPERI_DBUSRECORDER (0xB5005000)
+#define BASE_NADDR_VCORE_VSYS_DBGMON (0xB5006000)
+#define BASE_NADDR_VCORE_VSYS_GLBCON (0xB5007000)
+#define BASE_NADDR_VCORE_VPERI_DSPCORECK_ABUS_REG (0xB5008000)
+#define BASE_NADDR_VCORE_VSYS_SWLA (0xB5010000)
+#define BASE_NADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST (0xB5011000)
+#define BASE_NADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST_1 (0xB5011100)
+#define BASE_NADDR_VCORE_VPERI_PERICK_ABUS_REG (0xB5014000)
+#define BASE_NADDR_VCORE_MBIST_CAT_BUS_DECODER (0xB5020000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_L1_CACHE (0xB5100000)
+#define BASE_NADDR_VCORE_VCORE0_L1D_CACHE (0xB5101000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CLKCTRL (0xB5102000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_EXCEPTION_CONTROLLER (0xB5103000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_PROFILING_UNIT (0xB5104000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_A2D (0xB5105000)
+#define BASE_NADDR_VCORE_VCORE0_A2D_128 (0xB5106000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_D2D (0xB5107000)
+#define BASE_NADDR_VCORE_DBUS_REG (0xB5108000)
+#define BASE_NADDR_VCORE_MML1_DSPEINTC (0xB5180000)
+#define BASE_NADDR_VCORE_VSYS_DSPDBGC1 (0xB5181000)
+#define BASE_NADDR_VCORE_VSYS_DSPCTIWRAP (0xB5182000)
+#define BASE_NADDR_VCORE_VSYS_DSPCTIWRAP_1 (0xB5182020)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_CORE (0xB5200000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_L0I_CACHE (0xB5210000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_DATA_CACHE (0xB5211000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_TIMER (0xB5212000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD0_EXCTRL (0xB5213000)
+#define BASE_NADDR_VCORE_MML1_DSPVCORE_TOP_PC_MONITOR (0xB5214000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD0_PROFILING_UNIT (0xB5215000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_L1 (0xB5220000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_BLAZE (0xB5230000)
+#define BASE_NADDR_VCORE_VCORE0_VU0_VMEM_CFG (0xB5231000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_HLSU (0xB5232000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_PROFILING_UNIT (0xB5233000)
+#define BASE_NADDR_VCORE_VCORE_VU_MBIST_CONFIG (0xB5234000)
+#define BASE_NADDR_VCORE_VCORE_VU_TOP_VCORE_VU_DBUS (0xB5235000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_SONIC (0xB5240000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_L0I_CACHE (0xB5250000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_L0D_CACHE (0xB5251000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_TIMER (0xB5252000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_EXCTRL (0xB5253000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_PC_MONITOR (0xB5254000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_PROFILING_UNIT (0xB5255000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_VMEM_MEM (0xB5260000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_BLAZE (0xB5270000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_VMEM_CFG (0xB5271000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_HLSU (0xB5272000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_PROFILING_UNIT (0xB5273000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_MBIST_CONFIG (0xB5274000)
+#define BASE_NADDR_VCORE_VCORE0_VU1_DBUS_REG (0xB5275000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_SONIC (0xB5280000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_L0I_CACHE (0xB5290000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_L0D_CACHE (0xB5291000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_TIMER (0xB5292000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_EXCTRL (0xB5293000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_PC_MONITOR (0xB5294000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_PROFILING_UNIT (0xB5295000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_VMEM_MEM (0xB52A0000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_BLAZE (0xB52B0000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_VMEM_CFG (0xB52B1000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_HLSU (0xB52B2000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_PROFILING_UNIT (0xB52B3000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_MBIST_CONFIG (0xB52B4000)
+#define BASE_NADDR_VCORE_VCORE0_VU2_DBUS_REG (0xB52B5000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_SONIC (0xB52C0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_L0I_CACHE (0xB52D0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_L0D_CACHE (0xB52D1000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_TIMER (0xB52D2000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_EXCTRL (0xB52D3000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_PC_MONITOR (0xB52D4000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_PROFILING_UNIT (0xB52D5000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_VMEM_MEM (0xB52E0000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_BLAZE (0xB52F0000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_VMEM_CFG (0xB52F1000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_HLSU (0xB52F2000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_PROFILING_UNIT (0xB52F3000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_MBIST_CONFIG (0xB52F4000)
+#define BASE_NADDR_VCORE_VCORE0_VU3_DBUS_REG (0xB52F5000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_SONIC (0xB5300000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_L0I_CACHE (0xB5310000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_L0D_CACHE (0xB5311000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_TIMER (0xB5312000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_EXCTRL (0xB5313000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_PC_MONITOR (0xB5314000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_PROFILING_UNIT (0xB5315000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_VMEM_MEM (0xB5320000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_BLAZE (0xB5330000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_VMEM_CFG (0xB5331000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_HLSU (0xB5332000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_PROFILING_UNIT (0xB5333000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_MBIST_CONFIG (0xB5334000)
+#define BASE_NADDR_VCORE_VCORE0_VU4_DBUS_REG (0xB5335000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_SONIC (0xB5340000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_L0I_CACHE (0xB5350000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_L0D_CACHE (0xB5351000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_TIMER (0xB5352000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_EXCTRL (0xB5353000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_PC_MONITOR (0xB5354000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_PROFILING_UNIT (0xB5355000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_VMEM_MEM (0xB5360000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_BLAZE (0xB5370000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_VMEM_CFG (0xB5371000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_HLSU (0xB5372000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_PROFILING_UNIT (0xB5373000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_MBIST_CONFIG (0xB5374000)
+#define BASE_NADDR_VCORE_VCORE0_VU5_DBUS_REG (0xB5375000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_SONIC (0xB5380000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_L0I_CACHE (0xB5390000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_L0D_CACHE (0xB5391000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_TIMER (0xB5392000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_EXCTRL (0xB5393000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_PC_MONITOR (0xB5394000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_PROFILING_UNIT (0xB5395000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_VMEM_MEM (0xB53A0000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_BLAZE (0xB53B0000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_VMEM_CFG (0xB53B1000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_HLSU (0xB53B2000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_PROFILING_UNIT (0xB53B3000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_MBIST_CONFIG (0xB53B4000)
+#define BASE_NADDR_VCORE_VCORE0_VU6_DBUS_REG (0xB53B5000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_SONIC (0xB53C0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_L0I_CACHE (0xB53D0000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_L0D_CACHE (0xB53D1000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_TIMER (0xB53D2000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_EXCTRL (0xB53D3000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_PC_MONITOR (0xB53D4000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_PROFILING_UNIT (0xB53D5000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_VMEM_MEM (0xB53E0000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_BLAZE (0xB53F0000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_VMEM_CFG (0xB53F1000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_HLSU (0xB53F2000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_PROFILING_UNIT (0xB53F3000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_MBIST_CONFIG (0xB53F4000)
+#define BASE_NADDR_VCORE_VCORE0_VU7_DBUS_REG (0xB53F5000)
+#define BASE_NADDR_VCORE_VCORE0_L1I_CACHE (0xB5800000)
+#define BASE_NADDR_VCORE_VCORE0_L1D_CACHE_1 (0xB5900000)
+#define BASE_NADDR_VCORE_THREAD0_ICM (0xB5A00000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD0_SONIC_RESERVED0 (0xB5A04000)
+#define BASE_NADDR_VCORE_THREAD1_ICM (0xB5A10000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD1_SONIC_RESERVED1 (0xB5A14000)
+#define BASE_NADDR_VCORE_THREAD2_ICM (0xB5A20000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD2_SONIC_RESERVED2 (0xB5A24000)
+#define BASE_NADDR_VCORE_THREAD3_ICM (0xB5A30000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD3_SONIC_RESERVED3 (0xB5A34000)
+#define BASE_NADDR_VCORE_THREAD4_ICM (0xB5A40000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD4_SONIC_RESERVED4 (0xB5A44000)
+#define BASE_NADDR_VCORE_THREAD5_ICM (0xB5A50000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD5_SONIC_RESERVED5 (0xB5A54000)
+#define BASE_NADDR_VCORE_THREAD6_ICM (0xB5A60000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD6_SONIC_RESERVED6 (0xB5A64000)
+#define BASE_NADDR_VCORE_THREAD7_ICM (0xB5A70000)
+#define BASE_NADDR_VCORE_VCORE0_THREAD7_SONIC_RESERVED7 (0xB5A74000)
+#define BASE_NADDR_GRAM_GRAM_BRIDGE (0xB6000000)
+#define BASE_NADDR_GRAM_GRAM_GLBCON (0xB6F00000)
+#define BASE_NADDR_GRAM_GRAMSYS_MBIST_MBIST_TOP_CFG (0xB6F10000)
+#define BASE_NADDR_GRAM_GRAM_BRIDGE_REG (0xB6F20000)
+#define BASE_NADDR_GRAM_GRAM_REG (0xB6F30000)
+#define BASE_NADDR_GRAM_GRAM_BUS_CONFIG (0xB6F40000)
+#define BASE_NADDR_2ND_ROM_TABLE_DAP_2ND_ROM (0xB0600000)
+#define BASE_NADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_NADDR_MDPERISYS_MISC_REG_MDPERISYS_MISC_REG (0xB0602000)
+#define BASE_NADDR_MD_DBGMON_MD_DBGMON (0xB0603000)
+#define BASE_NADDR_MDPERI_CLKTL_MDPERI_CLKTL (0xB0603800)
+#define BASE_NADDR_IA_USIP_ECT_MD_CXCTI (0xB0604000)
+#define BASE_NADDR_VDSP_MD32_ECT_MD_CXCTI (0xB0605000)
+#define BASE_NADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB0606000)
+#define BASE_NADDR_TOPSM_PROTECT_MDL1_MODEM_TOPSM_PROTECT (0xB060B000)
+#define BASE_NADDR_TOPSM_MDL1_MODEM_TOPSM (0xB060C000)
+#define BASE_NADDR_OSTIMER_MD_OSTIMER (0xB060D000)
+#define BASE_NADDR_RGU_MDRGU_REG (0xB060E000)
+#define BASE_NADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB060F000)
+#define BASE_NADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0610000)
+#define BASE_NADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0611000)
+#define BASE_NADDR_MD_CLKSW_MD_CLKSW_REG (0xB0612000)
+#define BASE_NADDR_RAKE_BUS_INTF_RAKESYS_BUS_DBGAPB_INTF (0xB0614000)
+#define BASE_NADDR_RAKE_MD32_RAKE_MD32 (0xB0616000)
+#define BASE_NADDR_VDSP_1_MD32SCQ (0xB0618000)
+#define BASE_NADDR_VDSP_2_MD32SCQ (0xB0619000)
+#define BASE_NADDR_VDSP_3_MD32SCQ (0xB061A000)
+#define BASE_NADDR_VDSP_4_MD32SCQ (0xB061B000)
+#define BASE_NADDR_BIGRAM_BUS_INTF_BIGRAM_BUS_INTF (0xB061C000)
+#define BASE_NADDR_INR_BUS_INTF_INR_BUS_INTF (0xB061E000)
+#define BASE_NADDR_USIP0_USIP0 (0xB0620000)
+#define BASE_NADDR_USIP1_USIP1 (0xB0621000)
+#define BASE_NADDR_USIPCORE_BUS_INTF_USIPCORE_BUS_INTF (0xB0622000)
+#define BASE_NADDR_L2SRAM_L2SRAM (0xB0624000)
+#define BASE_NADDR_MDMCU_BUS_INTF_VDNR__MDMCU_BUS_INTF (0xB0628000)
+#define BASE_NADDR_MDMCU_COREBUS_INTF_VDNR__MDMCU_COREBUS_INTF (0xB062A000)
+#define BASE_NADDR_MDMCU_BUSMON_MDMCU_BUSMON (0xB062C000)
+#define BASE_NADDR_MDMCU_USIP_BUS_INTF_MDMCU_USIP_BUS_INTF (0xB062D000)
+#define BASE_NADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB0630000)
+#define BASE_NADDR_SHAOLIN_DEBUG_PERI_SHAOLIN_DEBUG_PERI (0xB0633000)
+#define BASE_NADDR_SHAOLIN_MACRO_BUS_INTF_VDNR__SHAOLIN_MACRO_BUS_INTF (0xB0634000)
+#define BASE_NADDR_SHAOLIN_BUSMPU_SHAOLIN_BUSMPU (0xB0636000)
+#define BASE_NADDR_SHAOLIN_CM2_SHAOLIN_CM2 (0xB0637000)
+#define BASE_NADDR_SHAOLIN_CORE0__SHAOLIN_CORE0 (0xB0638000)
+#define BASE_NADDR_SHAOLIN_CORE1_SHAOLIN_CORE1 (0xB0639000)
+#define BASE_NADDR_SHAOLIN_CORE2__SHAOLIN_CORE2 (0xB063A000)
+#define BASE_NADDR_SHAOLIN_CORE3_SHAOLIN_CORE3 (0xB063B000)
+#define BASE_NADDR_MDINFRA_BUS4X_REG_MDINFRA_BUS4X_REG (0xB063C000)
+#define BASE_NADDR_MDINFRA_BUS2X_REG_MDINFRA_BUS2X_REG (0xB063D000)
+#define BASE_NADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB063E000)
+#define BASE_NADDR_NRL2_BUS_INTF_NRL2_BUS_INTF (0xB0640000)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_RXCPC_NR_DBGAPB_MAS_BUS_INTF (0xB0642000)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2 (0xB0642800)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_RXCPC_NR_DBGAPB_SLV_BUS_INTF (0xB0643000)
+#define BASE_NADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2 (0xB0643800)
+#define BASE_NADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF (0xB0644000)
+#define BASE_NADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF_1 (0xB0645000)
+#define BASE_NADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF (0xB0646000)
+#define BASE_NADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF_1 (0xB0647000)
+#define BASE_NADDR_MDAO_MAS_BUS_CK_DBG_MDAO_MAS_BUS_CK_DBG (0xB0648000)
+#define BASE_NADDR_MDAO_SLV_BUS_CK_DBG_MDAO_SLV_BUS_CK_DBG (0xB0649000)
+#define BASE_NADDR_MD_DVFS_TOP_CK_DBG_MD_DVFS_TOP_CK_DBG (0xB0649800)
+#define BASE_NADDR_MDL1_TOPSM_MDL1_TOPSM (0xB064A000)
+#define BASE_NADDR_RFSLPC_RFSLPC (0xB064B000)
+#define BASE_NADDR_MD2G_BUS_MD2G_BUS (0xB064C000)
+#define BASE_NADDR_CSSYS_BUS_CK_DBG_CSSYS_BUS_CK_DBG (0xB064E000)
+#define BASE_NADDR_CSSYS_BUS_DIV2_CK_DBG_CSSYS_BUS_DIV2_CK_DBG (0xB064E800)
+#define BASE_NADDR_MDAO_BUS_CK_DBG_MDAO_BUS_CK_DBG (0xB064F000)
+#define BASE_NADDR_VCORE_TOP_TH0_SONIC_VCORE (0xB0650000)
+#define BASE_NADDR_VCORE_TOP_TH0_PC_MONITOR_VCORE (0xB0650400)
+#define BASE_NADDR_VCORE_TOP_TH0_VUDBUS_VCORE (0xB0650480)
+#define BASE_NADDR_VCORE_TOP_TH1_SONIC_VCORE (0xB0650600)
+#define BASE_NADDR_VCORE_TOP_TH1_PC_MONITOR_VCORE (0xB0650A00)
+#define BASE_NADDR_VCORE_TOP_TH1_VUDBUS_VCORE (0xB0650A80)
+#define BASE_NADDR_VCORE_TOP_TH2_SONIC_VCORE (0xB0650C00)
+#define BASE_NADDR_VCORE_TOP_TH2_PC_MONITOR_VCORE (0xB0651000)
+#define BASE_NADDR_VCORE_TOP_TH2_VUDBUS_VCORE (0xB0651080)
+#define BASE_NADDR_VCORE_TOP_TH3_SONIC_VCORE (0xB0651200)
+#define BASE_NADDR_VCORE_TOP_TH3_PC_MONITOR_VCORE (0xB0651600)
+#define BASE_NADDR_VCORE_TOP_TH3_VUDBUS_VCORE (0xB0651680)
+#define BASE_NADDR_VCORE_TOP_TH4_SONIC_VCORE (0xB0651800)
+#define BASE_NADDR_VCORE_TOP_TH4_PC_MONITOR_VCORE (0xB0651C00)
+#define BASE_NADDR_VCORE_TOP_TH4_VUDBUS_VCORE (0xB0651C80)
+#define BASE_NADDR_VCORE_TOP_TH5_SONIC_VCORE (0xB0651E00)
+#define BASE_NADDR_VCORE_TOP_TH5_PC_MONITOR_VCORE (0xB0652200)
+#define BASE_NADDR_VCORE_TOP_TH5_VUDBUS_VCORE (0xB0652280)
+#define BASE_NADDR_VCORE_TOP_TH6_SONIC_VCORE (0xB0652400)
+#define BASE_NADDR_VCORE_TOP_TH6_PC_MONITOR_VCORE (0xB0652800)
+#define BASE_NADDR_VCORE_TOP_TH6_VUDBUS_VCORE (0xB0652880)
+#define BASE_NADDR_VCORE_TOP_TH7_SONIC_VCORE (0xB0652A00)
+#define BASE_NADDR_VCORE_TOP_TH7_PC_MONITOR_VCORE (0xB0652E00)
+#define BASE_NADDR_VCORE_TOP_TH7_VUDBUS_VCORE (0xB0652E80)
+#define BASE_NADDR_VCORE_TOP_L1_DBUS_VCORE (0xB0653000)
+#define BASE_NADDR_VCORE_TOP_A2D32_VCORE (0xB0654000)
+#define BASE_NADDR_VCORE_TOP_A2D128_VCORE (0xB0654080)
+#define BASE_NADDR_VCORECK_ABUS_VCORECK_ABUS (0xB0655000)
+#define BASE_NADDR_VCORE_DIV2CK_ABUS_VCORE_DIV2CK_ABUS (0xB0655800)
+#define BASE_NADDR_VCORE_CK_DBUS_VCORE_CK_DBUS (0xB0656000)
+#define BASE_NADDR_VCORE_DIV2CK_DBUS_VCORE_DIV2CK_DBUS (0xB0656800)
+#define BASE_NADDR_BUS_RECORDER_BUS_RECORDER (0xB0657000)
+#define BASE_NADDR_VPERIA2D_DBGAPB_VPERIA2D_DBGAPB (0xB0657800)
+#define BASE_NADDR_DEBUG_MONITOR_FOR_DBG_FLAG_MML1_DSPVCORE_DBGMON_WRAP (0xB0657880)
+#define BASE_NADDR_VCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_VCORE_MML1_DSPCTIWRAP (0xB0657900)
+#define BASE_NADDR_VCORE_PAR_AO_CR_VCORE_PAR_AO_CR (0xB0657A00)
+#define BASE_NADDR_GRAM_PERI_GRAM_PERI (0xB0658000)
+#define BASE_NADDR_MCORE0_TOP_TH0_SONIC_MCORE0 (0xB0660000)
+#define BASE_NADDR_MCORE0_TOP_TH0_PC_MONITOR_MCORE0 (0xB0660400)
+#define BASE_NADDR_MCORE0_TOP_TH0_VUDBUS_MCORE0 (0xB0660480)
+#define BASE_NADDR_MCORE0_TOP_TH1_SONIC_MCORE0 (0xB0660600)
+#define BASE_NADDR_MCORE0_TOP_TH1_PC_MONITOR_MCORE0 (0xB0660A00)
+#define BASE_NADDR_MCORE0_TOP_TH1_VUDBUS_MCORE0 (0xB0660A80)
+#define BASE_NADDR_MCORE0_TOP_TH2_SONIC_MCORE0 (0xB0660C00)
+#define BASE_NADDR_MCORE0_TOP_TH2_PC_MONITOR_MCORE0 (0xB0661000)
+#define BASE_NADDR_MCORE0_TOP_TH2_VUDBUS_MCORE0 (0xB0661080)
+#define BASE_NADDR_MCORE0_TOP_TH3_SONIC_MCORE0 (0xB0661200)
+#define BASE_NADDR_MCORE0_TOP_TH3_PC_MONITOR_MCORE0 (0xB0661600)
+#define BASE_NADDR_MCORE0_TOP_TH3_VUDBUS_MCORE0 (0xB0661680)
+#define BASE_NADDR_MCORE0_TOP_TH4_SONIC_MCORE0 (0xB0661800)
+#define BASE_NADDR_MCORE0_TOP_TH4_PC_MONITOR_MCORE0 (0xB0661C00)
+#define BASE_NADDR_MCORE0_TOP_TH4_VUDBUS_MCORE0 (0xB0661C80)
+#define BASE_NADDR_MCORE0_TOP_TH5_SONIC_MCORE0 (0xB0661E00)
+#define BASE_NADDR_MCORE0_TOP_TH5_PC_MONITOR_MCORE0 (0xB0662200)
+#define BASE_NADDR_MCORE0_TOP_TH5_VUDBUS_MCORE0 (0xB0662280)
+#define BASE_NADDR_MCORE0_TOP_TH6_SONIC_MCORE0 (0xB0662400)
+#define BASE_NADDR_MCORE0_TOP_TH6_PC_MONITOR_MCORE0 (0xB0662800)
+#define BASE_NADDR_MCORE0_TOP_TH6_VUDBUS_MCORE0 (0xB0662880)
+#define BASE_NADDR_MCORE0_TOP_TH7_SONIC_MCORE0 (0xB0662A00)
+#define BASE_NADDR_MCORE0_TOP_TH7_PC_MONITOR_MCORE0 (0xB0662E00)
+#define BASE_NADDR_MCORE0_TOP_TH7_VUDBUS_MCORE0 (0xB0662E80)
+#define BASE_NADDR_MCORE0_TOP_TH8_SONIC_MCORE0 (0xB0663000)
+#define BASE_NADDR_MCORE0_TOP_TH8_PC_MONITOR_MCORE0 (0xB0663400)
+#define BASE_NADDR_MCORE0_TOP_TH8_VUDBUS_MCORE0 (0xB0663480)
+#define BASE_NADDR_MCORE0_TOP_TH9_SONIC_MCORE0 (0xB0663600)
+#define BASE_NADDR_MCORE0_TOP_TH9_PC_MONITOR_MCORE0 (0xB0663A00)
+#define BASE_NADDR_MCORE0_TOP_TH9_VUDBUS_MCORE0 (0xB0663A80)
+#define BASE_NADDR_MCORE0_TOP_TH10_SONIC_MCORE0 (0xB0663C00)
+#define BASE_NADDR_MCORE0_TOP_TH10_PC_MONITOR_MCORE0 (0xB0664000)
+#define BASE_NADDR_MCORE0_TOP_TH10_VUDBUS_MCORE0 (0xB0664080)
+#define BASE_NADDR_MCORE0_TOP_TH11_SONIC_MCORE0 (0xB0664200)
+#define BASE_NADDR_MCORE0_TOP_TH11_PC_MONITOR_MCORE0 (0xB0664600)
+#define BASE_NADDR_MCORE0_TOP_TH11_VUDBUS_MCORE0 (0xB0664680)
+#define BASE_NADDR_MCORE0_TOP_TH12_SONIC_MCORE0 (0xB0664800)
+#define BASE_NADDR_MCORE0_TOP_TH12_PC_MONITOR_MCORE0 (0xB0664C00)
+#define BASE_NADDR_MCORE0_TOP_TH12_VUDBUS_MCORE0 (0xB0664C80)
+#define BASE_NADDR_MCORE0_TOP_TH13_SONIC_MCORE0 (0xB0664E00)
+#define BASE_NADDR_MCORE0_TOP_TH13_PC_MONITOR_MCORE0 (0xB0665200)
+#define BASE_NADDR_MCORE0_TOP_TH13_VUDBUS_MCORE0 (0xB0665280)
+#define BASE_NADDR_MCORE0_TOP_TH14_SONIC_MCORE0 (0xB0665400)
+#define BASE_NADDR_MCORE0_TOP_TH14_PC_MONITOR_MCORE0 (0xB0665800)
+#define BASE_NADDR_MCORE0_TOP_TH14_VUDBUS_MCORE0 (0xB0665880)
+#define BASE_NADDR_MCORE0_TOP_TH15_SONIC_MCORE0 (0xB0665A00)
+#define BASE_NADDR_MCORE0_TOP_TH15_PC_MONITOR_MCORE0 (0xB0665E00)
+#define BASE_NADDR_MCORE0_TOP_TH15_VUDBUS_MCORE0 (0xB0665E80)
+#define BASE_NADDR_MCORE0_TOP_L1DBUS_MCORE0 (0xB0666000)
+#define BASE_NADDR_MCORE0_TOP_L1I_CACHE_MCORE0 (0xB0667000)
+#define BASE_NADDR_MCORE0_TOP_L1D_CACHE_MCORE0 (0xB0667200)
+#define BASE_NADDR_MCORE0_TOP_A2D32_MCORE0 (0xB0667400)
+#define BASE_NADDR_MCORE0_TOP_A2D128_MCORE0 (0xB0667480)
+#define BASE_NADDR_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB (0xB0670000)
+#define BASE_NADDR_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB (0xB0671000)
+#define BASE_NADDR_MML1_MPERI_PERICK_ABUS_REG_DBGAPB_MML1_MPERI_PERICK_ABUS_REG_DBGAPB (0xB0672000)
+#define BASE_NADDR_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB (0xB0673000)
+#define BASE_NADDR_MML1_MPERI_DSPCK_DBUS_REG_DBG_MML1_MPERI_DSPCK_DBUS_REG_DBG (0xB0674000)
+#define BASE_NADDR_MML1_MPERI_PERICK_DBUS_REG_DBG_MML1_MPERI_PERICK_DBUS_REG_DBG (0xB0675000)
+#define BASE_NADDR_MML1_MCOREPERI_ABUSMON_TOP_DBG_MML1_MCOREPERI_ABUSMON_TOP_DBG (0xB0676000)
+#define BASE_NADDR_MML1_MPERI_DBUSRECORDER_DBG_MML1_MPERI_DBUSRECORDER_DBG (0xB0677000)
+#define BASE_NADDR_MPERIA2D_DBGAPB_MPERIA2D_DBGAPB (0xB0678000)
+#define BASE_NADDR_MML1_MCORESYS_DBGMON_WRAP_MML1_MCORESYS_DBGMON_WRAP (0xB0679000)
+#define BASE_NADDR_MML1_MPERI_DSPCORECK_DBUS_REG_DBG_MML1_MPERI_DSPCORECK_DBUS_REG_DBG (0xB067A000)
+#define BASE_NADDR_CMCS_MAS_MDTOP_BUS4X_CK_REG_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0680000)
+#define BASE_NADDR_CMCS_SLV_MDTOP_BUS4X_CK_REG_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0681000)
+#define BASE_NADDR_CM_CS_BUS_CK_REG_MML1_CM_CS_BUS_CK_ABUS_REG (0xB0682000)
+#define BASE_NADDR_CS_NR_BUS_CK_REG_MML1_CS_NR_BUS_CK_ABUS_REG (0xB0683000)
+#define BASE_NADDR_CMCS_NR_CM_NR_CK_REG_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xB0684000)
+#define BASE_NADDR_CM_NR_MDTOP_BUS4X_CK_REG_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xB0685000)
+#define BASE_NADDR_CMCS_NR_RXTFC_NR_CK_REG_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xB0686000)
+#define BASE_NADDR_RXTFC_MDTOP_BUS4X_CK_REG_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xB0687000)
+#define BASE_NADDR_CMCS_NR_RXTDB_NR_CK_REG_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xB0688000)
+#define BASE_NADDR_RXTDB_MDTOP_BUS4X_CK_REG_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xB0689000)
+#define BASE_NADDR_CMCS_NR_RXTDB_PBCH_NR_CK_REG_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xB068A000)
+#define BASE_NADDR_RXTDB_PBCH_MDTOP_BUS4X_CK_REG_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xB068B000)
+#define BASE_NADDR_TX_NR_MAS_TXBSRP_NR_CK_REG_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xB0690000)
+#define BASE_NADDR_TX_NR_MAS_MDTOP_BUS4X_CK_REG_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0691000)
+#define BASE_NADDR_TX_NR_SLV_TXBSRP_NR_CK_REG_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xB0692000)
+#define BASE_NADDR_TX_NR_SLV_MDTOP_BUS4X_CK_REG_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0693000)
+#define BASE_NADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF (0xB0694000)
+#define BASE_NADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF_1 (0xB0696000)
+#define BASE_NADDR_DFESYS_BUS_INTF_DFESYS_MAS_BUS_CONFIG_REAL (0xB0698000)
+#define BASE_NADDR_DFESYS_BUS_INTF_DFESYS_SLV_BUS_CONFIG (0xB069A000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_BUS_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xB069C000)
+#define BASE_NADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xB069D000)
+#define BASE_NADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xB069F0000)
+#define BASE_NADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xB069F8000)
+#define BASE_NADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TXDFE_468M_CK_ABUS_REG (0xB06A0000)
+#define BASE_NADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TPC_468M_CK_ABUS_REG (0xB06A3000)
+#define BASE_NADDR_MMW_RXDFE_BUS_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xB06A4000)
+#define BASE_NADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xB06A5000)
+#define BASE_NADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xB06A7000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_NADDR_RXDDM_NR_RESERVED0 (0xB7008000)
+#define BASE_NADDR_RXDDM_NR_RESERVED1 (0xB700A000)
+#define BASE_NADDR_RXDDM_NR_RESERVED2 (0xB700C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB700E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_EGID (0xB7010000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_EGOC (0xB7012000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7014000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7016000)
+#define BASE_NADDR_RXDDM_NR_RESERVED3 (0xB7018000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_STIME_LOG (0xB701A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MDCC (0xB701C000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB701E000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7020000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_ROI (0xB7022000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_DCE (0xB7024000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_PP (0xB7026000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB7028000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB702A000)
+#define BASE_NADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB702C000)
+#define BASE_NADDR_RXDDM_NR_MML1_RXDDM_CK_ABUS_REG (0xB702E000)
+#define BASE_NADDR_RXDDM_NR_MML1_RXDDM_HALF_CK_ABUS_REG (0xB7030000)
+#define BASE_NADDR_RXDDM_NR_SLOT_RNTI (0xB7200000)
+#define BASE_NADDR_RXDDM_NR_RESERVED4 (0xB7201000)
+#define BASE_NADDR_RXDDM_NR_SYM (0xB7220000)
+#define BASE_NADDR_RXDDM_NR_RESERVED5 (0xB7228000)
+#define BASE_NADDR_RXDDM_NR_MASK_TYPE0 (0xB7240000)
+#define BASE_NADDR_RXDDM_NR_MASK_TYPE1 (0xB7260000)
+#define BASE_NADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_NADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED_0 (0xB7910000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_NADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_NADDR_RXDBRP_NR_RESERVED_1 (0xB7960000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_EMI_CK_ABUS_REG (0xB7970000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_EMI_HALF_CK_ABUS_REG (0xB7980000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_SD_CK_ABUS_REG (0xB7990000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_SD_HALF_CK_ABUS_REG (0xB79A0000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_CK_ABUS_REG (0xB79B0000)
+#define BASE_NADDR_RXDBRP_NR_MML1_RXDBRP_HALF_CK_ABUS_REG (0xB79C0000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_NADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_M_CK_ABUS_REG (0xB7C0C000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_M_HALF_CK_ABUS_REG (0xB7C0E000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_CK_ABUS_REG (0xB7C10000)
+#define BASE_NADDR_RXCPC_NR_MML1_RXCPC_HALF_CK_ABUS_REG (0xB7C12000)
+#define BASE_NADDR_RXCPC_NR_RESERVED0 (0xB7C14000)
+#define BASE_NADDR_RXCPC_NR_RESERVED1 (0xB7C16000)
+#define BASE_NADDR_RXCPC_NR_RXCPC_NR_CFG_SP (0xB7C20000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_NADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_NADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_NADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_NADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_NADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_NADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_NADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_NADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_NADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_NADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_NADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_NADDR_MODEML1_AO_MD_DVFS_TOP_CONFIG (0xB8110000)
+#define BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_NADDR_MODEML1_AO_BSI_MM_MIPI (0xB8140000)
+#define BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MAS_BUS_CONFIG (0xB8160000)
+#define BASE_NADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_NADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_NADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG (0xB81A0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_NADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_NADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_NADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_NADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_NADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_NADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_NADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_NADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_NADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_NADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_NADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_NADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_NADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_NADDR_MODEML1_AO_U_DFESYS_MEM_CONFIG (0xB82C0000)
+#define BASE_NADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_NADDR_MODEML1_AO_U_MMW_TXDFE_MEM_CONFIG (0xB8300000)
+#define BASE_NADDR_MODEML1_AO_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_NADDR_MODEML1_AO_MD_PLLMIXED (0xB0140000)
+#define BASE_NADDR_MODEML1_AO_MD_CLKSW (0xB0150000)
+#define BASE_NADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_NADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_NADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_NADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_NADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_NADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_NADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_NADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_NADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_NADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_NADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_NADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_NADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_NADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_NADDR_DFESYS_RESERVED0 (0xB89A0000)
+#define BASE_NADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_NADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_NADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_NADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_NADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_NADDR_DFESYS_RESERVED1 (0xB8AF0000)
+#define BASE_NADDR_DFESYS_RESERVED2 (0xB8B00000)
+#define BASE_NADDR_DFESYS_RESERVED3 (0xB8B10000)
+#define BASE_NADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_NADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_NADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_NADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_NADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_NADDR_DFESYS_RESERVED4 (0xB8B70000)
+#define BASE_NADDR_DFESYS_RESERVED5 (0xB8B80000)
+#define BASE_NADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_NADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_NADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_NADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_NADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_NADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_NADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES (0xB8C00000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_NADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_NADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_NADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_NADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_NADDR_DFESYS_DFE_COMDMA (0xB8E00000)
+#define BASE_NADDR_DFESYS_RESERVED6 (0xB8E10000)
+#define BASE_NADDR_DFESYS_RESERVED7 (0xB8E20000)
+#define BASE_NADDR_DFESYS_RESERVED8 (0xB8E30000)
+#define BASE_NADDR_DFESYS_RESERVED9 (0xB8E40000)
+#define BASE_NADDR_DFESYS_RESERVED10 (0xB8E50000)
+#define BASE_NADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_NADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_1 (0xB8E80000)
+#define BASE_NADDR_DFESYS_DIGBB_SERDES_2 (0xB8E88000)
+#define BASE_NADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_NADDR_DFESYS_RESERVED11 (0xB8EA0000)
+#define BASE_NADDR_DFESYS_MAS_BUS_INTF (0xB8EB0000)
+#define BASE_NADDR_DFESYS_SLV_BUS_INTF (0xB8EC0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_NADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_NADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_NADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_NADDR_CSSYS_CS (0xB9800000)
+#define BASE_NADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_NADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_NADDR_CSSYS_CSSYS_BUS_CONFIG (0xB9830000)
+#define BASE_NADDR_CSSYS_CSSYS_BUS_DIV2_CONFIG (0xB9838000)
+#define BASE_NADDR_CSSYS_MDAO_BUS_CONFIG (0xB983C000)
+#define BASE_NADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_NADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_NADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_NADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_NADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_NADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_NADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_NADDR_CS_NR_CS_NR_SCN_RPT (0xB9C20000)
+#define BASE_NADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_NADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_NADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_NADDR_CS_NR_CM_CS_BUS_CONFIG (0xB9C60000)
+#define BASE_NADDR_CMCS_PAR_AO_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBDC00000)
+#define BASE_NADDR_CMCS_PAR_AO_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBDC10000)
+#define BASE_NADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG (0xBDC20000)
+#define BASE_NADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG (0xBDC30000)
+#define BASE_NADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG (0xBDC40000)
+#define BASE_NADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO (0xBDC50000)
+#define BASE_NADDR_CMCS_PAR_AO_MCORE_PAR_AO_REG (0xBDC50400)
+#define BASE_NADDR_CMCS_PAR_AO_U_VCORE_PAR_WRAP_SRAM_AO (0xBDC60000)
+#define BASE_NADDR_CMCS_PAR_AO_U_VCORE_PAR_AO_CR (0xBDC60400)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_0_SM_CONFIG (0xBDC60600)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_1_SM_CONFIG (0xBDC60680)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_2_SM_CONFIG (0xBDC60700)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_3_SM_CONFIG (0xBDC60780)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_4_SM_CONFIG (0xBDC60800)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_5_SM_CONFIG (0xBDC60880)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_6_SM_CONFIG (0xBDC60900)
+#define BASE_NADDR_CMCS_PAR_AO_U_VU_7_SM_CONFIG (0xBDC60980)
+#define BASE_NADDR_CMCS_PAR_AO_U_GRAM_MEM_CONFIG (0xBDC70000)
+#define BASE_NADDR_CMCS_PAR_AO_U_TX_NR_MEM_CONFIG (0xBDC80000)
+#define BASE_NADDR_CMCS_PAR_AO_U_CMCS_NR_MEM_CONFIG (0xBDC90000)
+#define BASE_NADDR_CMCS_PAR_AO_U_CMCS_PAR_AO_CONFIG_REG (0xBDCA0000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBA000000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xBA008000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBA010000)
+#define BASE_NADDR_TXSYS_NR_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xBA018000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA020000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA030000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_2 (0xBA040000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_3 (0xBA050000)
+#define BASE_NADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_4 (0xBA060000)
+#define BASE_NADDR_TXSYS_NR_TXBSRP_GLB_APB_CONFIG (0xBA070000)
+#define BASE_NADDR_TXSYS_NR_TXBSRP_BIT_CONTROLLER (0xBA080000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA100000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG (0xBA101000)
+#define BASE_NADDR_TXSYS_NR_RESERVED0 (0xBA102000)
+#define BASE_NADDR_TXSYS_NR_TX_NR_PAR_AO_CONFIG_REG (0xBA10C000)
+#define BASE_NADDR_TXSYS_NR_RESERVED1 (0xBA10D000)
+#define BASE_NADDR_TXSYS_NR_RESERVED2 (0xBA10E000)
+#define BASE_NADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_NADDR_CM_NR_CM_NR_MBIST_WRAP (0xBA410000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_0 (0xBA420000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_DVTCRC (0xBA430000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH (0xBA440000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_1 (0xBA450000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_DVTCRC_1 (0xBA460000)
+#define BASE_NADDR_CM_NR_CM_NR_PBCH_1 (0xBA470000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_2 (0xBA480000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB_SSS (0xBA490000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB_SSS (0xBA4A0000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP_SSS (0xBA4B0000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT_SSS (0xBA4C0000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_SSS (0xBA4D0000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL_SSS (0xBA4E0000)
+#define BASE_NADDR_CM_NR_CM_NR_DVTCRC_SSS (0xBA4F0000)
+#define BASE_NADDR_CM_NR_CM_NR_TDB_CSIRS (0xBA500000)
+#define BASE_NADDR_CM_NR_CM_NR_FDB_CSIRS (0xBA510000)
+#define BASE_NADDR_CM_NR_CM_NR_RSSIRSRP_CSIRS (0xBA520000)
+#define BASE_NADDR_CM_NR_CM_NR_REPORT_CSIRS (0xBA530000)
+#define BASE_NADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_CSIRS (0xBA540000)
+#define BASE_NADDR_CM_NR_CM_NR_TD_CTRL_CSIRS (0xBA550000)
+#define BASE_NADDR_CM_NR_CM_NR_DVTCRC_CSIRS (0xBA560000)
+#define BASE_NADDR_CM_NR_CM_NR_RESERVED_3 (0xBA570000)
+#define BASE_NADDR_CM_NR_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xBA580000)
+#define BASE_NADDR_CM_NR_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xBA590000)
+#define BASE_NADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_NADDR_RXTFC_RESERVED0 (0xBA830000)
+#define BASE_NADDR_RXTFC_RESERVED1 (0xBA840000)
+#define BASE_NADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA850000)
+#define BASE_NADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_NADDR_RXTFC_RESERVED2 (0xBA870000)
+#define BASE_NADDR_RXTFC_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xBA880000)
+#define BASE_NADDR_RXTFC_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xBA890000)
+#define BASE_NADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC30000)
+#define BASE_NADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC40000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_NADDR_RXTDB_RXTDB_NR_TOP_3 (0xBAC70000)
+#define BASE_NADDR_RXTDB_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xBAC80000)
+#define BASE_NADDR_RXTDB_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xBAC90000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_NADDR_RXTDB_PBCH_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xBAE40000)
+#define BASE_NADDR_RXTDB_PBCH_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xBAE50000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE60000)
+#define BASE_NADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE70000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_NADDR_BIGRAM0_BIGRAM_BUS_CONFIG (0xBB880000)
+#define BASE_NADDR_BIGRAM0_INR_SLV_BUS_CONFIG (0xBB890000)
+#define BASE_NADDR_INR0_MEM (0xBBA00000)
+#define BASE_NADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_NADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_NADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_NADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_NADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_NADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_NADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_NADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_NADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_NADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_NADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_NADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_NADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_NADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_NADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_NADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_NADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_NADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_NADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_NADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_NADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_NADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_NADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_NADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_NADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_NADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_NADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_NADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_NADDR_RXBRP0_DMC_MBIST_CONFIG (0xBC810000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_NADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_NADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_MAS_HALF_CK_ABUS_REG (0xBC960000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_NADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_MAS_CK_ABUS_REG (0xBC990000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_SLV_HALF_CK_ABUS_REG (0xBC9A0000)
+#define BASE_NADDR_RXBRP0_MML1_RXBRP_SLV_CK_ABUS_REG (0xBC9B0000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_NADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_NADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_NADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_NADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_NADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_NADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_NADDR_RXBRP0_LTE_CE_SC (0xBCB20000)
+#define BASE_NADDR_RXBRP0_LTE_CE_OC1 (0xBCB21000)
+#define BASE_NADDR_RXBRP0_LTE_CE_OC2 (0xBCB22000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_PDSCH (0xBCB30000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_PDCCH (0xBCB33000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_EPDCCH (0xBCB34000)
+#define BASE_NADDR_RXBRP0_DEMOD_TOP_PBCH (0xBCB35000)
+#define BASE_NADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_NADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_NADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_NADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_NADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_NADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_NADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_NADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_NADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_NADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_NADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_NADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_NADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_NADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_NADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_NADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_NADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_NADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_NADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_NADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_NADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_NADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_NADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_NADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_NADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_NADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_NADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_NADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_SRAM_CTRL_AO (0xBD000000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MMW_DBB_CTRLACNT (0xBD001000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_GLOBAL_CON_AO (0xBD002000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_RESERVED0 (0xBD003000)
+#define BASE_NADDR_MMW_RF_CTRL_AO_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xBD010000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RFAC (0xBD020000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CM_DATA_INTF (0xBD040000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_EVENTGEN (0xBD050000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED1 (0xBD060000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xBD080000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_LOG (0xBD090000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_COMDMA (0xBD0A0000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_CONTROLLER (0xBD0B0000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD (0xBD0B8000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_1 (0xBD0B8100)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_2 (0xBD0B8200)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED2 (0xBD0B8300)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_MBIST (0xBD0B9000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_GLOBAL_CON (0xBD0BA000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED3 (0xBD0BB000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_CM_COMM_REG (0xBD0F8000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG (0xBD0F8400)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_1 (0xBD0F8800)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_2 (0xBD0F8C00)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED4 (0xBD0F9000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_TOP (0xBD100000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_LOG (0xBD108000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_SCH (0xBD110000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xBD120000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED5 (0xBD130000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BPI (0xBD180000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_DIGRF_MIPI_M (0xBD190000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_TOP (0xBD200000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SCH (0xBD210000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI0 (0xBD218000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI1 (0xBD219000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI2 (0xBD21A000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI3 (0xBD21B000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI4 (0xBD21C000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI5 (0xBD21D000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI6 (0xBD21E000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI7 (0xBD21F000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xBD220000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED6 (0xBD230000)
+#define BASE_NADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED7 (0xBD300000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_RESERVED0 (0xBD400000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_RESERVED1 (0xBD640000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TOP_CTRL (0xBD410000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_TXK (0xBD420000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_GLOBAL_CON (0xBD430000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BUS_CONFIG (0xBD440000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_MBIST_CONFIG_CAT (0xBD450000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TX_ACNT_TICK_GEN (0xBD460000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TQ (0xBD470000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR (0xBD480000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_1 (0xBD490000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_2 (0xBD4A0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_3 (0xBD4B0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_4 (0xBD4C0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_5 (0xBD4D0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_6 (0xBD4E0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_7 (0xBD4F0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D (0xBD500000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_1 (0xBD510000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_2 (0xBD520000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_3 (0xBD530000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_4 (0xBD540000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_5 (0xBD550000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_6 (0xBD560000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_7 (0xBD570000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_8 (0xBD580000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_9 (0xBD590000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_A (0xBD5A0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF (0xBD5B0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_1 (0xBD5C0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_2 (0xBD5D0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_3 (0xBD5E0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_ABB_MIXEDSYS (0xBD5F0000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MRX_DATA_DUMP (0xBD600000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_PCC_BB (0xBD610000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_U_MMW_PCC_BB_TOP_1 (0xBD620000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_LOG (0xBD660000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE0_COMDMA (0xBD670000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE1_COMDMA (0xBD680000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_MML1_MMW_TPC_468M_CK_ABUS_REG (0xBD690000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_TPC_M (0xBD700000)
+#define BASE_NADDR_MMW_TXDFE_PWR_WRAP_TPC_M_1 (0xBD780000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER (0xBD800000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER_RESERVED0 (0xBD804000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_EVTGEN (0xBD808000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_SLPC (0xBD80C000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_RESERVED1 (0xBD810000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_PAR_WRAP_SRAM_AO (0xBD820000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_CONFIG_AO_REG (0xBD821000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX0 (0xBD828000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX1 (0xBD829000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX2 (0xBD82A000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX3 (0xBD82B000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX0 (0xBD82C000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX1 (0xBD82D000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_SYS (0xBD82E000)
+#define BASE_NADDR_MMW_RXDFE_PAR_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xBD830000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CONFIG_REG (0xBD840000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MBIST_CAT_MBIST_TOP_CFG (0xBD844000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xBD850000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_RXDFE_BB_NR_MMW_DM_SEL_WRAP (0xBD860000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CS_SEL_WRAP (0xBD870000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_CMSEL_MMW (0xBD880000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_CMIPG_MMW (0xBD888000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_LOG (0xBD890000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MRSG (0xBD8A0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE0_COMDMA (0xBD8C0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_DMA_DESCRT (0xBD8D0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_0 (0xBD8F0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_1 (0xBD8F8000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_0 (0xBD900000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_0 (0xBD920000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_1 (0xBD920200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_2 (0xBD920400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_3 (0xBD920600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_4 (0xBD920800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_5 (0xBD920A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_6 (0xBD920C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_7 (0xBD920E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_0 (0xBD922000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_1 (0xBD922200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_2 (0xBD922400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_3 (0xBD922600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_4 (0xBD922800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_5 (0xBD922A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_6 (0xBD922C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_7 (0xBD922E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ1 (0xBD924000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_WM (0xBD92A000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TOT_PATT (0xBD92E000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_2 (0xBD940000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_2 (0xBD960000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_1 (0xBD980000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_0 (0xBD9A0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_1 (0xBD9A0200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_2 (0xBD9A0400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_3 (0xBD9A0600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_4 (0xBD9A0800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_5 (0xBD9A0A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_6 (0xBD9A0C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_7 (0xBD9A0E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_0 (0xBD9A2000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_1 (0xBD9A2200)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_2 (0xBD9A2400)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_3 (0xBD9A2600)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_4 (0xBD9A2800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_5 (0xBD9A2A00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_6 (0xBD9A2C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_7 (0xBD9A2E00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ1 (0xBD9A4000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_WM (0xBD9AA000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TOT_PATT (0xBD9AE000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_MBIST_CONFIG (0xBD9C0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_GLBCON (0xBD9F0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_SET (0xBDA00000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_HEADER (0xBDA04000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_STATUS (0xBDA08000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_P_REG (0xBDA10000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_L_REG (0xBDA20000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_IMM_REG (0xBDA30000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_P_REG (0xBDA40000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_L_REG (0xBDA50000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CS_AGC (0xBDA60000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_468 (0xBDA70000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_52 (0xBDA71000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_0 (0xBDA71800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_1 (0xBDA71C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC (0xBDA80000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_1 (0xBDA84000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_2 (0xBDA88000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_3 (0xBDA90000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_4 (0xBDAA0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_5 (0xBDAB0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_6 (0xBDAC0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_7 (0xBDAD0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_8 (0xBDAE0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_468 (0xBDAF0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_52 (0xBDAF1000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_0 (0xBDAF1800)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_1 (0xBDAF1C00)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xBDAFF000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_DM (0xBDB00000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD0_PM (0xBDBA0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD1_PM (0xBDBB0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_COREDBG (0xBDBD0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_GC_PM (0xBDBE0000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE1_COMDMA (0xBDBFE000)
+#define BASE_NADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ADC_TEST_ARBITOR (0xBDBFF000)
+ ////////////////////
+#define BASE_ADDR_RXDFESYS_BUS_CONFIG (0xB7000000)
+#define BASE_ADDR_RXDFESYS_CONFIG_REG (0xB7010000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DMA (0xB7020000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC (0xB7080000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC (0xB7090000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS (0xB70A0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC (0xB70B0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FC (0xB70C0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_ATIMER (0xB70D0000)
+#define BASE_ADDR_RXDFESYS_PCC (0xB70E0000)
+#define BASE_ADDR_RXDFESYS_MBIST_CONFIG (0xB70F0000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ (0xB7100000)
+#define BASE_ADDR_RXDFESYS_MRSG (0xB7110000)
+#define BASE_ADDR_RXDFESYS_GC_DBG (0xB7130000)
+#define BASE_ADDR_RXDFESYS_RXDFE_DUMP (0xB7140000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDCTC_SRAM (0xB7400000)
+#define BASE_ADDR_RXDFESYS_RXDFE_MS_SRAM (0xB7420000)
+#define BASE_ADDR_RXDFESYS_RXDFE_FCCALTC_SRAM (0xB7430000)
+#define BASE_ADDR_RXDFESYS_RXDFE_CQ_SRAM (0xB7440000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_PM_SRAM (0xB7450000)
+#define BASE_ADDR_RXDFESYS_RXDFE_AGCDC_DM_SRAM (0xB7460000)
+#define BASE_ADDR_MDPERI_MDCFGCTL (0xB0000000)
+#define BASE_ADDR_MDPERI_MDUART0 (0xB0010000)
+#define BASE_ADDR_MDPERI_MDGDMA (0xB0020000)
+#define BASE_ADDR_MDPERI_MDGPTM (0xB0030000)
+#define BASE_ADDR_MDPERI_USIM1 (0xB0040000)
+#define BASE_ADDR_MDPERI_USIM2 (0xB0050000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MISC_REG (0xB0060000)
+#define BASE_ADDR_MDPERI_MDCIRQ (0xB0070000)
+#define BASE_ADDR_MDPERI_MDL1_MODEM_TOPSM_PROTECT (0xB0080000)
+#define BASE_ADDR_MDPERI_COMDMA (0xB0090000)
+#define BASE_ADDR_MDPERI_PTP_THERM_CTRL (0xB00C0000)
+#define BASE_ADDR_MDPERI_MD_TOPSM (0xB00D0000)
+#define BASE_ADDR_MDPERI_MD_OSTIMER (0xB00E0000)
+#define BASE_ADDR_MDPERI_MDRGU (0xB00F0000)
+#define BASE_ADDR_MDPERI_MDSM_CORE_PWR_CTRL (0xB0100000)
+#define BASE_ADDR_MDPERI_MD_EINT (0xB0110000)
+#define BASE_ADDR_MDPERI_LOW_PWR_DBG_MON (0xB0120000)
+#define BASE_ADDR_MDPERI_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MDPERI_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MDPERI_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MDPERI_MDPAR_DBGMON (0xB0160000)
+#define BASE_ADDR_MDPERI_MD_PMS_CONFIG (0xB0170000)
+#define BASE_ADDR_MDPERI_MDPERISYS_MBIST_CONFIG (0xB0180000)
+#define BASE_ADDR_MDPERI_MDRXSYS_SRAM_AO (0xB0190000)
+#define BASE_ADDR_MDPERI_VU_SM_CONGIF_0 (0xB0191000)
+#define BASE_ADDR_MDPERI_VU_SM_CONGIF_1 (0xB0192000)
+#define BASE_ADDR_MDPERI_MDRXAO_CONFIG (0xB0193000)
+#define BASE_ADDR_MDPERI_RESERVED0 (0xB0194000)
+#define BASE_ADDR_MDPERI_BRP_SRAM_AO (0xB01A0000)
+#define BASE_ADDR_MDPERI_NRL2_SRAM_AO (0xB01B0000)
+#define BASE_ADDR_MDPERI_CLK_CTRL (0xB01C0000)
+#define BASE_ADDR_MDPERI_MDSYS_SRAM_AO (0xB01D0000)
+#define BASE_ADDR_MDPERI_MDDBGSYS (0xB0600000)
+#define BASE_ADDR_MDINFRA_I2C (0xB0400000)
+#define BASE_ADDR_MDINFRA_SOE (0xB0410000)
+#define BASE_ADDR_MDINFRA_BUSMON (0xB0420000)
+#define BASE_ADDR_MDINFRA_MDUART1 (0xB0430000)
+#define BASE_ADDR_MDINFRA_BUS2X_REG (0xB0440000)
+#define BASE_ADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG (0xB0450000)
+#define BASE_ADDR_MDINFRA_SHAOLIN_SEMAPHORE (0xB0460000)
+#define BASE_ADDR_MDINFRA_MDM (0xB0490000)
+#define BASE_ADDR_MDINFRA_SMI_CONFIG (0xB04A0000)
+#define BASE_ADDR_MDINFRA_BUS4X_REG (0xB04B0000)
+#define BASE_ADDR_MDINFRA_THROTTLE_CTRL_MDHW2EMI_CONFIG (0xB04C0000)
+#define BASE_ADDR_MDINFRA_LOG (0xB04F0000)
+#define BASE_ADDR_MDINFRA_HW_LOG (0xB0500000)
+#define BASE_ADDR_MDINFRA_ELM (0xB0520000)
+#define BASE_ADDR_MDINFRA_TRACE (0xB0540000)
+#define BASE_ADDR_MDINFRA_TRACE_NR_TOP_1 (0xB0550000)
+#define BASE_ADDR_MDINFRA_PPPHA (0xB0560000)
+#define BASE_ADDR_MDINFRA_SDF (0xB0570000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_AO_MISC_CTRL (0xB0260000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_SRAM_AO (0xB0270000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_MEM_DELSEL_CFG (0xB0280000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_MEM_DELSEL_CFG (0xB0281000)
+#define BASE_ADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE1_MEM_DELSEL_CFG (0xB0282000)
+#define BASE_ADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE2_MEM_DELSEL_CFG (0xB0283000)
+#define BASE_ADDR_MDMCU_SHAOLIN___RESERVED_SHAOLIN_CORE3_MEM_DELSEL_CFG (0xB0284000)
+#define BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER (0xB0290000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE0_REPAIR_CFG (0xB02A0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE1_REPAIR_CFG (0xB02A1000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE2_REPAIR_CFG (0xB02A2000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CORE3_REPAIR_CFG (0xB02A3000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_CM2_REPAIR_CFG (0xB02A4000)
+#define BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF (0xB02B0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__SHAOLIN_BUS_CONFIG (0xB02C0000)
+#define BASE_ADDR_MDMCU_SHAOLIN__BUSMPU_INFRA (0xB02D0000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB (0xB0300000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_VRB (0xB0301000)
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI (0xB0302000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUSMON (0xB0310000)
+#define BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG (0xB0320000)
+#define BASE_ADDR_MDCORESYS_MDMCU_COREBUS_INTF_CFG (0xB0330000)
+#define BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG (0xB0340000)
+#define BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI (0xB0350000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG (0xB0360000)
+#define BASE_ADDR_MDCORESYS_MDMCU_QOS_CTRL (0xB0380000)
+#define BASE_ADDR_MDCORESYS_SHAOLIN_QOS_CTRL (0xB0390000)
+#define BASE_ADDR_MDCORESYS_IA_MACRO_DELSEL_ADR_IF (0xB03B0000)
+#define BASE_ADDR_MDCORESYS_MDCORESYS_MBIST_MDCORE_FOR_CFG_DELSEL_CFG_WRAP (0xB03B1000)
+#define BASE_ADDR_USIP_USIP0_ITCM (0xB0800000)
+#define BASE_ADDR_USIP_USIP0_DTCM (0xB0840000)
+#define BASE_ADDR_USIP_USIP0_DEBUG (0xB0880000)
+#define BASE_ADDR_USIP_USIP1_ITCM (0xB0900000)
+#define BASE_ADDR_USIP_USIP1_DTCM (0xB0940000)
+#define BASE_ADDR_USIP_USIP1_DEBUG (0xB0980000)
+#define BASE_ADDR_USIP_SLOW_TCM (0xB0C00000)
+#define BASE_ADDR_USIP_MBIST_CONFIG (0xB0D00000)
+#define BASE_ADDR_USIP_MBIST_REPAIR_TOP_CFG_WRAP (0xB0D10000)
+#define BASE_ADDR_USIP_MBIST_DELSEL_TOP_CFG_WRAP (0xB0D20000)
+#define BASE_ADDR_USIP_USIPCORE_BUS_CONFIG (0xB0D30000)
+#define BASE_ADDR_USIP_CONFG (0xB0E00000)
+#define BASE_ADDR_USIP_DSPLOG (0xB0E20000)
+#define BASE_ADDR_USIP_CROSS_CORE_CTRL (0xB0E30000)
+#define BASE_ADDR_USIP_AFE (0xB0E40000)
+#define BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG (0xB0E50000)
+#define BASE_ADDR_USIP_SEMAPHORE (0xB0E60000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP (0xB2000000)
+#define BASE_ADDR_NRL2_NRL2_BUS_SMI (0xB2001000)
+#define BASE_ADDR_NRL2_VRB_MNG (0xB2002000)
+#define BASE_ADDR_NRL2_NRL2_MMU (0xB2003000)
+#define BASE_ADDR_NRL2_NRL2_SRAM_WRAP (0xB2004000)
+#define BASE_ADDR_NRL2_NRL2_TOP_CFG (0xB2005000)
+#define BASE_ADDR_NRL2_NRL2_LHIF (0xB2006000)
+#define BASE_ADDR_NRL2_NRL2_IPF_UL (0xB2007000)
+#define BASE_ADDR_NRL2_NRL2_IPF_DL (0xB2008000)
+#define BASE_ADDR_NRL2_NRL2_IPF_HPCNAT (0xB2009000)
+#define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (0xB200A000)
+#define BASE_ADDR_NRL2_NRL2_PPHY (0xB200B000)
+#define BASE_ADDR_NRL2_ROHC (0xB200C000)
+#define BASE_ADDR_NRL2_NRL2_CPHR_NR (0xB200D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_0 (0xB200E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_1 (0xB200F000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_DL_UPP (0xB2010000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_RDMA (0xB2011000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (0xB2012000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (0xB2013000)
+#define BASE_ADDR_NRL2_NRL2_UL_CIPHER_CONFIG (0xB2014000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_RETX (0xB2016000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_LHIF (0xB2017000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG (0xB2018000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG_REG (0xB2018000)
+#define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (0xB2019000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_NR (0xB201A000)
+#define BASE_ADDR_NRL2_NRL2_IPF_LOG (0xB201D000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (0xB201E000)
+#define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (0xB201F000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_QP (0xB2020000)
+#define BASE_ADDR_NRL2_DLSYS_4GPL_RDMA (0xB2021000)
+#define BASE_ADDR_NRL2_GEN95_QP (0xB2022000)
+#define BASE_ADDR_NRL2_GEN95_RDMA (0xB2023000)
+#define BASE_ADDR_NRL2_GEN95_CPHR (0xB2024000)
+#define BASE_ADDR_NRL2_LTEDL_LMAC (0xB2025000)
+#define BASE_ADDR_NRL2_LTEDL_HARQ (0xB2026000)
+#define BASE_ADDR_NRL2_GEN95_BYC (0xB2027000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RULE (0xB2028000)
+#define BASE_ADDR_NRL2_DLSYS_5GPL_QP (0xB2029000)
+#define BASE_ADDR_NRL2_NRL2_IPF_RQ_TBL (0xB202A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_UPP (0xB202B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_DECPHR (0xB202C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (0xB202D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (0xB202E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_RETX (0xB2031000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_LHIF (0xB2032000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_GEN95 (0xB2033000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_DL_LMAC (0xB2035000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_1 (0xB2036000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_2 (0xB2037000)
+#define BASE_ADDR_NRL2_NRL2_METADATA_MNG_SRAM (0xB2038000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_TB_MAP_4 (0xB2039000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_ST (0xB203A000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_0 (0xB203B000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_1 (0xB203C000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_2 (0xB203D000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_3 (0xB203E000)
+#define BASE_ADDR_NRL2_NRL2_DL_UPP_REASB_WB_4 (0xB203F000)
+#define BASE_ADDR_NRL2_NRL2_DL_META_AGG (0xB2040000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC2 (0xB2041000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC3 (0xB2042000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC4 (0xB2043000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC5 (0xB2044000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC6 (0xB2045000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC7 (0xB2046000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_NR_CC8 (0xB2047000)
+#define BASE_ADDR_NRL2_NRL2_RDMA_UL_PPRO (0xB2048000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC2 (0xB2049000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC3 (0xB204A000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC4 (0xB204B000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC5 (0xB204C000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC6 (0xB204D000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC7 (0xB204E000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_NR_CC8 (0xB204F000)
+#define BASE_ADDR_NRL2_NRL2_WDMA_UL_PPRO (0xB2050000)
+#define BASE_ADDR_NRL2_NRL2_BUS_CFG (0xB2051000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_PPRO_QP (0xB2052000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_0 (0xB2053000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_1 (0xB2054000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_2 (0xB2055000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_3 (0xB2056000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_4 (0xB2057000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_5 (0xB2058000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_6 (0xB2059000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_7 (0xB205A000)
+#define BASE_ADDR_NRL2_NRL2_NRUL_COTF_QP_8 (0xB205B000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC0 (0xB205C000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC1 (0xB205D000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC2 (0xB205E000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC3 (0xB205F000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC4 (0xB2060000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC5 (0xB2061000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC6 (0xB2062000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC7 (0xB2063000)
+#define BASE_ADDR_NRL2_NRL2_PPHY_WDMA_UL_NR_CC8 (0xB2064000)
+#define BASE_ADDR_MCORE_MSYS_DSPM2VSCHEDULER (0xB4000000)
+#define BASE_ADDR_MCORE_MPERI_DSPCK_ABUS_REG (0xB4001000)
+#define BASE_ADDR_MCORE_MPERI_DBUS3_APB2DBUSCR_INST (0xB4002000)
+#define BASE_ADDR_MCORE_MML1_DSPM2DDMSCHEDULER (0xB4004000)
+#define BASE_ADDR_MCORE_MSYS_DSPCSIF (0xB4010000)
+#define BASE_ADDR_MCORE_MSYS_DSPMCORELOG (0xB4011000)
+#define BASE_ADDR_MCORE_MML1_DSPCBSCHEDULER (0xB4012000)
+#define BASE_ADDR_MCORE_MPERI_DSPCORECK_ABUS_REG (0xB4013000)
+#define BASE_ADDR_MCORE_MPERI_DBUS1_APB2DBUSCR_INST (0xB4014000)
+#define BASE_ADDR_MCORE_MPERI_A2D (0xB4016000)
+#define BASE_ADDR_MCORE_MPERI_DBUSRECORDER (0xB4017000)
+#define BASE_ADDR_MCORE_MSYS_DSPUSTIMER (0xB4018000)
+#define BASE_ADDR_MCORE_MSYS_PROFILING (0xB4019000)
+#define BASE_ADDR_MCORE_MML1_DSPMPPT (0xB401A000)
+#define BASE_ADDR_MCORE_MSYS_DSPBTDMA (0xB4021000)
+#define BASE_ADDR_MCORE_MSYS_DSPSWLA (0xB4022000)
+#define BASE_ADDR_MCORE_MPERI_DBUS2_APB2DBUSCR_INST (0xB4023000)
+#define BASE_ADDR_MCORE_MSYSY_GLBCON (0xB4030000)
+#define BASE_ADDR_MCORE_MSYS_DBGMON (0xB4031000)
+#define BASE_ADDR_MCORE_MPERI_PERICK_ABUS_REG (0xB4032000)
+#define BASE_ADDR_MCORE_MML1_MCOREPERI_ABUSMON (0xB4033000)
+#define BASE_ADDR_MCORE_MSYS_COMDMA (0xB4034000)
+#define BASE_ADDR_MCORE_MSYS_MBIST_CAT (0xB4040000)
+#define BASE_ADDR_MCORE_MCORE_L1_CACHE (0xB4100000)
+#define BASE_ADDR_MCORE_MCORE0_L1D_CACHE (0xB4101000)
+#define BASE_ADDR_MCORE_MCORE_CLKCTRL (0xB4102000)
+#define BASE_ADDR_MCORE_MCORE_EXCEPTION_CONTROLLER (0xB4103000)
+#define BASE_ADDR_MCORE_MCORE0_L1_PROFILING_UNIT (0xB4104000)
+#define BASE_ADDR_MCORE_MCORE_A2D (0xB4105000)
+#define BASE_ADDR_MCORE_MCORE0_A2D_128 (0xB4106000)
+#define BASE_ADDR_MCORE_MCORE_D2D (0xB4107000)
+#define BASE_ADDR_MCORE_MCORE_D2A (0xB4108000)
+#define BASE_ADDR_MCORE_DBUS_REG (0xB4109000)
+#define BASE_ADDR_MCORE_MSYS_ISRD (0xB4180000)
+#define BASE_ADDR_MCORE_MML1_DSPEINTC (0xB4181000)
+#define BASE_ADDR_MCORE_MSYS_DSPDBGC1 (0xB4182000)
+#define BASE_ADDR_MCORE_MSYS_DSPCTIWRAP (0xB4183000)
+#define BASE_ADDR_MCORE_MCORE_CORE (0xB4200000)
+#define BASE_ADDR_MCORE_MCORE_L0I_CACHE (0xB4210000)
+#define BASE_ADDR_MCORE_MCORE_DATA_CACHE (0xB4211000)
+#define BASE_ADDR_MCORE_MCORE_TIMER (0xB4212000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD0_EXCTRL (0xB4213000)
+#define BASE_ADDR_MCORE_MCORE_PC_MONITOR (0xB4214000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD0_PROFILING_UNIT (0xB4215000)
+#define BASE_ADDR_MCORE_MCORE_MBIST_CONFIG_WRAP (0xB4216000)
+#define BASE_ADDR_MCORE_MCORE_MCORE_CRIT_DBUS (0xB4217000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_SONIC (0xB4220000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_L0I_CACHE (0xB4230000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_L0D_CACHE (0xB4231000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_TIMER (0xB4232000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_EXCTRL (0xB4233000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_PC_MONITOR (0xB4234000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_PROFILING_UNIT (0xB4235000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_MBIST_CONFIG (0xB4236000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_DBUS_REG (0xB4237000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_SONIC (0xB4240000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_L0I_CACHE (0xB4250000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_L0D_CACHE (0xB4251000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_TIMER (0xB4252000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_EXCTRL (0xB4253000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_PC_MONITOR (0xB4254000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_PROFILING_UNIT (0xB4255000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_MBIST_CONFIG (0xB4256000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_DBUS_REG (0xB4257000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_SONIC (0xB4260000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_L0I_CACHE (0xB4270000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_L0D_CACHE (0xB4271000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_TIMER (0xB4272000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_EXCTRL (0xB4273000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_PC_MONITOR (0xB4274000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_PROFILING_UNIT (0xB4275000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_MBIST_CONFIG (0xB4276000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_DBUS_REG (0xB4277000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_SONIC (0xB4280000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_L0I_CACHE (0xB4290000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_L0D_CACHE (0xB4291000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_TIMER (0xB4292000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_EXCTRL (0xB4293000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_PC_MONITOR (0xB4294000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_PROFILING_UNIT (0xB4295000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_MBIST_CONFIG (0xB4296000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_DBUS_REG (0xB4297000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_SONIC (0xB42A0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_L0I_CACHE (0xB42B0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_L0D_CACHE (0xB42B1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_TIMER (0xB42B2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_EXCTRL (0xB42B3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_PC_MONITOR (0xB42B4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_PROFILING_UNIT (0xB42B5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_MBIST_CONFIG (0xB42B6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_DBUS_REG (0xB42B7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_SONIC (0xB42C0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_L0I_CACHE (0xB42D0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_L0D_CACHE (0xB42D1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_TIMER (0xB42D2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_EXCTRL (0xB42D3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_PC_MONITOR (0xB42D4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_PROFILING_UNIT (0xB42D5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_MBIST_CONFIG (0xB42D6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_DBUS_REG (0xB42D7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_SONIC (0xB42E0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_L0I_CACHE (0xB42F0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_L0D_CACHE (0xB42F1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_TIMER (0xB42F2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_EXCTRL (0xB42F3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_PC_MONITOR (0xB42F4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_PROFILING_UNIT (0xB42F5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_MBIST_CONFIG (0xB42F6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_DBUS_REG (0xB42F7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_SONIC (0xB4300000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_L0I_CACHE (0xB4310000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_L0D_CACHE (0xB4311000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_TIMER (0xB4312000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_EXCTRL (0xB4313000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_PC_MONITOR (0xB4314000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_PROFILING_UNIT (0xB4315000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_MBIST_CONFIG (0xB4316000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_DBUS_REG (0xB4317000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_SONIC (0xB4320000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_L0I_CACHE (0xB4330000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_L0D_CACHE (0xB4331000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_TIMER (0xB4332000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_EXCTRL (0xB4333000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_PC_MONITOR (0xB4334000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_PROFILING_UNIT (0xB4335000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_MBIST_CONFIG (0xB4336000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_DBUS_REG (0xB4337000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_SONIC (0xB4340000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_L0I_CACHE (0xB4350000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_L0D_CACHE (0xB4351000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_TIMER (0xB4352000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_EXCTRL (0xB4353000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_PC_MONITOR (0xB4354000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_PROFILING_UNIT (0xB4355000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_MBIST_CONFIG (0xB4356000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_DBUS_REG (0xB4357000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_SONIC (0xB4360000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_L0I_CACHE (0xB4370000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_L0D_CACHE (0xB4371000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_TIMER (0xB4372000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_EXCTRL (0xB4373000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_PC_MONITOR (0xB4374000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_PROFILING_UNIT (0xB4375000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_MBIST_CONFIG (0xB4376000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_DBUS_REG (0xB4377000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_SONIC (0xB4380000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_L0I_CACHE (0xB4390000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_L0D_CACHE (0xB4391000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_TIMER (0xB4392000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_EXCTRL (0xB4393000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_PC_MONITOR (0xB4394000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_PROFILING_UNIT (0xB4395000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_MBIST_CONFIG (0xB4396000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_DBUS_REG (0xB4397000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_SONIC (0xB43A0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_L0I_CACHE (0xB43B0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_L0D_CACHE (0xB43B1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_TIMER (0xB43B2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_EXCTRL (0xB43B3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_PC_MONITOR (0xB43B4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_PROFILING_UNIT (0xB43B5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_MBIST_CONFIG (0xB43B6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_DBUS_REG (0xB43B7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_SONIC (0xB43C0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_L0I_CACHE (0xB43D0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_L0D_CACHE (0xB43D1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_TIMER (0xB43D2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_EXCTRL (0xB43D3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_PC_MONITOR (0xB43D4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_PROFILING_UNIT (0xB43D5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_MBIST_CONFIG (0xB43D6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_DBUS_REG (0xB43D7000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_SONIC (0xB43E0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_L0I_CACHE (0xB43F0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_L0D_CACHE (0xB43F1000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_TIMER (0xB43F2000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_EXCTRL (0xB43F3000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_PC_MONITOR (0xB43F4000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_PROFILING_UNIT (0xB43F5000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_MBIST_CONFIG (0xB43F6000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_DBUS_REG (0xB43F7000)
+#define BASE_ADDR_MCORE_MCORE0_L1I_CACHE (0xB4800000)
+#define BASE_ADDR_MCORE_MCORE0_L1D_CACHE_1 (0xB4900000)
+#define BASE_ADDR_MCORE_THREAD0_ICM (0xB4A00000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD0_SONIC_RESERVED0 (0xB4A04000)
+#define BASE_ADDR_MCORE_THREAD1_ICM (0xB4A10000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD1_SONIC_RESERVED1 (0xB4A14000)
+#define BASE_ADDR_MCORE_THREAD2_ICM (0xB4A20000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD2_SONIC_RESERVED2 (0xB4A24000)
+#define BASE_ADDR_MCORE_THREAD3_ICM (0xB4A30000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD3_SONIC_RESERVED3 (0xB4A34000)
+#define BASE_ADDR_MCORE_THREAD4_ICM (0xB4A40000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD4_SONIC_RESERVED4 (0xB4A44000)
+#define BASE_ADDR_MCORE_THREAD5_ICM (0xB4A50000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD5_SONIC_RESERVED5 (0xB4A54000)
+#define BASE_ADDR_MCORE_THREAD6_ICM (0xB4A60000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD6_SONIC_RESERVED6 (0xB4A64000)
+#define BASE_ADDR_MCORE_THREAD7_ICM (0xB4A70000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD7_SONIC_RESERVED7 (0xB4A74000)
+#define BASE_ADDR_MCORE_THREAD8_ICM (0xB4A80000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD8_SONIC_RESERVED8 (0xB4A84000)
+#define BASE_ADDR_MCORE_THREAD9_ICM (0xB4A90000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD9_SONIC_RESERVED9 (0xB4A94000)
+#define BASE_ADDR_MCORE_THREAD10_ICM (0xB4AA0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD10_SONIC_RESERVED10 (0xB4AA4000)
+#define BASE_ADDR_MCORE_THREAD11_ICM (0xB4AB0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD11_SONIC_RESERVED11 (0xB4AB4000)
+#define BASE_ADDR_MCORE_THREAD12_ICM (0xB4AC0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD12_SONIC_RESERVED12 (0xB4AC4000)
+#define BASE_ADDR_MCORE_THREAD13_ICM (0xB4AD0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD13_SONIC_RESERVED13 (0xB4AD4000)
+#define BASE_ADDR_MCORE_THREAD14_ICM (0xB4AE0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD14_SONIC_RESERVED14 (0xB4AE4000)
+#define BASE_ADDR_MCORE_THREAD15_ICM (0xB4AF0000)
+#define BASE_ADDR_MCORE_MCORE0_THREAD15_SONIC_RESERVED15 (0xB4AF4000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM0 (0xB4F00000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM1 (0xB4F40000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM2 (0xB4F80000)
+#define BASE_ADDR_MCORE_MSYS_O_L2TCM3 (0xB4FC0000)
+#define BASE_ADDR_MCORE_MML1_MCORESYS_SHDM (0xB4FFC000)
+#define BASE_ADDR_VCORE_VSYS_DSPSLVSCHEDULER (0xB5000000)
+#define BASE_ADDR_VCORE_VSYS_DSPVCORELOG (0xB5001000)
+#define BASE_ADDR_VCORE_VSYS_VU2GRAM (0xB5002000)
+#define BASE_ADDR_VCORE_VPERI_DBUS1_APB2DBUSCR_INST (0xB5003000)
+#define BASE_ADDR_VCORE_VPERI_A2D (0xB5004000)
+#define BASE_ADDR_VCORE_VPERI_DBUSRECORDER (0xB5005000)
+#define BASE_ADDR_VCORE_VSYS_DBGMON (0xB5006000)
+#define BASE_ADDR_VCORE_VSYS_GLBCON (0xB5007000)
+#define BASE_ADDR_VCORE_VPERI_DSPCORECK_ABUS_REG (0xB5008000)
+#define BASE_ADDR_VCORE_VSYS_SWLA (0xB5010000)
+#define BASE_ADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST (0xB5011000)
+#define BASE_ADDR_VCORE_VPERI_DBUS2_APB2DBUSCR_INST_1 (0xB5011100)
+#define BASE_ADDR_VCORE_VPERI_PERICK_ABUS_REG (0xB5014000)
+#define BASE_ADDR_VCORE_MBIST_CAT_BUS_DECODER (0xB5020000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_L1_CACHE (0xB5100000)
+#define BASE_ADDR_VCORE_VCORE0_L1D_CACHE (0xB5101000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CLKCTRL (0xB5102000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_EXCEPTION_CONTROLLER (0xB5103000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_PROFILING_UNIT (0xB5104000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_A2D (0xB5105000)
+#define BASE_ADDR_VCORE_VCORE0_A2D_128 (0xB5106000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_D2D (0xB5107000)
+#define BASE_ADDR_VCORE_DBUS_REG (0xB5108000)
+#define BASE_ADDR_VCORE_MML1_DSPEINTC (0xB5180000)
+#define BASE_ADDR_VCORE_VSYS_DSPDBGC1 (0xB5181000)
+#define BASE_ADDR_VCORE_VSYS_DSPCTIWRAP (0xB5182000)
+#define BASE_ADDR_VCORE_VSYS_DSPCTIWRAP_1 (0xB5182020)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_CORE (0xB5200000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_L0I_CACHE (0xB5210000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_DATA_CACHE (0xB5211000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_TIMER (0xB5212000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD0_EXCTRL (0xB5213000)
+#define BASE_ADDR_VCORE_MML1_DSPVCORE_TOP_PC_MONITOR (0xB5214000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD0_PROFILING_UNIT (0xB5215000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_L1 (0xB5220000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_BLAZE (0xB5230000)
+#define BASE_ADDR_VCORE_VCORE0_VU0_VMEM_CFG (0xB5231000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_HLSU (0xB5232000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_PROFILING_UNIT (0xB5233000)
+#define BASE_ADDR_VCORE_VCORE_VU_MBIST_CONFIG (0xB5234000)
+#define BASE_ADDR_VCORE_VCORE_VU_TOP_VCORE_VU_DBUS (0xB5235000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_SONIC (0xB5240000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_L0I_CACHE (0xB5250000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_L0D_CACHE (0xB5251000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_TIMER (0xB5252000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_EXCTRL (0xB5253000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_PC_MONITOR (0xB5254000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_PROFILING_UNIT (0xB5255000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_VMEM_MEM (0xB5260000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_BLAZE (0xB5270000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_VMEM_CFG (0xB5271000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_HLSU (0xB5272000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_PROFILING_UNIT (0xB5273000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_MBIST_CONFIG (0xB5274000)
+#define BASE_ADDR_VCORE_VCORE0_VU1_DBUS_REG (0xB5275000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_SONIC (0xB5280000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_L0I_CACHE (0xB5290000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_L0D_CACHE (0xB5291000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_TIMER (0xB5292000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_EXCTRL (0xB5293000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_PC_MONITOR (0xB5294000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_PROFILING_UNIT (0xB5295000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_VMEM_MEM (0xB52A0000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_BLAZE (0xB52B0000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_VMEM_CFG (0xB52B1000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_HLSU (0xB52B2000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_PROFILING_UNIT (0xB52B3000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_MBIST_CONFIG (0xB52B4000)
+#define BASE_ADDR_VCORE_VCORE0_VU2_DBUS_REG (0xB52B5000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_SONIC (0xB52C0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_L0I_CACHE (0xB52D0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_L0D_CACHE (0xB52D1000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_TIMER (0xB52D2000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_EXCTRL (0xB52D3000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_PC_MONITOR (0xB52D4000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_PROFILING_UNIT (0xB52D5000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_VMEM_MEM (0xB52E0000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_BLAZE (0xB52F0000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_VMEM_CFG (0xB52F1000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_HLSU (0xB52F2000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_PROFILING_UNIT (0xB52F3000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_MBIST_CONFIG (0xB52F4000)
+#define BASE_ADDR_VCORE_VCORE0_VU3_DBUS_REG (0xB52F5000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_SONIC (0xB5300000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_L0I_CACHE (0xB5310000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_L0D_CACHE (0xB5311000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_TIMER (0xB5312000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_EXCTRL (0xB5313000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_PC_MONITOR (0xB5314000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_PROFILING_UNIT (0xB5315000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_VMEM_MEM (0xB5320000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_BLAZE (0xB5330000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_VMEM_CFG (0xB5331000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_HLSU (0xB5332000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_PROFILING_UNIT (0xB5333000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_MBIST_CONFIG (0xB5334000)
+#define BASE_ADDR_VCORE_VCORE0_VU4_DBUS_REG (0xB5335000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_SONIC (0xB5340000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_L0I_CACHE (0xB5350000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_L0D_CACHE (0xB5351000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_TIMER (0xB5352000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_EXCTRL (0xB5353000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_PC_MONITOR (0xB5354000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_PROFILING_UNIT (0xB5355000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_VMEM_MEM (0xB5360000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_BLAZE (0xB5370000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_VMEM_CFG (0xB5371000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_HLSU (0xB5372000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_PROFILING_UNIT (0xB5373000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_MBIST_CONFIG (0xB5374000)
+#define BASE_ADDR_VCORE_VCORE0_VU5_DBUS_REG (0xB5375000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_SONIC (0xB5380000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_L0I_CACHE (0xB5390000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_L0D_CACHE (0xB5391000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_TIMER (0xB5392000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_EXCTRL (0xB5393000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_PC_MONITOR (0xB5394000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_PROFILING_UNIT (0xB5395000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_VMEM_MEM (0xB53A0000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_BLAZE (0xB53B0000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_VMEM_CFG (0xB53B1000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_HLSU (0xB53B2000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_PROFILING_UNIT (0xB53B3000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_MBIST_CONFIG (0xB53B4000)
+#define BASE_ADDR_VCORE_VCORE0_VU6_DBUS_REG (0xB53B5000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_SONIC (0xB53C0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_L0I_CACHE (0xB53D0000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_L0D_CACHE (0xB53D1000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_TIMER (0xB53D2000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_EXCTRL (0xB53D3000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_PC_MONITOR (0xB53D4000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_PROFILING_UNIT (0xB53D5000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_VMEM_MEM (0xB53E0000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_BLAZE (0xB53F0000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_VMEM_CFG (0xB53F1000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_HLSU (0xB53F2000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_PROFILING_UNIT (0xB53F3000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_MBIST_CONFIG (0xB53F4000)
+#define BASE_ADDR_VCORE_VCORE0_VU7_DBUS_REG (0xB53F5000)
+#define BASE_ADDR_VCORE_VCORE0_L1I_CACHE (0xB5800000)
+#define BASE_ADDR_VCORE_VCORE0_L1D_CACHE_1 (0xB5900000)
+#define BASE_ADDR_VCORE_THREAD0_ICM (0xB5A00000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD0_SONIC_RESERVED0 (0xB5A04000)
+#define BASE_ADDR_VCORE_THREAD1_ICM (0xB5A10000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD1_SONIC_RESERVED1 (0xB5A14000)
+#define BASE_ADDR_VCORE_THREAD2_ICM (0xB5A20000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD2_SONIC_RESERVED2 (0xB5A24000)
+#define BASE_ADDR_VCORE_THREAD3_ICM (0xB5A30000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD3_SONIC_RESERVED3 (0xB5A34000)
+#define BASE_ADDR_VCORE_THREAD4_ICM (0xB5A40000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD4_SONIC_RESERVED4 (0xB5A44000)
+#define BASE_ADDR_VCORE_THREAD5_ICM (0xB5A50000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD5_SONIC_RESERVED5 (0xB5A54000)
+#define BASE_ADDR_VCORE_THREAD6_ICM (0xB5A60000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD6_SONIC_RESERVED6 (0xB5A64000)
+#define BASE_ADDR_VCORE_THREAD7_ICM (0xB5A70000)
+#define BASE_ADDR_VCORE_VCORE0_THREAD7_SONIC_RESERVED7 (0xB5A74000)
+#define BASE_ADDR_GRAM_GRAM_BRIDGE (0xB6000000)
+#define BASE_ADDR_GRAM_GRAM_GLBCON (0xB6F00000)
+#define BASE_ADDR_GRAM_GRAMSYS_MBIST_MBIST_TOP_CFG (0xB6F10000)
+#define BASE_ADDR_GRAM_GRAM_BRIDGE_REG (0xB6F20000)
+#define BASE_ADDR_GRAM_GRAM_REG (0xB6F30000)
+#define BASE_ADDR_GRAM_GRAM_BUS_CONFIG (0xB6F40000)
+#define BASE_ADDR_2ND_ROM_TABLE_DAP_2ND_ROM (0xB0600000)
+#define BASE_ADDR_MDDBGSYS_DEM_DEM (0xB0601000)
+#define BASE_ADDR_MDPERISYS_MISC_REG_MDPERISYS_MISC_REG (0xB0602000)
+#define BASE_ADDR_MD_DBGMON_MD_DBGMON (0xB0603000)
+#define BASE_ADDR_MDPERI_CLKTL_MDPERI_CLKTL (0xB0603800)
+#define BASE_ADDR_IA_USIP_ECT_MD_CXCTI (0xB0604000)
+#define BASE_ADDR_VDSP_MD32_ECT_MD_CXCTI (0xB0605000)
+#define BASE_ADDR_DBGSYS_AO_MISC_DBGSYS_AO_MISC (0xB0606000)
+#define BASE_ADDR_TOPSM_PROTECT_MDL1_MODEM_TOPSM_PROTECT (0xB060B000)
+#define BASE_ADDR_TOPSM_MDL1_MODEM_TOPSM (0xB060C000)
+#define BASE_ADDR_OSTIMER_MD_OSTIMER (0xB060D000)
+#define BASE_ADDR_RGU_MDRGU_REG (0xB060E000)
+#define BASE_ADDR_MDSM_CORE_PWR_CTRL_MDSM_CORE_PWR_CTRL (0xB060F000)
+#define BASE_ADDR_MD_PLLMIXED_MD_PLLMIXED_REG (0xB0610000)
+#define BASE_ADDR_MD_GLOBALCON_MD_GLOBAL_CON_REG (0xB0611000)
+#define BASE_ADDR_MD_CLKSW_MD_CLKSW_REG (0xB0612000)
+#define BASE_ADDR_RAKE_BUS_INTF_RAKESYS_BUS_DBGAPB_INTF (0xB0614000)
+#define BASE_ADDR_RAKE_MD32_RAKE_MD32 (0xB0616000)
+#define BASE_ADDR_VDSP_1_MD32SCQ (0xB0618000)
+#define BASE_ADDR_VDSP_2_MD32SCQ (0xB0619000)
+#define BASE_ADDR_VDSP_3_MD32SCQ (0xB061A000)
+#define BASE_ADDR_VDSP_4_MD32SCQ (0xB061B000)
+#define BASE_ADDR_BIGRAM_BUS_INTF_BIGRAM_BUS_INTF (0xB061C000)
+#define BASE_ADDR_INR_BUS_INTF_INR_BUS_INTF (0xB061E000)
+#define BASE_ADDR_USIP0_USIP0 (0xB0620000)
+#define BASE_ADDR_USIP1_USIP1 (0xB0621000)
+#define BASE_ADDR_USIPCORE_BUS_INTF_USIPCORE_BUS_INTF (0xB0622000)
+#define BASE_ADDR_L2SRAM_L2SRAM (0xB0624000)
+#define BASE_ADDR_MDMCU_BUS_INTF_VDNR__MDMCU_BUS_INTF (0xB0628000)
+#define BASE_ADDR_MDMCU_COREBUS_INTF_VDNR__MDMCU_COREBUS_INTF (0xB062A000)
+#define BASE_ADDR_MDMCU_BUSMON_MDMCU_BUSMON (0xB062C000)
+#define BASE_ADDR_MDMCU_USIP_BUS_INTF_MDMCU_USIP_BUS_INTF (0xB062D000)
+#define BASE_ADDR_SHAOLIN_PDA_MON_SHAOLIN_PDA_MON (0xB0630000)
+#define BASE_ADDR_SHAOLIN_DEBUG_PERI_SHAOLIN_DEBUG_PERI (0xB0633000)
+#define BASE_ADDR_SHAOLIN_MACRO_BUS_INTF_VDNR__SHAOLIN_MACRO_BUS_INTF (0xB0634000)
+#define BASE_ADDR_SHAOLIN_BUSMPU_SHAOLIN_BUSMPU (0xB0636000)
+#define BASE_ADDR_SHAOLIN_CM2_SHAOLIN_CM2 (0xB0637000)
+#define BASE_ADDR_SHAOLIN_CORE0__SHAOLIN_CORE0 (0xB0638000)
+#define BASE_ADDR_SHAOLIN_CORE1_SHAOLIN_CORE1 (0xB0639000)
+#define BASE_ADDR_SHAOLIN_CORE2__SHAOLIN_CORE2 (0xB063A000)
+#define BASE_ADDR_SHAOLIN_CORE3_SHAOLIN_CORE3 (0xB063B000)
+#define BASE_ADDR_MDINFRA_BUS4X_REG_MDINFRA_BUS4X_REG (0xB063C000)
+#define BASE_ADDR_MDINFRA_BUS2X_REG_MDINFRA_BUS2X_REG (0xB063D000)
+#define BASE_ADDR_MDINFRA_BUSMON_MDINFRA_BUSMON (0xB063E000)
+#define BASE_ADDR_NRL2_BUS_INTF_NRL2_BUS_INTF (0xB0640000)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_RXCPC_NR_DBGAPB_MAS_BUS_INTF (0xB0642000)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_MAS_BUS_INTF_DIV2 (0xB0642800)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_RXCPC_NR_DBGAPB_SLV_BUS_INTF (0xB0643000)
+#define BASE_ADDR_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2_RXCPC_NR_DBGAPB_SLV_BUS_INTF_DIV2 (0xB0643800)
+#define BASE_ADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF (0xB0644000)
+#define BASE_ADDR_RXDDM_BUS_INTF_RXDDM_NR_SLV_BUS_INTF_1 (0xB0645000)
+#define BASE_ADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF (0xB0646000)
+#define BASE_ADDR_RXDBRP_BUS_INTF_RXDBRP_NR_SLV_BUS_INTF_1 (0xB0647000)
+#define BASE_ADDR_MDAO_MAS_BUS_CK_DBG_MDAO_MAS_BUS_CK_DBG (0xB0648000)
+#define BASE_ADDR_MDAO_SLV_BUS_CK_DBG_MDAO_SLV_BUS_CK_DBG (0xB0649000)
+#define BASE_ADDR_MD_DVFS_TOP_CK_DBG_MD_DVFS_TOP_CK_DBG (0xB0649800)
+#define BASE_ADDR_MDL1_TOPSM_MDL1_TOPSM (0xB064A000)
+#define BASE_ADDR_RFSLPC_RFSLPC (0xB064B000)
+#define BASE_ADDR_MD2G_BUS_MD2G_BUS (0xB064C000)
+#define BASE_ADDR_CSSYS_BUS_CK_DBG_CSSYS_BUS_CK_DBG (0xB064E000)
+#define BASE_ADDR_CSSYS_BUS_DIV2_CK_DBG_CSSYS_BUS_DIV2_CK_DBG (0xB064E800)
+#define BASE_ADDR_MDAO_BUS_CK_DBG_MDAO_BUS_CK_DBG (0xB064F000)
+#define BASE_ADDR_VCORE_TOP_TH0_SONIC_VCORE (0xB0650000)
+#define BASE_ADDR_VCORE_TOP_TH0_PC_MONITOR_VCORE (0xB0650400)
+#define BASE_ADDR_VCORE_TOP_TH0_VUDBUS_VCORE (0xB0650480)
+#define BASE_ADDR_VCORE_TOP_TH1_SONIC_VCORE (0xB0650600)
+#define BASE_ADDR_VCORE_TOP_TH1_PC_MONITOR_VCORE (0xB0650A00)
+#define BASE_ADDR_VCORE_TOP_TH1_VUDBUS_VCORE (0xB0650A80)
+#define BASE_ADDR_VCORE_TOP_TH2_SONIC_VCORE (0xB0650C00)
+#define BASE_ADDR_VCORE_TOP_TH2_PC_MONITOR_VCORE (0xB0651000)
+#define BASE_ADDR_VCORE_TOP_TH2_VUDBUS_VCORE (0xB0651080)
+#define BASE_ADDR_VCORE_TOP_TH3_SONIC_VCORE (0xB0651200)
+#define BASE_ADDR_VCORE_TOP_TH3_PC_MONITOR_VCORE (0xB0651600)
+#define BASE_ADDR_VCORE_TOP_TH3_VUDBUS_VCORE (0xB0651680)
+#define BASE_ADDR_VCORE_TOP_TH4_SONIC_VCORE (0xB0651800)
+#define BASE_ADDR_VCORE_TOP_TH4_PC_MONITOR_VCORE (0xB0651C00)
+#define BASE_ADDR_VCORE_TOP_TH4_VUDBUS_VCORE (0xB0651C80)
+#define BASE_ADDR_VCORE_TOP_TH5_SONIC_VCORE (0xB0651E00)
+#define BASE_ADDR_VCORE_TOP_TH5_PC_MONITOR_VCORE (0xB0652200)
+#define BASE_ADDR_VCORE_TOP_TH5_VUDBUS_VCORE (0xB0652280)
+#define BASE_ADDR_VCORE_TOP_TH6_SONIC_VCORE (0xB0652400)
+#define BASE_ADDR_VCORE_TOP_TH6_PC_MONITOR_VCORE (0xB0652800)
+#define BASE_ADDR_VCORE_TOP_TH6_VUDBUS_VCORE (0xB0652880)
+#define BASE_ADDR_VCORE_TOP_TH7_SONIC_VCORE (0xB0652A00)
+#define BASE_ADDR_VCORE_TOP_TH7_PC_MONITOR_VCORE (0xB0652E00)
+#define BASE_ADDR_VCORE_TOP_TH7_VUDBUS_VCORE (0xB0652E80)
+#define BASE_ADDR_VCORE_TOP_L1_DBUS_VCORE (0xB0653000)
+#define BASE_ADDR_VCORE_TOP_A2D32_VCORE (0xB0654000)
+#define BASE_ADDR_VCORE_TOP_A2D128_VCORE (0xB0654080)
+#define BASE_ADDR_VCORECK_ABUS_VCORECK_ABUS (0xB0655000)
+#define BASE_ADDR_VCORE_DIV2CK_ABUS_VCORE_DIV2CK_ABUS (0xB0655800)
+#define BASE_ADDR_VCORE_CK_DBUS_VCORE_CK_DBUS (0xB0656000)
+#define BASE_ADDR_VCORE_DIV2CK_DBUS_VCORE_DIV2CK_DBUS (0xB0656800)
+#define BASE_ADDR_BUS_RECORDER_BUS_RECORDER (0xB0657000)
+#define BASE_ADDR_VPERIA2D_DBGAPB_VPERIA2D_DBGAPB (0xB0657800)
+#define BASE_ADDR_DEBUG_MONITOR_FOR_DBG_FLAG_MML1_DSPVCORE_DBGMON_WRAP (0xB0657880)
+#define BASE_ADDR_VCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_VCORE_MML1_DSPCTIWRAP (0xB0657900)
+#define BASE_ADDR_VCORE_PAR_AO_CR_VCORE_PAR_AO_CR (0xB0657A00)
+#define BASE_ADDR_GRAM_PERI_GRAM_PERI (0xB0658000)
+#define BASE_ADDR_MCORE0_TOP_TH0_SONIC_MCORE0 (0xB0660000)
+#define BASE_ADDR_MCORE0_TOP_TH0_PC_MONITOR_MCORE0 (0xB0660400)
+#define BASE_ADDR_MCORE0_TOP_TH0_VUDBUS_MCORE0 (0xB0660480)
+#define BASE_ADDR_MCORE0_TOP_TH1_SONIC_MCORE0 (0xB0660600)
+#define BASE_ADDR_MCORE0_TOP_TH1_PC_MONITOR_MCORE0 (0xB0660A00)
+#define BASE_ADDR_MCORE0_TOP_TH1_VUDBUS_MCORE0 (0xB0660A80)
+#define BASE_ADDR_MCORE0_TOP_TH2_SONIC_MCORE0 (0xB0660C00)
+#define BASE_ADDR_MCORE0_TOP_TH2_PC_MONITOR_MCORE0 (0xB0661000)
+#define BASE_ADDR_MCORE0_TOP_TH2_VUDBUS_MCORE0 (0xB0661080)
+#define BASE_ADDR_MCORE0_TOP_TH3_SONIC_MCORE0 (0xB0661200)
+#define BASE_ADDR_MCORE0_TOP_TH3_PC_MONITOR_MCORE0 (0xB0661600)
+#define BASE_ADDR_MCORE0_TOP_TH3_VUDBUS_MCORE0 (0xB0661680)
+#define BASE_ADDR_MCORE0_TOP_TH4_SONIC_MCORE0 (0xB0661800)
+#define BASE_ADDR_MCORE0_TOP_TH4_PC_MONITOR_MCORE0 (0xB0661C00)
+#define BASE_ADDR_MCORE0_TOP_TH4_VUDBUS_MCORE0 (0xB0661C80)
+#define BASE_ADDR_MCORE0_TOP_TH5_SONIC_MCORE0 (0xB0661E00)
+#define BASE_ADDR_MCORE0_TOP_TH5_PC_MONITOR_MCORE0 (0xB0662200)
+#define BASE_ADDR_MCORE0_TOP_TH5_VUDBUS_MCORE0 (0xB0662280)
+#define BASE_ADDR_MCORE0_TOP_TH6_SONIC_MCORE0 (0xB0662400)
+#define BASE_ADDR_MCORE0_TOP_TH6_PC_MONITOR_MCORE0 (0xB0662800)
+#define BASE_ADDR_MCORE0_TOP_TH6_VUDBUS_MCORE0 (0xB0662880)
+#define BASE_ADDR_MCORE0_TOP_TH7_SONIC_MCORE0 (0xB0662A00)
+#define BASE_ADDR_MCORE0_TOP_TH7_PC_MONITOR_MCORE0 (0xB0662E00)
+#define BASE_ADDR_MCORE0_TOP_TH7_VUDBUS_MCORE0 (0xB0662E80)
+#define BASE_ADDR_MCORE0_TOP_TH8_SONIC_MCORE0 (0xB0663000)
+#define BASE_ADDR_MCORE0_TOP_TH8_PC_MONITOR_MCORE0 (0xB0663400)
+#define BASE_ADDR_MCORE0_TOP_TH8_VUDBUS_MCORE0 (0xB0663480)
+#define BASE_ADDR_MCORE0_TOP_TH9_SONIC_MCORE0 (0xB0663600)
+#define BASE_ADDR_MCORE0_TOP_TH9_PC_MONITOR_MCORE0 (0xB0663A00)
+#define BASE_ADDR_MCORE0_TOP_TH9_VUDBUS_MCORE0 (0xB0663A80)
+#define BASE_ADDR_MCORE0_TOP_TH10_SONIC_MCORE0 (0xB0663C00)
+#define BASE_ADDR_MCORE0_TOP_TH10_PC_MONITOR_MCORE0 (0xB0664000)
+#define BASE_ADDR_MCORE0_TOP_TH10_VUDBUS_MCORE0 (0xB0664080)
+#define BASE_ADDR_MCORE0_TOP_TH11_SONIC_MCORE0 (0xB0664200)
+#define BASE_ADDR_MCORE0_TOP_TH11_PC_MONITOR_MCORE0 (0xB0664600)
+#define BASE_ADDR_MCORE0_TOP_TH11_VUDBUS_MCORE0 (0xB0664680)
+#define BASE_ADDR_MCORE0_TOP_TH12_SONIC_MCORE0 (0xB0664800)
+#define BASE_ADDR_MCORE0_TOP_TH12_PC_MONITOR_MCORE0 (0xB0664C00)
+#define BASE_ADDR_MCORE0_TOP_TH12_VUDBUS_MCORE0 (0xB0664C80)
+#define BASE_ADDR_MCORE0_TOP_TH13_SONIC_MCORE0 (0xB0664E00)
+#define BASE_ADDR_MCORE0_TOP_TH13_PC_MONITOR_MCORE0 (0xB0665200)
+#define BASE_ADDR_MCORE0_TOP_TH13_VUDBUS_MCORE0 (0xB0665280)
+#define BASE_ADDR_MCORE0_TOP_TH14_SONIC_MCORE0 (0xB0665400)
+#define BASE_ADDR_MCORE0_TOP_TH14_PC_MONITOR_MCORE0 (0xB0665800)
+#define BASE_ADDR_MCORE0_TOP_TH14_VUDBUS_MCORE0 (0xB0665880)
+#define BASE_ADDR_MCORE0_TOP_TH15_SONIC_MCORE0 (0xB0665A00)
+#define BASE_ADDR_MCORE0_TOP_TH15_PC_MONITOR_MCORE0 (0xB0665E00)
+#define BASE_ADDR_MCORE0_TOP_TH15_VUDBUS_MCORE0 (0xB0665E80)
+#define BASE_ADDR_MCORE0_TOP_L1DBUS_MCORE0 (0xB0666000)
+#define BASE_ADDR_MCORE0_TOP_L1I_CACHE_MCORE0 (0xB0667000)
+#define BASE_ADDR_MCORE0_TOP_L1D_CACHE_MCORE0 (0xB0667200)
+#define BASE_ADDR_MCORE0_TOP_A2D32_MCORE0 (0xB0667400)
+#define BASE_ADDR_MCORE0_TOP_A2D128_MCORE0 (0xB0667480)
+#define BASE_ADDR_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCORECK_ABUS_REG_DBGAPB (0xB0670000)
+#define BASE_ADDR_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB_MML1_MPERI_DSPCK_ABUS_REG_DBGAPB (0xB0671000)
+#define BASE_ADDR_MML1_MPERI_PERICK_ABUS_REG_DBGAPB_MML1_MPERI_PERICK_ABUS_REG_DBGAPB (0xB0672000)
+#define BASE_ADDR_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB_MCORE_MML1_DSPCTIWRAP_TOP_DBGAPB (0xB0673000)
+#define BASE_ADDR_MML1_MPERI_DSPCK_DBUS_REG_DBG_MML1_MPERI_DSPCK_DBUS_REG_DBG (0xB0674000)
+#define BASE_ADDR_MML1_MPERI_PERICK_DBUS_REG_DBG_MML1_MPERI_PERICK_DBUS_REG_DBG (0xB0675000)
+#define BASE_ADDR_MML1_MCOREPERI_ABUSMON_TOP_DBG_MML1_MCOREPERI_ABUSMON_TOP_DBG (0xB0676000)
+#define BASE_ADDR_MML1_MPERI_DBUSRECORDER_DBG_MML1_MPERI_DBUSRECORDER_DBG (0xB0677000)
+#define BASE_ADDR_MPERIA2D_DBGAPB_MPERIA2D_DBGAPB (0xB0678000)
+#define BASE_ADDR_MML1_MCORESYS_DBGMON_WRAP_MML1_MCORESYS_DBGMON_WRAP (0xB0679000)
+#define BASE_ADDR_MML1_MPERI_DSPCORECK_DBUS_REG_DBG_MML1_MPERI_DSPCORECK_DBUS_REG_DBG (0xB067A000)
+#define BASE_ADDR_CMCS_MAS_MDTOP_BUS4X_CK_REG_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0680000)
+#define BASE_ADDR_CMCS_SLV_MDTOP_BUS4X_CK_REG_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0681000)
+#define BASE_ADDR_CM_CS_BUS_CK_REG_MML1_CM_CS_BUS_CK_ABUS_REG (0xB0682000)
+#define BASE_ADDR_CS_NR_BUS_CK_REG_MML1_CS_NR_BUS_CK_ABUS_REG (0xB0683000)
+#define BASE_ADDR_CMCS_NR_CM_NR_CK_REG_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xB0684000)
+#define BASE_ADDR_CM_NR_MDTOP_BUS4X_CK_REG_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xB0685000)
+#define BASE_ADDR_CMCS_NR_RXTFC_NR_CK_REG_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xB0686000)
+#define BASE_ADDR_RXTFC_MDTOP_BUS4X_CK_REG_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xB0687000)
+#define BASE_ADDR_CMCS_NR_RXTDB_NR_CK_REG_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xB0688000)
+#define BASE_ADDR_RXTDB_MDTOP_BUS4X_CK_REG_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xB0689000)
+#define BASE_ADDR_CMCS_NR_RXTDB_PBCH_NR_CK_REG_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xB068A000)
+#define BASE_ADDR_RXTDB_PBCH_MDTOP_BUS4X_CK_REG_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xB068B000)
+#define BASE_ADDR_TX_NR_MAS_TXBSRP_NR_CK_REG_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xB0690000)
+#define BASE_ADDR_TX_NR_MAS_MDTOP_BUS4X_CK_REG_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xB0691000)
+#define BASE_ADDR_TX_NR_SLV_TXBSRP_NR_CK_REG_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xB0692000)
+#define BASE_ADDR_TX_NR_SLV_MDTOP_BUS4X_CK_REG_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xB0693000)
+#define BASE_ADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF (0xB0694000)
+#define BASE_ADDR_RXBRP_BUS_INTF_RXBRP_BUS_INTF_1 (0xB0696000)
+#define BASE_ADDR_DFESYS_BUS_INTF_DFESYS_MAS_BUS_CONFIG_REAL (0xB0698000)
+#define BASE_ADDR_DFESYS_BUS_INTF_DFESYS_SLV_BUS_CONFIG (0xB069A000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_BUS_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xB069C000)
+#define BASE_ADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xB069D000)
+#define BASE_ADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xB069F0000)
+#define BASE_ADDR_MMW_RF_CTRL_BUS_INTF_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xB069F8000)
+#define BASE_ADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TXDFE_468M_CK_ABUS_REG (0xB06A0000)
+#define BASE_ADDR_MMW_TXDFE_BUS_INTF_MML1_MMW_TPC_468M_CK_ABUS_REG (0xB06A3000)
+#define BASE_ADDR_MMW_RXDFE_BUS_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xB06A4000)
+#define BASE_ADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xB06A5000)
+#define BASE_ADDR_MMW_RXDFE_BUS_INTF_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xB06A7000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR (0xB7000000)
+#define BASE_ADDR_RXDDM_NR_RESERVED0 (0xB7008000)
+#define BASE_ADDR_RXDDM_NR_RESERVED1 (0xB700A000)
+#define BASE_ADDR_RXDDM_NR_RESERVED2 (0xB700C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_CR_TOP_1 (0xB700E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_EGID (0xB7010000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_EGOC (0xB7012000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_GLOBAL_CON (0xB7014000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MBIST_CON (0xB7016000)
+#define BASE_ADDR_RXDDM_NR_RESERVED3 (0xB7018000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_STIME_LOG (0xB701A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MDCC (0xB701C000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DBRPIF (0xB701E000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_MCTRL (0xB7020000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_ROI (0xB7022000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_DCE (0xB7024000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_PP (0xB7026000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRQRD (0xB7028000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_SRCH (0xB702A000)
+#define BASE_ADDR_RXDDM_NR_RXDDM_NR_LLRGEN (0xB702C000)
+#define BASE_ADDR_RXDDM_NR_MML1_RXDDM_CK_ABUS_REG (0xB702E000)
+#define BASE_ADDR_RXDDM_NR_MML1_RXDDM_HALF_CK_ABUS_REG (0xB7030000)
+#define BASE_ADDR_RXDDM_NR_SLOT_RNTI (0xB7200000)
+#define BASE_ADDR_RXDDM_NR_RESERVED4 (0xB7201000)
+#define BASE_ADDR_RXDDM_NR_SYM (0xB7220000)
+#define BASE_ADDR_RXDDM_NR_RESERVED5 (0xB7228000)
+#define BASE_ADDR_RXDDM_NR_MASK_TYPE0 (0xB7240000)
+#define BASE_ADDR_RXDDM_NR_MASK_TYPE1 (0xB7260000)
+#define BASE_ADDR_RXCSI_NR_NR_CSI (0xB7400000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_GLOBAL_CON (0xB7500000)
+#define BASE_ADDR_RXCSI_NR_RXCSI_NR_MBIST_CON (0xB7501000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL (0xB7800000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRCTL_CR (0xB7810000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBOCTL (0xB7820000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DESCR (0xB7830000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DEREP (0xB7840000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CBRD (0xB7850000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_HARQ (0xB7860000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_LDPC (0xB7870000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_CRC (0xB7880000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DO (0xB7890000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_SHR_POOL (0xB78A0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT (0xB78B0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_1 (0xB78C0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_AXIPROT_2 (0xB78D0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DOPROT (0xB78E0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_TRACE (0xB78F0000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_GLOBAL_CON (0xB7900000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED_0 (0xB7910000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_IPG (0xB7920000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_DVTCRC (0xB7930000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_DELSEL_CFG_WRAP (0xB7940000)
+#define BASE_ADDR_RXDBRP_NR_RXDBRP_NR_MBIST_REPAIR_CFG (0xB7950000)
+#define BASE_ADDR_RXDBRP_NR_RESERVED_1 (0xB7960000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_EMI_CK_ABUS_REG (0xB7970000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_EMI_HALF_CK_ABUS_REG (0xB7980000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_SD_CK_ABUS_REG (0xB7990000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_SD_HALF_CK_ABUS_REG (0xB79A0000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_CK_ABUS_REG (0xB79B0000)
+#define BASE_ADDR_RXDBRP_NR_MML1_RXDBRP_HALF_CK_ABUS_REG (0xB79C0000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_GLOBAL_CON (0xB7C00000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CPC (0xB7C02000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_DELSEL_CFG_WRAP (0xB7C04000)
+#define BASE_ADDR_RXCPC_NR_RXPC_NR_REPAIR_CFG_WRAP (0xB7C06000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_DBGMON (0xB7C08000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_BUS_CONFIG (0xB7C0A000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_M_CK_ABUS_REG (0xB7C0C000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_M_HALF_CK_ABUS_REG (0xB7C0E000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_CK_ABUS_REG (0xB7C10000)
+#define BASE_ADDR_RXCPC_NR_MML1_RXCPC_HALF_CK_ABUS_REG (0xB7C12000)
+#define BASE_ADDR_RXCPC_NR_RESERVED0 (0xB7C14000)
+#define BASE_ADDR_RXCPC_NR_RESERVED1 (0xB7C16000)
+#define BASE_ADDR_RXCPC_NR_RXCPC_NR_CFG_SP (0xB7C20000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_TOPSM (0xB8000000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1 (0xB8010000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_CONFG (0xB8020000)
+#define BASE_ADDR_MODEML1_AO_TDMA_SLP (0xB8030000)
+#define BASE_ADDR_MODEML1_AO_TDD_SLP (0xB8040000)
+#define BASE_ADDR_MODEML1_AO_TDD_TIMER (0xB8050000)
+#define BASE_ADDR_MODEML1_AO_FDD_SLP (0xB8060000)
+#define BASE_ADDR_MODEML1_AO_FDD_TIMER (0xB8070000)
+#define BASE_ADDR_MODEML1_AO_LTE_SLP (0xB8080000)
+#define BASE_ADDR_MODEML1_AO_LTE_TIMER (0xB8090000)
+#define BASE_ADDR_MODEML1_AO_IDC_CTRL (0xB80A0000)
+#define BASE_ADDR_MODEML1_AO_IDC_UART (0xB80B0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_TIMER (0xB80C0000)
+#define BASE_ADDR_MODEML1_AO_C2K_1X_SLP (0xB80D0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_TIMER (0xB80E0000)
+#define BASE_ADDR_MODEML1_AO_C2K_DO_SLP (0xB80F0000)
+#define BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS (0xB8100000)
+#define BASE_ADDR_MODEML1_AO_MD_DVFS_TOP_CONFIG (0xB8110000)
+#define BASE_ADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0 (0xB8120000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM (0xB8130000)
+#define BASE_ADDR_MODEML1_AO_BSI_MM_MIPI (0xB8140000)
+#define BASE_ADDR_MODEML1_AO_MDL1_AO_BSI_MM2 (0xB8150000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MAS_BUS_CONFIG (0xB8160000)
+#define BASE_ADDR_MODEML1_AO_BPI_MM (0xB8170000)
+#define BASE_ADDR_MODEML1_AO_C1X_TTR (0xB8180000)
+#define BASE_ADDR_MODEML1_AO_CDO_TTR (0xB8190000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG (0xB81A0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_DELSEL_CFG (0xB81B0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_AO_MBIST_WRAPPER_REPAIR_CFG (0xB81B8000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_FREQM (0xB81C0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_SLP_CTRL (0xB81D0000)
+#define BASE_ADDR_MODEML1_AO_MM_EVENTGEN (0xB81E0000)
+#define BASE_ADDR_MODEML1_AO_MDAO_SMI (0xB81F0000)
+#define BASE_ADDR_MODEML1_AO_C1XEVT (0xB8200000)
+#define BASE_ADDR_MODEML1_AO_CDOEVT (0xB8210000)
+#define BASE_ADDR_MODEML1_AO_FDDEVT (0xB8220000)
+#define BASE_ADDR_MODEML1_AO_LTEEVT (0xB8230000)
+#define BASE_ADDR_MODEML1_AO_TDDEVT (0xB8240000)
+#define BASE_ADDR_MODEML1_AO_UCNT_D (0xB8250000)
+#define BASE_ADDR_MODEML1_AO_NR_TIMER (0xB8260000)
+#define BASE_ADDR_MODEML1_AO_NR_SLP (0xB8270000)
+#define BASE_ADDR_MODEML1_AO_NR_EVENTGEN (0xB8280000)
+#define BASE_ADDR_MODEML1_AO_TDMA_TMR (0xB8290000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_0 (0xB82A0000)
+#define BASE_ADDR_MODEML1_AO_RF_SLP_CTRL (0xB82B0000)
+#define BASE_ADDR_MODEML1_AO_U_DFESYS_MEM_CONFIG (0xB82C0000)
+#define BASE_ADDR_MODEML1_AO_DIGRF_MIPI_1 (0xB82D0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_0 (0xB82E0000)
+#define BASE_ADDR_MODEML1_AO_MODEML1_DVFS_CTRL_1 (0xB82F0000)
+#define BASE_ADDR_MODEML1_AO_U_MMW_TXDFE_MEM_CONFIG (0xB8300000)
+#define BASE_ADDR_MODEML1_AO_MD_GLOBAL_CON_DCM (0xB0130000)
+#define BASE_ADDR_MODEML1_AO_MD_PLLMIXED (0xB0140000)
+#define BASE_ADDR_MODEML1_AO_MD_CLKSW (0xB0150000)
+#define BASE_ADDR_MD2GSYS_IDMA_CM (0xB8400000)
+#define BASE_ADDR_MD2GSYS_IDMA_PM (0xB8500000)
+#define BASE_ADDR_MD2GSYS_IDMA_DM (0xB8600000)
+#define BASE_ADDR_MD2GSYS_MD2G_CONFG (0xB8700000)
+#define BASE_ADDR_MD2GSYS_MD2G_MBIST_CONFG (0xB8710000)
+#define BASE_ADDR_MD2GSYS_TDMA_BASE (0xB8720000)
+#define BASE_ADDR_MD2GSYS_APC (0xB8730000)
+#define BASE_ADDR_MD2GSYS_CSD_ACC (0xB8770000)
+#define BASE_ADDR_MD2GSYS_SHARE_D1 (0xB87A0000)
+#define BASE_ADDR_MD2GSYS_IRDBG (0xB87B0000)
+#define BASE_ADDR_MD2GSYS_PATCH (0xB87C0000)
+#define BASE_ADDR_MD2GSYS_AHB2DSPIO (0xB87F0000)
+#define BASE_ADDR_DFESYS_TXBSRP (0xB8800000)
+#define BASE_ADDR_DFESYS_TXCRP (0xB8900000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG0 (0xB8980000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG0 (0xB8990000)
+#define BASE_ADDR_DFESYS_RESERVED0 (0xB89A0000)
+#define BASE_ADDR_DFESYS_TPC_D (0xB8A00000)
+#define BASE_ADDR_DFESYS_TXDFE_D (0xB8A80000)
+#define BASE_ADDR_DFESYS_TXDFE_MD2G_BFE_TX1 (0xB8A90000)
+#define BASE_ADDR_DFESYS_TXDFE_WIN_CTRL_MEM (0xB8AA0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG0 (0xB8AB0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG1 (0xB8AC0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG2 (0xB8AD0000)
+#define BASE_ADDR_DFESYS_TXDFE_BB_REG3 (0xB8AE0000)
+#define BASE_ADDR_DFESYS_RESERVED1 (0xB8AF0000)
+#define BASE_ADDR_DFESYS_RESERVED2 (0xB8B00000)
+#define BASE_ADDR_DFESYS_RESERVED3 (0xB8B10000)
+#define BASE_ADDR_DFESYS_FDD_TTR (0xB8B20000)
+#define BASE_ADDR_DFESYS_TDD_TTR (0xB8B30000)
+#define BASE_ADDR_DFESYS_LTE_TTR (0xB8B40000)
+#define BASE_ADDR_DFESYS_LTE_TTR1 (0xB8B50000)
+#define BASE_ADDR_DFESYS_LTE_TTR2 (0xB8B60000)
+#define BASE_ADDR_DFESYS_RESERVED4 (0xB8B70000)
+#define BASE_ADDR_DFESYS_RESERVED5 (0xB8B80000)
+#define BASE_ADDR_DFESYS_NR_TTR (0xB8B90000)
+#define BASE_ADDR_DFESYS_NR_TTR1 (0xB8BA0000)
+#define BASE_ADDR_DFESYS_NR_TTR2 (0xB8BB0000)
+#define BASE_ADDR_DFESYS_NR_TTR3 (0xB8BC0000)
+#define BASE_ADDR_DFESYS_GLB_CON_CONFIG1 (0xB8BD0000)
+#define BASE_ADDR_DFESYS_MBIST_REPAIR_CFG (0xB8BE0000)
+#define BASE_ADDR_DFESYS_BUS_CONFIG1 (0xB8BF0000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES (0xB8C00000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L2 (0xB8C10000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L15 (0xB8C20000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_L1 (0xB8C30000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_MISC (0xB8C40000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_COS (0xB8C50000)
+#define BASE_ADDR_DFESYS_RXDFE_BB (0xB8C60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC0 (0xB8C70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC1 (0xB8C80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TC2 (0xB8C90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_MS (0xB8CA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_FC (0xB8CB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DUMP (0xB8CC0000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB1 (0xB8CD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CQ1 (0xB8CE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_DMA (0xB8CF0000)
+#define BASE_ADDR_DFESYS_RXDFE_AGCDC_EXTIF (0xB8D00000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE0 (0xB8D10000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE1 (0xB8D20000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE2 (0xB8D30000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE3 (0xB8D40000)
+#define BASE_ADDR_DFESYS_RXDFE_PCC_BB0 (0xB8D50000)
+#define BASE_ADDR_DFESYS_RXDFE_MRSG_BB (0xB8D60000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE0 (0xB8D70000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_BFE1 (0xB8D80000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CW_DM_SEL (0xB8D90000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_DM_SEL (0xB8DA0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CS_SEL (0xB8DB0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL0 (0xB8DC0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_NR_CM_SEL1 (0xB8DD0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_CORE4 (0xB8DE0000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_1 (0xB8DF0000)
+#define BASE_ADDR_DFESYS_DFE_COMDMA (0xB8E00000)
+#define BASE_ADDR_DFESYS_RESERVED6 (0xB8E10000)
+#define BASE_ADDR_DFESYS_RESERVED7 (0xB8E20000)
+#define BASE_ADDR_DFESYS_RESERVED8 (0xB8E30000)
+#define BASE_ADDR_DFESYS_RESERVED9 (0xB8E40000)
+#define BASE_ADDR_DFESYS_RESERVED10 (0xB8E50000)
+#define BASE_ADDR_DFESYS_COS_POST_WB (0xB8E60000)
+#define BASE_ADDR_DFESYS_MAS_BUS_CONFIG_REAL (0xB8E70000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_1 (0xB8E80000)
+#define BASE_ADDR_DFESYS_DIGBB_SERDES_2 (0xB8E88000)
+#define BASE_ADDR_DFESYS_RXDFE_BB_TOP_2 (0xB8E90000)
+#define BASE_ADDR_DFESYS_RESERVED11 (0xB8EA0000)
+#define BASE_ADDR_DFESYS_MAS_BUS_INTF (0xB8EB0000)
+#define BASE_ADDR_DFESYS_SLV_BUS_INTF (0xB8EC0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP (0xB9418000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_1 (0xB941C000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_2 (0xB9410000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_3 (0xB9414000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXK_WRAP_4 (0xB9416000)
+#define BASE_ADDR_DIGRF_TX_TOP_TPC_A (0xB9180000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL (0xB9400000)
+#define BASE_ADDR_DIGRF_TX_TOP_TXDFE_TQ (0xB94A0000)
+#define BASE_ADDR_DIGRF_TX_TOP_TX_TICK_GEN (0xB94B0000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_APC (0xB9298000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_BPI (0xB9170000)
+#define BASE_ADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN (0xB92E0000)
+#define BASE_ADDR_CSSYS_CS (0xB9800000)
+#define BASE_ADDR_CSSYS_LTE_CS (0xB9810000)
+#define BASE_ADDR_CSSYS_MBIST_CON (0xB9820000)
+#define BASE_ADDR_CSSYS_CSSYS_BUS_CONFIG (0xB9830000)
+#define BASE_ADDR_CSSYS_CSSYS_BUS_DIV2_CONFIG (0xB9838000)
+#define BASE_ADDR_CSSYS_MDAO_BUS_CONFIG (0xB983C000)
+#define BASE_ADDR_CSSYS_CS_DEBUG (0xB9840000)
+#define BASE_ADDR_CSSYS_1X_CS (0xB9850000)
+#define BASE_ADDR_CSSYS_CS_WT (0xB9860000)
+#define BASE_ADDR_CSSYS_CSSYS_CS_WT1 (0xB9870000)
+#define BASE_ADDR_CSSYS_EVDO_CS (0xB9880000)
+#define BASE_ADDR_CS_NR_CS_NR_TOP_REG (0xB9C00000)
+#define BASE_ADDR_CS_NR_CS_NR_CSFSM_REG (0xB9C10000)
+#define BASE_ADDR_CS_NR_CS_NR_SCN_RPT (0xB9C20000)
+#define BASE_ADDR_CS_NR_CS_NR_HEIF_REG (0xB9C30000)
+#define BASE_ADDR_CS_NR_CS_NR_BUS_CONFIG (0xB9C40000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_DELSEL_CFG (0xB9C50000)
+#define BASE_ADDR_CS_NR_CS_NR_MBIST_REPAIR_CFG (0xB9C58000)
+#define BASE_ADDR_CS_NR_CM_CS_BUS_CONFIG (0xB9C60000)
+#define BASE_ADDR_CMCS_PAR_AO_MML1_CMCS_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBDC00000)
+#define BASE_ADDR_CMCS_PAR_AO_MML1_CMCS_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBDC10000)
+#define BASE_ADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG (0xBDC20000)
+#define BASE_ADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG (0xBDC30000)
+#define BASE_ADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG (0xBDC40000)
+#define BASE_ADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO (0xBDC50000)
+#define BASE_ADDR_CMCS_PAR_AO_MCORE_PAR_AO_REG (0xBDC50400)
+#define BASE_ADDR_CMCS_PAR_AO_U_VCORE_PAR_WRAP_SRAM_AO (0xBDC60000)
+#define BASE_ADDR_CMCS_PAR_AO_U_VCORE_PAR_AO_CR (0xBDC60400)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_0_SM_CONFIG (0xBDC60600)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_1_SM_CONFIG (0xBDC60680)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_2_SM_CONFIG (0xBDC60700)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_3_SM_CONFIG (0xBDC60780)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_4_SM_CONFIG (0xBDC60800)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_5_SM_CONFIG (0xBDC60880)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_6_SM_CONFIG (0xBDC60900)
+#define BASE_ADDR_CMCS_PAR_AO_U_VU_7_SM_CONFIG (0xBDC60980)
+#define BASE_ADDR_CMCS_PAR_AO_U_GRAM_MEM_CONFIG (0xBDC70000)
+#define BASE_ADDR_CMCS_PAR_AO_U_TX_NR_MEM_CONFIG (0xBDC80000)
+#define BASE_ADDR_CMCS_PAR_AO_U_CMCS_NR_MEM_CONFIG (0xBDC90000)
+#define BASE_ADDR_CMCS_PAR_AO_U_CMCS_PAR_AO_CONFIG_REG (0xBDCA0000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_MAS_MDTOP_BUS4X_CK_ABUS_REG (0xBA000000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_MAS_TXBSRP_NR_CK_ABUS_REG (0xBA008000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_SLV_MDTOP_BUS4X_CK_ABUS_REG (0xBA010000)
+#define BASE_ADDR_TXSYS_NR_MML1_TX_NR_SLV_TXBSRP_NR_CK_ABUS_REG (0xBA018000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG (0xBA020000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_1 (0xBA030000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_2 (0xBA040000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_3 (0xBA050000)
+#define BASE_ADDR_TXSYS_NR_TXCTL_NR_APB_CONFIG_4 (0xBA060000)
+#define BASE_ADDR_TXSYS_NR_TXBSRP_GLB_APB_CONFIG (0xBA070000)
+#define BASE_ADDR_TXSYS_NR_TXBSRP_BIT_CONTROLLER (0xBA080000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_DELSEL_CFG_WRAP (0xBA100000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_MBIST_REPAIR_CFG (0xBA101000)
+#define BASE_ADDR_TXSYS_NR_RESERVED0 (0xBA102000)
+#define BASE_ADDR_TXSYS_NR_TX_NR_PAR_AO_CONFIG_REG (0xBA10C000)
+#define BASE_ADDR_TXSYS_NR_RESERVED1 (0xBA10D000)
+#define BASE_ADDR_TXSYS_NR_RESERVED2 (0xBA10E000)
+#define BASE_ADDR_CM_NR_CM_NR_GLOBAL_CON (0xBA400000)
+#define BASE_ADDR_CM_NR_CM_NR_MBIST_WRAP (0xBA410000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_0 (0xBA420000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_DVTCRC (0xBA430000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH (0xBA440000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_1 (0xBA450000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_DVTCRC_1 (0xBA460000)
+#define BASE_ADDR_CM_NR_CM_NR_PBCH_1 (0xBA470000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_2 (0xBA480000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB_SSS (0xBA490000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB_SSS (0xBA4A0000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP_SSS (0xBA4B0000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT_SSS (0xBA4C0000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_SSS (0xBA4D0000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL_SSS (0xBA4E0000)
+#define BASE_ADDR_CM_NR_CM_NR_DVTCRC_SSS (0xBA4F0000)
+#define BASE_ADDR_CM_NR_CM_NR_TDB_CSIRS (0xBA500000)
+#define BASE_ADDR_CM_NR_CM_NR_FDB_CSIRS (0xBA510000)
+#define BASE_ADDR_CM_NR_CM_NR_RSSIRSRP_CSIRS (0xBA520000)
+#define BASE_ADDR_CM_NR_CM_NR_REPORT_CSIRS (0xBA530000)
+#define BASE_ADDR_CM_NR_CM_NR_AXIPROT_RPT2DM_CSIRS (0xBA540000)
+#define BASE_ADDR_CM_NR_CM_NR_TD_CTRL_CSIRS (0xBA550000)
+#define BASE_ADDR_CM_NR_CM_NR_DVTCRC_CSIRS (0xBA560000)
+#define BASE_ADDR_CM_NR_CM_NR_RESERVED_3 (0xBA570000)
+#define BASE_ADDR_CM_NR_MML1_CMCS_NR_CM_NR_CK_ABUS_REG (0xBA580000)
+#define BASE_ADDR_CM_NR_MML1_CM_NR_MDTOP_BUS4X_CK_ABUS_REG (0xBA590000)
+#define BASE_ADDR_RXTFC_RXTFC_NR (0xBA800000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_TOP_1 (0xBA810000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_GLOBAL_CON (0xBA820000)
+#define BASE_ADDR_RXTFC_RESERVED0 (0xBA830000)
+#define BASE_ADDR_RXTFC_RESERVED1 (0xBA840000)
+#define BASE_ADDR_RXTFC_RXT2F_NR_MBIST_CONFIG (0xBA850000)
+#define BASE_ADDR_RXTFC_RXTFC_NR_MBIST_CAT_REPAIR_CFG (0xBA860000)
+#define BASE_ADDR_RXTFC_RESERVED2 (0xBA870000)
+#define BASE_ADDR_RXTFC_MML1_RXTFC_MDTOP_BUS4X_CK_ABUS_REG (0xBA880000)
+#define BASE_ADDR_RXTFC_MML1_CMCS_NR_RXTFC_NR_CK_ABUS_REG (0xBA890000)
+#define BASE_ADDR_RXTDB_RXTDB_NR (0xBAC00000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_1 (0xBAC10000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_GLOBAL_CON (0xBAC20000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_2 (0xBAC30000)
+#define BASE_ADDR_RXTDB_RXT2F_NR_MBIST_CONFIG (0xBAC40000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_DELSEL_CFG (0xBAC50000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_MBIST_CAT_REPAIR_CFG (0xBAC60000)
+#define BASE_ADDR_RXTDB_RXTDB_NR_TOP_3 (0xBAC70000)
+#define BASE_ADDR_RXTDB_MML1_RXTDB_MDTOP_BUS4X_CK_ABUS_REG (0xBAC80000)
+#define BASE_ADDR_RXTDB_MML1_CMCS_NR_RXTDB_NR_CK_ABUS_REG (0xBAC90000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR (0xBAE00000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_1 (0xBAE10000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_GLOBAL_CON (0xBAE20000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_2 (0xBAE30000)
+#define BASE_ADDR_RXTDB_PBCH_MML1_RXTDB_PBCH_MDTOP_BUS4X_CK_ABUS_REG (0xBAE40000)
+#define BASE_ADDR_RXTDB_PBCH_MML1_CMCS_NR_RXTDB_PBCH_NR_CK_ABUS_REG (0xBAE50000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_3 (0xBAE60000)
+#define BASE_ADDR_RXTDB_PBCH_RXTDB_NR_TOP_4 (0xBAE70000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_MEM (0xBB000000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_DELSEL_CFG_WRAP (0xBB800000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_MBIST_REPAIR_CFG (0xBB808000)
+#define BASE_ADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON (0xBB810000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_D2BIF (0xBB820000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_REG (0xBB830000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BRIDGE (0xBB840000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_RXT2F (0xBB850000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BR_DMA (0xBB860000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_DOWN_SAMP_TDB (0xBB870000)
+#define BASE_ADDR_BIGRAM0_BIGRAM_BUS_CONFIG (0xBB880000)
+#define BASE_ADDR_BIGRAM0_INR_SLV_BUS_CONFIG (0xBB890000)
+#define BASE_ADDR_INR0_MEM (0xBBA00000)
+#define BASE_ADDR_INR0_RESERVED0 (0xBBB00000)
+#define BASE_ADDR_INR0_SHARED_DM (0xBBB40000)
+#define BASE_ADDR_INR0_RESERVED1 (0xBBB80000)
+#define BASE_ADDR_INR0_RESERVED2 (0xBBC00000)
+#define BASE_ADDR_INR0_REGISTERS (0xBBC10000)
+#define BASE_ADDR_INR0_SCQ_SEMAPHORE (0xBBC11000)
+#define BASE_ADDR_INR0_SCQ_GLOBAL_CON (0xBBC12000)
+#define BASE_ADDR_INR0_SCQ_MBIST_DELSEL_CFG (0xBBC13000)
+#define BASE_ADDR_INR0_SCQ_MBIST_REPAIR_CFG (0xBBC13800)
+#define BASE_ADDR_INR0_VU_MBIST_DELSEL_CFG (0xBBC14000)
+#define BASE_ADDR_INR0_VU_MBIST_REPAIR_CFG (0xBBC14800)
+#define BASE_ADDR_INR0_RESERVED3 (0xBBC15000)
+#define BASE_ADDR_INR0_RESERVED4 (0xBBD00000)
+#define BASE_ADDR_INR0_LOCAL_DM (0xBBE00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB (0xBBE08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR (0xBBE09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR (0xBBE0A000)
+#define BASE_ADDR_INR0_MEM__REGISTER (0xBBE0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE (0xBBE0C000)
+#define BASE_ADDR_INR0_RESERVED5 (0xBBE0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_1 (0xBBF00000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_1 (0xBBF08000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_1 (0xBBF09000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_1 (0xBBF0A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF (0xBBF0B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_1 (0xBBF0C000)
+#define BASE_ADDR_INR0_RESERVED6 (0xBBF0D000)
+#define BASE_ADDR_INR0_LOCAL_DM_2 (0xBC000000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_2 (0xBC008000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_2 (0xBC009000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_2 (0xBC00A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_1 (0xBC00B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_2 (0xBC00C000)
+#define BASE_ADDR_INR0_RESERVED7 (0xBC00D000)
+#define BASE_ADDR_INR0_LOCAL_DM_3 (0xBC100000)
+#define BASE_ADDR_INR0_SCQ_DSPLOG_1PB_3 (0xBC108000)
+#define BASE_ADDR_INR0_SCQ_VU_CR_3 (0xBC109000)
+#define BASE_ADDR_INR0_SCQ_MBIST_CR_3 (0xBC10A000)
+#define BASE_ADDR_INR0_SCQ_MD32_TBUF_2 (0xBC10B000)
+#define BASE_ADDR_INR0_SCQ_DCACHE_3 (0xBC10C000)
+#define BASE_ADDR_INR0_RESERVED8 (0xBC10D000)
+#define BASE_ADDR_INR0_RESERVED9 (0xBC200000)
+#define BASE_ADDR_RXBRP0_RXBRP_MBIST_CONFIG (0xBC800000)
+#define BASE_ADDR_RXBRP0_DMC_MBIST_CONFIG (0xBC810000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_DRM (0xBC820000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_R99_WRAP (0xBC830000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_1XRTT (0xBC840000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_CORR_SER (0xBC850000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_BCH (0xBC860000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DVIT (0xBC870000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TRACE (0xBC900000)
+#define BASE_ADDR_RXBRP0_RXBRP_GLOBAL_CON (0xBC910000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_TUR (0xBC920000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_CVIT (0xBC930000)
+#define BASE_ADDR_RXBRP0_RXBRP_WTL_HARQ_BUF (0xBC940000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCT_DMA (0xBC950000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_MAS_HALF_CK_ABUS_REG (0xBC960000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_HARQ (0xBC970000)
+#define BASE_ADDR_RXBRP0_RXBRP_WT_CDRM (0xBC980000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_MAS_CK_ABUS_REG (0xBC990000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_SLV_HALF_CK_ABUS_REG (0xBC9A0000)
+#define BASE_ADDR_RXBRP0_MML1_RXBRP_SLV_CK_ABUS_REG (0xBC9B0000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_CORR (0xBCA00000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_TXIF (0xBCA10000)
+#define BASE_ADDR_RXBRP0_RXBRP_W_HSRM (0xBCA20000)
+#define BASE_ADDR_RXBRP0_RXBRP_C_EVDO (0xBCA30000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DBRP (0xBCA40000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP (0xBCA50000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_HARQ (0xBCA60000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_REBRP (0xBCA70000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_RBMAP (0xBCA80000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_DCI_PARSER (0xBCA90000)
+#define BASE_ADDR_RXBRP0_RXBRP_L_CBRP_RSLT (0xBCAA0000)
+#define BASE_ADDR_RXBRP0_RXBRP_WCTL_ECTRL (0xBCAB0000)
+#define BASE_ADDR_RXBRP0_DMC (0xBCB00000)
+#define BASE_ADDR_RXBRP0_DMC_PERI (0xBCB10000)
+#define BASE_ADDR_RXBRP0_LTE_CE_SC (0xBCB20000)
+#define BASE_ADDR_RXBRP0_LTE_CE_OC1 (0xBCB21000)
+#define BASE_ADDR_RXBRP0_LTE_CE_OC2 (0xBCB22000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_PDSCH (0xBCB30000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_PDCCH (0xBCB33000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_EPDCCH (0xBCB34000)
+#define BASE_ADDR_RXBRP0_DEMOD_TOP_PBCH (0xBCB35000)
+#define BASE_ADDR_RXBRP0_DMC_MIMO (0xBCB40000)
+#define BASE_ADDR_RXBRP0_DMC_PWR_MEAS (0xBCB50000)
+#define BASE_ADDR_RAKESYS_RAKE_INST_DEC (0xBCC00000)
+#define BASE_ADDR_RAKESYS_RAKE_LOADER (0xBCC20000)
+#define BASE_ADDR_RAKESYS_RAKE_DESP (0xBCC30000)
+#define BASE_ADDR_RAKESYS_RAKE_SEEDGEN (0xBCC40000)
+#define BASE_ADDR_RAKESYS_RAKE_EXT (0xBCC50000)
+#define BASE_ADDR_RAKESYS_RAKE_R2B_DMA (0xBCC60000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_ACC (0xBCC70000)
+#define BASE_ADDR_RAKESYS_RAKE_FCE (0xBCC80000)
+#define BASE_ADDR_RAKESYS_RAKE_DESIG (0xBCC90000)
+#define BASE_ADDR_RAKESYS_RAKE_R2TX_DHWIF (0xBCCA0000)
+#define BASE_ADDR_RAKESYS_RAKE_CPICH_INTF (0xBCCF0000)
+#define BASE_ADDR_RAKESYS_RAKE_BRIF (0xBCD00000)
+#define BASE_ADDR_RAKESYS_RAKE_UNITTEST (0xBCD10000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON (0xBCE00000)
+#define BASE_ADDR_RAKESYS_MBIST_DELSEL_CFG (0xBCE10000)
+#define BASE_ADDR_RAKESYS_MBIST_REPAIR_CFG (0xBCE18000)
+#define BASE_ADDR_RAKESYS_GLOBAL_CON_L1DBG (0xBCF00000)
+#define BASE_ADDR_RAKESYS_DSP_SW_LOGGER (0xBCF40000)
+#define BASE_ADDR_RAKESYS_CIRQ (0xBCF50000)
+#define BASE_ADDR_RAKESYS_PERICTRL (0xBCF51000)
+#define BASE_ADDR_RAKESYS_TRACE_BUF (0xBCF54000)
+#define BASE_ADDR_RAKESYS_CMIF (0xBCF58000)
+#define BASE_ADDR_RAKESYS_PM (0xBCF80000)
+#define BASE_ADDR_RAKESYS_RAKE_PM_ARB (0xBCF90000)
+#define BASE_ADDR_RAKESYS_PM_ARB_2 (0xBCFA0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_3 (0xBCFB0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_4 (0xBCFC0000)
+#define BASE_ADDR_RAKESYS_DM (0xBCFD0000)
+#define BASE_ADDR_RAKESYS_RAKE_DM_ARB (0xBCFE0000)
+#define BASE_ADDR_RAKESYS_PM_ARB_6 (0xBCFF0000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_SRAM_CTRL_AO (0xBD000000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MMW_DBB_CTRLACNT (0xBD001000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MMW_RF_CTRL_GLOBAL_CON_AO (0xBD002000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_RESERVED0 (0xBD003000)
+#define BASE_ADDR_MMW_RF_CTRL_AO_MML1_MMW_RF_CTRL_416M_AO_CK_ABUS_REG (0xBD010000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RFAC (0xBD020000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CM_DATA_INTF (0xBD040000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_EVENTGEN (0xBD050000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED1 (0xBD060000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_416M_CK_ABUS_REG (0xBD080000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_LOG (0xBD090000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_COMDMA (0xBD0A0000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_CONTROLLER (0xBD0B0000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD (0xBD0B8000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_1 (0xBD0B8100)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_CTRL_MD_TOP_2 (0xBD0B8200)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED2 (0xBD0B8300)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_MBIST (0xBD0B9000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_RF_CTRL_GLOBAL_CON (0xBD0BA000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED3 (0xBD0BB000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_CM_COMM_REG (0xBD0F8000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG (0xBD0F8400)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_1 (0xBD0F8800)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MIXEDSYS_AFE_PATH_REG_2 (0xBD0F8C00)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED4 (0xBD0F9000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_TOP (0xBD100000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_LOG (0xBD108000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BSI_SCH (0xBD110000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_208M_CK_ABUS_REG (0xBD120000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED5 (0xBD130000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_BPI (0xBD180000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_DIGRF_MIPI_M (0xBD190000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_TOP (0xBD200000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SCH (0xBD210000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI0 (0xBD218000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI1 (0xBD219000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI2 (0xBD21A000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI3 (0xBD21B000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI4 (0xBD21C000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI5 (0xBD21D000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI6 (0xBD21E000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MMW_MIPI_MM_SPI_LOG_MIPI7 (0xBD21F000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_MML1_MMW_RF_CTRL_104M_CK_ABUS_REG (0xBD220000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED6 (0xBD230000)
+#define BASE_ADDR_MMW_RF_CTRL_PWR_WRAP_RESERVED7 (0xBD300000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_RESERVED0 (0xBD400000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_RESERVED1 (0xBD640000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TOP_CTRL (0xBD410000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_TXK (0xBD420000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_GLOBAL_CON (0xBD430000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BUS_CONFIG (0xBD440000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_MBIST_CONFIG_CAT (0xBD450000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TX_ACNT_TICK_GEN (0xBD460000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_TQ (0xBD470000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR (0xBD480000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_1 (0xBD490000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_2 (0xBD4A0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_3 (0xBD4B0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_4 (0xBD4C0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_5 (0xBD4D0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_6 (0xBD4E0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TTR_TOP_7 (0xBD4F0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D (0xBD500000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_1 (0xBD510000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_2 (0xBD520000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_3 (0xBD530000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_4 (0xBD540000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_5 (0xBD550000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_6 (0xBD560000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_7 (0xBD570000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_8 (0xBD580000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_D_9 (0xBD590000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_BB_A (0xBD5A0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF (0xBD5B0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_1 (0xBD5C0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_2 (0xBD5D0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_RF_3 (0xBD5E0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_ABB_MIXEDSYS (0xBD5F0000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MRX_DATA_DUMP (0xBD600000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_PCC_BB (0xBD610000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_U_MMW_PCC_BB_TOP_1 (0xBD620000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE_LOG (0xBD660000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE0_COMDMA (0xBD670000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MMW_TXDFE1_COMDMA (0xBD680000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_MML1_MMW_TPC_468M_CK_ABUS_REG (0xBD690000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_TPC_M (0xBD700000)
+#define BASE_ADDR_MMW_TXDFE_PWR_WRAP_TPC_M_1 (0xBD780000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER (0xBD800000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXTIMER_RESERVED0 (0xBD804000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_EVTGEN (0xBD808000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_SLPC (0xBD80C000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_RESERVED1 (0xBD810000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_PAR_WRAP_SRAM_AO (0xBD820000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_RXDFE_CONFIG_AO_REG (0xBD821000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX0 (0xBD828000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX1 (0xBD829000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX2 (0xBD82A000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_RX3 (0xBD82B000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX0 (0xBD82C000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_TX1 (0xBD82D000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MMW_ABB_MIXEDSYS_AO_SYS (0xBD82E000)
+#define BASE_ADDR_MMW_RXDFE_PAR_AO_MML1_MMW_RXDFE_BUS_AO_468M_CK_ABUS_REG (0xBD830000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CONFIG_REG (0xBD840000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MBIST_CAT_MBIST_TOP_CFG (0xBD844000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_468M_CK_ABUS_REG (0xBD850000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_RXDFE_BB_NR_MMW_DM_SEL_WRAP (0xBD860000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CS_SEL_WRAP (0xBD870000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_CMSEL_MMW (0xBD880000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_CMIPG_MMW (0xBD888000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_LOG (0xBD890000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_MRSG (0xBD8A0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE0_COMDMA (0xBD8C0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_DMA_DESCRT (0xBD8D0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_0 (0xBD8F0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_PCC_1 (0xBD8F8000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_0 (0xBD900000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_0 (0xBD920000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_1 (0xBD920200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_2 (0xBD920400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_3 (0xBD920600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_4 (0xBD920800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_5 (0xBD920A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_6 (0xBD920C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_AGC_7 (0xBD920E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_0 (0xBD922000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_1 (0xBD922200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_2 (0xBD922400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_3 (0xBD922600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_4 (0xBD922800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_5 (0xBD922A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_6 (0xBD922C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ0_DFE_7 (0xBD922E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TQ1 (0xBD924000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_WM (0xBD92A000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_0_TOT_PATT (0xBD92E000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_2 (0xBD940000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_2 (0xBD960000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_1 (0xBD980000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_0 (0xBD9A0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_1 (0xBD9A0200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_2 (0xBD9A0400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_3 (0xBD9A0600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_4 (0xBD9A0800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_5 (0xBD9A0A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_6 (0xBD9A0C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_AGC_7 (0xBD9A0E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_0 (0xBD9A2000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_1 (0xBD9A2200)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_2 (0xBD9A2400)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_3 (0xBD9A2600)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_4 (0xBD9A2800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_5 (0xBD9A2A00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_6 (0xBD9A2C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ0_DFE_7 (0xBD9A2E00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TQ1 (0xBD9A4000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_WM (0xBD9AA000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_TC_SRAM_1_TOT_PATT (0xBD9AE000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_MBIST_CONFIG (0xBD9C0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_4P16L_GLBCON (0xBD9F0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_SET (0xBDA00000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_HEADER (0xBDA04000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CQ_STATUS (0xBDA08000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_P_REG (0xBDA10000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_ACT_L_REG (0xBDA20000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_IMM_REG (0xBDA30000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_P_REG (0xBDA40000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_MS_L_REG (0xBDA50000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_CS_AGC (0xBDA60000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_468 (0xBDA70000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_CR_52 (0xBDA71000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_0 (0xBDA71800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_0_SRAM_1 (0xBDA71C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC (0xBDA80000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_1 (0xBDA84000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_2 (0xBDA88000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_3 (0xBDA90000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_4 (0xBDAA0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_5 (0xBDAB0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_6 (0xBDAC0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_7 (0xBDAD0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_FC_TOP_8 (0xBDAE0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_468 (0xBDAF0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_CR_52 (0xBDAF1000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_0 (0xBDAF1800)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ABB_MIXEDSYS_1_SRAM_1 (0xBDAF1C00)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MML1_MMW_RXDFE_CORE_624M_CK_ABUS_REG (0xBDAFF000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_DM (0xBDB00000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD0_PM (0xBDBA0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_SRD1_PM (0xBDBB0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_COREDBG (0xBDBD0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_CORE_GC_PM (0xBDBE0000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE1_COMDMA (0xBDBFE000)
+#define BASE_ADDR_MMW_RXDFE_PWR_WRAP_MMW_RXDFE_ADC_TEST_ARBITOR (0xBDBFF000)
+////////////////////////////////////////////////////////////////
+//
+// END-- Generated from MMW_MD_MemoryMap_Detail.xlsx
+//
+////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header for fail save
+/////////////////////////////////////////
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_0 BASE_MADDR_MDPERI_VU_SM_CONGIF_0
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_0 BASE_NADDR_MDPERI_VU_SM_CONGIF_0
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_0 BASE_ADDR_MDPERI_VU_SM_CONGIF_0
+#define BASE_MADDR_MODEML1_AO_U_VU_SM_CONFIG_1 BASE_MADDR_MDPERI_VU_SM_CONGIF_1
+#define BASE_NADDR_MODEML1_AO_U_VU_SM_CONFIG_1 BASE_NADDR_MDPERI_VU_SM_CONGIF_1
+#define BASE_ADDR_MODEML1_AO_U_VU_SM_CONFIG_1 BASE_ADDR_MDPERI_VU_SM_CONGIF_1
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG BASE_MADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_CONFIG BASE_NADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_CONFIG BASE_ADDR_MDPERI_MDRXAO_CONFIG
+//#define BASE_MADDR_MODEML1_AO_U_MCORE_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO
+//#define BASE_NADDR_MODEML1_AO_U_MCORE_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO
+//#define BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_MCORE_PAR_WRAP_SRAM_AO
+#define BASE_MADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG
+#define BASE_MADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG
+#define BASE_MADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG BASE_MADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_MADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG BASE_MADDR_MDPERI_BRP_SRAM_AO
+#define BASE_NADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG BASE_NADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG BASE_NADDR_MDPERI_BRP_SRAM_AO
+#define BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_U_RXCPC_NR_MEM_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_U_RXDDM_MEM_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG BASE_ADDR_CMCS_PAR_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG BASE_ADDR_MDPERI_BRP_SRAM_AO
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_NADDR_MML2_METADATA_MA
+
+
+/////////////////////////////////////////
+// Predefined Header from 95
+/////////////////////////////////////////
+#define BASE_MADDR_TXSYS_TXBSRP BASE_MADDR_DFESYS_TXBSRP
+#define BASE_NADDR_TXSYS_TXBSRP BASE_NADDR_DFESYS_TXBSRP
+#define BASE_ADDR_MDCORESYS_LSRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDCORESYS_BTSLV BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MML2_METADATA_MANAGER BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_NADDR_MML2_METADATA_MANAGER BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_ADDR_MML2_METADATA_MANAGER BASE_ADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_MADDR_MML2_CFG BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_MML2_CFG BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDCORESYS_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MDCORESYS_MML2_MCU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MDCORESYS_MML2_MCU_MMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_MADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_NADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_NADDR_MDPERI_MDRXAO_CONFIG
+#define BASE_ADDR_MODEML1_AO_U_MDRXAO_MEM_CONFIG BASE_ADDR_MDPERI_MDRXAO_CONFIG
+
+/////////////////////////////////////////
+// Predefined Header from 93 due to unexpected MAP_MDMCU table
+/////////////////////////////////////////
+// (18): MAP_MDMCU
+#define BASE_ADDR_MDMCU_MML2_MCU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+//#define BASE_ADDR_MDMCU_IA_MBB3_INTEGRATION BASE_ADDR_MDCORESYS_SPRAM
+#define BASE_ADDR_MDMCU_MDL1_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MDMCU_MD_BOOTSLAVE_TOP_AXI BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+
+#define BASE_MADDR_MDMCU_IA_PDA_MON BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_MADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_IA_MACRO_MISC_REG BASE_MADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_MADDR_MDMCU_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MDMCU_BUSMON BASE_MADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_PERI_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MDMCU_BUS_CONFIG BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+////#define BASE_MADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MDMCU_ELM BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_MADDR_MDMCU_MV20E100 BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MDMCU_USIP0_DTCM BASE_MADDR_USIP_USIP0_DTCM
+#define BASE_MADDR_MDMCU_USIP_INT_DBG BASE_MADDR_USIP_USIP0_DEBUG
+#define BASE_MADDR_MDMCU_USIPCORE_BUS_INTF BASE_MADDR_USIP_USIP1_ITCM
+#define BASE_MADDR_MDMCU_USIP1_DTCM BASE_MADDR_USIP_USIP1_DTCM
+#define BASE_MADDR_MDMCU_USIP1_INT_DBG BASE_MADDR_USIP_USIP1_DEBUG
+#define BASE_MADDR_MDMCU_DSPLOG_4PB BASE_MADDR_USIP_DSPLOG
+#define BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_MADDR_USIP_CROSS_CORE_CTRL
+#define BASE_MADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_MADDR_MDMCU_MCU_SYNC_DFSLV (0xA1FF0000)
+
+#define BASE_NADDR_MDMCU_IA_PDA_MON BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_NADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_IA_MACRO_MISC_REG BASE_NADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_NADDR_MDMCU_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MDMCU_BUSMON BASE_NADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_NADDR_MDMCU_PERI_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MDMCU_BUS_CONFIG BASE_NADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+////#define BASE_NADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MDMCU_ELM BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_NADDR_MDMCU_MV20E100 BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MDMCU_USIP0_DTCM BASE_NADDR_USIP_USIP0_DTCM
+#define BASE_NADDR_MDMCU_USIP_INT_DBG BASE_NADDR_USIP_USIP0_DEBUG
+#define BASE_NADDR_MDMCU_USIPCORE_BUS_INTF BASE_NADDR_USIP_USIP1_ITCM
+#define BASE_NADDR_MDMCU_USIP1_DTCM BASE_NADDR_USIP_USIP1_DTCM
+#define BASE_NADDR_MDMCU_USIP1_INT_DBG BASE_NADDR_USIP_USIP1_DEBUG
+#define BASE_NADDR_MDMCU_DSPLOG_4PB BASE_NADDR_USIP_DSPLOG
+#define BASE_NADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_NADDR_USIP_CROSS_CORE_CTRL
+#define BASE_NADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_NADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_NADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_ADDR_MDMCU_IA_PDA_MON BASE_ADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_ADDR_MDMCU_IA_DEBUG_PERI_MBIST_CONFIG_V3 BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_IA_MACRO_MISC_REG BASE_ADDR_MDMCU_SHAOLIN__IA_DEBUG_PERI_MISC_REG_ADR_IF
+#define BASE_ADDR_MDMCU_MCUMMU BASE_ADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MDMCU_BUSMON BASE_ADDR_MDCORESYS_MDMCU_BUSMON
+#define BASE_ADDR_MDMCU_PERI_MBIST_CONFIG BASE_ADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MDMCU_BUS_CONFIG BASE_ADDR_MDCORESYS_MDMCU_BUS_INTF_CFG
+////#define BASE_ADDR_MDMCU_IA_MACRO_DELSEL_ADR_IF BASE_ADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MDMCU_ELM BASE_ADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MDMCU_MDCORESYS_MISC_REG_ADR_IF BASE_ADDR_MDCORESYS_MDCORESYS_MISC_REG
+
+#define BASE_ADDR_MDMCU_MV20E100 BASE_ADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MDMCU_USIP0_DTCM BASE_ADDR_USIP_USIP0_DTCM
+#define BASE_ADDR_MDMCU_USIP_INT_DBG BASE_ADDR_USIP_USIP0_DEBUG
+#define BASE_ADDR_MDMCU_USIPCORE_BUS_INTF BASE_ADDR_USIP_USIP1_ITCM
+#define BASE_ADDR_MDMCU_USIP1_DTCM BASE_ADDR_USIP_USIP1_DTCM
+#define BASE_ADDR_MDMCU_USIP1_INT_DBG BASE_ADDR_USIP_USIP1_DEBUG
+#define BASE_ADDR_MDMCU_DSPLOG_4PB BASE_ADDR_USIP_DSPLOG
+#define BASE_ADDR_MDMCU_USIP_CROSS_CORE_CTRL BASE_ADDR_USIP_CROSS_CORE_CTRL
+#define BASE_ADDR_MDMCU_USIP_BUS_CONFIG_REG BASE_ADDR_USIP_BUS_CONFIG___MPU_CONFIG
+#define BASE_ADDR_MDMCU_MCU_SYNC_DFSLV (0xB1FF0000)
+
+#define BASE_MADDR_MODEML1_AO_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_MADDR_MODEML1_AO_MDRX_P2P_TX BASE_MADDR_MDPERI_MDRXSYS_SRAM_AO
+
+#define BASE_NADDR_MODEML1_AO_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_NADDR_MODEML1_AO_MDRX_P2P_TX BASE_NADDR_MDPERI_MDRXSYS_SRAM_AO
+
+#define BASE_ADDR_MODEML1_AO_FESYS_P2P_TX BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MODEML1_AO_MDRX_P2P_TX BASE_ADDR_MDPERI_MDRXSYS_SRAM_AO
+
+/////////////////////////////////////////
+// Predefined Header from 92
+/////////////////////////////////////////
+#define BASE_ADDR_MMU_MML2 BASE_ADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_L2SRAM BASE_ADDR_MDCORESYS_SHAOLIN_L2SRAM
+#define BASE_ADDR_MIPS_BOOTROM BASE_ADDR_MDCORESYS_SHAOLIN_BTSLV
+#define BASE_MADDR_MDCFGCTL BASE_MADDR_MDPERI_MDCFGCTL
+#define BASE_MADDR_MDUART0 BASE_MADDR_MDPERI_MDUART0
+#define BASE_MADDR_MDGDMA BASE_MADDR_MDPERI_MDGDMA
+#define BASE_MADDR_MDGPTM BASE_MADDR_MDPERI_MDGPTM
+#define BASE_MADDR_USIM1 BASE_MADDR_MDPERI_USIM1
+#define BASE_MADDR_USIM2 BASE_MADDR_MDPERI_USIM2
+#define BASE_MADDR_MDPERIMISC BASE_MADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_MADDR_MDCIRQ BASE_MADDR_MDPERI_MDCIRQ
+#define BASE_MADDR_PTP_THERM_CTRL BASE_MADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_MADDR_MDTOPSM BASE_MADDR_MDPERI_MD_TOPSM
+#define BASE_MADDR_MDOSTIMER BASE_MADDR_MDPERI_MD_OSTIMER
+#define BASE_MADDR_MDRGU BASE_MADDR_MDPERI_MDRGU
+#define BASE_MADDR_MDEINT BASE_MADDR_MDPERI_MD_EINT
+#define BASE_MADDR_MDTOP_GLBCON BASE_MADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_MADDR_MDTOP_PLLMIXED BASE_MADDR_MDPERI_MD_PLLMIXED
+#define BASE_MADDR_MDTOP_CLKSW BASE_MADDR_MDPERI_MD_CLKSW
+#define BASE_MADDR_MDDBGMON BASE_MADDR_MDPERI_MDPAR_DBGMON
+#define BASE_MADDR_CLK_CTRL BASE_MADDR_MDPERI_CLK_CTRL
+//#define BASE_MADDR_MEM_CONFIG BASE_MADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_MADDR_MDMCU_PDAMON BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_MADDR_MCUSYS_MBIST_CONFIG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_MADDR_MCUMMU_MMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_MADDR_MCUMMU_VRB BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_MADDR_MCUMMU BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_MADDR_MCUSYS_MBISTG BASE_MADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+////#define BASE_MADDR_MCUSYS_IA_DEL_CFG BASE_MADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_MADDR_MCUSYS_ELM_EMI BASE_MADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_MADDR_MCUSYS_MISC_REG BASE_MADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_MADDR_SOE BASE_MADDR_MDINFRA_SOE
+#define BASE_MADDR_MDINFRABUSMON BASE_MADDR_MDINFRA_BUSMON
+#define BASE_MADDR_MDUART1 BASE_MADDR_MDINFRA_MDUART1
+#define BASE_MADDR_MDINFRASYS_MBIST_CFG BASE_MADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_MADDR_MDINFRA_BUS BASE_MADDR_MDINFRA_MDM
+#define BASE_MADDR_MDM BASE_MADDR_MDINFRA_MDM
+//#define BASE_MADDR_MDSMICFG BASE_MADDR_MDINFRA_MDSMICFG
+//#define BASE_MADDR_MDINFRAMISC BASE_MADDR_MDINFRA_MISC_REG
+#define BASE_MADDR_LOGTOP BASE_MADDR_MDINFRA_LOG
+//#define BASE_MADDR_MDINFRA_ELM BASE_MADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_MADDR_TRACE_TOP BASE_MADDR_MDINFRA_TRACE
+#define BASE_MADDR_PPPHA BASE_MADDR_MDINFRA_PPPHA
+#define BASE_MADDR_SDF_TOP BASE_MADDR_MDINFRA_SDF
+//#define BASE_MADDR_MML2_QP_APB BASE_MADDR_MML2_QUEUE_PROCESSOR
+#define BASE_MADDR_MML2_META_APB BASE_MADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_MADDR_MML2_CFG_TOP BASE_MADDR_NRL2_NRL2_TOP_CFG
+#define BASE_MADDR_USIP_PERISYS BASE_MADDR_USIP_USIP0_ITCM
+#define BASE_MADDR_MODEM_AO_APB BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+//#define BASE_MADDR_DFESYS_0 BASE_MADDR_RXDFESYS_BUS_CONFIG
+#define BASE_MADDR_CSTXBSYS BASE_MADDR_CSSYS_CS
+#define BASE_MADDR_LTXBSYS BASE_MADDR_DFESYS_TXBSRP
+//#define BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_NADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_NADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_NADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_NADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_NADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_NADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_NADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_NADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_NADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_NADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_NADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_NADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_NADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_NADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_NADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_NADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_NADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_NADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_NADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_NADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_NADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_NADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_NADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_NADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_NADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+////#define BASE_NADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_NADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_NADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_NADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_NADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_NADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_NADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_NADDR_MDINFRA_BUS BASE_NADDR_MDINFRA_MDM
+#define BASE_NADDR_MDM BASE_NADDR_MDINFRA_MDM
+//#define BASE_NADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+//#define BASE_NADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_NADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_NADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_NADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_NADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_NADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_NADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_NADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_NADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_NADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_NADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_NADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_NADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_NADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_NADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_NADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_ADDR_MDCFGCTL BASE_NADDR_MDPERI_MDCFGCTL
+#define BASE_ADDR_MDUART0 BASE_NADDR_MDPERI_MDUART0
+#define BASE_ADDR_MDGDMA BASE_NADDR_MDPERI_MDGDMA
+#define BASE_ADDR_MDGPTM BASE_NADDR_MDPERI_MDGPTM
+#define BASE_ADDR_USIM1 BASE_NADDR_MDPERI_USIM1
+#define BASE_ADDR_USIM2 BASE_NADDR_MDPERI_USIM2
+#define BASE_ADDR_MDPERIMISC BASE_NADDR_MDPERI_MDPERISYS_MISC_REG
+#define BASE_ADDR_MDCIRQ BASE_NADDR_MDPERI_MDCIRQ
+#define BASE_ADDR_PTP_THERM_CTRL BASE_NADDR_MDPERI_PTP_THERM_CTRL
+#define BASE_ADDR_MDTOPSM BASE_NADDR_MDPERI_MD_TOPSM
+#define BASE_ADDR_MDOSTIMER BASE_NADDR_MDPERI_MD_OSTIMER
+#define BASE_ADDR_MDRGU BASE_NADDR_MDPERI_MDRGU
+#define BASE_ADDR_MDEINT BASE_NADDR_MDPERI_MD_EINT
+#define BASE_ADDR_MDTOP_GLBCON BASE_NADDR_MDPERI_MD_GLOBAL_CON_DCM
+#define BASE_ADDR_MDTOP_PLLMIXED BASE_NADDR_MDPERI_MD_PLLMIXED
+#define BASE_ADDR_MDTOP_CLKSW BASE_NADDR_MDPERI_MD_CLKSW
+#define BASE_ADDR_MDDBGMON BASE_NADDR_MDPERI_MDPAR_DBGMON
+#define BASE_ADDR_CLK_CTRL BASE_NADDR_MDPERI_CLK_CTRL
+//#define BASE_ADDR_MEM_CONFIG BASE_NADDR_MDPERI_USIP0_MEM_CONFIG
+#define BASE_ADDR_MDMCU_PDAMON BASE_NADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER
+#define BASE_ADDR_MCUSYS_MBIST_CONFIG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+#define BASE_ADDR_MCUMMU_MMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+#define BASE_ADDR_MCUMMU_VRB BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+#define BASE_ADDR_MCUMMU BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+#define BASE_ADDR_MCUSYS_MBISTG BASE_NADDR_MDCORESYS_MCUSYS_MBIST_CONFIG
+////#define BASE_ADDR_MCUSYS_IA_DEL_CFG BASE_NADDR_MDCORESYS_MDCORE_IA_DELSEL_CFG
+#define BASE_ADDR_MCUSYS_ELM_EMI BASE_NADDR_MDCORESYS_MDMCU_ELM_EMI
+#define BASE_ADDR_MCUSYS_MISC_REG BASE_NADDR_MDCORESYS_MDCORESYS_MISC_REG
+#define BASE_ADDR_SOE BASE_NADDR_MDINFRA_SOE
+#define BASE_ADDR_MDINFRABUSMON BASE_NADDR_MDINFRA_BUSMON
+#define BASE_ADDR_MDUART1 BASE_NADDR_MDINFRA_MDUART1
+#define BASE_ADDR_MDINFRASYS_MBIST_CFG BASE_NADDR_MDINFRA_MDINFRASYS_MBIST_CONFIG
+#define BASE_ADDR_MDINFRA_BUS BASE_ADDR_MDINFRA_MDM
+#define BASE_ADDR_MDM BASE_ADDR_MDINFRA_MDM
+//#define BASE_ADDR_MDSMICFG BASE_NADDR_MDINFRA_MDSMICFG
+//#define BASE_ADDR_MDINFRAMISC BASE_NADDR_MDINFRA_MISC_REG
+#define BASE_ADDR_LOGTOP BASE_NADDR_MDINFRA_LOG
+//#define BASE_ADDR_MDINFRA_ELM BASE_NADDR_MDINFRA_MD_INFRA_ELM
+#define BASE_ADDR_TRACE_TOP BASE_NADDR_MDINFRA_TRACE
+#define BASE_ADDR_PPPHA BASE_NADDR_MDINFRA_PPPHA
+#define BASE_ADDR_SDF_TOP BASE_NADDR_MDINFRA_SDF
+//#define BASE_ADDR_MML2_QP_APB BASE_NADDR_MML2_QUEUE_PROCESSOR
+#define BASE_ADDR_MML2_META_APB BASE_NADDR_NRL2_NRL2_METADATA_MNG_REG
+#define BASE_ADDR_MML2_CFG_TOP BASE_NADDR_NRL2_NRL2_TOP_CFG
+#define BASE_ADDR_USIP_PERISYS BASE_NADDR_USIP_USIP0_ITCM
+#define BASE_ADDR_MODEM_AO_APB BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+#define BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define BASE_ADDR_DFESYS_0 BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define BASE_ADDR_CSTXBSYS BASE_NADDR_CSSYS_CS
+#define BASE_ADDR_LTXBSYS BASE_NADDR_DFESYS_TXBSRP
+//#define BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+#define BASE_ADDR_RAKESYS1 BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define BASE_ADDR_BRPSYS1 BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_MADDR_MODEM_TOPSM BASE_MADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_MADDR_DVFS_TOP BASE_MADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_MADDR_AO_CONFG BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_MADDR_TDMA_SLP BASE_MADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_MADDR_TDD_SLP BASE_MADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_MADDR_TDD_TIMER BASE_MADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_MADDR_FDD_SLP BASE_MADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_MADDR_FDD_TIMER BASE_MADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_MADDR_LTE_SLP BASE_MADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_MADDR_LTETIMER BASE_MADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_MADDR_IDC_CTRL BASE_MADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_MADDR_IDC_UART BASE_MADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_MADDR_C1XTIMER BASE_MADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_MADDR_C1XSLP BASE_MADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_MADDR_CDOTIMER BASE_MADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_MADDR_CDOSLP BASE_MADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_MADDR_FESYS_P2P_TX BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_MADDR_MDRX_P2P_RX BASE_MADDR_MDPERI_MDRXSYS_SRAM_AO
+#define L1_BASE_MADDR_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_MADDR_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_MADDR_AO_BUS_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG
+//#define L1_BASE_MADDR_AO_MBIST_CONFIG BASE_MADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_MADDR_FREQM BASE_MADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_MADDR_MD2GSYS BASE_MADDR_MD2GSYS_IDMA_CM
+#define L1_TDMA_BASE BASE_MADDR_MD2GSYS_TDMA_BASE
+#define BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2GSYS_MD2G_CONFG
+#define BASE_MADDR_MD2G_MBIST_CONFG BASE_MADDR_MD2GSYS_MD2G_MBIST_CONFG
+#define BASE_MADDR_MD2G_TDMA_TMR BASE_MADDR_MD2GSYS_TDMA_BASE
+//#define BASE_MADDR_MD2G_BFE BASE_MADDR_MD2GSYS_BFE
+//#define L1_BASE_MADDR_RXDFESYS BASE_MADDR_RXDFESYS_BUS_CONFIG
+//#define BASE_MADDR_LTE_EVENTGEN BASE_MADDR_RXDFESYS_LTE_EVENTGEN
+//#define BASE_MADDR_FDD_EVENTGEN BASE_MADDR_RXDFESYS_FDD_EVENTGEN
+//#define BASE_MADDR_TDD_EVENTGEN BASE_MADDR_RXDFESYS_TDD_EVENTGEN
+//#define BASE_MADDR_C2K_1X_EVENTGEN BASE_MADDR_RXDFESYS_C1X_EVENTGEN
+//#define BASE_MADDR_C2K_DO_EVENTGEN BASE_MADDR_RXDFESYS_CDO_EVENTGEN
+#define L1_BASE_MADDR_CSSYS BASE_MADDR_CSSYS_CS
+#define L1_BASE_MADDR_TXSYS BASE_MADDR_DFESYS_TXBSRP
+//#define L1_BASE_MADDR_BIGRAMSYS BASE_MADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_MADDR_SHARE_PM BASE_MADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_MADDR_MD32SCQ_VU01 BASE_MADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_MADDR_PERI BASE_MADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_MADDR_DFE_DUMP BASE_MADDR_BRAM_BIGRAM_DFE_DUMP
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_RXT2F BASE_MADDR_BRAM_BIGRAM_RXT2F
+//#define BASE_MADDR_BRDMA BASE_MADDR_BRAM_BIGRAM_BR_DMA
+#define L1_BASE_MADDR_RAKESYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_MADDR_BRPSYS BASE_MADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_NADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_NADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_NADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_NADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_NADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_NADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_NADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_NADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_NADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_NADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_NADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_NADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_NADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_NADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_NADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_NADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_NADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_NADDR_MDRX_P2P_RX BASE_NADDR_MDPERI_MDRXSYS_SRAM_AO
+#define L1_BASE_NADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_NADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_NADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG
+//#define L1_BASE_NADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_NADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_NADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_NADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_NADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_NADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_NADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_NADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_NADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_NADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_NADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+#define L1_BASE_NADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_NADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define L1_BASE_ADDR_MODEM_TOPSM BASE_NADDR_MODEML1_AO_MODEML1_TOPSM
+//#define L1_BASE_ADDR_DVFS_TOP BASE_NADDR_MODEML1_AO_MODEML1_DVFS_CTRL
+#define L1_BASE_ADDR_AO_CONFG BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define L1_BASE_ADDR_TDMA_SLP BASE_NADDR_MODEML1_AO_TDMA_SLP
+#define L1_BASE_ADDR_TDD_SLP BASE_NADDR_MODEML1_AO_TDD_SLP
+#define L1_BASE_ADDR_TDD_TIMER BASE_NADDR_MODEML1_AO_TDD_TIMER
+#define L1_BASE_ADDR_FDD_SLP BASE_NADDR_MODEML1_AO_FDD_SLP
+#define L1_BASE_ADDR_FDD_TIMER BASE_NADDR_MODEML1_AO_FDD_TIMER
+#define L1_BASE_ADDR_LTE_SLP BASE_NADDR_MODEML1_AO_LTE_SLP
+#define L1_BASE_ADDR_LTETIMER BASE_NADDR_MODEML1_AO_LTE_TIMER
+#define L1_BASE_ADDR_IDC_CTRL BASE_NADDR_MODEML1_AO_IDC_CTRL
+#define L1_BASE_ADDR_IDC_UART BASE_NADDR_MODEML1_AO_IDC_UART
+#define L1_BASE_ADDR_C2K_1X_TIMER BASE_NADDR_MODEML1_AO_C2K_1X_TIMER
+#define L1_BASE_ADDR_C2K_1x_SLP BASE_NADDR_MODEML1_AO_C2K_1X_SLP
+#define L1_BASE_ADDR_C2K_DO_TIMER BASE_NADDR_MODEML1_AO_C2K_DO_TIMER
+#define L1_BASE_ADDR_C2K_DO_SLP BASE_NADDR_MODEML1_AO_C2K_DO_SLP
+#define L1_BASE_ADDR_FESYS_P2P_TX BASE_NADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define L1_BASE_ADDR_MDRX_P2P_RX BASE_ADDR_MDPERI_MDRXSYS_SRAM_AO
+#define L1_BASE_ADDR_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define L1_BASE_ADDR_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define L1_BASE_ADDR_AO_BUS_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_SLV_BUS_CONFIG
+//#define L1_BASE_ADDR_AO_MBIST_CONFIG BASE_NADDR_MODEML1_AO_MODEML1_AO_MBIST_CONFIG
+#define L1_BASE_ADDR_FREQM BASE_NADDR_MODEML1_AO_MODEML1_FREQM
+#define L1_BASE_ADDR_MD2GSYS BASE_NADDR_MD2GSYS_IDMA_CM
+//#define L1_BASE_ADDR_RXDFESYS BASE_NADDR_RXDFESYS_BUS_CONFIG
+#define L1_BASE_ADDR_CSSYS BASE_NADDR_CSSYS_CS
+#define L1_BASE_ADDR_TXSYS BASE_NADDR_DFESYS_TXBSRP
+//#define L1_BASE_ADDR_BIGRAMSYS BASE_NADDR_BRAM_BIGRAM_MEM
+//#define L1_BASE_ADDR_SHARE_PM BASE_NADDR_BRAM_SCQ_SHARED_PM
+//#define L1_BASE_ADDR_MD32SCQ_VU01 BASE_NADDR_BRAM_SCQ0_LOCAL_PM
+//#define L1_BASE_ADDR_PERI BASE_NADDR_BRAM_BIGRAMSYS_MBIST_CONFIG
+//#define BASE_ADDR_D2BIF BASE_NADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_ADDR_BIGRAM BASE_MADDR_BRAM_BIGRAM_REG
+#define L1_BASE_ADDR_RAKESYS BASE_NADDR_RAKESYS_RAKE_INST_DEC
+//#define L1_BASE_ADDR_BRPSYS BASE_NADDR_BRP_RXBRP_MBIST_CONFIG
+#define BASE_MADDR_FESYS_AO BASE_MADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+
+/////////////////////////////////////////
+// Manaul Offset
+/////////////////////////////////////////
+//#define BASE_MADDR_MML2_QP_MEM (BASE_MADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_NADDR_MML2_QP_MEM (BASE_NADDR_MML2_QUEUE_PROCESSOR+0x800)
+//#define BASE_ADDR_MML2_QP_MEM (BASE_ADDR_MML2_QUEUE_PROCESSOR+0x800)
+
+#define BASE_MADDR_MML2_META_MEM (0xA2018800)
+#define BASE_NADDR_MML2_META_MEM (0xB2018800)
+#define BASE_ADDR_MML2_META_MEM (0xB2018800)
+
+#define BASE_MADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_MADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_NADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+#define BASE_ADDR_FESYS_MODEML1_AO_CONFIG_ADR_IF BASE_NADDR_MODEML1_AO_MODEML1_AO_CONFG
+
+////#define BASE_MADDR_FESYS_TXDFE_RF BASE_MADDR_TXSYS_TXDFE_RF
+////#define BASE_NADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+////#define BASE_ADDR_FESYS_TXDFE_RF BASE_NADDR_TXSYS_TXDFE_RF
+
+#define BASE_MADDR_FESYS_BSI_MM BASE_MADDR_MODEML1_AO_BSI_MM
+#define BASE_NADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+#define BASE_ADDR_FESYS_BSI_MM BASE_NADDR_MODEML1_AO_BSI_MM
+
+#define BASE_MADDR_FESYS_BPI_MM BASE_MADDR_MODEML1_AO_BPI_MM
+#define BASE_NADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+#define BASE_ADDR_FESYS_BPI_MM BASE_NADDR_MODEML1_AO_BPI_MM
+
+//#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_3 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+//#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_3 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM3
+
+#define BASE_MADDR_FESYS_MDL1AO_BSI_MM_2 BASE_MADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_NADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+#define BASE_ADDR_FESYS_MDL1AO_BSI_MM_2 BASE_NADDR_MODEML1_AO_MDL1_AO_BSI_MM2
+
+////#define BASE_MADDR_FESYS_TXDFE_BB BASE_MADDR_TXSYS_TXDFE_BB
+////#define BASE_NADDR_FESYS_TXDFE_BB BASE_NADDR_TXSYS_TXDFE_BB
+////#define BASE_ADDR_FESYS_TXDFE_BB BASE_ADDR_TXSYS_TXDFE_BB
+
+#endif /* end of __REG_BASE_MERCURY_FPGA_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_FPGA_username.h b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_FPGA_username.h
new file mode 100644
index 0000000..a9127c9
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_FPGA_username.h
@@ -0,0 +1,163 @@
+#ifndef __REG_BASE_MERCURY_FPGA_USERNAME_H__
+#define __REG_BASE_MERCURY_FPGA_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C00000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1F60000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1F60000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1F60000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MERCURY_FPGA_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_username.h b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_username.h
new file mode 100644
index 0000000..bb79b9f
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/reg_base_MERCURY_username.h
@@ -0,0 +1,166 @@
+#ifndef __REG_BASE_MERCURY_USERNAME_H__
+#define __REG_BASE_MERCURY_USERNAME_H__
+
+/****************************
+* AP registers *
+*****************************/
+//WSP/SE7/SD6 Kun Niu
+#define CLDMA0_MD_BASE (0xC023C000)
+#define CLDMA0_AP_BASE (0xC023D000)
+#define CLDMA1_MD_BASE (0xC023E000)
+#define CLDMA1_AP_BASE (0xC023F000)
+#define CLDMA0_AO_MD_BASE (0xC0022000)
+#define CLDMA0_AO_AP_BASE (0xC0023000)
+#define CLDMA1_AO_MD_BASE (0xC0024000)
+#define CLDMA1_AO_AP_BASE (0xC0025000)
+
+//WSP/SE7/SD3 Hanna Chiang
+#define BASE_MADDR_AES_TOP0 (0xC0016000)
+#define EFUSE_base (0xC1C10000)
+
+// SSE/SS2 Justin Chen
+#define BASE_MADDR_EFUSE (EFUSE_base)
+
+// MCD/WSP/SE7/SD9 Da Li
+#define BASE_MADDR_APRGU (0xC3670000)
+#define BASE_NADDR_APRGU (0xD3670000)
+#define BASE_ADDR_APRGU (0xD3670000)
+
+//WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_AP_GPIOMUX (0xC0005000)
+#define BASE_ADDR_AP_GPIOMUX (0xD0005000)
+#define BASE_NADDR_AP_GPIOMUX (0xD0005000)
+
+//WSP/SE7/SD6 Flamingo
+#define BASE_MADDR_PCCIF0_AP (0xC0209000)
+#define BASE_MADDR_PCCIF0_MD (0xC020A000)
+#define BASE_MADDR_PCCIF1_AP (0xC020B000)
+#define BASE_MADDR_PCCIF1_MD (0xC020C000)
+
+//WCS/SE2/CS22 Iris Su
+#define BASE_ADDR_MODEM_TEMP_SHARE (0xD0018000)
+
+//WCS/SE2/CS18 Sophia Huang
+#define BASE_ADDR_TIA (0xD001C000)
+
+//WCS/SSE/SS2 Shin-Chieh Tsai
+#define BASE_MADDR_INFRASYS_EMI_CONFIG (0xC0219000)
+
+//WSP/SE7/SD10 Owen Ho
+#define BASE_INFRA_AO_SYS_TIMER (0xC0017000)
+
+//WSD/OSS1/SS10 Brian-py Chen
+#define BASE_MADDR_APMCU_MISC (0xC0026000)
+//End of AP registers
+/****************************
+* MD registers *
+*****************************/
+
+//WCS/SSE/SS2 Yen-Chun Liu
+#define BASE_ADDR_MDCIRQ_GCR (GCR_CUSTOM_ADDR + 0x4000)
+
+// WSP/SE7/SD3 Bernie Chang
+#define SIM0_base (BASE_MADDR_USIM1)
+#define SIM1_base (BASE_MADDR_USIM2)
+
+//SE7/SD9 shenghui.shi
+#define UART1_base (BASE_MADDR_MDUART0)
+#define UART2_base (BASE_MADDR_MDUART1)
+
+//WCT/SD/SP2 Daniel Lu
+#define PATCH_base (BASE_MADDR_MD2GSYS_PATCH) //FIXIT: the same as L1_BASE_MADDR_PATCH
+
+// SE2/CS15 Shengfu Tsai request
+#define MODEM_TOPSM_base (BASE_MADDR_MODEML1_AO_MODEML1_TOPSM)
+#define TDMA_SLP_base (BASE_MADDR_MODEML1_AO_TDMA_SLP)
+#define FDD_SLP_base (BASE_MADDR_MODEML1_AO_FDD_SLP)
+#define LTE_SLP_base (BASE_MADDR_MODEML1_AO_LTE_SLP)
+
+//WCS/SSE/SS3 Ruta Lin
+#define MD_CONFIG_base BASE_MADDR_MDCFGCTL
+
+//WCT/SE3/PS7 MC Li, temp workaround for build error
+//#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+//#define BASE_MADDR_HSPAL2_CONFIG (0xA0910000)
+//#define BASE_MADDR_HSPAL2_UPA (0xA0920000)
+//#define BASE_MADDR_HSPAL2_MAC (0xA0930000)
+//#define BASE_MADDR_HSPAL2_RLC (0xA0940000)
+//#define BASE_MADDR_PS_PERI_CONFG (0xA0A00000)
+//#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA8400000)
+#define BASE_MADDR_HSPAL2_MBIST (0xA0900000)
+#define BASE_MADDR_HSPAL2_CONFIG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA (0xA0900000)
+#define BASE_MADDR_HSPAL2_MAC (0xA0900000)
+#define BASE_MADDR_HSPAL2_RLC (0xA0900000)
+#define BASE_MADDR_PS_PERI_CONFG (0xA0900000)
+#define BASE_MADDR_HSPAL2_UPA_SRAM (0xA0900000)
+
+//L2 Ciphering UEA var
+#define BASE_MADDR_UEA_UIA_1 BASE_MADDR_MDINFRA_RESERVED0
+#define BASE_MADDR_UEA_UIA_0 BASE_MADDR_MDINFRA_RESERVED1
+
+#define BASE_MADDR_MDINFRA_RESERVED0 (0xA0A50000)
+#define BASE_MADDR_MDINFRA_RESERVED1 (0xA0A40000)
+
+
+// MCD/WSP/SE7/SD9 Zhiqiang Yu
+#define BASE_MADDR_USB20_MAC (0xC1200000)
+#define BASE_MADDR_USB20_PHY (0xC1CC0000)
+#define BASE_MADDR_U3PHY0 (0xC1E40000)
+#define BASE_MADDR_U3MAC0 (0xC1200000)
+#define BASE_MADDR_U3MAC1 (0xC3900000)
+#define BASE_NADDR_USB20_MAC (0xD1200000)
+#define BASE_NADDR_USB20_PHY (0xD1CC0000)
+#define BASE_NADDR_U3PHY0 (0xD1E40000)
+#define BASE_NADDR_U3MAC0 (0xD1200000)
+#define BASE_NADDR_U3MAC1 (0xD3900000)
+#define BASE_ADDR_USB20_MAC (0xD1200000)
+#define BASE_ADDR_USB20_PHY (0xD1CC0000)
+#define BASE_ADDR_U3PHY0 (0xD1E40000)
+#define BASE_ADDR_U3MAC0 (0xD1200000)
+#define BASE_ADDR_U3MAC1 (0xD3900000)
+
+// MTK/SSE/SS3 YY Hsieh
+#define BASE_ADDR_AP_VCORE_DVFS (0xC0012000)
+
+//WCS/SD/SP5 Ming-Yu Lai
+#define BASE_ADDR_TXSYS_TPC_TRG (0xB8221800)
+#define BASE_ADDR_TXSYS_TXK (0xBF441000)
+//WCS/SD/SP5 Claudia Yang
+#define BASE_ADDR_TXSYS_TXK_1 (0xBF451000)
+// WCS/SE2/CS6 Tsung-Yu Tsai
+//#define BASE_MADDR_RXDFESYS_CONFIG_REG (0xA7010000)
+//#define BASE_MADDR_RXDFESYS_MRSG (0xA7110000)
+//#define BASE_MADDR_TXSYS_TXCRP (0xA8100000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG0 (0xA8190000)
+//#define BASE_MADDR_TXSYS_GLB_CON_CONFIG1 (0xA84F0000)
+//#define BASE_MADDR_TXSYS_FDD_TTR (0xA8480000)
+//#define BASE_MADDR_BRAM_BIGRAM_D2BIF (0xAB820000)
+//#define BASE_MADDR_D2BIF BASE_MADDR_BRAM_BIGRAM_D2BIF
+//#define BASE_MADDR_BRAM_BIGRAMSYS_GLOBAL_CON (0xAB810000)
+//#define BASE_MADDR_BRAM_BIGRAM_REG (0xAB830000)
+//#define BASE_MADDR_MODEML1_AO_FDD_EVENTGEN (0xA6230000)
+//#define BASE_MADDR_BRP_RXBRP_BUS_CONFIG (0xAD160000)
+//#define BASE_MADDR_BRP_RXBRP_GLOBAL_CON (0xAD110000)
+
+//WCS/SE2/CS7 Singasani lakshmi reddy
+#define L1_BASE_MADDR_ABB_MIXEDSYS (0xA9296000)
+#define L1_BASE_NADDR_ABB_MIXEDSYS (0xB9296000)
+
+//WSD1/OSS8/ME9 Fu-Shing Ju (for MD speech driver)
+#define AFE_BASE (0xA0E40000) //AFE_BASE c L1_BASE_MADDR_AFE
+#define AFE_SHARED_REGISTER_BASE (0xA87A0000) //AFE_SHARE_REGISTER_BASE L1_BASE_MADDR_SHARE_D1
+#define SPEECHDSP_CONFIG_BASE (0xA0E00000) //uSIP_CONFIG_BASE L1_BASE_MADDR_MD2G_CONFG
+
+//WCS/SSE/SS3 Hou-Yi Chou for BUS build option fix
+#define BASE_MADDR_MDINFRA_SMI_A_CONFIG (0xA04A0000)
+
+//End of MD registers
+
+#if defined(__MIPS_IA__)
+//WCS/SSE/SS3 Tungchieh Tsai
+# define BASE_ADDR_MO_SYNC_MAGIC (0xA1FF0000)
+
+#endif /* __MIPS_IA__ */
+
+#endif /* end of __REG_BASE_MERCURY_USERNAME_H__ */
diff --git a/mcu/interface/driver/regbase/md97p/reg_base_md97p.h b/mcu/interface/driver/regbase/md97p/reg_base_md97p.h
new file mode 100644
index 0000000..ed870e2
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/reg_base_md97p.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * reg_base_md97.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for chipset register base and global configuration registers
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _REG_BASE_MD97P_H
+#define _REG_BASE_MD97P_H
+
+#if defined(MERCURY)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MERCURY_FPGA.h"
+ #else
+ #include "reg_base_MERCURY.h"
+ #endif /*__FPGA__*/
+#else
+ #error "unknown project"
+#endif
+
+#endif /* !_REG_BASE_MD97P_H */
+
diff --git a/mcu/interface/driver/regbase/md97p/reg_base_username_md97p.h b/mcu/interface/driver/regbase/md97p/reg_base_username_md97p.h
new file mode 100644
index 0000000..937b961
--- /dev/null
+++ b/mcu/interface/driver/regbase/md97p/reg_base_username_md97p.h
@@ -0,0 +1,17 @@
+#ifndef __REG_BASE_USERNAME_MD97P_H__
+#define __REG_BASE_USERNAME_MD97P_H__
+
+/* This header file only includes product specific header files.
+ * Please add your reg base difinitions to correct product specific file. */
+
+#if defined(MERCURY)/* only for FPGA */
+ #ifdef __FPGA__
+ #include "reg_base_MERCURY_FPGA_username.h"
+ #else/* not FPGA */
+ #include "reg_base_MERCURY_username.h"
+ #endif
+#else
+ #error "unknown project"
+#endif
+
+#endif /* end of __REG_BASE_USERNAME_MD97P_H__ */
diff --git a/mcu/interface/driver/regbase/reg_base.h b/mcu/interface/driver/regbase/reg_base.h
new file mode 100644
index 0000000..3d941db
--- /dev/null
+++ b/mcu/interface/driver/regbase/reg_base.h
@@ -0,0 +1,513 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * reg_base.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for chipset register base and global configuration registers
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _REG_BASE_H
+#define _REG_BASE_H
+
+
+#define UINT16P unsigned short *
+#define UINT32P unsigned int *
+
+#if defined(__MD93__)
+ #include "md93/reg_base_md93.h"
+#elif defined(__MD95__)
+ #include "md95/reg_base_md95.h"
+#elif defined(__MD97__)
+ #include "md97/reg_base_md97.h"
+#elif defined(__MD97P__)
+ #include "md97p/reg_base_md97p.h"
+#else
+ #error "ERROR in reg_base define (reg_base.h)"
+#endif
+
+#include "cpu_info.h"
+#include "reg_base_username.h"
+
+#if defined(__ESL_ENABLE__)||defined(__ESL_MASE__)
+
+#if defined(__ESL_MASE_GEN97__)
+ #include "reg_base_esl_mase_gen97.h"
+#else
+ #include "reg_base_esl.h"
+#endif
+
+#endif /* __ESL_COSIM_LTE__ */
+
+#endif /* !_REG_BASE_H */
+
diff --git a/mcu/interface/driver/regbase/reg_base_esl.h b/mcu/interface/driver/regbase/reg_base_esl.h
new file mode 100644
index 0000000..cc2cde6
--- /dev/null
+++ b/mcu/interface/driver/regbase/reg_base_esl.h
@@ -0,0 +1,86 @@
+#ifndef __REG_BASE_ESL_H__
+#define __REG_BASE_ESL_H__
+
+#if defined(MT6763) || defined(__MD97__)
+#if defined(__MD97__)
+ #define ESL_REG_BANK 0xD0000000
+#endif
+
+ #undef BASE_ADDR_MDCIRQ
+ #undef BASE_MADDR_MDCIRQ
+
+ #undef BASE_NADDR_MML2_QP_APB
+ #undef BASE_NADDR_MML2_QP_MEM
+ #undef BASE_NADDR_MML2_META_APB
+ #undef BASE_NADDR_MML2_META_MEM
+ #undef BASE_NADDR_MML2_VRB_MANAGER
+ #undef BASE_NADDR_MML2_MMU
+ #undef BASE_NADDR_MML2_DMA_RD
+ #undef BASE_NADDR_MML2_DMA_WR
+ #undef BASE_NADDR_MML2_LHIF
+ #undef BASE_NADDR_MML2_CIPHER
+ #undef BASE_NADDR_MML2_DL_LMAC
+ #undef BASE_NADDR_MML2_HARQ_CTRL
+ #undef BASE_NADDR_MML2_SRAM_WRAP
+ #undef BASE_NADDR_MML2_CFG_TOP
+ #undef BASE_NADDR_MML2_BYC
+ #undef BASE_MADDR_MML2_QP_APB
+ #undef BASE_MADDR_MML2_QP_MEM
+ #undef BASE_MADDR_MML2_META_APB
+ #undef BASE_MADDR_MML2_META_MEM
+ #undef BASE_MADDR_MML2_VRB_MANAGER
+ #undef BASE_MADDR_MML2_MMU
+ #undef BASE_MADDR_MML2_DMA_RD
+ #undef BASE_MADDR_MML2_DMA_WR
+ #undef BASE_MADDR_MML2_LHIF
+ #undef BASE_MADDR_MML2_CIPHER
+ #undef BASE_MADDR_MML2_DL_LMAC
+ #undef BASE_MADDR_MML2_HARQ_CTRL
+ #undef BASE_MADDR_MML2_SRAM_WRAP
+ #undef BASE_MADDR_MML2_CFG_TOP
+ #undef BASE_MADDR_MML2_BYC
+
+ #define BASE_ADDR_MDCIRQ (ESL_REG_BANK + 0x7000000)
+ #define BASE_MADDR_MDCIRQ (ESL_REG_BANK + 0x7000000)
+
+ #define BASE_USCOUNTER (ESL_REG_BANK + 0x1000000)
+ #define BASE_GLOBAL_TS (ESL_REG_BANK + 0x1000010)
+
+ #define BASE_MADDR_MML2_QP_APB (ESL_REG_BANK + 0x0600000)
+ #define BASE_MADDR_MML2_QP_MEM (ESL_REG_BANK + 0x0600800)
+ #define BASE_MADDR_MML2_META_APB (ESL_REG_BANK + 0x0601000)
+ #define BASE_MADDR_MML2_META_MEM (ESL_REG_BANK + 0x0601800)
+ #define BASE_MADDR_MML2_VRB_MANAGER (ESL_REG_BANK + 0x0602000)
+ #define BASE_MADDR_MML2_MMU (ESL_REG_BANK + 0x0603000)
+ #define BASE_MADDR_MML2_DMA_RD (ESL_REG_BANK + 0x0604000)
+ #define BASE_MADDR_MML2_DMA_WR (ESL_REG_BANK + 0x0605000)
+ #define BASE_MADDR_MML2_LHIF (ESL_REG_BANK + 0x0606000)
+ #define BASE_MADDR_MML2_CIPHER (ESL_REG_BANK + 0x0607000)
+ #define BASE_MADDR_MML2_DL_LMAC (ESL_REG_BANK + 0x0608000)
+ #define BASE_MADDR_MML2_HARQ_CTRL (ESL_REG_BANK + 0x0609000)
+ #define BASE_MADDR_MML2_SRAM_WRAP (ESL_REG_BANK + 0x060A000)
+ #define BASE_MADDR_MML2_CFG_TOP (ESL_REG_BANK + 0x060B000)
+ #define BASE_MADDR_MML2_BYC (ESL_REG_BANK + 0x060C000)
+
+ #define BASE_NADDR_MML2_QP_APB BASE_MADDR_MML2_QP_APB
+ #define BASE_NADDR_MML2_QP_MEM BASE_MADDR_MML2_QP_MEM
+ #define BASE_NADDR_MML2_META_APB BASE_MADDR_MML2_META_APB
+ #define BASE_NADDR_MML2_META_MEM BASE_MADDR_MML2_META_MEM
+ #define BASE_NADDR_MML2_VRB_MANAGER BASE_MADDR_MML2_VRB_MANAGER
+ #define BASE_NADDR_MML2_MMU BASE_MADDR_MML2_MMU
+ #define BASE_NADDR_MML2_DMA_RD BASE_MADDR_MML2_DMA_RD
+ #define BASE_NADDR_MML2_DMA_WR BASE_MADDR_MML2_DMA_WR
+ #define BASE_NADDR_MML2_LHIF BASE_MADDR_MML2_LHIF
+ #define BASE_NADDR_MML2_CIPHER BASE_MADDR_MML2_CIPHER
+ #define BASE_NADDR_MML2_DL_LMAC BASE_MADDR_MML2_DL_LMAC
+ #define BASE_NADDR_MML2_HARQ_CTRL BASE_MADDR_MML2_HARQ_CTRL
+ #define BASE_NADDR_MML2_SRAM_WRAP BASE_MADDR_MML2_SRAM_WRAP
+ #define BASE_NADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG_TOP
+ #define BASE_NADDR_MML2_BYC BASE_MADDR_MML2_BYC
+
+
+
+
+#endif /* ELBRUS */
+
+#endif /* end of __REG_BASE_ELBRUS_H__ */
diff --git a/mcu/interface/driver/regbase/reg_base_esl_mase_gen97.h b/mcu/interface/driver/regbase/reg_base_esl_mase_gen97.h
new file mode 100644
index 0000000..35fe132
--- /dev/null
+++ b/mcu/interface/driver/regbase/reg_base_esl_mase_gen97.h
@@ -0,0 +1,265 @@
+/*****
+ * IMPORTANT: reg_base_esl.h and reg_base_MT6297_FPGA.h have two copies:
+ * mcu/protocol/enl2/el2_sec/el2it/custom_hw/MASE_5G_LIB_IA_TLM/reg/...
+ * mcu/interface/driver/regbase/...
+ * If you modify this file, make sure to update the one in the other location as well.
+ *****/
+
+#ifndef __REG_BASE_ESL_MASE_GEN97_H__
+#define __REG_BASE_ESL_MASE_GEN97_H__
+
+#if defined(MT6763) || defined(__MD97__) || defined(MT6885)
+#if defined(__MD97__) || defined(MT6885)
+ #define ESL_REG_BANK 0xD0000000
+#endif
+
+ //only values ESL_REG_START<->ESL_REG_END will be routed from SW to HW model under ESL
+ #define ESL_REG_START 0xD0600000
+ #define ESL_REG_END 0xD07fffff
+
+ //this is a COMPLETE list of register bases used in ESL/ModisHWCopro - all of those are re-defined to fit ESL_REG_START-ESL_REG_END range:
+ #undef BASE_ADDR_MDCIRQ
+ #undef BASE_MADDR_MDCIRQ
+
+ #undef BASE_NADDR_NRL2_VRB_MNG
+ #undef BASE_NADDR_NRL2_GEN95_QP
+ #undef BASE_NADDR_NRL2_NRL2_METADATA_MNG
+ #undef BASE_NADDR_MML2_VRB_MANAGER
+ #undef TEMP_REGISTER_BASE
+ #undef BASE_NADDR_NRL2_NRL2_MMU
+ #undef BASE_NADDR_NRL2_NRL2_TOP_CFG
+ #undef BASE_NADDR_NRL2_LTEDL_LMAC
+ #undef BASE_USCOUNTER
+ #undef BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB
+ #undef BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI
+ #undef BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB
+ #undef BASE_NADDR_NRL2_NRL2_SRAM_WRAP
+ #undef BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP
+ #undef BASE_NADDR_NRL2_DLSYS_5GPL_RDMA
+ #undef BASE_NADDR_NRL2_DLSYS_4GPL_RDMA
+ #undef BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0
+ #undef BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1
+ #undef BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX
+ #undef BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF
+ #undef BASE_NADDR_NRL2_GEN95_RDMA
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_GEN95
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR
+ #undef BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP
+ #undef BASE_ADDR_NRL2_NRL2_QP_UL_LHIF
+ #undef BASE_ADDR_NRL2_DLSYS_COPRO_ARB
+ #undef BASE_ADDR_NRL2_NRL2_QP_UL_NR
+ #undef BASE_ADDR_NRL2_NRL2_QP_UL_RETX
+ #undef BASE_NADDR_MML2_CIPHER
+ #undef BASE_NADDR_NRL2_NRL2_CPHR_NR
+ #undef BASE_ADDR_NRL2_ROHC
+ #undef BASE_NADDR_NRL2_GEN95_CPHR
+ #undef BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH
+ #undef BASE_NADDR_NRL2_NRL2_IPF_DL
+ #undef BASE_NADDR_NRL2_NRL2_IPF_UL
+ #undef BASE_NADDR_NRL2_VRB_MNG
+ #undef BASE_NADDR_NRL2_LTEDL_HARQ
+ #undef BASE_NADDR_NRL2_NRL2_DL_UPP
+ #undef BASE_NADDR_NRL2_NRL2_BUS_SMI
+ #undef TEMP_REGISTER_BASE_HARQ_CON0
+ #undef TEMP_REGISTER_BASE_HARQ_CON1
+ #undef BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL
+ #undef BASE_NADDR_MML2_LHIF
+ #undef BASE_NADDR_MML2_META_APB
+ #undef BASE_GLOBAL_TS
+ #undef BASE_ADDR_NRL2_NRL2_BUS_SMI
+ #undef BASE_NADDR_NRL2_NRL2_QP_UL_LHIF
+ #undef BASE_NADDR_NRL2_DLSYS_COPRO_ARB
+ #undef BASE_NADDR_NRL2_NRL2_QP_UL_NR
+ #undef BASE_NADDR_NRL2_NRL2_QP_UL_RETX
+ #undef BASE_NADDR_NRL2_ROHC
+ #undef BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH
+ #undef BASE_NADDR_MML2_BYC
+ #undef BASE_NADDR_NRL2_DPMAIF_DL
+ #undef BASE_NADDR_NRL2_NRL2_PPHY
+
+ #undef BASE_MADDR_NRL2_VRB_MNG
+ #undef BASE_MADDR_NRL2_GEN95_QP
+ #undef BASE_MADDR_NRL2_NRL2_METADATA_MNG
+ #undef BASE_MADDR_MML2_VRB_MANAGER
+ #undef BASE_MADDR_NRL2_NRL2_MMU
+ #undef BASE_MADDR_NRL2_NRL2_TOP_CFG
+ #undef BASE_MADDR_NRL2_LTEDL_LMAC
+ #undef BASE_MADDR_MDCORESYS_MML2_MCU_MMU_TLB
+ #undef BASE_MADDR_MDCORESYS_MML2_MCU_MMU_AXI
+ #undef BASE_MADDR_MDCORESYS_MML2_MCU_MMU_VRB
+ #undef BASE_MADDR_NRL2_NRL2_SRAM_WRAP
+ #undef BASE_MADDR_NRL2_NRL2_RDMA_DL_UPP
+ #undef BASE_MADDR_NRL2_DLSYS_5GPL_RDMA
+ #undef BASE_MADDR_NRL2_DLSYS_4GPL_RDMA
+ #undef BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC0
+ #undef BASE_MADDR_NRL2_NRL2_RDMA_UL_NR_CC1
+ #undef BASE_MADDR_NRL2_NRL2_RDMA_UL_RETX
+ #undef BASE_MADDR_NRL2_NRL2_RDMA_UL_LHIF
+ #undef BASE_MADDR_NRL2_GEN95_RDMA
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_DL_LMAC
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_GEN95
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_UL_LHIF
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_UL_RETX
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC0
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_UL_NR_CC1
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_DL_DECPHR
+ #undef BASE_MADDR_NRL2_NRL2_WDMA_DL_UPP
+ #undef BASE_MADDR_MML2_CIPHER
+ #undef BASE_MADDR_NRL2_NRL2_CPHR_NR
+ #undef BASE_MADDR_NRL2_GEN95_CPHR
+ #undef BASE_MADDR_NRL2_NRL2_IPF_DL
+ #undef BASE_MADDR_NRL2_NRL2_IPF_UL
+ #undef BASE_MADDR_NRL2_VRB_MNG
+ #undef BASE_MADDR_NRL2_LTEDL_HARQ
+ #undef BASE_MADDR_NRL2_NRL2_DL_UPP
+ #undef BASE_MADDR_NRL2_NRL2_BUS_SMI
+ #undef BASE_MADDR_NRL2_NRL2_IPF_RQ_TBL
+ #undef BASE_MADDR_MML2_LHIF
+ #undef BASE_MADDR_MML2_META_APB
+ #undef BASE_MADDR_NRL2_NRL2_QP_UL_LHIF
+ #undef BASE_MADDR_NRL2_DLSYS_COPRO_ARB
+ #undef BASE_MADDR_NRL2_NRL2_QP_UL_NR
+ #undef BASE_MADDR_NRL2_NRL2_QP_UL_RETX
+ #undef BASE_MADDR_NRL2_ROHC
+ #undef BASE_MADDR_NRL2_NRL2_IPF_PN_MATCH
+ #undef BASE_MADDR_MML2_BYC
+
+ /* For Petrus */
+ #undef BASE_ADDR_NRL2_NRL2_TOP_CFG
+ #undef BASE_MADDR_EFUSE
+
+#ifdef __MTK_TARGET__ //in ESL those two registers have a SPECIAL values outside "Bank D" (ESL_REG_START - ESL_REG_END range), and are NOT routed into HW models
+ #define BASE_USCOUNTER (ESL_REG_BANK + 0x1000000)
+ #define BASE_GLOBAL_TS (ESL_REG_BANK + 0x1000010)
+ /* MCUMMU is not ready in ESL yet
+ * this define should be re-enabled once it becomes ready
+ * #define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (ESL_REG_BANK + 0x1302000)
+ */
+ #define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (ESL_REG_BANK + 0x1303000)
+ #define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (ESL_REG_BANK + 0x1304000)
+ #define BASE_ADDR_MDCIRQ (ESL_REG_BANK + 0x7000000)
+ #define BASE_MADDR_MDCIRQ (ESL_REG_BANK + 0x7000000)
+#else //in MODIS MASE those registers are "regular" and are routed to HW models
+ #define BASE_USCOUNTER (ESL_REG_START + (0x1000*0) + 0x00)
+ #define BASE_GLOBAL_TS (ESL_REG_START + (0x1000*0) + 0x10)
+ #define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI (ESL_REG_START + (0x1000*1))
+ #define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB (ESL_REG_START + (0x1000*2))
+#endif
+
+ #define BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB (ESL_REG_START + (0x1000*3))
+ #define BASE_NADDR_NRL2_GEN95_QP (ESL_REG_START + (0x1000*4))
+ #define BASE_NADDR_NRL2_NRL2_METADATA_MNG (ESL_REG_START + (0x1000*5))
+ #define BASE_NADDR_MML2_VRB_MANAGER (ESL_REG_START + (0x1000*6))
+ #define TEMP_REGISTER_BASE (ESL_REG_START + (0x1000*7))
+ #define BASE_NADDR_NRL2_NRL2_MMU (ESL_REG_START + (0x1000*8))
+ #define BASE_NADDR_NRL2_NRL2_TOP_CFG (ESL_REG_START + (0x1000*9))
+ #define BASE_NADDR_NRL2_LTEDL_LMAC (ESL_REG_START + (0x1000*10))
+ #define BASE_NADDR_NRL2_VRB_MNG (ESL_REG_START + (0x1000*11))
+ #define BASE_NADDR_NRL2_NRL2_SRAM_WRAP (ESL_REG_START + (0x1000*12))
+ #define BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP (ESL_REG_START + (0x1000*13))
+ #define BASE_NADDR_NRL2_DLSYS_5GPL_RDMA (ESL_REG_START + (0x1000*14))
+ #define BASE_NADDR_NRL2_DLSYS_4GPL_RDMA (ESL_REG_START + (0x1000*15))
+ #define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0 (ESL_REG_START + (0x1000*16))
+ #define BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1 (ESL_REG_START + (0x1000*17))
+ #define BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX (ESL_REG_START + (0x1000*18))
+ #define BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF (ESL_REG_START + (0x1000*19))
+ #define BASE_NADDR_NRL2_GEN95_RDMA (ESL_REG_START + (0x1000*20))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC (ESL_REG_START + (0x1000*21))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_GEN95 (ESL_REG_START + (0x1000*22))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF (ESL_REG_START + (0x1000*23))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX (ESL_REG_START + (0x1000*24))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0 (ESL_REG_START + (0x1000*25))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1 (ESL_REG_START + (0x1000*26))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR (ESL_REG_START + (0x1000*27))
+ #define BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP (ESL_REG_START + (0x1000*28))
+ #define BASE_ADDR_NRL2_NRL2_QP_UL_LHIF (ESL_REG_START + (0x1000*29))
+ #define BASE_ADDR_NRL2_DLSYS_COPRO_ARB (ESL_REG_START + (0x1000*30))
+ #define BASE_ADDR_NRL2_NRL2_QP_UL_NR (ESL_REG_START + (0x1000*31))
+ #define BASE_ADDR_NRL2_NRL2_QP_UL_RETX (ESL_REG_START + (0x1000*32))
+ #define BASE_NADDR_MML2_CIPHER (ESL_REG_START + (0x1000*33))
+ #define BASE_NADDR_NRL2_NRL2_CPHR_NR (ESL_REG_START + (0x1000*34))
+ #define BASE_ADDR_NRL2_ROHC (ESL_REG_START + (0x1000*35))
+ #define BASE_NADDR_NRL2_GEN95_CPHR (ESL_REG_START + (0x1000*36))
+ #define BASE_ADDR_NRL2_NRL2_IPF_PN_MATCH (ESL_REG_START + (0x1000*37))
+ #define BASE_NADDR_NRL2_NRL2_IPF_DL (ESL_REG_START + (0x1000*38))
+ #define BASE_NADDR_NRL2_NRL2_IPF_UL (ESL_REG_START + (0x1000*39))
+ #define BASE_NADDR_NRL2_LTEDL_HARQ (ESL_REG_START + (0x1000*40))
+ #define BASE_NADDR_NRL2_NRL2_DL_UPP (ESL_REG_START + (0x1000*41))
+ #define BASE_NADDR_NRL2_NRL2_BUS_SMI (ESL_REG_START + (0x1000*42))
+ #define TEMP_REGISTER_BASE_HARQ_CON0 (ESL_REG_START + (0x1000*43))
+ #define TEMP_REGISTER_BASE_HARQ_CON1 (ESL_REG_START + (0x1000*44))
+ #define BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL (ESL_REG_START + (0x1000*45))
+ #define BASE_NADDR_MML2_LHIF (ESL_REG_START + (0x1000*46))
+ #define BASE_NADDR_MML2_META_APB (BASE_NADDR_NRL2_NRL2_METADATA_MNG)
+ #define BASE_ADDR_NRL2_NRL2_BUS_SMI (ESL_REG_START + (0x1000*48))
+ #define BASE_NADDR_NRL2_NRL2_QP_UL_LHIF (ESL_REG_START + (0x1000*49))
+ #define BASE_NADDR_NRL2_DLSYS_COPRO_ARB (ESL_REG_START + (0x1000*50))
+ #define BASE_NADDR_NRL2_NRL2_QP_UL_NR (ESL_REG_START + (0x1000*51))
+ #define BASE_NADDR_NRL2_NRL2_QP_UL_RETX (ESL_REG_START + (0x1000*52))
+ #define BASE_NADDR_NRL2_ROHC (ESL_REG_START + (0x1000*53))
+ #define BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH (ESL_REG_START + (0x1000*54))
+ #define BASE_NADDR_MML2_BYC (ESL_REG_START + (0x1000*55))
+ #define BASE_NADDR_NRL2_DPMAIF_DL (ESL_REG_START + (0x1000*56))
+ #define DP_AP_REG_BASE_MD_VIEW (ESL_REG_START + (0x1000*57)) /* Must leave at least 0x20000 gap for these registers
+ * see dpmaif_dev_arch97_md.h for reg range
+ */
+ #define BASE_NADDR_NRL2_NRL2_PPHY (ESL_REG_START + (0x1000*90))
+
+ /* DPMAIF Reg bases */
+ #define BASE_NADDR_NRL2_DPMAIF_MD_MISC (ESL_REG_START + (0x1000*91))
+ #define BASE_NADDR_NRL2_DPMAIF_MD_DL_REORDER (ESL_REG_START + (0x1000*92))
+ #define BASE_NADDR_NRL2_DPMAIF_DL_REORDER (ESL_REG_START + (0x1000*93))
+ #define BASE_NADDR_NRL2_DPMAIF_DL_RB_DBG (ESL_REG_START + (0x1000*94))
+ #define BASE_NADDR_NRL2_DPMAIF_DL_AO_AP_CFG (ESL_REG_START + (0x1000*95))
+
+ /* For Petrus */
+ #define BASE_NADDR_NRL2_DPMAIF_DL_AO_CFG (ESL_REG_START + (0x1000*96))
+ #define BASE_ADDR_NRL2_NRL2_TOP_CFG (ESL_REG_START + (0x1000*97))
+ #define BASE_MADDR_EFUSE (ESL_REG_START + (0x1000*98))
+
+
+#if defined (__ESL_MASE_GEN97__)
+/* IMPORTANT: if you need to modify registers in this block - do the same modification in this file:
+ //UMOLYE_CBr/steve.barrett/UMOLYE.GEN97.DEV_MODIS_MASE/mcu/protocol/enl2/el2_sec/el2it/custom_hw/MASE_5G_LIB_IA_TLM/reg/reg_base.h
+
+ Those registers are for MODIS/ESL simulation only.
+*/
+
+// Temporary Registers introduced for 97 prototype code for the UL cipher engine, I will remove these as part of James UL COTF work:
+#define NRL2_QP_5G_UL_MAC_TRIG_CH0 (TEMP_REGISTER_BASE+0x04)
+#define NRL2_QP_5G_UL_MAC_TRIG_CH1 (TEMP_REGISTER_BASE+0x08)
+#define NRL2_QP_5G_UL_MAC_TRIG_CH2 (TEMP_REGISTER_BASE+0x0C)
+#define NRL2_QP_5G_UL_MAC_TRIG_CH3 (TEMP_REGISTER_BASE+0x10)
+
+#define NRL2_UPP_META_BUF_READY_THRES (TEMP_REGISTER_BASE+0x14) /* Email sent to Chi-Yen for clarification on this one */
+
+#define MML2_PPHY_CON (TEMP_REGISTER_BASE+0x18) /* LTE DL TB trigger (for MASE only), add to nrl2_ltedl_lmac.h */
+#define MML2_UPP_TRIG_TB (TEMP_REGISTER_BASE+0x1C) /* UPP DL TB trigger (for MASE only), add to nrl2_dl_upp.h reg file */
+#define MML2_SRAM_CON7 (TEMP_REGISTER_BASE+0x20) /* Used for initisalising the COPRO HW SRAM, would suggest adding the this register to nrl2_sram_wrap.h */
+#define MML2_UL_COTF_DESC_ACTIVITY (TEMP_REGISTER_BASE+0x24) /* Used to monitor activity in COTF (HW model) in MASE */
+#define FAKE_REG_NOTIFY_HW_SIM_DONE (TEMP_REGISTER_BASE+0x28) /* MASE task tells HW models that SIM is ending */
+#endif /* __ESL_MASE_GEN97__ */
+
+// LHIF registers
+#define MML2_LHIF_SETTING ((unsigned) BASE_NADDR_MML2_LHIF + 0x0)
+#define MML2_LHIF_LOG_SETTING ((unsigned) BASE_NADDR_MML2_LHIF + 0x4)
+#define MML2_LHIF_LOG_SEQ ((unsigned) BASE_NADDR_MML2_LHIF + 0x8)
+#define MML2_LHIF_EXCEP_STATUS ((unsigned) BASE_NADDR_MML2_LHIF + 0x10)
+#define MML2_LHIF_EXCEP_MASK ((unsigned) BASE_NADDR_MML2_LHIF + 0x14)
+#define FAKE_MML2_LHIF_CLR_INT ((unsigned) BASE_NADDR_MML2_LHIF + 0xF0)
+#define FAKE_MML2_LHIF_AP_UL_SETTING ((unsigned) BASE_NADDR_MML2_LHIF + 0xF4)
+#define FAKE_MML2_LHIF_AP_UL_BURST_GEN ((unsigned) BASE_NADDR_MML2_LHIF + 0xF8)
+#define FAKE_MML2_LHIF_REORDER_ACTIVITY ((unsigned) BASE_NADDR_MML2_LHIF + 0xFC) /* Used to monitor activity in LHIF Reordering (HW model) in MASE */
+
+//LHIF log part
+// BYTECOPY registers
+#define FAKE_IOCU_TEST_ADDR ((unsigned) BASE_NADDR_MML2_BYC + 0x0)
+#define FAKE_IOCU_TEST_RESULT ((unsigned) BASE_NADDR_MML2_BYC + 0x4)
+#endif /* MT6763 || __MD97__ */
+
+#endif /* !__REG_BASE_ESL_MASE_GEN97_H__ */
diff --git a/mcu/interface/driver/regbase/reg_base_username.h b/mcu/interface/driver/regbase/reg_base_username.h
new file mode 100644
index 0000000..233f7fe
--- /dev/null
+++ b/mcu/interface/driver/regbase/reg_base_username.h
@@ -0,0 +1,21 @@
+#ifndef __REG_BASE_USERNAME_H__
+#define __REG_BASE_USERNAME_H__
+
+#include "boot.h"
+
+/* This header file only includes product specific header files.
+ * Please add your reg base difinitions to correct product specific file. */
+
+ #if defined(__MD93__)
+ #include "md93/reg_base_username_md93.h"
+ #elif defined(__MD95__)
+ #include "md95/reg_base_username_md95.h"
+ #elif defined(__MD97__)
+ #include "md97/reg_base_username_md97.h"
+ #elif defined(__MD97P__)
+ #include "md97p/reg_base_username_md97p.h"
+ #else
+ #error "ERROR in reg_base_username define (reg_base_username.h)"
+ #endif
+
+#endif /* end of __REG_BASE_USERNAME_H__ */