[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/sys_drv/asm_def.h b/mcu/interface/driver/sys_drv/asm_def.h
new file mode 100644
index 0000000..8aba388
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/asm_def.h
@@ -0,0 +1,32 @@
+#ifndef _ASM_DEF_H
+#define _ASM_DEF_H
+
+//#if defined(__PCORE__)
+
+#ifdef __THUMB2_UNIFIED__
+#define FUNC_ATTR(name) .thumb_func
+#define CPU_ISA() .thumb
+#define ISA_UNIFIED_SETTING() .syntax unified
+#else
+#define FUNC_ATTR(name) .type name, %function
+#define CPU_ISA() .arm
+#define ISA_UNIFIED_SETTING()
+#endif
+
+#ifdef __STACK_ALIGN_MPU__
+#define STACK_ALIGN_NUM 5
+#else
+#define STACK_ALIGN_NUM 3
+#endif
+
+
+//#else
+
+//#define FUNC_ATTR(name) .type name, %function
+//#define CPU_ISA() .arm
+//#define ISA_UNIFIED_SETTING()
+
+//#endif
+
+#endif
+
diff --git a/mcu/interface/driver/sys_drv/boot.h b/mcu/interface/driver/sys_drv/boot.h
new file mode 100644
index 0000000..4337657
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/boot.h
@@ -0,0 +1,390 @@
+/*
+ * boot.h
+ *
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#ifndef __BOOT_H__
+#define __BOOT_H__
+
+// Segmentation Control CP0 registers
+// Example setting SegCtl2 for Legacy KUSEG (CFG4 and CFG5)
+// li t4, (SEGCTL_CFG4_AM_MUSK | SEGCTL_CFG5_AM_MUSK | SEGCTL_CFG4_PA_0 | SEGCTL_CFG5_PA_4 | SEGCTL_CFG4_EU | SEGCTL_CFG5_EU)
+// mtc0 s0, C0_SEGCTL2
+
+
+/*#define C0_SEGCTL0 $5, 2
+#define C0_SEGCTL1 $5, 3
+#define C0_SEGCTL2 $5, 4
+#define C0_CONFIG4 $16, 4
+#define C0_CONFIG5 $16, 5*/
+
+// Segmentation Control AM - Access mode bits
+// AM Masks
+#define SEGCTL_CFG0_AM_MASK 0x00000070
+#define SEGCTL_CFG2_AM_MASK 0x00000070
+#define SEGCTL_CFG4_AM_MASK 0x00000070
+
+#define SEGCTL_CFG1_AM_MASK 0x00700000
+#define SEGCTL_CFG3_AM_MASK 0x00700000
+#define SEGCTL_CFG5_AM_MASK 0x00700000
+
+// AM Settings
+// UK UnMapped Kernel
+#define SEGCTL_CFG0_AM_UK 0x00000000
+#define SEGCTL_CFG2_AM_UK 0x00000000
+#define SEGCTL_CFG4_AM_UK 0x00000000
+
+#define SEGCTL_CFG1_AM_UK 0x00000000
+#define SEGCTL_CFG3_AM_UK 0x00000000
+#define SEGCTL_CFG5_AM_UK 0x00000000
+
+// MK Mapped Kernel
+#define SEGCTL_CFG0_AM_MK 0x00000010
+#define SEGCTL_CFG2_AM_MK 0x00000010
+#define SEGCTL_CFG4_AM_MK 0x00000010
+
+#define SEGCTL_CFG1_AM_MK 0x00100000
+#define SEGCTL_CFG3_AM_MK 0x00100000
+#define SEGCTL_CFG5_AM_MK 0x00100000
+
+// MSK Mapped Supervisor Kernel
+#define SEGCTL_CFG0_AM_MSK 0x00000020
+#define SEGCTL_CFG2_AM_MSK 0x00000020
+
+#define SEGCTL_CFG1_AM_MSK 0x00200000
+#define SEGCTL_CFG3_AM_MSK 0x00200000
+#define SEGCTL_CFG5_AM_MSK 0x00200000
+
+// MUSK Mapped User Supervisor Kernel
+#define SEGCTL_CFG0_AM_MUSK 0x00000030
+#define SEGCTL_CFG2_AM_MUSK 0x00000030
+#define SEGCTL_CFG4_AM_MUSK 0x00000030
+
+#define SEGCTL_CFG1_AM_MUSK 0x00300000
+#define SEGCTL_CFG3_AM_MUSK 0x00300000
+#define SEGCTL_CFG5_AM_MUSK 0x00300000
+
+// MUSUK Mapped User and Supervisor and Unmapped Kernel
+#define SEGCTL_CFG0_AM_MUSUK 0x00000040
+#define SEGCTL_CFG2_AM_MUSUK 0x00000040
+#define SEGCTL_CFG4_AM_MUSUK 0x00000040
+
+#define SEGCTL_CFG1_AM_MUSUK 0x00400000
+#define SEGCTL_CFG3_AM_MUSUK 0x00400000
+#define SEGCTL_CFG5_AM_MUSUK 0x00400000
+
+// USK Unmapped Supervisor and Kernel Segment
+#define SEGCTL_CFG0_AM_USK 0x00000050
+#define SEGCTL_CFG2_AM_USK 0x00000050
+#define SEGCTL_CFG4_AM_USK 0x00000050
+
+#define SEGCTL_CFG1_AM_USK 0x00500000
+#define SEGCTL_CFG3_AM_USK 0x00500000
+#define SEGCTL_CFG5_AM_USK 0x00500000
+
+// UUSK Unrestricted Unmapped Segment
+#define SEGCTL_CFG0_AM_UUSK 0x00000070
+#define SEGCTL_CFG2_AM_UUSK 0x00000070
+#define SEGCTL_CFG4_AM_UUSK 0x00000070
+
+#define SEGCTL_CFG1_AM_UUSK 0x00700000
+#define SEGCTL_CFG3_AM_UUSK 0x00700000
+#define SEGCTL_CFG5_AM_UUSK 0x00700000
+
+// Segmentation Control PA - Physical Address bits
+// PA Masks
+#define SEGCTL_CFG0_PA_MASK 0x00000E00
+#define SEGCTL_CFG2_PA_MASK 0x00000E00
+#define SEGCTL_CFG4_PA_MASK 0x00000E00
+
+#define SEGCTL_CFG1_PA_MASK 0x0E000000
+#define SEGCTL_CFG3_PA_MASK 0x0E000000
+#define SEGCTL_CFG5_PA_MASK 0x0E000000
+
+// PA Settings
+// PA 0x0000 0000
+#define SEGCTL_CFG0_PA_0 0x00000000
+#define SEGCTL_CFG2_PA_0 0x00000000
+#define SEGCTL_CFG4_PA_0 0x00000000
+
+#define SEGCTL_CFG1_PA_0 0x00000000
+#define SEGCTL_CFG3_PA_0 0x00000000
+#define SEGCTL_CFG5_PA_0 0x00000000
+
+// PA 0x2000 0000
+#define SEGCTL_CFG0_PA_2 0x00000200
+#define SEGCTL_CFG2_PA_2 0x00000200
+#define SEGCTL_CFG4_PA_2 0x00000200
+
+#define SEGCTL_CFG1_PA_2 0x02000000
+#define SEGCTL_CFG3_PA_2 0x02000000
+#define SEGCTL_CFG5_PA_2 0x02000000
+
+// PA 0x4000 0000
+#define SEGCTL_CFG0_PA_4 0x00000400
+#define SEGCTL_CFG2_PA_4 0x00000400
+#define SEGCTL_CFG4_PA_4 0x00000400
+
+#define SEGCTL_CFG1_PA_4 0x04000000
+#define SEGCTL_CFG3_PA_4 0x04000000
+#define SEGCTL_CFG5_PA_4 0x04000000
+
+// PA 0x6000 0000
+#define SEGCTL_CFG0_PA_6 0x00000600
+#define SEGCTL_CFG2_PA_6 0x00000600
+#define SEGCTL_CFG4_PA_6 0x00000600
+
+#define SEGCTL_CFG1_PA_6 0x06000000
+#define SEGCTL_CFG3_PA_6 0x06000000
+#define SEGCTL_CFG5_PA_6 0x06000000
+
+// PA 0x8000 0000
+#define SEGCTL_CFG0_PA_8 0x00000800
+#define SEGCTL_CFG2_PA_8 0x00000800
+#define SEGCTL_CFG4_PA_8 0x00000800
+
+#define SEGCTL_CFG1_PA_8 0x08000000
+#define SEGCTL_CFG3_PA_8 0x08000000
+#define SEGCTL_CFG5_PA_8 0x08000000
+
+// PA 0xA000 0000
+#define SEGCTL_CFG0_PA_A 0x00000A00
+#define SEGCTL_CFG2_PA_A 0x00000A00
+#define SEGCTL_CFG4_PA_A 0x00000A00
+
+#define SEGCTL_CFG1_PA_A 0x0A000000
+#define SEGCTL_CFG3_PA_A 0x0A000000
+#define SEGCTL_CFG5_PA_A 0x0A000000
+
+// PA 0xC000 0000
+#define SEGCTL_CFG0_PA_C 0x00000C00
+#define SEGCTL_CFG2_PA_C 0x00000C00
+#define SEGCTL_CFG4_PA_C 0x00000C00
+
+#define SEGCTL_CFG1_PA_C 0x0C000000
+#define SEGCTL_CFG3_PA_C 0x0C000000
+#define SEGCTL_CFG5_PA_C 0x0C000000
+
+// PA 0xE000 0000
+#define SEGCTL_CFG0_PA_E 0x00000E00
+#define SEGCTL_CFG2_PA_E 0x00000E00
+#define SEGCTL_CFG4_PA_E 0x00000E00
+
+#define SEGCTL_CFG1_PA_E 0x0E000000
+#define SEGCTL_CFG3_PA_E 0x0E000000
+#define SEGCTL_CFG5_PA_E 0x0E000000
+
+// Segmentation Control EU - Error Condiction bits
+// EU Masks
+#define SEGCTL_CFG0_EU_MASK 0x00000008
+#define SEGCTL_CFG2_EU_MASK 0x00000008
+#define SEGCTL_CFG4_EU_MASK 0x00000008
+
+#define SEGCTL_CFG1_EU_MASK 0x00080000
+#define SEGCTL_CFG3_EU_MASK 0x00080000
+#define SEGCTL_CFG5_EU_MASK 0x00080000
+
+// EU bit setting
+#define SEGCTL_CFG0_EU 0x00000008
+#define SEGCTL_CFG2_EU 0x00000008
+#define SEGCTL_CFG4_EU 0x00000008
+
+#define SEGCTL_CFG1_EU 0x00080000
+#define SEGCTL_CFG3_EU 0x00080000
+#define SEGCTL_CFG5_EU 0x00080000
+
+// Segmentation Control C - Cache Coherency Attribute bits
+// C Masks
+#define SEGCTL_CFG0_C_MASK 0x00000007
+#define SEGCTL_CFG2_C_MASK 0x00000007
+#define SEGCTL_CFG4_C_MASK 0x00000007
+
+#define SEGCTL_CFG1_C_MASK 0x00070000
+#define SEGCTL_CFG3_C_MASK 0x00070000
+#define SEGCTL_CFG5_C_MASK 0x00070000
+
+// C Bit setting
+// UC Uncached, non Coherent
+#define SEGCTL_CFG0_C_UC 0x00000002
+#define SEGCTL_CFG2_C_UC 0x00000002
+#define SEGCTL_CFG4_C_UC 0x00000002
+
+#define SEGCTL_CFG1_C_UC 0x00020000
+#define SEGCTL_CFG3_C_UC 0x00020000
+#define SEGCTL_CFG5_C_UC 0x00020000
+
+// WB Writeback, write-allocate, non-coherent
+#define SEGCTL_CFG0_C_WB 0x00000003
+#define SEGCTL_CFG2_C_WB 0x00000003
+#define SEGCTL_CFG4_C_WB 0x00000003
+
+#define SEGCTL_CFG1_C_WB 0x00030000
+#define SEGCTL_CFG3_C_WB 0x00030000
+#define SEGCTL_CFG5_C_WB 0x00030000
+
+// CWBE Writeback, write-allocate, coherent, exclusive
+#define SEGCTL_CFG0_C_CWBE 0x00000004
+#define SEGCTL_CFG2_C_CWBE 0x00000004
+#define SEGCTL_CFG4_C_CWBE 0x00000004
+
+#define SEGCTL_CFG1_C_CWBE 0x00040000
+#define SEGCTL_CFG3_C_CWBE 0x00040000
+#define SEGCTL_CFG5_C_CWBE 0x00040000
+
+// CWB Writeback, write-allocate, coherent, exclusive on write
+#define SEGCTL_CFG0_C_CWB 0x00000005
+#define SEGCTL_CFG2_C_CWB 0x00000005
+#define SEGCTL_CFG4_C_CWB 0x00000005
+
+#define SEGCTL_CFG1_C_CWB 0x00050000
+#define SEGCTL_CFG3_C_CWB 0x00050000
+#define SEGCTL_CFG5_C_CWB 0x00050000
+
+// UCA Uncached accelerated, non-coherent
+#define SEGCTL_CFG0_C_UCA 0x00000007
+#define SEGCTL_CFG2_C_UCA 0x00000007
+#define SEGCTL_CFG4_C_UCA 0x00000007
+
+#define SEGCTL_CFG1_C_UCA 0x00070000
+#define SEGCTL_CFG3_C_UCA 0x00070000
+#define SEGCTL_CFG5_C_UCA 0x00070000
+
+#define LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define L2SRAM_L2C_LEAF(name)\
+ .##section "L2SRAM_L2C_ROCODE", "ax";\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#if defined(__MD93__)
+#define L2CACHE_LOCK_LEAF(name)\
+ .##section "L2CACHE_LOCK_ROCODE", "ax";\
+ .##globl name;\
+ .##ent name;\
+name:
+#else
+#define L2CACHE_LOCK_LEAF(name) LEAF(name)
+#endif
+
+#define NONCACHED_ROCODE_LEAF(name)\
+ .##section "NONCACHED_ROCODE", "ax";\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define END(name)\
+ .##size name,.-name;\
+ .##end name
+
+//#define GCR_CONFIG_ADDR 0xbfbf8000 // KSEG1 address of the GCR registers
+#define GCR_CONFIG_ADDR 0x1f000000 // KSEG1 address of the GCR registers
+#define GCR_CUSTOM_ADDR 0x1f010000 // KSEG1 address of the GCR registers
+#define GIC_P_BASE_ADDR 0x1f020000 // physical address of the GIC
+#define GIC_BASE_ADDR 0x1f020000 // KSEG1 address address of the GIC
+#define CPC_P_BASE_ADDR 0x1f008000 // physical address of the CPC
+#define CPC_BASE_ADDR 0x1f008000 // KSEG1 address address of the CPC
+#define GCR_CDMM_ADDR 0x1fc10000
+
+#define DENALI_CTL_SECTION 0xbbc00000
+#define MALTA_DISP_ADDR 0xbf000410
+
+#define STACK_BASE_ADDR 0x82000000 /* Change: Base on memory size. */
+#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
+
+
+/**************************************************************************************
+ Register use while executing in this file: ("GLOBAL" denotes a common value.)
+**************************************************************************************/
+
+#if defined(__MIPS_IA__)
+#define r1_all_ones $1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
+
+// $2 - $7 (v0, v1 a0 - a3) reserved for program use
+
+#define r8_core_num $8 /* t0 Core number. Only core 0 is active after reset. */
+#define r9_vpe_num $9 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */
+#define r10_has_mt_ase $10 /* t2 Core implements the MT ASE. */
+#define r11_is_cps $11 /* t3 Core is part of a Coherent Processing System. */
+
+// $12 - $15 (t4 - t7) are free to use
+// $16, $17 (s0 and s1) reserved for program use
+
+#define r18_tc_num $18 /* s2 MT ASE TC number (0 if non-MT.) */
+#define r19_more_cores $19 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */
+#define r20_more_vpes $20 /* s4 Number of vpes in this core in addition to vpe 0. */
+#define r21_more_tcs $21 /* s5 Number of tcs in vpe in addition to the first. */
+#define r22_gcr_addr $22 /* s6 Uncached (kseg1) base address of the Global Config Registers. */
+#define r23_cpu_num $23 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
+#define r24_malta_word $24 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
+#define r25_coreid $25 /* t9 Copy of cp0 PRiD GLOBAL! */
+#define r26_int_addr $26 /* k0 Interrupt handler scratch address. */
+#define r27_int_data $27 /* k1 Interrupt handler scratch data. */
+// $28 gp and $29 sp
+#define r30_cpc_addr $30 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */
+// $31 ra
+
+#else
+
+// $2 - $7 (v0, v1 a0 - a3) reserved for program use
+
+#define r8_core_num $t0 /* t0 Core number. Only core 0 is active after reset. */
+#define r9_vpe_num $t1 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */
+#define r10_has_mt_ase $t2 /* t2 Core implements the MT ASE. */
+#define r11_is_cps $t3 /* t3 Core is part of a Coherent Processing System. */
+
+// $12 - $15 (t4 - t7) are free to use
+// $16, $17 (s0 and s1) reserved for program use
+
+#define r18_tc_num $s2 /* s2 MT ASE TC number (0 if non-MT.) */
+#define r19_more_cores $s3 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */
+#define r20_more_vpes $s4 /* s4 Number of vpes in this core in addition to vpe 0. */
+#define r21_more_tcs $s5 /* s5 Number of tcs in vpe in addition to the first. */
+#define r22_gcr_addr $s6 /* s6 Uncached (kseg1) base address of the Global Config Registers. */
+#define r23_cpu_num $s7 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
+#define r24_malta_word $t8 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
+#define r25_coreid $t9 /* t9 Copy of cp0 PRiD GLOBAL! */
+#define r26_int_addr $k0 /* k0 Interrupt handler scratch address. */
+#define r27_int_data $k1 /* k1 Interrupt handler scratch data. */
+// $28 gp and $29 sp
+#define r30_cpc_addr $s8 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */
+// $31 ra
+
+#endif
+#endif /* __BOOT_H__ */
+
+
diff --git a/mcu/interface/driver/sys_drv/boot_comm.h b/mcu/interface/driver/sys_drv/boot_comm.h
new file mode 100644
index 0000000..0e4f9de
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/boot_comm.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * boot_comm.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ * Rev 1.0 Nov 30 2002 19:49:52 admin
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _BOOT_COMM_H
+#define _BOOT_COMM_H
+
+#define TEMP_UNCACHE_BOOTSTACK_BANK (0x00000000)
+#define TEMP_UNCACHE_BOOTSTACK_MASK (0xF0000000)
+#define TEMP_CACHE_BOOTSTACK_BANK (0x6)
+
+
+#define BOOT_SYS_STACK_SIZE (1024)
+#define BOOT_CORE0_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
+#if !defined(__SINGLE_CORE__)
+#define BOOT_CORE1_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
+#if (defined(__MD95__) && !defined(__MD95_IS_2CORES__)) || (defined(MT6297_IA))
+#define BOOT_CORE2_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
+#endif
+#if (defined(MT6297_IA))
+#define BOOT_CORE3_SYS_STACK_SIZE (BOOT_SYS_STACK_SIZE)
+#endif
+#endif
+
+// bootup trace
+#define VPE_BOOTUP_TRC_SIZE (256) // bytes
+
+#define BOOTUP_TRC_OFFSET (1024*7)
+#define BOOTUP_TRC_MAGIC (0x746F6200) // ascii : nBOT
+
+#define BOOTUP_TRC_ID_LEN (10)
+#define BOOTUP_TRC_ID_MASK ((1<<BOOTUP_TRC_ID_LEN) - 1)
+#define BOOTUP_TRC_FRC_MASK (0xFFFFFFFF ^ BOOTUP_TRC_ID_MASK)
+
+#define BASE_MD_FMA_ADDR (GCR_CUSTOM_ADDR)
+#define MD_USCNTI_VAL_ADDR (BASE_MD_FMA_ADDR + 0x40)
+#if defined(__MD97__) || defined(__MD97P__)
+#if defined(MT6297)
+#define BOOTTRC_CCIF0_OLD_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA)
+#define BOOTTRC_CCIF0_OLD_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*1)
+#define BOOTTRC_CCIF0_OLD_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*2)
+#define BOOTTRC_CCIF0_OLD_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*3)
+#define BOOTTRC_CCIF0_OLD_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*4)
+#define BOOTTRC_CCIF0_OLD_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*5)
+#define BOOTTRC_CCIF0_OLD_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*6)
+#define BOOTTRC_CCIF0_OLD_VPE6_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*7)
+#define BOOTTRC_CCIF0_OLD_VPE7_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*8)
+#define BOOTTRC_CCIF0_OLD_VPE8_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
+#define BOOTTRC_CCIF0_OLD_VPE9_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*10)
+#define BOOTTRC_CCIF0_OLD_VPE10_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
+#define BOOTTRC_CCIF0_OLD_VPE11_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*12)
+#else
+#define BOOTTRC_CCIF0_NEW_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA)
+#define BOOTTRC_CCIF0_NEW_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*1)
+#define BOOTTRC_CCIF0_NEW_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*2)
+#define BOOTTRC_CCIF0_NEW_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*3)
+#define BOOTTRC_CCIF0_NEW_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*4)
+#define BOOTTRC_CCIF0_NEW_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*5)
+#define BOOTTRC_CCIF0_NEW_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*6)
+#define BOOTTRC_CCIF0_NEW_VPE6_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*7)
+#define BOOTTRC_CCIF0_NEW_VPE7_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*8)
+#define BOOTTRC_CCIF0_NEW_VPE8_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
+#define BOOTTRC_CCIF0_NEW_VPE9_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*10)
+#define BOOTTRC_CCIF0_NEW_VPE10_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
+#define BOOTTRC_CCIF0_NEW_VPE11_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*12)
+#endif
+#else //__MD97__
+#define BOOTTRC_CCIF0_NEW_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA)
+#define BOOTTRC_CCIF0_NEW_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*1)
+#define BOOTTRC_CCIF0_NEW_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*3)
+#define BOOTTRC_CCIF0_NEW_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*5)
+#define BOOTTRC_CCIF0_NEW_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*7)
+#define BOOTTRC_CCIF0_NEW_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
+#define BOOTTRC_CCIF0_NEW_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
+
+#define BOOTTRC_CCIF0_OLD_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*9)
+#define BOOTTRC_CCIF0_OLD_VPE0_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*10)
+#define BOOTTRC_CCIF0_OLD_VPE1_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*11)
+#define BOOTTRC_CCIF0_OLD_VPE2_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*12)
+#define BOOTTRC_CCIF0_OLD_VPE3_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*13)
+#define BOOTTRC_CCIF0_OLD_VPE4_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*14)
+#define BOOTTRC_CCIF0_OLD_VPE5_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*15)
+#endif
+#if defined(__PROFILE_INIT__)
+#define PROFILE_INIT_ENTRY_COUNT 128
+#define PROFILE_INIT_VPE_SIZE (PROFILE_INIT_ENTRY_COUNT * 0x8)
+#endif
+
+#endif /* !_BOOT_COMM_H */
+
diff --git a/mcu/interface/driver/sys_drv/bootarm.h b/mcu/interface/driver/sys_drv/bootarm.h
new file mode 100644
index 0000000..ea12fbc
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/bootarm.h
@@ -0,0 +1,197 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* Filename:
+* ---------
+* bootarm.inc
+*
+* Project:
+* --------
+* Maui_Software
+*
+* Description:
+* ------------
+* This Module defines the platform dependent setting for boot sequence of asm level.
+*
+* Author:
+* -------
+ * -------
+*
+*============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+*
+ * removed!
+ * removed!
+ * removed!
+*
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+*
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *****************************************************************************/
+
+#ifndef __BOOTARM_H__
+#define __BOOTARM_H__
+
+
+#define PC_INITIALIZE_VAL 0xE59FF018
+#define DUMMY_END_VAL 0x454E4400
+
+
+/* Define init boot-up trace label before HS1 */
+#define INIT_MAGIC 0x30305F49 //I_00
+#define LABEL_POLLING_BUS_READY 0x0000
+#define LABEL_PREINIT_PDAMON 0x0001
+#define LABEL_PREINIT_BUSMON 0x0002
+#define LABEL_PREINIT_FRC 0x0003
+#define LABEL_START_INIT 0x0004
+#define LABEL_START_P1 0x0005
+#define LABEL_RESTART_WDT 0x0006
+#define LABEL_SAVE_RASP 0x0007
+#define LABEL_RESET_EXC_SP_ARRAY 0x0008
+#define LABEL_SET_C0_COFIG5_K 0x0009
+#define LABEL_CLR_C0_STATUS_BEV_ERL 0x000A
+#define LABEL_INTERRUPT_PREINIT 0x000B
+#define LABEL_CM_L2_INIT 0x000C
+#define LABEL_CM_INIT 0x000D
+#define LABEL_PLL_INIT 0x000E
+#define LABEL_L1_CACHE_INIT 0x000F
+#define LABEL_L2_CACHE_INIT 0x0010
+#define LABEL_SET_CM_WT 0x0011
+#define LABEL_INIT_OTHER_CORES 0x0012
+#define LABEL_SET_BOOTSLAVE 0x0013
+#define LABEL_JOIN_CH_DOMAIN 0x0014
+#define LABEL_ABN_RST_CHECK 0x0015
+#define LABEL_SETUP_CDMMBASE 0x0016
+#define LABEL_MPU_INIT 0x0017
+#define LABEL_START_P2 0x0018
+#define LABEL_REGION_INIT 0x0019
+#define LABEL_REGION_INIT_DONE 0x001A
+#define LABEL_INIT_GPR 0x001B
+#define LABEL_INIT_EX_STACK 0x001C
+#define LABEL_SET_C0_EBASE 0x001D
+#define LABEL_DISPATCH_SP 0x001E
+#define LABEL_STACK_INIT 0x001F
+#define LABEL_INIT_VPE1 0x0020
+#define LABEL_INIT_ASM_DONE 0x0021
+
+#define LABEL_CLIB_BASE_INIT 0x0101
+#define LABEL_DUMMY_REF 0x0102
+#define LABEL_WDT_VAR_INIT 0x0103
+#define LABEL_CCCI_HW_INIT 0x0104
+#define LABEL_CCCI_HS1 0x0105
+#define LABEL_EMM_INIT 0x0106
+
+#define LABEL_CCCI_START 0x0200
+#define LABEL_CCCI_LIMIT 0x02FF
+
+/*
+#define LABEL_APP_INIT 0x0100
+#define LABEL_PCM_START 0x0101
+#define LABEL_SYSSTACK_PROT 0x0102
+#define LABEL_CLIB_BASE_INIT 0x0103
+#define LABEL_WDT_VAR_INIT 0x0104
+#define LABEL_BOOT_MODE_POLLING 0x0105
+#define LABEL_SHARE_MEM_MPU 0x0106
+#define LABEL_EMM_INIT 0x0108
+*/
+#endif /* __BOOTARM_H__ */
diff --git a/mcu/interface/driver/sys_drv/cache_dpdl2.h b/mcu/interface/driver/sys_drv/cache_dpdl2.h
new file mode 100644
index 0000000..42df9cb
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/cache_dpdl2.h
@@ -0,0 +1,91 @@
+#ifndef _CACHE_DPDL2_H
+#define _CACHE_DPDL2_H
+
+#include "kal_general_types.h"
+#include "dl2cmgr.h"
+
+
+
+/*****************************************************************************
+ * Symbol/Type Definition *
+ *****************************************************************************/
+typedef enum {
+ SIZE_None = 0,
+ L2CACHE_Size_32KB, L2CACHE_Size_64KB, L2CACHE_Size_96KB, L2CACHE_Size_128KB, L2CACHE_Size_160KB,
+ L2CACHE_Size_192KB, L2CACHE_Size_224KB, L2CACHE_Size_256KB, L2CACHE_Size_288KB, L2CACHE_Size_320KB,
+ L2CACHE_Size_352KB, L2CACHE_Size_384KB, L2CACHE_Size_416KB, L2CACHE_Size_448KB, L2CACHE_Size_480KB,
+ L2CACHE_Size_512KB, L2CACHE_Size_544KB, L2CACHE_Size_576KB, L2CACHE_Size_608KB, L2CACHE_Size_640KB,
+ L2CACHE_Size_672KB, L2CACHE_Size_704KB, L2CACHE_Size_736KB, L2CACHE_Size_768KB, L2CACHE_Size_800KB,
+ L2CACHE_Size_832KB, L2CACHE_Size_864KB, L2CACHE_Size_896KB, L2CACHE_Size_928KB, L2CACHE_Size_960KB,
+ L2CACHE_Size_992KB, L2CACHE_Size_1024KB, L2CACHE_Size_1056KB, L2CACHE_Size_1088KB, L2CACHE_Size_1120KB,
+ L2CACHE_Size_1152KB, L2CACHE_Size_1184KB, L2CACHE_Size_1216KB, L2CACHE_Size_1248KB, L2CACHE_Size_1280KB,
+ L2CACHE_Size_1312KB, L2CACHE_Size_1344KB, L2CACHE_Size_1376KB, L2CACHE_Size_1408KB, L2CACHE_Size_1440KB,
+ L2CACHE_Size_1472KB, L2CACHE_Size_1504KB, L2CACHE_Size_1536KB, L2CACHE_Size_1568KB, L2CACHE_Size_1600KB,
+ L2CACHE_Size_1632KB, L2CACHE_Size_1664KB, L2CACHE_Size_1696KB, L2CACHE_Size_1728KB, L2CACHE_Size_1760KB,
+ L2CACHE_Size_1792KB, L2CACHE_Size_1824KB, L2CACHE_Size_1856KB, L2CACHE_Size_1888KB, L2CACHE_Size_1920KB,
+ L2CACHE_Size_1952KB, L2CACHE_Size_1984KB, L2CACHE_Size_2016KB, L2CACHE_Size_2048KB = 64,
+
+ L2CACHE_Size_Min = L2CACHE_Size_32KB,
+ L2CACHE_Size_Max = L2CACHE_Size_2048KB,
+} DPDL2_SIZE;
+
+typedef enum {
+ CASE_None = 0,
+
+ PDN_Fail = 0x10,
+ PDN_Case = 0x10,
+ PDN_1Way = 0x11,
+ PDN_2Way = 0x12,
+ PDN_3Way = 0x13,
+ PDN_4Way = 0x14,
+ PDN_5Way = 0x15,
+ PDN_6Way = 0x16,
+ PDN_7Way = 0x17,
+ PDN_8Way = 0x18,
+
+ PO_Fail = 0x20,
+ PO_Case = 0x20,
+ PO_1Way = 0x21,
+ PO_2Way = 0x22,
+ PO_3Way = 0x23,
+ PO_4Way = 0x24,
+ PO_5Way = 0x25,
+ PO_6Way = 0x26,
+ PO_7Way = 0x27,
+ PO_8Way = 0x28,
+
+ PDN_Aborted_Case = 0x30,
+ PDN_Aborted_PO_1Way = 0x31,
+ PDN_Aborted_PO_2Way = 0x32,
+ PDN_Aborted_PO_3Way = 0x33,
+ PDN_Aborted_PO_4Way = 0x34,
+ PDN_Aborted_PO_5Way = 0x35,
+ PDN_Aborted_PO_6Way = 0x36,
+ PDN_Aborted_PO_7Way = 0x37,
+ PDN_Aborted_PO_8Way = 0x38,
+
+
+ CASE_Mask = 0xF0,
+ CASE_Fail = 0xFF,
+} DPDL2_RETURN_CASE;
+
+typedef enum {
+ STATUS_None = 0,
+ PDN_Processing = 1,
+ PDN_Done = 2,
+ PO_Processing = 3,
+ PO_Done = 4,
+} DPDL2_STATUS;
+
+
+/*******************************************************************************
+ * function prototypes
+ *******************************************************************************/
+
+extern DPDL2_RETURN_CASE dpdl2_change_l2cache_size(DPDL2_SIZE l2cache_size);
+extern DPDL2_STATUS dpdl2_query_status(void);
+extern DPDL2_SIZE dpdl2_query_po_l2cache_size(void);
+extern kal_uint32 lock_l2cache_excludeway(kal_uint32 addr, kal_uint32 len, dl2cm_section_id lock_section);
+extern void dpdl2_polling_status_done(void);
+
+#endif /* _CACHE_DPDL2_H */
diff --git a/mcu/interface/driver/sys_drv/cache_hw.h b/mcu/interface/driver/sys_drv/cache_hw.h
new file mode 100644
index 0000000..fb9f264
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/cache_hw.h
@@ -0,0 +1,125 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cache_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the functionality of L1 and L2 cache.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _CACHE_HW_H
+#define _CACHE_HW_H
+
+#endif /* _CACHE_HW_H */
diff --git a/mcu/interface/driver/sys_drv/cache_sw.h b/mcu/interface/driver/sys_drv/cache_sw.h
new file mode 100644
index 0000000..bce9224
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/cache_sw.h
@@ -0,0 +1,587 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cache_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the functionality of code and data cache.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _CACHE_SW_H
+#define _CACHE_SW_H
+
+#include "kal_general_types.h"
+
+
+#define L2_Only_Sync() do {\
+ register kal_uint32 __tmp__;\
+ __asm__ volatile (\
+ "li %0, 0x1\n"\
+ "sw %0, 0(%1)\n"\
+ :"=&r"(__tmp__)\
+ :"r"(l2_sync_base):\
+ );\
+ } while (0)
+
+/*******************************************************************************
+ * constants & macros
+ *******************************************************************************/
+
+/* cacheable and non-cacheable */
+#if defined(__DYNAMIC_SWITCH_CACHEABILITY__)
+enum
+{
+ DYNAMIC_SWITCH_CACHEABILITY_NON_CACHEABLE = 0x0,
+ DYNAMIC_SWITCH_CACHEABILITY_CACHEABLE = 0x1
+};
+#endif
+
+#define CPU_CACHE_LINE_SIZE 32
+#define CPU_L2CACHE_LINE_SIZE 64
+#define CPU_CACHE_LINE_BIT_OFFSET 5
+#define CPU_CACHE_LINE_SIZE_MASK 0x0000001F
+#define L2CACHE_LINE_SIZE_MASK 0x0000003F
+
+#define CPU_CACHE_LINE_ALIGN_ADDR(_addr) \
+ ((_addr) & ~CPU_CACHE_LINE_SIZE_MASK)
+#define CPU_CACHE_LINE_ALIGN_LEN(_addr, _len) \
+ ((CPU_CACHE_LINE_ALIGN_ADDR((_addr) + (_len) -1) - CPU_CACHE_LINE_ALIGN_ADDR((_addr))) + CPU_CACHE_LINE_SIZE)
+
+#define IS_CACHE_LINE_SIZE_ALIGNED(value) ((value&CPU_CACHE_LINE_SIZE_MASK)==0? 1: 0)
+
+#define L2CACHE_LINE_ALIGN_ADDR(_addr) \
+ ((_addr) & ~L2CACHE_LINE_SIZE_MASK)
+#define L2CACHE_LINE_ALIGN_LEN(_addr, _len) \
+ ((L2CACHE_LINE_ALIGN_ADDR((_addr) + (_len) -1) - L2CACHE_LINE_ALIGN_ADDR((_addr))) + CPU_L2CACHE_LINE_SIZE)
+
+#define IS_L2CACHE_LINE_SIZE_ALIGNED(value) ((value&L2CACHE_LINE_SIZE_MASK)==0? 1: 0)
+
+/*******************************************************************************
+ * function prototypes
+ *******************************************************************************/
+
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__) || defined(__MTK_MMU__) || defined(__CR4__) || defined(__MIPS_IA__) || defined(__MIPS_I7200__)
+
+kal_uint32 is_predef_dyna_c_region(kal_uint32 vaddr, kal_uint32 len);
+kal_uint32 dynamic_switch_cacheable_region(void *vaddr, kal_uint32 len, kal_uint32 cacheable);
+kal_uint32 dynamic_switch_cacheable_region_nonblocking(void *vaddr, kal_uint32 len, kal_uint32 cacheable);
+
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ || __MTK_MMU__ || __CR4__ || __MIPS_IA__ || __MIPS_I7200__*/
+
+kal_int32 query_is_dram(kal_uint32 addr, kal_uint32 len);
+#define INT_QueryIsDRAM(addr, len) \
+ query_is_dram((kal_uint32)addr, (kal_uint32)len)
+
+kal_int32 query_is_noncached_ram(kal_uint32 addr, kal_uint32 len);
+#define INT_QueryIsNonCachedRAM(addr, len) \
+ query_is_noncached_ram((kal_uint32)addr, (kal_uint32)len)
+
+kal_int32 query_is_cached_ram(kal_uint32 addr, kal_uint32 len);
+#define INT_QueryIsCachedRAM(addr, len) \
+ query_is_cached_ram((kal_uint32)addr, (kal_uint32)len)
+
+#if defined(__DYNAMIC_SWITCH_CACHEABILITY__) || defined(__WRITE_THROUGH_CACHEABLE__)
+kal_int32 invalidate_dcache(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16;
+kal_int32 invalidate_dcache_L2WB(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16;
+// kal_int32 invalidate_icache(kal_uint32 addr, kal_uint32 len); // Not released to user due to HRT concern about L2$ lock.
+kal_int32 invalidate_dcache_nonblocking(kal_uint32 addr, kal_uint32 len);
+// kal_int32 invalidate_icache_nonblocking(kal_uint32 addr, kal_uint32 len); // Not released to user due to HRT concern about L2$ lock.
+
+#endif /* __DYNAMIC_SWITCH_CACHEABILITY__ || __WRITE_THROUGH_CACHEABLE__ */
+
+#if defined(__DYNAMIC_SWITCH_CACHEABILITY__)
+ /*******************************************************************************
+ * <GROUP Functions>
+ *
+ * FUNCTION
+ * clean_dcache
+ * DESCRIPTION
+ * This function is used to clean cache
+ * PARAMETERS
+ * addr: [IN] the start address. it must be cache line size aligned (usually 32byte)
+ * len: [IN] the length. it must be the multiple of cache line size
+ * RETURNS
+ * always return 0
+ ******************************************************************************/
+kal_int32 clean_dcache(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16;
+kal_int32 clean_dcache_L2WB(kal_uint32 addr, kal_uint32 len);
+kal_int32 clean_dcache_nonblocking(kal_uint32 addr, kal_uint32 len);
+ /*******************************************************************************
+ * <GROUP Functions>
+ *
+ * FUNCTION
+ * clean_and_invalidate_dcache
+ * DESCRIPTION
+ * This function is used to clean and invalidate cache.
+ * PARAMETERS
+ * addr: [IN] the start address. it must be cache line size aligned (usually 32byte)
+ * len: [IN] the length. it must be the multiple of cache line size
+ * RETURNS
+ * always return 0
+ ******************************************************************************/
+kal_int32 clean_and_invalidate_dcache(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16;
+kal_int32 clean_and_invalidate_dcache_L2WB(kal_uint32 addr, kal_uint32 len);
+kal_int32 clean_and_invalidate_dcache_nonblocking(kal_uint32 addr, kal_uint32 len);
+#ifdef __DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__
+kal_int32 clean_and_invalidate_dcache_unlockL2(kal_uint32 addr, kal_uint32 len) DECLARE_MIPS16;
+#endif
+kal_uint32 virt_to_phys(void * address);
+kal_uint32 phys_to_virt(void * address);
+kal_uint32 remap_to_physRam(void * address);
+#endif /* __DYNAMIC_SWITCH_CACHEABILITY__ */
+
+kal_int32 lock_l2cache(kal_uint32 addr, kal_uint32 len);
+kal_int32 invalidate_l2cache(kal_uint32 addr, kal_uint32 len);
+#ifdef __DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__
+kal_int32 invalidate_l2cache_unlockL2(kal_uint32 addr, kal_uint32 len);
+#endif
+#endif /* _CACHE_SW_H */
diff --git a/mcu/interface/driver/sys_drv/cdif_public.h b/mcu/interface/driver/sys_drv/cdif_public.h
new file mode 100644
index 0000000..c372668
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/cdif_public.h
@@ -0,0 +1,65 @@
+#ifndef __CDIF_PUBLIC_H__
+#define __CDIF_PUBLIC_H__
+
+/*****************************************************************************
+ * Value Definition *
+ *****************************************************************************/
+typedef enum {
+ CDIF_CONTROL_CHANNEL_MASTER_TX = 0,
+ CDIF_CONTROL_CHANNEL_MASTER_RX,
+ CDIF_IPC_MASTER_TX,
+ CDIF_IPC_MASTER_RX,
+ CDIF_EVG_MASTER_TX,
+ CDIF_EVG_MASTER_RX,
+ CDIF_MUTEX_MASTER_TX,
+ CDIF_MUTEX_MASTER_RX,
+ CDIF_EXCEP_MASTER_TX,
+ CDIF_EXCEP_MASTER_RX,
+#if defined(CDIF_IT)
+ CDIF_CCIF_IT_MASTER_TX,
+ CDIF_CCIF_IT_MASTER_RX,
+#endif
+ CDIF_MAX_CHANNEL,
+} CDIF_CHANNEL_T;
+
+typedef enum {
+ CDIF_SUCCESS = 0,
+ CDIF_NO_PHY_CHANNEL = -1001,
+ CDIF_INVALID_PARAM = -1002,
+ CDIF_IN_USE = -1003,
+ CDIF_IN_LISR = -1004,
+ CDIF_NOT_OWNER = -1005,
+} CDIF_RET_VALUE_T;
+
+
+/*****************************************************************************
+ * Data Type Definition *
+ *****************************************************************************/
+typedef struct {
+ kal_uint32 data[2];
+ kal_uint32 channel;
+ kal_uint32 reserved;
+} CDIF_BUFF_T;
+
+typedef void (*CDIF_CALLBACK)(CDIF_BUFF_T *buff);
+
+typedef struct {
+ kal_uint32 state;
+ kal_uint32 owner;
+ CDIF_CALLBACK funp;
+} CDIF_CTRL_T;
+
+
+/*****************************************************************************
+ * public API *
+ *****************************************************************************/
+extern void cdif_init();
+extern void cdif_init_handshake();
+extern kal_int32 cdif_channel_init(kal_uint32 channel, CDIF_CALLBACK funp);
+extern kal_int32 cdif_channel_deinit(kal_uint32 channel);
+extern kal_int32 cdif_mailbox_write(kal_uint32 channel, kal_uint32 message_id, kal_uint32 reseerved);
+extern kal_int32 cdif_mailbox_write_with_polling(kal_uint32 channel, kal_uint32 message_id, kal_uint32 reserved);
+extern kal_uint32 cdif_chk_recentry_in_queue(kal_uint32 query_channel, kal_bool ack_if_found);
+extern kal_uint32 cdif_init_ready();
+
+#endif /* __U3G_CCCI_H__ */
diff --git a/mcu/interface/driver/sys_drv/cp15.h b/mcu/interface/driver/sys_drv/cp15.h
new file mode 100644
index 0000000..4a3b44d
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/cp15.h
@@ -0,0 +1,359 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cp15.h
+ *
+ * Project:
+ * --------
+ * MAUI
+ *
+ * Description:
+ * ------------
+ * Header file for coprocessor(CP15) control.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
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+ *
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+ * removed!
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+ *
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#if 0
+#ifndef __CP15_H__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM11_MMU__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM11_MMU__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM11_MMU__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM11_MMU__ */
+/* under construction !*/
+#elif defined (__CR4__) /* __ARM9_MMU__ || __ARM11_MMU__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* __CR4__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+/* under construction !*/
+#endif /* __CP15_H__ */
+/* under construction !*/
+#endif
diff --git a/mcu/interface/driver/sys_drv/init.h b/mcu/interface/driver/sys_drv/init.h
new file mode 100644
index 0000000..6b645fd
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/init.h
@@ -0,0 +1,920 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+[MAUI_03121063] remove PDN registers
+[MAUI_03147344] Dummy read for early response HW
+[MAUI_03161918] remove custom_setAdvEMI from bootarm.S
+[MAUI_03157059] security use meta to write
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+ *
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+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INIT_H
+#define _INIT_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+//MSBB remove #include "kal_non_specific_general_types.h"
+#include "init_comm.h"
+#endif /* !_INIT_H */
+
diff --git a/mcu/interface/driver/sys_drv/init_comm.h b/mcu/interface/driver/sys_drv/init_comm.h
new file mode 100644
index 0000000..5c443ae
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/init_comm.h
@@ -0,0 +1,1403 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+[MAUI_03149504] ([MAUI_03180970]) all time memory dump
+[MAUI_03121063] remove PDN registers
+[MAUI_03147344] Dummy read for early response HW
+[MAUI_03161918] remove custom_setAdvEMI from bootarm.S
+[MAUI_03157059] security use meta to write
+
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INIT_COMM_H
+#define _INIT_COMM_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+//MSBB remove #include "kal_non_specific_general_types.h"
+#include "kal_trace.h"
+#include "init_public.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+
+/*******************************************************************************
+ * Boot slave register base
+ *******************************************************************************/
+
+#if defined(__MD97__)||defined(__MD97P__)
+ #if defined(MT6297_IA)
+ #define MCU_BOOTSLV_CTRL_BASE (BASE_MADDR_MDPERIMISC + 0x1204)
+ #else
+ #define MCU_BOOTSLV_CTRL_BASE (BASE_MADDR_MDPERIMISC + 0x1104)
+ #endif
+#else
+#define MCU_BOOTSLV_CTRL_BASE (BASE_MADDR_MDPERIMISC + 0x104)
+#endif
+
+#define MCU_BOOTSLV_CTRL_CORE(index) (MCU_BOOTSLV_CTRL_BASE + (index) * 0xC)
+#define MCU_BOOTSLV_JUMP_ADDR(index) (MCU_BOOTSLV_CTRL_CORE(index) + 0x0)
+#define MCU_BOOTSLV_JUMP_ADDR_UPDATE(index) (MCU_BOOTSLV_CTRL_CORE(index) + 0x4)
+#define MCU_BOOTSLV_JUMP_ADDR_UNLOCK(index) (MCU_BOOTSLV_CTRL_CORE(index) + 0x8)
+#define MCU_BOOTSLV_AP_TRIG (BASE_MADDR_MDCFGCTL + 0x24)
+#define MCU_BOOTSLV_JUMP_KEY_VALUE (0x5500)
+
+/*************************************************************************
+ * Define data structure
+ *************************************************************************/
+
+typedef struct
+{
+ kal_uint16 pdn_con0;
+ kal_uint16 pdn_con1;
+ kal_uint16 pdn_con2;
+ kal_uint16 pdn_con3;
+} CONFIG_PDN_TYPE;
+
+
+typedef enum
+{
+
+ UNKNOWN,
+
+ ECO_END = 0x7FFFFFFF
+} ECO_VERSION;
+
+
+typedef enum
+{
+ CHIP_UNKNOWN
+} CHIP_NAME;
+
+
+typedef enum
+{
+ GP_UNKNOWN
+} CHIP_GROUP;
+
+typedef enum
+{
+ B63216A,
+ C63216A,
+ C63216B,
+ UNKNOWN_ANALOG_DIE
+} analog_die_id; /* analog die identification */
+
+typedef enum
+{
+ SYS_CMD_NONE,
+ SYS_CMD_SET_BL_DL,
+ SYS_CMD_SET_BROM_DL,
+ SYS_CMD_CLR_DL_FLAG,
+ CHK_USB_META_WO_BAT,
+ CHK_FAST_META,
+ SYS_CMD_BL_LOGO_DISPLAYED,
+ SYS_CMD_GET_PWN_STA,
+ SYS_CMD_GET_EMI_PARAM,
+ SYS_CMD_BL_BROM_CMD_MODE_DISABLED
+} INIT_SYSCMD_CODE;
+
+
+typedef enum mem_dev_enum_t
+{
+ DRAM = 0xA0,
+ NOR_ASYNC = 0xB0,
+ NOR_ASYNC_PAGE = 0xB1,
+ NOR_SYNC_READ_ASYNC_WRITE = 0xB2,
+ NOR_SYNC_READ_SYNC_WRITE = 0xB3,
+ RAM_ASYNC = 0xC0,
+ RAM_ASYNC_PAGE = 0xC1,
+ RAM_SYNC_READ_ASYNC_WRITE = 0xC2,
+ RAM_SYNC_READ_SYNC_WRITE = 0xC3
+} MEM_DEV_TYPE;
+
+typedef enum
+{
+ BL_INFO_FROM_RTC
+} BL_FIRST_PWON_INFO_SRC;
+
+typedef struct EMI_CS_STRUCT
+{
+ kal_uint8 CS0;
+ kal_uint8 CS1;
+ kal_uint8 CS2;
+ kal_uint8 CS3;
+} EMI_CS;
+
+typedef struct EXTSRAM_REGION_INFO_STRCUT
+{
+ kal_uint32 addr;
+ kal_uint32 len;
+} EXTSRAM_REGION_INFO_T;
+
+typedef enum
+{
+ E_BROM,
+ E_BLNUSB,
+ E_BLSUSB,
+ E_ERROR_MODE
+} MODE_ENTRY_SRC;
+
+#if defined(MT6763) || defined(MT6739) || defined(MT6771) || defined(MT6765) || defined(MT6295M) || defined(MT3967) || defined(MT6779) || defined(MT6785)|| defined(MT6297) || defined(MT6885)|| defined(MERCURY) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+// Check these macro define is the same as MT6763 FPGA?
+#define DATE_CODE_BASE 0xA0000018
+#if defined(__MD97__)||defined(__MD97P__)
+ #define PURPOSE_CODE_BASE 0xA0000018
+#else
+ #define PURPOSE_CODE_BASE 0xA000001C
+#endif
+#define PURPOSE_CODE_BIT (24)
+#define PURPOSE_CODE_MASK 0x0F000000
+#define CORENUM_BIT (16)
+#define CORENUM_MASK 0x000F0000
+#endif
+#if defined(__MD97__)||defined(__MD97P__)
+typedef enum
+{
+ PURPOSE_NotSupport,
+ FPGA_H1,
+ FPGA_H2,
+ FPGA_H3,
+ FPGA_H4,
+ FPGA_H5,
+ FPGA_H6,
+ FPGA_Platform = 0xFF,
+ FPGA_LTEL2= 0xFF,
+ FPGA_SIB= 0xFF,
+ FPGA_U4G= 0xFF,
+ FPGA_U4G_LTEL2= 0xFF,
+ FPGA_BIT_PURPOSE_END = 0xFFFFFFFF
+} HW_PURPOSE;
+#else
+typedef enum
+{
+ PURPOSE_NotSupport,
+ FPGA_Platform,
+ FPGA_LTEL2,
+ FPGA_SIB,
+ FPGA_U4G,
+ FPGA_U4G_LTEL2,
+ FPGA_BIT_PURPOSE_END = 0xFFFFFFFF
+} HW_PURPOSE;
+#endif
+typedef enum
+{
+ CORENUM_NotSupport,
+ CORENUM_1,
+ CORENUM_2,
+ CORENUM_3,
+ CORENUM_4,
+ FPGA_BIT_CORENUM_END = 0xFFFFFFFF
+} HW_CORENUM;
+
+extern kal_uint32 INT_FPGA_DATECODE(void);
+/*Only FPGA Support this function*/
+#if defined (__FPGA__)
+extern HW_PURPOSE INT_FPGA_PURPOSE(void);
+#endif
+extern HW_CORENUM INT_FPGA_CORENUM(void);
+extern kal_bool INT_FPGA_IS_ASIC(void);
+
+typedef enum
+{
+ E_Before_20140801,
+ E_20140801,
+ E_20140802,
+ E_20140808,
+ E_20140819,
+ E_20140822,
+ E_20140824,
+ E_20140825,
+ E_20140826,
+ E_20140827,
+ E_20140828,
+ E_20140830,
+ E_20140901,
+ E_20140902,
+ E_20140903,
+ E_20140904,
+ E_20140905,
+ E_20140908,
+ E_FPGA_BIT_DATE_END = 0xFFFFFFFF
+} FPGA_BIT_DATE;
+typedef enum
+{
+ E_Platform,
+ E_3G,
+ E_4G,
+ E_FPGA_BIT_PURPOSE_END = 0xFFFFFFFF
+} FPGA_BIT_PURPOSE;
+typedef struct
+{
+ FPGA_BIT_DATE date;
+ FPGA_BIT_PURPOSE purpose;
+} FPGA_VERSION;
+extern FPGA_VERSION INT_FPGA_Version(void);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+ * Define system internal RAM pool size
+ *************************************************************************/
+
+#ifdef __SYS_INTERN_RAM__
+
+#define KAL_TIMER_STACK_SIZE 512
+
+#if defined(IC_BURNIN_TEST)
+#define GLOBAL_INT_SRAM_STACK_MEM_SIZE (2048)
+#endif
+
+#endif /* __SYS_INTERN_RAM__ */
+
+
+/*************************************************************************
+ * Define import function prototype
+ *************************************************************************/
+/* Category 0: Initialize related */
+extern void Initialize(void);
+/* Category 1: chip information */
+extern ECO_VERSION INT_ecoVersion(void);
+extern CHIP_GROUP INT_ChipGroup(void);
+extern analog_die_id AnalogDieID(void);
+extern CHIP_NAME INT_ChipName(void);
+void INT_Init_Misc(void);
+
+/* Category 2: Query or Set system information */
+extern kal_bool INT_IsBootForUSBAT(void);
+extern void INT_SetCmdToSys(INIT_SYSCMD_CODE cmd_val);
+extern kal_uint32 INT_GetSysStaByCmd(INIT_SYSCMD_CODE cmd_val, void *data_p);
+extern void INT_Set_BootSlave(kal_uint32 core_index, kal_uint32 jmp_addr);
+
+
+#ifdef __MTK_TARGET__
+extern kal_bool INT_GetAvailableMemory_Ptr(kal_uint32 **, kal_uint32 *);
+extern kal_bool INT_QueryBiggestPool(kal_uint32 *, void **);
+#endif
+
+extern kal_uint32 INT_RetrieveFlashBaseAddr(void);
+extern kal_bool INT_CheckSystemDriveOnNAND(void);
+extern void init_32khz_output(kal_uint16 gpio_pin, kal_uint16 gpio_data);
+extern kal_int32 enable_32khz_output(void);
+extern kal_int32 disable_32khz_output(void);
+extern kal_bool INT_RetrieveDSPTXRXBaseAddr(kal_uint32 *TX_Base, kal_uint32 *RX_Base, kal_uint32 *CS, kal_uint32 *TX_Size, kal_uint32 *RX_Size);
+extern kal_int32 INT_QuerySystemRAMInfo(kal_uint32 *addr, kal_uint32 *len);
+extern void wait_32k_start(void);
+
+#if defined(__MTK_TARGET__)
+extern kal_int32 show_sysinit_msg(void);
+#else /* __MTK_TARGET__ */
+#define show_sysinit_msg()
+#endif /* __MTK_TARGET__ */
+
+#if defined(__RTL_SIMULATION_FOR_60QBIT__)
+extern kal_int32 profile_INT_SwitchStackToRun_before(void);
+extern kal_int32 profile_INT_SwitchStackToRun_after(void);
+#endif /* __RTL_SIMULATION_FOR_60QBIT__ */
+
+
+/*************************************************************************
+ * Define customized function prototype
+ *************************************************************************/
+
+extern kal_int8 custom_setEMI(void);
+extern EMI_CS * custom_getCS(void);
+extern void custom_get_EXTSRAM_size(kal_uint32 *);
+extern kal_uint32 custom_get_demp_image_table(void);
+extern kal_int32 custom_config_demp_page(kal_uint32 **list, kal_uint32 **pool, kal_uint32 *pool_size);
+extern MODE_ENTRY_SRC INT_GetMetaModeSrc(void);
+
+
+/*************************************************************************
+ * Define region attribute
+ *************************************************************************/
+#if defined(__MTK_TARGET__)
+#include "sys/cdefs.h"
+#undef __section
+#define __section(S) __attribute__ ((section(#S)))
+
+#define __attr_cached_ext_zi __section(CACHED_EXTSRAM_PREINIT_ZI)
+#define __attr_emiinit_zi __section(EMIINITZI)
+#define __attr_emiinit_code __section(EMIINITCODE)
+#define __attr_lead_part __section(INTSRAM_RODATA)
+
+#else
+
+#define __attr_cached_ext_zi
+#define __attr_emiinit_zi
+#define __attr_emiinit_code
+#define __attr_lead_part
+
+#endif /* __MTK_TARGET__ */
+
+#endif /* !_INIT_H */
+
diff --git a/mcu/interface/driver/sys_drv/init_trc_api.h b/mcu/interface/driver/sys_drv/init_trc_api.h
new file mode 100644
index 0000000..479d604
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/init_trc_api.h
@@ -0,0 +1,480 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_trc_api.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
+ * removed!
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+ * removed!
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+ *
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/************************************************************
+ * NOTE: prefix of trace id:
+ * TSID_: can be found in mcu\service\sys_svc\profile\inc\maui_time_stamp_id.h
+ * SST_: can be found in mcu\driver\sys_drv\init\inc\system_trc.h
+ * BOOT_: can be found in mcu\driver\sys_drv\init\inc\init_trc_id.h
+ ************************************************************/
+
+#ifndef _INIT_TRC_API_H
+#define _INIT_TRC_API_H
+
+#include "kal_public_defs.h" // MSBB change #include "stack_config.h"
+#include "kal_trace.h"
+//#include "mcu_pmu_montr.h"
+#include "cpu.h"
+#include "cpu_info.h"
+#include "ex_mem_manager_public.h" // for EMM_WriteBootupTrace
+#include "init_trc_id.h"
+#if defined(__SP_BOOTTRC_ENABLE__)
+#include "ccci.h"
+#endif
+#include "mdm_trc.h"
+#include "us_timer.h"
+
+extern void INT_backupBootLogs(void);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+// These could be removed, but kal_task_lifecycle.c should update
+#define TASK_MAGIC
+#define TASK_MAGIC1
+#define TASK_MAGIC2
+#endif
+#define FATAL_ERROR_MAGIC 0x4C544146 //ASCII code FATL
+#define ASSERT_ERROR_MAGIC 0x54525341 //ASCII code ASRT
+#define VPE_HEADER_MAGIC 0xFF000000 //VPE number
+#define EXCEPTION_ERROR_MAGIC 0x50435845 //ASCII code EXCP
+
+typedef struct
+{
+ kal_uint32 HS1_boot_trace;
+ kal_uint32 HS1_boot_trace_time;
+ kal_uint32 HS2_boot_trace;
+ kal_uint32 HS2_boot_trace_time;
+} BOOTTRACE_FINAL_STEP_STRUCT;
+
+#if defined(__PROFILE_INIT__)
+typedef struct
+{
+ kal_uint32 boot_trc;
+ kal_uint32 boot_trc_time;
+} BOOTTRC_ENTRY_STRUCT;
+
+typedef struct
+{
+ BOOTTRC_ENTRY_STRUCT INT_bootup_trc_record[PROFILE_INIT_ENTRY_COUNT];
+} BOOTUP_TRC_STRUCT;
+#endif
+
+typedef enum
+{
+ E_DEFAULT = 0,
+ E_ASM_DONE = 0xA5A55A5a,
+} INIT_STAGE;
+
+extern INIT_STAGE INT_QueryInitStage(void);
+extern kal_bool INT_hasEMMAddress(void);
+
+
+extern const kal_uint32 g_EMM_BOOTTRC_MAGIC_ADDR;
+extern const kal_uint32 g_EMM_BOOTTRC_VPE0_ADDR;
+extern const kal_uint32 g_EMM_BOOTTRC_VPE1_ADDR;
+extern const kal_uint32 g_EMM_BOOTTRC_VPE2_ADDR;
+extern const kal_uint32 g_EMM_BOOTTRC_VPE3_ADDR;
+extern BOOTTRACE_FINAL_STEP_STRUCT INC_Init_Step[SYS_MCU_NUM_VPE];
+
+extern kal_uint32 INT_bootup_entry;
+#if defined(__MD97__)||defined(__MD97P__)
+extern kal_uint32 INC_TRC_PROFILE(kal_uint32 traceData, kal_uint32 traceTime);
+#else
+extern kal_uint32 INC_TRC_PROFILE;
+#endif
+#if !defined(__COSIM_BYPASS_DRV__)
+
+#if defined(__ESL_DBG_UTIL__)
+
+#include "esl_debug.h"
+#define INT_TRC_C(index)
+#define INT_Trace_Enter(trc_id) esl_printf(ESL_SIM_TIME_FLAG|ESL_WALL_TIME_FLAG, "%s:%d\n", __FILE__, __LINE__);
+#define INT_Trace_Exit(trc_id) esl_printf(ESL_SIM_TIME_FLAG|ESL_WALL_TIME_FLAG, "%s:%d\n", __FILE__, __LINE__);
+
+#else
+
+#if !defined(__PROFILE_INIT__)
+#define INT_TRC_C(index) \
+ do { \
+ kal_uint32 glb_vpe_idx = kal_get_current_vpe_id(); \
+ kal_uint32 glb_cur_time = ust_get_current_time(); \
+ ((void(*)(kal_uint32, kal_uint32))INT_bootup_entry)(index, glb_cur_time); \
+ INC_Init_Step[glb_vpe_idx].HS1_boot_trace = index; \
+ INC_Init_Step[glb_vpe_idx].HS1_boot_trace_time = glb_cur_time; \
+ } while (0)
+#else
+#define INT_TRC_C(index) \
+ do { \
+ kal_uint32 glb_vpe_idx = kal_get_current_vpe_id(); \
+ kal_uint32 glb_cur_time = ust_get_current_time(); \
+ ((void(*)(kal_uint32, kal_uint32))INT_bootup_entry)(index, glb_cur_time); \
+ ((void(*)(kal_uint32, kal_uint32))&INC_TRC_PROFILE)(index, glb_cur_time); \
+ INC_Init_Step[glb_vpe_idx].HS1_boot_trace = index; \
+ INC_Init_Step[glb_vpe_idx].HS1_boot_trace_time = glb_cur_time; \
+ } while (0)
+#endif
+/*
+ * Macro: INT_Trace_Enter(trc_id)
+ * trc_id: trace id, for TSID and SST
+ */
+#define INT_Trace_Enter(trc_id) \
+ do { \
+ EMM_BOOT_TS(trc_id); \
+ } while(0)
+/*
+ * Macro: INT_Trace_Exit(trc_id, is_ts, is_tst_duration)
+ * trc_id: trace id, for TSID and SST
+ * is_ts: if TS_BEGIN and TS_END invoked
+ * is_tst_duration: record duration or not
+ */
+#define INT_Trace_Exit(trc_id)
+
+#endif /* defined(__ESL_DBG_UTIL__) */
+
+#else
+
+/* For RTL Cosim, output trace log by MDM */
+#define INT_TRC_C(index)
+#define INT_Trace_Enter(trc_id) \
+ do { \
+ MDM_INT32_WRITE(MDM_APP_INIT_MAGIC+BOOT_##trc_id); \
+ } while (0)
+
+#define INT_Trace_Exit(trc_id)
+
+#endif /* !defined(__COSIM_BYPASS_DRV__) */
+
+
+/*************************************************************************
+ * Log bootup trace through EMM to AP CCCI share memory
+ *************************************************************************/
+#if !defined(__COSIM_BYPASS_DRV__)
+
+#if !defined(__PROFILE_INIT__)
+#define EMM_BOOT_TS(trc_id) \
+ do { \
+ kal_uint32 glb_vpe_idx = kal_get_current_vpe_id(); \
+ kal_uint32 core_idx = kal_get_current_core_id(); \
+ kal_uint32 frc_counts = 0; \
+ frc_counts = ust_get_current_time(); \
+ EMM_WriteBootupTrace(core_idx, (kal_uint32)BOOT_##trc_id, frc_counts); \
+ INC_Init_Step[glb_vpe_idx].HS2_boot_trace = (kal_uint32) (BOOT_##trc_id); \
+ INC_Init_Step[glb_vpe_idx].HS2_boot_trace_time = frc_counts; \
+ } while (0)
+#else
+#define EMM_BOOT_TS(trc_id) \
+ do { \
+ kal_uint32 glb_vpe_idx = kal_get_current_vpe_id(); \
+ kal_uint32 core_idx = kal_get_current_core_id(); \
+ kal_uint32 frc_counts = 0; \
+ frc_counts = ust_get_current_time(); \
+ EMM_WriteBootupTrace(core_idx, (kal_uint32)BOOT_##trc_id, frc_counts); \
+ ((void(*)(kal_uint32, kal_uint32))&INC_TRC_PROFILE)(0x10000000 | ((kal_uint32)BOOT_##trc_id), frc_counts); \
+ INC_Init_Step[glb_vpe_idx].HS2_boot_trace = (kal_uint32) (BOOT_##trc_id); \
+ INC_Init_Step[glb_vpe_idx].HS2_boot_trace_time = frc_counts; \
+ } while (0)
+#endif
+#define TASK_Trace(task_index) \
+ do { \
+ kal_uint32 glb_vpe_idx = kal_get_current_vpe_id(); \
+ kal_uint32 core_idx = kal_get_current_core_id(); \
+ kal_uint32 frc_counts = 0; \
+ frc_counts = ust_get_current_time(); \
+ EMM_WriteBootupTrace(core_idx, (kal_uint32)task_index, frc_counts); \
+ INC_Init_Step[glb_vpe_idx].HS2_boot_trace = (kal_uint32)(task_index); \
+ INC_Init_Step[glb_vpe_idx].HS2_boot_trace_time = frc_counts; \
+ } while (0)
+
+#else
+
+#define EMM_BOOT_TS(trc_id)
+#define TASK_Trace(task_index)
+
+#endif /* !defined(__COSIM_BYPASS_DRV__) */
+
+/*************************************************************************
+ * Bootup trace to Catcher
+ *************************************************************************/
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+
+/*
+ * NoteXXX:
+ * (1) Use print_trace(_with_info)() instead of print_bootup_trace(_with_info)()
+ * after TST task init
+ * (2) xxx_enter() and xxx_exit() should be used in a pair
+ * (3) xxx_enter() and xxx_exit() are invalid before TDMA timer is init
+ */
+
+#define print_bootup_trace(i) \
+ do { \
+ kal_bootup_trace(TRACE_INFO, i); \
+ } while (0)
+
+#define print_bootup_trace_enter(i) \
+ do { \
+ extern kal_uint32 init_duration; \
+ init_duration = drv_get_current_time(); \
+ kal_bootup_trace(TRACE_INFO, i##_ENTER); \
+ } while (0)
+
+#define print_bootup_trace_exit(i) \
+ do { \
+ extern kal_uint32 init_duration; \
+ init_duration = drv_get_duration_ms(init_duration); \
+ kal_bootup_trace(TRACE_INFO, i##_EXIT, init_duration); \
+ } while (0)
+
+#define print_trace(i) \
+ do { \
+ MD_TRC_##i(); \
+ } while (0)
+
+#define print_bootup_trace_with_info_enter(i, info) \
+ do { \
+ extern kal_uint32 init_duration; \
+ init_duration = drv_get_current_time(); \
+ kal_bootup_trace(TRACE_INFO, i##_ENTER, info); \
+ } while (0)
+
+#define print_bootup_trace_with_info_exit(i, info) \
+ do { \
+ extern kal_uint32 init_duration; \
+ init_duration = drv_get_duration_ms(init_duration); \
+ kal_bootup_trace(TRACE_INFO, i##_EXIT, info, init_duration); \
+ } while (0)
+
+#define print_trace_with_info_enter(i, info) \
+ do { \
+ extern kal_uint32 init_duration; \
+ init_duration = drv_get_current_time(); \
+ kal_trace(TRACE_INFO, i##_ENTER, info); \
+ } while (0)
+
+#define print_trace_with_info_exit(i, info) \
+ do { \
+ extern kal_uint32 init_duration; \
+ init_duration = drv_get_duration_ms(init_duration); \
+ kal_trace(TRACE_INFO, i##_EXIT, info, init_duration); \
+ } while (0)
+
+#define print_boot_mode(m) \
+ do { \
+ extern void INT_printBootMode(void); \
+ INT_printBootMode(); \
+ } while (0)
+
+#else /* __KAL_RECORD_BOOTUP_LOG__ || __KEYPAD_DEBUG_TRACE__ */
+
+#define print_bootup_trace(i)
+#define print_bootup_trace_enter(i)
+#define print_bootup_trace_exit(i)
+#define print_trace(i)
+#define print_bootup_trace_with_info_enter(i, info)
+#define print_bootup_trace_with_info_exit(i, info)
+#define print_trace_with_info_enter(i, info)
+#define print_trace_with_info_exit(i, info)
+#define print_boot_mode(m)
+
+#endif /* __KAL_RECORD_BOOTUP_LOG__ || __KEYPAD_DEBUG_TRACE__ */
+
+#endif /* _INIT_TRC_API_H */
+
diff --git a/mcu/interface/driver/sys_drv/init_trc_id.h b/mcu/interface/driver/sys_drv/init_trc_id.h
new file mode 100644
index 0000000..69f580c
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/init_trc_id.h
@@ -0,0 +1,178 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_trc_id.h
+ *
+ * Project:
+ * --------
+ * WR8
+ *
+ * Description:
+ * ------------
+ * Time stamp measurement id (MOLY Only)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+#ifndef __INIT_TRC_ID_H
+#define __INIT_TRC_ID_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//==============================================================================
+// TimeStamp Measurement ID
+//==============================================================================
+
+typedef enum
+{
+
+ /* init main flow */
+ BOOT_INIT_TOTAL = 0x0
+ ,BOOT_INIT_READY_TO_DISPLAY
+ ,BOOT_INIT_ASM
+ ,BOOT_INIT_APPINIT
+ ,BOOT_INIT_CLIB1
+ ,BOOT_INIT_CCCI
+ ,BOOT_INIT_CCCIHS1
+ ,BOOT_INIT_MDCIHS1
+ ,BOOT_INIT_BOOTMODE
+ ,BOOT_INIT_BOOTMODE_CHECK
+ ,BOOT_INIT_SYSTEMINIT
+ ,BOOT_INIT_NVRAM
+ ,BOOT_INIT_HWDINIT
+
+ /* HWDInitialization */
+ ,BOOT_INIT_CHIPREG = 0x100
+ ,BOOT_INIT_PDAMON
+ ,BOOT_INIT_INIT_MISC
+ ,BOOT_INIT_BUS
+ ,BOOT_INIT_ELM
+ ,BOOT_INIT_USC
+ ,BOOT_INIT_PMS
+ ,BOOT_INIT_RM
+ ,BOOT_INIT_OSTD
+ ,BOOT_INIT_GDMA
+ ,BOOT_INIT_L1SM
+ ,BOOT_INIT_UL1SM
+ ,BOOT_INIT_EL1SM
+ ,BOOT_INIT_HWDIVIDER
+ ,BOOT_INIT_PTP
+ ,BOOT_INIT_IDMALOAD
+ ,BOOT_INIT_NFIRESET
+ ,BOOT_INIT_DRV1
+ ,BOOT_INIT_DIGRF
+ ,BOOT_INIT_DVFS
+ ,BOOT_INIT_SIB
+ ,BOOT_INIT_MML1_TXSYS
+ ,BOOT_INIT_IA_MISC
+ ,BOOT_INIT_RMPU_MD_INIT
+ ,BOOT_INIT_BUSMON
+ ,BOOT_INIT_AMIF
+ ,BOOT_INIT_SFU_INIT
+ ,BOOT_INIT_SPU_INIT
+
+ /* Drv_Init_Phase1 */
+ ,BOOT_INIT_DRV1_PW = 0x200
+ ,BOOT_INIT_DRV1_TTY
+ ,BOOT_INIT_DRV1_DRVHISR
+ ,BOOT_INIT_DRV1_CCCI
+ ,BOOT_INIT_DRV1_OSTD_CCCI_CALLBACK
+ ,BOOT_INIT_DRV1_PCCIF4
+ ,BOOT_INIT_DRV1_PCCIF5
+ ,BOOT_INIT_DRV1_MHCCIF
+ ,BOOT_INIT_DRV1_PCIE
+ ,BOOT_INIT_DRV1_EMIMPU
+ ,BOOT_INIT_DRV1_PWM
+ ,BOOT_INIT_DRV1_CUSTOM
+ ,BOOT_INIT_DRV1_GPT3
+ ,BOOT_INIT_DRV1_GPTI
+ ,BOOT_INIT_DRV1_WDT
+ ,BOOT_INIT_DRV1_UART1
+ ,BOOT_INIT_DRV1_UART2
+ ,BOOT_INIT_DRV1_UART3
+
+ ,BOOT_INIT_PREFOTA
+ ,BOOT_INIT_THIRDROM
+ ,BOOT_INIT_LOADSECMAUI
+ ,BOOT_INIT_DEMP
+ ,BOOT_INIT_DISABLE_WDT
+ ,BOOT_INIT_DRV2
+
+ /* Drv_Init_Phase2 */
+ ,BOOT_INIT_DRV2_SIM = 0x300
+ ,BOOT_INIT_DRV2_EINTSWDBNC
+ ,BOOT_INIT_DRV2_CHE
+ ,BOOT_INIT_DRV2_ADC
+ ,BOOT_INIT_DRV2_SOE
+ ,BOOT_INIT_DRV2_PCIE2
+
+ ,BOOT_INIT_RESINIT
+ ,BOOT_INIT_GETRANDOMSEED_INTRAM /*systemInitializeResource*/
+ ,BOOT_INIT_GETRANDOMSEED_AP /*systemInitializeResource*/
+ ,BOOT_INIT_CLIB2
+ ,BOOT_INIT_SSF
+ ,BOOT_INIT_ECT
+ ,BOOT_INIT_DSPINIT
+ ,BOOT_INIT_TG_HISR_INIT
+ ,BOOT_INIT_MAINP
+ ,BOOT_INIT_SLA
+ ,BOOT_INIT_ENABLE_WDT
+ ,BOOT_INIT_HIFBOOT
+ ,BOOT_INIT_SLP_LPM_INIT
+ ,BOOT_INIT_CCCIHS2
+ ,BOOT_INIT_CCCIHS2_DONE
+
+ ,BOOT_NUM
+
+ ,BOOT_END = 0x400 // max 0x400 records
+ ,BOOT_NONE = BOOT_END
+
+
+} BOOT;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/mcu/interface/driver/sys_drv/mcu_pmu_montr_mips_ia_public.h b/mcu/interface/driver/sys_drv/mcu_pmu_montr_mips_ia_public.h
new file mode 100644
index 0000000..38046e8
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mcu_pmu_montr_mips_ia_public.h
@@ -0,0 +1,334 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2016
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mcu_pmu_montr_mips_ia_public.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * Header file general ARM core performance monitor API
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ ******************************************************************************/
+
+#ifndef MCU_PMU_MONTR_MIPS_IA_PUBLIC_H
+#ifdef __MTK_TARGET__
+#if defined(__MIPS_IA__)
+#define MCU_PMU_MONTR_MIPS_IA_PUBLIC_H
+
+#include "kal_public_api.h"
+#include "mips_ia_utils_public.h"
+
+#define IAPMU_READ_CNT_ERROR_VAL (0xffffffff)
+#define IAPMU_PERFCNT_U (MIU_PERFCNT_U)
+#define IAPMU_PERFCNT_S (MIU_PERFCNT_S)
+#define IAPMU_PERFCNT_K (MIU_PERFCNT_K)
+#define IAPMU_PERFCNT_EXL (MIU_PERFCNT_EXL)
+#define IAPMU_PERFCNT_ALL (IAPMU_PERFCNT_U | IAPMU_PERFCNT_S | IAPMU_PERFCNT_K | IAPMU_PERFCNT_EXL)
+#define PERFCNT_ALL (IAPMU_PERFCNT_ALL)
+
+/* Map IAPMU counter IDs to gereric PMU interface counter names.
+ * Using of specific IAPMU naming is preferred for code clarity.
+ *
+ * Please note that counters are per TC and counter ID refers to a
+ * specific counter on current TC. User must ensure that execution
+ * does not migrate to other TC/VPE between counter is started and
+ * stopped. */
+typedef enum
+{
+ IAPMU_COUNTER_0 = PMU_EVENT_COUNTER_1,
+ IAPMU_COUNTER_1 = PMU_EVENT_COUNTER_2,
+ IAPMU_CYCLE_COUNTER = PMU_CYCLE_COUNTER
+} IAPMU_MONITOR_COUNTER_TYPE;
+
+/* Target of event counter */
+typedef enum
+{
+ IAPMU_TARGET_ALL = 0, /* Count events on all TCs on all VPEs on current core. */
+ IAPMU_TARGET_VPE = 1, /* Count events on all TCs on VPE specified by target ID on current core. */
+ IAPMU_TARGET_TC = 2, /* Count events on TC specified by target ID on current core. */
+} IAPMU_MONITOR_TARGET_TYPE;
+
+/* Event IDs per counter. Refer MIPS IA Software Users Manual for detailled descriptions. */
+typedef enum
+{
+ /* Evenst available for IAPMU counter 0 */
+ PMU_EVENT_C0_FIRST_EVENT = 0,
+ PMU_EVENT_C0_CYCLES = PMU_EVENT_C0_FIRST_EVENT,
+ PMU_EVENT_C0_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C0_BRANCH_INSTRUCTIONS,
+ PMU_EVENT_C0_JR_R31_INSTRUCTIONS,
+ PMU_EVENT_C0_JR_NOT_R31_INSTRUCTIONS,
+ PMU_EVENT_C0_ITLB_ACCESSES,
+ PMU_EVENT_C0_DTLB_ACCESSES,
+ PMU_EVENT_C0_JTLB_INSTRUCTION_ACCESSES,
+ PMU_EVENT_C0_JTLB_DATA_ACCESSES,
+ PMU_EVENT_C0_INSTRUCTION_CACHE_ACCESSES,
+ PMU_EVENT_C0_DATA_CACHE_ACCESSES,
+ PMU_EVENT_C0_DATA_CACHE_MISSES,
+ PMU_EVENT_C0_RESERVED1,
+ PMU_EVENT_C0_STORE_MISSES,
+ PMU_EVENT_C0_INTEGER_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C0_LOADS_COMPLETED,
+ PMU_EVENT_C0_J_JAL_COMPLETED,
+ PMU_EVENT_C0_NO_OPS_COMPLETED,
+ PMU_EVENT_C0_STALL_CYCLES,
+ PMU_EVENT_C0_SC_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C0_PREFETCH_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C0_L2_CACHE_WRITEBACKS,
+ PMU_EVENT_C0_L2_CACHE_MISSES,
+ PMU_EVENT_C0_EXCEPTIONS_TAKEN,
+ PMU_EVENT_C0_CACHE_FIXUP,
+ PMU_EVENT_C0_IFU_STALL_CYCLES,
+ PMU_EVENT_C0_DSP_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C0_RESERVED2,
+ PMU_EVENT_C0_IMPL_SPECIFIC_PM_EVENT,
+ PMU_EVENT_C0_IMPL_SPECIFIC_ISPRAM_EVENT,
+ PMU_EVENT_C0_IMPL_SPECIFIC_COREXTEND_EVENT,
+ PMU_EVENT_C0_IMPL_SPECIFIC_XYM_EVENT,
+ PMU_EVENT_C0_ITC_LOADS,
+ PMU_EVENT_C0_UNCACHED_LOADS,
+ PMU_EVENT_C0_FORK_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C0_CP2_ARITHMETIC_INSTNS_COMPLETED,
+ PMU_EVENT_C0_INTERVENTION_STALL_MAIN_PIPE,
+ PMU_EVENT_C0_I_MISS_STALL_CYCLES,
+ PMU_EVENT_C0_SYNC_STALL_CYCLES,
+ PMU_EVENT_C0_D_MISS_CYCLES,
+ PMU_EVENT_C0_UNCACHED_STALL_CYCLES,
+ PMU_EVENT_C0_MDU_STALL_CYCLES,
+ PMU_EVENT_C0_CP2_STALL_CYCLES,
+ PMU_EVENT_C0_ISPRAM_STALL_CYCLES,
+ PMU_EVENT_C0_CACHE_INSTN_STALL_CYCLES,
+ PMU_EVENT_C0_LOAD_TO_USE_STALL_CYCLES,
+ PMU_EVENT_C0_OTHER_INTERLOCK_STALL_CYCLES,
+ PMU_EVENT_C0_RELAX_BUBBLES,
+ PMU_EVENT_C0_IFU_FB_FULL_REFETCHES,
+ PMU_EVENT_C0_EJTAG_INSTRUCTION_TRIGGERPOINTS,
+ PMU_EVENT_C0_FSB_LESS_THAN_1_4_FULL,
+ PMU_EVENT_C0_FSB_MORE_THAN_1_2_FULL,
+ PMU_EVENT_C0_LDQ_LESS_THAN_1_4_FULL,
+ PMU_EVENT_C0_LDQ_MORE_THAN_1_2_FULL,
+ PMU_EVENT_C0_WBB_LESS_THAN_1_4_FULL,
+ PMU_EVENT_C0_WBB_MORE_THAN_1_2_FULL,
+ PMU_EVENT_C0_INTERVENTION_HITS,
+ PMU_EVENT_C0_ALL_INVALIDATES,
+ PMU_EVENT_C0_EVICTIONS,
+ PMU_EVENT_C0_ST_INVAL,
+ PMU_EVENT_C0_ST_STORE_TO_S,
+ PMU_EVENT_C0_REQUEST_LATENCY_TO_SELF_INTERVENTION,
+ PMU_EVENT_C0_REQUEST_LATENCY_TO_READ_RESPONSE,
+ PMU_EVENT_C0_RESERVED3,
+ PMU_EVENT_C0_SYSTEM_SPECIFIC_EVENT_0,
+ PMU_EVENT_C0_SYSTEM_SPECIFIC_EVENT_2,
+ PMU_EVENT_C0_SYSTEM_SPECIFIC_EVENT_4,
+ PMU_EVENT_C0_SYSTEM_SPECIFIC_EVENT_6,
+ PMU_EVENT_C0_LAST_EVENT = 127,
+
+ /* Evenst available for IAPMU counter 1 */
+ /* Actual event id is <enum ID> - PMU_EVENT_C1_FIRST_EVENT */
+ PMU_EVENT_C1_FIRST_EVENT = 128,
+ PMU_EVENT_C1_CYCLES = PMU_EVENT_C1_FIRST_EVENT,
+ PMU_EVENT_C1_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C1_BRANCH_MISPREDICTIONS,
+ PMU_EVENT_C1_JR_R31_MISPREDICTIONS,
+ PMU_EVENT_C1_JR_R31_NOT_PREDICTED,
+ PMU_EVENT_C1_ITLB_MISSES,
+ PMU_EVENT_C1_DTLB_MISSES,
+ PMU_EVENT_C1_JTLB_INSTRUCTION_MISSES,
+ PMU_EVENT_C1_JTLB_DATA_MISSES,
+ PMU_EVENT_C1_INSTRUCTION_CACHE_MISSES,
+ PMU_EVENT_C1_DATA_CACHE_WRITEBACKS,
+ PMU_EVENT_C1_DATA_CACHE_MISSES,
+ PMU_EVENT_C1_RESERVED4,
+ PMU_EVENT_C1_LOAD_MISSES,
+ PMU_EVENT_C1_FPU_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C1_STORES_COMPLETED,
+ PMU_EVENT_C1_MIPS16_INSTRUCTIONS_COMPLETED,
+ PMU_EVENT_C1_INTEGER_MULTIPLY_DIVIDE_COMPLETED,
+ PMU_EVENT_C1_REPLAY_TRAPS_OTHER_THAN_UTLB,
+ PMU_EVENT_C1_SC_INSTRUCTIONS_FAILED,
+ PMU_EVENT_C1_PREFETCH_INSTRUCTIONS_COMPLETED_WITH_CACHE_HIT,
+ PMU_EVENT_C1_L2_CACHE_ACCESSES,
+ PMU_EVENT_C1_L2_CACHE_SINGLE_BIT_ERRORS_CORRECTED,
+ PMU_EVENT_C1_SINGLE_THREADED_MODE,
+ PMU_EVENT_C1_REFETCHES,
+ PMU_EVENT_C1_ALU_STALL_CYCLES,
+ PMU_EVENT_C1_ALU_DSP_SATURATIONS_DONE,
+ PMU_EVENT_C1_MDU_DSP_SATURATIONS_DONE,
+ PMU_EVENT_C1_IMPL_SPECIFIC_CP2_EVENT,
+ PMU_EVENT_C1_IMPL_SPECIFIC_DSPRAM_EVENT,
+ PMU_EVENT_C1_RESERVED5,
+ PMU_EVENT_C1_IMPL_SPECIFIC_ITC_EVENT,
+ PMU_EVENT_C1_ITC_STORES,
+ PMU_EVENT_C1_UNCACHED_STORES,
+ PMU_EVENT_C1_YIELD_INSTRUCTION_COMPLETED,
+ PMU_EVENT_C1_CP2_TO_FROM_INSTNS_COMPLETED,
+ PMU_EVENT_C1_INTERVENTION_RESPONSE_STALLED_ON_MISS,
+ PMU_EVENT_C1_D_MISS_STALL_CYCLES,
+ PMU_EVENT_C1_FSB_STALL_CYCLES,
+ PMU_EVENT_C1_L2_MISS_CYCLES,
+ PMU_EVENT_C1_ITC_STALL_CYCLES,
+ PMU_EVENT_C1_FPU_STALL_CYCLES,
+ PMU_EVENT_C1_COREXTEND_STALL_CYCLES,
+ PMU_EVENT_C1_DSPRAM_STALL_CYCLES,
+ PMU_EVENT_C1_LONG_STALL_CYCLES,
+ PMU_EVENT_C1_ALU_TO_AGEN_STALLS_CYCLES,
+ PMU_EVENT_C1_BRANCH_MISPREDICT_STALL_CYCLES,
+ PMU_EVENT_C1_NUMBER_OF_CORRECTED_ECC_ERRORS_IN_THE_L1_DATA_CACHE_OR_DSPRAM,
+ PMU_EVENT_C1_FB_ENTRY_ALLOCATED,
+ PMU_EVENT_C1_EJTAG_DATA_TRIGGERPOINTS,
+ PMU_EVENT_C1_FSB_1_4_TO_1_2_FULL,
+ PMU_EVENT_C1_FSB_FULL_PIPELINE_STALL_CYCLES,
+ PMU_EVENT_C1_LDQ_1_4_TO_1_2_FULL,
+ PMU_EVENT_C1_LDQ_FULL_PIPELINE_STALL_CYCLES,
+ PMU_EVENT_C1_WBB_1_4_TO_1_2_FULL,
+ PMU_EVENT_C1_WBB_FULL_PIPELINE_STALL_CYCLES,
+ PMU_EVENT_C1_ALL_INTERVENTIONS,
+ PMU_EVENT_C1_INVALIDATE_HITS,
+ PMU_EVENT_C1_WRITEBACKS,
+ PMU_EVENT_C1_ST_EXCLUSIVE,
+ PMU_EVENT_C1_ST_DOWNGRADE,
+ PMU_EVENT_C1_REQUEST_COUNT_FOR_SI_LATENCY,
+ PMU_EVENT_C1_REQUEST_COUNT_FOR_RESP_LATENCY_P,
+ PMU_EVENT_C1_RESERVED6,
+ PMU_EVENT_C1_SYSTEM_SPECIFIC_EVENT_1,
+ PMU_EVENT_C1_SYSTEM_SPECIFIC_EVENT_3,
+ PMU_EVENT_C1_SYSTEM_SPECIFIC_EVENT_5,
+ PMU_EVENT_C1_SYSTEM_SPECIFIC_EVENT_7,
+ PMU_EVENT_C1_LAST_EVENT = 255
+} IAPMU_MONITOR_EVENT_TYPE;
+
+#define DEF_MIPS_IAPMU_USER_SYS (0)
+#define DEF_MIPS_IAPMU_USER_SWLA (1)
+#define DEF_MIPS_IAPMU_USER_EL1BD (2)
+
+typedef enum {
+ MIPS_IAPMU_USER_SYS = DEF_MIPS_IAPMU_USER_SYS,
+ MIPS_IAPMU_USER_SWLA = DEF_MIPS_IAPMU_USER_SWLA,
+ MIPS_IAPMU_USER_EL1BD = DEF_MIPS_IAPMU_USER_EL1BD,
+ MIPS_IAPMU_USER_NR
+} MIPS_IA_PMU_USER_E;
+
+extern MIPS_IA_PMU_USER_E IAPMU_get_current_sw_cfg(void);
+extern IAPMU_STATUS_E IAPMU_set_current_sw_cfg(MIPS_IA_PMU_USER_E new_sw_cfg);
+
+/* [TC] force pmu function to m32 since some of them using mttc0/mftc0 */
+#if !defined(GEN_FOR_PC) && defined(__MTK_TARGET__)
+# if defined(__MIPS16__)
+# if defined(__GNUC__)
+# define MIPSIA_PMU_FUNC_ISA_TYPE __attribute__((nomips16))
+# endif
+# endif
+#endif
+
+#ifndef MIPSIA_PMU_FUNC_ISA_TYPE
+# define MIPSIA_PMU_FUNC_ISA_TYPE
+#endif
+
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_StartCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_StopCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_ResetCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_ReadCounter (IAPMU_MONITOR_COUNTER_TYPE cnt, kal_uint32 *val);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_SetEvent (IAPMU_MONITOR_COUNTER_TYPE cnt, IAPMU_MONITOR_EVENT_TYPE event, kal_uint32 target_id, IAPMU_MONITOR_TARGET_TYPE target_type, kal_uint32 context_mask);
+
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_StartCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_StopCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_ResetCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_ReadCounterTC (IAPMU_MONITOR_COUNTER_TYPE cnt, kal_uint32 target_tc, kal_uint32 *val);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SWLA_SetEventTC (IAPMU_MONITOR_COUNTER_TYPE cnt, IAPMU_MONITOR_EVENT_TYPE event, kal_uint32 target_tc, kal_uint32 target_id, IAPMU_MONITOR_TARGET_TYPE target_type, kal_uint32 context_mask);
+
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_StartCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_StopCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_ResetCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_ReadCounter (IAPMU_MONITOR_COUNTER_TYPE cnt, kal_uint32 *val);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_SetEvent (IAPMU_MONITOR_COUNTER_TYPE cnt, IAPMU_MONITOR_EVENT_TYPE event, kal_uint32 target_id, IAPMU_MONITOR_TARGET_TYPE target_type, kal_uint32 context_mask);
+
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_StartCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_StopCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_ResetCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_ReadCounterTC (IAPMU_MONITOR_COUNTER_TYPE cnt, kal_uint32 target_tc, kal_uint32 *val);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_EL1BD_SetEventTC (IAPMU_MONITOR_COUNTER_TYPE cnt, IAPMU_MONITOR_EVENT_TYPE event, kal_uint32 target_tc, kal_uint32 target_id, IAPMU_MONITOR_TARGET_TYPE target_type, kal_uint32 context_mask);
+
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_StartCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_StopCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_ResetCounter (kal_uint32 cnts);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_ReadCounter (IAPMU_MONITOR_COUNTER_TYPE cnt, kal_uint32 *val);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_SetEvent (IAPMU_MONITOR_COUNTER_TYPE cnt, IAPMU_MONITOR_EVENT_TYPE event, kal_uint32 target_id, IAPMU_MONITOR_TARGET_TYPE target_type, kal_uint32 context_mask);
+
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_StartCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_StopCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_ResetCounterTC (kal_uint32 cnts, kal_uint32 target_tc_mask);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_ReadCounterTC (IAPMU_MONITOR_COUNTER_TYPE cnt, kal_uint32 target_tc, kal_uint32 *val);
+MIPSIA_PMU_FUNC_ISA_TYPE extern const kal_uint32 IAPMU_SYS_SetEventTC (IAPMU_MONITOR_COUNTER_TYPE cnt, IAPMU_MONITOR_EVENT_TYPE event, kal_uint32 target_tc, kal_uint32 target_id, IAPMU_MONITOR_TARGET_TYPE target_type, kal_uint32 context_mask);
+
+#endif /* __MIPS_IA__ || __MIPS_I7200__ */
+#endif /* __MTK_TARGET__ */
+#endif /* MCU_PMU_MONTR_MIPS_IA_PUBLIC_H */
diff --git a/mcu/interface/driver/sys_drv/mcu_pmu_montr_public.h b/mcu/interface/driver/sys_drv/mcu_pmu_montr_public.h
new file mode 100644
index 0000000..eb54d66
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mcu_pmu_montr_public.h
@@ -0,0 +1,93 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2016
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mcu_pmu_montr_public.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * Header file general ARM core performance monitor API
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ ******************************************************************************/
+#ifndef MCU_PMU_MONTR_PUBLIC_H
+#ifdef __MTK_TARGET__
+
+#define MCU_PMU_MONTR_PUBLIC_H
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+
+#if defined(__MIPS_IA__)
+#define PMU_EVENT_COUNTER_1 0x00000001
+#define PMU_EVENT_COUNTER_2 0x00000002
+#define PMU_EVENT_COUNTER_3 0x00000004
+#define PMU_CYCLE_COUNTER 0x80000000
+
+typedef enum {
+ PMU_STATUS_OK = 0,
+ PMU_STATUS_ERROR = 0xFFFFFFFF,
+ PMU_STATUS_NOPERM = 0xFFFFFFFE,
+} IAPMU_STATUS_E;
+
+# include "mcu_pmu_montr_mips_ia_public.h"
+#elif defined(__MIPS_I7200__)
+/* I7200 PMU are not public */
+/* backward compatible for dhl */
+# define PMU_CYCLE_COUNTER 0x80000000
+#endif
+
+#endif /* __MTK_TARGET__ */
+#endif /* MCU_PMU_MONTR_PUBLIC_H */
diff --git a/mcu/interface/driver/sys_drv/mdm_trc.h b/mcu/interface/driver/sys_drv/mdm_trc.h
new file mode 100644
index 0000000..069ebd0
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mdm_trc.h
@@ -0,0 +1,902 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mdm_trc.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * This file defines the index trace of MDM module.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _MDM_TRACE_H
+#define _MDM_TRACE_H
+
+void MDM_ASSERT(kal_uint32 e1, kal_uint32 e2, kal_uint32 e3);
+void MDM_kal_fatal_error_handler(kal_uint32 code1, kal_uint32 code2);
+void MDM_EXCEPTION(void);
+
+#define MDM_BASE 0xb0490000
+#define MDM32P volatile unsigned int *
+#define MDM_TM_TINFOMSG ((MDM32P)(MDM_BASE+0x0000)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR ((MDM32P)(MDM_BASE+0x0004)) //apb32 message parameter
+#define MDM_TM_INFOMSG ((MDM32P)(MDM_BASE+0x0008)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG ((MDM32P)(MDM_BASE+0x000C)) //apb32 Error Message Register
+#define MDM_TM_TTAG ((MDM32P)(MDM_BASE+0x0010)) //apb32 TTAG
+#define MDM_TM_ENDSIM ((MDM32P)(MDM_BASE+0x0014)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT ((MDM32P)(MDM_BASE+0x0018)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO ((MDM32P)(MDM_BASE+0x001c)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG ((MDM32P)(MDM_BASE+0x0020)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK ((MDM32P)(MDM_BASE+0x0024)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL ((MDM32P)(MDM_BASE+0x0028)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC ((MDM32P)(MDM_BASE+0x002C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT ((MDM32P)(MDM_BASE+0x0030)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B ((MDM32P)(MDM_BASE+0x0034)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B ((MDM32P)(MDM_BASE+0x0038)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B ((MDM32P)(MDM_BASE+0x003C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B ((MDM32P)(MDM_BASE+0x0040)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B ((MDM32P)(MDM_BASE+0x0044)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B ((MDM32P)(MDM_BASE+0x0048)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B ((MDM32P)(MDM_BASE+0x004C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR ((MDM32P)(MDM_BASE+0x0050)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP ((MDM32P)(MDM_BASE+0x0054)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR ((MDM32P)(MDM_BASE+0x0058)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP ((MDM32P)(MDM_BASE+0x005C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR ((MDM32P)(MDM_BASE+0x0060)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP ((MDM32P)(MDM_BASE+0x0064)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO ((MDM32P)(MDM_BASE+0x0068)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC ((MDM32P)(MDM_BASE+0x006C)) // apb32
+#define MDM_TM_PHASE ((MDM32P)(MDM_BASE+0x0070)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION ((MDM32P)(MDM_BASE+0x0074)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE ((MDM32P)(MDM_BASE+0x0080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS ((MDM32P)(MDM_BASE+0x0084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP ((MDM32P)(MDM_BASE+0x0088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE ((MDM32P)(MDM_BASE+0x008C)) // apb32
+
+#define MDM_TM_STR_CLEAR ((MDM32P)(MDM_BASE+0x0090)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY ((MDM32P)(MDM_BASE+0x0094)) // apb32 display string buf
+#define MDM_TM_STR0 ((MDM32P)(MDM_BASE+0x0098)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1 ((MDM32P)(MDM_BASE+0x009c)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2 ((MDM32P)(MDM_BASE+0x00a0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3 ((MDM32P)(MDM_BASE+0x00a4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4 ((MDM32P)(MDM_BASE+0x00a8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5 ((MDM32P)(MDM_BASE+0x00ac)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6 ((MDM32P)(MDM_BASE+0x00b0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7 ((MDM32P)(MDM_BASE+0x00b4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ ((MDM32P)(MDM_BASE+0x00b8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2 ((MDM32P)(MDM_BASE+0x00bC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG ((MDM32P)(MDM_BASE+0x0078)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2 ((MDM32P)(MDM_BASE+0x007C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL ((MDM32P)(MDM_BASE+0x00E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL ((MDM32P)(MDM_BASE+0x00E4)) //apb32
+
+#define MDM_TM_FH_CTRL ((MDM32P)(MDM_BASE+0x00E8)) //apb32
+#define MDM_DELAY ((MDM32P)(MDM_BASE+0x00EC)) //apb32
+#define MDM_RANDOM_DELAY_MIN ((MDM32P)(MDM_BASE+0x00F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX ((MDM32P)(MDM_BASE+0x00F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN ((MDM32P)(MDM_BASE+0x00F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX ((MDM32P)(MDM_BASE+0x00FC)) //apb32
+
+
+#define MDM_TM_TINFOMSG_01 ((MDM32P)(MDM_BASE+0x0100)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_01 ((MDM32P)(MDM_BASE+0x0104)) //apb32 message parameter
+#define MDM_TM_INFOMSG_01 ((MDM32P)(MDM_BASE+0x0108)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_01 ((MDM32P)(MDM_BASE+0x010C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_01 ((MDM32P)(MDM_BASE+0x0110)) //apb32 TTAG
+#define MDM_TM_ENDSIM_01 ((MDM32P)(MDM_BASE+0x0114)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_01 ((MDM32P)(MDM_BASE+0x0118)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_01 ((MDM32P)(MDM_BASE+0x011c)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_01 ((MDM32P)(MDM_BASE+0x0120)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_01 ((MDM32P)(MDM_BASE+0x0124)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_01 ((MDM32P)(MDM_BASE+0x0128)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_01 ((MDM32P)(MDM_BASE+0x012C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_01 ((MDM32P)(MDM_BASE+0x0130)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_01 ((MDM32P)(MDM_BASE+0x0134)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_01 ((MDM32P)(MDM_BASE+0x0138)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_01 ((MDM32P)(MDM_BASE+0x013C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_01 ((MDM32P)(MDM_BASE+0x0140)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_01 ((MDM32P)(MDM_BASE+0x0144)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_01 ((MDM32P)(MDM_BASE+0x0148)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_01 ((MDM32P)(MDM_BASE+0x014C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_01 ((MDM32P)(MDM_BASE+0x0150)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_01 ((MDM32P)(MDM_BASE+0x0154)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_01 ((MDM32P)(MDM_BASE+0x0158)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_01 ((MDM32P)(MDM_BASE+0x015C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_01 ((MDM32P)(MDM_BASE+0x0160)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_01 ((MDM32P)(MDM_BASE+0x0164)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_01 ((MDM32P)(MDM_BASE+0x0168)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_01 ((MDM32P)(MDM_BASE+0x016C)) // apb32
+#define MDM_TM_PHASE_01 ((MDM32P)(MDM_BASE+0x0170)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_01 ((MDM32P)(MDM_BASE+0x0174)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_01 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_01 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_01 ((MDM32P)(MDM_BASE+0x0180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_01 ((MDM32P)(MDM_BASE+0x0184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_01 ((MDM32P)(MDM_BASE+0x0188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_01 ((MDM32P)(MDM_BASE+0x018C)) // apb32
+
+#define MDM_TM_STR_CLEAR_01 ((MDM32P)(MDM_BASE+0x0190)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_01 ((MDM32P)(MDM_BASE+0x0194)) // apb32 display string buf
+#define MDM_TM_STR0_01 ((MDM32P)(MDM_BASE+0x0198)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_01 ((MDM32P)(MDM_BASE+0x019C)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_01 ((MDM32P)(MDM_BASE+0x01A0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_01 ((MDM32P)(MDM_BASE+0x01A4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_01 ((MDM32P)(MDM_BASE+0x01A8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_01 ((MDM32P)(MDM_BASE+0x01AC)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_01 ((MDM32P)(MDM_BASE+0x01B0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_01 ((MDM32P)(MDM_BASE+0x01B4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_01 ((MDM32P)(MDM_BASE+0x01B8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_01 ((MDM32P)(MDM_BASE+0x01BC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_01 ((MDM32P)(MDM_BASE+0x0178)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_01 ((MDM32P)(MDM_BASE+0x017C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_01 ((MDM32P)(MDM_BASE+0x01E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_01 ((MDM32P)(MDM_BASE+0x01E4)) //apb32
+
+#define MDM_TM_FH_CTRL_01 ((MDM32P)(MDM_BASE+0x01E8)) //apb32
+#define MDM_DELAY_01 ((MDM32P)(MDM_BASE+0x01EC)) //apb32
+#define MDM_RANDOM_DELAY_MIN_01 ((MDM32P)(MDM_BASE+0x01F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_01 ((MDM32P)(MDM_BASE+0x01F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_01 ((MDM32P)(MDM_BASE+0x01F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_01 ((MDM32P)(MDM_BASE+0x01FC)) //apb32
+
+#define MDM_TM_TINFOMSG_10 ((MDM32P)(MDM_BASE+0x1000)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_10 ((MDM32P)(MDM_BASE+0x1004)) //apb32 message parameter
+#define MDM_TM_INFOMSG_10 ((MDM32P)(MDM_BASE+0x1008)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_10 ((MDM32P)(MDM_BASE+0x100C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_10 ((MDM32P)(MDM_BASE+0x1010)) //apb32 TTAG
+#define MDM_TM_ENDSIM_10 ((MDM32P)(MDM_BASE+0x1014)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_10 ((MDM32P)(MDM_BASE+0x1018)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_10 ((MDM32P)(MDM_BASE+0x101C)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_10 ((MDM32P)(MDM_BASE+0x1020)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_10 ((MDM32P)(MDM_BASE+0x1024)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_10 ((MDM32P)(MDM_BASE+0x1028)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_10 ((MDM32P)(MDM_BASE+0x102C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_10 ((MDM32P)(MDM_BASE+0x1030)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_10 ((MDM32P)(MDM_BASE+0x1034)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_10 ((MDM32P)(MDM_BASE+0x1038)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_10 ((MDM32P)(MDM_BASE+0x103C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_10 ((MDM32P)(MDM_BASE+0x1040)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_10 ((MDM32P)(MDM_BASE+0x1044)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_10 ((MDM32P)(MDM_BASE+0x1048)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_10 ((MDM32P)(MDM_BASE+0x104C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_10 ((MDM32P)(MDM_BASE+0x1050)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_10 ((MDM32P)(MDM_BASE+0x1054)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_10 ((MDM32P)(MDM_BASE+0x1058)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_10 ((MDM32P)(MDM_BASE+0x105C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_10 ((MDM32P)(MDM_BASE+0x1060)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_10 ((MDM32P)(MDM_BASE+0x1064)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_10 ((MDM32P)(MDM_BASE+0x1068)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_10 ((MDM32P)(MDM_BASE+0x106C)) // apb32
+#define MDM_TM_PHASE_10 ((MDM32P)(MDM_BASE+0x1070)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_10 ((MDM32P)(MDM_BASE+0x1074)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_10 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_10 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_10 ((MDM32P)(MDM_BASE+0x1080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_10 ((MDM32P)(MDM_BASE+0x1084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_10 ((MDM32P)(MDM_BASE+0x1088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_10 ((MDM32P)(MDM_BASE+0x108C)) // apb32
+
+#define MDM_TM_STR_CLEAR_10 ((MDM32P)(MDM_BASE+0x1090)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_10 ((MDM32P)(MDM_BASE+0x1094)) // apb32 display string buf
+#define MDM_TM_STR0_10 ((MDM32P)(MDM_BASE+0x1098)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_10 ((MDM32P)(MDM_BASE+0x109C)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_10 ((MDM32P)(MDM_BASE+0x10A0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_10 ((MDM32P)(MDM_BASE+0x10A4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_10 ((MDM32P)(MDM_BASE+0x10A8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_10 ((MDM32P)(MDM_BASE+0x10AC)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_10 ((MDM32P)(MDM_BASE+0x10B0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_10 ((MDM32P)(MDM_BASE+0x10B4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_10 ((MDM32P)(MDM_BASE+0x10B8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_10 ((MDM32P)(MDM_BASE+0x10BC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_10 ((MDM32P)(MDM_BASE+0x1078)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_10 ((MDM32P)(MDM_BASE+0x107C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_10 ((MDM32P)(MDM_BASE+0x10E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_10 ((MDM32P)(MDM_BASE+0x10E4)) //apb32
+
+#define MDM_TM_FH_CTRL_10 ((MDM32P)(MDM_BASE+0x10E8)) //apb32
+#define MDM_DELAY_10 ((MDM32P)(MDM_BASE+0x10EC)) //apb32
+#define MDM_RANDOM_DELAY_MIN_10 ((MDM32P)(MDM_BASE+0x10F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_10 ((MDM32P)(MDM_BASE+0x10F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_10 ((MDM32P)(MDM_BASE+0x10F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_10 ((MDM32P)(MDM_BASE+0x10FC)) //apb32
+
+#define MDM_TM_TINFOMSG_11 ((MDM32P)(MDM_BASE+0x1100)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_11 ((MDM32P)(MDM_BASE+0x1104)) //apb32 message parameter
+#define MDM_TM_INFOMSG_11 ((MDM32P)(MDM_BASE+0x1108)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_11 ((MDM32P)(MDM_BASE+0x110C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_11 ((MDM32P)(MDM_BASE+0x1110)) //apb32 TTAG
+#define MDM_TM_ENDSIM_11 ((MDM32P)(MDM_BASE+0x1114)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_11 ((MDM32P)(MDM_BASE+0x1118)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_11 ((MDM32P)(MDM_BASE+0x111C)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_11 ((MDM32P)(MDM_BASE+0x1120)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_11 ((MDM32P)(MDM_BASE+0x1124)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_11 ((MDM32P)(MDM_BASE+0x1128)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_11 ((MDM32P)(MDM_BASE+0x112C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_11 ((MDM32P)(MDM_BASE+0x1130)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_11 ((MDM32P)(MDM_BASE+0x1134)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_11 ((MDM32P)(MDM_BASE+0x1138)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_11 ((MDM32P)(MDM_BASE+0x113C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_11 ((MDM32P)(MDM_BASE+0x1140)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_11 ((MDM32P)(MDM_BASE+0x1144)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_11 ((MDM32P)(MDM_BASE+0x1148)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_11 ((MDM32P)(MDM_BASE+0x114C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_11 ((MDM32P)(MDM_BASE+0x1150)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_11 ((MDM32P)(MDM_BASE+0x1154)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_11 ((MDM32P)(MDM_BASE+0x1158)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_11 ((MDM32P)(MDM_BASE+0x115C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_11 ((MDM32P)(MDM_BASE+0x1160)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_11 ((MDM32P)(MDM_BASE+0x1164)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_11 ((MDM32P)(MDM_BASE+0x1168)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_11 ((MDM32P)(MDM_BASE+0x116C)) // apb32
+#define MDM_TM_PHASE_11 ((MDM32P)(MDM_BASE+0x1170)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_11 ((MDM32P)(MDM_BASE+0x1174)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_11 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_11 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_11 ((MDM32P)(MDM_BASE+0x1180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_11 ((MDM32P)(MDM_BASE+0x1184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_11 ((MDM32P)(MDM_BASE+0x1188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_11 ((MDM32P)(MDM_BASE+0x118C)) // apb32
+
+#define MDM_TM_STR_CLEAR_11 ((MDM32P)(MDM_BASE+0x1190)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_11 ((MDM32P)(MDM_BASE+0x1194)) // apb32 display string buf
+#define MDM_TM_STR0_11 ((MDM32P)(MDM_BASE+0x1198)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_11 ((MDM32P)(MDM_BASE+0x119C)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_11 ((MDM32P)(MDM_BASE+0x11A0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_11 ((MDM32P)(MDM_BASE+0x11A4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_11 ((MDM32P)(MDM_BASE+0x11A8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_11 ((MDM32P)(MDM_BASE+0x11AC)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_11 ((MDM32P)(MDM_BASE+0x11B0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_11 ((MDM32P)(MDM_BASE+0x11B4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_11 ((MDM32P)(MDM_BASE+0x11B8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_11 ((MDM32P)(MDM_BASE+0x11BC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_11 ((MDM32P)(MDM_BASE+0x1178)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_11 ((MDM32P)(MDM_BASE+0x117C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_11 ((MDM32P)(MDM_BASE+0x11E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_11 ((MDM32P)(MDM_BASE+0x11E4)) //apb32
+
+#define MDM_TM_FH_CTRL_11 ((MDM32P)(MDM_BASE+0x11E8)) //apb32
+#define MDM_DELAY_11 ((MDM32P)(MDM_BASE+0x11EC)) //apb32
+#define MDM_RANDOM_DELAY_MIN_11 ((MDM32P)(MDM_BASE+0x11F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_11 ((MDM32P)(MDM_BASE+0x11F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_11 ((MDM32P)(MDM_BASE+0x11F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_11 ((MDM32P)(MDM_BASE+0x11Fc)) //apb32
+
+#ifdef INCLUDE_MT6293_NOT_INCLUDED_CORES
+#define MDM_TM_TINFOMSG_20 ((MDM32P)(MDM_BASE+0x2000)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_20 ((MDM32P)(MDM_BASE+0x2004)) //apb32 message parameter
+#define MDM_TM_INFOMSG_20 ((MDM32P)(MDM_BASE+0x2008)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_20 ((MDM32P)(MDM_BASE+0x200C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_20 ((MDM32P)(MDM_BASE+0x2010)) //apb32 TTAG
+#define MDM_TM_ENDSIM_20 ((MDM32P)(MDM_BASE+0x2014)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_20 ((MDM32P)(MDM_BASE+0x2018)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_20 ((MDM32P)(MDM_BASE+0x201C)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_20 ((MDM32P)(MDM_BASE+0x2020)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_20 ((MDM32P)(MDM_BASE+0x2024)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_20 ((MDM32P)(MDM_BASE+0x2028)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_20 ((MDM32P)(MDM_BASE+0x202C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_20 ((MDM32P)(MDM_BASE+0x2030)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_20 ((MDM32P)(MDM_BASE+0x2034)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_20 ((MDM32P)(MDM_BASE+0x2038)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_20 ((MDM32P)(MDM_BASE+0x203C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_20 ((MDM32P)(MDM_BASE+0x2040)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_20 ((MDM32P)(MDM_BASE+0x2044)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_20 ((MDM32P)(MDM_BASE+0x2048)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_20 ((MDM32P)(MDM_BASE+0x204C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_20 ((MDM32P)(MDM_BASE+0x2050)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_20 ((MDM32P)(MDM_BASE+0x2054)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_20 ((MDM32P)(MDM_BASE+0x2058)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_20 ((MDM32P)(MDM_BASE+0x205C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_20 ((MDM32P)(MDM_BASE+0x2060)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_20 ((MDM32P)(MDM_BASE+0x2064)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_20 ((MDM32P)(MDM_BASE+0x2068)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_20 ((MDM32P)(MDM_BASE+0x206C)) // apb32
+#define MDM_TM_PHASE_20 ((MDM32P)(MDM_BASE+0x2070)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_20 ((MDM32P)(MDM_BASE+0x2074)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_20 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_20 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_20 ((MDM32P)(MDM_BASE+0x2080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_20 ((MDM32P)(MDM_BASE+0x2084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_20 ((MDM32P)(MDM_BASE+0x2088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_20 ((MDM32P)(MDM_BASE+0x208C)) // apb32
+
+#define MDM_TM_STR_CLEAR_20 ((MDM32P)(MDM_BASE+0x2090)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_20 ((MDM32P)(MDM_BASE+0x2094)) // apb32 display string buf
+#define MDM_TM_STR0_20 ((MDM32P)(MDM_BASE+0x2098)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_20 ((MDM32P)(MDM_BASE+0x209C)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_20 ((MDM32P)(MDM_BASE+0x20A0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_20 ((MDM32P)(MDM_BASE+0x20A4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_20 ((MDM32P)(MDM_BASE+0x20A8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_20 ((MDM32P)(MDM_BASE+0x20AC)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_20 ((MDM32P)(MDM_BASE+0x20B0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_20 ((MDM32P)(MDM_BASE+0x20B4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_20 ((MDM32P)(MDM_BASE+0x20B8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_20 ((MDM32P)(MDM_BASE+0x20BC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_20 ((MDM32P)(MDM_BASE+0x2078)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_20 ((MDM32P)(MDM_BASE+0x207C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_20 ((MDM32P)(MDM_BASE+0x20E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_20 ((MDM32P)(MDM_BASE+0x20E4)) //apb32
+
+#define MDM_TM_FH_CTRL_20 ((MDM32P)(MDM_BASE+0x20E8)) //apb32
+#define MDM_DELAY_20 ((MDM32P)(MDM_BASE+0x20EC)) //apb32
+#define MDM_RANDOM_DELAY_MIN_20 ((MDM32P)(MDM_BASE+0x20F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_20 ((MDM32P)(MDM_BASE+0x20F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_20 ((MDM32P)(MDM_BASE+0x20F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_20 ((MDM32P)(MDM_BASE+0x20Fc)) //apb32
+
+#define MDM_TM_TINFOMSG_21 ((MDM32P)(MDM_BASE+0x2100)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_21 ((MDM32P)(MDM_BASE+0x2104)) //apb32 message parameter
+#define MDM_TM_INFOMSG_21 ((MDM32P)(MDM_BASE+0x2108)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_21 ((MDM32P)(MDM_BASE+0x210C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_21 ((MDM32P)(MDM_BASE+0x2110)) //apb32 TTAG
+#define MDM_TM_ENDSIM_21 ((MDM32P)(MDM_BASE+0x2114)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_21 ((MDM32P)(MDM_BASE+0x2118)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_21 ((MDM32P)(MDM_BASE+0x211c)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_21 ((MDM32P)(MDM_BASE+0x2120)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_21 ((MDM32P)(MDM_BASE+0x2124)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_21 ((MDM32P)(MDM_BASE+0x2128)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_21 ((MDM32P)(MDM_BASE+0x212C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_21 ((MDM32P)(MDM_BASE+0x2130)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_21 ((MDM32P)(MDM_BASE+0x2134)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_21 ((MDM32P)(MDM_BASE+0x2138)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_21 ((MDM32P)(MDM_BASE+0x213C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_21 ((MDM32P)(MDM_BASE+0x2140)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_21 ((MDM32P)(MDM_BASE+0x2144)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_21 ((MDM32P)(MDM_BASE+0x2148)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_21 ((MDM32P)(MDM_BASE+0x214C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_21 ((MDM32P)(MDM_BASE+0x2150)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_21 ((MDM32P)(MDM_BASE+0x2154)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_21 ((MDM32P)(MDM_BASE+0x2158)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_21 ((MDM32P)(MDM_BASE+0x215C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_21 ((MDM32P)(MDM_BASE+0x2160)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_21 ((MDM32P)(MDM_BASE+0x2164)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_21 ((MDM32P)(MDM_BASE+0x2168)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_21 ((MDM32P)(MDM_BASE+0x216C)) // apb32
+#define MDM_TM_PHASE_21 ((MDM32P)(MDM_BASE+0x2170)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_21 ((MDM32P)(MDM_BASE+0x2174)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_21 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_21 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_21 ((MDM32P)(MDM_BASE+0x2180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_21 ((MDM32P)(MDM_BASE+0x2184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_21 ((MDM32P)(MDM_BASE+0x2188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_21 ((MDM32P)(MDM_BASE+0x218C)) // apb32
+
+#define MDM_TM_STR_CLEAR_21 ((MDM32P)(MDM_BASE+0x2190)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_21 ((MDM32P)(MDM_BASE+0x2194)) // apb32 display string buf
+#define MDM_TM_STR0_21 ((MDM32P)(MDM_BASE+0x2198)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_21 ((MDM32P)(MDM_BASE+0x219C)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_21 ((MDM32P)(MDM_BASE+0x21A0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_21 ((MDM32P)(MDM_BASE+0x21A4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_21 ((MDM32P)(MDM_BASE+0x21A8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_21 ((MDM32P)(MDM_BASE+0x21AC)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_21 ((MDM32P)(MDM_BASE+0x21B0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_21 ((MDM32P)(MDM_BASE+0x21B4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_21 ((MDM32P)(MDM_BASE+0x21B8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_21 ((MDM32P)(MDM_BASE+0x21BC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_21 ((MDM32P)(MDM_BASE+0x2178)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_21 ((MDM32P)(MDM_BASE+0x217C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_21 ((MDM32P)(MDM_BASE+0x21E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_21 ((MDM32P)(MDM_BASE+0x21E4)) //apb32
+
+#define MDM_TM_FH_CTRL_21 ((MDM32P)(MDM_BASE+0x21E8)) //apb32
+#define MDM_DELAY_21 ((MDM32P)(MDM_BASE+0x21Ec)) //apb32
+#define MDM_RANDOM_DELAY_MIN_21 ((MDM32P)(MDM_BASE+0x21F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_21 ((MDM32P)(MDM_BASE+0x21F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_21 ((MDM32P)(MDM_BASE+0x21F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_21 ((MDM32P)(MDM_BASE+0x21Fc)) //apb32
+
+#define MDM_TM_TINFOMSG_30 ((MDM32P)(MDM_BASE+0x3000)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_30 ((MDM32P)(MDM_BASE+0x3004)) //apb32 message parameter
+#define MDM_TM_INFOMSG_30 ((MDM32P)(MDM_BASE+0x3008)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_30 ((MDM32P)(MDM_BASE+0x300C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_30 ((MDM32P)(MDM_BASE+0x3010)) //apb32 TTAG
+#define MDM_TM_ENDSIM_30 ((MDM32P)(MDM_BASE+0x3014)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_30 ((MDM32P)(MDM_BASE+0x3018)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_30 ((MDM32P)(MDM_BASE+0x301c)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_30 ((MDM32P)(MDM_BASE+0x3020)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_30 ((MDM32P)(MDM_BASE+0x3024)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_30 ((MDM32P)(MDM_BASE+0x3028)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_30 ((MDM32P)(MDM_BASE+0x302C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_30 ((MDM32P)(MDM_BASE+0x3030)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_30 ((MDM32P)(MDM_BASE+0x3034)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_30 ((MDM32P)(MDM_BASE+0x3038)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_30 ((MDM32P)(MDM_BASE+0x303C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_30 ((MDM32P)(MDM_BASE+0x3040)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_30 ((MDM32P)(MDM_BASE+0x3044)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_30 ((MDM32P)(MDM_BASE+0x3048)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_30 ((MDM32P)(MDM_BASE+0x304C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_30 ((MDM32P)(MDM_BASE+0x3050)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_30 ((MDM32P)(MDM_BASE+0x3054)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_30 ((MDM32P)(MDM_BASE+0x3058)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_30 ((MDM32P)(MDM_BASE+0x305C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_30 ((MDM32P)(MDM_BASE+0x3060)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_30 ((MDM32P)(MDM_BASE+0x3064)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_30 ((MDM32P)(MDM_BASE+0x3068)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_30 ((MDM32P)(MDM_BASE+0x306C)) // apb32
+#define MDM_TM_PHASE_30 ((MDM32P)(MDM_BASE+0x3070)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_30 ((MDM32P)(MDM_BASE+0x3074)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_30 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_30 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_30 ((MDM32P)(MDM_BASE+0x3080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_30 ((MDM32P)(MDM_BASE+0x3084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_30 ((MDM32P)(MDM_BASE+0x3088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_30 ((MDM32P)(MDM_BASE+0x308C)) // apb32
+
+#define MDM_TM_STR_CLEAR_30 ((MDM32P)(MDM_BASE+0x3090)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_30 ((MDM32P)(MDM_BASE+0x3094)) // apb32 display string buf
+#define MDM_TM_STR0_30 ((MDM32P)(MDM_BASE+0x3098)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_30 ((MDM32P)(MDM_BASE+0x309c)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_30 ((MDM32P)(MDM_BASE+0x30a0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_30 ((MDM32P)(MDM_BASE+0x30a4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_30 ((MDM32P)(MDM_BASE+0x30a8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_30 ((MDM32P)(MDM_BASE+0x30ac)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_30 ((MDM32P)(MDM_BASE+0x30b0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_30 ((MDM32P)(MDM_BASE+0x30b4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_30 ((MDM32P)(MDM_BASE+0x30b8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_30 ((MDM32P)(MDM_BASE+0x30bC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_30 ((MDM32P)(MDM_BASE+0x3078)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_30 ((MDM32P)(MDM_BASE+0x307C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_30 ((MDM32P)(MDM_BASE+0x30E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_30 ((MDM32P)(MDM_BASE+0x30E4)) //apb32
+
+#define MDM_TM_FH_CTRL_30 ((MDM32P)(MDM_BASE+0x30E8)) //apb32
+#define MDM_DELAY_30 ((MDM32P)(MDM_BASE+0x30Ec)) //apb32
+#define MDM_RANDOM_DELAY_MIN_30 ((MDM32P)(MDM_BASE+0x30F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_30 ((MDM32P)(MDM_BASE+0x30F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_30 ((MDM32P)(MDM_BASE+0x30F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_30 ((MDM32P)(MDM_BASE+0x30Fc)) //apb32
+
+#define MDM_TM_TINFOMSG_31 ((MDM32P)(MDM_BASE+0x3100)) //apb32 Information Message Register (T)
+#define MDM_TM_TPAR_31 ((MDM32P)(MDM_BASE+0x3104)) //apb32 message parameter
+#define MDM_TM_INFOMSG_31 ((MDM32P)(MDM_BASE+0x3108)) //apb32 Information Message Register
+#define MDM_TM_ERRMSG_31 ((MDM32P)(MDM_BASE+0x310C)) //apb32 Error Message Register
+#define MDM_TM_TTAG_31 ((MDM32P)(MDM_BASE+0x3110)) //apb32 TTAG
+#define MDM_TM_ENDSIM_31 ((MDM32P)(MDM_BASE+0x3114)) //apb32 End Simulation Register
+#define MDM_TM_ERRCNT_31 ((MDM32P)(MDM_BASE+0x3118)) //apb32 Error Count Register
+#define MDM_TM_DBGINFO_31 ((MDM32P)(MDM_BASE+0x311c)) //apb32 Debug Infomation
+#define MDM_TM_TERRMSG_31 ((MDM32P)(MDM_BASE+0x3120)) //apb32 Error Message Register (T)
+#define MDM_TM_TBLANK_31 ((MDM32P)(MDM_BASE+0x3124)) //apb32 Blank line (T)
+#define MDM_TM_ENDFAIL_31 ((MDM32P)(MDM_BASE+0x3128)) //apb32 End Simulation With Fail Msg
+#define MDM_TM_ENDSUCC_31 ((MDM32P)(MDM_BASE+0x312C)) //apb32 End Simulation With Success Msg
+#define MDM_TM_ENDASSERT_31 ((MDM32P)(MDM_BASE+0x3130)) //apb32 End Simulation Register
+#define MDM_TM_ALLFMT32B_31 ((MDM32P)(MDM_BASE+0x3134)) //apb32 Display All Format 32b Value
+#define MDM_TM_HEXFMT32B_31 ((MDM32P)(MDM_BASE+0x3138)) //apb32 Display Hexa Format 32b Value
+#define MDM_TM_DECFMT32B_31 ((MDM32P)(MDM_BASE+0x313C)) //apb32 Display Dec Format 32b Value
+#define MDM_TM_BINFMT32B_31 ((MDM32P)(MDM_BASE+0x3140)) //apb32 Display Bin Format 32b Value
+#define MDM_TM_HEXFMT16B_31 ((MDM32P)(MDM_BASE+0x3144)) //apb32 Display Hexa Format 16b Value
+#define MDM_TM_DECFMT16B_31 ((MDM32P)(MDM_BASE+0x3148)) //apb32 Display Dec Format 16b Value
+#define MDM_TM_BINFMT16B_31 ((MDM32P)(MDM_BASE+0x314C)) //apb32 Display Bin Format 16b Value
+
+#define MDM_TM_MEMDUMPSTR_31 ((MDM32P)(MDM_BASE+0x3150)) //apb32 Start Address of Memory Dumping
+#define MDM_TM_MEMDUMPSTOP_31 ((MDM32P)(MDM_BASE+0x3154)) //apb32 Stop Address of Memory Dumping
+
+#define MDM_TM_MEMGOLDENSTR_31 ((MDM32P)(MDM_BASE+0x3158)) //apb32 Start Address of Memory Compare(Golden)
+#define MDM_TM_MEMGOLDENSTOP_31 ((MDM32P)(MDM_BASE+0x315C)) //apb32 Stop Address of Memory Compare(Golden)
+
+#define MDM_TM_MEMREVISESTR_31 ((MDM32P)(MDM_BASE+0x3160)) //apb32 Start Address of Memory Compare(Revised)
+#define MDM_TM_MEMREVISESTOP_31 ((MDM32P)(MDM_BASE+0x3164)) //apb32 Stop Address of Memory Compare(Revised)
+#define MDM_TM_EXT_MEM_INFO_31 ((MDM32P)(MDM_BASE+0x3168)) // apb32
+ // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
+ // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
+ // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
+ // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
+#define MDM_TM_RUNTIME_USEC_31 ((MDM32P)(MDM_BASE+0x316C)) // apb32
+#define MDM_TM_PHASE_31 ((MDM32P)(MDM_BASE+0x3170)) // apb32 rtl/post
+ // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
+ // [5:4]: {0:none, 1:max, 2:typ, 3:min}
+#define MDM_TM_SIM_OPTION_31 ((MDM32P)(MDM_BASE+0x3174)) // apb32
+ // [0]: PLL enable -> {0:OFF, 1:ON}
+//`define TM_CFSDB_CTRL_31 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
+//`define TM_DMESS_CTRL_31 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
+
+#define MDM_TM_FSDBDUMPFILE_31 ((MDM32P)(MDM_BASE+0x3180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
+#define MDM_TM_FSDBDUMPVARS_31 ((MDM32P)(MDM_BASE+0x3184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
+#define MDM_TM_FSDBDUMP_31 ((MDM32P)(MDM_BASE+0x3188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
+#define MDM_TM_FSDBDUMPSCOPE_31 ((MDM32P)(MDM_BASE+0x318C)) // apb32
+
+#define MDM_TM_STR_CLEAR_31 ((MDM32P)(MDM_BASE+0x3190)) // apb32 clear string ptr
+#define MDM_TM_STR_DISPLAY_31 ((MDM32P)(MDM_BASE+0x3194)) // apb32 display string buf
+#define MDM_TM_STR0_31 ((MDM32P)(MDM_BASE+0x3198)) // apb32 string buffer to be displayed
+#define MDM_TM_STR1_31 ((MDM32P)(MDM_BASE+0x319c)) // apb32 string buffer to be displayed
+#define MDM_TM_STR2_31 ((MDM32P)(MDM_BASE+0x31a0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR3_31 ((MDM32P)(MDM_BASE+0x31a4)) // apb32 string buffer to be displayed
+#define MDM_TM_STR4_31 ((MDM32P)(MDM_BASE+0x31a8)) // apb32 string buffer to be displayed
+#define MDM_TM_STR5_31 ((MDM32P)(MDM_BASE+0x31ac)) // apb32 string buffer to be displayed
+#define MDM_TM_STR6_31 ((MDM32P)(MDM_BASE+0x31b0)) // apb32 string buffer to be displayed
+#define MDM_TM_STR7_31 ((MDM32P)(MDM_BASE+0x31b4)) // apb32 string buffer to be displayed
+
+#define MDM_TRIG_IRQ_31 ((MDM32P)(MDM_BASE+0x31b8)) // apb32 trigger EIRQ
+#define MDM_TRIG_IRQ2_31 ((MDM32P)(MDM_BASE+0x31bC)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG_31 ((MDM32P)(MDM_BASE+0x3178)) // apb32 trigger EIRQ
+#define MDM_WAIT_TRIG2_31 ((MDM32P)(MDM_BASE+0x317C)) // apb32 trigger EIRQ
+
+ // for MDM_cosim purpose, to replace bsi_reg usage
+#define MDM_CORE0VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31C0)) //core 0 to core0
+#define MDM_CORE0VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31C4)) //core 1 to core0
+#define MDM_CORE1VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31C8)) //core 2 to core0
+#define MDM_CORE1VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31CC)) //core 3 to core0
+#define MDM_CORE2VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31D0)) //core 4 to core0
+#define MDM_CORE2VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31D4)) //core 5 to core0
+#define MDM_CORE3VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31D8)) //core 6 to core0
+#define MDM_CORE3VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31DC)) //core 7 to core0
+
+#define MDM_MDM_SIMIF0_CTRL_31 ((MDM32P)(MDM_BASE+0x31E0)) //apb32
+#define MDM_MDM_SIMIF1_CTRL_31 ((MDM32P)(MDM_BASE+0x31E4)) //apb32
+
+#define MDM_TM_FH_CTRL_31 ((MDM32P)(MDM_BASE+0x31E8)) //apb32
+#define MDM_DELAY_31 ((MDM32P)(MDM_BASE+0x31Ec)) //apb32
+#define MDM_RANDOM_DELAY_MIN_31 ((MDM32P)(MDM_BASE+0x31F0)) //apb32
+#define MDM_RANDOM_DELAY_MAX_31 ((MDM32P)(MDM_BASE+0x31F4)) //apb32
+#define MDM_URANDOM_RANGE_MIN_31 ((MDM32P)(MDM_BASE+0x31F8)) //apb32
+#define MDM_URANDOM_RANGE_MAX_31 ((MDM32P)(MDM_BASE+0x31Fc)) //apb32
+
+#endif
+
+#define MIPS_CORE0_TERR_BASE 0x00020001
+#define MIPS_CORE0_TINFO_BASE 0x00020017
+#define MIPS_CORE0_FSDBSCOPE_BASE 0x0002003b
+
+#ifndef __MTK_TARGET__
+static char *terr_msg[] = {
+"data check error read_back_data=%x,golden_data=%x", //0
+"REG_MDCFGCTL_DUMMY miscompare", //1
+"REG_MDGDMA_FDSAR1_DV_DUMMY miscompare", //2
+"REG_MDGPTM_DUMMY miscompare", //3
+"REG_MDPERIMISC_MD_AP_DUMMY miscompare", //4
+"REG_MDPERIMISC_MDINFRA_DUMMY miscompare", //5
+"REG_MDPERIMISC_MDMCU_DUMMY miscompare", //6
+"REG_MDPERIMISC_L1_AP_DUMMY miscompare", //7
+"REG_MDPERIMISC_DUMMY miscompare", //8
+"REG_MDCIRQ_DUMMY miscompare", //9
+"REG_MDOSTIMER_DUMMY0_REG miscompare", //10
+"REG_MDRGU_DUMMY miscompare", //11
+"REG_MDEINT_MD_DUMMY miscompare", //12
+"REG_MDTOP_GLBCON_MD_TOP_DUMMY miscompare", //13
+"REG_MDTOP_PLLMIXED_PLL_DUMMY miscompare", //14
+"REG_MDTOP_CLKSW_CLK_DUMMY miscompare", //15
+"REG_SOE_DUMMY_0 miscompare", //16
+"REG_MDINFRAMISC_DUMMY_REGISTER miscompare", //17
+"REG_L1_IDC_CTRL_IDC_CTRL_DUMMY_ADDR miscompare", //18
+"REG_MDMCU_BUS_CONFIG_MCU_BUS_CONFIG4 miscompare", //19
+"usip slave reg test miscompare", //20
+"rxbrp slave reg test miscompare" //21
+};
+
+static char *tinfo_msg[] = {
+"Hello world, this is IRQ_Proc... ", //0
+"Irq service begin... ", //1
+"Read IRQ_Proc id is %x...", //2
+"Irq service end... ", //3
+"Enter core0_vpe0... with cpu_num %x", //4
+"execute the md_common ...", //5
+"user testcase start ...", //6
+"user testcase end...", //7
+"Enter core0_vpe1... with cpu_num %x", //8
+"Enter core1_vpe0... with cpu_num %x", //9
+"Enter core1_vpe1... with cpu_num %x", //10
+"read&write emi test begin", //11
+"read&write emi test end", //12
+"REG_MDCFGCTL_DUMMY:", //13
+"write data: %x", //14
+"read data: %x", //15
+"REG_MDGDMA_FDSAR1_DV_DUMMY:", //16
+"REG_MDGPTM_DUMMY:", //17
+"REG_MDPERIMISC_MD_AP_DUMMY:", //18
+"REG_MDPERIMISC_MDINFRA_DUMMY:", //19
+"REG_MDPERIMISC_MDMCU_DUMMY:", //20
+"REG_MDPERIMISC_L1_AP_DUMMY:", //21
+"REG_MDPERIMISC_DUMMY:", //22
+"REG_MDCIRQ_DUMMY:", //23
+"REG_MDOSTIMER_DUMMY0_REG:", //24
+"REG_MDRGU_DUMMY:", //25
+"REG_MDEINT_MD_DUMMY:", //26
+"REG_MDTOP_GLBCON_MD_TOP_DUMMY:", //27
+"REG_MDTOP_PLLMIXED_PLL_DUMMY:", //28
+"REG_MDTOP_CLKSW_CLK_DUMMY:", //29
+"REG_SOE_DUMMY_0:", //30
+"REG_MDINFRAMISC_DUMMY_REGISTER:", //31
+"REG_L1_IDC_CTRL_IDC_CTRL_DUMMY_ADDR:", //32
+"REG_MDMCU_BUS_CONFIG_MCU_BUS_CONFIG4:", //33
+"usip slave test:", //34
+"rxbrp slave test:" //35
+};
+#endif
+
+
+#define FATAL_ERROR_MAGIC 0x4C544146 //ASCII code FATL
+#define ASSERT_ERROR_MAGIC 0x54525341 //ASCII code ASRT
+#define VPE_HEADER_MAGIC 0xFF000000 //VPE number
+#define EXCEPTION_ERROR_MAGIC 0x50435845 //ASCII code EXCP
+#define MDM_APP_INIT_MAGIC 0x30504100
+
+#if !defined(__COSIM_BYPASS_DRV__)
+
+#define MDM_INT32_WRITE(int32_log)
+#define MDM_TMMEMDUMP_STR_WRITE(int32_log)
+#define MDM_TMMEMDUMP_STOP_WRITE(int32_log)
+#define MDM_TM_END_FAIL_WRITE
+#define MDM_TM_END_SUCC_WRITE
+#define MDM_STR0_WRITE(char_write)
+#define MDM_TM_STR_CLEAR_WRITE(clear_buffer_num)
+#define MDM_TM_STR_DISPLAY_WRITE(display_buffer_num)
+
+#else
+
+// Check these macro defines are the same for MT6763 Cosim?
+#define MDM_TM_HEXFMT_32B MDM_TM_HEXFMT32B
+
+extern void MDM_ASSERT(kal_uint32 e1, kal_uint32 e2, kal_uint32 e3);
+extern void MDM_kal_fatal_error_handler(kal_uint32 code1, kal_uint32 code2);
+
+#define MDM_INT32_WRITE(int32_log) \
+do { \
+ (*MDM_TM_HEXFMT32B)=(kal_uint32)VPE_HEADER_MAGIC|kal_get_current_vpe_id(); \
+ (*MDM_TM_HEXFMT32B)=(kal_uint32)(int32_log); \
+} while(0)
+
+#define MDM_TMMEMDUMP_STR_WRITE(int32_log)
+#define MDM_TMMEMDUMP_STOP_WRITE(int32_log)
+#define MDM_TM_END_FAIL_WRITE (*MDM_TM_ENDFAIL=0);
+#define MDM_TM_END_SUCC_WRITE (*MDM_TM_ENDSUCC=0);
+#define MDM_STR0_WRITE(char_write) (*MDM_TM_STR0 = (unsigned int)(char_write))
+#define MDM_TM_STR_CLEAR_WRITE(clear_buffer_num) (*MDM_TM_STR_CLEAR = (unsigned int)(clear_buffer_num))
+#define MDM_TM_STR_DISPLAY_WRITE(display_buffer_num) (*MDM_TM_STR_DISPLAY = (unsigned int)(display_buffer_num))
+
+#endif
+
+#endif //_MDM_TRACE_H
+
diff --git a/mcu/interface/driver/sys_drv/mips_ia_utils_public.h b/mcu/interface/driver/sys_drv/mips_ia_utils_public.h
new file mode 100644
index 0000000..fa6eafe
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mips_ia_utils_public.h
@@ -0,0 +1,987 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ * Public header for some MIPS iA/I7200 utils
+ *****************************************************************************/
+
+#ifndef __MIPS_IA_UTILS_PUBLIC_H__
+#define __MIPS_IA_UTILS_PUBLIC_H__
+
+/* First undefine all config option, them config by project */
+#undef CONFIG_MIPS_IA_MR2
+#undef CONFIG_MIPS_IA_MR3
+#undef CONFIG_MIPS_I7200
+#undef CONFIG_MIPS_I7200_RELEASE_1_5
+#undef CONFIG_MIPS_I7200_RELEASE_1_6
+#undef CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS
+#undef CONFIG_EHB_FOR_DMT_DVPE_HAZARD
+#undef CONFIG_MIPS_IA_DISABLE_BUSSLP
+#undef CONFIG_MIPS_IA_MR3_LOWER_IDLE_WAIT_GRP_FOR_RPS
+
+#if defined(MT6763) || defined(MT6739) || defined(MT6771) || defined(MT6765)
+# define CONFIG_MIPS_IA_MR2
+#elif defined(MT6295M) || defined(MT3967) || defined(MT6779) || defined(MT6785)
+# define CONFIG_MIPS_IA_MR3
+#elif defined(__MD93__)
+# define CONFIG_MIPS_IA_MR2
+#elif defined(__MD95__)
+# define CONFIG_MIPS_IA_MR3
+#elif defined(__MD97__)
+# define CONFIG_MIPS_I7200
+# define CONFIG_MIPS_I7200_RELEASE_1_5
+#elif defined(__MD97P__)
+# define CONFIG_MIPS_I7200
+# define CONFIG_MIPS_I7200_RELEASE_1_6
+#endif
+
+#if defined(CONFIG_MIPS_IA_MR2)
+# define CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS
+# define CONFIG_EHB_FOR_DMT_DVPE_HAZARD
+# define CONFIG_MIPS_IA_DISABLE_BUSSLP
+#elif defined(CONFIG_MIPS_IA_MR3)
+# undef CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS
+# define CONFIG_EHB_FOR_DMT_DVPE_HAZARD
+// disable it since it (E52.a) has been fixed in 1.4b
+# undef CONFIG_MIPS_IA_DISABLE_BUSSLP
+#elif defined(CONFIG_MIPS_I7200)
+# define CONFIG_EHB_FOR_DMT_DVPE_HAZARD
+#endif
+
+
+#if defined(__MIPS_I7200__) && !defined(__MIPS_I7200_CP0_DEF_H__)
+#define __MIPS_I7200_CP0_DEF_H__
+
+/*
+ * C0 register definition from MD00904, Rev 01.04
+ * MIPS32 Coprocessor 0 register "$numbers,select"
+ */
+#define MIU_C0_INDEX " $0,0"
+#define MIU_C0_MVPCONTROL " $0,1"
+#define MIU_C0_MVPCONF0 " $0,2"
+#define MIU_C0_MVPCONF1 " $0,3"
+#define MIU_C0_VPECONTROL " $1,1"
+#define MIU_C0_VPECONF0 " $1,2"
+#define MIU_C0_VPECONF1 " $1,3"
+#define MIU_C0_YQMASK " $1,4"
+#define MIU_C0_VPEOPT " $1,7"
+#define MIU_C0_ENTRYLO0 " $2,0"
+#define MIU_C0_TCSTATUS " $2,1"
+#define MIU_C0_TCBIND " $2,2"
+#define MIU_C0_TCRESTART " $2,3"
+#define MIU_C0_TCHALT " $2,4"
+#define MIU_C0_TCCONTEXT " $2,5"
+#define MIU_C0_TCSCHEDULE " $2,6"
+#define MIU_C0_ENTRYLO1 " $3,0"
+#define MIU_C0_CONTEXT " $4,0"
+#define MIU_C0_CONTEXTCONFIG " $4,1"
+#define MIU_C0_USERLOCAL " $4,2"
+#define MIU_C0_PAGEMASK " $5,0"
+#define MIU_C0_SEGCTL0 " $5,2"
+#define MIU_C0_SEGCTL1 " $5,3"
+#define MIU_C0_SEGCTL2 " $5,4"
+#define MIU_C0_WIRED " $6,0"
+#define MIU_C0_SRSCONF0 " $6,1"
+#define MIU_C0_HWRENA " $7,0"
+#define MIU_C0_BADVADDR " $8,0"
+#define MIU_C0_BADINSTR " $8,1"
+#define MIU_C0_BADINSTRX " $8,3"
+#define MIU_C0_COUNT " $9,0"
+#define MIU_C0_ENTRYHI "$10,0"
+#define MIU_C0_COMPARE "$11,0"
+#define MIU_C0_STATUS "$12,0"
+#define MIU_C0_INTCTL "$12,1"
+#define MIU_C0_SRSCTL "$12,2"
+#define MIU_C0_SRSMAP "$12,3"
+#define MIU_C0_CAUSE "$13,0"
+#define MIU_C0_EPC "$14,0"
+#define MIU_C0_PRID "$15,0"
+#define MIU_C0_EBASE "$15,1"
+#define MIU_C0_CDMMBASE "$15,2"
+#define MIU_C0_CMGCR "$15,3"
+#define MIU_C0_BEVVA "$15,4"
+#define MIU_C0_CONFIG "$16,0"
+#define MIU_C0_CONFIG1 "$16,1"
+#define MIU_C0_CONFIG2 "$16,2"
+#define MIU_C0_CONFIG3 "$16,3"
+#define MIU_C0_CONFIG4 "$16,4"
+#define MIU_C0_CONFIG5 "$16,5"
+#define MIU_C0_CONFIG7 "$16,7"
+#define MIU_C0_LLADDR "$17,0"
+#define MIU_C0_WATCHLO0 "$18,0"
+#define MIU_C0_WATCHLO1 "$18,1"
+#define MIU_C0_WATCHLO2 "$18,2"
+#define MIU_C0_WATCHLO3 "$18,3"
+#define MIU_C0_WATCHLO4 "$18,4"
+#define MIU_C0_WATCHLO5 "$18,5"
+#define MIU_C0_WATCHLO6 "$18,6"
+#define MIU_C0_WATCHLO7 "$18,7"
+#define MIU_C0_WATCHHI0 "$19,0"
+#define MIU_C0_WATCHHI1 "$19,1"
+#define MIU_C0_WATCHHI2 "$19,2"
+#define MIU_C0_WATCHHI3 "$19,3"
+#define MIU_C0_WATCHHI4 "$19,4"
+#define MIU_C0_WATCHHI5 "$19,5"
+#define MIU_C0_WATCHHI6 "$19,6"
+#define MIU_C0_WATCHHI7 "$19,7"
+#define MIU_C0_BATCHCACHEOPCONTROL "$22,0"
+#define MIU_C0_BATCHCACHEOPSTATUS "$22,1"
+#define MIU_C0_CORECONTROL "$22,3"
+#define MIU_C0_DEBUG "$23,0"
+#define MIU_C0_TRACECONTROL "$23,1"
+#define MIU_C0_TRACECONTROL2 "$23,2"
+#define MIU_C0_USERTRACEDATA1 "$23,3"
+#define MIU_C0_TRACEIBPC "$23,4"
+#define MIU_C0_TRACEDBPC "$23,5"
+#define MIU_C0_DEPC "$24,0"
+#define MIU_C0_TRACECONTROL3 "$24,2"
+#define MIU_C0_USERTRACEDATA2 "$24,3"
+#define MIU_C0_PERFCTL0 "$25,0"
+#define MIU_C0_PERFCNT0 "$25,1"
+#define MIU_C0_PERFCTL1 "$25,2"
+#define MIU_C0_PERFCNT1 "$25,3"
+#define MIU_C0_PERFCTL2 "$25,4"
+#define MIU_C0_PERFCNT2 "$25,5"
+#define MIU_C0_PERFCTL3 "$25,6"
+#define MIU_C0_PERFCNT3 "$25,7"
+#define MIU_C0_ERRCTL "$26,0"
+#define MIU_C0_CACHEERR "$27,0"
+#define MIU_C0_ITAGLO "$28,0"
+#define MIU_C0_IDATALO "$28,1"
+#define MIU_C0_DTAGLO "$28,2"
+#define MIU_C0_DDATALO "$28,3"
+
+#define MIU_C0_IDATAHI "$29,1"
+#define MIU_C0_DTAGHI "$29,2"
+
+#define MIU_C0_ERROREPC "$30,0"
+#define MIU_C0_DESAVE "$31,0"
+#define MIU_C0_KSCRATCH1 "$31,2"
+#define MIU_C0_KSCRATCH2 "$31,3"
+#define MIU_C0_KSCRATCH3 "$31,4"
+#define MIU_C0_KSCRATCH4 "$31,5"
+#define MIU_C0_KSCRATCH5 "$31,6"
+#define MIU_C0_KSCRATCH6 "$31,7"
+
+/* Alias */
+#define MIU_C0_BCOCTL MIU_C0_BATCHCACHEOPCONTROL
+#define MIU_C0_BCOSTA MIU_C0_BATCHCACHEOPSTATUS
+
+#define MIU_RDHWR_CPUNUM "$0"
+
+/* C0_MVPCONTROL ($0, 1) */
+#define MIU_C0_MVPCONTROL_EVP_BITFIELD_BEG ( 0)
+#define MIU_C0_MVPCONTROL_EVP_BITFIELD_END ( 0)
+#define MIU_C0_MVPCONTROL_VPC_BITFIELD_BEG ( 1)
+#define MIU_C0_MVPCONTROL_VPC_BITFIELD_END ( 1)
+#define MIU_C0_MVPCONTROL_STLB_BITFIELD_BEG ( 2)
+#define MIU_C0_MVPCONTROL_STLB_BITFIELD_END ( 2)
+#define MIU_C0_MVPCONTROL_POLICY_MODE_BITFIELD_BEG (16)
+#define MIU_C0_MVPCONTROL_POLICY_MODE_BITFIELD_END (16)
+#if defined(CONFIG_MIPS_I7200_RELEASE_1_6)
+#define MIU_C0_MVPCONTROL_QSE_BITFIELD_BEG (17)
+#define MIU_C0_MVPCONTROL_QSE_BITFIELD_END (17)
+#endif /* defined(CONFIG_MIPS_I7200_RELEASE_1_6) */
+
+/* C0_VPECONTROL ($1, 1) */
+#define MIU_C0_VPECONTROL_TARGTC_BITFIELD_BEG ( 0)
+#define MIU_C0_VPECONTROL_TARGTC_BITFIELD_END ( 7)
+#define MIU_C0_VPECONTROL_TE_BITFIELD_BEG (15)
+#define MIU_C0_VPECONTROL_TE_BITFIELD_END (15)
+#define MIU_C0_VPECONTROL_EXCPT_BITFIELD_BEG (16)
+#define MIU_C0_VPECONTROL_EXCPT_BITFIELD_END (18)
+#define MIU_C0_VPECONTROL_GSI_BITFIELD_BEG (20)
+#define MIU_C0_VPECONTROL_GSI_BITFIELD_END (20)
+#define MIU_C0_VPECONTROL_YSI_BITFIELD_BEG (21)
+#define MIU_C0_VPECONTROL_YSI_BITFIELD_END (21)
+
+/* C0_TCBIND ($2, 2) */
+#define MIU_C0_TCBIND_CURVPE_BITFIELD_BEG ( 0)
+#define MIU_C0_TCBIND_CURVPE_BITFIELD_END ( 3)
+#define MIU_C0_TCBIND_TBE_BITFIELD_BEG (17)
+#define MIU_C0_TCBIND_TBE_BITFIELD_END (17)
+#define MIU_C0_TCBIND_CURTC_BITFIELD_BEG (21)
+#define MIU_C0_TCBIND_CURTC_BITFIELD_END (28)
+
+/* C0_PERFCTL $(25, 0; $25, 2; $25, 4; $25, 6) */
+#define MIU_C0_PERFCTL_EXL_BITFIELD_BEG ( 0)
+#define MIU_C0_PERFCTL_EXL_BITFIELD_END ( 0)
+#define MIU_C0_PERFCTL_K_BITFIELD_BEG ( 1)
+#define MIU_C0_PERFCTL_K_BITFIELD_END ( 1)
+#define MIU_C0_PERFCTL_S_BITFIELD_BEG ( 2)
+#define MIU_C0_PERFCTL_S_BITFIELD_END ( 2)
+#define MIU_C0_PERFCTL_U_BITFIELD_BEG ( 3)
+#define MIU_C0_PERFCTL_U_BITFIELD_END ( 3)
+#define MIU_C0_PERFCTL_IE_BITFIELD_BEG ( 4)
+#define MIU_C0_PERFCTL_IE_BITFIELD_END ( 4)
+#define MIU_C0_PERFCTL_EVENT_BITFIELD_BEG ( 5)
+#define MIU_C0_PERFCTL_EVENT_BITFIELD_END (14)
+#define MIU_C0_PERFCTL_PCTD_BITFIELD_BEG (15)
+#define MIU_C0_PERFCTL_PCTD_BITFIELD_END (15)
+#define MIU_C0_PERFCTL_MTEID_BITFIELD_BEG (25)
+#define MIU_C0_PERFCTL_MTEID_BITFIELD_END (29)
+#define MIU_C0_PERFCTL_M_BITFIELD_BEG (31)
+#define MIU_C0_PERFCTL_M_BITFIELD_END (31)
+#define MIU_C0_PERFCTL_CONTEXT_BITFIELD_BEG (MIU_C0_PERFCTL_EXL_BITFIELD_BEG)
+#define MIU_C0_PERFCTL_CONTEXT_BITFIELD_END (MIU_C0_PERFCTL_IE_BITFIELD_END)
+
+/* FIXME: workaround to build pass */
+#define MIU_C0_PERFCTL_VPEID_BITFIELD_BEG ( 0)
+#define MIU_C0_PERFCTL_VPEID_BITFIELD_END ( 0)
+#define MIU_C0_PERFCTL_MT_EN_BITFIELD_BEG ( 0)
+#define MIU_C0_PERFCTL_MT_EN_BITFIELD_END ( 0)
+#define MIU_C0_PERFCTL_TCID_BITFIELD_BEG ( 0)
+#define MIU_C0_PERFCTL_TCID_BITFIELD_END ( 0)
+
+#define MIU_PERFCNT_M (0x80000000)
+#define MIU_PERFCNT_EVENT_MASK (0x000007e0)
+#define MIU_PERFCNT_EVENTMASK (0x000007e0)
+#define MIU_PERFCNT_EVENT_SHIFT ( 5)
+#define MIU_PERFCNT_EVENTSHIFT ( 5)
+#define MIU_PERFCNT_EVENT_BITS ( 6)
+#define MIU_PERFCNT_IE (0x00000010)
+#define MIU_PERFCNT_U (0x00000008)
+#define MIU_PERFCNT_S (0x00000004)
+#define MIU_PERFCNT_K (0x00000002)
+#define MIU_PERFCNT_EXL (0x00000001)
+
+/* C0_TCSCHEDULE ($2, 6) */
+#define MIU_C0_TCSCHEDULE_TCHALT_EN_BITFIELD_BEG ( 0)
+#define MIU_C0_TCSCHEDULE_TCHALT_EN_BITFIELD_END ( 0)
+#define MIU_C0_TCSCHEDULE_PRIO_EN_BITFIELD_BEG ( 1)
+#define MIU_C0_TCSCHEDULE_PRIO_EN_BITFIELD_END ( 1)
+#define MIU_C0_TCSCHEDULE_PRIO_BITFIELD_BEG ( 2)
+#define MIU_C0_TCSCHEDULE_PRIO_BITFIELD_END ( 3)
+
+/* C0_PRID ($15, 0) */
+#define MIU_C0_PRID_COOPT_BITFIELD_END (31)
+#define MIU_C0_PRID_COOPT_BITFIELD_BEG (24)
+#define MIU_C0_PRID_COID_BITFIELD_END (23)
+#define MIU_C0_PRID_COID_BITFIELD_BEG (16)
+#define MIU_C0_PRID_PROCTYPE_BITFIELD_END (15)
+#define MIU_C0_PRID_PROCTYPE_BITFIELD_BEG ( 8)
+#define MIU_C0_PRID_REV_BITFIELD_END ( 7)
+#define MIU_C0_PRID_REV_BITFIELD_BEG ( 0)
+#define MIU_C0_PRID_REV_MAJOR_BITFIELD_END ( 7)
+#define MIU_C0_PRID_REV_MAJOR_BITFIELD_BEG ( 5)
+#define MIU_C0_PRID_REV_MINOR_BITFIELD_END ( 4)
+#define MIU_C0_PRID_REV_MINOR_BITFIELD_BEG ( 2)
+#define MIU_C0_PRID_REV_PATCH_LV_BITFIELD_END ( 1)
+#define MIU_C0_PRID_REV_PATCH_LV_BITFIELD_BEG ( 0)
+
+/* C0_EBASE ($15, 1) */
+/* [TC] EBase use bit 0:9 in definition,
+ * but we only need 4 bit (max to 8 vpe/4 core, bit 0:3) */
+#define MIU_C0_EBASE_CPUNUM_BITFIELD_BEG ( 0)
+#define MIU_C0_EBASE_CPUNUM_BITFIELD_END ( 3)
+#define MIU_C0_EBASE_WG_BITFIELD_BEG (11)
+#define MIU_C0_EBASE_WG_BITFIELD_END (11)
+#define MIU_C0_EBASE_EXCBASE_BITFIELD_BEG (12)
+#define MIU_C0_EBASE_EXCBASE_BITFIELD_END (31)
+
+/* C0_CONFIG7 ($16, 7) */
+#define MIU_C0_CONFIG7_RPS_BITFIELD_BEG (2 )
+#define MIU_C0_CONFIG7_RPS_BITFIELD_END (2 )
+#define MIU_C0_CONFIG7_NBLSU_BITFIELD_BEG (5 )
+#define MIU_C0_CONFIG7_NBLSU_BITFIELD_END (5 )
+#define MIU_C0_CONFIG7_BTLM_BITFIELD_BEG (7 )
+#define MIU_C0_CONFIG7_BTLM_BITFIELD_END (7 )
+#define MIU_C0_CONFIG7_ES_BITFIELD_BEG (8 )
+#define MIU_C0_CONFIG7_ES_BITFIELD_END (8 )
+#define MIU_C0_CONFIG7_IVAD_BITFIELD_BEG (9 )
+#define MIU_C0_CONFIG7_IVAD_BITFIELD_END (9 )
+#define MIU_C0_CONFIG7_IAR_BITFIELD_BEG (10)
+#define MIU_C0_CONFIG7_IAR_BITFIELD_END (10)
+#define MIU_C0_CONFIG7_BUSSLP_BITFIELD_BEG (11)
+#define MIU_C0_CONFIG7_BUSSLP_BITFIELD_END (11)
+#define MIU_C0_CONFIG7_USP_BITFIELD_BEG (14)
+#define MIU_C0_CONFIG7_USP_BITFIELD_END (14)
+#define MIU_C0_CONFIG7_PCEN_BITFIELD_BEG (15)
+#define MIU_C0_CONFIG7_PCEN_BITFIELD_END (15)
+#define MIU_C0_CONFIG7_AR_BITFIELD_BEG (16)
+#define MIU_C0_CONFIG7_AR_BITFIELD_END (16)
+#define MIU_C0_CONFIG7_HCI_BITFIELD_BEG (18)
+#define MIU_C0_CONFIG7_HCI_BITFIELD_END (18)
+#define MIU_C0_CONFIG7_PCT_BITFIELD_BEG (19)
+#define MIU_C0_CONFIG7_PCT_BITFIELD_END (19)
+#define MIU_C0_CONFIG7_RAMSLP_BITFIELD_BEG (21)
+#define MIU_C0_CONFIG7_RAMSLP_BITFIELD_END (21)
+#define MIU_C0_CONFIG7_WII_BITFIELD_BEG (31)
+#define MIU_C0_CONFIG7_WII_BITFIELD_END (31)
+
+/* C0_ERRCTL ($26, 0) */
+#define MIU_C0_ERRCTL_PD_BITFIELD_BEG ( 0)
+#define MIU_C0_ERRCTL_PD_BITFIELD_END ( 3)
+#define MIU_C0_ERRCTL_PI_BITFIELD_BEG ( 4)
+#define MIU_C0_ERRCTL_PI_BITFIELD_END (11)
+#define MIU_C0_ERRCTL_FE_BITFIELD_BEG (19)
+#define MIU_C0_ERRCTL_FE_BITFIELD_END (19)
+#define MIU_C0_ERRCTL_SE_BITFIELD_BEG (20)
+#define MIU_C0_ERRCTL_SE_BITFIELD_END (20)
+#define MIU_C0_ERRCTL_L1ECC_BITFIELD_BEG (22)
+#define MIU_C0_ERRCTL_L1ECC_BITFIELD_END (22)
+#define MIU_C0_ERRCTL_WABE_BITFIELD_BEG (24)
+#define MIU_C0_ERRCTL_WABE_BITFIELD_END (24)
+#define MIU_C0_ERRCTL_LBE_BITFIELD_BEG (25)
+#define MIU_C0_ERRCTL_LBE_BITFIELD_END (25)
+#define MIU_C0_ERRCTL_ITC_BITFIELD_BEG (26)
+#define MIU_C0_ERRCTL_ITC_BITFIELD_END (26)
+#define MIU_C0_ERRCTL_SPR_BITFIELD_BEG (28)
+#define MIU_C0_ERRCTL_SPR_BITFIELD_END (28)
+#define MIU_C0_ERRCTL_WST_BITFIELD_BEG (29)
+#define MIU_C0_ERRCTL_WST_BITFIELD_END (29)
+#define MIU_C0_ERRCTL_PO_BITFIELD_BEG (30)
+#define MIU_C0_ERRCTL_PO_BITFIELD_END (30)
+#define MIU_C0_ERRCTL_PE_BITFIELD_BEG (31)
+#define MIU_C0_ERRCTL_PE_BITFIELD_END (31)
+
+/* C0_CORECONTROL ($22, 3) */
+#define MIU_C0_CORECONTROL_DSP_EN_BITFIELD_BEG ( 0)
+#define MIU_C0_CORECONTROL_DSP_EN_BITFIELD_END ( 0)
+#define MIU_C0_CORECONTROL_ISP_EN_BITFIELD_BEG ( 1)
+#define MIU_C0_CORECONTROL_ISP_EN_BITFIELD_END ( 1)
+#define MIU_C0_CORECONTROL_USPDPB_DIS_BITFIELD_BEG ( 5)
+#define MIU_C0_CORECONTROL_USPDPB_DIS_BITFIELD_END ( 5)
+#define MIU_C0_CORECONTROL_USPIPRED_DIS_BITFIELD_BEG ( 6)
+#define MIU_C0_CORECONTROL_USPIPRED_DIS_BITFIELD_END ( 6)
+#define MIU_C0_CORECONTROL_ISPIPRED_DIS_BITFIELD_BEG ( 7)
+#define MIU_C0_CORECONTROL_ISPIPRED_DIS_BITFIELD_END ( 7)
+#if defined(CONFIG_MIPS_I7200_RELEASE_1_6)
+#define MIU_C0_CORECONTROL_QOSLOCK_BITFIELD_BEG ( 3)
+#define MIU_C0_CORECONTROL_QOSLOCK_BITFIELD_END ( 3)
+#define MIU_C0_CORECONTROL_LITETRACE_EN_BITFIELD_BEG ( 8)
+#define MIU_C0_CORECONTROL_LITETRACE_EN_BITFIELD_END ( 8)
+/* Alias */
+#define MIU_C0_CORECONTROL_QOS_RR_ECO_BITFIELD_BEG (MIU_C0_CORECONTROL_QOSLOCK_BITFIELD_BEG)
+#define MIU_C0_CORECONTROL_QOS_RR_ECO_BITFIELD_END (MIU_C0_CORECONTROL_QOSLOCK_BITFIELD_END)
+#else /* CONFIG_MIPS_I7200_RELEASE_1_5 or earlier */
+#define MIU_C0_CORECONTROL_WPB_EN_BITFIELD_BEG ( 3)
+#define MIU_C0_CORECONTROL_WPB_EN_BITFIELD_END ( 3)
+/* Alias */
+#define MIU_C0_CORECONTROL_QOS_RR_ECO_BITFIELD_BEG (MIU_C0_CORECONTROL_WPB_EN_BITFIELD_BEG)
+#define MIU_C0_CORECONTROL_QOS_RR_ECO_BITFIELD_END (MIU_C0_CORECONTROL_WPB_EN_BITFIELD_END)
+#endif /* defined(CONFIG_MIPS_I7200_RELEASE_1_6) */
+
+
+#endif /* defined(__MIPS_I7200__) && !defined(__MIPS_I7200_CP0_DEF_H__) */
+
+#if defined(__MIPS_IA__) && !defined(__MIPS_IA_CP0_DEF_H__)
+#define __MIPS_IA_CP0_DEF_H__
+
+/*
+ * C0 register definition from MD00904, Rev 01.04
+ * MIPS32 Coprocessor 0 register "$numbers,select"
+ */
+#define MIU_C0_INDEX " $0,0"
+#define MIU_C0_MVPCONTROL " $0,1"
+#define MIU_C0_MVPCONF0 " $0,2"
+#define MIU_C0_MVPCONF1 " $0,3"
+#define MIU_C0_RANDOM " $1,0"
+#define MIU_C0_VPECONTROL " $1,1"
+#define MIU_C0_VPECONF0 " $1,2"
+#define MIU_C0_VPECONF1 " $1,3"
+#define MIU_C0_YQMASK " $1,4"
+#define MIU_C0_VPESCHEDULE " $1,5"
+#define MIU_C0_VPESCHEFBACK " $1,6"
+#define MIU_C0_VPEOPT " $1,7"
+#define MIU_C0_ENTRYLO0 " $2,0"
+#define MIU_C0_TCSTATUS " $2,1"
+#define MIU_C0_TCBIND " $2,2"
+#define MIU_C0_TCRESTART " $2,3"
+#define MIU_C0_TCHALT " $2,4"
+#define MIU_C0_TCCONTEXT " $2,5"
+#define MIU_C0_TCSCHEDULE " $2,6"
+#define MIU_C0_TCSCHEFBACK " $2,7"
+#define MIU_C0_ENTRYLO1 " $3,0"
+#define MIU_C0_TCOPT " $3,7"
+#define MIU_C0_CONTEXT " $4,0"
+#define MIU_C0_CONTEXTCONFIG " $4,1"
+#define MIU_C0_USERLOCAL " $4,2"
+#define MIU_C0_PAGEMASK " $5,0"
+#define MIU_C0_PAGEGRAIN " $5,1"
+#define MIU_C0_SEGCTL0 " $5,2"
+#define MIU_C0_SEGCTL1 " $5,3"
+#define MIU_C0_SEGCTL2 " $5,4"
+#define MIU_C0_WIRED " $6,0"
+#define MIU_C0_SRSCONF0 " $6,1"
+#define MIU_C0_SRSCONF1 " $6,2"
+#define MIU_C0_SRSCONF2 " $6,3"
+#define MIU_C0_SRSCONF3 " $6,4"
+#define MIU_C0_SRSCONF4 " $6,5"
+#define MIU_C0_HWRENA " $7,0"
+#define MIU_C0_BADVADDR " $8,0"
+#define MIU_C0_COUNT " $9,0"
+#define MIU_C0_ENTRYHI "$10,0"
+#define MIU_C0_COMPARE "$11,0"
+#define MIU_C0_STATUS "$12,0"
+#define MIU_C0_INTCTL "$12,1"
+#define MIU_C0_SRSCTL "$12,2"
+#define MIU_C0_SRSMAP "$12,3"
+#define MIU_C0_CAUSE "$13,0"
+#define MIU_C0_EPC "$14,0"
+#define MIU_C0_PRID "$15,0"
+#define MIU_C0_EBASE "$15,1"
+#define MIU_C0_CDMMBASE "$15,2"
+#define MIU_C0_CMGCR "$15,3"
+#define MIU_C0_CONFIG "$16,0"
+#define MIU_C0_CONFIG1 "$16,1"
+#define MIU_C0_CONFIG2 "$16,2"
+#define MIU_C0_CONFIG3 "$16,3"
+#define MIU_C0_CONFIG4 "$16,4"
+#define MIU_C0_CONFIG5 "$16,5"
+#define MIU_C0_CONFIG7 "$16,7"
+#define MIU_C0_LLADDR "$17,0"
+#define MIU_C0_WATCHLO0 "$18,0"
+#define MIU_C0_WATCHLO1 "$18,1"
+#define MIU_C0_WATCHLO2 "$18,2"
+#define MIU_C0_WATCHLO3 "$18,3"
+#define MIU_C0_WATCHHI0 "$19,0"
+#define MIU_C0_WATCHHI1 "$19,1"
+#define MIU_C0_WATCHHI2 "$19,2"
+#define MIU_C0_WATCHHI3 "$19,3"
+#define MIU_C0_DEBUG "$23,0"
+#define MIU_C0_TRACECONTROL "$23,1"
+#define MIU_C0_TRACECONTROL2 "$23,2"
+#define MIU_C0_USERTRACEDATA1 "$23,3"
+#define MIU_C0_TRACEIBPC "$23,4"
+#define MIU_C0_TRACEDBPC "$23,5"
+#define MIU_C0_DEPC "$24,0"
+#define MIU_C0_TRACECONTROL3 "$24,2"
+#define MIU_C0_USERTRACEDATA2 "$24,3"
+#define MIU_C0_PERFCTL0 "$25,0"
+#define MIU_C0_PERFCNT0 "$25,1"
+#define MIU_C0_PERFCTL1 "$25,2"
+#define MIU_C0_PERFCNT1 "$25,3"
+#define MIU_C0_ERRCTL "$26,0"
+#define MIU_C0_CACHEERR "$27,0"
+#define MIU_C0_ITAGLO "$28,0"
+#define MIU_C0_IDATALO "$28,1"
+#define MIU_C0_DTAGLO "$28,2"
+#define MIU_C0_DDATALO "$28,3"
+#define MIU_C0_L23TAGLO "$28,4"
+#define MIU_C0_L23DATALO "$28,5"
+#define MIU_C0_IDATAHI "$29,1"
+#define MIU_C0_DTAGHI "$29,2"
+#define MIU_C0_L23DATAHI "$29,5"
+#define MIU_C0_ERROREPC "$30,0"
+#define MIU_C0_DESAVE "$31,0"
+#define MIU_C0_KSCRATCH1 "$31,2"
+#define MIU_C0_KSCRATCH2 "$31,3"
+#define MIU_C0_KSCRATCH3 "$31,4"
+
+#define MIU_RDHWR_CPUNUM "$0"
+
+/* MIPS32 PerfCnt Register (CP0 Register 25) */
+/* TODO: clean it up */
+#define MIU_PERFCNT_M (0x80000000)
+#define MIU_PERFCNT_EVENT_MASK (0x000007e0)
+#define MIU_PERFCNT_EVENTMASK (0x000007e0)
+#define MIU_PERFCNT_EVENT_SHIFT ( 5)
+#define MIU_PERFCNT_EVENTSHIFT ( 5)
+#define MIU_PERFCNT_EVENT_BITS ( 6)
+#define MIU_PERFCNT_IE (0x00000010)
+#define MIU_PERFCNT_U (0x00000008)
+#define MIU_PERFCNT_S (0x00000004)
+#define MIU_PERFCNT_K (0x00000002)
+#define MIU_PERFCNT_EXL (0x00000001)
+
+/* C0_MVPCONTROL */
+#define MIU_C0_MVPCONTROL_EVP_BITFIELD_BEG ( 0)
+#define MIU_C0_MVPCONTROL_EVP_BITFIELD_END ( 0)
+#define MIU_C0_MVPCONTROL_VPC_BITFIELD_BEG ( 1)
+#define MIU_C0_MVPCONTROL_VPC_BITFIELD_END ( 1)
+#define MIU_C0_MVPCONTROL_STLB_BITFIELD_BEG ( 2)
+#define MIU_C0_MVPCONTROL_STLB_BITFIELD_END ( 2)
+#define MIU_C0_MVPCONTROL_CPA_BITFIELD_BEG ( 3)
+#define MIU_C0_MVPCONTROL_CPA_BITFIELD_END ( 3)
+#define MIU_C0_MVPCONTROL_TPP_BITFIELD_BEG (16)
+#define MIU_C0_MVPCONTROL_TPP_BITFIELD_END (16)
+
+/* C0_VPECONTROL */
+#define MIU_C0_VPECONTROL_TARGTC_BITFIELD_BEG ( 0)
+#define MIU_C0_VPECONTROL_TARGTC_BITFIELD_END ( 7)
+#define MIU_C0_VPECONTROL_TE_BITFIELD_BEG (15)
+#define MIU_C0_VPECONTROL_TE_BITFIELD_END (15)
+#define MIU_C0_VPECONTROL_EXCPT_BITFIELD_BEG (16)
+#define MIU_C0_VPECONTROL_EXCPT_BITFIELD_END (18)
+#define MIU_C0_VPECONTROL_GSI_BITFIELD_BEG (20)
+#define MIU_C0_VPECONTROL_GSI_BITFIELD_END (20)
+#define MIU_C0_VPECONTROL_YSI_BITFIELD_BEG (21)
+#define MIU_C0_VPECONTROL_YSI_BITFIELD_END (21)
+
+/* C0_TCBIND */
+#define MIU_C0_TCBIND_CURVPE_BITFIELD_BEG ( 0)
+#define MIU_C0_TCBIND_CURVPE_BITFIELD_END ( 3)
+#define MIU_C0_TCBIND_TBE_BITFIELD_BEG (17)
+#define MIU_C0_TCBIND_TBE_BITFIELD_END (17)
+#define MIU_C0_TCBIND_CURTC_BITFIELD_BEG (21)
+#define MIU_C0_TCBIND_CURTC_BITFIELD_END (28)
+
+/* C0_PERFCTL */
+#define MIU_C0_PERFCTL_EXL_BITFIELD_BEG ( 0)
+#define MIU_C0_PERFCTL_EXL_BITFIELD_END ( 0)
+#define MIU_C0_PERFCTL_K_BITFIELD_BEG ( 1)
+#define MIU_C0_PERFCTL_K_BITFIELD_END ( 1)
+#define MIU_C0_PERFCTL_S_BITFIELD_BEG ( 2)
+#define MIU_C0_PERFCTL_S_BITFIELD_END ( 2)
+#define MIU_C0_PERFCTL_U_BITFIELD_BEG ( 3)
+#define MIU_C0_PERFCTL_U_BITFIELD_END ( 3)
+#define MIU_C0_PERFCTL_IE_BITFIELD_BEG ( 4)
+#define MIU_C0_PERFCTL_IE_BITFIELD_END ( 4)
+#define MIU_C0_PERFCTL_EVENT_BITFIELD_BEG ( 5)
+#define MIU_C0_PERFCTL_EVENT_BITFIELD_END (11)
+#define MIU_C0_PERFCTL_PCTD_BITFIELD_BEG (15)
+#define MIU_C0_PERFCTL_PCTD_BITFIELD_END (15)
+#define MIU_C0_PERFCTL_VPEID_BITFIELD_BEG (16)
+#define MIU_C0_PERFCTL_VPEID_BITFIELD_END (19)
+#define MIU_C0_PERFCTL_MT_EN_BITFIELD_BEG (20)
+#define MIU_C0_PERFCTL_MT_EN_BITFIELD_END (21)
+#define MIU_C0_PERFCTL_TCID_BITFIELD_BEG (22)
+#define MIU_C0_PERFCTL_TCID_BITFIELD_END (29)
+#define MIU_C0_PERFCTL_M_BITFIELD_BEG (31)
+#define MIU_C0_PERFCTL_M_BITFIELD_END (31)
+#define MIU_C0_PERFCTL_CONTEXT_BITFIELD_BEG ( 0)
+#define MIU_C0_PERFCTL_CONTEXT_BITFIELD_END ( 4)
+
+#define MIU_C0_PERFCTL_MT_EN_ALL ( 0)
+#define MIU_C0_PERFCTL_MT_EN_CUR_VPE ( 1)
+#define MIU_C0_PERFCTL_MT_EN_CUR_TC ( 2)
+
+/* C0_TCSCHEDULE */
+#define MIU_C0_TCSCHEDULE_GRP_BITFIELD_BEG ( 0)
+#define MIU_C0_TCSCHEDULE_GRP_BITFIELD_END ( 1)
+#define MIU_C0_TCSCHEDULE_STP_BITFIELD_BEG ( 3)
+#define MIU_C0_TCSCHEDULE_STP_BITFIELD_END ( 3)
+#define MIU_C0_TCSCHEDULE_T0_QE_BITFIELD_BEG ( 4)
+#define MIU_C0_TCSCHEDULE_T0_QE_BITFIELD_END ( 7)
+#define MIU_C0_TCSCHEDULE_T0_TH_BITFIELD_BEG ( 8)
+#define MIU_C0_TCSCHEDULE_T0_TH_BITFIELD_END (10)
+#define MIU_C0_TCSCHEDULE_T0_GRP_BITFIELD_BEG (11)
+#define MIU_C0_TCSCHEDULE_T0_GRP_BITFIELD_END (12)
+#define MIU_C0_TCSCHEDULE_T0_STP_BITFIELD_BEG (13)
+#define MIU_C0_TCSCHEDULE_T0_STP_BITFIELD_END (13)
+#define MIU_C0_TCSCHEDULE_T1_QE_BITFIELD_BEG (14)
+#define MIU_C0_TCSCHEDULE_T1_QE_BITFIELD_END (17)
+#define MIU_C0_TCSCHEDULE_T1_TH_BITFIELD_BEG (18)
+#define MIU_C0_TCSCHEDULE_T1_TH_BITFIELD_END (20)
+#define MIU_C0_TCSCHEDULE_T1_GRP_BITFIELD_BEG (21)
+#define MIU_C0_TCSCHEDULE_T1_GRP_BITFIELD_END (22)
+#define MIU_C0_TCSCHEDULE_T1_STP_BITFIELD_BEG (23)
+#define MIU_C0_TCSCHEDULE_T1_STP_BITFIELD_END (23)
+
+#define MIU_C0_TCSCHEDULE_QE_NOT ( 0)
+#define MIU_C0_TCSCHEDULE_QE_WBB ( 1)
+#define MIU_C0_TCSCHEDULE_QE_LDQ ( 2)
+#define MIU_C0_TCSCHEDULE_QE_FSB ( 4)
+#define MIU_C0_TCSCHEDULE_QE_SYS ( 8)
+
+/* C0_PRID */
+#define MIU_C0_PRID_COOPT_BITFIELD_END (31)
+#define MIU_C0_PRID_COOPT_BITFIELD_BEG (24)
+#define MIU_C0_PRID_COID_BITFIELD_END (23)
+#define MIU_C0_PRID_COID_BITFIELD_BEG (16)
+#define MIU_C0_PRID_PROCTYPE_BITFIELD_END (15)
+#define MIU_C0_PRID_PROCTYPE_BITFIELD_BEG ( 8)
+#define MIU_C0_PRID_REV_BITFIELD_END ( 7)
+#define MIU_C0_PRID_REV_BITFIELD_BEG ( 0)
+#define MIU_C0_PRID_REV_MAJOR_BITFIELD_END ( 7)
+#define MIU_C0_PRID_REV_MAJOR_BITFIELD_BEG ( 5)
+#define MIU_C0_PRID_REV_MINOR_BITFIELD_END ( 4)
+#define MIU_C0_PRID_REV_MINOR_BITFIELD_BEG ( 2)
+#define MIU_C0_PRID_REV_PATCH_LV_BITFIELD_END ( 1)
+#define MIU_C0_PRID_REV_PATCH_LV_BITFIELD_BEG ( 0)
+
+/* C0_EBASE */
+/* [TC] EBase use bit 0:9 in definition,
+ * but we only need 4 bit (max to 8 vpe/4 core, bit 0:3) */
+#define MIU_C0_EBASE_CPUNUM_BITFIELD_BEG ( 0)
+#define MIU_C0_EBASE_CPUNUM_BITFIELD_END ( 3)
+#define MIU_C0_EBASE_WG_BITFIELD_BEG (11)
+#define MIU_C0_EBASE_WG_BITFIELD_END (11)
+#define MIU_C0_EBASE_EXCBASE_BITFIELD_BEG (12)
+#define MIU_C0_EBASE_EXCBASE_BITFIELD_END (31)
+
+/* C0_CONFIG7 */
+#define MIU_C0_CONFIG7_SL_BITFIELD_BEG (0 )
+#define MIU_C0_CONFIG7_SL_BITFIELD_END (0 )
+#define MIU_C0_CONFIG7_BHT_BITFIELD_BEG (1 )
+#define MIU_C0_CONFIG7_BHT_BITFIELD_END (1 )
+#define MIU_C0_CONFIG7_RPS_BITFIELD_BEG (2 )
+#define MIU_C0_CONFIG7_RPS_BITFIELD_END (2 )
+#define MIU_C0_CONFIG7_BP_BITFIELD_BEG (3 )
+#define MIU_C0_CONFIG7_BP_BITFIELD_END (3 )
+#define MIU_C0_CONFIG7_ULB_BITFIELD_BEG (4 )
+#define MIU_C0_CONFIG7_ULB_BITFIELD_END (4 )
+#define MIU_C0_CONFIG7_NBLSU_BITFIELD_BEG (5 )
+#define MIU_C0_CONFIG7_NBLSU_BITFIELD_END (5 )
+#define MIU_C0_CONFIG7_CPOOO_BITFIELD_BEG (6 )
+#define MIU_C0_CONFIG7_CPOOO_BITFIELD_END (6 )
+#define MIU_C0_CONFIG7_BTLM_BITFIELD_BEG (7 )
+#define MIU_C0_CONFIG7_BTLM_BITFIELD_END (7 )
+#define MIU_C0_CONFIG7_ES_BITFIELD_BEG (8 )
+#define MIU_C0_CONFIG7_ES_BITFIELD_END (8 )
+#define MIU_C0_CONFIG7_IVAD_BITFIELD_BEG (9 )
+#define MIU_C0_CONFIG7_IVAD_BITFIELD_END (9 )
+#define MIU_C0_CONFIG7_IAR_BITFIELD_BEG (10)
+#define MIU_C0_CONFIG7_IAR_BITFIELD_END (10)
+#define MIU_C0_CONFIG7_BUSSLP_BITFIELD_BEG (11)
+#define MIU_C0_CONFIG7_BUSSLP_BITFIELD_END (11)
+#define MIU_C0_CONFIG7_ICWP_BITFIELD_BEG (12)
+#define MIU_C0_CONFIG7_ICWP_BITFIELD_END (12)
+#define MIU_C0_CONFIG7_AR_BITFIELD_BEG (16)
+#define MIU_C0_CONFIG7_AR_BITFIELD_END (16)
+#define MIU_C0_CONFIG7_FPR_BITFIELD_BEG (17)
+#define MIU_C0_CONFIG7_FPR_BITFIELD_END (17)
+#define MIU_C0_CONFIG7_HCI_BITFIELD_BEG (18)
+#define MIU_C0_CONFIG7_HCI_BITFIELD_END (18)
+#define MIU_C0_CONFIG7_PCT_BITFIELD_BEG (19)
+#define MIU_C0_CONFIG7_PCT_BITFIELD_END (19)
+#define MIU_C0_CONFIG7_NCWB_BITFIELD_BEG (20)
+#define MIU_C0_CONFIG7_NCWB_BITFIELD_END (20)
+#define MIU_C0_CONFIG7_RAMSLP_BITFIELD_BEG (21)
+#define MIU_C0_CONFIG7_RAMSLP_BITFIELD_END (21)
+#define MIU_C0_CONFIG7_CP_BITFIELD_BEG (22)
+#define MIU_C0_CONFIG7_CP_BITFIELD_END (22)
+#define MIU_C0_CONFIG7_MCRO_BITFIELD_BEG (23)
+#define MIU_C0_CONFIG7_MCRO_BITFIELD_END (23)
+#define MIU_C0_CONFIG7_WII_BITFIELD_BEG (31)
+#define MIU_C0_CONFIG7_WII_BITFIELD_END (31)
+
+/* C0_ERRCTL */
+#define MIU_C0_ERRCTL_PD_BITFIELD_BEG ( 0)
+#define MIU_C0_ERRCTL_PD_BITFIELD_END ( 3)
+#define MIU_C0_ERRCTL_PI_BITFIELD_BEG ( 4)
+#define MIU_C0_ERRCTL_PI_BITFIELD_END (12)
+#define MIU_C0_ERRCTL_PCI_BITFIELD_BEG (13)
+#define MIU_C0_ERRCTL_PCI_BITFIELD_END (18)
+#define MIU_C0_ERRCTL_FE_BITFIELD_BEG (19)
+#define MIU_C0_ERRCTL_FE_BITFIELD_END (19)
+#define MIU_C0_ERRCTL_SE_BITFIELD_BEG (20)
+#define MIU_C0_ERRCTL_SE_BITFIELD_END (20)
+#define MIU_C0_ERRCTL_L1ECC_BITFIELD_BEG (22)
+#define MIU_C0_ERRCTL_L1ECC_BITFIELD_END (22)
+#define MIU_C0_ERRCTL_L2P_BITFIELD_BEG (23)
+#define MIU_C0_ERRCTL_L2P_BITFIELD_END (23)
+#define MIU_C0_ERRCTL_WABE_BITFIELD_BEG (24)
+#define MIU_C0_ERRCTL_WABE_BITFIELD_END (24)
+#define MIU_C0_ERRCTL_LBE_BITFIELD_BEG (25)
+#define MIU_C0_ERRCTL_LBE_BITFIELD_END (25)
+#define MIU_C0_ERRCTL_ITC_BITFIELD_BEG (26)
+#define MIU_C0_ERRCTL_ITC_BITFIELD_END (26)
+#define MIU_C0_ERRCTL_PCO_BITFIELD_BEG (27)
+#define MIU_C0_ERRCTL_PCO_BITFIELD_END (27)
+#define MIU_C0_ERRCTL_SPR_BITFIELD_BEG (28)
+#define MIU_C0_ERRCTL_SPR_BITFIELD_END (28)
+#define MIU_C0_ERRCTL_WST_BITFIELD_BEG (29)
+#define MIU_C0_ERRCTL_WST_BITFIELD_END (29)
+#define MIU_C0_ERRCTL_PO_BITFIELD_BEG (30)
+#define MIU_C0_ERRCTL_PO_BITFIELD_END (30)
+#define MIU_C0_ERRCTL_PE_BITFIELD_BEG (31)
+#define MIU_C0_ERRCTL_PE_BITFIELD_END (31)
+
+#endif /* defined(__MIPS_IA__) && !defined(__MIPS_IA_CP0_DEF_H__) */
+
+#define miu_glue(x,y) x##y
+#define miu_xglue(x,y) miu_glue(x,y)
+#define miu_str(x) #x
+#define miu_xstr(x) miu_str(x)
+
+#define miu_reg_bitfd_mskn(beg, end) \
+ ((1 << (end - beg + 1)) - 1)
+
+#define miu_reg_bitfd_msk(__reg_name__) \
+ miu_reg_bitfd_mskn( \
+ miu_xglue(__reg_name__, _BITFIELD_BEG), \
+ miu_xglue(__reg_name__, _BITFIELD_END) \
+ )
+
+#define miu_reg_bitfd_off(__reg_name__) \
+ (miu_glue(__reg_name__, _BITFIELD_BEG))
+
+#define miu_reg_bitfd_mskoff_val(__reg_name__, __val__) \
+ ( \
+ ((__val__) & miu_reg_bitfd_msk(__reg_name__)) \
+ << miu_reg_bitfd_off(__reg_name__) \
+ )
+
+#define miu_reg_bitfd_mskoff(__reg_name__) \
+ ( \
+ miu_reg_bitfd_msk(__reg_name__) \
+ << miu_reg_bitfd_off(__reg_name__) \
+ )
+
+#define miu_reg_bitfd_rmskoff(__reg_name__) \
+ (~miu_reg_bitfd_mskoff(__reg_name__))
+
+#define miu_get_reg_bitfd_val(__reg_name__, __val__) \
+ ( \
+ ((__val__) & miu_reg_bitfd_mskoff(__reg_name__)) \
+ >> miu_reg_bitfd_off(__reg_name__) \
+ )
+
+#define miu_update_reg_bitfd(__reg_name__, __oval__, __nval__) \
+ __extension__ ({ \
+ ( \
+ ( \
+ (__oval__) & \
+ miu_reg_bitfd_rmskoff(__reg_name__) \
+ ) | \
+ miu_reg_bitfd_mskoff_val(__reg_name__, __nval__) \
+ ); \
+ })
+
+/* Make it work on both MIPS32/16
+ * - "d" would choose correct register number based on MIPS16/32, "r" would
+ * choose registers available on MIPS32
+ * - "J" (Integer zero) may choose zero register ($0), which is not available
+ * on MIPS16 (Ticket: 105306)
+ */
+#if defined(CONFIG_MIPS_IA_MR3) // MR3 would use MIPS16 & MIPS32
+# define __GCC_ASM_REG_CONSTRAINTS__ "d"
+#elif defined(CONFIG_MIPS_IA_MR2) // MR2 would use MIPS16 & MIPS32
+# define __GCC_ASM_REG_CONSTRAINTS__ "d"
+#elif defined(CONFIG_MIPS_I7200) // NanoMIPS doesn't have this limitation
+# define __GCC_ASM_REG_CONSTRAINTS__ "dJ"
+#else // if not MR2/MR3, assume it's MR1. MR1 only use MIPS32
+# define __GCC_ASM_REG_CONSTRAINTS__ "dJ"
+#endif /* !defined(CONFIG_MIPS_IA_MR2) */
+
+/*
+ * mfc0/mtc0 macro modified from m32c0.h
+ * Define macros for accessing the MIPS32 coprocessor 0 registers.
+ * Take cp0 register "$numbers,select" defined above as parameter.
+ */
+#define miu_mfc0(reg_sel) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ "mfc0 %0," reg_sel ";\n" \
+ : "=d" (__r) \
+ ); \
+ __r; \
+ })
+
+#define miu_mtc0(reg_sel, val) \
+ do { \
+ __asm__ __volatile__ ( \
+ ".set push \n" \
+ ".set noreorder \n" \
+ "mtc0 %z0," reg_sel "; \n" \
+ "ehb \n" \
+ ".set pop" \
+ : \
+ :__GCC_ASM_REG_CONSTRAINTS__\
+ ((miu_reg32_t)(val)) \
+ : "memory" \
+ ); \
+ } while (0)
+
+#define miu_mftc0(reg_sel) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__( \
+ "mftc0 %0," reg_sel ";\n" \
+ : "=d" (__r) \
+ ); \
+ __r; \
+ })
+
+#define miu_mttc0(reg_sel,val) \
+ do { \
+ __asm__ __volatile__ ( \
+ "%(mttc0\t %z0," reg_sel \
+ "; ehb%)" \
+ : : __GCC_ASM_REG_CONSTRAINTS__ \
+ ((miu_reg32_t)(val)) \
+ : "memory" \
+ ); \
+ } while (0)
+
+#define miu_jr_hb() \
+ do { \
+ register miu_reg32_t __tmp__; \
+ __asm__ __volatile__ ( \
+ " la %0, 1f \n" \
+ " jr.hb %0 \n" \
+ "1: \n" \
+ :"=&d"(__tmp__) \
+ ); \
+ } while(0)
+
+#define miu_ehb() \
+ do { \
+ __asm__ __volatile__ ( \
+ "ehb;\n" \
+ ); \
+ } while(0)
+
+#define miu_rdhwr(__rd__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ "rdhwr %0," __rd__ ";\n" \
+ : "=d" (__r) \
+ ); \
+ __r; \
+ })
+
+#define miu_mt_gettarget() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_VPECONTROL); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_VPECONTROL_TARGTC, __r); \
+ })
+
+#define miu_mt_settarget(tc) \
+ __extension__ ({ \
+ register miu_reg32_t __old; \
+ __old = miu_mfc0(MIU_C0_VPECONTROL); \
+ miu_mtc0(MIU_C0_VPECONTROL, \
+ miu_update_reg_bitfd( \
+ MIU_C0_VPECONTROL_TARGTC, __old, tc)\
+ ); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_VPECONTROL_TARGTC, __old); \
+ })
+
+#ifdef CONFIG_EHB_FOR_DMT_DVPE_HAZARD
+# define __miu_dmt_dvpe_hazard() miu_ehb()
+#else
+# define __miu_dmt_dvpe_hazard() miu_jr_hb()
+#endif
+
+#define miu_mt_dmt() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set mt; \n" \
+ "dmt %0; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ ); \
+ __miu_dmt_dvpe_hazard(); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_VPECONTROL_TE, __r); \
+ })
+
+#define miu_mt_emt() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set mt; \n" \
+ "emt %0; \n" \
+ "ehb; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ ); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_VPECONTROL_TE, __r); \
+ })
+
+#define miu_mt_dvpe() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set mt; \n" \
+ "dvpe %0; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ ); \
+ __miu_dmt_dvpe_hazard(); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_MVPCONTROL_EVP, __r);\
+ })
+
+#define miu_mt_evpe() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set mt; \n" \
+ "evpe %0; \n" \
+ "ehb; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ ); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_MVPCONTROL_EVP, __r);\
+ })
+
+#define miu_syncn(n) \
+ do { \
+ __asm__ __volatile__ ( \
+ "sync %0\n" \
+ : : "JK" (n) \
+ : "memory" \
+ ); \
+ } while(0)
+
+#define miu_c0_count_get() \
+ miu_mfc0(MIU_C0_COUNT)
+
+#define miu_cycle_counter_read() \
+ (miu_c0_count_get() << 1)
+
+#define miu_get_current_cpunum() \
+ miu_rdhwr(MIU_RDHWR_CPUNUM)
+
+#if defined(__MIPS_I7200__)
+# define miu_get_current_vpe_id() \
+ miu_mfc0(MIU_C0_TRACEDBPC) \
+
+# define miu_get_current_core_id() \
+ (miu_get_current_cpunum() >> 2)
+
+# define miu_relinquish() do { \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ ".set mt; \n" \
+ "yield %[yqn]; \n" \
+ ".set pop; \n" \
+ :: [yqn] "d" (-1) \
+ : "memory" \
+ ); \
+ } while(0)
+#elif defined(__MIPS_IA__) /* interAptiv */
+# define miu_get_current_vpe_id() \
+ miu_get_current_cpunum()
+
+# define miu_get_current_core_id() \
+ (miu_get_current_cpunum() >> 1)
+
+# define miu_relinquish() do {} while(0)
+#endif /* __MIPS_I7200__ */
+
+#define miu_get_current_tc_id() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCBIND); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_TCBIND_CURTC, __r); \
+ })
+
+#define miu_compiler_barrier() do { \
+ __asm__ __volatile__ ( \
+ "\n" \
+ : : : "memory" \
+ ); \
+ } while(0)
+
+#ifndef __ASSEMBLER__
+typedef unsigned int miu_reg32_t;
+#endif /* __ASSEMBLER__ */
+
+/* 201908121924.7c6d2ecdf3804c770b9936ff850c09807d995e2a */
+#endif /* __MIPS_IA_UTILS_PUBLIC_H__ */
diff --git a/mcu/interface/driver/sys_drv/mips_mmu.h b/mcu/interface/driver/sys_drv/mips_mmu.h
new file mode 100644
index 0000000..e56f469
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mips_mmu.h
@@ -0,0 +1,84 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mips_mmu.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Header file for MIPS MMU.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MIPS_MMU_H__
+#define __MIPS_MMU_H__
+
+#if defined(__MTK_TARGET__)
+#if defined(__MIPS_IA__)
+
+#define MMU_WRITABLE 0x1
+#define MMU_NON_WRITABLE 0x0
+
+typedef struct _mips_mmu_info_t
+{
+ kal_uint32 EntryLo0;
+ kal_uint32 EntryLo1;
+ kal_uint32 PageMask;
+ kal_uint32 EntryHi;
+} MIPS_MMU_INFO_T;
+
+/* Save TLB configuration*/
+void exception_save_mmu(MIPS_MMU_INFO_T* tlbs);
+
+/* MMU adjustment function for SST memory dumping*/
+void exception_set_mmu(void);
+
+/* Region init adjustment function for RO sections*/
+void region_init_set_mmu(kal_uint32 address, kal_uint32 size, kal_uint32 writable);
+
+/* MMU adjustment function for CCCI shared memory */
+void ccif_set_share_mem_mmu (kal_uint32 address, kal_uint32 size);
+
+/* MMU adjustment function for DHL shared memory */
+void dhl_set_share_mem_mmu (kal_uint32 address, kal_uint32 size);
+
+#endif /* __MIPS_IA__ */
+#endif /* __MTK_TARGET__ */
+
+#endif /* __MIPS_MMU_H__ */
+
diff --git a/mcu/interface/driver/sys_drv/mmu.h b/mcu/interface/driver/sys_drv/mmu.h
new file mode 100644
index 0000000..89b4049
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mmu.h
@@ -0,0 +1,125 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mmu.h
+ *
+ * Project:
+ * --------
+ * Device Test
+ *
+ * Description:
+ * ------------
+ * Header file for MMU.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MMU_H__
+#define __MMU_H__
+
+/* cacheable and bufferable */
+enum
+{
+ PAGE_NO_CACHE = 0x0,
+ PAGE_BUFFERABLE = 0x1,
+ PAGE_CACHEABLE = 0x1
+};
+
+#endif /* __MMU_H__ */
+
diff --git a/mcu/interface/driver/sys_drv/mpu_public.h b/mcu/interface/driver/sys_drv/mpu_public.h
new file mode 100644
index 0000000..15b65f8
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/mpu_public.h
@@ -0,0 +1,135 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mpu_public.h
+ *
+ * Project:
+ * --------
+ * UMOLYA Software
+ *
+ * Description:
+ * ------------
+ * Header file for IA MPU
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MPU_PUBLIC_H__
+#define __MPU_PUBLIC_H__
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#include "kal_general_types.h"
+#endif
+
+#define CXIF_MPU_PROTECTION_REMOVE
+
+/******************************************************************
+ * Define date structures
+ ******************************************************************/
+typedef struct MPU_REG_T
+{
+ volatile kal_uint32 reg_MPU_ACSR;
+ volatile kal_uint32 reg_MPU_CONFIG;
+ kal_uint8 MPU_Enable;
+ kal_uint8 exc_RI;
+ kal_uint8 exc_WI;
+ kal_uint8 exc_XI;
+ kal_uint8 exc_REG_MATCH;
+ kal_uint8 exc_REG_NUM;
+ kal_uint8 reserve[2];
+} _MPU_REG;
+
+#if defined(__MD97__) || defined(__MD97P__)
+typedef enum CXIF_MPU_SETTING_T
+{
+ CUIF_INNER_MPU_SETTING_BANK5 = 0,
+ CUIF_INNER_MPU_SETTING_BANK8 = 1,
+ CSIF_ALL_MPU_SETTING_BANK5 = 2,
+ CSIF_ALL_MPU_SETTING_BANK8 = 3
+} CXIF_MPU_SETTING_TYPE;
+#endif
+
+extern _MPU_REG *IA_MPU_REG_PTR[];
+
+extern kal_bool mpu_dump_ex(kal_uint32 coreid);
+
+#if defined(__MD95__)
+extern void system_set_rxdfe(kal_uint32 * shm_setting);
+extern void system_clr_rxdfe(kal_bool enable);
+extern void system_set_cuif(kal_uint32 * shm_setting);
+#elif defined(__MD97__) || defined(__MD97P__)
+extern void system_set_cxif(kal_uint32 * shm_setting, CXIF_MPU_SETTING_TYPE mpu_type);
+#endif
+
+
+kal_uint32 system_exception_mpu_region_check(void);
+kal_uint32 system_exception_mpu_segment_check(void);
+
+#endif /* __MPU_PUBLIC_H__ */
+
diff --git a/mcu/interface/driver/sys_drv/nfb_loader.h b/mcu/interface/driver/sys_drv/nfb_loader.h
new file mode 100644
index 0000000..1c786b4
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/nfb_loader.h
@@ -0,0 +1,110 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * enfb_loader.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ENFBLOADER_H
+#define _ENFBLOADER_H
+
+/*******************************************************************************
+ * Define constants.
+ *******************************************************************************/
+
+#define BOOTLOADER_THRESHOLD_8BITS 0x400000
+#define BOOTLOADER_THRESHOLD_16BITS 0x800000
+#define NFB_PERCENTAGE_STEP 10
+#define MAX_IMAGE_NUMBER 20
+#define CHECK_PASS_ID (0x53534150)
+
+
+/*******************************************************************************
+ * Define data structures.
+ *******************************************************************************/
+typedef struct
+{
+ void *dst_addr;
+ kal_uint32 offset;
+ kal_uint32 length;
+} enfb_scatter;
+
+
+typedef enum {
+ ENFB_CONTENT_RESERVED = 0x0,
+ /* Built dynamic RO-CODE */
+ /* External Binary Files */
+ ENFB_CONTENT_IMAGERES = 0x41,
+ ENFB_CONTENT_STRINGRES = 0x42,
+ /* --------------------- */
+ ENFB_CONTENT_ENDMARKER = 0xff
+} enfb_cidtbl;
+
+/*******************************************************************************
+ * Define function prototypes.
+ *******************************************************************************/
+void NFB_LIB_Load(kal_uint8 cid);
+void NFB_LIB_Unload(kal_uint8 cid);
+kal_bool NFB_RES_Load(kal_uint8 cid, void * dst_addr, kal_uint32 offset, kal_uint32 length);
+kal_bool NFB_RES_Loadv(kal_uint8 cid, enfb_scatter *Scatter, kal_uint32 scatter_number);
+extern kal_int32 Swapin_Read(kal_uint8 demp_bin, kal_uint32 va, kal_uint32 pa);
+#endif /* _ENFBLOADER_H */
+
+
diff --git a/mcu/interface/driver/sys_drv/sfu.h b/mcu/interface/driver/sys_drv/sfu.h
new file mode 100644
index 0000000..1c684e8
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/sfu.h
@@ -0,0 +1,47 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sfu.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __SFU_H__
+#define __SFU_H__
+
+#include "drv_sfu.h"
+void sfu_dynamic_set_fetch_line(kal_uint32 vpe, kal_uint32 line);
+void sfu_dynamic_monitor(kal_uint32 mode);
+
+#endif /* __SFU_H__ */
+
diff --git a/mcu/interface/driver/sys_drv/sync_data.h b/mcu/interface/driver/sys_drv/sync_data.h
new file mode 100644
index 0000000..3b364b2
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/sync_data.h
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2020
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef __SYNC_DATA_H__
+#define __SYNC_DATA_H__
+
+#include "reg_base.h"
+#include "mips_ia_utils_public.h"
+
+// DSB: Data_Sync_Barrier()
+#if defined(__MIPS_I7200__) && defined(__MTK_TARGET__)
+# define Data_Sync_Barrier() miu_syncn(7)
+# define MO_Sync() miu_syncn(6)
+# define MM_Sync() miu_syncn(3)
+# define Data_Coherent_Sync() miu_syncn(0x10)
+#elif defined(__MIPS_IA__) && defined(__MTK_TARGET__)
+# define Data_Sync_Barrier() do { \
+ register kal_uint32 __tmp__; \
+ __asm__ volatile ( \
+ "sync 0x3\n" \
+ "lw %0, 0(%1)\n" \
+ "sw %0, 0(%1)\n" \
+ :"=&d"(__tmp__) \
+ :"d"(BASE_ADDR_MO_SYNC_MAGIC) \
+ : "memory" \
+ );\
+ } while (0)
+# define MO_Sync() do { \
+ register kal_uint32 __tmp__; \
+ __asm__ volatile ( \
+ "sw %0, 0(%1)\n" \
+ "lw %0, 0(%1)\n" \
+ "sw %0, 0(%1)\n" \
+ :"=&d"(__tmp__) \
+ :"d"(BASE_ADDR_MO_SYNC_MAGIC) \
+ : "memory" \
+ );\
+ } while (0)
+# define MM_Sync() miu_syncn(3)
+# define Data_Coherent_Sync() do {} while(0)
+#else /* __MIPS_IA__ && __MTK_TARGET__ */
+#define Data_Sync_Barrier() do {} while(0)
+#define MO_Sync() do {} while(0)
+#define MM_Sync() do {} while(0)
+#define Data_Coherent_Sync() do {} while(0)
+#endif /* __MIPS_IA__ && __MTK_TARGET__ */
+
+// DMB: Data_Mem_Barrier()
+#define Data_Mem_Barrier() do {} while(0)
+
+// ISB: Inst_Sync_Barrier()
+#define Inst_Sync_Barrier() do {} while(0)
+
+#endif /* __SYNC_DATA_H__ */
diff --git a/mcu/interface/driver/sys_drv/system_trc.h b/mcu/interface/driver/sys_drv/system_trc.h
new file mode 100644
index 0000000..8cf5f10
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/system_trc.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * system_trc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines the index trace of system module.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _SYSTEM_TRACE_H
+#define _SYSTEM_TRACE_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+#define SYSTRACE_GROUP_INIT TRACE_GROUP_1
+#define SYSTRACE_GROUP_DEMP TRACE_GROUP_2
+#define SYSTRACE_GROUP_MMV1 TRACE_GROUP_3
+#define SYSTRACE_GROUP_MMV2 TRACE_GROUP_4
+#define SYSTRACE_GROUP_KAL_TIMER TRACE_GROUP_5
+#define SYSTRACE_GROUP_RTOS TRACE_GROUP_6
+#define SYSTRACE_GROUP_KALOTHER TRACE_GROUP_7
+#if !defined(GEN_FOR_PC)
+#if !defined(__MAUI_BASIC__)
+#include"system_trc_mod_system_utmd.h"
+#endif
+#endif
+#endif /* _TST_TRACE_H */
diff --git a/mcu/interface/driver/sys_drv/system_trc_mod_system_utmd.json b/mcu/interface/driver/sys_drv/system_trc_mod_system_utmd.json
new file mode 100644
index 0000000..382ba22
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/system_trc_mod_system_utmd.json
@@ -0,0 +1,1756 @@
+{
+ "endGen": "Legacy",
+ "startGen": "Legacy",
+ "legacyParameters": {},
+ "module": "MOD_SYSTEM",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "SST_INIT_L1CACHE_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter L1-cache init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_L1CACHE_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit L1-cache init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MMU_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter MMU init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MMU_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit MMU init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MPU_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter MPU init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MPU_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit MPU init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_L2CACHE_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter L2-cache init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_L2CACHE_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit L2-cache init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_APPINIT_START": {
+ "_comment": "Trace reference not found",
+ "format": "Starting Application_Initialize()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CLIB1_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter C library basic init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CLIB1_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit C library basic init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CCCI_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter CCCI init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CCCI_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit CCCI init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CCCIHS1_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter CCCI handshake phase1 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CCCIHS1_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit CCCI handshake phase1 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MDCIHS1_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter MDCI handshake phase1 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MDCIHS1_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit MDCI handshake phase1 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_BOOTMODE_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter Boot Mode variable setting",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_BOOTMODE_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit Boot Mode variable setting ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_SYSTEMINIT_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter system intialization",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_SYSTEMINIT_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit system intialization ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_NVRAM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter NVRAM init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_NVRAM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit NVRAM init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_USC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter ARM us counter init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_USC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit ARM us counter init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_OSTD_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter ARM OS Timer Sleep Mode init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_OSTD_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit ARM OS Timer Sleep Mode init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DVFS_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter DVFS init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DVFS_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit DVFS init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_L1SM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter L1SM init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_L1SM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit L1SM init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_UL1SM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter UL1SM init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_UL1SM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit UL1SM init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_EL1SM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter EL1SM init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_EL1SM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit EL1SM init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_HWDIVIDER_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter HW divider init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_HWDIVIDER_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit HW divider init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_IDMALOAD_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter load DSP via iDMA",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_IDMALOAD_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit load DSP via iDMA ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_NFIRESET_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter NFI reset",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_NFIRESET_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit NFI reset ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_START": {
+ "_comment": "Trace reference not found",
+ "format": "Starting driver init phase1",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_TTY_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter TTY init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_TTY_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit TTY init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DRVHISR_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter driver HISR init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DRVHISR_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit driver HISR init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_MDCIHW_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter MDCI HW init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_MDCIHW_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit MDCI HW init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_CCCI_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter CCCI init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_CCCI_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit CCCI init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_EMIMPU_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter EMIMPU init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_EMIMPU_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit EMIMPU init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_LPWR_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter low power init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_LPWR_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit low power init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DRVPDN_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter power down control init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DRVPDN_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit power down control init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PWM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter power management init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PWM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit power management init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_CUSTOM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter customized driver init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_CUSTOM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit customized driver init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_GPT3_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter GPT3 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_GPT3_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit GPT3 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_VISUAL_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter visual init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_VISUAL_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit visual init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_GPTI_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter GPTI init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_GPTI_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit GPTI init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_WDT_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter WDT init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_WDT_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit WDT init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DMA_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter DMA init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DMA_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit DMA init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_XOSC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter XOSC set",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_XOSC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit XOSC set ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_ADC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter ADC init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_ADC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit ADC init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_CSFACDET_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter customized factory mode detection init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_CSFACDET_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit customized factory mode detection init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_ACCDET_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter ACCDET init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_ACCDET_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit ACCDET init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_LCD_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter LCD init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_LCD_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit LCD init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_RTCHW_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter RTC HW init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_RTCHW_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit RTC HW init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PMIC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter PMIC init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PMIC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit PMIC init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PW_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter power ON init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PW_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit power ON init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DMAVFIFO_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter DMA VFIFO init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_DMAVFIFO_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit DMA VFIFO init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_UART1_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter UART1 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_UART1_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit UART1 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_UART2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter UART2 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_UART2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit UART2 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_UART3_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter UART3 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_UART3_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit UART3 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PCIE_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter PCIE init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_PCIE_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit PCIE init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV1_OK": {
+ "_comment": "Trace reference not found",
+ "format": "Driver init phase1 ... [ OK ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_PREFOTA_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter FOTA preparation",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_PREFOTA_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit FOTA preparation ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_THIRDROM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter third ROM init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_THIRDROM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit third ROM init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_LOADSECMAUI_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter Load Secondary MAUI",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_LOADSECMAUI_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit Load Secondary MAUI ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DEMP_ENTER": {
+ "apiType": "index",
+ "format": "Enter demand paging init",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_INIT_DEMP_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit demand paging init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_PWRKEY": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: PWRKEY: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_CHRIN": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: CHRIN: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_USBIN": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: USBIN: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_RTCALARM": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: RTC_ALARM: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_WDT": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: WDT: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_NORMAL_RST": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: NORMAL_RST_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_CHR_PWRON_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: CHR_PWRON_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_USBMS_PWRON_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: USBMS_PWRON_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_RTC_PWRON_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: RTC_PWRON_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_PRECHR_PWRON_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: PRECHR_PWRON_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_FC2IDLE_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: SWITCH2IDLE_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_FC2CHR_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: SWITCH2CHR_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_FACTOR_FC2USB_FG": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: factor: SWITCH2USB_FG: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_PWRON_REASON": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: BMT.PWRon: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_ABNORMAL_PWRON": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: Abnormal power on",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PW_POWERINIT_META_PWRON": {
+ "_comment": "Trace reference not found",
+ "format": "PW_PowerInit: META power on",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_START": {
+ "_comment": "Trace reference not found",
+ "format": "Starting driver init phase2",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_USB2UART_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter USB2UART init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_USB2UART_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit USB2UART init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_KBD_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter keypad init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_KBD_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit keypad init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_RTCSW_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter RTC SW init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_RTCSW_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit RTC SW init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_SIM_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter SIM init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_SIM_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit SIM init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_SIMMT6302_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter SIM MT6302 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_SIMMT6302_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit SIM MT6302 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_MSDC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter MSDC init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_MSDC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit MSDC init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_MSDC2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter MSDC2 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_MSDC2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit MSDC2 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_EINTSWDBNC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter EINT SW Debounce init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_EINTSWDBNC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit EINT SW Debounce init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_SWDBG_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter SWDBG init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_SWDBG_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit SWDBG init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_CHE_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter cipher/hash engine init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_CHE_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit cipher/hash engine init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_IMGSENS_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter ISP/Camera init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_IMGSENS_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit ISP/Camera init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_CIS_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter Power ON CIS",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_CIS_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit Power ON CIS ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_MSENS_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter motion sensor init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_MSENS_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit motion sensor init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_WN_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter WLAN network init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_WN_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit WLAN network init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_I2C_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter I2C init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_I2C_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Init I2C init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_ICC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter ICC init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_ICC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit ICC ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_BTIF_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter BTIF init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_BTIF_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit BTIF init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_ADC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter ADC init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_ADC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit ADC init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_PFC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter PFC init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_PFC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit PFC init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_PCIE2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter PCIE2 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_PCIE2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit PCIE2 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DRV2_OK": {
+ "_comment": "Trace reference not found",
+ "format": "Driver init phase2 ... [ OK ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_RESINIT_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter resource initialization",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_RESINIT_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit resource initialization ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CHECKMSGID_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter message ID check",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CHECKMSGID_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Check message ID check ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CLIB2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter C library init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CLIB2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit C library init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DMDSP1_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter Dual MAC DSP init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DMDSP1_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit Dual MAC DSP init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CCCIHS2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter CCCI handshake phase2 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_CCCIHS2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit CCCI handshake phase2 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MDCIHS2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter MDCI handshake phase2 init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_MDCIHS2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit MDCI handshake phase2 init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DMDSP2_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter Dual MAC DSP exception init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_DMDSP2_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit Dual MAC DSP exception init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_RTFINIT_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter file system init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_RTFINIT_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit file system init ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_RTFSANITY_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "Enter file system sanity check",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_RTFSANITY_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "Exit file system sanity check ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_TASKINIT": {
+ "_comment": "Trace reference not found",
+ "format": "Starting task init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_TASKINIT_INDX_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": " Enter task init - %Mtask_indx_type",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_TASKINIT_INDX_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": " Exit task init - %Mtask_indx_type ... [ duration: %d ms ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_INIT_APPINIT_OK": {
+ "_comment": "Trace reference not found",
+ "format": "Application_Initialize() ... [ OK ]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_FAULT_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Enter do_page_fault(), task:%Mtask_indx_type, prio:%d, ERROR_TYPE:%d, fault addr:0x%X, FSR:0x%X, nested count:%d +++++++",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_ERR_CODE": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Return error code: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_ALLOC_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Enter page allocation",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_ALLOC_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Exit page allocation, page VA:0x%X, page PA:0x%X, balance count:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_SWAPOUT_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Enter page swap-out, page VA:0x%X, fault addr:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_SWAPOUT_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Exit page swap-out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_SWAPIN_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Enter page swap-in, page VA:0x%X, fault addr:0x%X, prio:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_LOCK_TAKEN": {
+ "apiType": "index",
+ "format": "[DEMP] MTD lock is taken by %Mtask_indx_type, lock count:%d",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "DEMP_PAGE_LOCK_AVAILABLE": {
+ "apiType": "index",
+ "format": "[DEMP] MTD lock is available",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "DEMP_PAGE_GET_LOCK": {
+ "apiType": "index",
+ "format": "[DEMP] %Mtask_indx_type gets MTD lock, prio:%d",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "DEMP_PAGE_FREE_LOCK": {
+ "apiType": "index",
+ "format": "[DEMP] %Mtask_indx_type frees MTD lock, prio:%d",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "DEMP_PAGE_SWAPIN_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Exit page swap-in, page VA:0x%X, fault addr:0x%X, prio:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PTABLE_UPDATE_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Enter page table update, smallest_pd addr:0x%X, smallest_pd value:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PTABLE_UPDATE_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Exit page table update, smallest_pd addr:0x%X, smallest_pd value:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_PAGE_FAULT_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Exit do_page_fault(), task:%Mtask_indx_type, prio:%d, ERROR_TYPE:%d, fault addr:0x%X, FSR:0x%X -------------------------------------",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_LOCK_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP][LOCK] Enter demp_lock_pages(), user:%Mdemp_lock_user, addr:0x%X, len:0x%X >>>>>>>>>>>>",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_LOCK": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Lock page:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_LOCK_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP][LOCK] Exit demp_lock_pages(), user:%Mdemp_lock_user, addr:0x%X, len:0x%X <<<<<<<<<<<<",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_UNLOCK_ENTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP][LOCK] Enter demp_unlock_pages(), user:%Mdemp_lock_user, addr:0x%X, len:0x%X >>>>>>>>>>>>",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_UNLOCK": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP] Unlock page:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DEMP_UNLOCK_EXIT": {
+ "_comment": "Trace reference not found",
+ "format": "[DEMP][LOCK] Exit demp_unlock_pages(), user:%Mdemp_lock_user, addr:0x%X, len:0x%X <<<<<<<<<<<<",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SYSMEM_ALLOC_FORMAT": {
+ "apiType": "index",
+ "format": "[KAL] sys_mem_alloc(%u, %x)",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "ADM_CREATE2_FORMAT": {
+ "apiType": "index",
+ "format": "[KAL] adm_create2(%x, %u, %d/%d/%d..., %x, %d)=%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "ADM_DELETE_FORMAT": {
+ "apiType": "index",
+ "format": "[KAL] adm_delete(%x)=%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "ADM_ALLOC_FORMAT": {
+ "apiType": "index",
+ "format": "[KAL] adm_alloc(%x, %u, %u, %u, %s, %d)=%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "ADM_FREE_FORMAT": {
+ "apiType": "index",
+ "format": "[KAL] adm_free(%x, %x)",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "FLMM_ALLOC_FORMAT": {
+ "_comment": "Trace reference not found",
+ "format": "[KAL] flmm_alloc(%x)=%x/%x~%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "FLMM_FREE_FORMAT": {
+ "_comment": "Trace reference not found",
+ "format": "[KAL] flmm_free(%x), virtual=%x~%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLMM_DROP_FORMAT": {
+ "_comment": "Trace reference not found",
+ "format": "[KAL] slmm_drop(%x, %x~%x))",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "PROFILE_CPUUSAGE_FORMAT": {
+ "apiType": "index",
+ "format": "[KAL] CPU Usage: %d percent",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "TP_OVER_200QB": {
+ "_comment": "Trace reference not found",
+ "format": "[Thread Protect] Over 200QB warning: thread: %x, taker address: %x, giver address: %x, duration: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "EVSHED_CREATE": {
+ "apiType": "index",
+ "format": "[evshed]evshed_create. task %d es 0x%x st 0x%x module %d fuzz %d max_delay_tick %d name %c %c %c %c %c %c %c %c",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_SET_EVENT": {
+ "apiType": "index",
+ "format": "[evshed]set_event task %d es 0x%x st 0x%x eid 0x%x hf 0x%x, tick %d",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_SET_INDEX": {
+ "apiType": "index",
+ "format": "[evshed] set_index, task %d es 0x%x st 0x%x, index %d",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_GET_INDEX": {
+ "apiType": "index",
+ "format": "[evshed] get_index, task %d st 0x%x, index %d",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_CANCEL_EVENT": {
+ "apiType": "index",
+ "format": "[evshed] cancel_event, task %d es 0x%x st 0x%x, eid 0x%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_SUSPEND": {
+ "apiType": "index",
+ "format": "[evshed]suspend, task %d es 0x%x st 0x%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_RESUME": {
+ "apiType": "index",
+ "format": "[evshed]resume, task %d es 0x%x st 0x%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_HANDLER": {
+ "apiType": "index",
+ "format": "[evshed]handler task %d es 0x%x st 0x%x eid 0x%x hf 0x%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_DEL": {
+ "apiType": "index",
+ "format": "[evshed]delete_all, task %d es 0x%x st 0x%x",
+ "traceClass": "TRACE_GROUP_1"
+ }
+ },
+ {
+ "EVSHED_SET_ALIGN": {
+ "_comment": "Trace reference not found",
+ "format": "[evshed] set_aligned_timer, task %d st 0x%x max_delay %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "EVSHED_UNSET_ALIGN": {
+ "_comment": "Trace reference not found",
+ "format": "[evshed]unset_aligned, task %d st 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "EVSHED_EVENT_COUNT_MAX": {
+ "apiType": "index",
+ "format": "[evshed]event_cnt_max record, es 0x%x e_cnt %d module %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DCM_COUNTER": {
+ "_comment": "Trace reference not found",
+ "format": "[DCM] DCM_CNT:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "DCM_ACTIVE_CYCLES": {
+ "_comment": "Trace reference not found",
+ "format": "[DCM] HW_DCM_CYCLES:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ }
+ ],
+ "traceFamily": "PS"
+}
diff --git a/mcu/interface/driver/sys_drv/tg_hisr.h b/mcu/interface/driver/sys_drv/tg_hisr.h
new file mode 100644
index 0000000..660593f
--- /dev/null
+++ b/mcu/interface/driver/sys_drv/tg_hisr.h
@@ -0,0 +1,38 @@
+#ifndef __TG_HISR_H__
+#define __TG_HISR_H__
+
+#include "kal_general_types.h"
+
+typedef enum{
+ TG_TRIGGER_NONE = 0,
+ TG_TRIGGER_GPT = 1,
+ TG_TRIGGER_LTE,
+ TG_TRIGGER_W,
+ TG_TRIGGER_T,
+ TG_TRIGGER_C
+}TG_TRIGGER_MODE;
+
+extern void tg_first_L_tick(void);
+extern void tg_last_L_tick(void);
+extern void tg_group1_trigger(TG_TRIGGER_MODE);
+extern void tg_group2_trigger(TG_TRIGGER_MODE);
+extern void tg_hmu_callback_control_sync(void);
+
+#ifdef __LP_SCHEDULE_ENABLE__
+extern void tg_hisr_init(void);
+#else
+#define tg_hisr_init() \
+ do {} while(0)
+#endif
+
+#ifdef __LP_SCHEDULE_HMU_RESCHEDULE__
+extern void tg_hmu_callback_control(kal_bool enable);
+#endif /* __LP_SCHEDULE_HMU_RESCHEDULE__ */
+
+#if defined(__LP_SCHEDULE_FDD3G_TALKING__)
+extern void tg_fdd3g_talking_mode(kal_uint32 mode);
+extern void tg_group3_start(TG_TRIGGER_MODE mode);
+extern void tg_group3_end(TG_TRIGGER_MODE mode);
+#endif /* __LP_SCHEDULE_FDD3G_TALKING__ */
+
+#endif /* __TG_HISR_C__ */