[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/l1/cl1/common/FW/cphregaccesscuif.h b/mcu/interface/l1/cl1/common/FW/cphregaccesscuif.h
new file mode 100644
index 0000000..f53201a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/FW/cphregaccesscuif.h
@@ -0,0 +1,51 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_REGACCESS_CUIF_H_
+#define _CPH_REGACCESS_CUIF_H_
+
+
+#define INCLUDE_DSP_HEADER_ENABLE_INNER_BRP
+#include "CUIF_inner_brp_ALL.h"
+#undef INCLUDE_DSP_HEADER_ENABLE_INNER_BRP
+
+#if defined(MTK_PLT_ON_PC_IT)
+extern CUIF_C2K_EVDO_REGS CphCuifRegs;
+#define CUIF_READ(reg) (CphCuifRegs.reg)
+#define CUIF_WRITE(reg, val) (CphCuifRegs.reg = val)
+#else
+#define CUIF_READ(reg) (CUIF_C2K_EVDO->reg)
+#define CUIF_WRITE(reg, val) (CUIF_C2K_EVDO->reg = val)
+#endif
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrp.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp.h
new file mode 100644
index 0000000..2133cd2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxbrp_93.h"
+#elif defined(__MD95__)
+#include "cph1xrxbrp_93.h"
+#elif defined(__MD97__)
+#include "cph1xrxbrp_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_93.h
new file mode 100644
index 0000000..39f21bf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_93.h
@@ -0,0 +1,444 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_H_
+#define _CPH_1X_RXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_1XRTT_REG_BASE (0xAD040000)
+
+#define RXBRP_C_1XRTT_end (RXBRP_C_1XRTT_REG_BASE + 0x0210 + 1*4)
+
+
+
+#define DBRP_RTT_START ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0000))
+#define DBRP_RTT_DONE ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0004))
+#define DBRP_RTT_DONE_VEC ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0008))
+#define DBRP_RTT_CFG_OK ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x000C))
+#define DBRP_RTT_CH_DET ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0010))
+#define DBRP_RTT_SCAL_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0014))
+#define DBRP_RTT_FCH_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0018))
+#define DBRP_RTT_FCH_ET_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x001C))
+#define DBRP_RTT_SYNC_VIT_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0020))
+#define DBRP_RTT_DBG0 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00D0))
+#define DBRP_RTT_PWR_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00F0))
+#define DBRP_RTT_FCH_FULL_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0100))
+#define DBRP_RTT_FCH_FULL_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0104))
+#define DBRP_RTT_FCH_FULL_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0108))
+#define DBRP_RTT_FCH_HALF_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x010C))
+#define DBRP_RTT_FCH_HALF_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0110))
+#define DBRP_RTT_FCH_QUAR_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0114))
+#define DBRP_RTT_FCH_QUAR_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0118))
+#define DBRP_RTT_FCH_EIGH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x011C))
+#define DBRP_RTT_FCH_EIGH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0120))
+#define DBRP_RTT_SCH_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0124))
+#define DBRP_RTT_SCH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0128))
+#define DBRP_RTT_SCH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x012C))
+#define DBRP_RTT_FCH_ET_PCG_CNT ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0200))
+#define DBRP_RTT_FCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0204))
+#define DBRP_RTT_FCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0208))
+#define DBRP_RTT_SCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x020C))
+#define DBRP_RTT_SCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0210))
+
+
+#define DBRP_RTT_START_BRP_RTT_START_LSB (15)
+#define DBRP_RTT_START_BRP_RTT_START_WIDTH (1)
+#define DBRP_RTT_START_BRP_RTT_START_MASK (0x00008000)
+#define DBRP_RTT_START_BRP_RTT_START_BIT (0x00008000)
+
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_LSB (16)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_MASK (0x00010000)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_BIT (0x00010000)
+
+#define DBRP_RTT_DONE_RTT_DONE_LSB (0)
+#define DBRP_RTT_DONE_RTT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_RTT_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_DONE_VEC_TUR_DONE_LSB (3)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_MASK (0x00000008)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_BIT (0x00000008)
+
+#define DBRP_RTT_DONE_VEC_VIT_DONE_LSB (2)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_MASK (0x00000004)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_BIT (0x00000004)
+
+#define DBRP_RTT_DONE_VEC_CORR_DONE_LSB (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_MASK (0x00000002)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_BIT (0x00000002)
+
+#define DBRP_RTT_DONE_VEC_DRM_DONE_LSB (0)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_LSB (15)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_MASK (0x00008000)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_BIT (0x00008000)
+
+#define DBRP_RTT_CFG_OK_CFG_OK_LSB (0)
+#define DBRP_RTT_CFG_OK_CFG_OK_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_OK_MASK (0x00000001)
+#define DBRP_RTT_CFG_OK_CFG_OK_BIT (0x00000001)
+
+#define DBRP_RTT_CH_DET_SCH_ENCODING_LSB (2)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_MASK (0x00000004)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_BIT (0x00000004)
+
+#define DBRP_RTT_CH_DET_SCH_EN_LSB (1)
+#define DBRP_RTT_CH_DET_SCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_EN_MASK (0x00000002)
+#define DBRP_RTT_CH_DET_SCH_EN_BIT (0x00000002)
+
+#define DBRP_RTT_CH_DET_FCH_EN_LSB (0)
+#define DBRP_RTT_CH_DET_FCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_FCH_EN_MASK (0x00000001)
+#define DBRP_RTT_CH_DET_FCH_EN_BIT (0x00000001)
+
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_LSB (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_MASK (0x00000002)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_BIT (0x00000002)
+
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_LSB (0)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_MASK (0x00000001)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_BIT (0x00000001)
+
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_LSB (18)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_MASK (0x00040000)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_BIT (0x00040000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_LSB (17)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_MASK (0x00020000)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_BIT (0x00020000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_LSB (16)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_MASK (0x00010000)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_LSB (12)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_MASK (0x0000F000)
+
+#define DBRP_RTT_FCH_CFG_CH_SEL_LSB (0)
+#define DBRP_RTT_FCH_CFG_CH_SEL_WIDTH (2)
+#define DBRP_RTT_FCH_CFG_CH_SEL_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_LSB (31)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_WIDTH (1)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_MASK (0x80000000)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_BIT (0x80000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_LSB (24)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_MASK (0x0F000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_LSB (20)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_MASK (0x00F00000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_LSB (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_MASK (0x000F0000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_LSB (0)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_WIDTH (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_MASK (0x0000FFFF)
+
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_LSB (0)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_DBG0_DRM_FSM_CS_LSB (24)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_MASK (0x1F000000)
+
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_LSB (20)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_WIDTH (3)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_MASK (0x00700000)
+
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_LSB (12)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_MASK (0x0001F000)
+
+#define DBRP_RTT_DBG0_TOP_FSM_CS_LSB (0)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_WIDTH (9)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_MASK (0x000001FF)
+
+#define DBRP_RTT_PWR_CFG_PWR_MODE_LSB (15)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_WIDTH (1)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_MASK (0x00008000)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_BIT (0x00008000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_SCH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_SCH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F)
+
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF)
+
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_97.h
new file mode 100644
index 0000000..aad994f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_97.h
@@ -0,0 +1,444 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_H_
+#define _CPH_1X_RXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_1XRTT_REG_BASE (0xAC840000)
+
+#define RXBRP_C_1XRTT_end (RXBRP_C_1XRTT_REG_BASE + 0x0210 + 1*4)
+
+
+
+#define DBRP_RTT_START ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0000))
+#define DBRP_RTT_DONE ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0004))
+#define DBRP_RTT_DONE_VEC ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0008))
+#define DBRP_RTT_CFG_OK ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x000C))
+#define DBRP_RTT_CH_DET ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0010))
+#define DBRP_RTT_SCAL_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0014))
+#define DBRP_RTT_FCH_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0018))
+#define DBRP_RTT_FCH_ET_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x001C))
+#define DBRP_RTT_SYNC_VIT_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0020))
+#define DBRP_RTT_DBG0 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00D0))
+#define DBRP_RTT_PWR_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00F0))
+#define DBRP_RTT_FCH_FULL_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0100))
+#define DBRP_RTT_FCH_FULL_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0104))
+#define DBRP_RTT_FCH_FULL_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0108))
+#define DBRP_RTT_FCH_HALF_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x010C))
+#define DBRP_RTT_FCH_HALF_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0110))
+#define DBRP_RTT_FCH_QUAR_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0114))
+#define DBRP_RTT_FCH_QUAR_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0118))
+#define DBRP_RTT_FCH_EIGH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x011C))
+#define DBRP_RTT_FCH_EIGH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0120))
+#define DBRP_RTT_SCH_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0124))
+#define DBRP_RTT_SCH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0128))
+#define DBRP_RTT_SCH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x012C))
+#define DBRP_RTT_FCH_ET_PCG_CNT ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0200))
+#define DBRP_RTT_FCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0204))
+#define DBRP_RTT_FCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0208))
+#define DBRP_RTT_SCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x020C))
+#define DBRP_RTT_SCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0210))
+
+
+#define DBRP_RTT_START_BRP_RTT_START_LSB (15)
+#define DBRP_RTT_START_BRP_RTT_START_WIDTH (1)
+#define DBRP_RTT_START_BRP_RTT_START_MASK (0x00008000)
+#define DBRP_RTT_START_BRP_RTT_START_BIT (0x00008000)
+
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_LSB (16)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_MASK (0x00010000)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_BIT (0x00010000)
+
+#define DBRP_RTT_DONE_RTT_DONE_LSB (0)
+#define DBRP_RTT_DONE_RTT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_RTT_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_DONE_VEC_TUR_DONE_LSB (3)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_MASK (0x00000008)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_BIT (0x00000008)
+
+#define DBRP_RTT_DONE_VEC_VIT_DONE_LSB (2)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_MASK (0x00000004)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_BIT (0x00000004)
+
+#define DBRP_RTT_DONE_VEC_CORR_DONE_LSB (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_MASK (0x00000002)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_BIT (0x00000002)
+
+#define DBRP_RTT_DONE_VEC_DRM_DONE_LSB (0)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_LSB (15)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_MASK (0x00008000)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_BIT (0x00008000)
+
+#define DBRP_RTT_CFG_OK_CFG_OK_LSB (0)
+#define DBRP_RTT_CFG_OK_CFG_OK_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_OK_MASK (0x00000001)
+#define DBRP_RTT_CFG_OK_CFG_OK_BIT (0x00000001)
+
+#define DBRP_RTT_CH_DET_SCH_ENCODING_LSB (2)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_MASK (0x00000004)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_BIT (0x00000004)
+
+#define DBRP_RTT_CH_DET_SCH_EN_LSB (1)
+#define DBRP_RTT_CH_DET_SCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_EN_MASK (0x00000002)
+#define DBRP_RTT_CH_DET_SCH_EN_BIT (0x00000002)
+
+#define DBRP_RTT_CH_DET_FCH_EN_LSB (0)
+#define DBRP_RTT_CH_DET_FCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_FCH_EN_MASK (0x00000001)
+#define DBRP_RTT_CH_DET_FCH_EN_BIT (0x00000001)
+
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_LSB (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_MASK (0x00000002)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_BIT (0x00000002)
+
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_LSB (0)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_MASK (0x00000001)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_BIT (0x00000001)
+
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_LSB (18)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_MASK (0x00040000)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_BIT (0x00040000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_LSB (17)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_MASK (0x00020000)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_BIT (0x00020000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_LSB (16)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_MASK (0x00010000)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_LSB (12)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_MASK (0x0000F000)
+
+#define DBRP_RTT_FCH_CFG_CH_SEL_LSB (0)
+#define DBRP_RTT_FCH_CFG_CH_SEL_WIDTH (2)
+#define DBRP_RTT_FCH_CFG_CH_SEL_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_LSB (31)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_WIDTH (1)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_MASK (0x80000000)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_BIT (0x80000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_LSB (24)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_MASK (0x0F000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_LSB (20)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_MASK (0x00F00000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_LSB (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_MASK (0x000F0000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_LSB (0)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_WIDTH (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_MASK (0x0000FFFF)
+
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_LSB (0)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_DBG0_DRM_FSM_CS_LSB (24)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_MASK (0x1F000000)
+
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_LSB (20)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_WIDTH (3)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_MASK (0x00700000)
+
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_LSB (12)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_MASK (0x0001F000)
+
+#define DBRP_RTT_DBG0_TOP_FSM_CS_LSB (0)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_WIDTH (9)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_MASK (0x000001FF)
+
+#define DBRP_RTT_PWR_CFG_PWR_MODE_LSB (15)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_WIDTH (1)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_MASK (0x00008000)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_BIT (0x00008000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_SCH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_SCH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F)
+
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF)
+
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser.h
new file mode 100644
index 0000000..b8fa30c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser.h
@@ -0,0 +1,45 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxbrpcorrser_93.h"
+#elif defined(__MD95__)
+#include "cph1xrxbrpcorrser_93.h"
+#elif defined(__MD97__)
+#include "cph1xrxbrpcorrser_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_93.h
new file mode 100644
index 0000000..9c2cccf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_93.h
@@ -0,0 +1,224 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_CORRSER_H_
+#define _CPH_1X_RXBRP_CORRSER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_CORR_SER_REG_BASE (0xAD050000)
+
+#define RXBRP_C_CORR_SER_end (RXBRP_C_CORR_SER_REG_BASE + 0x007C + 1*4)
+
+
+
+#define DBRP_RTT_CORR_BUF_IDX ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0000))
+#define DBRP_RTT_CORR_ENERGY ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0004))
+#define DBRP_RTT_CORR_RSLT0 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0008))
+#define DBRP_RTT_CORR_RSLT1 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x000C))
+#define DBRP_RTT_CORR_RSLT2 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0010))
+#define DBRP_RTT_CORR_RSLT3 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0014))
+#define DBRP_RTT_CORR_RSLT4 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0018))
+#define DBRP_RTT_CORR_RSLT5 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x001C))
+#define DBRP_RTT_CORR_RSLT6 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0020))
+#define DBRP_RTT_CORR_RSLT7 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0024))
+#define DBRP_RTT_CORR_RSLT8 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0028))
+#define DBRP_RTT_CORR_RSLT9 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x002C))
+#define DBRP_RTT_CORR_RSLT10 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0030))
+#define DBRP_RTT_CORR_RSLT11 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0034))
+#define DBRP_RTT_CORR_RSLT12 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0038))
+#define DBRP_RTT_CORR_RSLT13 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x003C))
+#define DBRP_RTT_CORR_RSLT14 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0040))
+#define DBRP_RTT_CORR_RSLT15 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0044))
+#define DBRP_RTT_CORR_RSLT_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0048))
+#define DBRP_RTT_CORR_FULL_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x004C))
+#define DBRP_RTT_CORR_HALF_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0050))
+#define DBRP_RTT_CORR_QUAR_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0054))
+#define DBRP_RTT_CORR_EIGH_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0058))
+#define DBRP_RTT_CORR_FULL_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x005C))
+#define DBRP_RTT_CORR_HALF_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0060))
+#define DBRP_RTT_CORR_QUAR_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0064))
+#define DBRP_RTT_CORR_EIGH_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0068))
+#define DBRP_RTT_CORR_PATTERN_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x006C))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0070))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0074))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0078))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x007C))
+
+
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_LSB (0)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_CORR_ENERGY_ENERGY_LSB (0)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_WIDTH (9)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_LSB (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_WIDTH (1)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_MASK (0x00000040)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_BIT (0x00000040)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_LSB (0)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_WIDTH (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_MASK (0x0000003F)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_CORRSER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_97.h
new file mode 100644
index 0000000..70ae320
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_97.h
@@ -0,0 +1,229 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_CORRSER_H_
+#define _CPH_1X_RXBRP_CORRSER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_CORR_SER_REG_BASE (0xAC850000)
+
+#define RXBRP_C_CORR_SER_end (RXBRP_C_CORR_SER_REG_BASE + 0x007C + 1*4)
+
+
+
+#define DBRP_RTT_CORR_BUF_IDX ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0000))
+#define DBRP_RTT_CORR_ENERGY ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0004))
+#define DBRP_RTT_CORR_RSLT0 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0008))
+#define DBRP_RTT_CORR_RSLT1 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x000C))
+#define DBRP_RTT_CORR_RSLT2 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0010))
+#define DBRP_RTT_CORR_RSLT3 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0014))
+#define DBRP_RTT_CORR_RSLT4 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0018))
+#define DBRP_RTT_CORR_RSLT5 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x001C))
+#define DBRP_RTT_CORR_RSLT6 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0020))
+#define DBRP_RTT_CORR_RSLT7 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0024))
+#define DBRP_RTT_CORR_RSLT8 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0028))
+#define DBRP_RTT_CORR_RSLT9 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x002C))
+#define DBRP_RTT_CORR_RSLT10 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0030))
+#define DBRP_RTT_CORR_RSLT11 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0034))
+#define DBRP_RTT_CORR_RSLT12 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0038))
+#define DBRP_RTT_CORR_RSLT13 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x003C))
+#define DBRP_RTT_CORR_RSLT14 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0040))
+#define DBRP_RTT_CORR_RSLT15 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0044))
+#define DBRP_RTT_CORR_RSLT16 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0048))
+#define DBRP_RTT_CORR_RSLT_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x004C))
+#define DBRP_RTT_CORR_FULL_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0050))
+#define DBRP_RTT_CORR_HALF_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0054))
+#define DBRP_RTT_CORR_QUAR_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0058))
+#define DBRP_RTT_CORR_EIGH_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x005C))
+#define DBRP_RTT_CORR_FULL_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0060))
+#define DBRP_RTT_CORR_HALF_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0064))
+#define DBRP_RTT_CORR_QUAR_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0068))
+#define DBRP_RTT_CORR_EIGH_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x006C))
+#define DBRP_RTT_CORR_PATTERN_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0070))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0074))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0078))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x007C))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0080))
+
+
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_LSB (0)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_CORR_ENERGY_ENERGY_LSB (0)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_WIDTH (9)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT16_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT16_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT16_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_LSB (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_WIDTH (1)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_MASK (0x00000040)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_BIT (0x00000040)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_LSB (0)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_WIDTH (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_MASK (0x0000003F)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_CORRSER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpdma.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpdma.h
new file mode 100644
index 0000000..7ef6a48
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpdma.h
@@ -0,0 +1,84 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_DMA_H_
+#define _CPH_1X_RXBRP_DMA_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_1XRTT_DMA_REG_BASE (0x00000000)
+
+#define RXBRP_C_1XRTT_DMA_end (RXBRP_C_1XRTT_DMA_REG_BASE + 0x0010 + 1*4)
+
+
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0000))
+#define DBRP_RTT_FCH_SCALE_PARAM_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0004))
+#define DBRP_RTT_FCH_SCALE_PARAM1_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0008))
+#define DBRP_RTT_SCH_SCALE_PARAM_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x000C))
+#define DBRP_RTT_SCH_SCALE_PARAM1_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0010))
+
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F)
+
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF)
+
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_DMA_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma.h
new file mode 100644
index 0000000..7e377b3
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxbrpwctdma_93.h"
+#elif defined(__MD95__)
+#include "cph1xrxbrpwctdma_93.h"
+#elif defined(__MD97__)
+#include "cph1xrxbrpwctdma_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_93.h
new file mode 100644
index 0000000..bbc358c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_93.h
@@ -0,0 +1,510 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
+#define _CPH_1X_RX_BRP_WCT_DMA_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DMA_REG_BASE (0xAD150000)
+
+#define RXBRP_WCT_DMA_end (RXBRP_WCT_DMA_REG_BASE + 0x00B4 + 1*4)
+
+
+
+#define DBRP_DMA_RESET ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0000))
+#define DBRP_DMA_CH0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0004))
+#define DBRP_DMA_CH0_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0008))
+#define DBRP_DMA_CH0_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x000C))
+#define DBRP_DMA_CH0_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0010))
+#define DBRP_DMA_CH0_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0014))
+#define DBRP_DMA_CH0_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0018))
+#define DBRP_DMA_CH1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x001C))
+#define DBRP_DMA_CH1_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0020))
+#define DBRP_DMA_CH1_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0024))
+#define DBRP_DMA_CH1_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0028))
+#define DBRP_DMA_CH1_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x002C))
+#define DBRP_DMA_CH1_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0030))
+#define DBRP_DMA_CH2 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0034))
+#define DBRP_DMA_CH2_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0038))
+#define DBRP_DMA_CH2_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x003C))
+#define DBRP_DMA_CH2_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0040))
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0044))
+#define DBRP_DMA_CH2_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0048))
+#define DBRP_DMA_CH2_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x004C))
+#define DBRP_DMA_CH2_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0050))
+#define DBRP_DMA_CH2_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0054))
+#define DBRP_DMA_CH3 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0058))
+#define DBRP_DMA_CH3_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x005C))
+#define DBRP_DMA_CH3_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0060))
+#define DBRP_DMA_CH3_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0064))
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0068))
+#define DBRP_DMA_CH3_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x006C))
+#define DBRP_DMA_CH3_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0070))
+#define DBRP_DMA_CH3_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0074))
+#define DBRP_DMA_CH3_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0078))
+#define DBRP_DMA_CH4 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x007C))
+#define DBRP_DMA_CH4_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0080))
+#define DBRP_DMA_CH4_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0084))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0088))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x008C))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0090))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0094))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0098))
+#define DBRP_DMA_CH4_CTRL_DATA_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x009C))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A0))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A4))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A8))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00AC))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B0))
+#define DBRP_DMA_CH4_CTRL_DATA_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B4))
+
+#define DBRP_DMA_DEBUG_START ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00E0))
+
+
+#define DBRP_DMA_RESET_SW_RESET_LSB (0)
+#define DBRP_DMA_RESET_SW_RESET_WIDTH (1)
+#define DBRP_DMA_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_DMA_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_TRIG_LSB (0)
+#define DBRP_DMA_CH0_TRIG_WIDTH (1)
+#define DBRP_DMA_CH0_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH0_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH0_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH0_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH0_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH0_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH0_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH0_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH0_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_TRIG_LSB (0)
+#define DBRP_DMA_CH1_TRIG_WIDTH (1)
+#define DBRP_DMA_CH1_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH1_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH1_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH1_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH1_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH1_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH1_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH1_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH1_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_TRIG_LSB (0)
+#define DBRP_DMA_CH2_TRIG_WIDTH (1)
+#define DBRP_DMA_CH2_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH2_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH2_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH2_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH2_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH2_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH2_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH2_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_TRIG_LSB (0)
+#define DBRP_DMA_CH3_TRIG_WIDTH (1)
+#define DBRP_DMA_CH3_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH3_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH3_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH3_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH3_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH3_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH3_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH3_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_TRIG_LSB (0)
+#define DBRP_DMA_CH4_TRIG_WIDTH (1)
+#define DBRP_DMA_CH4_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH4_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_LSB (3)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_MASK (0x00000008)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_LSB (2)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_MASK (0x00000004)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_BIT (0x00000004)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_LSB (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_LSB (0)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_LSB (20)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_MASK (0x00F00000)
+
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_MASK (0x000F0000)
+
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_LSB (9)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_MASK (0x0000FE00)
+
+#define DBRP_DMA_CH4_CTRL_CC_EN_LSB (7)
+#define DBRP_DMA_CH4_CTRL_CC_EN_WIDTH (2)
+#define DBRP_DMA_CH4_CTRL_CC_EN_MASK (0x00000180)
+
+#define DBRP_DMA_CH4_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH4_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH4_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH4_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH4_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_MASK (0x0000FFFF)
+
+
+#endif //#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_97.h
new file mode 100644
index 0000000..b6e8774
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_97.h
@@ -0,0 +1,510 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
+#define _CPH_1X_RX_BRP_WCT_DMA_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DMA_REG_BASE (0xAC950000)
+
+#define RXBRP_WCT_DMA_end (RXBRP_WCT_DMA_REG_BASE + 0x00B4 + 1*4)
+
+
+
+#define DBRP_DMA_RESET ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0000))
+#define DBRP_DMA_CH0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0004))
+#define DBRP_DMA_CH0_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0008))
+#define DBRP_DMA_CH0_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x000C))
+#define DBRP_DMA_CH0_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0010))
+#define DBRP_DMA_CH0_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0014))
+#define DBRP_DMA_CH0_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0018))
+#define DBRP_DMA_CH1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x001C))
+#define DBRP_DMA_CH1_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0020))
+#define DBRP_DMA_CH1_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0024))
+#define DBRP_DMA_CH1_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0028))
+#define DBRP_DMA_CH1_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x002C))
+#define DBRP_DMA_CH1_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0030))
+#define DBRP_DMA_CH2 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0034))
+#define DBRP_DMA_CH2_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0038))
+#define DBRP_DMA_CH2_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x003C))
+#define DBRP_DMA_CH2_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0040))
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0044))
+#define DBRP_DMA_CH2_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0048))
+#define DBRP_DMA_CH2_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x004C))
+#define DBRP_DMA_CH2_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0050))
+#define DBRP_DMA_CH2_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0054))
+#define DBRP_DMA_CH3 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0058))
+#define DBRP_DMA_CH3_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x005C))
+#define DBRP_DMA_CH3_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0060))
+#define DBRP_DMA_CH3_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0064))
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0068))
+#define DBRP_DMA_CH3_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x006C))
+#define DBRP_DMA_CH3_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0070))
+#define DBRP_DMA_CH3_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0074))
+#define DBRP_DMA_CH3_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0078))
+#define DBRP_DMA_CH4 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x007C))
+#define DBRP_DMA_CH4_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0080))
+#define DBRP_DMA_CH4_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0084))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0088))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x008C))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0090))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0094))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0098))
+#define DBRP_DMA_CH4_CTRL_DATA_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x009C))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A0))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A4))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A8))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00AC))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B0))
+#define DBRP_DMA_CH4_CTRL_DATA_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B4))
+
+#define DBRP_DMA_DEBUG_START ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00E0))
+
+
+#define DBRP_DMA_RESET_SW_RESET_LSB (0)
+#define DBRP_DMA_RESET_SW_RESET_WIDTH (1)
+#define DBRP_DMA_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_DMA_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_TRIG_LSB (0)
+#define DBRP_DMA_CH0_TRIG_WIDTH (1)
+#define DBRP_DMA_CH0_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH0_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH0_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH0_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH0_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH0_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH0_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH0_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH0_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_TRIG_LSB (0)
+#define DBRP_DMA_CH1_TRIG_WIDTH (1)
+#define DBRP_DMA_CH1_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH1_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH1_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH1_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH1_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH1_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH1_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH1_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH1_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_TRIG_LSB (0)
+#define DBRP_DMA_CH2_TRIG_WIDTH (1)
+#define DBRP_DMA_CH2_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH2_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH2_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH2_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH2_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH2_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH2_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH2_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_TRIG_LSB (0)
+#define DBRP_DMA_CH3_TRIG_WIDTH (1)
+#define DBRP_DMA_CH3_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH3_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH3_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH3_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH3_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH3_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH3_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH3_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_TRIG_LSB (0)
+#define DBRP_DMA_CH4_TRIG_WIDTH (1)
+#define DBRP_DMA_CH4_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH4_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_LSB (3)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_MASK (0x00000008)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_LSB (2)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_MASK (0x00000004)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_BIT (0x00000004)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_LSB (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_LSB (0)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_LSB (20)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_MASK (0x00F00000)
+
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_MASK (0x000F0000)
+
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_LSB (9)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_MASK (0x0000FE00)
+
+#define DBRP_DMA_CH4_CTRL_CC_EN_LSB (7)
+#define DBRP_DMA_CH4_CTRL_CC_EN_WIDTH (2)
+#define DBRP_DMA_CH4_CTRL_CC_EN_MASK (0x00000180)
+
+#define DBRP_DMA_CH4_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH4_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH4_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH4_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH4_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_MASK (0x0000FFFF)
+
+
+#endif //#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen.h
new file mode 100644
index 0000000..e25af1d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxeventgen_g93.h"
+#elif defined(__MD95__)
+#include "cph1xrxeventgen_g95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cph1xrxeventgen_g97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g93.h
new file mode 100644
index 0000000..4e90e88
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g93.h
@@ -0,0 +1,586 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_EVENTGEN_H_
+#define _CPH_1X_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_EVENTGEN_REG_BASE (0xA7060000)
+
+#define ST1X_RX_EVENTGEN_end (ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + 38*4)
+
+
+#define ST1X_RXBRP_EVENT_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0000))
+#define ST1X_RXBRP_EVENT_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0004))
+#define ST1X_uSIP_IRQ_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0008))
+#define ST1X_uSIP_IRQ_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x000C))
+#define ST1X_uSIP_IRQ_CLR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0010))
+#define ST1X_uSIP_IRQ_SRC ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0014))
+#define ST1X_uSIP_IRQ_ISR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0018))
+#define ST1X_RXDFE_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x001C))
+#define ST1X_RXDFE_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0020))
+#define ST1X_DBG_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0024))
+#define ST1X_DBG_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0028))
+#define ST1X_TTR_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x002C))
+#define ST1X_TTR_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0030))
+#define ST1X_DVFS_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0034))
+#define ST1X_RX_BSIRD_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define ST1X_RX_BSI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 49
+#define ST1X_RX_MIPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 81
+#define ST1X_RX_BPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 37
+
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define ST1X_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define ST1X_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define ST1X_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define ST1X_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define ST1X_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define ST1X_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define ST1X_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define ST1X_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define ST1X_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define ST1X_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define ST1X_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define ST1X_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define ST1X_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define ST1X_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define ST1X_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define ST1X_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define ST1X_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define ST1X_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define ST1X_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define ST1X_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define ST1X_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define ST1X_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define ST1X_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define ST1X_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define ST1X_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define ST1X_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define ST1X_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define ST1X_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define ST1X_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define ST1X_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define ST1X_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define ST1X_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define ST1X_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define ST1X_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define ST1X_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define ST1X_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define ST1X_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define ST1X_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define ST1X_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define ST1X_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define ST1X_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define ST1X_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define ST1X_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define ST1X_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define ST1X_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define ST1X_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define ST1X_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define ST1X_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define ST1X_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define ST1X_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define ST1X_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define ST1X_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define ST1X_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define ST1X_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define ST1X_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define ST1X_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define ST1X_RXDFE_ON_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RXDFE_OFF_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DBG_ON_EVENT_EN_LSB (31)
+#define ST1X_DBG_ON_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_DBG_OFF_EVENT_EN_LSB (31)
+#define ST1X_DBG_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_TTR_ON_EVENT_EN_LSB (31)
+#define ST1X_TTR_ON_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_TTR_OFF_EVENT_EN_LSB (31)
+#define ST1X_TTR_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DVFS_EVENT_EN_LSB (31)
+#define ST1X_DVFS_EVENT_EN_WIDTH (1)
+#define ST1X_DVFS_EVENT_EN_MASK (0x80000000)
+#define ST1X_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DVFS_EVENT_MODE_LSB (30)
+#define ST1X_DVFS_EVENT_MODE_WIDTH (1)
+#define ST1X_DVFS_EVENT_MODE_MASK (0x40000000)
+#define ST1X_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSIRD_EVENT_EN_LSB (31)
+#define ST1X_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSI_EVENT_EN_LSB (31)
+#define ST1X_RX_BSI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_MIPI_EVENT_EN_LSB (31)
+#define ST1X_RX_MIPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BPI_EVENT_EN_LSB (31)
+#define ST1X_RX_BPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_1X_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g95.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g95.h
new file mode 100644
index 0000000..4356073
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g95.h
@@ -0,0 +1,586 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_EVENTGEN_H_
+#define _CPH_1X_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_EVENTGEN_REG_BASE (0xA6210000)
+
+#define ST1X_RX_EVENTGEN_end (ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + 38*4)
+
+
+#define ST1X_RXBRP_EVENT_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0000))
+#define ST1X_RXBRP_EVENT_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0004))
+#define ST1X_uSIP_IRQ_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0008))
+#define ST1X_uSIP_IRQ_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x000C))
+#define ST1X_uSIP_IRQ_CLR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0010))
+#define ST1X_uSIP_IRQ_SRC ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0014))
+#define ST1X_uSIP_IRQ_ISR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0018))
+#define ST1X_RXDFE_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x001C))
+#define ST1X_RXDFE_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0020))
+#define ST1X_DBG_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0024))
+#define ST1X_DBG_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0028))
+#define ST1X_TTR_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x002C))
+#define ST1X_TTR_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0030))
+#define ST1X_DVFS_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0034))
+#define ST1X_RX_BSIRD_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define ST1X_RX_BSI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 49
+#define ST1X_RX_MIPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 81
+#define ST1X_RX_BPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 37
+
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define ST1X_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define ST1X_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define ST1X_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define ST1X_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define ST1X_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define ST1X_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define ST1X_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define ST1X_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define ST1X_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define ST1X_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define ST1X_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define ST1X_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define ST1X_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define ST1X_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define ST1X_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define ST1X_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define ST1X_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define ST1X_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define ST1X_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define ST1X_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define ST1X_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define ST1X_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define ST1X_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define ST1X_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define ST1X_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define ST1X_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define ST1X_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define ST1X_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define ST1X_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define ST1X_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define ST1X_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define ST1X_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define ST1X_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define ST1X_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define ST1X_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define ST1X_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define ST1X_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define ST1X_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define ST1X_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define ST1X_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define ST1X_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define ST1X_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define ST1X_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define ST1X_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define ST1X_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define ST1X_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define ST1X_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define ST1X_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define ST1X_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define ST1X_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define ST1X_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define ST1X_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define ST1X_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define ST1X_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define ST1X_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define ST1X_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define ST1X_RXDFE_ON_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RXDFE_OFF_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DBG_ON_EVENT_EN_LSB (31)
+#define ST1X_DBG_ON_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_DBG_OFF_EVENT_EN_LSB (31)
+#define ST1X_DBG_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_TTR_ON_EVENT_EN_LSB (31)
+#define ST1X_TTR_ON_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_TTR_OFF_EVENT_EN_LSB (31)
+#define ST1X_TTR_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DVFS_EVENT_EN_LSB (31)
+#define ST1X_DVFS_EVENT_EN_WIDTH (1)
+#define ST1X_DVFS_EVENT_EN_MASK (0x80000000)
+#define ST1X_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DVFS_EVENT_MODE_LSB (30)
+#define ST1X_DVFS_EVENT_MODE_WIDTH (1)
+#define ST1X_DVFS_EVENT_MODE_MASK (0x40000000)
+#define ST1X_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSIRD_EVENT_EN_LSB (31)
+#define ST1X_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSI_EVENT_EN_LSB (31)
+#define ST1X_RX_BSI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_MIPI_EVENT_EN_LSB (31)
+#define ST1X_RX_MIPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BPI_EVENT_EN_LSB (31)
+#define ST1X_RX_BPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_1X_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g97.h
new file mode 100644
index 0000000..1fa948f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g97.h
@@ -0,0 +1,421 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_EVENTGEN_H_
+#define _CPH_1X_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_EVENTGEN_REG_BASE (0xA8200000)
+
+#define ST1X_RX_EVENTGEN_end (ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + 38*4)
+
+
+#define ST1X_RXBRP_EVENT_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0000))
+#define ST1X_RXBRP_EVENT_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0004))
+
+#define ST1X_RXDFE_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x001C))
+#define ST1X_RXDFE_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0020))
+#define ST1X_DBG_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0024))
+#define ST1X_DBG_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0028))
+#define ST1X_TTR_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x002C))
+#define ST1X_TTR_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0030))
+#define ST1X_DVFS_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0034))
+
+#define ST1X_WDG_EN ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0040))
+#define ST1X_WDG_BOUND_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0044))
+#define ST1X_WDG_CHKPT_UNCHK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0048))
+#define ST1X_WDG_CHKPT_TIME_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x004C))
+#define ST1X_WDG_URGENT_SW_CLR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0060))
+#define ST1X_WDG_DBG ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0064))
+
+#define ST1X_uSIP_IRQ_OFFSET_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0080))
+#define ST1X_uSIP_IRQ_MASK_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0084))
+#define ST1X_uSIP_IRQ_CLR_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0088))
+#define ST1X_uSIP_IRQ_SRC_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x008C))
+#define ST1X_uSIP_IRQ_ISR_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0090))
+#define ST1X_uSIP_IRQ_LATCH_TIME_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0094))
+
+#define ST1X_uSIP_IRQ_OFFSET_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00A0))
+#define ST1X_uSIP_IRQ_MASK_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00A4))
+#define ST1X_uSIP_IRQ_CLR_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00A8))
+#define ST1X_uSIP_IRQ_SRC_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00AC))
+#define ST1X_uSIP_IRQ_ISR_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00B0))
+#define ST1X_uSIP_IRQ_LATCH_TIME_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00B4))
+
+#define ST1X_uSIP_IRQ_OFFSET_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00C0))
+#define ST1X_uSIP_IRQ_MASK_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00C4))
+#define ST1X_uSIP_IRQ_CLR_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00C8))
+#define ST1X_uSIP_IRQ_SRC_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00CC))
+#define ST1X_uSIP_IRQ_ISR_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00D0))
+#define ST1X_uSIP_IRQ_LATCH_TIME_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00D4))
+
+#define ST1X_uSIP_IRQ_OFFSET_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00E0))
+#define ST1X_uSIP_IRQ_MASK_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00E4))
+#define ST1X_uSIP_IRQ_CLR_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00E8))
+#define ST1X_uSIP_IRQ_SRC_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00EC))
+#define ST1X_uSIP_IRQ_ISR_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00F0))
+#define ST1X_uSIP_IRQ_LATCH_TIME_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00F4))
+
+#define ST1X_uSIP_IRQ_STATUS ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0100))
+
+
+
+
+
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+
+#define ST1X_RXDFE_ON_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RXDFE_OFF_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DBG_ON_EVENT_EN_LSB (31)
+#define ST1X_DBG_ON_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_DBG_OFF_EVENT_EN_LSB (31)
+#define ST1X_DBG_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_TTR_ON_EVENT_EN_LSB (31)
+#define ST1X_TTR_ON_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_TTR_OFF_EVENT_EN_LSB (31)
+#define ST1X_TTR_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DVFS_EVENT_EN_LSB (31)
+#define ST1X_DVFS_EVENT_EN_WIDTH (1)
+#define ST1X_DVFS_EVENT_EN_MASK (0x80000000)
+#define ST1X_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DVFS_EVENT_MODE_LSB (30)
+#define ST1X_DVFS_EVENT_MODE_WIDTH (1)
+#define ST1X_DVFS_EVENT_MODE_MASK (0x40000000)
+#define ST1X_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_WDG_EN_WDG_EN_LSB (0)
+#define ST1X_WDG_EN_WDG_EN_WIDTH (1)
+#define ST1X_WDG_EN_WDG_EN_MASK (0x00000001)
+
+#define ST1X_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_LSB (3)
+#define ST1X_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_WIDTH (11)
+#define ST1X_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_MASK (0x00003FF8)
+
+#define ST1X_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_LSB (0)
+#define ST1X_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_WIDTH (1)
+#define ST1X_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_MASK (0x00000001)
+
+
+#define ST1X_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_LSB (3)
+#define ST1X_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_WIDTH (17)
+#define ST1X_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_MASK (0x0000FFF8)
+
+#define ST1X_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_0_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_0_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_0_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_0_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_0_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_0_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_0_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_0_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_0_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_1_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_1_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_1_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_1_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_1_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_1_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_1_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_1_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_1_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_1_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_1_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_2_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_2_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_2_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_2_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_2_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_2_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_2_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_2_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_2_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_2_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_2_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_2_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_3_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_3_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_3_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_3_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_3_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_3_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_3_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_3_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_3_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_3_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_3_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_3_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_0_LSB (0)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_0_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_0_MASK (0x00000001)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_1_LSB (1)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_1_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_1_MASK (0x00000002)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_2_LSB (2)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_2_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_2_MASK (0x00000004)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_3_LSB (1)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_3_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_3_MASK (0x00000008)
+
+#endif //#ifndef _CPH_1X_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxslp.h b/mcu/interface/l1/cl1/common/HW/cph1xrxslp.h
new file mode 100644
index 0000000..ec12e35
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxslp.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXSLP_H_
+#define _CPH_1X_RXSLP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_SLP_REG_BASE (0x00000000)
+
+#define ST1X_RX_SLP_end (ST1X_RX_SLP_REG_BASE + 0xA60D0060 + 1*4)
+
+
+
+#define ST1X_SM_CON ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0000))
+#define ST1X_SM_PAUSE_TIME ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0004))
+#define ST1X_SM_STA ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0008))
+#define ST1X_SM_CFG ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D000C))
+#define ST1X_SM_START_TIME ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0010))
+#define ST1X_SM_SW_WAKE_CON ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0014))
+#define ST1X_SM_STEP_FRAC ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0018))
+#define ST1X_SM_SYSCNT_F32K_INT ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D001C))
+#define ST1X_SM_SYSCNT_F32K_FRAC ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0020))
+#define ST1X_SM_SUPFRM_F32K_L ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0024))
+#define ST1X_SM_SUPFRM_F32K_H ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0028))
+#define ST1X_SM_SLEEP_OFFSET ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D002C))
+#define ST1X_SM_TIME_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0030))
+#define ST1X_SM_SUPFRM_TIME_L_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0034))
+#define ST1X_SM_SUPFRM_TIME_H_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0038))
+#define ST1X_SM_TIME_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D003C))
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0040))
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0044))
+#define ST1X_SM_TIME_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0048))
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D004C))
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0050))
+#define ST1X_SM_FINAL_PAUSE_DURATION ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0054))
+#define ST1X_SM_PRESLP_CNT ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0058))
+#define ST1X_SM_SLT_START_F32K ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D005C))
+#define ST1X_SM_WAKEUP_START_F32K ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0060))
+
+
+#define ST1X_SM_CON_CLR_CNT_LSB (15)
+#define ST1X_SM_CON_CLR_CNT_WIDTH (1)
+#define ST1X_SM_CON_CLR_CNT_MASK (0x00008000)
+#define ST1X_SM_CON_CLR_CNT_BIT (0x00008000)
+
+#define ST1X_SM_CON_PAUSE_START_LSB (1)
+#define ST1X_SM_CON_PAUSE_START_WIDTH (1)
+#define ST1X_SM_CON_PAUSE_START_MASK (0x00000002)
+#define ST1X_SM_CON_PAUSE_START_BIT (0x00000002)
+
+#define ST1X_SM_CON_PAUSE_MODE_LSB (0)
+#define ST1X_SM_CON_PAUSE_MODE_WIDTH (1)
+#define ST1X_SM_CON_PAUSE_MODE_MASK (0x00000001)
+#define ST1X_SM_CON_PAUSE_MODE_BIT (0x00000001)
+
+#define ST1X_SM_PAUSE_TIME_PAUSE_TIME_LSB (0)
+#define ST1X_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32)
+#define ST1X_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_STA_SLP_EXIT_CPL_LSB (7)
+#define ST1X_SM_STA_SLP_EXIT_CPL_WIDTH (1)
+#define ST1X_SM_STA_SLP_EXIT_CPL_MASK (0x00000080)
+#define ST1X_SM_STA_SLP_EXIT_CPL_BIT (0x00000080)
+
+#define ST1X_SM_STA_PAUSE_CPL_LSB (6)
+#define ST1X_SM_STA_PAUSE_CPL_WIDTH (1)
+#define ST1X_SM_STA_PAUSE_CPL_MASK (0x00000040)
+#define ST1X_SM_STA_PAUSE_CPL_BIT (0x00000040)
+
+#define ST1X_SM_CFG_SW_WAKE_EN_LSB (8)
+#define ST1X_SM_CFG_SW_WAKE_EN_WIDTH (1)
+#define ST1X_SM_CFG_SW_WAKE_EN_MASK (0x00000100)
+#define ST1X_SM_CFG_SW_WAKE_EN_BIT (0x00000100)
+
+#define ST1X_SM_CFG_IRQ_EN_LSB (1)
+#define ST1X_SM_CFG_IRQ_EN_WIDTH (1)
+#define ST1X_SM_CFG_IRQ_EN_MASK (0x00000002)
+#define ST1X_SM_CFG_IRQ_EN_BIT (0x00000002)
+
+#define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_LSB (0)
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1)
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001)
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001)
+
+#define ST1X_SM_STEP_FRAC_STEP_INT_LSB (18)
+#define ST1X_SM_STEP_FRAC_STEP_INT_WIDTH (9)
+#define ST1X_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000)
+
+#define ST1X_SM_STEP_FRAC_STEP_FRAC_LSB (0)
+#define ST1X_SM_STEP_FRAC_STEP_FRAC_WIDTH (18)
+#define ST1X_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF)
+
+#define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0)
+#define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20)
+#define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF)
+
+#define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0)
+#define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18)
+#define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF)
+
+#define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0)
+#define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32)
+#define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0)
+#define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4)
+#define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F)
+
+#define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14)
+#define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC)
+
+#define ST1X_SM_TIME_START_SM_TIME_START_LSB (0)
+#define ST1X_SM_TIME_START_SM_TIME_START_WIDTH (20)
+#define ST1X_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32)
+#define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4)
+#define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F)
+
+#define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0)
+#define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20)
+#define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32)
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4)
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F)
+
+#define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0)
+#define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20)
+#define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32)
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4)
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F)
+
+#define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0)
+#define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32)
+#define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0)
+#define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6)
+#define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F)
+
+#define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0)
+#define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6)
+#define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F)
+
+#define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0)
+#define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32)
+#define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_1X_RXSLP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg.h
new file mode 100644
index 0000000..a8c8648
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg.h
@@ -0,0 +1,46 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xschreg_93.h"
+#elif defined(__MD95__)
+#include "cph1xschreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cph1xschreg_97.h"
+
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg_93.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg_93.h
new file mode 100644
index 0000000..cf3d2f3
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg_93.h
@@ -0,0 +1,529 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_SCH_H_
+#define _CPH_1X_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define SEARCHER_REG_BASE (0xA7880000)
+
+#define SEARCHER_end (SEARCHER_REG_BASE + 0x0b60 + 1*4)
+
+
+
+#define SR_CTL1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0000))
+#define SR_CORR_LEN ((APBADDR32)(SEARCHER_REG_BASE + 0x0004))
+#define SR_NONCO_PASS ((APBADDR32)(SEARCHER_REG_BASE + 0x0008))
+#define SR_AUX_PLT_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x000C))
+#define SR_WIND ((APBADDR32)(SEARCHER_REG_BASE + 0x0010))
+#define SR_D1_THRES ((APBADDR32)(SEARCHER_REG_BASE + 0x0014))
+#define SR_AUX_OFF_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x0018))
+#define SR_OUTPUT ((APBADDR32)(SEARCHER_REG_BASE + 0x001C))
+#define SR_TST_CTL ((APBADDR32)(SEARCHER_REG_BASE + 0x0020))
+#define SR_TST_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0024))
+#define SR_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0028))
+#define SR_STAT ((APBADDR32)(SEARCHER_REG_BASE + 0x002c))
+#define SR_SMPL_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0030))
+#define SR_THRESH ((APBADDR32)(SEARCHER_REG_BASE + 0x0034))
+#define SR_WIN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0038))
+#define SR_INBUF_TSTCTL ((APBADDR32)(SEARCHER_REG_BASE + 0x003C))
+#define SR_INBUF_TSTDAT ((APBADDR32)(SEARCHER_REG_BASE + 0x0040))
+#define SR_PEAK1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0044))
+#define SR_PEAK2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0048))
+#define SR_PEAK3 ((APBADDR32)(SEARCHER_REG_BASE + 0x004C))
+#define SR_PEAK4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0050))
+#define SR_START_DLY ((APBADDR32)(SEARCHER_REG_BASE + 0x0054))
+#define SR_PN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0058))
+#define SR_PAGE_NUM ((APBADDR32)(SEARCHER_REG_BASE + 0x005C))
+#define SR_DATA_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0060))
+#define SR_IC_DLY_CFG ((APBADDR32)(SEARCHER_REG_BASE + 0x0064))
+#define SR_IC_DLY_CFG1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0068))
+#define SR_WIND_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0110))
+#define SR_PN_OFFSET_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0158))
+#define SR_DATA_CNT_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0160))
+#define SR_WIND_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0210))
+#define SR_PN_OFFSET_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0258))
+#define SR_DATA_CNT_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0260))
+#define SR_WIND_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0310))
+#define SR_PN_OFFSET_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0358))
+#define SR_DATA_CNT_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0360))
+#define SR_WIND_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0410))
+#define SR_PN_OFFSET_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0458))
+#define SR_DATA_CNT_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0460))
+#define SR_WIND_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0510))
+#define SR_PN_OFFSET_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0558))
+#define SR_DATA_CNT_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0560))
+#define SR_WIND_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0610))
+#define SR_PN_OFFSET_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0658))
+#define SR_DATA_CNT_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0660))
+#define SR_WIND_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0710))
+#define SR_PN_OFFSET_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0758))
+#define SR_DATA_CNT_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0760))
+#define SR_WIND_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0810))
+#define SR_PN_OFFSET_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0858))
+#define SR_DATA_CNT_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0860))
+#define SR_WIND_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0910))
+#define SR_PN_OFFSET_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0958))
+#define SR_DATA_CNT_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0960))
+#define SR_WIND_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a10))
+#define SR_PN_OFFSET_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a58))
+#define SR_DATA_CNT_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a60))
+#define SR_WIND_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b10))
+#define SR_PN_OFFSET_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b58))
+#define SR_DATA_CNT_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b60))
+
+
+#define SR_CTL1_OUT_SEL_LSB (16)
+#define SR_CTL1_OUT_SEL_WIDTH (2)
+#define SR_CTL1_OUT_SEL_MASK (0x00030000)
+
+#define SR_CTL1_THRESH_EN_LSB (14)
+#define SR_CTL1_THRESH_EN_WIDTH (1)
+#define SR_CTL1_THRESH_EN_MASK (0x00004000)
+#define SR_CTL1_THRESH_EN_BIT (0x00004000)
+
+#define SR_CTL1_CLR_BUF_CNTRS_LSB (12)
+#define SR_CTL1_CLR_BUF_CNTRS_WIDTH (1)
+#define SR_CTL1_CLR_BUF_CNTRS_MASK (0x00001000)
+#define SR_CTL1_CLR_BUF_CNTRS_BIT (0x00001000)
+
+#define SR_CTL1_TONE_LSB (11)
+#define SR_CTL1_TONE_WIDTH (1)
+#define SR_CTL1_TONE_MASK (0x00000800)
+#define SR_CTL1_TONE_BIT (0x00000800)
+
+#define SR_CTL1_TC_LSB (9)
+#define SR_CTL1_TC_WIDTH (2)
+#define SR_CTL1_TC_MASK (0x00000600)
+
+#define SR_CTL1_AUX_PILOT_EN_LSB (7)
+#define SR_CTL1_AUX_PILOT_EN_WIDTH (1)
+#define SR_CTL1_AUX_PILOT_EN_MASK (0x00000080)
+#define SR_CTL1_AUX_PILOT_EN_BIT (0x00000080)
+
+#define SR_CTL1_COHERENT_LSB (6)
+#define SR_CTL1_COHERENT_WIDTH (1)
+#define SR_CTL1_COHERENT_MASK (0x00000040)
+#define SR_CTL1_COHERENT_BIT (0x00000040)
+
+#define SR_CTL1_FREQ_DOMAIN_LSB (5)
+#define SR_CTL1_FREQ_DOMAIN_WIDTH (1)
+#define SR_CTL1_FREQ_DOMAIN_MASK (0x00000020)
+#define SR_CTL1_FREQ_DOMAIN_BIT (0x00000020)
+
+#define SR_CTL1_LOAD_TWO_BUF_LSB (3)
+#define SR_CTL1_LOAD_TWO_BUF_WIDTH (1)
+#define SR_CTL1_LOAD_TWO_BUF_MASK (0x00000008)
+#define SR_CTL1_LOAD_TWO_BUF_BIT (0x00000008)
+
+#define SR_CTL1_INPUT_BUF_EN_LSB (2)
+#define SR_CTL1_INPUT_BUF_EN_WIDTH (1)
+#define SR_CTL1_INPUT_BUF_EN_MASK (0x00000004)
+#define SR_CTL1_INPUT_BUF_EN_BIT (0x00000004)
+
+#define SR_CTL1_ACQ_MODE_EN_LSB (1)
+#define SR_CTL1_ACQ_MODE_EN_WIDTH (1)
+#define SR_CTL1_ACQ_MODE_EN_MASK (0x00000002)
+#define SR_CTL1_ACQ_MODE_EN_BIT (0x00000002)
+
+#define SR_CTL1_INIT_LSB (0)
+#define SR_CTL1_INIT_WIDTH (1)
+#define SR_CTL1_INIT_MASK (0x00000001)
+#define SR_CTL1_INIT_BIT (0x00000001)
+
+#define SR_CORR_LEN_D2_LSB (6)
+#define SR_CORR_LEN_D2_WIDTH (6)
+#define SR_CORR_LEN_D2_MASK (0x00000FC0)
+
+#define SR_CORR_LEN_D1_LSB (0)
+#define SR_CORR_LEN_D1_WIDTH (6)
+#define SR_CORR_LEN_D1_MASK (0x0000003F)
+
+#define SR_NONCO_PASS_D2MSB_LSB (7)
+#define SR_NONCO_PASS_D2MSB_WIDTH (6)
+#define SR_NONCO_PASS_D2MSB_MASK (0x00001F80)
+
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_LSB (6)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_WIDTH (1)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_MASK (0x00000040)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_BIT (0x00000040)
+
+#define SR_NONCO_PASS_D1LSB_LSB (0)
+#define SR_NONCO_PASS_D1LSB_WIDTH (6)
+#define SR_NONCO_PASS_D1LSB_MASK (0x0000003F)
+
+#define SR_AUX_PLT_WALSH_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_WIND_SIZE_LSB (0)
+#define SR_WIND_SIZE_WIDTH (15)
+#define SR_WIND_SIZE_MASK (0x00007FFF)
+
+#define SR_D1_THRES_CFG_LSB (0)
+#define SR_D1_THRES_CFG_WIDTH (16)
+#define SR_D1_THRES_CFG_MASK (0x0000FFFF)
+
+#define SR_AUX_OFF_WALSH_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_CODE_MASK (0x000001FF)
+
+#define SR_OUTPUT_WIN_OFFSET_LSB (17)
+#define SR_OUTPUT_WIN_OFFSET_WIDTH (9)
+#define SR_OUTPUT_WIN_OFFSET_MASK (0x03FE0000)
+
+#define SR_OUTPUT_E_L_IND_LSB (16)
+#define SR_OUTPUT_E_L_IND_WIDTH (1)
+#define SR_OUTPUT_E_L_IND_MASK (0x00010000)
+#define SR_OUTPUT_E_L_IND_BIT (0x00010000)
+
+#define SR_OUTPUT_METRIC_LSB (0)
+#define SR_OUTPUT_METRIC_WIDTH (16)
+#define SR_OUTPUT_METRIC_MASK (0x0000FFFF)
+
+#define SR_TST_CTL_TST_GO_LSB (4)
+#define SR_TST_CTL_TST_GO_WIDTH (1)
+#define SR_TST_CTL_TST_GO_MASK (0x00000010)
+#define SR_TST_CTL_TST_GO_BIT (0x00000010)
+
+#define SR_TST_CTL_TEST3_LSB (2)
+#define SR_TST_CTL_TEST3_WIDTH (1)
+#define SR_TST_CTL_TEST3_MASK (0x00000004)
+#define SR_TST_CTL_TEST3_BIT (0x00000004)
+
+#define SR_TST_CTL2_OBUF_ADDR_LSB (3)
+#define SR_TST_CTL2_OBUF_ADDR_WIDTH (9)
+#define SR_TST_CTL2_OBUF_ADDR_MASK (0x00000FF8)
+
+#define SR_TST_CTL2_OBF_RPTR_RST_LSB (2)
+#define SR_TST_CTL2_OBF_RPTR_RST_WIDTH (1)
+#define SR_TST_CTL2_OBF_RPTR_RST_MASK (0x00000004)
+#define SR_TST_CTL2_OBF_RPTR_RST_BIT (0x00000004)
+
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_LSB (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_WIDTH (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_MASK (0x00000002)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_BIT (0x00000002)
+
+#define SR_TST_CTL2_TEST_MODE_LSB (0)
+#define SR_TST_CTL2_TEST_MODE_WIDTH (1)
+#define SR_TST_CTL2_TEST_MODE_MASK (0x00000001)
+#define SR_TST_CTL2_TEST_MODE_BIT (0x00000001)
+
+#define SR_CTL2_CLK_ENB_LSB (0)
+#define SR_CTL2_CLK_ENB_WIDTH (1)
+#define SR_CTL2_CLK_ENB_MASK (0x00000001)
+#define SR_CTL2_CLK_ENB_BIT (0x00000001)
+
+#define SR_STAT_DONE_STAT_LSB (2)
+#define SR_STAT_DONE_STAT_WIDTH (1)
+#define SR_STAT_DONE_STAT_MASK (0x00000004)
+#define SR_STAT_DONE_STAT_BIT (0x00000004)
+
+#define SR_STAT_OBF_STAT_LSB (0)
+#define SR_STAT_OBF_STAT_WIDTH (1)
+#define SR_STAT_OBF_STAT_MASK (0x00000001)
+#define SR_STAT_OBF_STAT_BIT (0x00000001)
+
+#define SR_SMPL_CNT_SMPL_CNT_LSB (0)
+#define SR_SMPL_CNT_SMPL_CNT_WIDTH (10)
+#define SR_SMPL_CNT_SMPL_CNT_MASK (0x000003FF)
+
+#define SR_THRESH_OUTPUT_LSB (0)
+#define SR_THRESH_OUTPUT_WIDTH (16)
+#define SR_THRESH_OUTPUT_MASK (0x0000FFFF)
+
+#define SR_WIN_OFFSET_CFG_LSB (1)
+#define SR_WIN_OFFSET_CFG_WIDTH (9)
+#define SR_WIN_OFFSET_CFG_MASK (0x000003FE)
+
+#define SR_WIN_OFFSET_E_L_IND_LSB (0)
+#define SR_WIN_OFFSET_E_L_IND_WIDTH (1)
+#define SR_WIN_OFFSET_E_L_IND_MASK (0x00000001)
+#define SR_WIN_OFFSET_E_L_IND_BIT (0x00000001)
+
+#define SR_INBUF_TSTCTL_TST_EN_LSB (11)
+#define SR_INBUF_TSTCTL_TST_EN_WIDTH (1)
+#define SR_INBUF_TSTCTL_TST_EN_MASK (0x00000800)
+#define SR_INBUF_TSTCTL_TST_EN_BIT (0x00000800)
+
+#define SR_INBUF_TSTCTL_TST_ADDR_LSB (0)
+#define SR_INBUF_TSTCTL_TST_ADDR_WIDTH (11)
+#define SR_INBUF_TSTCTL_TST_ADDR_MASK (0x000007FF)
+
+#define SR_INBUF_TSTDAT_TSTDAT_LSB (0)
+#define SR_INBUF_TSTDAT_TSTDAT_WIDTH (16)
+#define SR_INBUF_TSTDAT_TSTDAT_MASK (0x0000FFFF)
+
+#define SR_PEAK1_WIN_OFFSET_LSB (17)
+#define SR_PEAK1_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK1_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK1_E_L_IND_LSB (16)
+#define SR_PEAK1_E_L_IND_WIDTH (1)
+#define SR_PEAK1_E_L_IND_MASK (0x00010000)
+#define SR_PEAK1_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK1_METRIC_LSB (0)
+#define SR_PEAK1_METRIC_WIDTH (16)
+#define SR_PEAK1_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK2_WIN_OFFSET_LSB (17)
+#define SR_PEAK2_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK2_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK2_E_L_IND_LSB (16)
+#define SR_PEAK2_E_L_IND_WIDTH (1)
+#define SR_PEAK2_E_L_IND_MASK (0x00010000)
+#define SR_PEAK2_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK2_METRIC_LSB (0)
+#define SR_PEAK2_METRIC_WIDTH (16)
+#define SR_PEAK2_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK3_WIN_OFFSET_LSB (17)
+#define SR_PEAK3_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK3_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK3_E_L_IND_LSB (16)
+#define SR_PEAK3_E_L_IND_WIDTH (1)
+#define SR_PEAK3_E_L_IND_MASK (0x00010000)
+#define SR_PEAK3_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK3_METRIC_LSB (0)
+#define SR_PEAK3_METRIC_WIDTH (16)
+#define SR_PEAK3_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK4_WIN_OFFSET_LSB (17)
+#define SR_PEAK4_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK4_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK4_E_L_IND_LSB (16)
+#define SR_PEAK4_E_L_IND_WIDTH (1)
+#define SR_PEAK4_E_L_IND_MASK (0x00010000)
+#define SR_PEAK4_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK4_METRIC_LSB (0)
+#define SR_PEAK4_METRIC_WIDTH (16)
+#define SR_PEAK4_METRIC_MASK (0x0000FFFF)
+
+#define SR_START_DLY_EN_LSB (20)
+#define SR_START_DLY_EN_WIDTH (1)
+#define SR_START_DLY_EN_MASK (0x00100000)
+#define SR_START_DLY_EN_BIT (0x00100000)
+
+#define SR_PN_OFFSET_CFG_LSB (0)
+#define SR_PN_OFFSET_CFG_WIDTH (15)
+#define SR_PN_OFFSET_CFG_MASK (0x00007FFF)
+
+#define SR_PAGE_NUM_CFG_LSB (0)
+#define SR_PAGE_NUM_CFG_WIDTH (4)
+#define SR_PAGE_NUM_CFG_MASK (0x0000000F)
+
+#define SR_DATA_CNT_READ_LSB (0)
+#define SR_DATA_CNT_READ_WIDTH (9)
+#define SR_DATA_CNT_READ_MASK (0x000001FF)
+
+#define SR_IC_DLY_CFG_DLY_MODE_LSB (6)
+#define SR_IC_DLY_CFG_DLY_MODE_WIDTH (2)
+#define SR_IC_DLY_CFG_DLY_MODE_MASK (0x000000C0)
+
+#define SR_IC_DLY_CFG_SR_SFT_RST_LSB (2)
+#define SR_IC_DLY_CFG_SR_SFT_RST_WIDTH (1)
+#define SR_IC_DLY_CFG_SR_SFT_RST_MASK (0x00000004)
+#define SR_IC_DLY_CFG_SR_SFT_RST_BIT (0x00000004)
+
+#define SR_IC_DLY_CFG_IC_EN_LSB (1)
+#define SR_IC_DLY_CFG_IC_EN_WIDTH (1)
+#define SR_IC_DLY_CFG_IC_EN_MASK (0x00000002)
+#define SR_IC_DLY_CFG_IC_EN_BIT (0x00000002)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_LSB (0)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_WIDTH (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_MASK (0x00000001)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_BIT (0x00000001)
+
+#define SR_WIND_1_SIZE_LSB (0)
+#define SR_WIND_1_SIZE_WIDTH (15)
+#define SR_WIND_1_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_1_CFG_LSB (0)
+#define SR_PN_OFFSET_1_CFG_WIDTH (15)
+#define SR_PN_OFFSET_1_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_1_READ_LSB (0)
+#define SR_DATA_CNT_1_READ_WIDTH (9)
+#define SR_DATA_CNT_1_READ_MASK (0x000001FF)
+
+#define SR_WIND_2_SIZE_LSB (0)
+#define SR_WIND_2_SIZE_WIDTH (15)
+#define SR_WIND_2_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_2_CFG_LSB (0)
+#define SR_PN_OFFSET_2_CFG_WIDTH (15)
+#define SR_PN_OFFSET_2_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_2_READ_LSB (0)
+#define SR_DATA_CNT_2_READ_WIDTH (9)
+#define SR_DATA_CNT_2_READ_MASK (0x000001FF)
+
+#define SR_WIND_3_SIZE_LSB (0)
+#define SR_WIND_3_SIZE_WIDTH (15)
+#define SR_WIND_3_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_3_CFG_LSB (0)
+#define SR_PN_OFFSET_3_CFG_WIDTH (15)
+#define SR_PN_OFFSET_3_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_3_READ_LSB (0)
+#define SR_DATA_CNT_3_READ_WIDTH (9)
+#define SR_DATA_CNT_3_READ_MASK (0x000001FF)
+
+#define SR_WIND_4_SIZE_LSB (0)
+#define SR_WIND_4_SIZE_WIDTH (15)
+#define SR_WIND_4_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_4_CFG_LSB (0)
+#define SR_PN_OFFSET_4_CFG_WIDTH (15)
+#define SR_PN_OFFSET_4_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_4_READ_LSB (0)
+#define SR_DATA_CNT_4_READ_WIDTH (9)
+#define SR_DATA_CNT_4_READ_MASK (0x000001FF)
+
+#define SR_WIND_5_SIZE_LSB (0)
+#define SR_WIND_5_SIZE_WIDTH (15)
+#define SR_WIND_5_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_5_CFG_LSB (0)
+#define SR_PN_OFFSET_5_CFG_WIDTH (15)
+#define SR_PN_OFFSET_5_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_5_READ_LSB (0)
+#define SR_DATA_CNT_5_READ_WIDTH (9)
+#define SR_DATA_CNT_5_READ_MASK (0x000001FF)
+
+#define SR_WIND_6_SIZE_LSB (0)
+#define SR_WIND_6_SIZE_WIDTH (15)
+#define SR_WIND_6_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_6_CFG_LSB (0)
+#define SR_PN_OFFSET_6_CFG_WIDTH (15)
+#define SR_PN_OFFSET_6_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_6_READ_LSB (0)
+#define SR_DATA_CNT_6_READ_WIDTH (9)
+#define SR_DATA_CNT_6_READ_MASK (0x000001FF)
+
+#define SR_WIND_7_SIZE_LSB (0)
+#define SR_WIND_7_SIZE_WIDTH (15)
+#define SR_WIND_7_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_7_CFG_LSB (0)
+#define SR_PN_OFFSET_7_CFG_WIDTH (15)
+#define SR_PN_OFFSET_7_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_7_READ_LSB (0)
+#define SR_DATA_CNT_7_READ_WIDTH (9)
+#define SR_DATA_CNT_7_READ_MASK (0x000001FF)
+
+#define SR_WIND_8_SIZE_LSB (0)
+#define SR_WIND_8_SIZE_WIDTH (15)
+#define SR_WIND_8_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_8_CFG_LSB (0)
+#define SR_PN_OFFSET_8_CFG_WIDTH (15)
+#define SR_PN_OFFSET_8_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_8_READ_LSB (0)
+#define SR_DATA_CNT_8_READ_WIDTH (9)
+#define SR_DATA_CNT_8_READ_MASK (0x000001FF)
+
+#define SR_WIND_9_SIZE_LSB (0)
+#define SR_WIND_9_SIZE_WIDTH (15)
+#define SR_WIND_9_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_9_CFG_LSB (0)
+#define SR_PN_OFFSET_9_CFG_WIDTH (15)
+#define SR_PN_OFFSET_9_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_9_READ_LSB (0)
+#define SR_DATA_CNT_9_READ_WIDTH (9)
+#define SR_DATA_CNT_9_READ_MASK (0x000001FF)
+
+#define SR_WIND_10_SIZE_LSB (0)
+#define SR_WIND_10_SIZE_WIDTH (15)
+#define SR_WIND_10_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_10_CFG_LSB (0)
+#define SR_PN_OFFSET_10_CFG_WIDTH (15)
+#define SR_PN_OFFSET_10_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_10_READ_LSB (0)
+#define SR_DATA_CNT_10_READ_WIDTH (9)
+#define SR_DATA_CNT_10_READ_MASK (0x000001FF)
+
+#define SR_WIND_11_SIZE_LSB (0)
+#define SR_WIND_11_SIZE_WIDTH (15)
+#define SR_WIND_11_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_11_CFG_LSB (0)
+#define SR_PN_OFFSET_11_CFG_WIDTH (15)
+#define SR_PN_OFFSET_11_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_11_READ_LSB (0)
+#define SR_DATA_CNT_11_READ_WIDTH (9)
+#define SR_DATA_CNT_11_READ_MASK (0x000001FF)
+
+
+#endif //#ifndef _CPH_1X_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg_95.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg_95.h
new file mode 100644
index 0000000..d159749
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg_95.h
@@ -0,0 +1,775 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_SCH_H_
+#define _CPH_1X_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define SEARCHER_REG_BASE (0xA7850000)
+
+#define SEARCHER_end (SEARCHER_REG_BASE + 0x0b60 + 1*4)
+
+
+
+#define SR_CTL1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0000))
+#define SR_CORR_LEN ((APBADDR32)(SEARCHER_REG_BASE + 0x0004))
+#define SR_NONCO_PASS ((APBADDR32)(SEARCHER_REG_BASE + 0x0008))
+#define SR_AUX_PLT_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x000C))
+#define SR_WIND ((APBADDR32)(SEARCHER_REG_BASE + 0x0010))
+#define SR_D1_THRES ((APBADDR32)(SEARCHER_REG_BASE + 0x0014))
+#define SR_AUX_OFF_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x0018))
+#define SR_OUTPUT ((APBADDR32)(SEARCHER_REG_BASE + 0x001C))
+#define SR_TST_CTL ((APBADDR32)(SEARCHER_REG_BASE + 0x0020))
+#define SR_TST_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0024))
+#define SR_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0028))
+#define SR_STAT ((APBADDR32)(SEARCHER_REG_BASE + 0x002c))
+#define SR_SMPL_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0030))
+#define SR_THRESH ((APBADDR32)(SEARCHER_REG_BASE + 0x0034))
+#define SR_WIN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0038))
+#define SR_INBUF_TSTCTL ((APBADDR32)(SEARCHER_REG_BASE + 0x003C))
+#define SR_INBUF_TSTDAT ((APBADDR32)(SEARCHER_REG_BASE + 0x0040))
+#define SR_PEAK1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0044))
+#define SR_PEAK2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0048))
+#define SR_PEAK3 ((APBADDR32)(SEARCHER_REG_BASE + 0x004C))
+#define SR_PEAK4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0050))
+#define SR_START_DLY ((APBADDR32)(SEARCHER_REG_BASE + 0x0054))
+#define SR_PN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0058))
+#define SR_PAGE_NUM ((APBADDR32)(SEARCHER_REG_BASE + 0x005C))
+#define SR_DATA_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0060))
+#define SR_IC_DLY_CFG ((APBADDR32)(SEARCHER_REG_BASE + 0x0064))
+#define SR_IC_DLY_CFG1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0068))
+#define SR_IC_DLY_CFG2 ((APBADDR32)(SEARCHER_REG_BASE + 0x006c))
+#define SR_AUX_PLT_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x010C))
+#define SR_AUX_PLT_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x020C))
+#define SR_AUX_PLT_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x030C))
+#define SR_AUX_PLT_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x040C))
+#define SR_AUX_PLT_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x050C))
+#define SR_AUX_PLT_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x060C))
+#define SR_AUX_PLT_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x070C))
+#define SR_AUX_PLT_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x080C))
+#define SR_AUX_PLT_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x090C))
+#define SR_AUX_PLT_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A0C))
+#define SR_AUX_PLT_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B0C))
+#define SR_AUX_OFF_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0118))
+#define SR_AUX_OFF_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0218))
+#define SR_AUX_OFF_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0318))
+#define SR_AUX_OFF_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0418))
+#define SR_AUX_OFF_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0518))
+#define SR_AUX_OFF_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0618))
+#define SR_AUX_OFF_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0718))
+#define SR_AUX_OFF_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0818))
+#define SR_AUX_OFF_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0918))
+#define SR_AUX_OFF_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A18))
+#define SR_AUX_OFF_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B18))
+#define SR_WIND_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0110))
+#define SR_PN_OFFSET_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0158))
+#define SR_DATA_CNT_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0160))
+#define SR_WIND_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0210))
+#define SR_PN_OFFSET_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0258))
+#define SR_DATA_CNT_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0260))
+#define SR_WIND_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0310))
+#define SR_PN_OFFSET_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0358))
+#define SR_DATA_CNT_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0360))
+#define SR_WIND_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0410))
+#define SR_PN_OFFSET_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0458))
+#define SR_DATA_CNT_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0460))
+#define SR_WIND_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0510))
+#define SR_PN_OFFSET_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0558))
+#define SR_DATA_CNT_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0560))
+#define SR_WIND_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0610))
+#define SR_PN_OFFSET_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0658))
+#define SR_DATA_CNT_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0660))
+#define SR_WIND_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0710))
+#define SR_PN_OFFSET_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0758))
+#define SR_DATA_CNT_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0760))
+#define SR_WIND_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0810))
+#define SR_PN_OFFSET_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0858))
+#define SR_DATA_CNT_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0860))
+#define SR_WIND_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0910))
+#define SR_PN_OFFSET_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0958))
+#define SR_DATA_CNT_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0960))
+#define SR_WIND_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a10))
+#define SR_PN_OFFSET_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a58))
+#define SR_DATA_CNT_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a60))
+#define SR_WIND_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b10))
+#define SR_PN_OFFSET_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b58))
+#define SR_DATA_CNT_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b60))
+
+
+#define SR_CTL1_OUT_SEL_LSB (16)
+#define SR_CTL1_OUT_SEL_WIDTH (2)
+#define SR_CTL1_OUT_SEL_MASK (0x00030000)
+
+#define SR_CTL1_THRESH_EN_LSB (14)
+#define SR_CTL1_THRESH_EN_WIDTH (1)
+#define SR_CTL1_THRESH_EN_MASK (0x00004000)
+#define SR_CTL1_THRESH_EN_BIT (0x00004000)
+
+#define SR_CTL1_CLR_BUF_CNTRS_LSB (12)
+#define SR_CTL1_CLR_BUF_CNTRS_WIDTH (1)
+#define SR_CTL1_CLR_BUF_CNTRS_MASK (0x00001000)
+#define SR_CTL1_CLR_BUF_CNTRS_BIT (0x00001000)
+
+#define SR_CTL1_TONE_LSB (11)
+#define SR_CTL1_TONE_WIDTH (1)
+#define SR_CTL1_TONE_MASK (0x00000800)
+#define SR_CTL1_TONE_BIT (0x00000800)
+
+#define SR_CTL1_TC_LSB (9)
+#define SR_CTL1_TC_WIDTH (2)
+#define SR_CTL1_TC_MASK (0x00000600)
+
+#define SR_CTL1_AUX_PILOT_EN_LSB (7)
+#define SR_CTL1_AUX_PILOT_EN_WIDTH (1)
+#define SR_CTL1_AUX_PILOT_EN_MASK (0x00000080)
+#define SR_CTL1_AUX_PILOT_EN_BIT (0x00000080)
+
+#define SR_CTL1_COHERENT_LSB (6)
+#define SR_CTL1_COHERENT_WIDTH (1)
+#define SR_CTL1_COHERENT_MASK (0x00000040)
+#define SR_CTL1_COHERENT_BIT (0x00000040)
+
+#define SR_CTL1_FREQ_DOMAIN_LSB (5)
+#define SR_CTL1_FREQ_DOMAIN_WIDTH (1)
+#define SR_CTL1_FREQ_DOMAIN_MASK (0x00000020)
+#define SR_CTL1_FREQ_DOMAIN_BIT (0x00000020)
+
+#define SR_CTL1_LOAD_TWO_BUF_LSB (3)
+#define SR_CTL1_LOAD_TWO_BUF_WIDTH (1)
+#define SR_CTL1_LOAD_TWO_BUF_MASK (0x00000008)
+#define SR_CTL1_LOAD_TWO_BUF_BIT (0x00000008)
+
+#define SR_CTL1_INPUT_BUF_EN_LSB (2)
+#define SR_CTL1_INPUT_BUF_EN_WIDTH (1)
+#define SR_CTL1_INPUT_BUF_EN_MASK (0x00000004)
+#define SR_CTL1_INPUT_BUF_EN_BIT (0x00000004)
+
+#define SR_CTL1_ACQ_MODE_EN_LSB (1)
+#define SR_CTL1_ACQ_MODE_EN_WIDTH (1)
+#define SR_CTL1_ACQ_MODE_EN_MASK (0x00000002)
+#define SR_CTL1_ACQ_MODE_EN_BIT (0x00000002)
+
+#define SR_CTL1_INIT_LSB (0)
+#define SR_CTL1_INIT_WIDTH (1)
+#define SR_CTL1_INIT_MASK (0x00000001)
+#define SR_CTL1_INIT_BIT (0x00000001)
+
+#define SR_CORR_LEN_D2_LSB (6)
+#define SR_CORR_LEN_D2_WIDTH (6)
+#define SR_CORR_LEN_D2_MASK (0x00000FC0)
+
+#define SR_CORR_LEN_D1_LSB (0)
+#define SR_CORR_LEN_D1_WIDTH (6)
+#define SR_CORR_LEN_D1_MASK (0x0000003F)
+
+#define SR_NONCO_PASS_D2MSB_LSB (7)
+#define SR_NONCO_PASS_D2MSB_WIDTH (6)
+#define SR_NONCO_PASS_D2MSB_MASK (0x00001F80)
+
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_LSB (6)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_WIDTH (1)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_MASK (0x00000040)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_BIT (0x00000040)
+
+#define SR_NONCO_PASS_D1LSB_LSB (0)
+#define SR_NONCO_PASS_D1LSB_WIDTH (6)
+#define SR_NONCO_PASS_D1LSB_MASK (0x0000003F)
+
+#define SR_AUX_PLT_WALSH_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_WIND_SIZE_LSB (0)
+#define SR_WIND_SIZE_WIDTH (15)
+#define SR_WIND_SIZE_MASK (0x00007FFF)
+
+#define SR_D1_THRES_CFG_LSB (0)
+#define SR_D1_THRES_CFG_WIDTH (16)
+#define SR_D1_THRES_CFG_MASK (0x0000FFFF)
+
+#define SR_AUX_OFF_WALSH_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_CODE_MASK (0x000001FF)
+
+#define SR_OUTPUT_WIN_OFFSET_LSB (17)
+#define SR_OUTPUT_WIN_OFFSET_WIDTH (9)
+#define SR_OUTPUT_WIN_OFFSET_MASK (0x03FE0000)
+
+#define SR_OUTPUT_E_L_IND_LSB (16)
+#define SR_OUTPUT_E_L_IND_WIDTH (1)
+#define SR_OUTPUT_E_L_IND_MASK (0x00010000)
+#define SR_OUTPUT_E_L_IND_BIT (0x00010000)
+
+#define SR_OUTPUT_METRIC_LSB (0)
+#define SR_OUTPUT_METRIC_WIDTH (16)
+#define SR_OUTPUT_METRIC_MASK (0x0000FFFF)
+
+#define SR_TST_CTL_TST_GO_LSB (4)
+#define SR_TST_CTL_TST_GO_WIDTH (1)
+#define SR_TST_CTL_TST_GO_MASK (0x00000010)
+#define SR_TST_CTL_TST_GO_BIT (0x00000010)
+
+#define SR_TST_CTL_TEST3_LSB (2)
+#define SR_TST_CTL_TEST3_WIDTH (1)
+#define SR_TST_CTL_TEST3_MASK (0x00000004)
+#define SR_TST_CTL_TEST3_BIT (0x00000004)
+
+#define SR_TST_CTL_NOT_STOP_MODE_LSB (0)
+#define SR_TST_CTL_NOT_STOP_MODE_WIDTH (1)
+#define SR_TST_CTL_NOT_STOP_MODE_MASK (0x00000001)
+#define SR_TST_CTL_NOT_STOP_MODE_BIT (0x00000001)
+#define SR_TST_CTL2_OBUF_ADDR_LSB (3)
+#define SR_TST_CTL2_OBUF_ADDR_WIDTH (9)
+#define SR_TST_CTL2_OBUF_ADDR_MASK (0x00000FF8)
+
+#define SR_TST_CTL2_OBF_RPTR_RST_LSB (2)
+#define SR_TST_CTL2_OBF_RPTR_RST_WIDTH (1)
+#define SR_TST_CTL2_OBF_RPTR_RST_MASK (0x00000004)
+#define SR_TST_CTL2_OBF_RPTR_RST_BIT (0x00000004)
+
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_LSB (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_WIDTH (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_MASK (0x00000002)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_BIT (0x00000002)
+
+#define SR_TST_CTL2_TEST_MODE_LSB (0)
+#define SR_TST_CTL2_TEST_MODE_WIDTH (1)
+#define SR_TST_CTL2_TEST_MODE_MASK (0x00000001)
+#define SR_TST_CTL2_TEST_MODE_BIT (0x00000001)
+
+#define SR_CTL2_CLK_ENB_LSB (0)
+#define SR_CTL2_CLK_ENB_WIDTH (1)
+#define SR_CTL2_CLK_ENB_MASK (0x00000001)
+#define SR_CTL2_CLK_ENB_BIT (0x00000001)
+
+#define SR_STAT_DONE_STAT_LSB (2)
+#define SR_STAT_DONE_STAT_WIDTH (1)
+#define SR_STAT_DONE_STAT_MASK (0x00000004)
+#define SR_STAT_DONE_STAT_BIT (0x00000004)
+
+#define SR_STAT_OBF_STAT_LSB (0)
+#define SR_STAT_OBF_STAT_WIDTH (1)
+#define SR_STAT_OBF_STAT_MASK (0x00000001)
+#define SR_STAT_OBF_STAT_BIT (0x00000001)
+
+#define SR_SMPL_CNT_SMPL_CNT_LSB (0)
+#define SR_SMPL_CNT_SMPL_CNT_WIDTH (10)
+#define SR_SMPL_CNT_SMPL_CNT_MASK (0x000003FF)
+
+#define SR_THRESH_OUTPUT_LSB (0)
+#define SR_THRESH_OUTPUT_WIDTH (16)
+#define SR_THRESH_OUTPUT_MASK (0x0000FFFF)
+
+#define SR_WIN_OFFSET_CFG_LSB (1)
+#define SR_WIN_OFFSET_CFG_WIDTH (9)
+#define SR_WIN_OFFSET_CFG_MASK (0x000003FE)
+
+#define SR_WIN_OFFSET_E_L_IND_LSB (0)
+#define SR_WIN_OFFSET_E_L_IND_WIDTH (1)
+#define SR_WIN_OFFSET_E_L_IND_MASK (0x00000001)
+#define SR_WIN_OFFSET_E_L_IND_BIT (0x00000001)
+
+#define SR_INBUF_TSTCTL_TST_EN_LSB (11)
+#define SR_INBUF_TSTCTL_TST_EN_WIDTH (1)
+#define SR_INBUF_TSTCTL_TST_EN_MASK (0x00000800)
+#define SR_INBUF_TSTCTL_TST_EN_BIT (0x00000800)
+
+#define SR_INBUF_TSTCTL_TST_ADDR_LSB (0)
+#define SR_INBUF_TSTCTL_TST_ADDR_WIDTH (11)
+#define SR_INBUF_TSTCTL_TST_ADDR_MASK (0x000007FF)
+
+#define SR_INBUF_TSTDAT_TSTDAT_LSB (0)
+#define SR_INBUF_TSTDAT_TSTDAT_WIDTH (16)
+#define SR_INBUF_TSTDAT_TSTDAT_MASK (0x0000FFFF)
+
+#define SR_PEAK1_WIN_OFFSET_LSB (17)
+#define SR_PEAK1_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK1_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK1_E_L_IND_LSB (16)
+#define SR_PEAK1_E_L_IND_WIDTH (1)
+#define SR_PEAK1_E_L_IND_MASK (0x00010000)
+#define SR_PEAK1_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK1_METRIC_LSB (0)
+#define SR_PEAK1_METRIC_WIDTH (16)
+#define SR_PEAK1_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK2_WIN_OFFSET_LSB (17)
+#define SR_PEAK2_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK2_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK2_E_L_IND_LSB (16)
+#define SR_PEAK2_E_L_IND_WIDTH (1)
+#define SR_PEAK2_E_L_IND_MASK (0x00010000)
+#define SR_PEAK2_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK2_METRIC_LSB (0)
+#define SR_PEAK2_METRIC_WIDTH (16)
+#define SR_PEAK2_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK3_WIN_OFFSET_LSB (17)
+#define SR_PEAK3_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK3_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK3_E_L_IND_LSB (16)
+#define SR_PEAK3_E_L_IND_WIDTH (1)
+#define SR_PEAK3_E_L_IND_MASK (0x00010000)
+#define SR_PEAK3_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK3_METRIC_LSB (0)
+#define SR_PEAK3_METRIC_WIDTH (16)
+#define SR_PEAK3_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK4_WIN_OFFSET_LSB (17)
+#define SR_PEAK4_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK4_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK4_E_L_IND_LSB (16)
+#define SR_PEAK4_E_L_IND_WIDTH (1)
+#define SR_PEAK4_E_L_IND_MASK (0x00010000)
+#define SR_PEAK4_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK4_METRIC_LSB (0)
+#define SR_PEAK4_METRIC_WIDTH (16)
+#define SR_PEAK4_METRIC_MASK (0x0000FFFF)
+
+#define SR_START_DLY_EN_LSB (20)
+#define SR_START_DLY_EN_WIDTH (1)
+#define SR_START_DLY_EN_MASK (0x00100000)
+#define SR_START_DLY_EN_BIT (0x00100000)
+
+#define SR_PN_OFFSET_CFG_LSB (0)
+#define SR_PN_OFFSET_CFG_WIDTH (15)
+#define SR_PN_OFFSET_CFG_MASK (0x00007FFF)
+
+#define SR_PAGE_NUM_CFG_LSB (0)
+#define SR_PAGE_NUM_CFG_WIDTH (4)
+#define SR_PAGE_NUM_CFG_MASK (0x0000000F)
+
+#define SR_DATA_CNT_READ_LSB (0)
+#define SR_DATA_CNT_READ_WIDTH (9)
+#define SR_DATA_CNT_READ_MASK (0x000001FF)
+
+#define SR_IC_DLY_CFG_SR_SFT_RST_LSB (2)
+#define SR_IC_DLY_CFG_SR_SFT_RST_WIDTH (1)
+#define SR_IC_DLY_CFG_SR_SFT_RST_MASK (0x00000004)
+#define SR_IC_DLY_CFG_SR_SFT_RST_BIT (0x00000004)
+
+#define SR_IC_DLY_CFG_IC_EN_LSB (1)
+#define SR_IC_DLY_CFG_IC_EN_WIDTH (1)
+#define SR_IC_DLY_CFG_IC_EN_MASK (0x00000002)
+#define SR_IC_DLY_CFG_IC_EN_BIT (0x00000002)
+
+#define SR_IC_DLY_CFG_DLY_MODE_LSB (0)
+#define SR_IC_DLY_CFG_DLY_MODE_WIDTH (1)
+#define SR_IC_DLY_CFG_DLY_MODE_MASK (0x00000001)
+#define SR_IC_DLY_CFG_DLY_MODE_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_LSB (16)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_MASK (0x01FF0000)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_LSB (7)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_MASK (0x0000FF80)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_LSB (5)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_MASK (0x00000060)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_LSB (3)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_MASK (0x00000018)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_LSB (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_MASK (0x00000006)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_LSB (0)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_WIDTH (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_MASK (0x00000001)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_LSB (10)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_WIDTH (1)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_MASK (0x00000400)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_BIT (0x00000400)
+
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_LSB (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_WIDTH (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_MASK (0x000003E0)
+
+#define SR_IC_DLY_CFG2_IC_PLUS_LSB (4)
+#define SR_IC_DLY_CFG2_IC_PLUS_WIDTH (1)
+#define SR_IC_DLY_CFG2_IC_PLUS_MASK (0x00000010)
+#define SR_IC_DLY_CFG2_IC_PLUS_BIT (0x00000010)
+
+#define SR_IC_DLY_CFG2_SMPL_RPH_LSB (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_MASK (0x0000000C)
+
+#define SR_IC_DLY_CFG2_SMPL_WPH_LSB (0)
+#define SR_IC_DLY_CFG2_SMPL_WPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_WPH_MASK (0x00000003)
+
+#define SR_AUX_PLT_WALSH_1_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_1_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_1_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_1_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_2_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_2_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_2_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_2_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_3_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_3_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_3_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_3_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_4_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_4_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_4_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_4_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_5_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_5_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_5_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_5_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_6_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_6_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_6_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_6_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_7_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_7_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_7_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_7_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_8_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_8_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_8_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_8_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_9_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_9_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_9_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_9_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_10_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_10_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_10_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_10_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_11_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_11_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_11_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_11_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_OFF_WALSH_1_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_1_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_1_CODE_MASK (0x000001FF)
+
+
+#define SR_AUX_OFF_WALSH_2_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_2_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_2_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_3_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_3_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_3_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_4_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_4_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_4_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_5_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_5_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_5_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_6_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_6_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_6_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_7_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_7_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_7_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_8_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_8_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_8_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_9_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_9_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_9_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_10_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_10_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_10_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_11_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_11_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_11_CODE_MASK (0x000001FF)
+
+#define SR_WIND_1_SIZE_LSB (0)
+#define SR_WIND_1_SIZE_WIDTH (15)
+#define SR_WIND_1_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_1_CFG_LSB (0)
+#define SR_PN_OFFSET_1_CFG_WIDTH (15)
+#define SR_PN_OFFSET_1_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_1_READ_LSB (0)
+#define SR_DATA_CNT_1_READ_WIDTH (9)
+#define SR_DATA_CNT_1_READ_MASK (0x000001FF)
+
+#define SR_WIND_2_SIZE_LSB (0)
+#define SR_WIND_2_SIZE_WIDTH (15)
+#define SR_WIND_2_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_2_CFG_LSB (0)
+#define SR_PN_OFFSET_2_CFG_WIDTH (15)
+#define SR_PN_OFFSET_2_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_2_READ_LSB (0)
+#define SR_DATA_CNT_2_READ_WIDTH (9)
+#define SR_DATA_CNT_2_READ_MASK (0x000001FF)
+
+#define SR_WIND_3_SIZE_LSB (0)
+#define SR_WIND_3_SIZE_WIDTH (15)
+#define SR_WIND_3_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_3_CFG_LSB (0)
+#define SR_PN_OFFSET_3_CFG_WIDTH (15)
+#define SR_PN_OFFSET_3_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_3_READ_LSB (0)
+#define SR_DATA_CNT_3_READ_WIDTH (9)
+#define SR_DATA_CNT_3_READ_MASK (0x000001FF)
+
+#define SR_WIND_4_SIZE_LSB (0)
+#define SR_WIND_4_SIZE_WIDTH (15)
+#define SR_WIND_4_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_4_CFG_LSB (0)
+#define SR_PN_OFFSET_4_CFG_WIDTH (15)
+#define SR_PN_OFFSET_4_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_4_READ_LSB (0)
+#define SR_DATA_CNT_4_READ_WIDTH (9)
+#define SR_DATA_CNT_4_READ_MASK (0x000001FF)
+
+#define SR_WIND_5_SIZE_LSB (0)
+#define SR_WIND_5_SIZE_WIDTH (15)
+#define SR_WIND_5_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_5_CFG_LSB (0)
+#define SR_PN_OFFSET_5_CFG_WIDTH (15)
+#define SR_PN_OFFSET_5_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_5_READ_LSB (0)
+#define SR_DATA_CNT_5_READ_WIDTH (9)
+#define SR_DATA_CNT_5_READ_MASK (0x000001FF)
+
+#define SR_WIND_6_SIZE_LSB (0)
+#define SR_WIND_6_SIZE_WIDTH (15)
+#define SR_WIND_6_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_6_CFG_LSB (0)
+#define SR_PN_OFFSET_6_CFG_WIDTH (15)
+#define SR_PN_OFFSET_6_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_6_READ_LSB (0)
+#define SR_DATA_CNT_6_READ_WIDTH (9)
+#define SR_DATA_CNT_6_READ_MASK (0x000001FF)
+
+#define SR_WIND_7_SIZE_LSB (0)
+#define SR_WIND_7_SIZE_WIDTH (15)
+#define SR_WIND_7_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_7_CFG_LSB (0)
+#define SR_PN_OFFSET_7_CFG_WIDTH (15)
+#define SR_PN_OFFSET_7_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_7_READ_LSB (0)
+#define SR_DATA_CNT_7_READ_WIDTH (9)
+#define SR_DATA_CNT_7_READ_MASK (0x000001FF)
+
+#define SR_WIND_8_SIZE_LSB (0)
+#define SR_WIND_8_SIZE_WIDTH (15)
+#define SR_WIND_8_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_8_CFG_LSB (0)
+#define SR_PN_OFFSET_8_CFG_WIDTH (15)
+#define SR_PN_OFFSET_8_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_8_READ_LSB (0)
+#define SR_DATA_CNT_8_READ_WIDTH (9)
+#define SR_DATA_CNT_8_READ_MASK (0x000001FF)
+
+#define SR_WIND_9_SIZE_LSB (0)
+#define SR_WIND_9_SIZE_WIDTH (15)
+#define SR_WIND_9_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_9_CFG_LSB (0)
+#define SR_PN_OFFSET_9_CFG_WIDTH (15)
+#define SR_PN_OFFSET_9_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_9_READ_LSB (0)
+#define SR_DATA_CNT_9_READ_WIDTH (9)
+#define SR_DATA_CNT_9_READ_MASK (0x000001FF)
+
+#define SR_WIND_10_SIZE_LSB (0)
+#define SR_WIND_10_SIZE_WIDTH (15)
+#define SR_WIND_10_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_10_CFG_LSB (0)
+#define SR_PN_OFFSET_10_CFG_WIDTH (15)
+#define SR_PN_OFFSET_10_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_10_READ_LSB (0)
+#define SR_DATA_CNT_10_READ_WIDTH (9)
+#define SR_DATA_CNT_10_READ_MASK (0x000001FF)
+
+#define SR_WIND_11_SIZE_LSB (0)
+#define SR_WIND_11_SIZE_WIDTH (15)
+#define SR_WIND_11_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_11_CFG_LSB (0)
+#define SR_PN_OFFSET_11_CFG_WIDTH (15)
+#define SR_PN_OFFSET_11_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_11_READ_LSB (0)
+#define SR_DATA_CNT_11_READ_WIDTH (9)
+#define SR_DATA_CNT_11_READ_MASK (0x000001FF)
+
+
+#endif //#ifndef _CPH_1X_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg_97.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg_97.h
new file mode 100644
index 0000000..ff47ae7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg_97.h
@@ -0,0 +1,781 @@
+/*
+ 97 1xschreg
+ author: aubrey wang
+ data:2018.4.25
+*/
+ /*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2016
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+#ifndef _CPH_1X_SCH_H_
+#define _CPH_1X_SCH_H_
+
+
+ typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+ typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+ typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+ typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+ typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+ typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+ typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+ typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+ typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define SEARCHER_REG_BASE (0xA9850000)
+
+#define SEARCHER_end (SEARCHER_REG_BASE + 0x0b60 + 1*4)
+
+
+
+#define SR_CTL1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0000))
+#define SR_CORR_LEN ((APBADDR32)(SEARCHER_REG_BASE + 0x0004))
+#define SR_NONCO_PASS ((APBADDR32)(SEARCHER_REG_BASE + 0x0008))
+#define SR_AUX_PLT_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x000C))
+#define SR_WIND ((APBADDR32)(SEARCHER_REG_BASE + 0x0010))
+#define SR_D1_THRES ((APBADDR32)(SEARCHER_REG_BASE + 0x0014))
+#define SR_AUX_OFF_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x0018))
+#define SR_OUTPUT ((APBADDR32)(SEARCHER_REG_BASE + 0x001C))
+#define SR_TST_CTL ((APBADDR32)(SEARCHER_REG_BASE + 0x0020))
+#define SR_TST_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0024))
+#define SR_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0028))
+#define SR_STAT ((APBADDR32)(SEARCHER_REG_BASE + 0x002c))
+#define SR_SMPL_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0030))
+#define SR_THRESH ((APBADDR32)(SEARCHER_REG_BASE + 0x0034))
+#define SR_WIN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0038))
+#define SR_INBUF_TSTCTL ((APBADDR32)(SEARCHER_REG_BASE + 0x003C))
+#define SR_INBUF_TSTDAT ((APBADDR32)(SEARCHER_REG_BASE + 0x0040))
+#define SR_PEAK1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0044))
+#define SR_PEAK2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0048))
+#define SR_PEAK3 ((APBADDR32)(SEARCHER_REG_BASE + 0x004C))
+#define SR_PEAK4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0050))
+#define SR_START_DLY ((APBADDR32)(SEARCHER_REG_BASE + 0x0054))
+#define SR_PN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0058))
+#define SR_PAGE_NUM ((APBADDR32)(SEARCHER_REG_BASE + 0x005C))
+#define SR_DATA_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0060))
+#define SR_IC_DLY_CFG ((APBADDR32)(SEARCHER_REG_BASE + 0x0064))
+#define SR_IC_DLY_CFG1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0068))
+#define SR_IC_DLY_CFG2 ((APBADDR32)(SEARCHER_REG_BASE + 0x006c))
+#define SR_AUX_PLT_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x010C))
+#define SR_AUX_PLT_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x020C))
+#define SR_AUX_PLT_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x030C))
+#define SR_AUX_PLT_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x040C))
+#define SR_AUX_PLT_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x050C))
+#define SR_AUX_PLT_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x060C))
+#define SR_AUX_PLT_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x070C))
+#define SR_AUX_PLT_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x080C))
+#define SR_AUX_PLT_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x090C))
+#define SR_AUX_PLT_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A0C))
+#define SR_AUX_PLT_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B0C))
+#define SR_AUX_OFF_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0118))
+#define SR_AUX_OFF_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0218))
+#define SR_AUX_OFF_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0318))
+#define SR_AUX_OFF_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0418))
+#define SR_AUX_OFF_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0518))
+#define SR_AUX_OFF_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0618))
+#define SR_AUX_OFF_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0718))
+#define SR_AUX_OFF_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0818))
+#define SR_AUX_OFF_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0918))
+#define SR_AUX_OFF_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A18))
+#define SR_AUX_OFF_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B18))
+#define SR_WIND_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0110))
+#define SR_PN_OFFSET_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0158))
+#define SR_DATA_CNT_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0160))
+#define SR_WIND_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0210))
+#define SR_PN_OFFSET_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0258))
+#define SR_DATA_CNT_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0260))
+#define SR_WIND_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0310))
+#define SR_PN_OFFSET_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0358))
+#define SR_DATA_CNT_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0360))
+#define SR_WIND_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0410))
+#define SR_PN_OFFSET_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0458))
+#define SR_DATA_CNT_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0460))
+#define SR_WIND_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0510))
+#define SR_PN_OFFSET_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0558))
+#define SR_DATA_CNT_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0560))
+#define SR_WIND_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0610))
+#define SR_PN_OFFSET_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0658))
+#define SR_DATA_CNT_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0660))
+#define SR_WIND_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0710))
+#define SR_PN_OFFSET_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0758))
+#define SR_DATA_CNT_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0760))
+#define SR_WIND_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0810))
+#define SR_PN_OFFSET_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0858))
+#define SR_DATA_CNT_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0860))
+#define SR_WIND_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0910))
+#define SR_PN_OFFSET_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0958))
+#define SR_DATA_CNT_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0960))
+#define SR_WIND_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a10))
+#define SR_PN_OFFSET_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a58))
+#define SR_DATA_CNT_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a60))
+#define SR_WIND_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b10))
+#define SR_PN_OFFSET_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b58))
+#define SR_DATA_CNT_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b60))
+
+
+#define SR_CTL1_OUT_SEL_LSB (16)
+#define SR_CTL1_OUT_SEL_WIDTH (2)
+#define SR_CTL1_OUT_SEL_MASK (0x00030000)
+
+#define SR_CTL1_THRESH_EN_LSB (14)
+#define SR_CTL1_THRESH_EN_WIDTH (1)
+#define SR_CTL1_THRESH_EN_MASK (0x00004000)
+#define SR_CTL1_THRESH_EN_BIT (0x00004000)
+
+#define SR_CTL1_CLR_BUF_CNTRS_LSB (12)
+#define SR_CTL1_CLR_BUF_CNTRS_WIDTH (1)
+#define SR_CTL1_CLR_BUF_CNTRS_MASK (0x00001000)
+#define SR_CTL1_CLR_BUF_CNTRS_BIT (0x00001000)
+
+#define SR_CTL1_TONE_LSB (11)
+#define SR_CTL1_TONE_WIDTH (1)
+#define SR_CTL1_TONE_MASK (0x00000800)
+#define SR_CTL1_TONE_BIT (0x00000800)
+
+#define SR_CTL1_TC_LSB (9)
+#define SR_CTL1_TC_WIDTH (2)
+#define SR_CTL1_TC_MASK (0x00000600)
+
+#define SR_CTL1_AUX_PILOT_EN_LSB (7)
+#define SR_CTL1_AUX_PILOT_EN_WIDTH (1)
+#define SR_CTL1_AUX_PILOT_EN_MASK (0x00000080)
+#define SR_CTL1_AUX_PILOT_EN_BIT (0x00000080)
+
+#define SR_CTL1_COHERENT_LSB (6)
+#define SR_CTL1_COHERENT_WIDTH (1)
+#define SR_CTL1_COHERENT_MASK (0x00000040)
+#define SR_CTL1_COHERENT_BIT (0x00000040)
+
+#define SR_CTL1_FREQ_DOMAIN_LSB (5)
+#define SR_CTL1_FREQ_DOMAIN_WIDTH (1)
+#define SR_CTL1_FREQ_DOMAIN_MASK (0x00000020)
+#define SR_CTL1_FREQ_DOMAIN_BIT (0x00000020)
+
+#define SR_CTL1_LOAD_TWO_BUF_LSB (3)
+#define SR_CTL1_LOAD_TWO_BUF_WIDTH (1)
+#define SR_CTL1_LOAD_TWO_BUF_MASK (0x00000008)
+#define SR_CTL1_LOAD_TWO_BUF_BIT (0x00000008)
+
+#define SR_CTL1_INPUT_BUF_EN_LSB (2)
+#define SR_CTL1_INPUT_BUF_EN_WIDTH (1)
+#define SR_CTL1_INPUT_BUF_EN_MASK (0x00000004)
+#define SR_CTL1_INPUT_BUF_EN_BIT (0x00000004)
+
+#define SR_CTL1_ACQ_MODE_EN_LSB (1)
+#define SR_CTL1_ACQ_MODE_EN_WIDTH (1)
+#define SR_CTL1_ACQ_MODE_EN_MASK (0x00000002)
+#define SR_CTL1_ACQ_MODE_EN_BIT (0x00000002)
+
+#define SR_CTL1_INIT_LSB (0)
+#define SR_CTL1_INIT_WIDTH (1)
+#define SR_CTL1_INIT_MASK (0x00000001)
+#define SR_CTL1_INIT_BIT (0x00000001)
+
+#define SR_CORR_LEN_D2_LSB (6)
+#define SR_CORR_LEN_D2_WIDTH (6)
+#define SR_CORR_LEN_D2_MASK (0x00000FC0)
+
+#define SR_CORR_LEN_D1_LSB (0)
+#define SR_CORR_LEN_D1_WIDTH (6)
+#define SR_CORR_LEN_D1_MASK (0x0000003F)
+
+#define SR_NONCO_PASS_D2MSB_LSB (7)
+#define SR_NONCO_PASS_D2MSB_WIDTH (6)
+#define SR_NONCO_PASS_D2MSB_MASK (0x00001F80)
+
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_LSB (6)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_WIDTH (1)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_MASK (0x00000040)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_BIT (0x00000040)
+
+#define SR_NONCO_PASS_D1LSB_LSB (0)
+#define SR_NONCO_PASS_D1LSB_WIDTH (6)
+#define SR_NONCO_PASS_D1LSB_MASK (0x0000003F)
+
+#define SR_AUX_PLT_WALSH_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_WIND_SIZE_LSB (0)
+#define SR_WIND_SIZE_WIDTH (15)
+#define SR_WIND_SIZE_MASK (0x00007FFF)
+
+#define SR_D1_THRES_CFG_LSB (0)
+#define SR_D1_THRES_CFG_WIDTH (16)
+#define SR_D1_THRES_CFG_MASK (0x0000FFFF)
+
+#define SR_AUX_OFF_WALSH_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_CODE_MASK (0x000001FF)
+
+#define SR_OUTPUT_WIN_OFFSET_LSB (17)
+#define SR_OUTPUT_WIN_OFFSET_WIDTH (9)
+#define SR_OUTPUT_WIN_OFFSET_MASK (0x03FE0000)
+
+#define SR_OUTPUT_E_L_IND_LSB (16)
+#define SR_OUTPUT_E_L_IND_WIDTH (1)
+#define SR_OUTPUT_E_L_IND_MASK (0x00010000)
+#define SR_OUTPUT_E_L_IND_BIT (0x00010000)
+
+#define SR_OUTPUT_METRIC_LSB (0)
+#define SR_OUTPUT_METRIC_WIDTH (16)
+#define SR_OUTPUT_METRIC_MASK (0x0000FFFF)
+
+#define SR_TST_CTL_TST_GO_LSB (4)
+#define SR_TST_CTL_TST_GO_WIDTH (1)
+#define SR_TST_CTL_TST_GO_MASK (0x00000010)
+#define SR_TST_CTL_TST_GO_BIT (0x00000010)
+
+#define SR_TST_CTL_TEST3_LSB (2)
+#define SR_TST_CTL_TEST3_WIDTH (1)
+#define SR_TST_CTL_TEST3_MASK (0x00000004)
+#define SR_TST_CTL_TEST3_BIT (0x00000004)
+
+#define SR_TST_CTL_NOT_STOP_MODE_LSB (0)
+#define SR_TST_CTL_NOT_STOP_MODE_WIDTH (1)
+#define SR_TST_CTL_NOT_STOP_MODE_MASK (0x00000001)
+#define SR_TST_CTL_NOT_STOP_MODE_BIT (0x00000001)
+#define SR_TST_CTL2_OBUF_ADDR_LSB (3)
+#define SR_TST_CTL2_OBUF_ADDR_WIDTH (9)
+#define SR_TST_CTL2_OBUF_ADDR_MASK (0x00000FF8)
+
+#define SR_TST_CTL2_OBF_RPTR_RST_LSB (2)
+#define SR_TST_CTL2_OBF_RPTR_RST_WIDTH (1)
+#define SR_TST_CTL2_OBF_RPTR_RST_MASK (0x00000004)
+#define SR_TST_CTL2_OBF_RPTR_RST_BIT (0x00000004)
+
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_LSB (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_WIDTH (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_MASK (0x00000002)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_BIT (0x00000002)
+
+#define SR_TST_CTL2_TEST_MODE_LSB (0)
+#define SR_TST_CTL2_TEST_MODE_WIDTH (1)
+#define SR_TST_CTL2_TEST_MODE_MASK (0x00000001)
+#define SR_TST_CTL2_TEST_MODE_BIT (0x00000001)
+
+#define SR_CTL2_CLK_ENB_LSB (0)
+#define SR_CTL2_CLK_ENB_WIDTH (1)
+#define SR_CTL2_CLK_ENB_MASK (0x00000001)
+#define SR_CTL2_CLK_ENB_BIT (0x00000001)
+
+#define SR_STAT_DONE_STAT_LSB (2)
+#define SR_STAT_DONE_STAT_WIDTH (1)
+#define SR_STAT_DONE_STAT_MASK (0x00000004)
+#define SR_STAT_DONE_STAT_BIT (0x00000004)
+
+#define SR_STAT_OBF_STAT_LSB (0)
+#define SR_STAT_OBF_STAT_WIDTH (1)
+#define SR_STAT_OBF_STAT_MASK (0x00000001)
+#define SR_STAT_OBF_STAT_BIT (0x00000001)
+
+#define SR_SMPL_CNT_SMPL_CNT_LSB (0)
+#define SR_SMPL_CNT_SMPL_CNT_WIDTH (10)
+#define SR_SMPL_CNT_SMPL_CNT_MASK (0x000003FF)
+
+#define SR_THRESH_OUTPUT_LSB (0)
+#define SR_THRESH_OUTPUT_WIDTH (16)
+#define SR_THRESH_OUTPUT_MASK (0x0000FFFF)
+
+#define SR_WIN_OFFSET_CFG_LSB (1)
+#define SR_WIN_OFFSET_CFG_WIDTH (9)
+#define SR_WIN_OFFSET_CFG_MASK (0x000003FE)
+
+#define SR_WIN_OFFSET_E_L_IND_LSB (0)
+#define SR_WIN_OFFSET_E_L_IND_WIDTH (1)
+#define SR_WIN_OFFSET_E_L_IND_MASK (0x00000001)
+#define SR_WIN_OFFSET_E_L_IND_BIT (0x00000001)
+
+#define SR_INBUF_TSTCTL_TST_EN_LSB (11)
+#define SR_INBUF_TSTCTL_TST_EN_WIDTH (1)
+#define SR_INBUF_TSTCTL_TST_EN_MASK (0x00000800)
+#define SR_INBUF_TSTCTL_TST_EN_BIT (0x00000800)
+
+#define SR_INBUF_TSTCTL_TST_ADDR_LSB (0)
+#define SR_INBUF_TSTCTL_TST_ADDR_WIDTH (11)
+#define SR_INBUF_TSTCTL_TST_ADDR_MASK (0x000007FF)
+
+#define SR_INBUF_TSTDAT_TSTDAT_LSB (0)
+#define SR_INBUF_TSTDAT_TSTDAT_WIDTH (16)
+#define SR_INBUF_TSTDAT_TSTDAT_MASK (0x0000FFFF)
+
+#define SR_PEAK1_WIN_OFFSET_LSB (17)
+#define SR_PEAK1_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK1_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK1_E_L_IND_LSB (16)
+#define SR_PEAK1_E_L_IND_WIDTH (1)
+#define SR_PEAK1_E_L_IND_MASK (0x00010000)
+#define SR_PEAK1_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK1_METRIC_LSB (0)
+#define SR_PEAK1_METRIC_WIDTH (16)
+#define SR_PEAK1_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK2_WIN_OFFSET_LSB (17)
+#define SR_PEAK2_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK2_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK2_E_L_IND_LSB (16)
+#define SR_PEAK2_E_L_IND_WIDTH (1)
+#define SR_PEAK2_E_L_IND_MASK (0x00010000)
+#define SR_PEAK2_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK2_METRIC_LSB (0)
+#define SR_PEAK2_METRIC_WIDTH (16)
+#define SR_PEAK2_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK3_WIN_OFFSET_LSB (17)
+#define SR_PEAK3_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK3_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK3_E_L_IND_LSB (16)
+#define SR_PEAK3_E_L_IND_WIDTH (1)
+#define SR_PEAK3_E_L_IND_MASK (0x00010000)
+#define SR_PEAK3_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK3_METRIC_LSB (0)
+#define SR_PEAK3_METRIC_WIDTH (16)
+#define SR_PEAK3_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK4_WIN_OFFSET_LSB (17)
+#define SR_PEAK4_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK4_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK4_E_L_IND_LSB (16)
+#define SR_PEAK4_E_L_IND_WIDTH (1)
+#define SR_PEAK4_E_L_IND_MASK (0x00010000)
+#define SR_PEAK4_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK4_METRIC_LSB (0)
+#define SR_PEAK4_METRIC_WIDTH (16)
+#define SR_PEAK4_METRIC_MASK (0x0000FFFF)
+
+#define SR_START_DLY_EN_LSB (20)
+#define SR_START_DLY_EN_WIDTH (1)
+#define SR_START_DLY_EN_MASK (0x00100000)
+#define SR_START_DLY_EN_BIT (0x00100000)
+
+#define SR_PN_OFFSET_CFG_LSB (0)
+#define SR_PN_OFFSET_CFG_WIDTH (15)
+#define SR_PN_OFFSET_CFG_MASK (0x00007FFF)
+
+#define SR_PAGE_NUM_CFG_LSB (0)
+#define SR_PAGE_NUM_CFG_WIDTH (4)
+#define SR_PAGE_NUM_CFG_MASK (0x0000000F)
+
+#define SR_DATA_CNT_READ_LSB (0)
+#define SR_DATA_CNT_READ_WIDTH (9)
+#define SR_DATA_CNT_READ_MASK (0x000001FF)
+
+#define SR_IC_DLY_CFG_SR_SFT_RST_LSB (2)
+#define SR_IC_DLY_CFG_SR_SFT_RST_WIDTH (1)
+#define SR_IC_DLY_CFG_SR_SFT_RST_MASK (0x00000004)
+#define SR_IC_DLY_CFG_SR_SFT_RST_BIT (0x00000004)
+
+#define SR_IC_DLY_CFG_IC_EN_LSB (1)
+#define SR_IC_DLY_CFG_IC_EN_WIDTH (1)
+#define SR_IC_DLY_CFG_IC_EN_MASK (0x00000002)
+#define SR_IC_DLY_CFG_IC_EN_BIT (0x00000002)
+
+#define SR_IC_DLY_CFG_DLY_MODE_LSB (0)
+#define SR_IC_DLY_CFG_DLY_MODE_WIDTH (1)
+#define SR_IC_DLY_CFG_DLY_MODE_MASK (0x00000001)
+#define SR_IC_DLY_CFG_DLY_MODE_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_LSB (16)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_MASK (0x01FF0000)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_LSB (7)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_MASK (0x0000FF80)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_LSB (5)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_MASK (0x00000060)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_LSB (3)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_MASK (0x00000018)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_LSB (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_MASK (0x00000006)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_LSB (0)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_WIDTH (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_MASK (0x00000001)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_LSB (10)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_WIDTH (1)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_MASK (0x00000400)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_BIT (0x00000400)
+
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_LSB (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_WIDTH (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_MASK (0x000003E0)
+
+#define SR_IC_DLY_CFG2_IC_PLUS_LSB (4)
+#define SR_IC_DLY_CFG2_IC_PLUS_WIDTH (1)
+#define SR_IC_DLY_CFG2_IC_PLUS_MASK (0x00000010)
+#define SR_IC_DLY_CFG2_IC_PLUS_BIT (0x00000010)
+
+#define SR_IC_DLY_CFG2_SMPL_RPH_LSB (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_MASK (0x0000000C)
+
+#define SR_IC_DLY_CFG2_SMPL_WPH_LSB (0)
+#define SR_IC_DLY_CFG2_SMPL_WPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_WPH_MASK (0x00000003)
+
+#define SR_AUX_PLT_WALSH_1_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_1_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_1_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_1_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_2_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_2_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_2_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_2_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_3_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_3_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_3_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_3_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_4_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_4_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_4_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_4_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_5_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_5_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_5_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_5_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_6_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_6_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_6_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_6_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_7_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_7_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_7_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_7_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_8_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_8_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_8_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_8_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_9_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_9_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_9_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_9_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_10_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_10_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_10_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_10_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_11_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_11_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_11_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_11_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_OFF_WALSH_1_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_1_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_1_CODE_MASK (0x000001FF)
+
+
+#define SR_AUX_OFF_WALSH_2_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_2_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_2_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_3_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_3_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_3_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_4_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_4_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_4_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_5_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_5_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_5_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_6_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_6_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_6_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_7_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_7_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_7_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_8_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_8_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_8_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_9_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_9_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_9_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_10_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_10_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_10_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_11_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_11_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_11_CODE_MASK (0x000001FF)
+
+#define SR_WIND_1_SIZE_LSB (0)
+#define SR_WIND_1_SIZE_WIDTH (15)
+#define SR_WIND_1_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_1_CFG_LSB (0)
+#define SR_PN_OFFSET_1_CFG_WIDTH (15)
+#define SR_PN_OFFSET_1_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_1_READ_LSB (0)
+#define SR_DATA_CNT_1_READ_WIDTH (9)
+#define SR_DATA_CNT_1_READ_MASK (0x000001FF)
+
+#define SR_WIND_2_SIZE_LSB (0)
+#define SR_WIND_2_SIZE_WIDTH (15)
+#define SR_WIND_2_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_2_CFG_LSB (0)
+#define SR_PN_OFFSET_2_CFG_WIDTH (15)
+#define SR_PN_OFFSET_2_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_2_READ_LSB (0)
+#define SR_DATA_CNT_2_READ_WIDTH (9)
+#define SR_DATA_CNT_2_READ_MASK (0x000001FF)
+
+#define SR_WIND_3_SIZE_LSB (0)
+#define SR_WIND_3_SIZE_WIDTH (15)
+#define SR_WIND_3_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_3_CFG_LSB (0)
+#define SR_PN_OFFSET_3_CFG_WIDTH (15)
+#define SR_PN_OFFSET_3_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_3_READ_LSB (0)
+#define SR_DATA_CNT_3_READ_WIDTH (9)
+#define SR_DATA_CNT_3_READ_MASK (0x000001FF)
+
+#define SR_WIND_4_SIZE_LSB (0)
+#define SR_WIND_4_SIZE_WIDTH (15)
+#define SR_WIND_4_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_4_CFG_LSB (0)
+#define SR_PN_OFFSET_4_CFG_WIDTH (15)
+#define SR_PN_OFFSET_4_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_4_READ_LSB (0)
+#define SR_DATA_CNT_4_READ_WIDTH (9)
+#define SR_DATA_CNT_4_READ_MASK (0x000001FF)
+
+#define SR_WIND_5_SIZE_LSB (0)
+#define SR_WIND_5_SIZE_WIDTH (15)
+#define SR_WIND_5_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_5_CFG_LSB (0)
+#define SR_PN_OFFSET_5_CFG_WIDTH (15)
+#define SR_PN_OFFSET_5_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_5_READ_LSB (0)
+#define SR_DATA_CNT_5_READ_WIDTH (9)
+#define SR_DATA_CNT_5_READ_MASK (0x000001FF)
+
+#define SR_WIND_6_SIZE_LSB (0)
+#define SR_WIND_6_SIZE_WIDTH (15)
+#define SR_WIND_6_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_6_CFG_LSB (0)
+#define SR_PN_OFFSET_6_CFG_WIDTH (15)
+#define SR_PN_OFFSET_6_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_6_READ_LSB (0)
+#define SR_DATA_CNT_6_READ_WIDTH (9)
+#define SR_DATA_CNT_6_READ_MASK (0x000001FF)
+
+#define SR_WIND_7_SIZE_LSB (0)
+#define SR_WIND_7_SIZE_WIDTH (15)
+#define SR_WIND_7_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_7_CFG_LSB (0)
+#define SR_PN_OFFSET_7_CFG_WIDTH (15)
+#define SR_PN_OFFSET_7_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_7_READ_LSB (0)
+#define SR_DATA_CNT_7_READ_WIDTH (9)
+#define SR_DATA_CNT_7_READ_MASK (0x000001FF)
+
+#define SR_WIND_8_SIZE_LSB (0)
+#define SR_WIND_8_SIZE_WIDTH (15)
+#define SR_WIND_8_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_8_CFG_LSB (0)
+#define SR_PN_OFFSET_8_CFG_WIDTH (15)
+#define SR_PN_OFFSET_8_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_8_READ_LSB (0)
+#define SR_DATA_CNT_8_READ_WIDTH (9)
+#define SR_DATA_CNT_8_READ_MASK (0x000001FF)
+
+#define SR_WIND_9_SIZE_LSB (0)
+#define SR_WIND_9_SIZE_WIDTH (15)
+#define SR_WIND_9_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_9_CFG_LSB (0)
+#define SR_PN_OFFSET_9_CFG_WIDTH (15)
+#define SR_PN_OFFSET_9_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_9_READ_LSB (0)
+#define SR_DATA_CNT_9_READ_WIDTH (9)
+#define SR_DATA_CNT_9_READ_MASK (0x000001FF)
+
+#define SR_WIND_10_SIZE_LSB (0)
+#define SR_WIND_10_SIZE_WIDTH (15)
+#define SR_WIND_10_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_10_CFG_LSB (0)
+#define SR_PN_OFFSET_10_CFG_WIDTH (15)
+#define SR_PN_OFFSET_10_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_10_READ_LSB (0)
+#define SR_DATA_CNT_10_READ_WIDTH (9)
+#define SR_DATA_CNT_10_READ_MASK (0x000001FF)
+
+#define SR_WIND_11_SIZE_LSB (0)
+#define SR_WIND_11_SIZE_WIDTH (15)
+#define SR_WIND_11_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_11_CFG_LSB (0)
+#define SR_PN_OFFSET_11_CFG_WIDTH (15)
+#define SR_PN_OFFSET_11_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_11_READ_LSB (0)
+#define SR_DATA_CNT_11_READ_WIDTH (9)
+#define SR_DATA_CNT_11_READ_MASK (0x000001FF)
+
+
+#endif //#ifndef _CPH_1X_SCH_H_
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxbrp.h b/mcu/interface/l1/cl1/common/HW/cph1xtxbrp.h
new file mode 100644
index 0000000..17248b2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxbrp.h
@@ -0,0 +1,879 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXBRP_H_
+#define _CPH_1X_TXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#if defined(__MD93__)||defined(__MD95__)
+#define BRP_C2K_1XRTT_REG_BASE (0xa8020000)
+#else
+#define BRP_C2K_1XRTT_REG_BASE (0xa8820000)
+#endif
+#define BRP_C2K_1XRTT_end (BRP_C2K_1XRTT_REG_BASE + 0x03c8 + 1*4)
+
+
+#define WORK_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0000))
+#define GLOBAL_IRQ ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0008))
+#define GLOBAL_IRQ_MASK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x000c))
+#define GLOBAL_IRQ_CLR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0010))
+#define RTT_IRQ ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0044))
+#define RTT_IRQ_MASK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0048))
+#define RTT_IRQ_CLR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x004c))
+#define TXBRP_SW_CKEN_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0050))
+#define TXBRP_CLK_CTRLSEL_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0054))
+#define DEBUG_REG_BANK_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0058))
+#define MEM_TEST_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x005c))
+#define TRIGGER_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0060))
+#define DI_SWAP_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0064))
+#define DI_TEST_CFG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0068))
+#define I_REG_ULTRA_PRE_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x006c))
+#define I_REG_BEGIN_ULTRA_CNT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0070))
+#define I_REG_ULTRA_WATER_MARK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0074))
+#define DI_DEBUG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0078))
+#define DEBUG_TRIG_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x007c))
+#define ENC_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0090))
+#define CRC_DBG_FLAG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0094))
+#define INTLV_B_LWT_ST_0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0098))
+#define INTLV_B_LWT_ST_1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x009c))
+#define UTXBRP_CTRL_FSM_STATE1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a0))
+#define UTXBRP_CTRL_FSM_STATE2 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a4))
+#define RM_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a8))
+#define RUMAP_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00ac))
+#define UTXBRP_TEST_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00c4))
+#define CRP_SW_READ_CTRL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00c8))
+#define C2K_READ_RST ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00cc))
+#define RTT_START ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00f0))
+#define TXA_INPUT_LEN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0110))
+#define TXA_PUNC ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0118))
+#define TXA_HA_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x011c))
+#define TXA_INTRLV_PARM ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0120))
+#define TXA_FREP_L ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0124))
+#define CHL_TYPE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0128))
+#define TXA_CRC ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x012c))
+#define TXA_FREP_LPML ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0130))
+#define TXA_FREP_MM1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0134))
+#define TXA_FREP_ACC0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0138))
+#define TXA_PUNC_PAT0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x013c))
+#define TXA_PUNC_PAT1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0140))
+#define TXA_FREP_LP ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0144))
+#define TXA_TST_CTRL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0148))
+#define RTT_CHNL_BASE_ADDR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x014c))
+#define TXBRP_DBG_CRC32_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03bc))
+#define TXBRP_DBG_CRC32_RSLT_I_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c0))
+#define TXBRP_DBG_CRC32_RSLT_Q_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c4))
+#define DEBUG_CRC_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c8))
+
+
+#define WORK_MODE_LSB (0)
+#define WORK_MODE_WIDTH (5)
+#define WORK_MODE_MASK (0x0000001F)
+
+#define GLOBAL_IRQ_DI_ERR_IRQ_LSB (3)
+#define GLOBAL_IRQ_DI_ERR_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_DI_ERR_IRQ_MASK (0x00000008)
+#define GLOBAL_IRQ_DI_ERR_IRQ_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_LSB (2)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_MASK (0x00000004)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_LSB (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_MASK (0x00000002)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MODE_IRQ_LSB (0)
+#define GLOBAL_IRQ_MODE_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_IRQ_MASK (0x00000001)
+#define GLOBAL_IRQ_MODE_IRQ_BIT (0x00000001)
+
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_LSB (3)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_MASK (0x00000008)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_LSB (2)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_MASK (0x00000004)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_LSB (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_MASK (0x00000002)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_LSB (0)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_MASK (0x00000001)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_BIT (0x00000001)
+
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_LSB (3)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_MASK (0x00000008)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_BIT (0x00000008)
+
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_LSB (2)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_MASK (0x00000004)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_BIT (0x00000004)
+
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_LSB (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_MASK (0x00000002)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_BIT (0x00000002)
+
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_LSB (0)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_MASK (0x00000001)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_BIT (0x00000001)
+
+#define RTT_IRQ_RTT_TRIG_ERR_LSB (3)
+#define RTT_IRQ_RTT_TRIG_ERR_WIDTH (1)
+#define RTT_IRQ_RTT_TRIG_ERR_MASK (0x00000008)
+#define RTT_IRQ_RTT_TRIG_ERR_BIT (0x00000008)
+
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_LSB (2)
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_WIDTH (1)
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_MASK (0x00000004)
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_BIT (0x00000004)
+
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_LSB (1)
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_WIDTH (1)
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_MASK (0x00000002)
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_BIT (0x00000002)
+
+#define RTT_IRQ_RTT_DONE_LSB (0)
+#define RTT_IRQ_RTT_DONE_WIDTH (1)
+#define RTT_IRQ_RTT_DONE_MASK (0x00000001)
+#define RTT_IRQ_RTT_DONE_BIT (0x00000001)
+
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_LSB (3)
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_MASK (0x00000008)
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_BIT (0x00000008)
+
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_LSB (2)
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_MASK (0x00000004)
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_BIT (0x00000004)
+
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_LSB (1)
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_MASK (0x00000002)
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_BIT (0x00000002)
+
+#define RTT_IRQ_MASK_RTT_DONE_MASK_LSB (0)
+#define RTT_IRQ_MASK_RTT_DONE_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_DONE_MASK_MASK (0x00000001)
+#define RTT_IRQ_MASK_RTT_DONE_MASK_BIT (0x00000001)
+
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_LSB (3)
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_MASK (0x00000008)
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_BIT (0x00000008)
+
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_LSB (2)
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_MASK (0x00000004)
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_BIT (0x00000004)
+
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_LSB (1)
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_MASK (0x00000002)
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_BIT (0x00000002)
+
+#define RTT_IRQ_CLR_RTT_DONE_CLR_LSB (0)
+#define RTT_IRQ_CLR_RTT_DONE_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_DONE_CLR_MASK (0x00000001)
+#define RTT_IRQ_CLR_RTT_DONE_CLR_BIT (0x00000001)
+
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_LSB (12)
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_MASK (0x00001000)
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_BIT (0x00001000)
+
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_LSB (11)
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_MASK (0x00000800)
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_BIT (0x00000800)
+
+#define TXBRP_SW_CKEN_APB_SW_CKEN_LSB (10)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_MASK (0x00000400)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_BIT (0x00000400)
+
+#define TXBRP_SW_CKEN_OB_SW_CKEN_LSB (9)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_MASK (0x00000200)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_BIT (0x00000200)
+
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_LSB (8)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_MASK (0x00000100)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_BIT (0x00000100)
+
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_LSB (7)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_MASK (0x00000080)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_BIT (0x00000080)
+
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_LSB (6)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_MASK (0x00000040)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_BIT (0x00000040)
+
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_LSB (5)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_MASK (0x00000020)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_BIT (0x00000020)
+
+#define TXBRP_SW_CKEN_RM_SW_CKEN_LSB (4)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_MASK (0x00000010)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_BIT (0x00000010)
+
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_LSB (3)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_MASK (0x00000008)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_BIT (0x00000008)
+
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_LSB (2)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_MASK (0x00000004)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_BIT (0x00000004)
+
+#define TXBRP_SW_CKEN_DI_SW_CKEN_LSB (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_MASK (0x00000002)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_BIT (0x00000002)
+
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_LSB (0)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_MASK (0x00000001)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_LSB (12)
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_MASK (0x00001000)
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_BIT (0x00001000)
+
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_LSB (11)
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_MASK (0x00000800)
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_BIT (0x00000800)
+
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_LSB (10)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_MASK (0x00000400)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_BIT (0x00000400)
+
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_LSB (9)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_MASK (0x00000200)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_BIT (0x00000200)
+
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_LSB (8)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_MASK (0x00000100)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_BIT (0x00000100)
+
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_LSB (7)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_MASK (0x00000080)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_BIT (0x00000080)
+
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_LSB (6)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_MASK (0x00000040)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_BIT (0x00000040)
+
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_LSB (5)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_MASK (0x00000020)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_BIT (0x00000020)
+
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_LSB (4)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_MASK (0x00000010)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_BIT (0x00000010)
+
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_LSB (3)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_MASK (0x00000008)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_BIT (0x00000008)
+
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_LSB (2)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_MASK (0x00000004)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_BIT (0x00000004)
+
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_LSB (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_MASK (0x00000002)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_BIT (0x00000002)
+
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_LSB (0)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_MASK (0x00000001)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_BIT (0x00000001)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_LSB (24)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_MASK (0xFF000000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_LSB (16)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_MASK (0x00FF0000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_LSB (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_LSB (0)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_MASK (0x000000FF)
+
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_LSB (1)
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_WIDTH (1)
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_MASK (0x00000002)
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_BIT (0x00000002)
+
+#define MEM_TEST_MODE_MEM_TEST_MODE_LSB (0)
+#define MEM_TEST_MODE_MEM_TEST_MODE_WIDTH (1)
+#define MEM_TEST_MODE_MEM_TEST_MODE_MASK (0x00000001)
+#define MEM_TEST_MODE_MEM_TEST_MODE_BIT (0x00000001)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_LSB (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_MASK (0x00000002)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_BIT (0x00000002)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_LSB (0)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_MASK (0x00000001)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_BIT (0x00000001)
+
+#define DI_SWAP_EN_LSB (0)
+#define DI_SWAP_EN_WIDTH (3)
+#define DI_SWAP_EN_MASK (0x00000007)
+
+#define DI_TEST_CFG_DI_TEST_MODE_EN_LSB (10)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_WIDTH (1)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_MASK (0x00000400)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_BIT (0x00000400)
+
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_LSB (8)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_WIDTH (2)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_MASK (0x00000300)
+
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_LSB (0)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_WIDTH (8)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_MASK (0x000000FF)
+
+#define I_REG_ULTRA_PRE_EN_LSB (0)
+#define I_REG_ULTRA_PRE_EN_WIDTH (1)
+#define I_REG_ULTRA_PRE_EN_MASK (0x00000001)
+#define I_REG_ULTRA_PRE_EN_BIT (0x00000001)
+
+#define I_REG_BEGIN_ULTRA_CNT_LSB (0)
+#define I_REG_BEGIN_ULTRA_CNT_WIDTH (3)
+#define I_REG_BEGIN_ULTRA_CNT_MASK (0x00000007)
+
+#define I_REG_ULTRA_WATER_MARK_LSB (0)
+#define I_REG_ULTRA_WATER_MARK_WIDTH (3)
+#define I_REG_ULTRA_WATER_MARK_MASK (0x00000007)
+
+#define DI_DEBUG_DMA0_STATE_LSB (20)
+#define DI_DEBUG_DMA0_STATE_WIDTH (2)
+#define DI_DEBUG_DMA0_STATE_MASK (0x00300000)
+
+#define DI_DEBUG_RAM_RD_STATE_LSB (16)
+#define DI_DEBUG_RAM_RD_STATE_WIDTH (2)
+#define DI_DEBUG_RAM_RD_STATE_MASK (0x00030000)
+
+#define DI_DEBUG_O_DMA0_UTR_LSB (13)
+#define DI_DEBUG_O_DMA0_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_UTR_MASK (0x00002000)
+#define DI_DEBUG_O_DMA0_UTR_BIT (0x00002000)
+
+#define DI_DEBUG_O_DMA0_PTR_UTR_LSB (12)
+#define DI_DEBUG_O_DMA0_PTR_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_PTR_UTR_MASK (0x00001000)
+#define DI_DEBUG_O_DMA0_PTR_UTR_BIT (0x00001000)
+
+#define DI_DEBUG_O_DMA0_RD_REQ_LSB (10)
+#define DI_DEBUG_O_DMA0_RD_REQ_WIDTH (1)
+#define DI_DEBUG_O_DMA0_RD_REQ_MASK (0x00000400)
+#define DI_DEBUG_O_DMA0_RD_REQ_BIT (0x00000400)
+
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_LSB (9)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_WIDTH (1)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_MASK (0x00000200)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_BIT (0x00000200)
+
+#define DI_DEBUG_RAM_FULL_LSB (8)
+#define DI_DEBUG_RAM_FULL_WIDTH (1)
+#define DI_DEBUG_RAM_FULL_MASK (0x00000100)
+#define DI_DEBUG_RAM_FULL_BIT (0x00000100)
+
+#define DI_DEBUG_CHECK_DONE_LSB (7)
+#define DI_DEBUG_CHECK_DONE_WIDTH (1)
+#define DI_DEBUG_CHECK_DONE_MASK (0x00000080)
+#define DI_DEBUG_CHECK_DONE_BIT (0x00000080)
+
+#define DI_DEBUG_DI_OUT_BIT_FINISH_LSB (6)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_WIDTH (1)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_MASK (0x00000040)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_BIT (0x00000040)
+
+#define DI_DEBUG_RAM_ALL_RDATA_READ_LSB (5)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_WIDTH (1)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_MASK (0x00000020)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_BIT (0x00000020)
+
+#define DI_DEBUG_DI_BUSY_LSB (4)
+#define DI_DEBUG_DI_BUSY_WIDTH (1)
+#define DI_DEBUG_DI_BUSY_MASK (0x00000010)
+#define DI_DEBUG_DI_BUSY_BIT (0x00000010)
+
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_LSB (3)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_MASK (0x00000008)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_BIT (0x00000008)
+
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_LSB (2)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_WIDTH (1)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_MASK (0x00000004)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_BIT (0x00000004)
+
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_LSB (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_MASK (0x00000002)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_BIT (0x00000002)
+
+#define DI_DEBUG_CRC_BUF_OUT_SEL_LSB (0)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_MASK (0x00000001)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_BIT (0x00000001)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_LSB (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_MASK (0x000000FF)
+
+#define ENC_FSM_STATE_WT_CONV_STATE_LSB (17)
+#define ENC_FSM_STATE_WT_CONV_STATE_WIDTH (3)
+#define ENC_FSM_STATE_WT_CONV_STATE_MASK (0x000E0000)
+
+#define ENC_FSM_STATE_LTE_STATE_LSB (13)
+#define ENC_FSM_STATE_LTE_STATE_WIDTH (4)
+#define ENC_FSM_STATE_LTE_STATE_MASK (0x0001E000)
+
+#define ENC_FSM_STATE_CODEC_DIS_STATE_LSB (10)
+#define ENC_FSM_STATE_CODEC_DIS_STATE_WIDTH (3)
+#define ENC_FSM_STATE_CODEC_DIS_STATE_MASK (0x00001C00)
+
+#define ENC_FSM_STATE_CODEC_EN_STATE_LSB (6)
+#define ENC_FSM_STATE_CODEC_EN_STATE_WIDTH (4)
+#define ENC_FSM_STATE_CODEC_EN_STATE_MASK (0x000003C0)
+
+#define ENC_FSM_STATE_CODEC_W_STATE_LSB (3)
+#define ENC_FSM_STATE_CODEC_W_STATE_WIDTH (3)
+#define ENC_FSM_STATE_CODEC_W_STATE_MASK (0x00000038)
+
+#define ENC_FSM_STATE_CODEC_STATE_LSB (0)
+#define ENC_FSM_STATE_CODEC_STATE_WIDTH (3)
+#define ENC_FSM_STATE_CODEC_STATE_MASK (0x00000007)
+
+#define CRC_DBG_FLAG_CRC_LEN_DBG_LSB (26)
+#define CRC_DBG_FLAG_CRC_LEN_DBG_WIDTH (5)
+#define CRC_DBG_FLAG_CRC_LEN_DBG_MASK (0x7C000000)
+
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_LSB (25)
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_WIDTH (1)
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_MASK (0x02000000)
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_BIT (0x02000000)
+
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_LSB (24)
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_WIDTH (1)
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_MASK (0x01000000)
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_BIT (0x01000000)
+
+#define CRC_DBG_FLAG_CRC_STATE_DBG_LSB (16)
+#define CRC_DBG_FLAG_CRC_STATE_DBG_WIDTH (6)
+#define CRC_DBG_FLAG_CRC_STATE_DBG_MASK (0x003F0000)
+
+#define CRC_DBG_FLAG_BIT_CNT_DBG_LSB (0)
+#define CRC_DBG_FLAG_BIT_CNT_DBG_WIDTH (15)
+#define CRC_DBG_FLAG_BIT_CNT_DBG_MASK (0x00007FFF)
+
+#define INTLV_B_LWT_ST_0_LTE_WEN_ST_LSB (15)
+#define INTLV_B_LWT_ST_0_LTE_WEN_ST_WIDTH (3)
+#define INTLV_B_LWT_ST_0_LTE_WEN_ST_MASK (0x00038000)
+
+#define INTLV_B_LWT_ST_0_TS_W_STATE_LSB (12)
+#define INTLV_B_LWT_ST_0_TS_W_STATE_WIDTH (3)
+#define INTLV_B_LWT_ST_0_TS_W_STATE_MASK (0x00007000)
+
+#define INTLV_B_LWT_ST_0_TS_R_STATE_LSB (9)
+#define INTLV_B_LWT_ST_0_TS_R_STATE_WIDTH (3)
+#define INTLV_B_LWT_ST_0_TS_R_STATE_MASK (0x00000E00)
+
+#define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_LSB (6)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_WIDTH (3)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_MASK (0x000001C0)
+
+#define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_LSB (3)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_WIDTH (3)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_MASK (0x00000038)
+
+#define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_LSB (0)
+#define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_WIDTH (3)
+#define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_MASK (0x00000007)
+
+#define INTLV_B_LWT_ST_1_CLM_CNT_LSB (25)
+#define INTLV_B_LWT_ST_1_CLM_CNT_WIDTH (5)
+#define INTLV_B_LWT_ST_1_CLM_CNT_MASK (0x3E000000)
+
+#define INTLV_B_LWT_ST_1_ROW_CNT_LSB (22)
+#define INTLV_B_LWT_ST_1_ROW_CNT_WIDTH (3)
+#define INTLV_B_LWT_ST_1_ROW_CNT_MASK (0x01C00000)
+
+#define INTLV_B_LWT_ST_1_BLK_CNT_LSB (14)
+#define INTLV_B_LWT_ST_1_BLK_CNT_WIDTH (8)
+#define INTLV_B_LWT_ST_1_BLK_CNT_MASK (0x003FC000)
+
+#define INTLV_B_LWT_ST_1_SEC_REQO_LSB (13)
+#define INTLV_B_LWT_ST_1_SEC_REQO_WIDTH (1)
+#define INTLV_B_LWT_ST_1_SEC_REQO_MASK (0x00002000)
+#define INTLV_B_LWT_ST_1_SEC_REQO_BIT (0x00002000)
+
+#define INTLV_B_LWT_ST_1_PPR_REQ_UPA_LSB (9)
+#define INTLV_B_LWT_ST_1_PPR_REQ_UPA_WIDTH (4)
+#define INTLV_B_LWT_ST_1_PPR_REQ_UPA__MASK (0x00001E00)
+
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_LSB (5)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_WIDTH (4)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_MASK (0x000001E0)
+
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_LSB (4)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_WIDTH (1)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_MASK (0x00000010)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_BIT (0x00000010)
+
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_LSB (3)
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_WIDTH (1)
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_MASK (0x00000008)
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_BIT (0x00000008)
+
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_LSB (2)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_WIDTH (1)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_MASK (0x00000004)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_BIT (0x00000004)
+
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_LSB (1)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_WIDTH (1)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_MASK (0x00000002)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_BIT (0x00000002)
+
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_LSB (0)
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_WIDTH (1)
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_MASK (0x00000001)
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_BIT (0x00000001)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_LSB (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_WIDTH (6)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_MASK (0x03F00000)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_WIDTH (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_MASK (0x000FFFFF)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_LSB (16)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_WIDTH (4)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_MASK (0x000F0000)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_LSB (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_WIDTH (9)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_MASK (0x0000FF80)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_WIDTH (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_MASK (0x0000007F)
+
+#define RM_FSM_STATE_BIT_SEP_STATE_LSB (16)
+#define RM_FSM_STATE_BIT_SEP_STATE_WIDTH (3)
+#define RM_FSM_STATE_BIT_SEP_STATE_MASK (0x00070000)
+
+#define RM_FSM_STATE_BC_STATE_LSB (0)
+#define RM_FSM_STATE_BC_STATE_WIDTH (16)
+#define RM_FSM_STATE_BC_STATE_MASK (0x0000FFFF)
+
+#define RUMAP_FSM_STATE_BUF_STATE_LSB (5)
+#define RUMAP_FSM_STATE_BUF_STATE_WIDTH (1)
+#define RUMAP_FSM_STATE_BUF_STATE_MASK (0x00000020)
+#define RUMAP_FSM_STATE_BUF_STATE_BIT (0x00000020)
+
+#define RUMAP_FSM_STATE_RU_MAP_STATE_LSB (0)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_WIDTH (5)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_MASK (0x0000001F)
+
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_LSB (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_MASK (0x00000002)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_BIT (0x00000002)
+
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_LSB (0)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_MASK (0x00000001)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_BIT (0x00000001)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_LSB (13)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_MASK (0x00006000)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_LSB (11)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_MASK (0x00001800)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_LSB (9)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_MASK (0x00000600)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_LSB (7)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_MASK (0x00000180)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_LSB (5)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_MASK (0x00000060)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_LSB (4)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_MASK (0x00000010)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_BIT (0x00000010)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_LSB (3)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_MASK (0x00000008)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_BIT (0x00000008)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_LSB (2)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_MASK (0x00000004)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_BIT (0x00000004)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_LSB (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_MASK (0x00000002)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_BIT (0x00000002)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_LSB (0)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_MASK (0x00000001)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_BIT (0x00000001)
+
+#define C2K_READ_RST_LSB (0)
+#define C2K_READ_RST_WIDTH (1)
+#define C2K_READ_RST_MASK (0x00000001)
+#define C2K_READ_RST_BIT (0x00000001)
+
+#define RTT_START_LSB (0)
+#define RTT_START_WIDTH (1)
+#define RTT_START_MASK (0x00000001)
+#define RTT_START_BIT (0x00000001)
+
+#define TXA_INPUT_LEN_LSB (0)
+#define TXA_INPUT_LEN_WIDTH (13)
+#define TXA_INPUT_LEN_MASK (0x00001FFF)
+
+#define TXA_PUNC_LSB (0)
+#define TXA_PUNC_WIDTH (5)
+#define TXA_PUNC_MASK (0x0000001F)
+
+#define TXA_HA_MODE_TX_SUP_CH_REP_LSB (10)
+#define TXA_HA_MODE_TX_SUP_CH_REP_WIDTH (3)
+#define TXA_HA_MODE_TX_SUP_CH_REP_MASK (0x00001C00)
+
+#define TXA_HA_MODE_TX_CLK_EN_LSB (9)
+#define TXA_HA_MODE_TX_CLK_EN_WIDTH (1)
+#define TXA_HA_MODE_TX_CLK_EN_MASK (0x00000200)
+#define TXA_HA_MODE_TX_CLK_EN_BIT (0x00000200)
+
+#define TXA_HA_MODE_TURBO_TEST_LSB (8)
+#define TXA_HA_MODE_TURBO_TEST_WIDTH (1)
+#define TXA_HA_MODE_TURBO_TEST_MASK (0x00000100)
+#define TXA_HA_MODE_TURBO_TEST_BIT (0x00000100)
+
+#define TXA_HA_MODE_INTRLV_RATE_LSB (6)
+#define TXA_HA_MODE_INTRLV_RATE_WIDTH (2)
+#define TXA_HA_MODE_INTRLV_RATE_MASK (0x000000C0)
+
+#define TXA_HA_MODE_INTRLV_TYPE_LSB (4)
+#define TXA_HA_MODE_INTRLV_TYPE_WIDTH (2)
+#define TXA_HA_MODE_INTRLV_TYPE_MASK (0x00000030)
+
+#define TXA_HA_MODE_ENC_RATE_LSB (2)
+#define TXA_HA_MODE_ENC_RATE_WIDTH (2)
+#define TXA_HA_MODE_ENC_RATE_MASK (0x0000000C)
+
+#define TXA_HA_MODE_ENC_TYPE_LSB (1)
+#define TXA_HA_MODE_ENC_TYPE_WIDTH (1)
+#define TXA_HA_MODE_ENC_TYPE_MASK (0x00000002)
+#define TXA_HA_MODE_ENC_TYPE_BIT (0x00000002)
+
+#define TXA_HA_MODE_TX_HA_MEM_RST_LSB (0)
+#define TXA_HA_MODE_TX_HA_MEM_RST_WIDTH (1)
+#define TXA_HA_MODE_TX_HA_MEM_RST_MASK (0x00000001)
+#define TXA_HA_MODE_TX_HA_MEM_RST_BIT (0x00000001)
+
+#define TXA_INTRLV_PARM_BLK_J1_LSB (9)
+#define TXA_INTRLV_PARM_BLK_J1_WIDTH (3)
+#define TXA_INTRLV_PARM_BLK_J1_MASK (0x00000E00)
+
+#define TXA_INTRLV_PARM_BLK_J0_LSB (6)
+#define TXA_INTRLV_PARM_BLK_J0_WIDTH (3)
+#define TXA_INTRLV_PARM_BLK_J0_MASK (0x000001C0)
+
+#define TXA_INTRLV_PARM_BLK_M_LSB (4)
+#define TXA_INTRLV_PARM_BLK_M_WIDTH (2)
+#define TXA_INTRLV_PARM_BLK_M_MASK (0x00000030)
+
+#define TXA_INTRLV_PARM_TURBO_N_LSB (0)
+#define TXA_INTRLV_PARM_TURBO_N_WIDTH (3)
+#define TXA_INTRLV_PARM_TURBO_N_MASK (0x00000007)
+
+#define TXA_FREP_L_LSB (0)
+#define TXA_FREP_L_WIDTH (14)
+#define TXA_FREP_L_MASK (0x00003FFF)
+
+#define CHL_TYPE_LSB (0)
+#define CHL_TYPE_WIDTH (2)
+#define CHL_TYPE_MASK (0x00000003)
+
+#define TXA_CRC_RTT_RC_IDX_LSB (5)
+#define TXA_CRC_RTT_RC_IDX_WIDTH (1)
+#define TXA_CRC_RTT_RC_IDX_MASK (0x00000020)
+#define TXA_CRC_RTT_RC_IDX_BIT (0x00000020)
+
+#define TXA_CRC_TXA_CRC_LEN_LSB (0)
+#define TXA_CRC_TXA_CRC_LEN_WIDTH (5)
+#define TXA_CRC_TXA_CRC_LEN_MASK (0x0000001F)
+
+#define TXA_FREP_LPML_LSB (0)
+#define TXA_FREP_LPML_WIDTH (15)
+#define TXA_FREP_LPML_MASK (0x00007FFF)
+
+#define TXA_FREP_MM1_LSB (0)
+#define TXA_FREP_MM1_WIDTH (15)
+#define TXA_FREP_MM1_MASK (0x00007FFF)
+
+#define TXA_FREP_ACC0_LSB (0)
+#define TXA_FREP_ACC0_WIDTH (15)
+#define TXA_FREP_ACC0_MASK (0x00007FFF)
+
+#define TXA_PUNC_PAT0_LSB (0)
+#define TXA_PUNC_PAT0_WIDTH (16)
+#define TXA_PUNC_PAT0_MASK (0x0000FFFF)
+
+#define TXA_PUNC_PAT1_LSB (0)
+#define TXA_PUNC_PAT1_WIDTH (16)
+#define TXA_PUNC_PAT1_MASK (0x0000FFFF)
+
+#define TXA_FREP_LP_LSB (0)
+#define TXA_FREP_LP_WIDTH (15)
+#define TXA_FREP_LP_MASK (0x00007FFF)
+
+#define TXA_TST_CTRL_TXA_ADD_LSB (2)
+#define TXA_TST_CTRL_TXA_ADD_WIDTH (11)
+#define TXA_TST_CTRL_TXA_ADD_MASK (0x00001FFC)
+
+#define TXA_TST_CTRL_TXA_ADD_MD_LSB (1)
+#define TXA_TST_CTRL_TXA_ADD_MD_WIDTH (1)
+#define TXA_TST_CTRL_TXA_ADD_MD_MASK (0x00000002)
+#define TXA_TST_CTRL_TXA_ADD_MD_BIT (0x00000002)
+
+#define TXA_TST_CTRL_TXA_TST_MD_LSB (0)
+#define TXA_TST_CTRL_TXA_TST_MD_WIDTH (1)
+#define TXA_TST_CTRL_TXA_TST_MD_MASK (0x00000001)
+#define TXA_TST_CTRL_TXA_TST_MD_BIT (0x00000001)
+
+#define RTT_CHNL_BASE_ADDR_LSB (0)
+#define RTT_CHNL_BASE_ADDR_WIDTH (32)
+#define RTT_CHNL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_LSB (2)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_WIDTH (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_MASK (0x00000004)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_BIT (0x00000004)
+
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_LSB (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_WIDTH (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_MASK (0x00000002)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_BIT (0x00000002)
+
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_LSB (0)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_WIDTH (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_MASK (0x00000001)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_BIT (0x00000001)
+
+#define TXBRP_DBG_CRC32_RSLT_I_LSB (0)
+#define TXBRP_DBG_CRC32_RSLT_I_WIDTH (24)
+#define TXBRP_DBG_CRC32_RSLT_I_MASK (0x00FFFFFF)
+
+#define TXBRP_DBG_CRC32_RSLT_Q_LSB (0)
+#define TXBRP_DBG_CRC32_RSLT_Q_WIDTH (24)
+#define TXBRP_DBG_CRC32_RSLT_Q_MASK (0x00FFFFFF)
+
+#define DEBUG_CRC_SEL_LSB (0)
+#define DEBUG_CRC_SEL_WIDTH (4)
+#define DEBUG_CRC_SEL_MASK (0x0000000F)
+
+#endif //#ifndef _CPH_1X_TXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxcrp.h b/mcu/interface/l1/cl1/common/HW/cph1xtxcrp.h
new file mode 100644
index 0000000..cfe1355
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxcrp.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXCRP_H_
+#define _CPH_1X_TXCRP_H_
+
+/** TBD: Common register read and write function, maybe replaced later */
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_C_1XRTT_REG_BASE (0xa8160000)
+#else
+#define TXCRP_C_1XRTT_REG_BASE (0xa8960000)
+#endif
+#define TXCRP_C_1XRTT_end (TXCRP_C_1XRTT_REG_BASE + 0x0064 + 1*4)
+
+#define C1XTXCRP_ACK1_BIT ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0000))
+#define C1XTXCRP_CTRL ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0004))
+#define C1XTXCRP_PC_BIT_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0008))
+#define C1XTXCRP_FCH_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x000C))
+#define C1XTXCRP_SCH_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0010))
+#define C1XTXCRP_PILOT_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0014))
+#define C1XTXCRP_ACKCH1_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0018))
+#define C1XTXCRP_TEST_CTRL ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x001C))
+#define C1XTXCRP_LC_INIT_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0020))
+#define C1XTXCRP_LC_INIT_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0024))
+#define C1XTXCRP_LC_INIT_2 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0028))
+#define C1XTXCRP_LC_MASK_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x002C))
+#define C1XTXCRP_LC_MASK_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0030))
+#define C1XTXCRP_LC_MASK_2 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0034))
+#define C1XTXCRP_LC_SCRAMBLE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0038))
+#define C1XTXCRP_ACTIVE_STOP ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x003C))
+#define C1XTXCRP_SC_INIT_PCG ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0040))
+#define C1XTXCRP_FCH_STATUS ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0044))
+#define C1XTXCRP_KS_START ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0048))
+#define C1XTXCRP_KS_SQUARE_DB_RESULT ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x004C))
+#define C1XTXCRP_PCG_INDEX_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0054))
+#define C1XTXCRP_TXBRP_MEM_END_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0058))
+#define C1XTXCRP_DEBUG_OB_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x005C))
+#define C1XTXCRP_DEBUG_OB_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0060))
+#define C1XTXCRP_LATCH_SWITCH ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0064))
+//#define C1XTXCRP_SW_RESET ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0068))
+
+/** Register filed definition */
+#define ACKCH1_RESULT_LSB (0)
+#define ACKCH1_RESULT_WIDTH (1)
+#define ACKCH1_RESULT_MASK (0x00000001)
+#define ACKCH1_RESULT_BIT (0x00000001)
+
+#define ACKCH1_EN_LSB (8)
+#define ACKCH1_EN_WIDTH (1)
+#define ACKCH1_EN_MASK (0x00000100)
+#define ACKCH1_EN_BIT (0x00000100)
+
+#define SCH_WALSH_COVER_LSB (6)
+#define SCH_WALSH_COVER_WIDTH (2)
+#define SCH_WALSH_COVER_MASK (0x000000C0)
+
+#define PILOT_EN_LSB (5)
+#define PILOT_EN_WIDTH (1)
+#define PILOT_EN_MASK (0x00000020)
+#define PILOT_EN_BIT (0x00000020)
+
+#define SCH_EN_LSB (4)
+#define SCH_EN_WIDTH (1)
+#define SCH_EN_MASK (0x00000010)
+#define SCH_EN_BIT (0x00000010)
+
+#define FCH_EN_LSB (2)
+#define FCH_EN_WIDTH (1)
+#define FCH_EN_MASK (0x00000004)
+#define FCH_EN_BIT (0x00000004)
+
+#define IS95_EN_LSB (0)
+#define IS95_EN_WIDTH (1)
+#define IS95_EN_MASK (0x00000001)
+#define IS95_EN_BIT (0x00000001)
+
+#define PC_BIT_MANUAL_LSB (1)
+#define PC_BIT_MANUAL_WIDTH (1)
+#define PC_BIT_MANUAL_MASK (0x00000002)
+#define PC_BIT_MANUAL_BIT (0x00000002)
+
+#define PC_BIT_MANUAL_EN_LSB (0)
+#define PC_BIT_MANUAL_EN_WIDTH (1)
+#define PC_BIT_MANUAL_EN_MASK (0x00000001)
+#define PC_BIT_MANUAL_EN_BIT (0x00000001)
+
+#define FCH_SCALE_LSB (0)
+#define FCH_SCALE_WIDTH (9)
+#define FCH_SCALE_MASK (0x000001FF)
+
+#define SCH_SCALE_LSB (0)
+#define SCH_SCALE_WIDTH (9)
+#define SCH_SCALE_MASK (0x000001FF)
+
+#define PILOT_SCALE_LSB (0)
+#define PILOT_SCALE_WIDTH (9)
+#define PILOT_SCALE_MASK (0x000001FF)
+
+#define ACKCH1_SCALE_LSB (0)
+#define ACKCH1_SCALE_WIDTH (9)
+#define ACKCH1_SCALE_MASK (0x000001FF)
+
+#define TESTCTRL_HW_CLKEN_BYP_LSB (1)
+#define TESTCTRL_HW_CLKEN_BYP_WIDTH (1)
+#define TESTCTRL_HW_CLKEN_BYP_MASK (0x00000002)
+#define TESTCTRL_HW_CLKEN_BYP_BIT (0x00000002)
+
+#define TESTCTRL_CONJUGATE_LSB (0)
+#define TESTCTRL_CONJUGATE_WIDTH (1)
+#define TESTCTRL_CONJUGATE_MASK (0x00000001)
+#define TESTCTRL_CONJUGATE_BIT (0x00000001)
+
+#define LC_INIT_VALUE_15_0_LSB (0)
+#define LC_INIT_VALUE_15_0_WIDTH (16)
+#define LC_INIT_VALUE_15_0_MASK (0x0000FFFF)
+
+#define LC_INIT_VALUE_31_16_LSB (0)
+#define LC_INIT_VALUE_31_16_WIDTH (16)
+#define LC_INIT_VALUE_31_16_MASK (0x0000FFFF)
+
+#define LC_INIT_VALUE_41_32_LSB (0)
+#define LC_INIT_VALUE_41_32_WIDTH (10)
+#define LC_INIT_VALUE_41_32_MASK (0x000003FF)
+
+#define LC_MASK_15_0_LSB (0)
+#define LC_MASK_15_0_WIDTH (16)
+#define LC_MASK_15_0_MASK (0x0000FFFF)
+
+#define LC_MASK_31_16_LSB (0)
+#define LC_MASK_31_16_WIDTH (16)
+#define LC_MASK_31_16_MASK (0x0000FFFF)
+
+#define LC_MASK_41_32_LSB (0)
+#define LC_MASK_41_32_WIDTH (10)
+#define LC_MASK_41_32_MASK (0x000003FF)
+
+#define LC_SCRAMBLE_LSB (0)
+#define LC_SCRAMBLE_WIDTH (14)
+#define LC_SCRAMBLE_MASK (0x00003FFF)
+
+#define ACTIVE_EN_LSB (1)
+#define ACTIVE_EN_WIDTH (1)
+#define ACTIVE_EN_MASK (0x00000002)
+#define ACTIVE_EN_BIT (0x00000002)
+
+#define STOP_BY_PCG_LSB (0)
+#define STOP_BY_PCG_WIDTH (1)
+#define STOP_BY_PCG_MASK (0x00000001)
+#define STOP_BY_PCG_BIT (0x00000001)
+
+#define SC_INIT_PCG_LSB (1)
+#define SC_INIT_PCG_WIDTH (6)
+#define SC_INIT_PCG_MASK (0x0000007E)
+
+#define SC_INIT_PCG_START_LSB (0)
+#define SC_INIT_PCG_START_WIDTH (1)
+#define SC_INIT_PCG_START_MASK (0x00000001)
+#define SC_INIT_PCG_START_BIT (0x00000001)
+
+#define FCH_PREAMBLE_EN_LSB (1)
+#define FCH_PREAMBLE_EN_WIDTH (1)
+#define FCH_PREAMBLE_EN_MASK (0x00000002)
+#define FCH_PREAMBLE_EN_BIT (0x00000002)
+
+#define FCH_GATING_EN_LSB (0)
+#define FCH_GATING_EN_WIDTH (1)
+#define FCH_GATING_EN_MASK (0x00000001)
+#define FCH_GATING_EN_BIT (0x00000001)
+
+#define KS_CALC_START_LSB (1)
+#define KS_CALC_START_WIDTH (1)
+#define KS_CALC_START_MASK (0x00000002)
+#define KS_CALC_START_BIT (0x00000002)
+
+#define KS_CALC_MANUAL_LSB (0)
+#define KS_CALC_MANUAL_WIDTH (1)
+#define KS_CALC_MANUAL_MASK (0x00000001)
+#define KS_CALC_MANUAL_BIT (0x00000001)
+
+#define KS_CALC_RESULT_LSB (1)
+#define KS_CALC_RESULT_WIDTH (13)
+#define KS_CALC_RESULT_MASK (0x00003FFE)
+
+#define KS_CALC_FINISH_LSB (0)
+#define KS_CALC_FINISH_WIDTH (1)
+#define KS_CALC_FINISH_MASK (0x00000001)
+#define KS_CALC_FINISH_BIT (0x00000001)
+
+#define PCG_INDEX_MANUAL_LSB (1)
+#define PCG_INDEX_MANUAL_WIDTH (4)
+#define PCG_INDEX_MANUAL_MASK (0x0000001E)
+
+#define PCG_INDEX_MANUAL_EN_LSB (0)
+#define PCG_INDEX_MANUAL_EN_WIDTH (1)
+#define PCG_INDEX_MANUAL_EN_MASK (0x00000001)
+#define PCG_INDEX_MANUAL_EN_BIT (0x00000001)
+
+#define TXBRP_ADDR_2_MANUAL_EN_LSB (10)
+#define TXBRP_ADDR_2_MANUAL_EN_WIDTH (10)
+#define TXBRP_ADDR_2_MANUAL_EN_MASK (0x000FFC00)
+
+#define TXBRP_ADDR_1_MANUAL_EN_LSB (1)
+#define TXBRP_ADDR_1_MANUAL_EN_WIDTH (9)
+#define TXBRP_ADDR_1_MANUAL_EN_MASK (0x000003FE)
+
+#define TXBRP_ADDR_MANUAL_EN_LSB (0)
+#define TXBRP_ADDR_MANUAL_EN_WIDTH (1)
+#define TXBRP_ADDR_MANUAL_EN_MASK (0x00000001)
+#define TXBRP_ADDR_MANUAL_EN_BIT (0x00000001)
+
+#define HW_DEBUG_OB_31_0_LSB (0)
+#define HW_DEBUG_OB_31_0_WIDTH (32)
+#define HW_DEBUG_OB_31_0_MASK (0xFFFFFFFF)
+
+#define HW_DEBUG_OB_63_32_LSB (0)
+#define HW_DEBUG_OB_63_32_WIDTH (32)
+#define HW_DEBUG_OB_63_32_MASK (0xFFFFFFFF)
+
+#define LATCH_SWITCH_LSB (0)
+#define LATCH_SWITCH_WIDTH (1)
+#define LATCH_SWITCH_MASK (0x00000001)
+#define LATCH_SWITCH_BIT (0x00000001)
+
+#define SW_RST_LSB (0)
+#define SW_RST_WIDTH (1)
+#define SW_RST_MASK (0x00000001)
+#define SW_RST_BIT (0x00000001)
+
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h b/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h
new file mode 100644
index 0000000..5e2849a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h
@@ -0,0 +1,65 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXTRM_H_
+#define _CPH_1X_TX_TRM_H_
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define TXTMR_C_1XRTT_REG_BASE (0) /**TBD*/
+
+#define C1XTXTMR_ENABLE ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0000))
+#define C1XTXTMR_FRAME_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0004))
+#define C1XTXTMR_TRX_DLY ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0008))
+#define C1XTXTMR_RA_DLY ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x000C))
+#define C1XTXTMR_TXDFE_WIN_ON_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0010))
+#define C1XTXTMR_TXDFE_WIN_OFF_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0014))
+#define C1XTXTMR_TXDFE_FIFO_WIN_ON_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0018))
+#define C1XTXTMR_TXDFE_FIFO_WIN_OFF_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x001C))
+#define C1XTXTMR_TXDAC_WIN_ON_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0020))
+#define C1XTXTMR_TXDAC_WIN_OFF_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0024))
+#define C1XTXTMR_TXBRP_STR ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0028))
+#define C1XTXTMR_TXCRP_STR ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x002C))
+#define C1XTXTMR_KS_STR ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0030))
+#define C1XTXTMR_SYSTMR_CNT ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0034))
+
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphb2rif.h b/mcu/interface/l1/cl1/common/HW/cphb2rif.h
new file mode 100644
index 0000000..b6e5d9a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphb2rif.h
@@ -0,0 +1,39 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__) || defined(__MD95__)
+#include "cphb2rif_93_95.h"
+#else
+#include "cphb2rif_97.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphb2rif_93_95.h b/mcu/interface/l1/cl1/common/HW/cphb2rif_93_95.h
new file mode 100644
index 0000000..97293d6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphb2rif_93_95.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _EL1D_REG_ELBRUS_H_
+#define _EL1D_REG_ELBRUS_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define B2RIF_REG_BASE (0xAC100000)
+
+#define B2RIF_end (B2RIF_REG_BASE + 0x003C + 1*4)
+
+
+
+#define B2RIF_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0000))
+#define B2RIF_SW_RST ((APBADDR32)(B2RIF_REG_BASE + 0x0004))
+#define B2RIF_2SLOT_IND ((APBADDR32)(B2RIF_REG_BASE + 0x0008))
+#define B2RIF_DIS ((APBADDR32)(B2RIF_REG_BASE + 0x000C))
+#define B2RIF_DBG_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0010))
+#define B2RIF_RREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0014))
+#define B2RIF_RRDY_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0018))
+#define B2RIF_LREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x001C))
+#define B2RIF_R_CON_A0C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0020))
+#define B2RIF_R_CON_A1C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0024))
+#define B2RIF_R_CON_A0C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0028))
+#define B2RIF_R_CON_A1C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x002C))
+#define B2RIF_R_CON_A0C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0030))
+#define B2RIF_R_CON_A1C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0034))
+#define B2RIF_R_CON_A0C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0038))
+#define B2RIF_R_CON_A1C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x003C))
+#define B2RIF_R_CON_QLIC_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0040))
+#define B2RIF_R_CON_QLIC_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0044))
+#define B2RIF_HOLD_STA ((APBADDR32)(B2RIF_REG_BASE + 0x0048))
+
+
+#define B2RIF_CON_B2RIF_MODE_LSB (2)
+#define B2RIF_CON_B2RIF_MODE_WIDTH (2)
+#define B2RIF_CON_B2RIF_MODE_MASK (0x0000000C)
+
+#define B2RIF_CON_B2RIF_QLIC_EN_LSB (1)
+#define B2RIF_CON_B2RIF_QLIC_EN_WIDTH (1)
+#define B2RIF_CON_B2RIF_QLIC_EN_MASK (0x00000002)
+#define B2RIF_CON_B2RIF_QLIC_EN_BIT (0x00000002)
+
+#define B2RIF_CON_B2RIF_EN_LSB (0)
+#define B2RIF_CON_B2RIF_EN_WIDTH (1)
+#define B2RIF_CON_B2RIF_EN_MASK (0x00000001)
+#define B2RIF_CON_B2RIF_EN_BIT (0x00000001)
+
+#define B2RIF_SW_RST_B2RIF_SW_RST_LSB (0)
+#define B2RIF_SW_RST_B2RIF_SW_RST_WIDTH (1)
+#define B2RIF_SW_RST_B2RIF_SW_RST_MASK (0x00000001)
+#define B2RIF_SW_RST_B2RIF_SW_RST_BIT (0x00000001)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_LSB (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_MASK (0x00000002)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_BIT (0x00000002)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_LSB (0)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_MASK (0x00000001)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_BIT (0x00000001)
+
+#define B2RIF_DIS_LDR_REQ_DIS_LSB (3)
+#define B2RIF_DIS_LDR_REQ_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_REQ_DIS_MASK (0x00000008)
+#define B2RIF_DIS_LDR_REQ_DIS_BIT (0x00000008)
+
+#define B2RIF_DIS_BRAM_READ0_DIS_LSB (2)
+#define B2RIF_DIS_BRAM_READ0_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ0_DIS_MASK (0x00000004)
+#define B2RIF_DIS_BRAM_READ0_DIS_BIT (0x00000004)
+
+#define B2RIF_DIS_BRAM_READ1_DIS_LSB (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_MASK (0x00000002)
+#define B2RIF_DIS_BRAM_READ1_DIS_BIT (0x00000002)
+
+#define B2RIF_DIS_LDR_LPWR_DIS_LSB (0)
+#define B2RIF_DIS_LDR_LPWR_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_LPWR_DIS_MASK (0x00000001)
+#define B2RIF_DIS_LDR_LPWR_DIS_BIT (0x00000001)
+
+#define B2RIF_DBG_CON_DBG_CLR_LSB (4)
+#define B2RIF_DBG_CON_DBG_CLR_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define B2RIF_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define B2RIF_DBG_CON_DBG_EN_LSB (0)
+#define B2RIF_DBG_CON_DBG_EN_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_EN_MASK (0x00000001)
+#define B2RIF_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_LSB (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_LSB (0)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_LSB (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_LSB (0)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_LSB (0)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_WIDTH (8)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_MASK (0x000000FF)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_LSB (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_LSB (0)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_LSB (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_LSB (0)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_LSB (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_LSB (0)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_LSB (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_LSB (0)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_LSB (0)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_LSB (0)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_LSB (0)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_LSB (0)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_LSB (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_MASH (0xFFFF0000)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_MASH (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_MASH (0x0000FFFF)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_REAL_LSB (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_REAL_WIDTH (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_REAL_MASH (0xFFFF0000)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_LSB (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_WIDTH (1)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_MASH (0x00000100)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MAX_LSB (0)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MAX_WIDTH (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MAX_MASH (0x000000FF)
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphb2rif_97.h b/mcu/interface/l1/cl1/common/HW/cphb2rif_97.h
new file mode 100644
index 0000000..f8b3b6d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphb2rif_97.h
@@ -0,0 +1,261 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_B2RIF_97_H_
+#define _CPH_B2RIF_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define B2RIF_REG_BASE (0xACD00000)
+
+#define B2RIF_end (B2RIF_REG_BASE + 0x0108 + 1*4)
+
+
+
+#define B2RIF_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0000))
+#define B2RIF_SW_RST ((APBADDR32)(B2RIF_REG_BASE + 0x0004))
+#define B2RIF_2SLOT_IND ((APBADDR32)(B2RIF_REG_BASE + 0x0008))
+#define B2RIF_DIS ((APBADDR32)(B2RIF_REG_BASE + 0x000C))
+#define B2RIF_DBG_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0010))
+#define B2RIF_RREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0014))
+#define B2RIF_RRDY_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0018))
+#define B2RIF_LREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x001C))
+#define B2RIF_R_CON_A0C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0020))
+#define B2RIF_R_CON_A1C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0024))
+#define B2RIF_R_CON_A0C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0028))
+#define B2RIF_R_CON_A1C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x002C))
+#define B2RIF_R_CON_A0C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0030))
+#define B2RIF_R_CON_A1C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0034))
+#define B2RIF_R_CON_A0C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0038))
+#define B2RIF_R_CON_A1C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x003C))
+#define B2RIF_R_CON_QLIC_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0040))
+#define B2RIF_R_CON_QLIC_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0044))
+#define B2RIF_HOLD_STA ((APBADDR32)(B2RIF_REG_BASE + 0x0048))
+#define B2RIF_RESERVED0 ((APBADDR32)(B2RIF_REG_BASE + 0x004c))
+#define B2RIF_RESERVED1 ((APBADDR32)(B2RIF_REG_BASE + 0x0050))
+#define IC_SYNC ((APBADDR32)(B2RIF_REG_BASE + 0x0100))
+#define IC_SYNC_SYS_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0104))
+#define IC_SYNC_IC_ADDR ((APBADDR32)(B2RIF_REG_BASE + 0x0108))
+
+
+
+
+#define B2RIF_CON_B2RIF_MODE_LSB (2)
+#define B2RIF_CON_B2RIF_MODE_WIDTH (2)
+#define B2RIF_CON_B2RIF_MODE_MASK (0x0000000C)
+
+#define B2RIF_CON_B2RIF_EN_LSB (0)
+#define B2RIF_CON_B2RIF_EN_WIDTH (1)
+#define B2RIF_CON_B2RIF_EN_MASK (0x00000001)
+#define B2RIF_CON_B2RIF_EN_BIT (0x00000001)
+
+#define B2RIF_SW_RST_B2RIF_SW_RST_LSB (0)
+#define B2RIF_SW_RST_B2RIF_SW_RST_WIDTH (1)
+#define B2RIF_SW_RST_B2RIF_SW_RST_MASK (0x00000001)
+#define B2RIF_SW_RST_B2RIF_SW_RST_BIT (0x00000001)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_LSB (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_MASK (0x00000002)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_BIT (0x00000002)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_LSB (0)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_MASK (0x00000001)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_BIT (0x00000001)
+
+#define B2RIF_DIS_LDR_REQ_DIS_LSB (3)
+#define B2RIF_DIS_LDR_REQ_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_REQ_DIS_MASK (0x00000008)
+#define B2RIF_DIS_LDR_REQ_DIS_BIT (0x00000008)
+
+#define B2RIF_DIS_BRAM_READ0_DIS_LSB (2)
+#define B2RIF_DIS_BRAM_READ0_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ0_DIS_MASK (0x00000004)
+#define B2RIF_DIS_BRAM_READ0_DIS_BIT (0x00000004)
+
+#define B2RIF_DIS_BRAM_READ1_DIS_LSB (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_MASK (0x00000002)
+#define B2RIF_DIS_BRAM_READ1_DIS_BIT (0x00000002)
+
+#define B2RIF_DIS_LDR_LPWR_DIS_LSB (0)
+#define B2RIF_DIS_LDR_LPWR_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_LPWR_DIS_MASK (0x00000001)
+#define B2RIF_DIS_LDR_LPWR_DIS_BIT (0x00000001)
+
+#define B2RIF_DBG_CON_DBG_CLR_LSB (4)
+#define B2RIF_DBG_CON_DBG_CLR_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define B2RIF_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define B2RIF_DBG_CON_DBG_EN_LSB (0)
+#define B2RIF_DBG_CON_DBG_EN_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_EN_MASK (0x00000001)
+#define B2RIF_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_LSB (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_LSB (0)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_LSB (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_LSB (0)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_LSB (0)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_WIDTH (8)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_MASK (0x000000FF)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_LSB (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_LSB (0)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_LSB (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_LSB (0)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_LSB (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_LSB (0)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_LSB (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_LSB (0)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_LSB (0)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_LSB (0)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_LSB (0)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_LSB (0)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_LSB (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_MASK (0x0000FFFF)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_LSB (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_WIDTH (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MASK (0xFFFF0000)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_LSB (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_WIDTH (1)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_MASK (0x00000100)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_BIT (0x00000100)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_MAX_CNT_LSB (0)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_MAX_CNT_WIDTH (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_MAX_CNT_MASK (0x000000FF)
+
+#define B2RIF_RESERVED0_B2RIF_RESERVED0_LSB (0)
+#define B2RIF_RESERVED0_B2RIF_RESERVED0_WIDTH (32)
+#define B2RIF_RESERVED0_B2RIF_RESERVED0_MASK (0xFFFFFFFF)
+
+#define B2RIF_RESERVED1_B2RIF_RESERVED1_LSB (0)
+#define B2RIF_RESERVED1_B2RIF_RESERVED1_WIDTH (32)
+#define B2RIF_RESERVED1_B2RIF_RESERVED1_MASK (0xFFFFFFFF)
+
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_LSB (0)
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_WIDTH (1)
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_MASK (0x00000001)
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_BIT (0x00000001)
+
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_LSB (31)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_WIDTH (1)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_MASK (0x80000000)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_BIT (0x80000000)
+
+#define IC_SYNC_SYS_CNT_B2RIF_IC_RD_SYS_CNT_LSB (0)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_RD_SYS_CNT_WIDTH (20)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_RD_SYS_CNT_MASK (0x000FFFFF)
+
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_LSB (31)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_WIDTH (1)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_MASK (0x80000000)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_BIT (0x80000000)
+
+#define IC_SYNC_IC_ADDR_B2RIF_IC_RD_ADDR_LSB (0)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_RD_ADDR_WIDTH (20)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_RD_ADDR_MASK (0x000FFFFF)
+#endif //#ifndef _CPH_B2RIF_97_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg.h b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg.h
new file mode 100644
index 0000000..6f6c5a9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphbigramglbconreg_93.h"
+#elif defined(__MD95__)
+#include "cphbigramglbconreg_95.h"
+#else
+#include "cphbigramglbconreg_95.h"/*#error "[ERROR] Invalid MD generation" For build error*/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_93.h b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_93.h
new file mode 100644
index 0000000..174950d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_93.h
@@ -0,0 +1,1282 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_BIGRAM_GLB_CON_REG_H_
+#define _CPH_BIGRAM_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define BIGRAM_GLOBAL_CON_REG_BASE (0xAB810000)
+
+#define BIGRAM_GLOBAL_CON_end (BIGRAM_GLOBAL_CON_REG_BASE + 0x0118 + 1*4)
+
+
+
+#define BIGRAM_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0000))
+#define BIGRAM_PWR_AWARE_CTRL ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0004))
+#define BIGRAM_LTE_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0008))
+#define BIGRAM_LTE_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x000C))
+#define BIGRAM_LTE_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0010))
+#define BIGRAM_FDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0018))
+#define BIGRAM_FDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x001C))
+#define BIGRAM_FDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0020))
+#define BIGRAM_TDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0028))
+#define BIGRAM_TDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x002C))
+#define BIGRAM_TDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0030))
+#define BIGRAM_C2K_1XRTT_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0038))
+#define BIGRAM_C2K_1XRTT_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x003C))
+#define BIGRAM_C2K_1XRTT_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0040))
+#define BIGRAM_C2K_EVDO_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0048))
+#define BIGRAM_C2K_EVDO_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x004C))
+#define BIGRAM_C2K_EVDO_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0050))
+#define BIGRAM_LTE_EL1D_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0058))
+#define BIGRAM_LTE_EL1D_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x005C))
+#define BIGRAM_LTE_EL1D_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0060))
+#define BIGRAM_CK_IDLE_DIV ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0068))
+#define BIGRAM_CK_IDLE_MASK ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x006C))
+#define BIGRAM_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0100))
+#define BIGRAM_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0104))
+#define BIGRAM_SLV_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0108))
+#define BIGRAM_SLV_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x010C))
+#define BIGRAM_SLV_BUS_STATUS1 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0110))
+#define BIGRAM_BUS_DBGOUT ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0114))
+#define BIGRAM_CLK_DIV2_DIS ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0118))
+
+
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_LSB (10)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_MASK (0x00000400)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_BIT (0x00000400)
+
+#define BIGRAM_CG_CON_DSTDB_CK_CG_LSB (9)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_MASK (0x00000200)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_BIT (0x00000200)
+
+#define BIGRAM_CG_CON_D2BIF_CK_CG_LSB (8)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_MASK (0x00000100)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_BIT (0x00000100)
+
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_LSB (7)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_MASK (0x00000080)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_BIT (0x00000080)
+
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_LSB (6)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_MASK (0x00000040)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_BIT (0x00000040)
+
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_LSB (5)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_MASK (0x00000020)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_BIT (0x00000020)
+
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_LSB (4)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_MASK (0x00000010)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_BIT (0x00000010)
+
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_LSB (3)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_MASK (0x00000008)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_BIT (0x00000008)
+
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_LSB (2)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_MASK (0x00000004)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_BIT (0x00000004)
+
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_LSB (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_MASK (0x00000002)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_BIT (0x00000002)
+
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_LSB (0)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_MASK (0x00000001)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_BIT (0x00000001)
+
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_LSB (0)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_WIDTH (32)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_LSB (10)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_LSB (9)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_LSB (8)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_LSB (6)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_LSB (5)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_LSB (10)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_LSB (9)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_LSB (8)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_LSB (6)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_LSB (5)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_LSB (0)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_LSB (10)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_LSB (9)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_LSB (8)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_LSB (6)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_LSB (5)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_LSB (9)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_LSB (8)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_LSB (7)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_LSB (6)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_LSB (5)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_LSB (4)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_LSB (3)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_LSB (2)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_LSB (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_LSB (0)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_BIT (0x00000001)
+
+#define BIGRAM_BUS_CONFIG0_debug_sel_LSB (31)
+#define BIGRAM_BUS_CONFIG0_debug_sel_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_debug_sel_MASK (0x80000000)
+#define BIGRAM_BUS_CONFIG0_debug_sel_BIT (0x80000000)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_LSB (9)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_MASK (0x00000600)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_LSB (7)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_MASK (0x00000180)
+
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_LSB (5)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_MASK (0x00000060)
+
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_LSB (3)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_MASK (0x00000018)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_LSB (2)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_MASK (0x00000004)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_BIT (0x00000004)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_LSB (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_MASK (0x00000002)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_BIT (0x00000002)
+
+#define BIGRAM_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_LSB (3)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_MASK (0x00000008)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_BIT (0x00000008)
+
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_LSB (2)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_MASK (0x00000004)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_BIT (0x00000004)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_LSB (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_MASK (0x00000002)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_BIT (0x00000002)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_LSB (0)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_MASK (0x00000001)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_LSB (5)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_MASK (0x00000060)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_LSB (4)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_LSB (3)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_LSB (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_MASK (0x00000006)
+
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_LSB (21)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_MASK (0x00200000)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_BIT (0x00200000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_LSB (18)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_WIDTH (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_MASK (0x001C0000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_LSB (5)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_WIDTH (13)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_MASK (0x0003FFE0)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_LSB (4)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_LSB (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_LSB (2)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_MASK (0x00000004)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_BIT (0x00000004)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_LSB (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_MASK (0x00000002)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_BIT (0x00000002)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_WIDTH (32)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_MASK (0xFFFFFFFF)
+
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_LSB (0)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_WIDTH (32)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_MASK (0xFFFFFFFF)
+
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_LSB (0)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_WIDTH (1)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_MASK (0x00000001)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_BIGRAM_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_95.h b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_95.h
new file mode 100644
index 0000000..174950d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_95.h
@@ -0,0 +1,1282 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_BIGRAM_GLB_CON_REG_H_
+#define _CPH_BIGRAM_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define BIGRAM_GLOBAL_CON_REG_BASE (0xAB810000)
+
+#define BIGRAM_GLOBAL_CON_end (BIGRAM_GLOBAL_CON_REG_BASE + 0x0118 + 1*4)
+
+
+
+#define BIGRAM_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0000))
+#define BIGRAM_PWR_AWARE_CTRL ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0004))
+#define BIGRAM_LTE_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0008))
+#define BIGRAM_LTE_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x000C))
+#define BIGRAM_LTE_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0010))
+#define BIGRAM_FDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0018))
+#define BIGRAM_FDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x001C))
+#define BIGRAM_FDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0020))
+#define BIGRAM_TDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0028))
+#define BIGRAM_TDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x002C))
+#define BIGRAM_TDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0030))
+#define BIGRAM_C2K_1XRTT_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0038))
+#define BIGRAM_C2K_1XRTT_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x003C))
+#define BIGRAM_C2K_1XRTT_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0040))
+#define BIGRAM_C2K_EVDO_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0048))
+#define BIGRAM_C2K_EVDO_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x004C))
+#define BIGRAM_C2K_EVDO_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0050))
+#define BIGRAM_LTE_EL1D_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0058))
+#define BIGRAM_LTE_EL1D_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x005C))
+#define BIGRAM_LTE_EL1D_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0060))
+#define BIGRAM_CK_IDLE_DIV ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0068))
+#define BIGRAM_CK_IDLE_MASK ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x006C))
+#define BIGRAM_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0100))
+#define BIGRAM_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0104))
+#define BIGRAM_SLV_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0108))
+#define BIGRAM_SLV_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x010C))
+#define BIGRAM_SLV_BUS_STATUS1 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0110))
+#define BIGRAM_BUS_DBGOUT ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0114))
+#define BIGRAM_CLK_DIV2_DIS ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0118))
+
+
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_LSB (10)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_MASK (0x00000400)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_BIT (0x00000400)
+
+#define BIGRAM_CG_CON_DSTDB_CK_CG_LSB (9)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_MASK (0x00000200)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_BIT (0x00000200)
+
+#define BIGRAM_CG_CON_D2BIF_CK_CG_LSB (8)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_MASK (0x00000100)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_BIT (0x00000100)
+
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_LSB (7)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_MASK (0x00000080)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_BIT (0x00000080)
+
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_LSB (6)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_MASK (0x00000040)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_BIT (0x00000040)
+
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_LSB (5)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_MASK (0x00000020)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_BIT (0x00000020)
+
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_LSB (4)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_MASK (0x00000010)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_BIT (0x00000010)
+
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_LSB (3)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_MASK (0x00000008)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_BIT (0x00000008)
+
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_LSB (2)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_MASK (0x00000004)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_BIT (0x00000004)
+
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_LSB (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_MASK (0x00000002)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_BIT (0x00000002)
+
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_LSB (0)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_MASK (0x00000001)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_BIT (0x00000001)
+
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_LSB (0)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_WIDTH (32)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_LSB (10)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_LSB (9)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_LSB (8)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_LSB (6)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_LSB (5)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_LSB (10)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_LSB (9)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_LSB (8)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_LSB (6)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_LSB (5)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_LSB (0)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_LSB (10)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_LSB (9)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_LSB (8)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_LSB (6)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_LSB (5)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_LSB (9)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_LSB (8)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_LSB (7)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_LSB (6)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_LSB (5)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_LSB (4)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_LSB (3)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_LSB (2)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_LSB (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_LSB (0)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_BIT (0x00000001)
+
+#define BIGRAM_BUS_CONFIG0_debug_sel_LSB (31)
+#define BIGRAM_BUS_CONFIG0_debug_sel_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_debug_sel_MASK (0x80000000)
+#define BIGRAM_BUS_CONFIG0_debug_sel_BIT (0x80000000)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_LSB (9)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_MASK (0x00000600)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_LSB (7)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_MASK (0x00000180)
+
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_LSB (5)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_MASK (0x00000060)
+
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_LSB (3)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_MASK (0x00000018)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_LSB (2)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_MASK (0x00000004)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_BIT (0x00000004)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_LSB (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_MASK (0x00000002)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_BIT (0x00000002)
+
+#define BIGRAM_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_LSB (3)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_MASK (0x00000008)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_BIT (0x00000008)
+
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_LSB (2)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_MASK (0x00000004)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_BIT (0x00000004)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_LSB (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_MASK (0x00000002)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_BIT (0x00000002)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_LSB (0)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_MASK (0x00000001)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_LSB (5)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_MASK (0x00000060)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_LSB (4)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_LSB (3)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_LSB (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_MASK (0x00000006)
+
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_LSB (21)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_MASK (0x00200000)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_BIT (0x00200000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_LSB (18)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_WIDTH (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_MASK (0x001C0000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_LSB (5)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_WIDTH (13)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_MASK (0x0003FFE0)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_LSB (4)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_LSB (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_LSB (2)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_MASK (0x00000004)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_BIT (0x00000004)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_LSB (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_MASK (0x00000002)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_BIT (0x00000002)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_WIDTH (32)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_MASK (0xFFFFFFFF)
+
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_LSB (0)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_WIDTH (32)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_MASK (0xFFFFFFFF)
+
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_LSB (0)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_WIDTH (1)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_MASK (0x00000001)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_BIGRAM_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg.h
new file mode 100644
index 0000000..d921103
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphc2kl1aocfg_93.h"
+#elif defined(__MD95__)
+#include "cphc2kl1aocfg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphc2kl1aocfg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_93.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_93.h
new file mode 100644
index 0000000..267f31e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_93.h
@@ -0,0 +1,563 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_L1_A0CFG_H_
+#define _CPH_C2K_L1_A0CFG_H_
+#include "drvpdn.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MODEML1_AO_CONFIG_REG_BASE (0xA6020000)
+
+#define MODEML1_AO_CONFIG_end (MODEML1_AO_CONFIG_REG_BASE + 0x350 + 1*4)
+
+
+
+#define MDL1AO_CON0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x00))
+#define MDL1AO_CON1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x04))
+#define MDL1AO_CON2 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x08))
+#define MDL1AO_CON4 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x10))
+#define MDL1AO_CON5 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x14))
+#define MDL1AO_CON6 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x18))
+#define MDL1AO_CON7 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x1c))
+#define MDL1AO_CON8 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x20))
+#define MDL1AO_CON9 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x24))
+#define MDL1AO_CON10 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x28))
+#define MDL1AO_CON11 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x2c))
+#define MDL1AO_CON12 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x30))
+#define MDL1AO_CON14 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x38))
+#define MDL1AO_CON15 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x3C))
+#define MDL1AO_CON16 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x40))
+#define MDL1AO_CON17 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x44))
+#define MDL1AO_CON18 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x48))
+#define MDL1AO_CON19 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x4C))
+#if 0 /* defined in drvpdn.h */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define MDL1AO_CON212 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x350))
+
+
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_LSB (0)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_WIDTH (1)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_MASK (0x00000001)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_LSB (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_MASK (0x00000002)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_BIT (0x00000002)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_LSB (0)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_MASK (0x00000001)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_BIT (0x00000001)
+
+#define MDL1AO_CON2_BUS2X_DCM_CON_LSB (0)
+#define MDL1AO_CON2_BUS2X_DCM_CON_WIDTH (32)
+#define MDL1AO_CON2_BUS2X_DCM_CON_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_LSB (0)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_WIDTH (8)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_MASK (0x000000FF)
+
+#define MDL1AO_CON5_GLBCON_DBG_SEL_LSB (0)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_WIDTH (2)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_MASK (0x00000003)
+
+#define MDL1AO_CON6_BUS_PWR_AWARE_LSB (0)
+#define MDL1AO_CON6_BUS_PWR_AWARE_WIDTH (32)
+#define MDL1AO_CON6_BUS_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON7_MBIST_OUT_SEL_LSB (0)
+#define MDL1AO_CON7_MBIST_OUT_SEL_WIDTH (4)
+#define MDL1AO_CON7_MBIST_OUT_SEL_MASK (0x0000000F)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_LSB (3)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_MASK (0x00000008)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_BIT (0x00000008)
+
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_LSB (2)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_MASK (0x00000004)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_BIT (0x00000004)
+
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_LSB (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_MASK (0x00000002)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_BIT (0x00000002)
+
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_LSB (0)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_MASK (0x00000001)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_LSB (0)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_WIDTH (1)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_MASK (0x00000001)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_BIT (0x00000001)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_LSB (2)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_MASK (0x00000004)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_BIT (0x00000004)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_LSB (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_MASK (0x00000002)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_BIT (0x00000002)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_LSB (0)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_MASK (0x00000001)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_BIT (0x00000001)
+
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_LSB (0)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_WIDTH (5)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_MASK (0x0000001F)
+
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_LSB (0)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_WIDTH (5)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_MASK (0x0000001F)
+
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_LSB (0)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_WIDTH (5)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_MASK (0x0000001F)
+
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_LSB (0)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_WIDTH (5)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_MASK (0x0000001F)
+
+#define MDL1AO_CON18_RG_DBG_SUB_EN_LSB (0)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_WIDTH (4)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_MASK (0x0000000F)
+
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_LSB (0)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_WIDTH (6)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_MASK (0x0000003F)
+
+#define MDL1AO_CON20_PDN_CDO_TTR_LSB (18)
+#define MDL1AO_CON20_PDN_CDO_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_CDO_TTR_MASK (0x00040000)
+#define MDL1AO_CON20_PDN_CDO_TTR_BIT (0x00040000)
+
+#define MDL1AO_CON20_PDN_C1X_TTR_LSB (17)
+#define MDL1AO_CON20_PDN_C1X_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C1X_TTR_MASK (0x00020000)
+#define MDL1AO_CON20_PDN_C1X_TTR_BIT (0x00020000)
+
+#define MDL1AO_CON20_PDN_FREQM_LSB (16)
+#define MDL1AO_CON20_PDN_FREQM_WIDTH (1)
+#define MDL1AO_CON20_PDN_FREQM_MASK (0x00010000)
+#define MDL1AO_CON20_PDN_FREQM_BIT (0x00010000)
+
+#define MDL1AO_CON20_PDN_DVFS_CTRL_LSB (15)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_MASK (0x00008000)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_BIT (0x00008000)
+
+#define MDL1AO_CON20_PDN_IDC_UART_LSB (14)
+#define MDL1AO_CON20_PDN_IDC_UART_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_UART_MASK (0x00004000)
+#define MDL1AO_CON20_PDN_IDC_UART_BIT (0x00004000)
+
+#define MDL1AO_CON20_PDN_BSI_LSB (13)
+#define MDL1AO_CON20_PDN_BSI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BSI_MASK (0x00002000)
+#define MDL1AO_CON20_PDN_BSI_BIT (0x00002000)
+
+#define MDL1AO_CON20_PDN_BPI_LSB (12)
+#define MDL1AO_CON20_PDN_BPI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BPI_MASK (0x00001000)
+#define MDL1AO_CON20_PDN_BPI_BIT (0x00001000)
+
+#define MDL1AO_CON20_PDN_IDC_CTRL_LSB (11)
+#define MDL1AO_CON20_PDN_IDC_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_CTRL_MASK (0x00000800)
+#define MDL1AO_CON20_PDN_IDC_CTRL_BIT (0x00000800)
+
+#define MDL1AO_CON20_PDN_LTE_SLP_LSB (10)
+#define MDL1AO_CON20_PDN_LTE_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_SLP_MASK (0x00000400)
+#define MDL1AO_CON20_PDN_LTE_SLP_BIT (0x00000400)
+
+#define MDL1AO_CON20_PDN_LTE_TMR_LSB (9)
+#define MDL1AO_CON20_PDN_LTE_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_TMR_MASK (0x00000200)
+#define MDL1AO_CON20_PDN_LTE_TMR_BIT (0x00000200)
+
+#define MDL1AO_CON20_PDN_FDD_SLP_LSB (8)
+#define MDL1AO_CON20_PDN_FDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_SLP_MASK (0x00000100)
+#define MDL1AO_CON20_PDN_FDD_SLP_BIT (0x00000100)
+
+#define MDL1AO_CON20_PDN_FDD_TMR_LSB (7)
+#define MDL1AO_CON20_PDN_FDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_TMR_MASK (0x00000080)
+#define MDL1AO_CON20_PDN_FDD_TMR_BIT (0x00000080)
+
+#define MDL1AO_CON20_PDN_TDD_SLP_LSB (6)
+#define MDL1AO_CON20_PDN_TDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_SLP_MASK (0x00000040)
+#define MDL1AO_CON20_PDN_TDD_SLP_BIT (0x00000040)
+
+#define MDL1AO_CON20_PDN_TDD_TMR_LSB (5)
+#define MDL1AO_CON20_PDN_TDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_TMR_MASK (0x00000020)
+#define MDL1AO_CON20_PDN_TDD_TMR_BIT (0x00000020)
+
+#define MDL1AO_CON20_PDN_TDMA_SLP_LSB (4)
+#define MDL1AO_CON20_PDN_TDMA_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDMA_SLP_MASK (0x00000010)
+#define MDL1AO_CON20_PDN_TDMA_SLP_BIT (0x00000010)
+
+#define MDL1AO_CON20_PDN_C2K1X_SLP_LSB (3)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_MASK (0x00000008)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_BIT (0x00000008)
+
+#define MDL1AO_CON20_PDN_C2K1X_TMR_LSB (2)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_MASK (0x00000004)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_BIT (0x00000004)
+
+#define MDL1AO_CON20_PDN_C2KDO_SLP_LSB (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_MASK (0x00000002)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_BIT (0x00000002)
+
+#define MDL1AO_CON20_PDN_C2KDO_TMR_LSB (0)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_MASK (0x00000001)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_BIT (0x00000001)
+
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_LSB (20)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_MASK (0x00100000)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_BIT (0x00100000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_LSB (21)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_MASK (0x00200000)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_BIT (0x00200000)
+
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_LSB (18)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_MASK (0x00040000)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_BIT (0x00040000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_LSB (17)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_MASK (0x00020000)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_BIT (0x00020000)
+
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_LSB (16)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_MASK (0x00010000)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_BIT (0x00010000)
+
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_LSB (15)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_MASK (0x00008000)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_BIT (0x00008000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_LSB (14)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_MASK (0x00004000)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_BIT (0x00004000)
+
+#define MDL1AO_PDN_SET_PDN_BSI_SET_LSB (13)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_MASK (0x00002000)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_BIT (0x00002000)
+
+#define MDL1AO_PDN_SET_PDN_BPI_SET_LSB (12)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_MASK (0x00001000)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_BIT (0x00001000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_LSB (11)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_MASK (0x00000800)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_BIT (0x00000800)
+
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_LSB (10)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_MASK (0x00000400)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_BIT (0x00000400)
+
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_LSB (9)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_MASK (0x00000200)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_BIT (0x00000200)
+
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_LSB (8)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_MASK (0x00000100)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_BIT (0x00000100)
+
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_LSB (7)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_MASK (0x00000080)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_BIT (0x00000080)
+
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_LSB (6)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_MASK (0x00000040)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_BIT (0x00000040)
+
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_LSB (5)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_MASK (0x00000020)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_BIT (0x00000020)
+
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_LSB (4)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_MASK (0x00000010)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_BIT (0x00000010)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_LSB (3)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_MASK (0x00000008)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_BIT (0x00000008)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_LSB (2)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_MASK (0x00000004)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_BIT (0x00000004)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_LSB (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_MASK (0x00000002)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_BIT (0x00000002)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_LSB (0)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_MASK (0x00000001)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_BIT (0x00000001)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_LSB (20)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_MASK (0x00100000)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_BIT (0x00100000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_LSB (21)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_MASK (0x00200000)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_BIT (0x00200000)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_LSB (18)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_MASK (0x00040000)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_BIT (0x00040000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_LSB (17)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_MASK (0x00020000)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_BIT (0x00020000)
+
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_LSB (16)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_MASK (0x00010000)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_BIT (0x00010000)
+
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_LSB (15)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_MASK (0x00008000)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_BIT (0x00008000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_LSB (14)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_MASK (0x00004000)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_BIT (0x00004000)
+
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_LSB (13)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_MASK (0x00002000)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_BIT (0x00002000)
+
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_LSB (12)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_MASK (0x00001000)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_BIT (0x00001000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_LSB (11)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_MASK (0x00000800)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_BIT (0x00000800)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_LSB (10)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_MASK (0x00000400)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_BIT (0x00000400)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_LSB (9)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_MASK (0x00000200)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_BIT (0x00000200)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_LSB (8)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_MASK (0x00000100)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_BIT (0x00000100)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_LSB (7)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_MASK (0x00000080)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_BIT (0x00000080)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_LSB (6)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_MASK (0x00000040)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_BIT (0x00000040)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_LSB (5)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_MASK (0x00000020)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_BIT (0x00000020)
+
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_LSB (4)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_MASK (0x00000010)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_BIT (0x00000010)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_LSB (3)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_MASK (0x00000008)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_BIT (0x00000008)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_LSB (2)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_MASK (0x00000004)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_BIT (0x00000004)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_LSB (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_MASK (0x00000002)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_BIT (0x00000002)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_LSB (0)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_MASK (0x00000001)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_BIT (0x00000001)
+
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_LSB (9)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_MASK (0x00000200)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_BIT (0x00000200)
+
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_LSB (8)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_MASK (0x00000100)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_BIT (0x00000100)
+
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_LSB (7)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_MASK (0x00000080)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_BIT (0x00000080)
+
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_LSB (6)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_MASK (0x00000040)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_BIT (0x00000040)
+
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_LSB (5)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_MASK (0x00000020)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_BIT (0x00000020)
+
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_LSB (4)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_MASK (0x00000010)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_BIT (0x00000010)
+
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_LSB (3)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_MASK (0x00000008)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_BIT (0x00000008)
+
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_LSB (2)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_MASK (0x00000004)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_BIT (0x00000004)
+
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_LSB (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_MASK (0x00000002)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_BIT (0x00000002)
+
+#define MDL1AO_CON212_EFUSE_VALID_LSB (0)
+#define MDL1AO_CON212_EFUSE_VALID_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_VALID_MASK (0x00000001)
+#define MDL1AO_CON212_EFUSE_VALID_BIT (0x00000001)
+#endif //#ifndef _CPH_C2K_L1_A0CFG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_95.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_95.h
new file mode 100644
index 0000000..267f31e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_95.h
@@ -0,0 +1,563 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_L1_A0CFG_H_
+#define _CPH_C2K_L1_A0CFG_H_
+#include "drvpdn.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MODEML1_AO_CONFIG_REG_BASE (0xA6020000)
+
+#define MODEML1_AO_CONFIG_end (MODEML1_AO_CONFIG_REG_BASE + 0x350 + 1*4)
+
+
+
+#define MDL1AO_CON0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x00))
+#define MDL1AO_CON1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x04))
+#define MDL1AO_CON2 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x08))
+#define MDL1AO_CON4 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x10))
+#define MDL1AO_CON5 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x14))
+#define MDL1AO_CON6 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x18))
+#define MDL1AO_CON7 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x1c))
+#define MDL1AO_CON8 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x20))
+#define MDL1AO_CON9 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x24))
+#define MDL1AO_CON10 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x28))
+#define MDL1AO_CON11 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x2c))
+#define MDL1AO_CON12 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x30))
+#define MDL1AO_CON14 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x38))
+#define MDL1AO_CON15 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x3C))
+#define MDL1AO_CON16 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x40))
+#define MDL1AO_CON17 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x44))
+#define MDL1AO_CON18 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x48))
+#define MDL1AO_CON19 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x4C))
+#if 0 /* defined in drvpdn.h */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define MDL1AO_CON212 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x350))
+
+
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_LSB (0)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_WIDTH (1)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_MASK (0x00000001)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_LSB (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_MASK (0x00000002)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_BIT (0x00000002)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_LSB (0)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_MASK (0x00000001)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_BIT (0x00000001)
+
+#define MDL1AO_CON2_BUS2X_DCM_CON_LSB (0)
+#define MDL1AO_CON2_BUS2X_DCM_CON_WIDTH (32)
+#define MDL1AO_CON2_BUS2X_DCM_CON_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_LSB (0)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_WIDTH (8)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_MASK (0x000000FF)
+
+#define MDL1AO_CON5_GLBCON_DBG_SEL_LSB (0)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_WIDTH (2)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_MASK (0x00000003)
+
+#define MDL1AO_CON6_BUS_PWR_AWARE_LSB (0)
+#define MDL1AO_CON6_BUS_PWR_AWARE_WIDTH (32)
+#define MDL1AO_CON6_BUS_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON7_MBIST_OUT_SEL_LSB (0)
+#define MDL1AO_CON7_MBIST_OUT_SEL_WIDTH (4)
+#define MDL1AO_CON7_MBIST_OUT_SEL_MASK (0x0000000F)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_LSB (3)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_MASK (0x00000008)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_BIT (0x00000008)
+
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_LSB (2)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_MASK (0x00000004)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_BIT (0x00000004)
+
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_LSB (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_MASK (0x00000002)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_BIT (0x00000002)
+
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_LSB (0)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_MASK (0x00000001)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_LSB (0)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_WIDTH (1)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_MASK (0x00000001)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_BIT (0x00000001)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_LSB (2)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_MASK (0x00000004)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_BIT (0x00000004)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_LSB (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_MASK (0x00000002)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_BIT (0x00000002)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_LSB (0)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_MASK (0x00000001)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_BIT (0x00000001)
+
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_LSB (0)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_WIDTH (5)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_MASK (0x0000001F)
+
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_LSB (0)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_WIDTH (5)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_MASK (0x0000001F)
+
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_LSB (0)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_WIDTH (5)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_MASK (0x0000001F)
+
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_LSB (0)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_WIDTH (5)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_MASK (0x0000001F)
+
+#define MDL1AO_CON18_RG_DBG_SUB_EN_LSB (0)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_WIDTH (4)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_MASK (0x0000000F)
+
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_LSB (0)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_WIDTH (6)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_MASK (0x0000003F)
+
+#define MDL1AO_CON20_PDN_CDO_TTR_LSB (18)
+#define MDL1AO_CON20_PDN_CDO_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_CDO_TTR_MASK (0x00040000)
+#define MDL1AO_CON20_PDN_CDO_TTR_BIT (0x00040000)
+
+#define MDL1AO_CON20_PDN_C1X_TTR_LSB (17)
+#define MDL1AO_CON20_PDN_C1X_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C1X_TTR_MASK (0x00020000)
+#define MDL1AO_CON20_PDN_C1X_TTR_BIT (0x00020000)
+
+#define MDL1AO_CON20_PDN_FREQM_LSB (16)
+#define MDL1AO_CON20_PDN_FREQM_WIDTH (1)
+#define MDL1AO_CON20_PDN_FREQM_MASK (0x00010000)
+#define MDL1AO_CON20_PDN_FREQM_BIT (0x00010000)
+
+#define MDL1AO_CON20_PDN_DVFS_CTRL_LSB (15)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_MASK (0x00008000)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_BIT (0x00008000)
+
+#define MDL1AO_CON20_PDN_IDC_UART_LSB (14)
+#define MDL1AO_CON20_PDN_IDC_UART_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_UART_MASK (0x00004000)
+#define MDL1AO_CON20_PDN_IDC_UART_BIT (0x00004000)
+
+#define MDL1AO_CON20_PDN_BSI_LSB (13)
+#define MDL1AO_CON20_PDN_BSI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BSI_MASK (0x00002000)
+#define MDL1AO_CON20_PDN_BSI_BIT (0x00002000)
+
+#define MDL1AO_CON20_PDN_BPI_LSB (12)
+#define MDL1AO_CON20_PDN_BPI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BPI_MASK (0x00001000)
+#define MDL1AO_CON20_PDN_BPI_BIT (0x00001000)
+
+#define MDL1AO_CON20_PDN_IDC_CTRL_LSB (11)
+#define MDL1AO_CON20_PDN_IDC_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_CTRL_MASK (0x00000800)
+#define MDL1AO_CON20_PDN_IDC_CTRL_BIT (0x00000800)
+
+#define MDL1AO_CON20_PDN_LTE_SLP_LSB (10)
+#define MDL1AO_CON20_PDN_LTE_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_SLP_MASK (0x00000400)
+#define MDL1AO_CON20_PDN_LTE_SLP_BIT (0x00000400)
+
+#define MDL1AO_CON20_PDN_LTE_TMR_LSB (9)
+#define MDL1AO_CON20_PDN_LTE_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_TMR_MASK (0x00000200)
+#define MDL1AO_CON20_PDN_LTE_TMR_BIT (0x00000200)
+
+#define MDL1AO_CON20_PDN_FDD_SLP_LSB (8)
+#define MDL1AO_CON20_PDN_FDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_SLP_MASK (0x00000100)
+#define MDL1AO_CON20_PDN_FDD_SLP_BIT (0x00000100)
+
+#define MDL1AO_CON20_PDN_FDD_TMR_LSB (7)
+#define MDL1AO_CON20_PDN_FDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_TMR_MASK (0x00000080)
+#define MDL1AO_CON20_PDN_FDD_TMR_BIT (0x00000080)
+
+#define MDL1AO_CON20_PDN_TDD_SLP_LSB (6)
+#define MDL1AO_CON20_PDN_TDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_SLP_MASK (0x00000040)
+#define MDL1AO_CON20_PDN_TDD_SLP_BIT (0x00000040)
+
+#define MDL1AO_CON20_PDN_TDD_TMR_LSB (5)
+#define MDL1AO_CON20_PDN_TDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_TMR_MASK (0x00000020)
+#define MDL1AO_CON20_PDN_TDD_TMR_BIT (0x00000020)
+
+#define MDL1AO_CON20_PDN_TDMA_SLP_LSB (4)
+#define MDL1AO_CON20_PDN_TDMA_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDMA_SLP_MASK (0x00000010)
+#define MDL1AO_CON20_PDN_TDMA_SLP_BIT (0x00000010)
+
+#define MDL1AO_CON20_PDN_C2K1X_SLP_LSB (3)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_MASK (0x00000008)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_BIT (0x00000008)
+
+#define MDL1AO_CON20_PDN_C2K1X_TMR_LSB (2)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_MASK (0x00000004)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_BIT (0x00000004)
+
+#define MDL1AO_CON20_PDN_C2KDO_SLP_LSB (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_MASK (0x00000002)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_BIT (0x00000002)
+
+#define MDL1AO_CON20_PDN_C2KDO_TMR_LSB (0)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_MASK (0x00000001)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_BIT (0x00000001)
+
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_LSB (20)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_MASK (0x00100000)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_BIT (0x00100000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_LSB (21)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_MASK (0x00200000)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_BIT (0x00200000)
+
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_LSB (18)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_MASK (0x00040000)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_BIT (0x00040000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_LSB (17)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_MASK (0x00020000)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_BIT (0x00020000)
+
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_LSB (16)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_MASK (0x00010000)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_BIT (0x00010000)
+
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_LSB (15)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_MASK (0x00008000)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_BIT (0x00008000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_LSB (14)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_MASK (0x00004000)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_BIT (0x00004000)
+
+#define MDL1AO_PDN_SET_PDN_BSI_SET_LSB (13)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_MASK (0x00002000)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_BIT (0x00002000)
+
+#define MDL1AO_PDN_SET_PDN_BPI_SET_LSB (12)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_MASK (0x00001000)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_BIT (0x00001000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_LSB (11)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_MASK (0x00000800)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_BIT (0x00000800)
+
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_LSB (10)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_MASK (0x00000400)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_BIT (0x00000400)
+
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_LSB (9)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_MASK (0x00000200)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_BIT (0x00000200)
+
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_LSB (8)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_MASK (0x00000100)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_BIT (0x00000100)
+
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_LSB (7)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_MASK (0x00000080)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_BIT (0x00000080)
+
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_LSB (6)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_MASK (0x00000040)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_BIT (0x00000040)
+
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_LSB (5)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_MASK (0x00000020)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_BIT (0x00000020)
+
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_LSB (4)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_MASK (0x00000010)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_BIT (0x00000010)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_LSB (3)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_MASK (0x00000008)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_BIT (0x00000008)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_LSB (2)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_MASK (0x00000004)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_BIT (0x00000004)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_LSB (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_MASK (0x00000002)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_BIT (0x00000002)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_LSB (0)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_MASK (0x00000001)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_BIT (0x00000001)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_LSB (20)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_MASK (0x00100000)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_BIT (0x00100000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_LSB (21)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_MASK (0x00200000)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_BIT (0x00200000)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_LSB (18)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_MASK (0x00040000)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_BIT (0x00040000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_LSB (17)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_MASK (0x00020000)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_BIT (0x00020000)
+
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_LSB (16)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_MASK (0x00010000)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_BIT (0x00010000)
+
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_LSB (15)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_MASK (0x00008000)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_BIT (0x00008000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_LSB (14)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_MASK (0x00004000)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_BIT (0x00004000)
+
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_LSB (13)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_MASK (0x00002000)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_BIT (0x00002000)
+
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_LSB (12)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_MASK (0x00001000)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_BIT (0x00001000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_LSB (11)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_MASK (0x00000800)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_BIT (0x00000800)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_LSB (10)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_MASK (0x00000400)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_BIT (0x00000400)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_LSB (9)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_MASK (0x00000200)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_BIT (0x00000200)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_LSB (8)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_MASK (0x00000100)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_BIT (0x00000100)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_LSB (7)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_MASK (0x00000080)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_BIT (0x00000080)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_LSB (6)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_MASK (0x00000040)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_BIT (0x00000040)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_LSB (5)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_MASK (0x00000020)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_BIT (0x00000020)
+
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_LSB (4)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_MASK (0x00000010)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_BIT (0x00000010)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_LSB (3)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_MASK (0x00000008)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_BIT (0x00000008)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_LSB (2)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_MASK (0x00000004)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_BIT (0x00000004)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_LSB (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_MASK (0x00000002)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_BIT (0x00000002)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_LSB (0)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_MASK (0x00000001)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_BIT (0x00000001)
+
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_LSB (9)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_MASK (0x00000200)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_BIT (0x00000200)
+
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_LSB (8)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_MASK (0x00000100)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_BIT (0x00000100)
+
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_LSB (7)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_MASK (0x00000080)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_BIT (0x00000080)
+
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_LSB (6)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_MASK (0x00000040)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_BIT (0x00000040)
+
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_LSB (5)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_MASK (0x00000020)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_BIT (0x00000020)
+
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_LSB (4)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_MASK (0x00000010)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_BIT (0x00000010)
+
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_LSB (3)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_MASK (0x00000008)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_BIT (0x00000008)
+
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_LSB (2)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_MASK (0x00000004)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_BIT (0x00000004)
+
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_LSB (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_MASK (0x00000002)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_BIT (0x00000002)
+
+#define MDL1AO_CON212_EFUSE_VALID_LSB (0)
+#define MDL1AO_CON212_EFUSE_VALID_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_VALID_MASK (0x00000001)
+#define MDL1AO_CON212_EFUSE_VALID_BIT (0x00000001)
+#endif //#ifndef _CPH_C2K_L1_A0CFG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_97.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_97.h
new file mode 100644
index 0000000..bccc5c1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_97.h
@@ -0,0 +1,577 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_L1_A0CFG_H_
+#define _CPH_C2K_L1_A0CFG_H_
+#include "drvpdn.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define MODEML1_AO_CONFIG_REG_BASE (0xA8020000)/*97*/
+#else
+#define MODEML1_AO_CONFIG_REG_BASE (0xA6020000)/*93 95*/
+#endif
+#define MODEML1_AO_CONFIG_end (MODEML1_AO_CONFIG_REG_BASE + 0x350 + 1*4)
+
+
+#define MDL1AO_CON0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x00))
+#define MDL1AO_CON1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x04))
+#define MDL1AO_CON2 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x08))
+#define MDL1AO_CON4 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x10))
+#define MDL1AO_CON5 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x14))
+#define MDL1AO_CON6 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x18))
+#define MDL1AO_CON7 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x1c))
+#define MDL1AO_CON8 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x20))
+#define MDL1AO_CON9 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x24))
+#define MDL1AO_CON10 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x28))
+#define MDL1AO_CON11 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x2c))
+#define MDL1AO_CON12 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x30))
+#define MDL1AO_CON14 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x38))
+#define MDL1AO_CON15 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x3C))
+#define MDL1AO_CON16 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x40))
+#define MDL1AO_CON17 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x44))
+#define MDL1AO_CON18 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x48))
+#define MDL1AO_CON19 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x4C))
+#if 0 /* defined in drvpdn.h */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define MDL1AO_CON212 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x350))
+#if defined(__MD97__) || defined(__MD97P__)
+#define MDL1AO_CON13 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x5c))
+#define MDL1AO_CON21 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x60))
+#define MDL1AO_CON22 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x64))
+#define MDL1AO_CON23 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x68))
+#define MDL1AO_CON24 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x6c))
+
+#define MDL1AO_DVFS_DBG_SEL ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x70))
+#define MDL1AO_DVFS_DBG_EN ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x74))
+#define MDL1AO_DIGRF_P2P_CON_0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x78))
+#define MDL1AO_DIGRF_P2P_CON_1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x7C))
+#define MDL1AO_BW_LMT_CON ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x80))
+#endif
+
+
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_LSB (0)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_WIDTH (1)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_MASK (0x00000001)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_LSB (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_MASK (0x00000002)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_BIT (0x00000002)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_LSB (0)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_MASK (0x00000001)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_BIT (0x00000001)
+
+#define MDL1AO_CON2_BUS2X_DCM_CON_LSB (0)
+#define MDL1AO_CON2_BUS2X_DCM_CON_WIDTH (32)
+#define MDL1AO_CON2_BUS2X_DCM_CON_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_LSB (0)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_WIDTH (8)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_MASK (0x000000FF)
+
+#define MDL1AO_CON5_GLBCON_DBG_SEL_LSB (0)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_WIDTH (2)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_MASK (0x00000003)
+
+#define MDL1AO_CON6_BUS_PWR_AWARE_LSB (0)
+#define MDL1AO_CON6_BUS_PWR_AWARE_WIDTH (32)
+#define MDL1AO_CON6_BUS_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON7_MBIST_OUT_SEL_LSB (0)
+#define MDL1AO_CON7_MBIST_OUT_SEL_WIDTH (4)
+#define MDL1AO_CON7_MBIST_OUT_SEL_MASK (0x0000000F)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_LSB (3)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_MASK (0x00000008)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_BIT (0x00000008)
+
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_LSB (2)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_MASK (0x00000004)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_BIT (0x00000004)
+
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_LSB (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_MASK (0x00000002)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_BIT (0x00000002)
+
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_LSB (0)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_MASK (0x00000001)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_LSB (0)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_WIDTH (1)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_MASK (0x00000001)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_BIT (0x00000001)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_LSB (2)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_MASK (0x00000004)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_BIT (0x00000004)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_LSB (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_MASK (0x00000002)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_BIT (0x00000002)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_LSB (0)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_MASK (0x00000001)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_BIT (0x00000001)
+
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_LSB (0)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_WIDTH (5)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_MASK (0x0000001F)
+
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_LSB (0)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_WIDTH (5)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_MASK (0x0000001F)
+
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_LSB (0)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_WIDTH (5)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_MASK (0x0000001F)
+
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_LSB (0)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_WIDTH (5)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_MASK (0x0000001F)
+
+#define MDL1AO_CON18_RG_DBG_SUB_EN_LSB (0)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_WIDTH (4)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_MASK (0x0000000F)
+
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_LSB (0)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_WIDTH (6)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_MASK (0x0000003F)
+
+#define MDL1AO_CON20_PDN_CDO_TTR_LSB (18)
+#define MDL1AO_CON20_PDN_CDO_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_CDO_TTR_MASK (0x00040000)
+#define MDL1AO_CON20_PDN_CDO_TTR_BIT (0x00040000)
+
+#define MDL1AO_CON20_PDN_C1X_TTR_LSB (17)
+#define MDL1AO_CON20_PDN_C1X_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C1X_TTR_MASK (0x00020000)
+#define MDL1AO_CON20_PDN_C1X_TTR_BIT (0x00020000)
+
+#define MDL1AO_CON20_PDN_FREQM_LSB (16)
+#define MDL1AO_CON20_PDN_FREQM_WIDTH (1)
+#define MDL1AO_CON20_PDN_FREQM_MASK (0x00010000)
+#define MDL1AO_CON20_PDN_FREQM_BIT (0x00010000)
+
+#define MDL1AO_CON20_PDN_DVFS_CTRL_LSB (15)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_MASK (0x00008000)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_BIT (0x00008000)
+
+#define MDL1AO_CON20_PDN_IDC_UART_LSB (14)
+#define MDL1AO_CON20_PDN_IDC_UART_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_UART_MASK (0x00004000)
+#define MDL1AO_CON20_PDN_IDC_UART_BIT (0x00004000)
+
+#define MDL1AO_CON20_PDN_BSI_LSB (13)
+#define MDL1AO_CON20_PDN_BSI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BSI_MASK (0x00002000)
+#define MDL1AO_CON20_PDN_BSI_BIT (0x00002000)
+
+#define MDL1AO_CON20_PDN_BPI_LSB (12)
+#define MDL1AO_CON20_PDN_BPI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BPI_MASK (0x00001000)
+#define MDL1AO_CON20_PDN_BPI_BIT (0x00001000)
+
+#define MDL1AO_CON20_PDN_IDC_CTRL_LSB (11)
+#define MDL1AO_CON20_PDN_IDC_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_CTRL_MASK (0x00000800)
+#define MDL1AO_CON20_PDN_IDC_CTRL_BIT (0x00000800)
+
+#define MDL1AO_CON20_PDN_LTE_SLP_LSB (10)
+#define MDL1AO_CON20_PDN_LTE_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_SLP_MASK (0x00000400)
+#define MDL1AO_CON20_PDN_LTE_SLP_BIT (0x00000400)
+
+#define MDL1AO_CON20_PDN_LTE_TMR_LSB (9)
+#define MDL1AO_CON20_PDN_LTE_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_TMR_MASK (0x00000200)
+#define MDL1AO_CON20_PDN_LTE_TMR_BIT (0x00000200)
+
+#define MDL1AO_CON20_PDN_FDD_SLP_LSB (8)
+#define MDL1AO_CON20_PDN_FDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_SLP_MASK (0x00000100)
+#define MDL1AO_CON20_PDN_FDD_SLP_BIT (0x00000100)
+
+#define MDL1AO_CON20_PDN_FDD_TMR_LSB (7)
+#define MDL1AO_CON20_PDN_FDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_TMR_MASK (0x00000080)
+#define MDL1AO_CON20_PDN_FDD_TMR_BIT (0x00000080)
+
+#define MDL1AO_CON20_PDN_TDD_SLP_LSB (6)
+#define MDL1AO_CON20_PDN_TDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_SLP_MASK (0x00000040)
+#define MDL1AO_CON20_PDN_TDD_SLP_BIT (0x00000040)
+
+#define MDL1AO_CON20_PDN_TDD_TMR_LSB (5)
+#define MDL1AO_CON20_PDN_TDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_TMR_MASK (0x00000020)
+#define MDL1AO_CON20_PDN_TDD_TMR_BIT (0x00000020)
+
+#define MDL1AO_CON20_PDN_TDMA_SLP_LSB (4)
+#define MDL1AO_CON20_PDN_TDMA_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDMA_SLP_MASK (0x00000010)
+#define MDL1AO_CON20_PDN_TDMA_SLP_BIT (0x00000010)
+
+#define MDL1AO_CON20_PDN_C2K1X_SLP_LSB (3)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_MASK (0x00000008)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_BIT (0x00000008)
+
+#define MDL1AO_CON20_PDN_C2K1X_TMR_LSB (2)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_MASK (0x00000004)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_BIT (0x00000004)
+
+#define MDL1AO_CON20_PDN_C2KDO_SLP_LSB (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_MASK (0x00000002)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_BIT (0x00000002)
+
+#define MDL1AO_CON20_PDN_C2KDO_TMR_LSB (0)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_MASK (0x00000001)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_BIT (0x00000001)
+
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_LSB (20)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_MASK (0x00100000)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_BIT (0x00100000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_LSB (21)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_MASK (0x00200000)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_BIT (0x00200000)
+
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_LSB (18)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_MASK (0x00040000)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_BIT (0x00040000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_LSB (17)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_MASK (0x00020000)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_BIT (0x00020000)
+
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_LSB (16)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_MASK (0x00010000)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_BIT (0x00010000)
+
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_LSB (15)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_MASK (0x00008000)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_BIT (0x00008000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_LSB (14)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_MASK (0x00004000)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_BIT (0x00004000)
+
+#define MDL1AO_PDN_SET_PDN_BSI_SET_LSB (13)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_MASK (0x00002000)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_BIT (0x00002000)
+
+#define MDL1AO_PDN_SET_PDN_BPI_SET_LSB (12)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_MASK (0x00001000)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_BIT (0x00001000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_LSB (11)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_MASK (0x00000800)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_BIT (0x00000800)
+
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_LSB (10)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_MASK (0x00000400)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_BIT (0x00000400)
+
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_LSB (9)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_MASK (0x00000200)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_BIT (0x00000200)
+
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_LSB (8)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_MASK (0x00000100)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_BIT (0x00000100)
+
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_LSB (7)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_MASK (0x00000080)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_BIT (0x00000080)
+
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_LSB (6)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_MASK (0x00000040)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_BIT (0x00000040)
+
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_LSB (5)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_MASK (0x00000020)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_BIT (0x00000020)
+
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_LSB (4)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_MASK (0x00000010)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_BIT (0x00000010)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_LSB (3)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_MASK (0x00000008)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_BIT (0x00000008)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_LSB (2)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_MASK (0x00000004)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_BIT (0x00000004)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_LSB (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_MASK (0x00000002)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_BIT (0x00000002)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_LSB (0)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_MASK (0x00000001)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_BIT (0x00000001)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_LSB (20)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_MASK (0x00100000)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_BIT (0x00100000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_LSB (21)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_MASK (0x00200000)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_BIT (0x00200000)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_LSB (18)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_MASK (0x00040000)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_BIT (0x00040000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_LSB (17)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_MASK (0x00020000)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_BIT (0x00020000)
+
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_LSB (16)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_MASK (0x00010000)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_BIT (0x00010000)
+
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_LSB (15)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_MASK (0x00008000)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_BIT (0x00008000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_LSB (14)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_MASK (0x00004000)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_BIT (0x00004000)
+
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_LSB (13)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_MASK (0x00002000)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_BIT (0x00002000)
+
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_LSB (12)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_MASK (0x00001000)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_BIT (0x00001000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_LSB (11)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_MASK (0x00000800)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_BIT (0x00000800)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_LSB (10)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_MASK (0x00000400)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_BIT (0x00000400)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_LSB (9)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_MASK (0x00000200)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_BIT (0x00000200)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_LSB (8)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_MASK (0x00000100)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_BIT (0x00000100)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_LSB (7)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_MASK (0x00000080)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_BIT (0x00000080)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_LSB (6)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_MASK (0x00000040)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_BIT (0x00000040)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_LSB (5)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_MASK (0x00000020)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_BIT (0x00000020)
+
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_LSB (4)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_MASK (0x00000010)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_BIT (0x00000010)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_LSB (3)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_MASK (0x00000008)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_BIT (0x00000008)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_LSB (2)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_MASK (0x00000004)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_BIT (0x00000004)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_LSB (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_MASK (0x00000002)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_BIT (0x00000002)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_LSB (0)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_MASK (0x00000001)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_BIT (0x00000001)
+
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_LSB (9)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_MASK (0x00000200)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_BIT (0x00000200)
+
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_LSB (8)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_MASK (0x00000100)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_BIT (0x00000100)
+
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_LSB (7)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_MASK (0x00000080)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_BIT (0x00000080)
+
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_LSB (6)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_MASK (0x00000040)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_BIT (0x00000040)
+
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_LSB (5)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_MASK (0x00000020)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_BIT (0x00000020)
+
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_LSB (4)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_MASK (0x00000010)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_BIT (0x00000010)
+
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_LSB (3)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_MASK (0x00000008)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_BIT (0x00000008)
+
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_LSB (2)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_MASK (0x00000004)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_BIT (0x00000004)
+
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_LSB (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_MASK (0x00000002)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_BIT (0x00000002)
+
+#define MDL1AO_CON212_EFUSE_VALID_LSB (0)
+#define MDL1AO_CON212_EFUSE_VALID_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_VALID_MASK (0x00000001)
+#define MDL1AO_CON212_EFUSE_VALID_BIT (0x00000001)
+#endif //#ifndef _CPH_C2K_L1_A0CFG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit.h
new file mode 100644
index 0000000..8b951e2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphc2krxbrpdvit_93.h"
+#elif defined(__MD95__)
+#include "cphc2krxbrpdvit_93.h"
+#elif defined(__MD97__)
+#include "cphc2krxbrpdvit_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_93.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_93.h
new file mode 100644
index 0000000..cafe5a5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_93.h
@@ -0,0 +1,1862 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_DVIT_H_
+#define _CPH_C2K_RX_BRP_DVIT_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DVIT_REG_BASE (0xAD070000)
+
+#define RXBRP_WCT_DVIT_end (RXBRP_WCT_DVIT_REG_BASE + 0x4038 + 1*4)
+
+
+
+#define DBRP_VITW_WT_CTRL ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0000))
+#define DBRP_VITW_WT_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0004))
+#define DBRP_VITW_WT_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0008))
+#define DBRP_VITW_WT_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x000c))
+#define DBRP_VITW_WT_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0010))
+#define DBRP_VITW_WT_CHEN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0018))
+#define DBRP_VITW_WT_BCH_DMACFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0100))
+#define DBRP_VITW_WT_BCH_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0104))
+#define DBRP_VITW_WT_BCH_SFN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0108))
+#define DBRP_VITW_WT_BCH_SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x010c))
+#define DBRP_VITW_WT_BCH_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0110))
+#define DBRP_VITW_WT_BCH_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0114))
+#define DBRP_VITW_WT_TRCH0_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1000))
+#define DBRP_VITW_WT_TRCH0_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1004))
+#define DBRP_VITW_WT_TRCH0_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1008))
+#define DBRP_VITW_WT_TRCH0_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x100c))
+#define DBRP_VITW_WT_TRCH0_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1010))
+#define DBRP_VITW_WT_TRCH0_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1014))
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1018))
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x101c))
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1020))
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1024))
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1028))
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x102C))
+#define DBRP_VITW_WT_TRCH0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1030))
+#define DBRP_VITW_WT_TRCH0_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1034))
+#define DBRP_VITW_WT_TRCH1_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1100))
+#define DBRP_VITW_WT_TRCH1_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1104))
+#define DBRP_VITW_WT_TRCH1_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1108))
+#define DBRP_VITW_WT_TRCH1_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x110c))
+#define DBRP_VITW_WT_TRCH1_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1110))
+#define DBRP_VITW_WT_TRCH1_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1114))
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1118))
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x111c))
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1120))
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1124))
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1128))
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x112C))
+#define DBRP_VITW_WT_TRCH1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1130))
+#define DBRP_VITW_WT_TRCH1_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1134))
+#define DBRP_VITW_WT_TRCH2_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1200))
+#define DBRP_VITW_WT_TRCH2_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1204))
+#define DBRP_VITW_WT_TRCH2_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1208))
+#define DBRP_VITW_WT_TRCH2_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x120c))
+#define DBRP_VITW_WT_TRCH2_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1210))
+#define DBRP_VITW_WT_TRCH2_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1214))
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1218))
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x121c))
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1220))
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1224))
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1228))
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x122C))
+#define DBRP_VITW_WT_TRCH2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1230))
+#define DBRP_VITW_WT_TRCH2_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1234))
+#define DBRP_VITW_WT_TRCH3_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1300))
+#define DBRP_VITW_WT_TRCH3_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1304))
+#define DBRP_VITW_WT_TRCH3_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1308))
+#define DBRP_VITW_WT_TRCH3_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x130c))
+#define DBRP_VITW_WT_TRCH3_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1310))
+#define DBRP_VITW_WT_TRCH3_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1314))
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1318))
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x131c))
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1320))
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1324))
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1328))
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x132C))
+#define DBRP_VITW_WT_TRCH3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1330))
+#define DBRP_VITW_WT_TRCH3_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1334))
+#define DBRP_VITW_WT_TRCH4_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1400))
+#define DBRP_VITW_WT_TRCH4_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1404))
+#define DBRP_VITW_WT_TRCH4_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1408))
+#define DBRP_VITW_WT_TRCH4_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x140c))
+#define DBRP_VITW_WT_TRCH4_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1410))
+#define DBRP_VITW_WT_TRCH4_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1414))
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1418))
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x141c))
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1420))
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1424))
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1428))
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x142C))
+#define DBRP_VITW_WT_TRCH4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1430))
+#define DBRP_VITW_WT_TRCH4_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1434))
+#define DBRP_VITW_WT_TRCH5_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1500))
+#define DBRP_VITW_WT_TRCH5_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1504))
+#define DBRP_VITW_WT_TRCH5_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1508))
+#define DBRP_VITW_WT_TRCH5_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x150c))
+#define DBRP_VITW_WT_TRCH5_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1510))
+#define DBRP_VITW_WT_TRCH5_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1514))
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1518))
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x151c))
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1520))
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1524))
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1528))
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x152C))
+#define DBRP_VITW_WT_TRCH5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1530))
+#define DBRP_VITW_WT_TRCH5_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1534))
+#define DBRP_VITW_WT_TRCH6_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1600))
+#define DBRP_VITW_WT_TRCH6_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1604))
+#define DBRP_VITW_WT_TRCH6_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1608))
+#define DBRP_VITW_WT_TRCH6_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x160c))
+#define DBRP_VITW_WT_TRCH6_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1610))
+#define DBRP_VITW_WT_TRCH6_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1614))
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1618))
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x161c))
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1620))
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1624))
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1628))
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x162C))
+#define DBRP_VITW_WT_TRCH6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1630))
+#define DBRP_VITW_WT_TRCH6_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1634))
+#define DBRP_VITW_WT_TRCH7_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1700))
+#define DBRP_VITW_WT_TRCH7_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1704))
+#define DBRP_VITW_WT_TRCH7_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1708))
+#define DBRP_VITW_WT_TRCH7_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x170c))
+#define DBRP_VITW_WT_TRCH7_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1710))
+#define DBRP_VITW_WT_TRCH7_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1714))
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1718))
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x171c))
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1720))
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1724))
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1728))
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x172C))
+#define DBRP_VITW_WT_TRCH7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1730))
+#define DBRP_VITW_WT_TRCH7_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1734))
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2000))
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2004))
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2008))
+#define DBRP_VITW_WT_BTFD1_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2010))
+#define DBRP_VITW_WT_BTFD1_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2014))
+#define DBRP_VITW_WT_BTFD2_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2020))
+#define DBRP_VITW_WT_BTFD2_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2024))
+#define DBRP_VITW_WT_BTFD3_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2030))
+#define DBRP_VITW_WT_BTFD3_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2034))
+#define DBRP_VITW_WT_BTFD_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2080))
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2100))
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2104))
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2108))
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2200))
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2204))
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2208))
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2300))
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2304))
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2308))
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2400))
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2404))
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2408))
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2500))
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2504))
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2508))
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2600))
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2604))
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2608))
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2700))
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2704))
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2708))
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2800))
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2804))
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2808))
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2900))
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2904))
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2908))
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A00))
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A04))
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A08))
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B00))
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B04))
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B08))
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C00))
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C04))
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C08))
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D00))
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D04))
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D08))
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E00))
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E04))
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E08))
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F00))
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F04))
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F08))
+#define DBRP_VITW_C_RESET ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3000))
+#define DBRP_VITW_C_LVA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3004))
+#define DBRP_VITW_C_PCH_CONF ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3008))
+#define DBRP_VITW_C_FIRST_FRM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x300C))
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3010))
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3014))
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3018))
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x301C))
+#define DBRP_VITW_C_SCH_DMA_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3020))
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3024))
+#define DBRP_VITW_C_SCH_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3028))
+#define DBRP_VITW_C_FCH_FULL_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x302C))
+#define DBRP_VITW_C_FCH_HALF_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3030))
+#define DBRP_VITW_C_FCH_QUAT_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3034))
+#define DBRP_VITW_C_FCH_EIGH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3038))
+#define DBRP_VITW_C_SCH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x303C))
+#define DBRP_VITW_C_FCH_FULL_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3040))
+#define DBRP_VITW_C_FCH_HALF_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3044))
+#define DBRP_VITW_C_FCH_QUAT_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3048))
+#define DBRP_VITW_C_FCH_EIGH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x304C))
+#define DBRP_VITW_C_SCH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3050))
+#define DBRP_VITW_C_FCH_FULL_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3054))
+#define DBRP_VITW_C_FCH_HALF_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3058))
+#define DBRP_VITW_C_FCH_QUAT_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x305C))
+#define DBRP_VITW_C_FCH_EIGH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3060))
+#define DBRP_VITW_C_SCH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3064))
+#define DBRP_VITW_C_FCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3068))
+#define DBRP_VITW_C_SCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x306C))
+#define DBRP_VITW_C_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3070))
+#define DBRP_VITW_C_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3074))
+#define DBRP_VITW_C_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3078))
+#define DBRP_VITW_C_FCH_FULL_USAGE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x307C))
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3080))
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3084))
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3088))
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x308C))
+#define DBRP_VITW_C_SCH_DMA_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3090))
+#define DBRP_VITW_MPU ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4000))
+#define DBRP_VITW_MPU_VIO ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4004))
+#define DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4008))
+#define DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x400C))
+#define DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4010))
+#define DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4014))
+#define DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4018))
+#define DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x401C))
+#define DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4020))
+#define DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4024))
+#define DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4028))
+#define DBRP_VITW_DBG0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x402C))
+#define DBRP_VITW_DBG1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4030))
+#define DBRP_VITW_DBG2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4034))
+#define DBRP_VITW_DBG3 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4038))
+
+
+#define DBRP_VITW_WT_CTRL_SW_RESET_LSB (4)
+#define DBRP_VITW_WT_CTRL_SW_RESET_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_SW_RESET_MASK (0x00000010)
+#define DBRP_VITW_WT_CTRL_SW_RESET_BIT (0x00000010)
+
+#define DBRP_VITW_WT_CTRL_Mode_LSB (0)
+#define DBRP_VITW_WT_CTRL_Mode_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_Mode_MASK (0x00000001)
+#define DBRP_VITW_WT_CTRL_Mode_BIT (0x00000001)
+
+#define DBRP_VITW_WT_START_ACC_START_LSB (15)
+#define DBRP_VITW_WT_START_ACC_START_WIDTH (1)
+#define DBRP_VITW_WT_START_ACC_START_MASK (0x00008000)
+#define DBRP_VITW_WT_START_ACC_START_BIT (0x00008000)
+
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_LSB (8)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_MASK (0x00000100)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_BIT (0x00000100)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_LSB (7)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_MASK (0x00000080)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_BIT (0x00000080)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_LSB (6)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_MASK (0x00000040)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_BIT (0x00000040)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_LSB (5)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_MASK (0x00000020)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_BIT (0x00000020)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_LSB (4)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_MASK (0x00000010)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_BIT (0x00000010)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_LSB (3)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_LSB (2)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_LSB (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_LSB (0)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_LSB (15)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_MASK (0x00008000)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_BIT (0x00008000)
+
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_LSB (8)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_MASK (0x00000100)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_BIT (0x00000100)
+
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_LSB (0)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_WIDTH (8)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_MASK (0x000000FF)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_LSB (8)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_MASK (0x00000100)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_BIT (0x00000100)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_LSB (14)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_WIDTH (1)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_MASK (0x00004000)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_BIT (0x00004000)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_LSB (0)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_WIDTH (11)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_MASK (0x000007FF)
+
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_LSB (0)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_WIDTH (21)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_LSB (0)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_MASK (0x00000001)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_BIT (0x00000001)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_C_RESET_SW_RESET_LSB (0)
+#define DBRP_VITW_C_RESET_SW_RESET_WIDTH (1)
+#define DBRP_VITW_C_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_VITW_C_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_VITW_C_LVA_LVA_EN_LSB (0)
+#define DBRP_VITW_C_LVA_LVA_EN_WIDTH (1)
+#define DBRP_VITW_C_LVA_LVA_EN_MASK (0x00000001)
+#define DBRP_VITW_C_LVA_LVA_EN_BIT (0x00000001)
+
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_LSB (0)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_WIDTH (1)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_MASK (0x00000001)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FIRST_FRM_START_LSB (0)
+#define DBRP_VITW_C_FIRST_FRM_START_WIDTH (1)
+#define DBRP_VITW_C_FIRST_FRM_START_MASK (0x00000001)
+#define DBRP_VITW_C_FIRST_FRM_START_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_SCH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_SCH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_SCH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_SCH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_LSB (3)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_MASK (0x00000008)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_BIT (0x00000008)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_LSB (2)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_MASK (0x00000004)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_BIT (0x00000004)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_LSB (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_MASK (0x00000002)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_BIT (0x00000002)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_LSB (3)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_LSB (2)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_LSB (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_LSB (0)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_WIDTH (2)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_MASK (0x00000003)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU_VIOLATE_LSB (0)
+#define DBRP_VITW_MPU_VIOLATE_WIDTH (1)
+#define DBRP_VITW_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_VITW_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_VITW_MPU_VIO_ADR_LSB (0)
+#define DBRP_VITW_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_VITW_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_EN_LSB (0)
+#define DBRP_VITW_MPU0_EN_WIDTH (1)
+#define DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_EN_LSB (0)
+#define DBRP_VITW_MPU1_EN_WIDTH (1)
+#define DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_EN_LSB (0)
+#define DBRP_VITW_MPU2_EN_WIDTH (1)
+#define DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_DBG0_VITW_BCH_CS_LSB (25)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_WIDTH (4)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_MASK (0x1E000000)
+
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_LSB (17)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_WIDTH (8)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_MASK (0x01FE0000)
+
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_LSB (10)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_WIDTH (7)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_MASK (0x0001FC00)
+
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_LSB (0)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_WIDTH (10)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_MASK (0x000003FF)
+
+#define DBRP_VITW_DBG1_VITW_SCH_CS_LSB (7)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_WIDTH (5)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_MASK (0x00000F80)
+
+#define DBRP_VITW_DBG1_VITW_FCH_CS_LSB (0)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_WIDTH (7)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_MASK (0x0000007F)
+
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_LSB (28)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_WIDTH (4)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_MASK (0xF0000000)
+
+#define DBRP_VITW_DBG2_VINFO_CS_LSB (16)
+#define DBRP_VITW_DBG2_VINFO_CS_WIDTH (11)
+#define DBRP_VITW_DBG2_VINFO_CS_MASK (0x07FF0000)
+
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_LSB (12)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_MASK (0x00007000)
+
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_LSB (9)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_MASK (0x00000E00)
+
+#define DBRP_VITW_DBG2_VDEC_CS_LSB (4)
+#define DBRP_VITW_DBG2_VDEC_CS_WIDTH (5)
+#define DBRP_VITW_DBG2_VDEC_CS_MASK (0x000001F0)
+
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_LSB (0)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_WIDTH (4)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_MASK (0x0000000F)
+
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_LSB (15)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_WIDTH (7)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_MASK (0x003F8000)
+
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_LSB (0)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_WIDTH (15)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_DVIT_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_97.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_97.h
new file mode 100644
index 0000000..d8179bc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_97.h
@@ -0,0 +1,1872 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_DVIT_H_
+#define _CPH_C2K_RX_BRP_DVIT_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DVIT_REG_BASE (0xAC870000)
+
+#define RXBRP_WCT_DVIT_end (RXBRP_WCT_DVIT_REG_BASE + 0x4038 + 1*4)
+
+
+
+#define DBRP_VITW_WT_CTRL ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0000))
+#define DBRP_VITW_WT_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0004))
+#define DBRP_VITW_WT_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0008))
+#define DBRP_VITW_WT_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x000c))
+#define DBRP_VITW_WT_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0010))
+#define DBRP_VITW_WT_CHEN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0018))
+#define DBRP_VITW_WT_BCH_DMACFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0100))
+#define DBRP_VITW_WT_BCH_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0104))
+#define DBRP_VITW_WT_BCH_SFN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0108))
+#define DBRP_VITW_WT_BCH_SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x010c))
+#define DBRP_VITW_WT_BCH_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0110))
+#define DBRP_VITW_WT_BCH_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0114))
+#define DBRP_VITW_WT_TRCH0_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1000))
+#define DBRP_VITW_WT_TRCH0_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1004))
+#define DBRP_VITW_WT_TRCH0_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1008))
+#define DBRP_VITW_WT_TRCH0_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x100c))
+#define DBRP_VITW_WT_TRCH0_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1010))
+#define DBRP_VITW_WT_TRCH0_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1014))
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1018))
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x101c))
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1020))
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1024))
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1028))
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x102C))
+#define DBRP_VITW_WT_TRCH0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1030))
+#define DBRP_VITW_WT_TRCH0_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1034))
+#define DBRP_VITW_WT_TRCH1_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1100))
+#define DBRP_VITW_WT_TRCH1_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1104))
+#define DBRP_VITW_WT_TRCH1_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1108))
+#define DBRP_VITW_WT_TRCH1_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x110c))
+#define DBRP_VITW_WT_TRCH1_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1110))
+#define DBRP_VITW_WT_TRCH1_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1114))
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1118))
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x111c))
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1120))
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1124))
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1128))
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x112C))
+#define DBRP_VITW_WT_TRCH1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1130))
+#define DBRP_VITW_WT_TRCH1_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1134))
+#define DBRP_VITW_WT_TRCH2_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1200))
+#define DBRP_VITW_WT_TRCH2_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1204))
+#define DBRP_VITW_WT_TRCH2_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1208))
+#define DBRP_VITW_WT_TRCH2_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x120c))
+#define DBRP_VITW_WT_TRCH2_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1210))
+#define DBRP_VITW_WT_TRCH2_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1214))
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1218))
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x121c))
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1220))
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1224))
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1228))
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x122C))
+#define DBRP_VITW_WT_TRCH2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1230))
+#define DBRP_VITW_WT_TRCH2_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1234))
+#define DBRP_VITW_WT_TRCH3_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1300))
+#define DBRP_VITW_WT_TRCH3_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1304))
+#define DBRP_VITW_WT_TRCH3_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1308))
+#define DBRP_VITW_WT_TRCH3_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x130c))
+#define DBRP_VITW_WT_TRCH3_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1310))
+#define DBRP_VITW_WT_TRCH3_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1314))
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1318))
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x131c))
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1320))
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1324))
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1328))
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x132C))
+#define DBRP_VITW_WT_TRCH3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1330))
+#define DBRP_VITW_WT_TRCH3_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1334))
+#define DBRP_VITW_WT_TRCH4_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1400))
+#define DBRP_VITW_WT_TRCH4_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1404))
+#define DBRP_VITW_WT_TRCH4_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1408))
+#define DBRP_VITW_WT_TRCH4_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x140c))
+#define DBRP_VITW_WT_TRCH4_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1410))
+#define DBRP_VITW_WT_TRCH4_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1414))
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1418))
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x141c))
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1420))
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1424))
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1428))
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x142C))
+#define DBRP_VITW_WT_TRCH4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1430))
+#define DBRP_VITW_WT_TRCH4_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1434))
+#define DBRP_VITW_WT_TRCH5_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1500))
+#define DBRP_VITW_WT_TRCH5_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1504))
+#define DBRP_VITW_WT_TRCH5_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1508))
+#define DBRP_VITW_WT_TRCH5_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x150c))
+#define DBRP_VITW_WT_TRCH5_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1510))
+#define DBRP_VITW_WT_TRCH5_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1514))
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1518))
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x151c))
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1520))
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1524))
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1528))
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x152C))
+#define DBRP_VITW_WT_TRCH5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1530))
+#define DBRP_VITW_WT_TRCH5_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1534))
+#define DBRP_VITW_WT_TRCH6_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1600))
+#define DBRP_VITW_WT_TRCH6_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1604))
+#define DBRP_VITW_WT_TRCH6_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1608))
+#define DBRP_VITW_WT_TRCH6_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x160c))
+#define DBRP_VITW_WT_TRCH6_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1610))
+#define DBRP_VITW_WT_TRCH6_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1614))
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1618))
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x161c))
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1620))
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1624))
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1628))
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x162C))
+#define DBRP_VITW_WT_TRCH6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1630))
+#define DBRP_VITW_WT_TRCH6_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1634))
+#define DBRP_VITW_WT_TRCH7_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1700))
+#define DBRP_VITW_WT_TRCH7_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1704))
+#define DBRP_VITW_WT_TRCH7_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1708))
+#define DBRP_VITW_WT_TRCH7_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x170c))
+#define DBRP_VITW_WT_TRCH7_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1710))
+#define DBRP_VITW_WT_TRCH7_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1714))
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1718))
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x171c))
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1720))
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1724))
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1728))
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x172C))
+#define DBRP_VITW_WT_TRCH7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1730))
+#define DBRP_VITW_WT_TRCH7_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1734))
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2000))
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2004))
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2008))
+#define DBRP_VITW_WT_BTFD1_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2010))
+#define DBRP_VITW_WT_BTFD1_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2014))
+#define DBRP_VITW_WT_BTFD2_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2020))
+#define DBRP_VITW_WT_BTFD2_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2024))
+#define DBRP_VITW_WT_BTFD3_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2030))
+#define DBRP_VITW_WT_BTFD3_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2034))
+#define DBRP_VITW_WT_BTFD_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2080))
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2100))
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2104))
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2108))
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2200))
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2204))
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2208))
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2300))
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2304))
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2308))
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2400))
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2404))
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2408))
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2500))
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2504))
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2508))
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2600))
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2604))
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2608))
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2700))
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2704))
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2708))
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2800))
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2804))
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2808))
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2900))
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2904))
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2908))
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A00))
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A04))
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A08))
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B00))
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B04))
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B08))
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C00))
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C04))
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C08))
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D00))
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D04))
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D08))
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E00))
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E04))
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E08))
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F00))
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F04))
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F08))
+#define DBRP_VITW_C_RESET ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3000))
+#define DBRP_VITW_C_LVA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3004))
+#define DBRP_VITW_C_PCH_CONF ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3008))
+#define DBRP_VITW_C_FIRST_FRM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x300C))
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3010))
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3014))
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3018))
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x301C))
+#define DBRP_VITW_C_SCH_DMA_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3020))
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3024))
+#define DBRP_VITW_C_SCH_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3028))
+#define DBRP_VITW_C_FCH_FULL_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x302C))
+#define DBRP_VITW_C_FCH_HALF_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3030))
+#define DBRP_VITW_C_FCH_QUAT_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3034))
+#define DBRP_VITW_C_FCH_EIGH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3038))
+#define DBRP_VITW_C_SCH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x303C))
+#define DBRP_VITW_C_FCH_FULL_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3040))
+#define DBRP_VITW_C_FCH_HALF_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3044))
+#define DBRP_VITW_C_FCH_QUAT_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3048))
+#define DBRP_VITW_C_FCH_EIGH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x304C))
+#define DBRP_VITW_C_SCH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3050))
+#define DBRP_VITW_C_FCH_FULL_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3054))
+#define DBRP_VITW_C_FCH_HALF_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3058))
+#define DBRP_VITW_C_FCH_QUAT_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x305C))
+#define DBRP_VITW_C_FCH_EIGH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3060))
+#define DBRP_VITW_C_SCH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3064))
+#define DBRP_VITW_C_FCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3068))
+#define DBRP_VITW_C_SCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x306C))
+#define DBRP_VITW_C_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3070))
+#define DBRP_VITW_C_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3074))
+#define DBRP_VITW_C_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3078))
+#define DBRP_VITW_C_FCH_FULL_USAGE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x307C))
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3080))
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3084))
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3088))
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x308C))
+#define DBRP_VITW_C_SCH_DMA_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3090))
+#define DBRP_VITW_MPU ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4000))
+#define DBRP_VITW_MPU_VIO ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4004))
+#define DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4008))
+#define DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x400C))
+#define DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4010))
+#define DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4014))
+#define DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4018))
+#define DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x401C))
+#define DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4020))
+#define DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4024))
+#define DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4028))
+#define DBRP_VITW_DBG0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x402C))
+#define DBRP_VITW_DBG1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4030))
+#define DBRP_VITW_DBG2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4034))
+#define DBRP_VITW_DBG3 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4038))
+
+
+
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_LSB (16)
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_MASK (0x00010000)
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_BIT (0x00010000)
+
+#define DBRP_VITW_WT_CTRL_PWR_MODE_LSB (5)
+#define DBRP_VITW_WT_CTRL_PWR_MODE_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_PWR_MODE_MASK (0x00000020)
+#define DBRP_VITW_WT_CTRL_PWR_MODE_BIT (0x00000020)
+#define DBRP_VITW_WT_CTRL_SW_RESET_LSB (4)
+#define DBRP_VITW_WT_CTRL_SW_RESET_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_SW_RESET_MASK (0x00000010)
+#define DBRP_VITW_WT_CTRL_SW_RESET_BIT (0x00000010)
+
+#define DBRP_VITW_WT_CTRL_Mode_LSB (0)
+#define DBRP_VITW_WT_CTRL_Mode_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_Mode_MASK (0x00000001)
+#define DBRP_VITW_WT_CTRL_Mode_BIT (0x00000001)
+
+#define DBRP_VITW_WT_START_ACC_START_LSB (15)
+#define DBRP_VITW_WT_START_ACC_START_WIDTH (1)
+#define DBRP_VITW_WT_START_ACC_START_MASK (0x00008000)
+#define DBRP_VITW_WT_START_ACC_START_BIT (0x00008000)
+
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_LSB (8)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_MASK (0x00000100)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_BIT (0x00000100)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_LSB (7)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_MASK (0x00000080)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_BIT (0x00000080)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_LSB (6)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_MASK (0x00000040)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_BIT (0x00000040)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_LSB (5)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_MASK (0x00000020)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_BIT (0x00000020)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_LSB (4)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_MASK (0x00000010)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_BIT (0x00000010)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_LSB (3)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_LSB (2)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_LSB (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_LSB (0)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_LSB (15)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_MASK (0x00008000)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_BIT (0x00008000)
+
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_LSB (8)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_MASK (0x00000100)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_BIT (0x00000100)
+
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_LSB (0)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_WIDTH (8)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_MASK (0x000000FF)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_LSB (8)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_MASK (0x00000100)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_BIT (0x00000100)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_LSB (14)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_WIDTH (1)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_MASK (0x00004000)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_BIT (0x00004000)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_LSB (0)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_WIDTH (11)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_MASK (0x000007FF)
+
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_LSB (0)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_WIDTH (21)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_LSB (0)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_MASK (0x00000001)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_BIT (0x00000001)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_C_RESET_SW_RESET_LSB (0)
+#define DBRP_VITW_C_RESET_SW_RESET_WIDTH (1)
+#define DBRP_VITW_C_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_VITW_C_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_VITW_C_LVA_LVA_EN_LSB (0)
+#define DBRP_VITW_C_LVA_LVA_EN_WIDTH (1)
+#define DBRP_VITW_C_LVA_LVA_EN_MASK (0x00000001)
+#define DBRP_VITW_C_LVA_LVA_EN_BIT (0x00000001)
+
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_LSB (0)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_WIDTH (1)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_MASK (0x00000001)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FIRST_FRM_START_LSB (0)
+#define DBRP_VITW_C_FIRST_FRM_START_WIDTH (1)
+#define DBRP_VITW_C_FIRST_FRM_START_MASK (0x00000001)
+#define DBRP_VITW_C_FIRST_FRM_START_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_SCH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_SCH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_SCH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_SCH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_LSB (3)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_MASK (0x00000008)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_BIT (0x00000008)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_LSB (2)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_MASK (0x00000004)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_BIT (0x00000004)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_LSB (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_MASK (0x00000002)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_BIT (0x00000002)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_LSB (3)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_LSB (2)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_LSB (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_LSB (0)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_WIDTH (2)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_MASK (0x00000003)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU_VIOLATE_LSB (0)
+#define DBRP_VITW_MPU_VIOLATE_WIDTH (1)
+#define DBRP_VITW_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_VITW_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_VITW_MPU_VIO_ADR_LSB (0)
+#define DBRP_VITW_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_VITW_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_EN_LSB (0)
+#define DBRP_VITW_MPU0_EN_WIDTH (1)
+#define DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_EN_LSB (0)
+#define DBRP_VITW_MPU1_EN_WIDTH (1)
+#define DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_EN_LSB (0)
+#define DBRP_VITW_MPU2_EN_WIDTH (1)
+#define DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_DBG0_VITW_BCH_CS_LSB (25)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_WIDTH (4)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_MASK (0x1E000000)
+
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_LSB (17)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_WIDTH (8)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_MASK (0x01FE0000)
+
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_LSB (10)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_WIDTH (7)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_MASK (0x0001FC00)
+
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_LSB (0)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_WIDTH (10)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_MASK (0x000003FF)
+
+#define DBRP_VITW_DBG1_VITW_SCH_CS_LSB (7)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_WIDTH (5)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_MASK (0x00000F80)
+
+#define DBRP_VITW_DBG1_VITW_FCH_CS_LSB (0)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_WIDTH (7)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_MASK (0x0000007F)
+
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_LSB (28)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_WIDTH (4)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_MASK (0xF0000000)
+
+#define DBRP_VITW_DBG2_VINFO_CS_LSB (16)
+#define DBRP_VITW_DBG2_VINFO_CS_WIDTH (11)
+#define DBRP_VITW_DBG2_VINFO_CS_MASK (0x07FF0000)
+
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_LSB (12)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_MASK (0x00007000)
+
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_LSB (9)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_MASK (0x00000E00)
+
+#define DBRP_VITW_DBG2_VDEC_CS_LSB (4)
+#define DBRP_VITW_DBG2_VDEC_CS_WIDTH (5)
+#define DBRP_VITW_DBG2_VDEC_CS_MASK (0x000001F0)
+
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_LSB (0)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_WIDTH (4)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_MASK (0x0000000F)
+
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_LSB (15)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_WIDTH (7)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_MASK (0x003F8000)
+
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_LSB (0)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_WIDTH (15)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_DVIT_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur.h
new file mode 100644
index 0000000..76a6c4e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphc2krxbrptur_93.h"
+#elif defined(__MD95__)
+#include "cphc2krxbrptur_93.h"
+#elif defined(__MD97__)
+#include "cphc2krxbrptur_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_93.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_93.h
new file mode 100644
index 0000000..7bb2a54
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_93.h
@@ -0,0 +1,2509 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_TUR_H_
+#define _CPH_C2K_RX_BRP_TUR_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCTL_TUR_REG_BASE (0xad120000)
+
+#define RXBRP_WCTL_TUR_end (RXBRP_WCTL_TUR_REG_BASE + 0xD0A0 + 1*4)
+
+
+
+#define DBRP_TUR_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0000))
+#define DBRP_TUR_DSCRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0004))
+#define DBRP_TUR_C_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0008))
+#define DBRP_TUR_DSCH_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2000))
+#define DBRP_TUR_DSCH_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2004))
+#define DBRP_TUR_DSCH_EN ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2008))
+#define DBRP_TUR_DSCH_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x200C))
+#define DBRP_TUR_DSCH_CBBUF ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2010))
+#define DBRP_TUR_DSCH_CH0_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2014))
+#define DBRP_TUR_DSCH_CH0_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2018))
+#define DBRP_TUR_DSCH_CH0_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x201C))
+#define DBRP_TUR_DSCH_CH0_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2020))
+#define DBRP_TUR_DSCH_CH0_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2024))
+#define DBRP_TUR_DSCH_CH0_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2028))
+#define DBRP_TUR_DSCH_CH0_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x202C))
+#define DBRP_TUR_DSCH_CH0_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2030))
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2034))
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2038))
+#define DBRP_TUR_DSCH_CH1_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x203C))
+#define DBRP_TUR_DSCH_CH1_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2040))
+#define DBRP_TUR_DSCH_CH1_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2044))
+#define DBRP_TUR_DSCH_CH1_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2048))
+#define DBRP_TUR_DSCH_CH1_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x204C))
+#define DBRP_TUR_DSCH_CH1_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2050))
+#define DBRP_TUR_DSCH_CH1_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2054))
+#define DBRP_TUR_DSCH_CH1_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2058))
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x205C))
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2060))
+#define DBRP_TUR_DSCH_CH2_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2064))
+#define DBRP_TUR_DSCH_CH2_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2068))
+#define DBRP_TUR_DSCH_CH2_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x206C))
+#define DBRP_TUR_DSCH_CH2_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2070))
+#define DBRP_TUR_DSCH_CH2_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2074))
+#define DBRP_TUR_DSCH_CH2_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2078))
+#define DBRP_TUR_DSCH_CH2_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x207C))
+#define DBRP_TUR_DSCH_CH2_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2080))
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2084))
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2088))
+#define DBRP_TUR_DSCH_CH3_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x208C))
+#define DBRP_TUR_DSCH_CH3_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2090))
+#define DBRP_TUR_DSCH_CH3_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2094))
+#define DBRP_TUR_DSCH_CH3_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2098))
+#define DBRP_TUR_DSCH_CH3_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x209C))
+#define DBRP_TUR_DSCH_CH3_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A0))
+#define DBRP_TUR_DSCH_CH3_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A4))
+#define DBRP_TUR_DSCH_CH3_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A8))
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20AC))
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B0))
+#define DBRP_TUR_DSCH_CH4_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B4))
+#define DBRP_TUR_DSCH_CH4_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B8))
+#define DBRP_TUR_DSCH_CH4_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20BC))
+#define DBRP_TUR_DSCH_CH4_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C0))
+#define DBRP_TUR_DSCH_CH4_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C4))
+#define DBRP_TUR_DSCH_CH4_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C8))
+#define DBRP_TUR_DSCH_CH4_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20CC))
+#define DBRP_TUR_DSCH_CH4_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D0))
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D4))
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D8))
+#define DBRP_TUR_DSCH_CH0_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20DC))
+#define DBRP_TUR_DSCH_CH0_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E0))
+#define DBRP_TUR_DSCH_CH0_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E4))
+#define DBRP_TUR_DSCH_CH0_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E8))
+#define DBRP_TUR_DSCH_CH0_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20EC))
+#define DBRP_TUR_DSCH_CH0_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F0))
+#define DBRP_TUR_DSCH_CH0_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F4))
+#define DBRP_TUR_DSCH_CH0_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F8))
+#define DBRP_TUR_DSCH_CH1_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20FC))
+#define DBRP_TUR_DSCH_CH1_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2100))
+#define DBRP_TUR_DSCH_CH1_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2104))
+#define DBRP_TUR_DSCH_CH1_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2108))
+#define DBRP_TUR_DSCH_CH1_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x210C))
+#define DBRP_TUR_DSCH_CH1_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2110))
+#define DBRP_TUR_DSCH_CH1_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2114))
+#define DBRP_TUR_DSCH_CH1_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2118))
+#define DBRP_TUR_DSCH_CH2_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x211C))
+#define DBRP_TUR_DSCH_CH2_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2120))
+#define DBRP_TUR_DSCH_CH2_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2124))
+#define DBRP_TUR_DSCH_CH2_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2128))
+#define DBRP_TUR_DSCH_CH2_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x212C))
+#define DBRP_TUR_DSCH_CH2_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2130))
+#define DBRP_TUR_DSCH_CH2_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2134))
+#define DBRP_TUR_DSCH_CH3_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2138))
+#define DBRP_TUR_DSCH_CH3_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x213C))
+#define DBRP_TUR_DSCH_CH3_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2140))
+#define DBRP_TUR_DSCH_CH3_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2144))
+#define DBRP_TUR_DSCH_CH3_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2148))
+#define DBRP_TUR_DSCH_CH3_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x214C))
+#define DBRP_TUR_DSCH_CH3_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2150))
+#define DBRP_TUR_DSCH_CH4_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2154))
+#define DBRP_TUR_DSCH_CH4_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2158))
+#define DBRP_TUR_DSCH_CH4_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x215C))
+#define DBRP_TUR_DSCH_CH4_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2160))
+#define DBRP_TUR_DSCH_CH4_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2164))
+#define DBRP_TUR_DSCH_CH4_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2168))
+#define DBRP_TUR_DSCH_CH4_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x216C))
+#define DBRP_TUR_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2170))
+#define DBRP_TUR_LTE_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3000))
+#define DBRP_TUR_LTE_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3004))
+#define DBRP_TUR_LTE_LATCH ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3008))
+#define DBRP_TUR_LTE_FRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x300C))
+#define DBRP_TUR_LTE_SI_PI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3010))
+#define DBRP_TUR_LTE_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3014))
+#define DBRP_TUR_LTE_CH0_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3018))
+#define DBRP_TUR_LTE_CH0_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x301C))
+#define DBRP_TUR_LTE_CH0_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3020))
+#define DBRP_TUR_LTE_CH0_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3024))
+#define DBRP_TUR_LTE_CH0_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3028))
+#define DBRP_TUR_LTE_CH0_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x302C))
+#define DBRP_TUR_LTE_CH1_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3030))
+#define DBRP_TUR_LTE_CH1_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3034))
+#define DBRP_TUR_LTE_CH1_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3038))
+#define DBRP_TUR_LTE_CH1_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x303C))
+#define DBRP_TUR_LTE_CH1_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3040))
+#define DBRP_TUR_LTE_CH1_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3044))
+#define DBRP_TUR_LTE_CH2_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3048))
+#define DBRP_TUR_LTE_CH2_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x304C))
+#define DBRP_TUR_LTE_CH2_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3050))
+#define DBRP_TUR_LTE_CH2_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3054))
+#define DBRP_TUR_LTE_CH2_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3058))
+#define DBRP_TUR_LTE_CH2_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x305C))
+#define DBRP_TUR_LTE_CH3_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3060))
+#define DBRP_TUR_LTE_CH3_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3064))
+#define DBRP_TUR_LTE_CH3_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3068))
+#define DBRP_TUR_LTE_CH3_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x306C))
+#define DBRP_TUR_LTE_CH3_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3070))
+#define DBRP_TUR_LTE_CH3_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3074))
+#define DBRP_TUR_LTE_CH4_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3078))
+#define DBRP_TUR_LTE_CH4_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x307C))
+#define DBRP_TUR_LTE_CH4_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3080))
+#define DBRP_TUR_LTE_CH4_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3084))
+#define DBRP_TUR_LTE_CH4_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3088))
+#define DBRP_TUR_LTE_CH4_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x308C))
+#define DBRP_TUR_LTE_CC0_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3090))
+#define DBRP_TUR_LTE_CC0_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3094))
+#define DBRP_TUR_LTE_CC0_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3098))
+#define DBRP_TUR_LTE_CC0_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x309C))
+#define DBRP_TUR_LTE_CC0_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A0))
+#define DBRP_TUR_LTE_CC0_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A4))
+#define DBRP_TUR_LTE_CC0_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A8))
+#define DBRP_TUR_LTE_CC0_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30AC))
+#define DBRP_TUR_LTE_CC0_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B0))
+#define DBRP_TUR_LTE_CC0_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B4))
+#define DBRP_TUR_LTE_CC1_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B8))
+#define DBRP_TUR_LTE_CC1_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30BC))
+#define DBRP_TUR_LTE_CC1_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C0))
+#define DBRP_TUR_LTE_CC1_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C4))
+#define DBRP_TUR_LTE_CC1_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C8))
+#define DBRP_TUR_LTE_CC1_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30CC))
+#define DBRP_TUR_LTE_CC1_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D0))
+#define DBRP_TUR_LTE_CC1_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D4))
+#define DBRP_TUR_LTE_CC1_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D8))
+#define DBRP_TUR_LTE_CC1_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30DC))
+#define DBRP_TUR_LTE_CC2_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E0))
+#define DBRP_TUR_LTE_CC2_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E4))
+#define DBRP_TUR_LTE_CC2_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E8))
+#define DBRP_TUR_LTE_CC2_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30EC))
+#define DBRP_TUR_LTE_CC2_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F0))
+#define DBRP_TUR_LTE_CC2_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F4))
+#define DBRP_TUR_LTE_CC2_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F8))
+#define DBRP_TUR_LTE_CC2_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30FC))
+#define DBRP_TUR_LTE_CC2_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3100))
+#define DBRP_TUR_LTE_CC2_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3104))
+#define DBRP_TUR_LTE_DONE_CC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3108))
+#define DBRP_TUR_LTE_CMD0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x310C))
+#define DBRP_TUR_LTE_CMD1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3110))
+#define DBRP_TUR_LTE_CC0_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3114))
+#define DBRP_TUR_LTE_CC0_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3118))
+#define DBRP_TUR_LTE_CC1_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x311C))
+#define DBRP_TUR_LTE_CC1_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3120))
+#define DBRP_TUR_LTE_CC2_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3124))
+#define DBRP_TUR_LTE_CC2_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3128))
+#define DBRP_TUR_LTE_DONE_ASSERT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x312C))
+#define DBRP_TUR_LTE_FW_RST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3FFC))
+#define DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x400C))
+#define DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4010))
+#define DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4014))
+#define DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4018))
+#define DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x401C))
+#define DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4020))
+#define DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4024))
+#define DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4028))
+#define DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x402C))
+#define DBRP_TUR_MPU_VIO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4030))
+#define DBRP_TUR_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4034))
+#define DBRP_TUR_LTE_MPIF_DATA_CNT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5000))
+#define DBRP_TUR_LTE_MPIF_DBG_0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5004))
+#define DBRP_TUR_LTE_MPIF_DBG_1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5008))
+#define DBRP_TUR_LTE_MPIF_DBG_2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x500C))
+#define DBRP_TUR_LTE_MPIF_DBG_3 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5010))
+#define DBRP_TUR_LTE_MPIF_DBG_4 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5014))
+#define DBRP_TUR_LTE_MPIF_DBG_5 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5018))
+#define DBRP_TUR_LTE_MPIF_DBG_6 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x501C))
+#define DBRP_TUR_LTE_MPIF_DBG_7 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5020))
+#define DBRP_TUR_LTE_MPIF_DBG_8 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5024))
+#define DBRP_TUR_LTE_MPIF_DBG_9 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5028))
+#define DBRP_TUR_LTE_MPIF_DBG_10 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x502C))
+#define DBRP_TUR_LTE_MPIF_DBG_11 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5030))
+#define DBRP_TUR_LTE_MPIF_DBG_12 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5034))
+#define DBRP_TUR_LTE_MPIF_DBG_13 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5038))
+#define DBRP_TUR_LTE_MPIF_DBG_14 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x503C))
+#define DBRP_TUR_LTE_MPIF_DBG_15 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5040))
+#define DBRP_TUR_LTE_MPIF_DBG_16 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5044))
+#define DBRP_TUR_LTE_MPIF_DBG_17 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5048))
+#define DBRP_TUR_LTE_MPIF_DBG_18 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x504C))
+#define DBRP_TUR_LTE_MPIF_DBG_19 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5050))
+#define DBRP_TUR_LTE_MPIF_DBG_20 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5054))
+#define DBRP_TUR_LTE_MPIF_DBG_21 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5058))
+#define DBRP_TUR_LTE_MPIF_DBG_22 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x505C))
+#define DBRP_TUR_LTE_MPIF_DBG_23 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5060))
+#define DBRP_TUR_LTE_MPIF_DBG_24 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5064))
+#define DBRP_TUR_LTE_MPIF_DBG_25 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5068))
+#define DBRP_TUR_LTE_MPIF_DBG_26 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x506C))
+#define DBRP_TUR_LTE_MPIF_DBG_27 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5070))
+#define DBRP_TUR_LTE_MPIF_DBG_28 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5074))
+#define DBRP_TUR_LTE_MPIF_DBG_29 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5078))
+#define DBRP_TUR_LTE_MPIF_DBG_30 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x507C))
+#define DBRP_TUR_LTE_MPIF_DBG_31 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5080))
+#define DBRP_TUR_LTE_MPIF_WRITE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5084))
+#define DBRP_TUR_L_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5088))
+#define DBRP_TUR_WT_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x508C))
+#define DBRP_TUR_DEC_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5090))
+#define DBRP_TUR_DOB_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5094))
+#define DBRP_TUR_C_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5098))
+#define DBRP_TUR_MODE_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x509C))
+#define DBRP_TUR_RTT_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6000))
+#define DBRP_TUR_RTT_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6004))
+#define DBRP_TUR_RTT_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6008))
+#define DBRP_TUR_RTT_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x600C))
+#define DBRP_TUR_RTT_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6010))
+#define DBRP_TUR_RTT_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6014))
+#define DBRP_TUR_RTT_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6018))
+#define DBRP_TUR_EVDO_ITER_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7000))
+#define DBRP_TUR_EVDO_DST_PING ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7004))
+#define DBRP_TUR_EVDO_DST_PONG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7008))
+#define DBRP_TUR_EVDO_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x700C))
+#define DBRP_TUR_EVDO_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7010))
+#define DBRP_TUR_EVDO_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7014))
+#define DBRP_TUR_EVDO_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7018))
+#define DBRP_TUR_EVDO_HARQ ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x701C))
+#define DBRP_TUR_EVDO_PACKET ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7020))
+#define DBRP_TUR_EVDO_DST_ADR ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7024))
+#define DBRP_TUR_EVDO_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7028))
+#define DBRP_TUR_C2K_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x702C))
+#define DBRP_TUR_CB_NUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD000))
+#define DBRP_TUR_CH0_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD018))
+#define DBRP_TUR_CH0_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD028))
+#define DBRP_TUR_CH0_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD030))
+#define DBRP_TUR_CH1_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD034))
+#define DBRP_TUR_CH1_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD044))
+#define DBRP_TUR_CH1_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD04C))
+#define DBRP_TUR_CH2_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD050))
+#define DBRP_TUR_CH2_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD060))
+#define DBRP_TUR_CH2_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD068))
+#define DBRP_TUR_CH3_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD06C))
+#define DBRP_TUR_CH3_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD07C))
+#define DBRP_TUR_CH3_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD084))
+#define DBRP_TUR_CH4_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD088))
+#define DBRP_TUR_CH4_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD098))
+#define DBRP_TUR_CH4_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD0A0))
+
+
+#define DBRP_TUR_CFG_CR_TH_OFST_LSB (0)
+#define DBRP_TUR_CFG_CR_TH_OFST_WIDTH (13)
+#define DBRP_TUR_CFG_CR_TH_OFST_MASK (0x00001FFF)
+
+#define DBRP_TUR_DSCRM_BYPASS_LSB (0)
+#define DBRP_TUR_DSCRM_BYPASS_WIDTH (1)
+#define DBRP_TUR_DSCRM_BYPASS_MASK (0x00000001)
+#define DBRP_TUR_DSCRM_BYPASS_BIT (0x00000001)
+
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_LSB (4)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_MASK (0x00000010)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_BIT (0x00000010)
+
+#define DBRP_TUR_C_DBG_EMI_EN_LSB (0)
+#define DBRP_TUR_C_DBG_EMI_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_C_DBG_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_TRG_START_LSB (0)
+#define DBRP_TUR_DSCH_TRG_START_WIDTH (1)
+#define DBRP_TUR_DSCH_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_DSCH_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_LSB (9)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_MASK (0x00000200)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_BIT (0x00000200)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_LSB (8)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_MASK (0x00000100)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_LSB (6)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_MASK (0x00000040)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_LSB (4)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_MASK (0x00000010)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_LSB (3)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_MASK (0x00000008)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_LSB (2)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_MASK (0x00000004)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_LSB (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_MASK (0x00000002)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_LSB (0)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_MASK (0x00000001)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_LSB (6)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_MASK (0x00000040)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_EN_CHi_LSB (0)
+#define DBRP_TUR_DSCH_EN_CHi_WIDTH (5)
+#define DBRP_TUR_DSCH_EN_CHi_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_LSB (0)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_WIDTH (5)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_LSB (0)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_WIDTH (12)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_MASK (0x00000FFF)
+
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_BUSY_DSCH_LSB (1)
+#define DBRP_TUR_BUSY_DSCH_WIDTH (1)
+#define DBRP_TUR_BUSY_DSCH_MASK (0x00000002)
+#define DBRP_TUR_BUSY_DSCH_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_TRG_START_LSB (0)
+#define DBRP_TUR_LTE_TRG_START_WIDTH (1)
+#define DBRP_TUR_LTE_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_LTE_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_LSB (13)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_MASK (0x00002000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_BIT (0x00002000)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_LSB (12)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_LATCH_STATUS_LSB (0)
+#define DBRP_TUR_LTE_LATCH_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_LATCH_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_LATCH_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_LSB (16)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_WIDTH (10)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_MASK (0x03FF0000)
+
+#define DBRP_TUR_LTE_FRM_SIM_IDX_LSB (4)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_WIDTH (1)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_MASK (0x00000010)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_LSB (0)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_SI_PI_PI_TID_LSB (22)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_MASK (0xFFC00000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_LSB (16)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_WIDTH (2)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_MASK (0x00030000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TID_LSB (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_MASK (0x0000FFC0)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_LSB (0)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_WIDTH (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_LSB (4)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_MASK (0x00000010)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_LSB (0)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_MASK (0x00000001)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH0_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH1_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH2_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH3_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH4_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_LSB (20)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_MASK (0x00100000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_LSB (19)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_MASK (0x00080000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_BIT (0x00080000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_LSB (18)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_MASK (0x00040000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_BIT (0x00040000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_LSB (17)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_MASK (0x00020000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_BIT (0x00020000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_LSB (16)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_MASK (0x00010000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_LSB (12)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_LSB (11)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_MASK (0x00000800)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_BIT (0x00000800)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_LSB (10)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_MASK (0x00000400)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_BIT (0x00000400)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_LSB (9)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_MASK (0x00000200)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_BIT (0x00000200)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_LSB (3)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_MASK (0x00000008)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_LSB (2)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_MASK (0x00000004)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_LSB (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_MASK (0x00000002)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CMD0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CMD1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_LSB (8)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_LSB (4)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_LSB (0)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FW_RST_FLAG_LSB (0)
+#define DBRP_TUR_LTE_FW_RST_FLAG_WIDTH (1)
+#define DBRP_TUR_LTE_FW_RST_FLAG_MASK (0x00000001)
+#define DBRP_TUR_LTE_FW_RST_FLAG_BIT (0x00000001)
+
+#define DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_MPU_VIO_ADR_LSB (0)
+#define DBRP_TUR_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_TUR_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_MPU_SW_IRQ_TRG_LSB (5)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_MASK (0x00000020)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_BIT (0x00000020)
+
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_LSB (4)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_MASK (0x00000010)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_MPU_VIOLATE_LSB (0)
+#define DBRP_TUR_MPU_VIOLATE_WIDTH (1)
+#define DBRP_TUR_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_TUR_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_WIDTH (1)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_LSB (0)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_WIDTH (6)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_MASK (0x0000003F)
+
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_LSB (16)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_WIDTH (7)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_MASK (0x007F0000)
+
+#define DBRP_TUR_L_FSM_STATE_LSB (0)
+#define DBRP_TUR_L_FSM_STATE_WIDTH (9)
+#define DBRP_TUR_L_FSM_STATE_MASK (0x000001FF)
+
+#define DBRP_TUR_WT_FSM_STATE_LSB (0)
+#define DBRP_TUR_WT_FSM_STATE_WIDTH (16)
+#define DBRP_TUR_WT_FSM_STATE_MASK (0x0000FFFF)
+
+#define DBRP_TUR_DEC_FSM_STATE_LSB (0)
+#define DBRP_TUR_DEC_FSM_STATE_WIDTH (32)
+#define DBRP_TUR_DEC_FSM_STATE_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DOB_FSM_DMA_STATE_LSB (21)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_WIDTH (2)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_MASK (0x00600000)
+
+#define DBRP_TUR_DOB_FSM_QUE_STATE_LSB (6)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_WIDTH (15)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_MASK (0x001FFFC0)
+
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_LSB (0)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_WIDTH (6)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_MASK (0x0000003F)
+
+#define DBRP_TUR_C_FSM_STATE_LSB (0)
+#define DBRP_TUR_C_FSM_STATE_WIDTH (10)
+#define DBRP_TUR_C_FSM_STATE_MASK (0x000003FF)
+
+#define DBRP_TUR_RTT_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_RTT_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_DST_ADR_LSB (0)
+#define DBRP_TUR_RTT_DST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_RTT_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_RTT_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_RTT_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_LST_ADR_LSB (0)
+#define DBRP_TUR_RTT_LST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_DST_PING_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PING_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PING_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DST_PONG_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_LST_ADR_LSB (0)
+#define DBRP_TUR_EVDO_LST_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_HARQ_ID_LSB (0)
+#define DBRP_TUR_EVDO_HARQ_ID_WIDTH (2)
+#define DBRP_TUR_EVDO_HARQ_ID_MASK (0x00000003)
+
+#define DBRP_TUR_EVDO_PACKET_SIZE_LSB (0)
+#define DBRP_TUR_EVDO_PACKET_SIZE_WIDTH (13)
+#define DBRP_TUR_EVDO_PACKET_SIZE_MASK (0x00001FFF)
+
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_LSB (0)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_WIDTH (1)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_C2K_BUSY_EVDO_LSB (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_MASK (0x00000002)
+#define DBRP_TUR_C2K_BUSY_EVDO_BIT (0x00000002)
+
+#define DBRP_TUR_C2K_BUSY_RTT_LSB (0)
+#define DBRP_TUR_C2K_BUSY_RTT_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_RTT_MASK (0x00000001)
+#define DBRP_TUR_C2K_BUSY_RTT_BIT (0x00000001)
+
+#define DBRP_TUR_CB_NUM_CB_NUM_LSB (0)
+#define DBRP_TUR_CB_NUM_CB_NUM_WIDTH (6)
+#define DBRP_TUR_CB_NUM_CB_NUM_MASK (0x0000003F)
+
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_TUR_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_97.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_97.h
new file mode 100644
index 0000000..004c9cc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_97.h
@@ -0,0 +1,2509 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_TUR_H_
+#define _CPH_C2K_RX_BRP_TUR_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCTL_TUR_REG_BASE (0xac920000)
+
+#define RXBRP_WCTL_TUR_end (RXBRP_WCTL_TUR_REG_BASE + 0xD0A0 + 1*4)
+
+
+
+#define DBRP_TUR_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0000))
+#define DBRP_TUR_DSCRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0004))
+#define DBRP_TUR_C_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0008))
+#define DBRP_TUR_DSCH_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2000))
+#define DBRP_TUR_DSCH_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2004))
+#define DBRP_TUR_DSCH_EN ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2008))
+#define DBRP_TUR_DSCH_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x200C))
+#define DBRP_TUR_DSCH_CBBUF ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2010))
+#define DBRP_TUR_DSCH_CH0_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2014))
+#define DBRP_TUR_DSCH_CH0_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2018))
+#define DBRP_TUR_DSCH_CH0_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x201C))
+#define DBRP_TUR_DSCH_CH0_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2020))
+#define DBRP_TUR_DSCH_CH0_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2024))
+#define DBRP_TUR_DSCH_CH0_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2028))
+#define DBRP_TUR_DSCH_CH0_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x202C))
+#define DBRP_TUR_DSCH_CH0_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2030))
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2034))
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2038))
+#define DBRP_TUR_DSCH_CH1_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x203C))
+#define DBRP_TUR_DSCH_CH1_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2040))
+#define DBRP_TUR_DSCH_CH1_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2044))
+#define DBRP_TUR_DSCH_CH1_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2048))
+#define DBRP_TUR_DSCH_CH1_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x204C))
+#define DBRP_TUR_DSCH_CH1_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2050))
+#define DBRP_TUR_DSCH_CH1_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2054))
+#define DBRP_TUR_DSCH_CH1_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2058))
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x205C))
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2060))
+#define DBRP_TUR_DSCH_CH2_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2064))
+#define DBRP_TUR_DSCH_CH2_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2068))
+#define DBRP_TUR_DSCH_CH2_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x206C))
+#define DBRP_TUR_DSCH_CH2_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2070))
+#define DBRP_TUR_DSCH_CH2_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2074))
+#define DBRP_TUR_DSCH_CH2_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2078))
+#define DBRP_TUR_DSCH_CH2_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x207C))
+#define DBRP_TUR_DSCH_CH2_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2080))
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2084))
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2088))
+#define DBRP_TUR_DSCH_CH3_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x208C))
+#define DBRP_TUR_DSCH_CH3_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2090))
+#define DBRP_TUR_DSCH_CH3_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2094))
+#define DBRP_TUR_DSCH_CH3_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2098))
+#define DBRP_TUR_DSCH_CH3_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x209C))
+#define DBRP_TUR_DSCH_CH3_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A0))
+#define DBRP_TUR_DSCH_CH3_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A4))
+#define DBRP_TUR_DSCH_CH3_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A8))
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20AC))
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B0))
+#define DBRP_TUR_DSCH_CH4_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B4))
+#define DBRP_TUR_DSCH_CH4_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B8))
+#define DBRP_TUR_DSCH_CH4_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20BC))
+#define DBRP_TUR_DSCH_CH4_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C0))
+#define DBRP_TUR_DSCH_CH4_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C4))
+#define DBRP_TUR_DSCH_CH4_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C8))
+#define DBRP_TUR_DSCH_CH4_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20CC))
+#define DBRP_TUR_DSCH_CH4_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D0))
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D4))
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D8))
+#define DBRP_TUR_DSCH_CH0_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20DC))
+#define DBRP_TUR_DSCH_CH0_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E0))
+#define DBRP_TUR_DSCH_CH0_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E4))
+#define DBRP_TUR_DSCH_CH0_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E8))
+#define DBRP_TUR_DSCH_CH0_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20EC))
+#define DBRP_TUR_DSCH_CH0_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F0))
+#define DBRP_TUR_DSCH_CH0_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F4))
+#define DBRP_TUR_DSCH_CH0_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F8))
+#define DBRP_TUR_DSCH_CH1_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20FC))
+#define DBRP_TUR_DSCH_CH1_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2100))
+#define DBRP_TUR_DSCH_CH1_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2104))
+#define DBRP_TUR_DSCH_CH1_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2108))
+#define DBRP_TUR_DSCH_CH1_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x210C))
+#define DBRP_TUR_DSCH_CH1_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2110))
+#define DBRP_TUR_DSCH_CH1_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2114))
+#define DBRP_TUR_DSCH_CH1_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2118))
+#define DBRP_TUR_DSCH_CH2_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x211C))
+#define DBRP_TUR_DSCH_CH2_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2120))
+#define DBRP_TUR_DSCH_CH2_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2124))
+#define DBRP_TUR_DSCH_CH2_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2128))
+#define DBRP_TUR_DSCH_CH2_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x212C))
+#define DBRP_TUR_DSCH_CH2_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2130))
+#define DBRP_TUR_DSCH_CH2_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2134))
+#define DBRP_TUR_DSCH_CH3_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2138))
+#define DBRP_TUR_DSCH_CH3_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x213C))
+#define DBRP_TUR_DSCH_CH3_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2140))
+#define DBRP_TUR_DSCH_CH3_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2144))
+#define DBRP_TUR_DSCH_CH3_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2148))
+#define DBRP_TUR_DSCH_CH3_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x214C))
+#define DBRP_TUR_DSCH_CH3_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2150))
+#define DBRP_TUR_DSCH_CH4_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2154))
+#define DBRP_TUR_DSCH_CH4_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2158))
+#define DBRP_TUR_DSCH_CH4_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x215C))
+#define DBRP_TUR_DSCH_CH4_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2160))
+#define DBRP_TUR_DSCH_CH4_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2164))
+#define DBRP_TUR_DSCH_CH4_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2168))
+#define DBRP_TUR_DSCH_CH4_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x216C))
+#define DBRP_TUR_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2170))
+#define DBRP_TUR_LTE_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3000))
+#define DBRP_TUR_LTE_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3004))
+#define DBRP_TUR_LTE_LATCH ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3008))
+#define DBRP_TUR_LTE_FRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x300C))
+#define DBRP_TUR_LTE_SI_PI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3010))
+#define DBRP_TUR_LTE_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3014))
+#define DBRP_TUR_LTE_CH0_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3018))
+#define DBRP_TUR_LTE_CH0_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x301C))
+#define DBRP_TUR_LTE_CH0_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3020))
+#define DBRP_TUR_LTE_CH0_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3024))
+#define DBRP_TUR_LTE_CH0_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3028))
+#define DBRP_TUR_LTE_CH0_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x302C))
+#define DBRP_TUR_LTE_CH1_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3030))
+#define DBRP_TUR_LTE_CH1_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3034))
+#define DBRP_TUR_LTE_CH1_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3038))
+#define DBRP_TUR_LTE_CH1_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x303C))
+#define DBRP_TUR_LTE_CH1_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3040))
+#define DBRP_TUR_LTE_CH1_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3044))
+#define DBRP_TUR_LTE_CH2_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3048))
+#define DBRP_TUR_LTE_CH2_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x304C))
+#define DBRP_TUR_LTE_CH2_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3050))
+#define DBRP_TUR_LTE_CH2_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3054))
+#define DBRP_TUR_LTE_CH2_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3058))
+#define DBRP_TUR_LTE_CH2_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x305C))
+#define DBRP_TUR_LTE_CH3_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3060))
+#define DBRP_TUR_LTE_CH3_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3064))
+#define DBRP_TUR_LTE_CH3_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3068))
+#define DBRP_TUR_LTE_CH3_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x306C))
+#define DBRP_TUR_LTE_CH3_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3070))
+#define DBRP_TUR_LTE_CH3_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3074))
+#define DBRP_TUR_LTE_CH4_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3078))
+#define DBRP_TUR_LTE_CH4_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x307C))
+#define DBRP_TUR_LTE_CH4_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3080))
+#define DBRP_TUR_LTE_CH4_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3084))
+#define DBRP_TUR_LTE_CH4_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3088))
+#define DBRP_TUR_LTE_CH4_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x308C))
+#define DBRP_TUR_LTE_CC0_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3090))
+#define DBRP_TUR_LTE_CC0_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3094))
+#define DBRP_TUR_LTE_CC0_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3098))
+#define DBRP_TUR_LTE_CC0_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x309C))
+#define DBRP_TUR_LTE_CC0_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A0))
+#define DBRP_TUR_LTE_CC0_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A4))
+#define DBRP_TUR_LTE_CC0_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A8))
+#define DBRP_TUR_LTE_CC0_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30AC))
+#define DBRP_TUR_LTE_CC0_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B0))
+#define DBRP_TUR_LTE_CC0_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B4))
+#define DBRP_TUR_LTE_CC1_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B8))
+#define DBRP_TUR_LTE_CC1_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30BC))
+#define DBRP_TUR_LTE_CC1_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C0))
+#define DBRP_TUR_LTE_CC1_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C4))
+#define DBRP_TUR_LTE_CC1_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C8))
+#define DBRP_TUR_LTE_CC1_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30CC))
+#define DBRP_TUR_LTE_CC1_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D0))
+#define DBRP_TUR_LTE_CC1_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D4))
+#define DBRP_TUR_LTE_CC1_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D8))
+#define DBRP_TUR_LTE_CC1_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30DC))
+#define DBRP_TUR_LTE_CC2_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E0))
+#define DBRP_TUR_LTE_CC2_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E4))
+#define DBRP_TUR_LTE_CC2_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E8))
+#define DBRP_TUR_LTE_CC2_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30EC))
+#define DBRP_TUR_LTE_CC2_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F0))
+#define DBRP_TUR_LTE_CC2_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F4))
+#define DBRP_TUR_LTE_CC2_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F8))
+#define DBRP_TUR_LTE_CC2_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30FC))
+#define DBRP_TUR_LTE_CC2_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3100))
+#define DBRP_TUR_LTE_CC2_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3104))
+#define DBRP_TUR_LTE_DONE_CC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3108))
+#define DBRP_TUR_LTE_CMD0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x310C))
+#define DBRP_TUR_LTE_CMD1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3110))
+#define DBRP_TUR_LTE_CC0_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3114))
+#define DBRP_TUR_LTE_CC0_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3118))
+#define DBRP_TUR_LTE_CC1_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x311C))
+#define DBRP_TUR_LTE_CC1_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3120))
+#define DBRP_TUR_LTE_CC2_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3124))
+#define DBRP_TUR_LTE_CC2_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3128))
+#define DBRP_TUR_LTE_DONE_ASSERT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x312C))
+#define DBRP_TUR_LTE_FW_RST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3FFC))
+#define DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x400C))
+#define DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4010))
+#define DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4014))
+#define DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4018))
+#define DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x401C))
+#define DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4020))
+#define DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4024))
+#define DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4028))
+#define DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x402C))
+#define DBRP_TUR_MPU_VIO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4030))
+#define DBRP_TUR_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4034))
+#define DBRP_TUR_LTE_MPIF_DATA_CNT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5000))
+#define DBRP_TUR_LTE_MPIF_DBG_0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5004))
+#define DBRP_TUR_LTE_MPIF_DBG_1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5008))
+#define DBRP_TUR_LTE_MPIF_DBG_2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x500C))
+#define DBRP_TUR_LTE_MPIF_DBG_3 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5010))
+#define DBRP_TUR_LTE_MPIF_DBG_4 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5014))
+#define DBRP_TUR_LTE_MPIF_DBG_5 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5018))
+#define DBRP_TUR_LTE_MPIF_DBG_6 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x501C))
+#define DBRP_TUR_LTE_MPIF_DBG_7 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5020))
+#define DBRP_TUR_LTE_MPIF_DBG_8 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5024))
+#define DBRP_TUR_LTE_MPIF_DBG_9 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5028))
+#define DBRP_TUR_LTE_MPIF_DBG_10 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x502C))
+#define DBRP_TUR_LTE_MPIF_DBG_11 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5030))
+#define DBRP_TUR_LTE_MPIF_DBG_12 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5034))
+#define DBRP_TUR_LTE_MPIF_DBG_13 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5038))
+#define DBRP_TUR_LTE_MPIF_DBG_14 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x503C))
+#define DBRP_TUR_LTE_MPIF_DBG_15 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5040))
+#define DBRP_TUR_LTE_MPIF_DBG_16 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5044))
+#define DBRP_TUR_LTE_MPIF_DBG_17 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5048))
+#define DBRP_TUR_LTE_MPIF_DBG_18 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x504C))
+#define DBRP_TUR_LTE_MPIF_DBG_19 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5050))
+#define DBRP_TUR_LTE_MPIF_DBG_20 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5054))
+#define DBRP_TUR_LTE_MPIF_DBG_21 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5058))
+#define DBRP_TUR_LTE_MPIF_DBG_22 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x505C))
+#define DBRP_TUR_LTE_MPIF_DBG_23 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5060))
+#define DBRP_TUR_LTE_MPIF_DBG_24 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5064))
+#define DBRP_TUR_LTE_MPIF_DBG_25 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5068))
+#define DBRP_TUR_LTE_MPIF_DBG_26 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x506C))
+#define DBRP_TUR_LTE_MPIF_DBG_27 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5070))
+#define DBRP_TUR_LTE_MPIF_DBG_28 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5074))
+#define DBRP_TUR_LTE_MPIF_DBG_29 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5078))
+#define DBRP_TUR_LTE_MPIF_DBG_30 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x507C))
+#define DBRP_TUR_LTE_MPIF_DBG_31 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5080))
+#define DBRP_TUR_LTE_MPIF_WRITE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5084))
+#define DBRP_TUR_L_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5088))
+#define DBRP_TUR_WT_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x508C))
+#define DBRP_TUR_DEC_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5090))
+#define DBRP_TUR_DOB_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5094))
+#define DBRP_TUR_C_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5098))
+#define DBRP_TUR_MODE_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x509C))
+#define DBRP_TUR_RTT_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6000))
+#define DBRP_TUR_RTT_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6004))
+#define DBRP_TUR_RTT_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6008))
+#define DBRP_TUR_RTT_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x600C))
+#define DBRP_TUR_RTT_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6010))
+#define DBRP_TUR_RTT_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6014))
+#define DBRP_TUR_RTT_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6018))
+#define DBRP_TUR_EVDO_ITER_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7000))
+#define DBRP_TUR_EVDO_DST_PING ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7004))
+#define DBRP_TUR_EVDO_DST_PONG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7008))
+#define DBRP_TUR_EVDO_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x700C))
+#define DBRP_TUR_EVDO_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7010))
+#define DBRP_TUR_EVDO_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7014))
+#define DBRP_TUR_EVDO_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7018))
+#define DBRP_TUR_EVDO_HARQ ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x701C))
+#define DBRP_TUR_EVDO_PACKET ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7020))
+#define DBRP_TUR_EVDO_DST_ADR ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7024))
+#define DBRP_TUR_EVDO_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7028))
+#define DBRP_TUR_C2K_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x702C))
+#define DBRP_TUR_CB_NUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD000))
+#define DBRP_TUR_CH0_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD018))
+#define DBRP_TUR_CH0_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD028))
+#define DBRP_TUR_CH0_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD030))
+#define DBRP_TUR_CH1_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD034))
+#define DBRP_TUR_CH1_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD044))
+#define DBRP_TUR_CH1_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD04C))
+#define DBRP_TUR_CH2_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD050))
+#define DBRP_TUR_CH2_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD060))
+#define DBRP_TUR_CH2_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD068))
+#define DBRP_TUR_CH3_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD06C))
+#define DBRP_TUR_CH3_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD07C))
+#define DBRP_TUR_CH3_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD084))
+#define DBRP_TUR_CH4_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD088))
+#define DBRP_TUR_CH4_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD098))
+#define DBRP_TUR_CH4_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD0A0))
+
+
+#define DBRP_TUR_CFG_CR_TH_OFST_LSB (0)
+#define DBRP_TUR_CFG_CR_TH_OFST_WIDTH (13)
+#define DBRP_TUR_CFG_CR_TH_OFST_MASK (0x00001FFF)
+
+#define DBRP_TUR_DSCRM_BYPASS_LSB (0)
+#define DBRP_TUR_DSCRM_BYPASS_WIDTH (1)
+#define DBRP_TUR_DSCRM_BYPASS_MASK (0x00000001)
+#define DBRP_TUR_DSCRM_BYPASS_BIT (0x00000001)
+
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_LSB (4)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_MASK (0x00000010)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_BIT (0x00000010)
+
+#define DBRP_TUR_C_DBG_EMI_EN_LSB (0)
+#define DBRP_TUR_C_DBG_EMI_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_C_DBG_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_TRG_START_LSB (0)
+#define DBRP_TUR_DSCH_TRG_START_WIDTH (1)
+#define DBRP_TUR_DSCH_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_DSCH_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_LSB (9)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_MASK (0x00000200)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_BIT (0x00000200)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_LSB (8)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_MASK (0x00000100)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_LSB (6)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_MASK (0x00000040)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_LSB (4)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_MASK (0x00000010)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_LSB (3)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_MASK (0x00000008)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_LSB (2)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_MASK (0x00000004)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_LSB (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_MASK (0x00000002)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_LSB (0)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_MASK (0x00000001)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_LSB (6)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_MASK (0x00000040)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_EN_CHi_LSB (0)
+#define DBRP_TUR_DSCH_EN_CHi_WIDTH (5)
+#define DBRP_TUR_DSCH_EN_CHi_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_LSB (0)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_WIDTH (5)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_LSB (0)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_WIDTH (12)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_MASK (0x00000FFF)
+
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_BUSY_DSCH_LSB (1)
+#define DBRP_TUR_BUSY_DSCH_WIDTH (1)
+#define DBRP_TUR_BUSY_DSCH_MASK (0x00000002)
+#define DBRP_TUR_BUSY_DSCH_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_TRG_START_LSB (0)
+#define DBRP_TUR_LTE_TRG_START_WIDTH (1)
+#define DBRP_TUR_LTE_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_LTE_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_LSB (13)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_MASK (0x00002000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_BIT (0x00002000)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_LSB (12)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_LATCH_STATUS_LSB (0)
+#define DBRP_TUR_LTE_LATCH_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_LATCH_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_LATCH_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_LSB (16)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_WIDTH (10)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_MASK (0x03FF0000)
+
+#define DBRP_TUR_LTE_FRM_SIM_IDX_LSB (4)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_WIDTH (1)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_MASK (0x00000010)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_LSB (0)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_SI_PI_PI_TID_LSB (22)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_MASK (0xFFC00000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_LSB (16)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_WIDTH (2)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_MASK (0x00030000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TID_LSB (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_MASK (0x0000FFC0)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_LSB (0)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_WIDTH (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_LSB (4)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_MASK (0x00000010)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_LSB (0)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_MASK (0x00000001)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH0_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH1_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH2_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH3_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH4_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_LSB (20)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_MASK (0x00100000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_LSB (19)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_MASK (0x00080000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_BIT (0x00080000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_LSB (18)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_MASK (0x00040000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_BIT (0x00040000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_LSB (17)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_MASK (0x00020000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_BIT (0x00020000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_LSB (16)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_MASK (0x00010000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_LSB (12)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_LSB (11)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_MASK (0x00000800)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_BIT (0x00000800)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_LSB (10)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_MASK (0x00000400)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_BIT (0x00000400)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_LSB (9)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_MASK (0x00000200)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_BIT (0x00000200)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_LSB (3)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_MASK (0x00000008)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_LSB (2)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_MASK (0x00000004)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_LSB (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_MASK (0x00000002)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CMD0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CMD1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_LSB (8)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_LSB (4)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_LSB (0)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FW_RST_FLAG_LSB (0)
+#define DBRP_TUR_LTE_FW_RST_FLAG_WIDTH (1)
+#define DBRP_TUR_LTE_FW_RST_FLAG_MASK (0x00000001)
+#define DBRP_TUR_LTE_FW_RST_FLAG_BIT (0x00000001)
+
+#define DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_MPU_VIO_ADR_LSB (0)
+#define DBRP_TUR_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_TUR_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_MPU_SW_IRQ_TRG_LSB (5)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_MASK (0x00000020)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_BIT (0x00000020)
+
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_LSB (4)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_MASK (0x00000010)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_MPU_VIOLATE_LSB (0)
+#define DBRP_TUR_MPU_VIOLATE_WIDTH (1)
+#define DBRP_TUR_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_TUR_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_WIDTH (1)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_LSB (0)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_WIDTH (6)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_MASK (0x0000003F)
+
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_LSB (16)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_WIDTH (7)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_MASK (0x007F0000)
+
+#define DBRP_TUR_L_FSM_STATE_LSB (0)
+#define DBRP_TUR_L_FSM_STATE_WIDTH (9)
+#define DBRP_TUR_L_FSM_STATE_MASK (0x000001FF)
+
+#define DBRP_TUR_WT_FSM_STATE_LSB (0)
+#define DBRP_TUR_WT_FSM_STATE_WIDTH (16)
+#define DBRP_TUR_WT_FSM_STATE_MASK (0x0000FFFF)
+
+#define DBRP_TUR_DEC_FSM_STATE_LSB (0)
+#define DBRP_TUR_DEC_FSM_STATE_WIDTH (32)
+#define DBRP_TUR_DEC_FSM_STATE_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DOB_FSM_DMA_STATE_LSB (21)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_WIDTH (2)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_MASK (0x00600000)
+
+#define DBRP_TUR_DOB_FSM_QUE_STATE_LSB (6)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_WIDTH (15)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_MASK (0x001FFFC0)
+
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_LSB (0)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_WIDTH (6)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_MASK (0x0000003F)
+
+#define DBRP_TUR_C_FSM_STATE_LSB (0)
+#define DBRP_TUR_C_FSM_STATE_WIDTH (10)
+#define DBRP_TUR_C_FSM_STATE_MASK (0x000003FF)
+
+#define DBRP_TUR_RTT_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_RTT_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_DST_ADR_LSB (0)
+#define DBRP_TUR_RTT_DST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_RTT_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_RTT_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_RTT_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_LST_ADR_LSB (0)
+#define DBRP_TUR_RTT_LST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_DST_PING_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PING_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PING_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DST_PONG_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_LST_ADR_LSB (0)
+#define DBRP_TUR_EVDO_LST_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_HARQ_ID_LSB (0)
+#define DBRP_TUR_EVDO_HARQ_ID_WIDTH (2)
+#define DBRP_TUR_EVDO_HARQ_ID_MASK (0x00000003)
+
+#define DBRP_TUR_EVDO_PACKET_SIZE_LSB (0)
+#define DBRP_TUR_EVDO_PACKET_SIZE_WIDTH (13)
+#define DBRP_TUR_EVDO_PACKET_SIZE_MASK (0x00001FFF)
+
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_LSB (0)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_WIDTH (1)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_C2K_BUSY_EVDO_LSB (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_MASK (0x00000002)
+#define DBRP_TUR_C2K_BUSY_EVDO_BIT (0x00000002)
+
+#define DBRP_TUR_C2K_BUSY_RTT_LSB (0)
+#define DBRP_TUR_C2K_BUSY_RTT_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_RTT_MASK (0x00000001)
+#define DBRP_TUR_C2K_BUSY_RTT_BIT (0x00000001)
+
+#define DBRP_TUR_CB_NUM_CB_NUM_LSB (0)
+#define DBRP_TUR_CB_NUM_CB_NUM_WIDTH (6)
+#define DBRP_TUR_CB_NUM_CB_NUM_MASK (0x0000003F)
+
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_TUR_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h b/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h
new file mode 100644
index 0000000..b5c6e49
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h
@@ -0,0 +1,1229 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RXDFE_H_
+#define _CPH_C2K_RXDFE_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FC_ACT_REG_BASE (0xA70C0000)
+
+#define RXDFE_FC_ACT_end (RXDFE_FC_ACT_REG_BASE + 0x01A0 + 1*4)
+
+
+
+#define RXDFE_FC_P_SWAP ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0000))
+#define RXDFE_FC_A_SWAP_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0004))
+#define RXDFE_FC_MS_WB_0_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0008))
+#define RXDFE_FC_MS_WB_1_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x000C))
+#define RXDFE_FC_A_SWAP_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0010))
+#define RXDFE_FC_MS_WB_0_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0014))
+#define RXDFE_FC_MS_WB_1_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0018))
+#define RXDFE_FC_P_CON_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x001C))
+#define RXDFE_FC_SW_DCOC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0020))
+#define RXDFE_FC_P_CON_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0024))
+#define RXDFE_FC_SW_DCOC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0028))
+#define RXDFE_FC_P_CON_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x002C))
+#define RXDFE_FC_SW_DCOC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0030))
+#define RXDFE_FC_P_CON_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0034))
+#define RXDFE_FC_SW_DCOC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0038))
+#define RXDFE_FC_C_CON_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x003C))
+#define RXDFE_FC_SW_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0040))
+#define RXDFE_FC_SW_CS_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0044))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0048))
+#define RXDFE_FC_C_CON_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x004C))
+#define RXDFE_FC_SW_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0050))
+#define RXDFE_FC_SW_CS_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0054))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0058))
+#define RXDFE_FC_C_CON_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x005C))
+#define RXDFE_FC_SW_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0060))
+#define RXDFE_FC_SW_CS_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0064))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0068))
+#define RXDFE_FC_C_CON_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x006C))
+#define RXDFE_FC_SW_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0070))
+#define RXDFE_FC_SW_CS_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0074))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0078))
+#define RXDFE_FC_FDPM_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x007C))
+#define RXDFE_FC_FDPM_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0080))
+#define RXDFE_FC_FDPM_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0084))
+#define RXDFE_FC_RFEQ_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0088))
+#define RXDFE_FC_RFEQ_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x008C))
+#define RXDFE_FC_RFEQ_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0090))
+#define RXDFE_FC_RFEQ_3_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0094))
+#define RXDFE_FC_RFEQ_4_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0098))
+#define RXDFE_FC_IQC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x009C))
+#define RXDFE_FC_FDPM_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A0))
+#define RXDFE_FC_FDPM_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A4))
+#define RXDFE_FC_FDPM_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A8))
+#define RXDFE_FC_RFEQ_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00AC))
+#define RXDFE_FC_RFEQ_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B0))
+#define RXDFE_FC_RFEQ_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B4))
+#define RXDFE_FC_RFEQ_3_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B8))
+#define RXDFE_FC_RFEQ_4_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00BC))
+#define RXDFE_FC_IQC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C0))
+#define RXDFE_FC_FDPM_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C4))
+#define RXDFE_FC_FDPM_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C8))
+#define RXDFE_FC_FDPM_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00CC))
+#define RXDFE_FC_RFEQ_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D0))
+#define RXDFE_FC_RFEQ_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D4))
+#define RXDFE_FC_RFEQ_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D8))
+#define RXDFE_FC_RFEQ_3_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00DC))
+#define RXDFE_FC_RFEQ_4_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E0))
+#define RXDFE_FC_IQC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E4))
+#define RXDFE_FC_FDPM_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E8))
+#define RXDFE_FC_FDPM_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00EC))
+#define RXDFE_FC_FDPM_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F0))
+#define RXDFE_FC_RFEQ_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F4))
+#define RXDFE_FC_RFEQ_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F8))
+#define RXDFE_FC_RFEQ_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00FC))
+#define RXDFE_FC_RFEQ_3_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0100))
+#define RXDFE_FC_RFEQ_4_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0104))
+#define RXDFE_FC_IQC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0108))
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x010C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x011C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x012C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x013C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x014C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x015C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x016C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x017C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NCO_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x018C))
+#define RXDFE_FC_NCO_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0190))
+#define RXDFE_FC_NCO_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0194))
+#define RXDFE_FC_NCO_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0198))
+#define RXDFE_FC_NCO_MBSFN_C0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x019C))
+#define RXDFE_FC_NCO_MBSFN_C1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x01A0))
+
+
+#define RXDFE_FC_P_SWAP_P_SWAP_LSB (0)
+#define RXDFE_FC_P_SWAP_P_SWAP_WIDTH (1)
+#define RXDFE_FC_P_SWAP_P_SWAP_MASK (0x00000001)
+#define RXDFE_FC_P_SWAP_P_SWAP_BIT (0x00000001)
+
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_LSB (0)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_WIDTH (1)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_MASK (0x00000001)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_BIT (0x00000001)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_LSB (24)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_LSB (16)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_LSB (8)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_LSB (0)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_LSB (0)
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_MASK (0x0000007F)
+
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_LSB (0)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_WIDTH (1)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_MASK (0x00000001)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_BIT (0x00000001)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_LSB (24)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_LSB (16)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_LSB (8)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_LSB (0)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_LSB (0)
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_MASK (0x0000007F)
+
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_LSB (20)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_LSB (15)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_LSB (14)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_LSB (13)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_LSB (12)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_LSB (10)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_LSB (9)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_LSB (8)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_LSB (4)
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_LSB (0)
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_LSB (16)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_LSB (0)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_LSB (20)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_LSB (15)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_LSB (14)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_LSB (13)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_LSB (12)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_LSB (10)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_LSB (9)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_LSB (8)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_LSB (4)
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_LSB (0)
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_LSB (16)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_LSB (0)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_LSB (20)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_LSB (15)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_LSB (14)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_LSB (13)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_LSB (12)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_LSB (10)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_LSB (9)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_LSB (8)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_LSB (4)
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_LSB (0)
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_LSB (16)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_LSB (0)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_LSB (20)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_LSB (15)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_LSB (14)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_LSB (13)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_LSB (12)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_LSB (10)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_LSB (9)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_LSB (8)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_LSB (4)
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_LSB (0)
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_LSB (16)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_LSB (0)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_LSB (22)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_LSB (21)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_LSB (20)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_LSB (13)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_LSB (12)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_LSB (8)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_LSB (4)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_LSB (0)
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_WIDTH (4)
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_LSB (8)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_LSB (0)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_LSB (22)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_LSB (21)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_LSB (20)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_LSB (13)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_LSB (12)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_LSB (8)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_LSB (4)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_LSB (0)
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_WIDTH (4)
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_LSB (8)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_LSB (0)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_LSB (22)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_LSB (21)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_LSB (20)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_LSB (13)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_LSB (12)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_LSB (8)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_LSB (4)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_LSB (0)
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_WIDTH (4)
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_LSB (8)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_LSB (0)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_LSB (22)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_LSB (21)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_LSB (20)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_LSB (13)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_LSB (12)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_LSB (8)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_LSB (4)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_LSB (0)
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_WIDTH (4)
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_LSB (8)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_LSB (0)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_LSB (16)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_LSB (16)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_LSB (31)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_LSB (28)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_LSB (31)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_LSB (30)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_LSB (28)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_LSB (31)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_LSB (8)
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_WIDTH (7)
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_LSB (0)
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_WIDTH (8)
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_LSB (16)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_LSB (16)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_LSB (31)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_LSB (28)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_LSB (31)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_LSB (30)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_LSB (28)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_LSB (31)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_LSB (8)
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_WIDTH (7)
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_LSB (0)
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_WIDTH (8)
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_LSB (16)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_LSB (16)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_LSB (31)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_LSB (28)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_LSB (31)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_LSB (30)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_LSB (28)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_LSB (31)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_LSB (8)
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_WIDTH (7)
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_LSB (0)
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_WIDTH (8)
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_LSB (16)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_LSB (16)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_LSB (31)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_LSB (28)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_LSB (31)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_LSB (30)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_LSB (28)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_LSB (31)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_LSB (8)
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_WIDTH (7)
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_LSB (0)
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_WIDTH (8)
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_MASK (0x000000FF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_MASK (0x00000007)
+
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_LSB (31)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_MASK (0x80000000)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_LSB (0)
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_WIDTH (23)
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_LSB (31)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_MASK (0x80000000)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_LSB (0)
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_WIDTH (23)
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_LSB (31)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_MASK (0x80000000)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_LSB (0)
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_WIDTH (23)
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_LSB (31)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_MASK (0x80000000)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_LSB (0)
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_WIDTH (23)
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_LSB (31)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_WIDTH (1)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_MASK (0x80000000)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_LSB (0)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_WIDTH (23)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_LSB (31)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_WIDTH (1)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_MASK (0x80000000)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_LSB (0)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_WIDTH (23)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_MASK (0x007FFFFF)
+
+
+#endif //#ifndef _CPH_C2K_RXDFE_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h b/mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h
new file mode 100644
index 0000000..2ca1c78
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h
@@ -0,0 +1,497 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RXDFE_FCIMM_H_
+#define _CPH_C2K_RXDFE_FCIMM_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FC_IMM_REG_BASE (0xA70C0000)
+
+#define RXDFE_FC_IMM_end (RXDFE_FC_IMM_REG_BASE + 0xFFFC + 1*4)
+
+
+
+#define RXDFE_FC_DATE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8000))
+#define RXDFE_FC_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8004))
+#define RXDFE_FC_MIXED_IF_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8008))
+#define RXDFE_FC_TEST_IN_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x800C))
+#define RXDFE_FC_TEST_IN_STEP_SIZE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8010))
+#define RXDFE_FC_TEST_IN_STEP_INIT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8014))
+#define RXDFE_FC_TEST_IN_CON_IQ ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8018))
+#define RXDFE_FC_TEST_IN_DC ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x801C))
+#define RXDFE_FC_TEST_MUQ_IN_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8020))
+#define RXDFE_FC_TEST_MUQ_IN_STEP ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8024))
+#define RXDFE_FC_TEST_MUQ_IN_DC ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8028))
+#define RXDFE_FC_TEST_OUT_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x802C))
+#define RXDFE_FC_TEST_OUT_ALPHA ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8030))
+#define RXDFE_FC_TEST_FORCE_OFF ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8034))
+#define RXDFE_FC_SW_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8038))
+#define RXDFE_FC_SW_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x803C))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8040))
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8044))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8048))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x804C))
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8050))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8054))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8058))
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x805C))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8060))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8064))
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8068))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x806C))
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8070))
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8074))
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8078))
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x807C))
+#define RXDFE_FC_MS_WB_LPF_0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8800))
+#define RXDFE_FC_MS_WB_LPF_1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8804))
+#define RXDFE_FC_INFO_AGCIF_REG(n) ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9000 + (n)*4)) //n is from 0 to 63
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9400))
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9404))
+#define RXDFE_FC_INFO_CRC32_OUT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9408))
+#define RXDFE_FC_INFO_ALPHA_OUT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x940C))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9410))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9414))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9418))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x941C))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9420))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9424))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9428))
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x942C))
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9430))
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9434))
+#define RXDFE_FC_FPGA ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0xF000))
+#define RXDFE_FC_RESERVED ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0xFFFC))
+
+
+#define RXDFE_FC_DATE_RXDFE_FC_DATE_LSB (0)
+#define RXDFE_FC_DATE_RXDFE_FC_DATE_WIDTH (32)
+#define RXDFE_FC_DATE_RXDFE_FC_DATE_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_LSB (0)
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_WIDTH (1)
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_MASK (0x00000001)
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_BIT (0x00000001)
+
+#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_LSB (0)
+#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_WIDTH (3)
+#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_LSB (31)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_WIDTH (1)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_MASK (0x80000000)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_BIT (0x80000000)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_LSB (8)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_MASK (0x00000F00)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_LSB (4)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_MASK (0x000000F0)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_LSB (0)
+#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_WIDTH (2)
+#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_MASK (0x00000003)
+
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_LSB (16)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_MASK (0x03FF0000)
+
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_LSB (0)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_MASK (0x000003FF)
+
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_LSB (16)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_MASK (0x03FF0000)
+
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_LSB (0)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_MASK (0x000003FF)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_LSB (24)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_MASK (0x0F000000)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_LSB (20)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_WIDTH (1)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_MASK (0x00100000)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_BIT (0x00100000)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_LSB (16)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_WIDTH (2)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_MASK (0x00030000)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_LSB (8)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_MASK (0x00000F00)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_LSB (4)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_WIDTH (1)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_MASK (0x00000010)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_BIT (0x00000010)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_LSB (0)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_WIDTH (2)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_MASK (0x00000003)
+
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_LSB (16)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_WIDTH (15)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_MASK (0x7FFF0000)
+
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_LSB (0)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_WIDTH (15)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_MASK (0x00007FFF)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_LSB (31)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_WIDTH (1)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_MASK (0x80000000)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_BIT (0x80000000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_LSB (24)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_WIDTH (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_MASK (0x0F000000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_LSB (20)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_WIDTH (1)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_MASK (0x00100000)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_BIT (0x00100000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_LSB (16)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_WIDTH (2)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_MASK (0x00030000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_LSB (8)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_WIDTH (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_MASK (0x00000F00)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_LSB (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_WIDTH (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_MASK (0x000000F0)
+
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_LSB (16)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_WIDTH (10)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_MASK (0x03FF0000)
+
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_LSB (0)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_WIDTH (10)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_MASK (0x000003FF)
+
+#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_LSB (0)
+#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_WIDTH (15)
+#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_MASK (0x00007FFF)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_LSB (31)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_WIDTH (1)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_MASK (0x80000000)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_BIT (0x80000000)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_LSB (20)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_MASK (0x00F00000)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_LSB (16)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_MASK (0x000F0000)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_LSB (8)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_WIDTH (5)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_MASK (0x00001F00)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_LSB (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_MASK (0x000000F0)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_LSB (0)
+#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_MASK (0x0000000F)
+
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_LSB (8)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_WIDTH (1)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_MASK (0x00000100)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_BIT (0x00000100)
+
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_LSB (0)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_WIDTH (3)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_LSB (4)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_MASK (0x00000010)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_BIT (0x00000010)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_LSB (3)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_MASK (0x00000008)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_BIT (0x00000008)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_LSB (2)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_MASK (0x00000004)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_BIT (0x00000004)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_LSB (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_MASK (0x00000002)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_BIT (0x00000002)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_LSB (0)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_MASK (0x00000001)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_BIT (0x00000001)
+
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_LSB (31)
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_WIDTH (1)
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_MASK (0x80000000)
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_BIT (0x80000000)
+
+#define RXDFE_FC_SW_WIN_SW_CS_WIN_LSB (16)
+#define RXDFE_FC_SW_WIN_SW_CS_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_CS_WIN_MASK (0x000F0000)
+
+#define RXDFE_FC_SW_WIN_SW_NCO_WIN_LSB (12)
+#define RXDFE_FC_SW_WIN_SW_NCO_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_NCO_WIN_MASK (0x0000F000)
+
+#define RXDFE_FC_SW_WIN_SW_C_WIN_LSB (8)
+#define RXDFE_FC_SW_WIN_SW_C_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_C_WIN_MASK (0x00000F00)
+
+#define RXDFE_FC_SW_WIN_SW_P_WIN_LSB (4)
+#define RXDFE_FC_SW_WIN_SW_P_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_P_WIN_MASK (0x000000F0)
+
+#define RXDFE_FC_SW_WIN_SW_ADC_WIN_LSB (0)
+#define RXDFE_FC_SW_WIN_SW_ADC_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_ADC_WIN_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_LSB (31)
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_WIDTH (1)
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_MASK (0x80000000)
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_BIT (0x80000000)
+
+#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_LSB (4)
+#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_WIDTH (4)
+#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_MASK (0x000000F0)
+
+#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_LSB (0)
+#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_WIDTH (4)
+#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_MASK (0x0000000F)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_LSB (24)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_LSB (16)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_LSB (8)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_LSB (0)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_LSB (0)
+#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_MASK (0x0000007F)
+
+#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_LSB (0)
+#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_WIDTH (32)
+#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_LSB (0)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_WIDTH (32)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_LSB (16)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_WIDTH (15)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_MASK (0x7FFF0000)
+
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_LSB (0)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_WIDTH (15)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_MASK (0x00007FFF)
+
+#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_LSB (0)
+#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_WIDTH (32)
+#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_LSB (16)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_WIDTH (15)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_MASK (0x7FFF0000)
+
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_LSB (0)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_WIDTH (15)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_MASK (0x00007FFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_LSB (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_MASK (0x0000FF00)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_MASK (0x000000FF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_LSB (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_MASK (0x00FF0000)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_LSB (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_MASK (0x0000FF00)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_MASK (0x000000FF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_LSB (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_MASK (0x0000FF00)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_MASK (0x000000FF)
+
+#define RXDFE_FC_FPGA_FPGA_CTRL_LSB (0)
+#define RXDFE_FC_FPGA_FPGA_CTRL_WIDTH (32)
+#define RXDFE_FC_FPGA_FPGA_CTRL_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_C2K_RXDFE_FCIMM_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg.h
new file mode 100644
index 0000000..b439591
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphcstopreg_93.h"
+#elif defined(__MD95__)
+#include "cphcstopreg_95.h"
+#else
+#include "cphcstopreg_97.h"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg_93.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg_93.h
new file mode 100644
index 0000000..78683ac
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg_93.h
@@ -0,0 +1,242 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_CSTOP_REG_H_
+#define _CPH_CSTOP_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_TOP_REG_REG_BASE (0xA7800000)
+
+#define CS_TOP_REG_end (CS_TOP_REG_REG_BASE + 0x0048 + 1*4)
+
+
+
+#define CS_C1X_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0000))
+#define CS_CDO_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0004))
+#define CS_WT_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0008))
+#define CS_L_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x000c))
+#define CS_C1X_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0010))
+#define CS_CDO_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0014))
+#define CS_WT_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0018))
+#define CS_L_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x001c))
+#define CS_DFE_PHASE_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0020))
+#define CS_C1X_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0024))
+#define CS_CDO_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0028))
+#define CS_MEM_SHARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x002c))
+#define CS_MEM_STATUS ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0030))
+#define CS_PWR_AWARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0034))
+#define CS_SYS_CK_IDLE_DIV_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0038))
+#define CS_SYS_CK_IDLE_DBG_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x003c))
+#define CS_TEST_BUS_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0040))
+#define CS_RESERVED0 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0044))
+#define CS_RESERVED1 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0048))
+
+/*
+ Merlot SRAM change DELSEL claim to add
+*/
+#if defined(__MTK_TARGET__) && defined(MT6761)
+
+#define CS_CW_1X_RAM_BIST_1 ((APBADDR32)(0xA78201b0))
+#define CS_CW_1X_RAM_BIST_2 ((APBADDR32)(0xA78201b4))
+#define CS_CW_1X_RAM_NOSHARE_BIST_1 ((APBADDR32)(0xA78201c8))
+
+#endif
+
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_LSB (0)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_WIDTH (1)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_MASK (0x00000001)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_BIT (0x00000001)
+
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_LSB (0)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_WIDTH (1)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_MASK (0x00000001)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_BIT (0x00000001)
+
+#define CS_WT_CK_EN_wtcs_ck_div2_en_LSB (1)
+#define CS_WT_CK_EN_wtcs_ck_div2_en_WIDTH (1)
+#define CS_WT_CK_EN_wtcs_ck_div2_en_MASK (0x00000002)
+#define CS_WT_CK_EN_wtcs_ck_div2_en_BIT (0x00000002)
+
+#define CS_WT_CK_EN_wtcs_ck_en_LSB (0)
+#define CS_WT_CK_EN_wtcs_ck_en_WIDTH (1)
+#define CS_WT_CK_EN_wtcs_ck_en_MASK (0x00000001)
+#define CS_WT_CK_EN_wtcs_ck_en_BIT (0x00000001)
+
+#define CS_L_CK_EN_lcs_ck_en_LSB (0)
+#define CS_L_CK_EN_lcs_ck_en_WIDTH (1)
+#define CS_L_CK_EN_lcs_ck_en_MASK (0x00000001)
+#define CS_L_CK_EN_lcs_ck_en_BIT (0x00000001)
+
+#define CS_C1X_SW_RST_c1xcs_sw_rst_LSB (0)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_WIDTH (1)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_MASK (0x00000001)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_BIT (0x00000001)
+
+#define CS_CDO_SW_RST_cdocs_sw_rst_LSB (0)
+#define CS_CDO_SW_RST_cdocs_sw_rst_WIDTH (1)
+#define CS_CDO_SW_RST_cdocs_sw_rst_MASK (0x00000001)
+#define CS_CDO_SW_RST_cdocs_sw_rst_BIT (0x00000001)
+
+#define CS_WT_SW_RST_tcs_sw_rst_LSB (1)
+#define CS_WT_SW_RST_tcs_sw_rst_WIDTH (1)
+#define CS_WT_SW_RST_tcs_sw_rst_MASK (0x00000002)
+#define CS_WT_SW_RST_tcs_sw_rst_BIT (0x00000002)
+
+#define CS_WT_SW_RST_wcs_sw_rst_LSB (0)
+#define CS_WT_SW_RST_wcs_sw_rst_WIDTH (1)
+#define CS_WT_SW_RST_wcs_sw_rst_MASK (0x00000001)
+#define CS_WT_SW_RST_wcs_sw_rst_BIT (0x00000001)
+
+#define CS_L_SW_RST_lcs_sw_rst_LSB (0)
+#define CS_L_SW_RST_lcs_sw_rst_WIDTH (1)
+#define CS_L_SW_RST_lcs_sw_rst_MASK (0x00000001)
+#define CS_L_SW_RST_lcs_sw_rst_BIT (0x00000001)
+
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_LSB (0)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_WIDTH (2)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_MASK (0x00000003)
+
+#define CS_C1X_CFG_c1xcs_data_frac_scale_LSB (6)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_MASK (0x000003C0)
+
+#define CS_C1X_CFG_c1xcs_data_rc_sel_LSB (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_WIDTH (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_MASK (0x00000038)
+
+#define CS_C1X_CFG_c1xcs_iq_swap_LSB (2)
+#define CS_C1X_CFG_c1xcs_iq_swap_WIDTH (1)
+#define CS_C1X_CFG_c1xcs_iq_swap_MASK (0x00000004)
+#define CS_C1X_CFG_c1xcs_iq_swap_BIT (0x00000004)
+
+#define CS_C1X_CFG_c1xcs_input_sel_LSB (0)
+#define CS_C1X_CFG_c1xcs_input_sel_WIDTH (2)
+#define CS_C1X_CFG_c1xcs_input_sel_MASK (0x00000003)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_LSB (14)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_MASK (0x0003C000)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_LSB (12)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_MASK (0x00003000)
+
+#define CS_CDO_CFG_cdocs_iq_swap_div_LSB (11)
+#define CS_CDO_CFG_cdocs_iq_swap_div_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_div_MASK (0x00000800)
+#define CS_CDO_CFG_cdocs_iq_swap_div_BIT (0x00000800)
+
+#define CS_CDO_CFG_cdocs_input_sel_div_LSB (9)
+#define CS_CDO_CFG_cdocs_input_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_input_sel_div_MASK (0x00000600)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_LSB (5)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_MASK (0x000001E0)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_LSB (3)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_MASK (0x00000018)
+
+#define CS_CDO_CFG_cdocs_iq_swap_main_LSB (2)
+#define CS_CDO_CFG_cdocs_iq_swap_main_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_main_MASK (0x00000004)
+#define CS_CDO_CFG_cdocs_iq_swap_main_BIT (0x00000004)
+
+#define CS_CDO_CFG_cdocs_input_sel_main_LSB (0)
+#define CS_CDO_CFG_cdocs_input_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_input_sel_main_MASK (0x00000003)
+
+#define CS_MEM_SHARE_cs_c1x_mem_share_LSB (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_WIDTH (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_MASK (0x00000002)
+#define CS_MEM_SHARE_cs_c1x_mem_share_BIT (0x00000002)
+
+#define CS_MEM_SHARE_cs_wc_mem_mode_LSB (0)
+#define CS_MEM_SHARE_cs_wc_mem_mode_WIDTH (1)
+#define CS_MEM_SHARE_cs_wc_mem_mode_MASK (0x00000001)
+#define CS_MEM_SHARE_cs_wc_mem_mode_BIT (0x00000001)
+
+#define CS_MEM_STATUS_cs_mem_status_LSB (0)
+#define CS_MEM_STATUS_cs_mem_status_WIDTH (2)
+#define CS_MEM_STATUS_cs_mem_status_MASK (0x00000003)
+
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_LSB (2)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_MASK (0x00000004)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_BIT (0x00000004)
+
+#define CS_PWR_AWARE_cs_dcm_idle_en_LSB (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_MASK (0x00000002)
+#define CS_PWR_AWARE_cs_dcm_idle_en_BIT (0x00000002)
+
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_LSB (0)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_MASK (0x00000001)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_BIT (0x00000001)
+
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_MASK (0x0000001F)
+
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_MASK (0x0000001F)
+
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_LSB (0)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_WIDTH (3)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_MASK (0x00000007)
+
+#define CS_RESERVED0_cs_rsv0_LSB (0)
+#define CS_RESERVED0_cs_rsv0_WIDTH (32)
+#define CS_RESERVED0_cs_rsv0_MASK (0xFFFFFFFF)
+
+#define CS_RESERVED1_cs_rsv1_LSB (0)
+#define CS_RESERVED1_cs_rsv1_WIDTH (32)
+#define CS_RESERVED1_cs_rsv1_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg_95.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg_95.h
new file mode 100644
index 0000000..aad6f3e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg_95.h
@@ -0,0 +1,252 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_CSTOP_REG_H_
+#define _CPH_CSTOP_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_TOP_REG_REG_BASE (0xA7800000)
+
+#define CS_TOP_REG_end (CS_TOP_REG_REG_BASE + 0x0048 + 1*4)
+
+
+
+#define CS_C1X_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0000))
+#define CS_CDO_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0004))
+#define CS_WT_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0008))
+#define CS_L_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x000c))
+#define CS_C1X_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0010))
+#define CS_CDO_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0014))
+#define CS_WT_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0018))
+#define CS_L_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x001c))
+#define CS_DFE_PHASE_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0020))
+#define CS_C1X_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0024))
+#define CS_CDO_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0028))
+#define CS_MEM_SHARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x002c))
+#define CS_MEM_STATUS ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0030))
+#define CS_PWR_AWARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0034))
+#define CS_SYS_CK_IDLE_DIV_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0038))
+#define CS_SYS_CK_IDLE_DBG_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x003c))
+#define CS_TEST_BUS_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0040))
+#define CS_RESERVED0 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0044))
+#define CS_RESERVED1 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0048))
+
+
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_LSB (0)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_WIDTH (1)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_MASK (0x00000001)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_BIT (0x00000001)
+
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_LSB (0)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_WIDTH (1)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_MASK (0x00000001)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_BIT (0x00000001)
+
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_LSB (3)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_MASK (0x00000008)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_BIT (0x00000008)
+#define CS_WT_CK_EN_TCS_CK_EN_LSB (2)
+#define CS_WT_CK_EN_TCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_EN_MASK (0x00000004)
+#define CS_WT_CK_EN_TCS_CK_EN_BIT (0x00000004)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_LSB (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_MASK (0x00000002)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_BIT (0x00000002)
+
+#define CS_WT_CK_EN_WCS_CK_EN_LSB (0)
+#define CS_WT_CK_EN_WCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_EN_MASK (0x00000001)
+#define CS_WT_CK_EN_WCS_CK_EN_BIT (0x00000001)
+
+#define CS_L_CK_EN_LCS_CK_EN_LSB (0)
+#define CS_L_CK_EN_LCS_CK_EN_WIDTH (1)
+#define CS_L_CK_EN_LCS_CK_EN_MASK (0x00000001)
+#define CS_L_CK_EN_LCS_CK_EN_BIT (0x00000001)
+
+#define CS_C1X_SW_RST_c1xcs_sw_rst_LSB (0)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_WIDTH (1)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_MASK (0x00000001)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_BIT (0x00000001)
+
+#define CS_CDO_SW_RST_cdocs_sw_rst_LSB (0)
+#define CS_CDO_SW_RST_cdocs_sw_rst_WIDTH (1)
+#define CS_CDO_SW_RST_cdocs_sw_rst_MASK (0x00000001)
+#define CS_CDO_SW_RST_cdocs_sw_rst_BIT (0x00000001)
+
+#define CS_WT_SW_RST_TCS_SW_RST_LSB (1)
+#define CS_WT_SW_RST_TCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_TCS_SW_RST_MASK (0x00000002)
+#define CS_WT_SW_RST_TCS_SW_RST_BIT (0x00000002)
+
+#define CS_WT_SW_RST_WCS_SW_RST_LSB (0)
+#define CS_WT_SW_RST_WCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_WCS_SW_RST_MASK (0x00000001)
+#define CS_WT_SW_RST_WCS_SW_RST_BIT (0x00000001)
+
+#define CS_L_SW_RST_LCS_SW_RST_LSB (0)
+#define CS_L_SW_RST_LCS_SW_RST_WIDTH (1)
+#define CS_L_SW_RST_LCS_SW_RST_MASK (0x00000001)
+#define CS_L_SW_RST_LCS_SW_RST_BIT (0x00000001)
+
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_LSB (0)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_WIDTH (2)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_MASK (0x00000003)
+
+#define CS_C1X_CFG_c1xcs_data_frac_scale_LSB (8)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_MASK (0x00000F00)
+
+#define CS_C1X_CFG_c1xcs_data_rc_sel_LSB (5)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_WIDTH (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_MASK (0x000000E0)
+
+#define CS_C1X_CFG_c1xcs_iq_swap_LSB (4)
+#define CS_C1X_CFG_c1xcs_iq_swap_WIDTH (1)
+#define CS_C1X_CFG_c1xcs_iq_swap_MASK (0x00000010)
+#define CS_C1X_CFG_c1xcs_iq_swap_BIT (0x00000010)
+
+#define CS_C1X_CFG_c1xcs_input_sel_LSB (0)
+#define CS_C1X_CFG_c1xcs_input_sel_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_input_sel_MASK (0x0000000F)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_LSB (18)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_MASK (0x003C0000)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_LSB (16)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_MASK (0x00030000)
+
+#define CS_CDO_CFG_cdocs_iq_swap_div_LSB (15)
+#define CS_CDO_CFG_cdocs_iq_swap_div_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_div_MASK (0x00008000)
+#define CS_CDO_CFG_cdocs_iq_swap_div_BIT (0x00008000)
+
+#define CS_CDO_CFG_cdocs_input_sel_div_LSB (11)
+#define CS_CDO_CFG_cdocs_input_sel_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_div_MASK (0x00007800)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_LSB (7)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_MASK (0x00000780)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_LSB (5)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_MASK (0x00000060)
+
+#define CS_CDO_CFG_cdocs_iq_swap_main_LSB (4)
+#define CS_CDO_CFG_cdocs_iq_swap_main_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_main_MASK (0x00000010)
+#define CS_CDO_CFG_cdocs_iq_swap_main_BIT (0x00000010)
+
+#define CS_CDO_CFG_cdocs_input_sel_main_LSB (0)
+#define CS_CDO_CFG_cdocs_input_sel_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_main_MASK (0x0000000F)
+
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_LSB (3)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_MASK (0x00000008)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_BIT (0x00000008)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_LSB (2)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_MASK (0x00000004)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_BIT (0x00000004)
+#define CS_MEM_SHARE_cs_c1x_mem_share_LSB (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_WIDTH (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_MASK (0x00000002)
+#define CS_MEM_SHARE_cs_c1x_mem_share_BIT (0x00000002)
+
+#define CS_MEM_SHARE_cs_wc_mem_mode_LSB (0)
+#define CS_MEM_SHARE_cs_wc_mem_mode_WIDTH (1)
+#define CS_MEM_SHARE_cs_wc_mem_mode_MASK (0x00000001)
+#define CS_MEM_SHARE_cs_wc_mem_mode_BIT (0x00000001)
+
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_LSB (2)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_WIDTH (1)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_MASK (0x00000004)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_BIT (0x00000004)
+#define CS_MEM_STATUS_cs_mem_status_LSB (0)
+#define CS_MEM_STATUS_cs_mem_status_WIDTH (2)
+#define CS_MEM_STATUS_cs_mem_status_MASK (0x00000003)
+
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_LSB (2)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_MASK (0x00000004)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_BIT (0x00000004)
+
+#define CS_PWR_AWARE_cs_dcm_idle_en_LSB (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_MASK (0x00000002)
+#define CS_PWR_AWARE_cs_dcm_idle_en_BIT (0x00000002)
+
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_LSB (0)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_MASK (0x00000001)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_BIT (0x00000001)
+
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_MASK (0x0000001F)
+
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_MASK (0x0000001F)
+
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_LSB (0)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_WIDTH (3)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_MASK (0x00000007)
+
+#define CS_RESERVED0_cs_rsv0_LSB (0)
+#define CS_RESERVED0_cs_rsv0_WIDTH (32)
+#define CS_RESERVED0_cs_rsv0_MASK (0xFFFFFFFF)
+
+#define CS_RESERVED1_cs_rsv1_LSB (0)
+#define CS_RESERVED1_cs_rsv1_WIDTH (32)
+#define CS_RESERVED1_cs_rsv1_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg_97.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg_97.h
new file mode 100644
index 0000000..5e8bf0b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg_97.h
@@ -0,0 +1,312 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_CSTOP_REG_97_H_
+#define _CPH_CSTOP_REG_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_TOP_REG_REG_BASE (0xA9800000)
+
+#define CS_TOP_REG_end (CS_TOP_REG_REG_BASE + 0x0060 + 1*4)
+
+
+
+#define CS_C1X_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0000))
+#define CS_CDO_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0004))
+#define CS_WT_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0008))
+#define CS_L_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x000c))
+#define CS_C1X_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0010))
+#define CS_CDO_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0014))
+#define CS_WT_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0018))
+#define CS_L_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x001c))
+#define CS_DFE_PHASE_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0020))
+#define CS_C1X_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0024))
+#define CS_CDO_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0028))
+#define CS_MEM_SHARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x002c))
+#define CS_MEM_STATUS ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0030))
+#define CS_PWR_AWARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0034))
+#define CS_SYS_CK_IDLE_DIV_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0038))
+#define CS_SYS_CK_IDLE_DBG_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x003c))
+#define CS_TEST_BUS_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0040))
+#define CS_RESERVED0 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0044))
+#define CS_RESERVED1 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0048))
+#define CS_ST_SYS_CNT_C1X_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x004c))
+#define CS_ST_SYS_CNT_CDO_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0050))
+#define CS_RXDFE_FC_OUT_IQ_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0054))
+#define CS_INPUT_SEL_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0058))
+#define CS_CW_MODE_SEL_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x005c))
+#define CS_DDR_EN_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0060))
+
+
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_LSB (0)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_WIDTH (1)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_MASK (0x00000001)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_BIT (0x00000001)
+
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_LSB (0)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_WIDTH (1)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_MASK (0x00000001)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_BIT (0x00000001)
+
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_LSB (3)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_MASK (0x00000008)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_BIT (0x00000008)
+
+#define CS_WT_CK_EN_TCS_CK_EN_LSB (2)
+#define CS_WT_CK_EN_TCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_EN_MASK (0x00000004)
+#define CS_WT_CK_EN_TCS_CK_EN_BIT (0x00000004)
+
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_LSB (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_MASK (0x00000002)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_BIT (0x00000002)
+
+#define CS_WT_CK_EN_WCS_CK_EN_LSB (0)
+#define CS_WT_CK_EN_WCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_EN_MASK (0x00000001)
+#define CS_WT_CK_EN_WCS_CK_EN_BIT (0x00000001)
+
+#define CS_L_CK_EN_LCS_CK_EN_LSB (0)
+#define CS_L_CK_EN_LCS_CK_EN_WIDTH (1)
+#define CS_L_CK_EN_LCS_CK_EN_MASK (0x00000001)
+#define CS_L_CK_EN_LCS_CK_EN_BIT (0x00000001)
+
+#define CS_C1X_SW_RST_c1xcs_sw_rst_LSB (0)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_WIDTH (1)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_MASK (0x00000001)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_BIT (0x00000001)
+
+#define CS_CDO_SW_RST_cdocs_sw_rst_LSB (0)
+#define CS_CDO_SW_RST_cdocs_sw_rst_WIDTH (1)
+#define CS_CDO_SW_RST_cdocs_sw_rst_MASK (0x00000001)
+#define CS_CDO_SW_RST_cdocs_sw_rst_BIT (0x00000001)
+
+#define CS_WT_SW_RST_TCS_SW_RST_LSB (1)
+#define CS_WT_SW_RST_TCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_TCS_SW_RST_MASK (0x00000002)
+#define CS_WT_SW_RST_TCS_SW_RST_BIT (0x00000002)
+
+#define CS_WT_SW_RST_WCS_SW_RST_LSB (0)
+#define CS_WT_SW_RST_WCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_WCS_SW_RST_MASK (0x00000001)
+#define CS_WT_SW_RST_WCS_SW_RST_BIT (0x00000001)
+
+#define CS_L_SW_RST_LCS_SW_RST_LSB (0)
+#define CS_L_SW_RST_LCS_SW_RST_WIDTH (1)
+#define CS_L_SW_RST_LCS_SW_RST_MASK (0x00000001)
+#define CS_L_SW_RST_LCS_SW_RST_BIT (0x00000001)
+
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_LSB (0)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_WIDTH (2)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_MASK (0x00000003)
+
+#define CS_C1X_CFG_c1xcs_data_frac_scale_LSB (8)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_MASK (0x00000F00)
+
+#define CS_C1X_CFG_c1xcs_data_rc_sel_LSB (5)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_WIDTH (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_MASK (0x000000E0)
+
+#define CS_C1X_CFG_c1xcs_iq_swap_LSB (4)
+#define CS_C1X_CFG_c1xcs_iq_swap_WIDTH (1)
+#define CS_C1X_CFG_c1xcs_iq_swap_MASK (0x00000010)
+#define CS_C1X_CFG_c1xcs_iq_swap_BIT (0x00000010)
+
+#define CS_C1X_CFG_c1xcs_input_sel_LSB (0)
+#define CS_C1X_CFG_c1xcs_input_sel_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_input_sel_MASK (0x0000000F)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_LSB (18)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_MASK (0x003C0000)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_LSB (16)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_MASK (0x00030000)
+
+#define CS_CDO_CFG_cdocs_iq_swap_div_LSB (15)
+#define CS_CDO_CFG_cdocs_iq_swap_div_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_div_MASK (0x00008000)
+#define CS_CDO_CFG_cdocs_iq_swap_div_BIT (0x00008000)
+
+#define CS_CDO_CFG_cdocs_input_sel_div_LSB (11)
+#define CS_CDO_CFG_cdocs_input_sel_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_div_MASK (0x00007800)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_LSB (7)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_MASK (0x00000780)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_LSB (5)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_MASK (0x00000060)
+
+#define CS_CDO_CFG_cdocs_iq_swap_main_LSB (4)
+#define CS_CDO_CFG_cdocs_iq_swap_main_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_main_MASK (0x00000010)
+#define CS_CDO_CFG_cdocs_iq_swap_main_BIT (0x00000010)
+
+#define CS_CDO_CFG_cdocs_input_sel_main_LSB (0)
+#define CS_CDO_CFG_cdocs_input_sel_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_main_MASK (0x0000000F)
+
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_LSB (3)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_MASK (0x00000008)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_BIT (0x00000008)
+
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_LSB (2)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_MASK (0x00000004)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_BIT (0x00000004)
+
+#define CS_MEM_SHARE_cs_c1x_mem_share_LSB (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_WIDTH (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_MASK (0x00000002)
+#define CS_MEM_SHARE_cs_c1x_mem_share_BIT (0x00000002)
+
+#define CS_MEM_SHARE_cs_wc_mem_mode_LSB (0)
+#define CS_MEM_SHARE_cs_wc_mem_mode_WIDTH (1)
+#define CS_MEM_SHARE_cs_wc_mem_mode_MASK (0x00000001)
+#define CS_MEM_SHARE_cs_wc_mem_mode_BIT (0x00000001)
+
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_LSB (2)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_WIDTH (1)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_MASK (0x00000004)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_BIT (0x00000004)
+#define CS_MEM_STATUS_cs_mem_status_LSB (0)
+#define CS_MEM_STATUS_cs_mem_status_WIDTH (2)
+#define CS_MEM_STATUS_cs_mem_status_MASK (0x00000003)
+
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_LSB (2)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_MASK (0x00000004)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_BIT (0x00000004)
+
+#define CS_PWR_AWARE_cs_dcm_idle_en_LSB (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_MASK (0x00000002)
+#define CS_PWR_AWARE_cs_dcm_idle_en_BIT (0x00000002)
+
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_LSB (0)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_MASK (0x00000001)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_BIT (0x00000001)
+
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_MASK (0x0000001F)
+
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_MASK (0x0000001F)
+
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_LSB (0)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_WIDTH (3)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_MASK (0x00000007)
+
+#define CS_RESERVED0_cs_rsv0_LSB (0)
+#define CS_RESERVED0_cs_rsv0_WIDTH (32)
+#define CS_RESERVED0_cs_rsv0_MASK (0xFFFFFFFF)
+
+#define CS_RESERVED1_cs_rsv1_LSB (0)
+#define CS_RESERVED1_cs_rsv1_WIDTH (32)
+#define CS_RESERVED1_cs_rsv1_MASK (0xFFFFFFFF)
+
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_LSB (20)
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_WIDTH (1)
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_MASK (0x00100000)
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_BIT (0x00100000)
+
+#define CS_ST_SYS_CNT_C1X_DBG_ST_SYS_CNT_C1X_DBG_LSB (0)
+#define CS_ST_SYS_CNT_C1X_DBG_ST_SYS_CNT_C1X_DBG_WIDTH (20)
+#define CS_ST_SYS_CNT_C1X_DBG_ST_SYS_CNT_C1X_DBG_MASK (0x000FFFFF)
+
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_LSB (20)
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_WIDTH (1)
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_MASK (0x00100000)
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_BIT (0x00100000)
+
+#define CS_ST_SYS_CNT_CDO_DBG_ST_SYS_CNT_CDO_DBG_LSB (0)
+#define CS_ST_SYS_CNT_CDO_DBG_ST_SYS_CNT_CDO_DBG_WIDTH (20)
+#define CS_ST_SYS_CNT_CDO_DBG_ST_SYS_CNT_CDO_DBG_MASK (0x000FFFFF)
+
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_Q_DBG_LSB (16)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_Q_DBG_WIDTH (15)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_Q_DBG_MASK (0x7FFF0000)
+
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_I_DBG_LSB (0)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_I_DBG_WIDTH (15)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_I_DBG_MASK (0x00007FFF)
+
+#define CS_INPUT_SEL_DBG_INPUT_SEL_DBG_LSB (0)
+#define CS_INPUT_SEL_DBG_INPUT_SEL_DBG_WIDTH (4)
+#define CS_INPUT_SEL_DBG_INPUT_SEL_DBG_MASK (0x0000000F)
+
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_LSB (0)
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_WIDTH (1)
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_MASK (0x00000001)
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_BIT (0x00000001)
+
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_LSB (2)
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_WIDTH (1)
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_MASK (0x00000004)
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_BIT (0x00000004)
+
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_LSB (1)
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_WIDTH (1)
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_MASK (0x00000002)
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_BIT (0x00000002)
+
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_LSB (0)
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_WIDTH (1)
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_MASK (0x00000001)
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_BIT (0x00000001)
+
+
+#endif //#ifndef #ifndef _CPH_CSTOP_REG_97_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphd2bif.h b/mcu/interface/l1/cl1/common/HW/cphd2bif.h
new file mode 100644
index 0000000..5ab61ec
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphd2bif.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphd2bif_93.h"
+#elif defined(__MD95__) || defined(__MD97__)
+#include "cphd2bif_95.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphd2bif_93.h b/mcu/interface/l1/cl1/common/HW/cphd2bif_93.h
new file mode 100644
index 0000000..db429a6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphd2bif_93.h
@@ -0,0 +1,458 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_D2BIF_H_
+#define _CPH_D2BIF_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define RX_BASIC_INFO_CC0 ((APBADDR32)0xAB820028)
+#define RX_BASIC_INFO_CC1 ((APBADDR32)0xAB82004C)
+
+#define D2BIF_CW_REG_BASE (0xAB824000)/*TBD*/
+
+
+#define D2BIF_CW_end (D2BIF_CW_REG_BASE + 0x0084 + 1*4)
+
+
+
+
+#define D2BIF_CW_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0000))
+#define D2BIF_CW_SW_RST ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0004))
+#define D2BIF_CW_ADDR_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0008))
+#define D2BIF_CW_ADDR_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x000C))
+#define D2BIF_CW_SYNC0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0010))
+#define D2BIF_CW_SYNC1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0014))
+#define D2BIF_CW_SYNC2 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0018))
+#define D2BIF_CW_SYNC3 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x001C))
+#define TIMER_SYNC_DATA0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0020))
+#define TIMER_SYNC_DATA1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0024))
+#define TIMER_SYNC_DATA2 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0028))
+#define TIMER_SYNC_DATA3 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x002C))
+#define D2BIF_CW_DIS ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0030))
+#define D2BIF_CW_DBG_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0034))
+#define D2BIF_CW_WREQ_CNT_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0038))
+#define D2BIF_CW_WREQ_CNT_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x003C))
+#define D2BIF_CW_WR_FSM_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0040))
+#define D2BIF_CW_WR_FSM_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0044))
+#define D2BIF_CW_REQ_REC_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0048))
+#define D2BIF_CW_REQ_REC_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x004C))
+#define D2BIF_CW_REQ_REC_2 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0050))
+#define D2BIF_CW_REQ_REC_3 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0054))
+#define D2BIF_CW_W_CON_A0C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0058))
+#define D2BIF_CW_W_CON_A1C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x005C))
+#define D2BIF_CW_W_CON_A0C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0060))
+#define D2BIF_CW_W_CON_A1C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0064))
+#define D2BIF_CW_W_CON_A0C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0068))
+#define D2BIF_CW_W_CON_A1C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x006C))
+#define D2BIF_CW_W_CON_A0C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0070))
+#define D2BIF_CW_W_CON_A1C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0074))
+#define D2BIF_CW_W_CON_QLIC_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0078))
+#define D2BIF_CW_W_CON_QLIC_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x007C))
+#define D2BIF_CW_WADDR_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0080))
+#define D2BIF_CW_RESERVED0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0084))
+
+
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_LSB (19)
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_MASK (0x00080000)
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_BIT (0x00080000)
+
+
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_LSB (16)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_WIDTH (3)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_MASK (0x00070000)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_BIT (0x00070000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_3_LSB (14)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_3_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_3_MASK (0x0000C000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_2_LSB (12)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_2_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_2_MASK (0x00003000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_1_LSB (10)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_1_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_1_MASK (0x00000C00)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_0_LSB (8)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_0_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_0_MASK (0x00000300)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_LSB (5)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_MASK (0x00000020)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_BIT (0x00000020)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_LSB (4)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_MASK (0x00000010)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_BIT (0x00000010)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_LSB (3)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_MASK (0x00000008)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_BIT (0x00000008)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_LSB (2)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_MASK (0x00000004)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_BIT (0x00000004)
+
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_LSB (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_MASK (0x00000002)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_BIT (0x00000002)
+
+#define D2BIF_CW_CON_D2BIF_CW_EN_LSB (0)
+#define D2BIF_CW_CON_D2BIF_CW_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_EN_MASK (0x00000001)
+#define D2BIF_CW_CON_D2BIF_CW_EN_BIT (0x00000001)
+
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_LSB (0)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_WIDTH (1)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_MASK (0x00000001)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_BIT (0x00000001)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_LSB (30)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_WIDTH (1)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_MASK (0x40000000)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_BIT (0x40000000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_1_LSB (16)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_1_WIDTH (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_1_MASK (0x3FFF0000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_LSB (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_WIDTH (1)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_MASK (0x00004000)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_0_LSB (0)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_0_WIDTH (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_0_MASK (0x00003FFF)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_LSB (30)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_WIDTH (1)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_MASK (0x40000000)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_BIT (0x40000000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_3_LSB (16)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_3_WIDTH (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_3_MASK (0x3FFF0000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_LSB (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_WIDTH (1)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_MASK (0x00004000)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_2_LSB (0)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_2_WIDTH (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_2_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_LSB (31)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_MASK (0x80000000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_LSB (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_MASK (0x00004000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_LSB (0)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_WIDTH (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_LSB (31)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_MASK (0x80000000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_LSB (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_MASK (0x00004000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_LSB (0)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_WIDTH (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_LSB (31)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_MASK (0x80000000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_LSB (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_MASK (0x00004000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_LSB (0)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_WIDTH (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_LSB (31)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_WIDTH (1)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_MASK (0x80000000)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_LSB (14)
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_WIDTH (1)
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_MASK (0x00004000)
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_ADDR_SYNC_3_LSB (0)
+#define D2BIF_CW_SYNC3_D2BIF_CW_ADDR_SYNC_3_WIDTH (14)
+#define D2BIF_CW_SYNC3_D2BIF_CW_ADDR_SYNC_3_MASK (0x00003FFF)
+
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_LSB (15)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_WIDTH (4)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_LSB (3)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_WIDTH (12)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_LSB (0)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_WIDTH (3)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_LSB (15)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_WIDTH (4)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_LSB (3)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_WIDTH (12)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_LSB (0)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_WIDTH (3)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_LSB (15)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_WIDTH (4)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_LSB (3)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_WIDTH (12)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_LSB (0)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_WIDTH (3)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_LSB (15)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_WIDTH (4)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_LSB (3)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_WIDTH (12)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_LSB (0)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_WIDTH (3)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_MASK (0x00000007)
+
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_LSB (20)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_MASK (0x00100000)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_BIT (0x00100000)
+
+#define D2BIF_CW_DIS_RSC_EN_DIS_LSB (17)
+#define D2BIF_CW_DIS_RSC_EN_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_RSC_EN_DIS_MASK (0x00020000)
+#define D2BIF_CW_DIS_RSC_EN_DIS_BIT (0x00020000)
+
+#define D2BIF_CW_DBG_CON_DBG_CLR_LSB (4)
+#define D2BIF_CW_DBG_CON_DBG_CLR_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define D2BIF_CW_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define D2BIF_CW_DBG_CON_DBG_EN_LSB (0)
+#define D2BIF_CW_DBG_CON_DBG_EN_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_EN_MASK (0x00000001)
+#define D2BIF_CW_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_LSB (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_LSB (0)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_LSB (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_LSB (0)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_LSB (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_LSB (0)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_LSB (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_LSB (0)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_LSB (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_WIDTH (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_LSB (0)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_WIDTH (1)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_LSB (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_WIDTH (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_LSB (0)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_WIDTH (1)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_LSB (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_WIDTH (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_LSB (0)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_WIDTH (1)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_LSB (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_WIDTH (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_LSB (0)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_WIDTH (1)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_BIT (0x00000001)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_LSB (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_LSB (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_LSB (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_LSB (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_LSB (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_LSB (4)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_MASK (0x00000030)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_LSB (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_MASK (0x0000000C)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_LSB (0)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_MASK (0x00000003)
+
+#endif //#ifndef _CPH_D2BIF_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphd2bif_95.h b/mcu/interface/l1/cl1/common/HW/cphd2bif_95.h
new file mode 100644
index 0000000..2f07d34
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphd2bif_95.h
@@ -0,0 +1,656 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_D2BIF_H_
+#define _CPH_D2BIF_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define RX_BASIC_INFO_CC0 ((APBADDR32)0xAB820028)
+#define RX_BASIC_INFO_CC1 ((APBADDR32)0xAB82004C)
+
+#define D2BIF_CW_REG_BASE (0xAB824000)/*TBD*/
+
+
+#define D2BIF_CW_end (D2BIF_CW_REG_BASE + 0x00F4 + 1*4)
+
+
+
+
+#define D2BIF_CW_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0000))
+#define D2BIF_CW_SW_RST ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0004))
+#define D2BIF_CW_CA_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0008))
+#define D2BIF_CW_CA_SEL_QLIC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x000C))
+#define D2BIF_CW_IQ_SWAP ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0010))
+#define D2BIF_CW_ADDR_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0014))
+#define D2BIF_CW_ADDR_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0018))
+#define D2BIF_CW_ADDR_IC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x001C))
+#define D2BIF_CW_SYNC_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0020))
+#define D2BIF_CW_SYNC_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0024))
+#define D2BIF_CW_SYNC_IC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0028))
+#define TIMER_SYNC_FDD ((APBADDR32)(D2BIF_CW_REG_BASE + 0x002C))
+#define TIMER_SYNC_C1X ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0030))
+#define TIMER_SYNC_CDO ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0034))
+#define D2BIF_CW_DIS ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0038))
+#define D2BIF_CW_DBG_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x003C))
+#define D2BIF_CW_WREQ_CNT_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0038))
+#define D2BIF_CW_WREQ_CNT_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x003C))
+#define D2BIF_CW_WREQ_CNT ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0040))
+#define D2BIF_CW_REQ_REC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0044))
+#define D2BIF_CW_REQ_REC_EN ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0048))
+#define D2BIF_CW_W_CON_A0C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x004C))
+#define D2BIF_CW_W_CON_A1C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0050))
+#define D2BIF_CW_W_CON_A0C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0054))
+#define D2BIF_CW_W_CON_A1C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0058))
+#define D2BIF_CW_W_CON_A0C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x005C))
+#define D2BIF_CW_W_CON_A1C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0060))
+#define D2BIF_CW_W_CON_A0C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0064))
+#define D2BIF_CW_W_CON_A1C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0068))
+#define D2BIF_CW_W_CON_QLIC_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x006C))
+#define D2BIF_CW_W_CON_QLIC_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0070))
+#define D2BIF_CW_WADDR_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0074))
+#define D2BIF_CW_OUT_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0078))
+#define D2BIF_CW_IC_CONF ((APBADDR32)(D2BIF_CW_REG_BASE + 0x007C))
+#define D2BIF_CW_FIFO_STA ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0080))
+#define D2BIF_CW_FIFO_STA_L ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0084))
+#define D2BIF_CW_STA_DBG ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0088))
+#define D2BIF_CW_FDD_RSC_ALIGN ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0090)) //ALPS04870355
+#define D2BIF_CW_RESERVED0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x00F0))
+#define D2BIF_CW_RESERVED1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x00F4))
+
+
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_LSB (15)
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_WIDTH (1)
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_MASK (0x00008000)
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_BIT (0x00008000)
+
+
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_LSB (12)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_WIDTH (3)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_MASK (0x00007000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_23_LSB (10)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_23_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_23_MASK (0x00000C00)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_01_LSB (8)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_01_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_01_MASK (0x00000300)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_LSB (5)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_MASK (0x00000020)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_BIT (0x00000020)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_LSB (4)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_MASK (0x00000010)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_BIT (0x00000010)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_LSB (3)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_MASK (0x00000008)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_BIT (0x00000008)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_LSB (2)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_MASK (0x00000004)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_BIT (0x00000004)
+
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_LSB (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_MASK (0x00000002)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_BIT (0x00000002)
+
+#define D2BIF_CW_CON_D2BIF_CW_EN_LSB (0)
+#define D2BIF_CW_CON_D2BIF_CW_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_EN_MASK (0x00000001)
+#define D2BIF_CW_CON_D2BIF_CW_EN_BIT (0x00000001)
+
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_LSB (0)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_WIDTH (1)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_MASK (0x00000001)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_BIT (0x00000001)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P3_LSB (12)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P3_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P3_MASK (0x0000F000)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P2_LSB (8)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P2_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P2_MASK (0x00000F00)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P1_LSB (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P1_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P1_MASK (0x000000F0)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P0_LSB (0)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P0_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P0_MASK (0x0000000F)
+
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P1_QLIC_LSB (4)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P1_QLIC_WIDTH (4)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P1_QLIC_MASK (0x000000F0)
+
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P0_QLIC_LSB (0)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P0_QLIC_WIDTH (4)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P0_QLIC_MASK (0x0000000F)
+
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_LSB (4)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_WIDTH (1)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_MASK (0x00000010)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_BIT (0x00000010)
+
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_LSB (0)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_WIDTH (4)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_MASK (0x0000000F)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_LSB (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_WIDTH (1)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_MASK (0x00004000)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_01_LSB (0)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_01_WIDTH (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_01_MASK (0x00003FFF)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_LSB (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_WIDTH (1)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_MASK (0x00004000)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_23_LSB (0)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_23_WIDTH (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_23_MASK (0x00003FFF)
+
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_LSB (14)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_WIDTH (1)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_MASK (0x00004000)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_ADDR_IC_LSB (0)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_ADDR_IC_WIDTH (14)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_ADDR_IC_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_LSB (31)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_MASK (0x80000000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_LSB (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_MASK (0x00004000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_LSB (0)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_WIDTH (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_LSB (31)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_MASK (0x80000000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_LSB (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_MASK (0x00004000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_LSB (0)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_WIDTH (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_LSB (31)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_MASK (0x80000000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_LSB (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_MASK (0x00004000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_LSB (0)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_WIDTH (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_LSB (31)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_WIDTH (1)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_MASK (0x80000000)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_BIT (0x80000000)
+
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_LSB (15)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_WIDTH (4)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_LSB (3)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_WIDTH (12)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_LSB (0)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_WIDTH (3)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_LSB (15)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_WIDTH (4)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_LSB (3)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_WIDTH (12)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_MASK (0x00007FF8)
+
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_LSB (31)
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_WIDTH (1)
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_MASK (0x80000000)
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_BIT (0x80000000)
+
+#define TIMER_SYNC_C1X_RTR_SYS_CNT_SYNC_C1X_LSB (0)
+#define TIMER_SYNC_C1X_RTR_SYS_CNT_SYNC_C1X_WIDTH (20)
+#define TIMER_SYNC_C1X_RTR_SYS_CNT_SYNC_C1X_MASK (0x000FFFFF)
+
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_LSB (31)
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_WIDTH (1)
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_MASK (0x80000000)
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_BIT (0x80000000)
+
+#define TIMER_SYNC_CDO_RTR_SYS_CNT_SYNC_CDO_LSB (0)
+#define TIMER_SYNC_CDO_RTR_SYS_CNT_SYNC_CDO_WIDTH (20)
+#define TIMER_SYNC_CDO_RTR_SYS_CNT_SYNC_CDO_MASK (0x000FFFFF)
+
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_LSB (0)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_WIDTH (3)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_LSB (15)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_WIDTH (4)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_LSB (3)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_WIDTH (12)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_LSB (0)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_WIDTH (3)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_LSB (15)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_WIDTH (4)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_LSB (3)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_WIDTH (12)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_LSB (0)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_WIDTH (3)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_MASK (0x00000007)
+
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_LSB (20)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_MASK (0x00100000)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_BIT (0x00100000)
+
+#define D2BIF_CW_DIS_RSC_EN_DIS_LSB (17)
+#define D2BIF_CW_DIS_RSC_EN_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_RSC_EN_DIS_MASK (0x00020000)
+#define D2BIF_CW_DIS_RSC_EN_DIS_BIT (0x00020000)
+
+#define D2BIF_CW_DBG_CON_DBG_CLR_LSB (4)
+#define D2BIF_CW_DBG_CON_DBG_CLR_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define D2BIF_CW_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define D2BIF_CW_DBG_CON_DBG_EN_LSB (0)
+#define D2BIF_CW_DBG_CON_DBG_EN_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_EN_MASK (0x00000001)
+#define D2BIF_CW_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_LSB (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_LSB (0)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_LSB (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_LSB (0)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_LSB (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_LSB (0)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_LSB (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_LSB (0)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_LSB (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_WIDTH (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_LSB (0)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_WIDTH (1)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_LSB (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_WIDTH (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_LSB (0)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_WIDTH (1)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_LSB (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_WIDTH (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_LSB (0)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_WIDTH (1)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_LSB (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_WIDTH (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_LSB (0)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_WIDTH (1)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_BIT (0x00000001)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_LSB (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_LSB (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_LSB (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_LSB (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_LSB (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_LSB (4)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_MASK (0x00000030)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_LSB (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_MASK (0x0000000C)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_LSB (0)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_MASK (0x00000003)
+
+#define D2BIF_CW_OUT_SEL_D2BIF_CW_OUT_SEL_LSB (0)
+#define D2BIF_CW_OUT_SEL_D2BIF_CW_OUT_SEL_WIDTH (2)
+#define D2BIF_CW_OUT_SEL_D2BIF_CW_OUT_SEL_MASK (0x00000003)
+
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_LSB (1)
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_WIDTH (1)
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_MASK (0x00000002)
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_BIT (0x00000002)
+
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_LSB (0)
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_WIDTH (1)
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_MASK (0x00000001)
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_BIT (0x00000001)
+
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_LSB (9)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_MASK (0x00000200)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_BIT (0x00000200)
+
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_LSB (8)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_MASK (0x00000100)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_BIT (0x00000100)
+
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_LSB (7)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_MASK (0x00000080)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_BIT (0x00000080)
+
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_LSB (6)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_MASK (0x00000040)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_BIT (0x00000040)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_LSB (5)
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_MASK (0x00000020)
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_BIT (0x00000020)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_LSB (4)
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_MASK (0x00000010)
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_BIT (0x00000010)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_LSB (3)
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_MASK (0x00000008)
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_BIT (0x00000008)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_LSB (2)
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_MASK (0x00000004)
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_BIT (0x00000004)
+
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_LSB (1)
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_MASK (0x00000002)
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_BIT (0x00000002)
+
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_LSB (0)
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_MASK (0x00000001)
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_BIT (0x00000001)
+
+#define D2BIF_CW_FIFO_STA_L_FIFO_FULL_CNT_LSB (16)
+#define D2BIF_CW_FIFO_STA_L_FIFO_FULL_CNT_WIDTH (16)
+#define D2BIF_CW_FIFO_STA_L_FIFO_FULL_CNT_MASK (0xFFFF0000)
+
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_LSB (12)
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_MASK (0x00001000)
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_BIT (0x00001000)
+
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_LSB (11)
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_MASK (0x00000800)
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_BIT (0x00000800)
+
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_LSB (10)
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_MASK (0x00000400)
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_BIT (0x00000400)
+
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_LSB (9)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_MASK (0x00000200)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_BIT (0x00000200)
+
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_LSB (8)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_MASK (0x00000100)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_BIT (0x00000100)
+
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_LSB (7)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_MASK (0x00000080)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_BIT (0x00000080)
+
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_LSB (6)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_MASK (0x00000040)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_BIT (0x00000040)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_LSB (5)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_MASK (0x00000020)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_BIT (0x00000020)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_LSB (4)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_MASK (0x00000010)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_BIT (0x00000010)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_LSB (3)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_MASK (0x00000008)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_BIT (0x00000008)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_LSB (2)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_MASK (0x00000004)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_BIT (0x00000004)
+
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_LSB (1)
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_MASK (0x00000002)
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_BIT (0x00000002)
+
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_LSB (0)
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_MASK (0x00000001)
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_BIT (0x00000001)
+
+#define D2BIF_CW_STA_DBG_WR_STATE_1_LSB (17)
+#define D2BIF_CW_STA_DBG_WR_STATE_1_WIDTH (3)
+#define D2BIF_CW_STA_DBG_WR_STATE_1_MASK (0x000E0000)
+
+#define D2BIF_CW_STA_DBG_WR_STATE_0_LSB (14)
+#define D2BIF_CW_STA_DBG_WR_STATE_0_WIDTH (3)
+#define D2BIF_CW_STA_DBG_WR_STATE_0_MASK (0x0001C000)
+
+#define D2BIF_CW_STA_DBG_W_DONE_STATE_LSB (12)
+#define D2BIF_CW_STA_DBG_W_DONE_STATE_WIDTH (2)
+#define D2BIF_CW_STA_DBG_W_DONE_STATE_MASK (0x00003000)
+
+#define D2BIF_CW_STA_DBG_DONE_STATE_Q_LSB (9)
+#define D2BIF_CW_STA_DBG_DONE_STATE_Q_WIDTH (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_Q_MASK (0x00000E00)
+
+#define D2BIF_CW_STA_DBG_DONE_STATE_1_LSB (6)
+#define D2BIF_CW_STA_DBG_DONE_STATE_1_WIDTH (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_1_MASK (0x000001C0)
+
+#define D2BIF_CW_STA_DBG_DONE_STATE_0_LSB (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_0_WIDTH (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_0_MASK (0x00000038)
+
+#define D2BIF_CW_STA_DBG_W_STATE_LSB (0)
+#define D2BIF_CW_STA_DBG_W_STATE_WIDTH (3)
+#define D2BIF_CW_STA_DBG_W_STATE_MASK (0x00000007)
+
+#define D2BIF_CW_RESERVED0_D2BIF_CW_RESERVED0_LSB (0)
+#define D2BIF_CW_RESERVED0_D2BIF_CW_RESERVED0_WIDTH (32)
+#define D2BIF_CW_RESERVED0_D2BIF_CW_RESERVED0_MASK (0xFFFFFFFF)
+
+#define D2BIF_CW_RESERVED1_D2BIF_CW_RESERVED1_LSB (0)
+#define D2BIF_CW_RESERVED1_D2BIF_CW_RESERVED1_WIDTH (32)
+#define D2BIF_CW_RESERVED1_D2BIF_CW_RESERVED1_MASK (0xFFFFFFFF)
+
+#endif //#ifndef _CPH_D2BIF_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h
new file mode 100644
index 0000000..a93cc5c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPH_DFESYS_GLBCON_CONFIG0_H_
+#define _CPH_DFESYS_GLBCON_CONFIG0_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define DFESYS_GLB_CON_CONFIG0_REG_BASE (0xA8990000)
+
+#define DFESYS_GLB_CON_CONFIG0_end (DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define DEBUG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define F208M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define F208M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBSRP_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBSRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBSRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define TXCRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define TXCRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0084))
+#define SW_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0090))
+#define MASK_TXBSRP_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0094))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+#define R2T_RDATA1 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0104))
+#define R2T_RDATA2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0108))
+#define R2T_RDATA3 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x010c))
+#define R2T_RDATA4 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0110))
+#define R2T_RDATA5 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114))
+
+
+#define DIV_TXBRP_DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_DIV_TXBRP_MASK (0x00000001)
+#define DIV_TXBRP_DIV_TXBRP_BIT (0x00000001)
+
+#define DIV_TXCRP_DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_DIV_TXCRP_MASK (0x00000003)
+
+#define DEBUG_SEL_DEBUG_SEL_3_LSB (24)
+#define DEBUG_SEL_DEBUG_SEL_3_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_3_MASK (0x1F000000)
+
+#define DEBUG_SEL_DEBUG_SEL_2_LSB (16)
+#define DEBUG_SEL_DEBUG_SEL_2_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_2_MASK (0x001F0000)
+
+#define DEBUG_SEL_DEBUG_SEL_1_LSB (8)
+#define DEBUG_SEL_DEBUG_SEL_1_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_1_MASK (0x00001F00)
+
+#define DEBUG_SEL_DEBUG_SEL_0_LSB (0)
+#define DEBUG_SEL_DEBUG_SEL_0_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_0_MASK (0x0000001F)
+
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_LSB (0)
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_WIDTH (32)
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_LSB (0)
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_WIDTH (32)
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_MASK (0xFFFFFFFF)
+
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_LSB (0)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_WIDTH (1)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_MASK (0x00000001)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_LSB (1)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_MASK (0x00000002)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_BIT (0x00000002)
+
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_LSB (0)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_WIDTH (1)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_MASK (0x00000001)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_BIT (0x00000001)
+
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_LSB (0)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_LSB (0)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_WIDTH (1)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_LSB (0)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_LSB (3)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_MASK (0x00000008)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_BIT (0x00000008)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_LSB (2)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_MASK (0x00000004)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_BIT (0x00000004)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_LSB (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000002)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000002)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+#define R2T_RDATA1_R2T_RDATA1_LSB (0)
+#define R2T_RDATA1_R2T_RDATA1_WIDTH (32)
+#define R2T_RDATA1_R2T_RDATA1_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA2_R2T_RDATA2_LSB (0)
+#define R2T_RDATA2_R2T_RDATA2_WIDTH (32)
+#define R2T_RDATA2_R2T_RDATA2_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA3_R2T_RDATA3_LSB (0)
+#define R2T_RDATA3_R2T_RDATA3_WIDTH (32)
+#define R2T_RDATA3_R2T_RDATA3_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA4_R2T_RDATA4_LSB (0)
+#define R2T_RDATA4_R2T_RDATA4_WIDTH (32)
+#define R2T_RDATA4_R2T_RDATA4_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA5_R2T_RDATA5_LSB (0)
+#define R2T_RDATA5_R2T_RDATA5_WIDTH (32)
+#define R2T_RDATA5_R2T_RDATA5_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h
new file mode 100644
index 0000000..e4a8a5d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h
@@ -0,0 +1,492 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_DFESYS_GLBCON_CONFIG1_H_
+#define _CPH_DFESYS_GLBCON_CONFIG1_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define DFESYS_GLB_CON_CONFIG1_REG_BASE (0xA8bd0000)
+
+#define DFESYS_GLB_CON_CONFIG1_end (DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218 + 1*4)
+
+
+
+#define TXDFE_D_BSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0008))
+#define TXDFE_D_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0010))
+#define TXDFE_D_F156M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define TXDFE_D_F26M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_D_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x001c))
+#define TPC_D_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0020))
+#define TPC_D_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TDD_TTR_F6P5M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define LTE_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0050))
+#define LTE_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define LTE_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0058))
+#define NR_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))
+#define NR_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+#define NR_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define NR_TTR3_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))
+#define SERDES_COS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a0))
+#define SERDES_ACNT_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a4))
+#define SERDES_L3_TX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a8))
+#define SERDES_L3_RX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00ac))
+#define SERDES_MISC_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b0))
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b4))
+#define DIGRF_OFF_HW_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00bc))
+#define F312M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c0))
+#define F312M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c4))
+#define DFESYS_DEBUG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c8))
+#define RXDFE_F312M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+#define RXDFE_F156M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0104))
+#define RXDFE_F26M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0108))
+#define SERDES_SWRST0_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0200))
+#define SERDES_SWRST1_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0204))
+#define DBG_FLAG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0208))
+#define DBG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x020c))
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0210))
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0214))
+#define D_GDMA_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218))
+
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_LSB (6)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_MASK (0x00000040)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_BIT (0x00000040)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_LSB (5)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_MASK (0x00000020)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_BIT (0x00000020)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_LSB (4)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_MASK (0x00000010)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_BIT (0x00000010)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_LSB (3)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_MASK (0x00000008)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_BIT (0x00000008)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_LSB (2)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_MASK (0x00000004)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_BIT (0x00000004)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_LSB (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_MASK (0x00000002)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_BIT (0x00000002)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_LSB (0)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_MASK (0x00000001)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_BIT (0x00000001)
+
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_LSB (0)
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_WIDTH (1)
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_MASK (0x00000001)
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_LSB (6)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_MASK (0x00000040)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_BIT (0x00000040)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_LSB (5)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_MASK (0x00000020)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_BIT (0x00000020)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_LSB (4)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_MASK (0x00000010)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_BIT (0x00000010)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_LSB (3)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_MASK (0x00000008)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_BIT (0x00000008)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_LSB (2)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_MASK (0x00000004)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_BIT (0x00000004)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_LSB (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_MASK (0x00000002)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_BIT (0x00000002)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_LSB (0)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_MASK (0x00000001)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_BIT (0x00000001)
+
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_LSB (0)
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_WIDTH (1)
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_MASK (0x00000001)
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_LSB (0)
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_WIDTH (1)
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_MASK (0x00000001)
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_BIT (0x00000001)
+
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_LSB (1)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_MASK (0x00000002)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_BIT (0x00000002)
+
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_LSB (0)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_LSB (1)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_MASK (0x00000002)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_BIT (0x00000002)
+
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_LSB (0)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000001)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)
+
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_LSB (0)
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_WIDTH (1)
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_MASK (0x00000001)
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_LSB (0)
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_WIDTH (1)
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_LSB (0)
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_WIDTH (1)
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_BIT (0x00000001)
+
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_LSB (0)
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_WIDTH (1)
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_MASK (0x00000001)
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_BIT (0x00000001)
+
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_LSB (0)
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_BIT (0x00000001)
+
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_LSB (0)
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_BIT (0x00000001)
+
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_LSB (0)
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_BIT (0x00000001)
+
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_LSB (0)
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_LSB (0)
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_WIDTH (1)
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_LSB (0)
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_WIDTH (1)
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_LSB (0)
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_WIDTH (1)
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_LSB (0)
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_WIDTH (1)
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_LSB (0)
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_WIDTH (1)
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_LSB (0)
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_WIDTH (1)
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_LSB (0)
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_WIDTH (1)
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_MASK (0x00000001)
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_BIT (0x00000001)
+
+#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_LSB (0)
+#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_WIDTH (32)
+#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_LSB (0)
+#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_WIDTH (32)
+#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_MASK (0xFFFFFFFF)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (5)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000001F)
+
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_LSB (0)
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_WIDTH (1)
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_MASK (0x00000001)
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_BIT (0x00000001)
+
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_LSB (0)
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_WIDTH (1)
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_MASK (0x00000001)
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_BIT (0x00000001)
+
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_LSB (0)
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_WIDTH (1)
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_MASK (0x00000001)
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_LSB (13)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_MASK (0x00002000)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_BIT (0x00002000)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_LSB (12)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_MASK (0x00001000)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_BIT (0x00001000)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_LSB (11)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_MASK (0x00000800)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_BIT (0x00000800)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_LSB (10)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_MASK (0x00000400)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_BIT (0x00000400)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_LSB (9)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_MASK (0x00000200)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_BIT (0x00000200)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_LSB (8)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_MASK (0x00000100)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_BIT (0x00000100)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_LSB (7)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_MASK (0x00000080)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_BIT (0x00000080)
+
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_LSB (6)
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_MASK (0x00000040)
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_BIT (0x00000040)
+
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_LSB (5)
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_MASK (0x00000020)
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_BIT (0x00000020)
+
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_LSB (4)
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_MASK (0x00000010)
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_BIT (0x00000010)
+
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_LSB (3)
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_MASK (0x00000008)
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_BIT (0x00000008)
+
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_LSB (2)
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_MASK (0x00000004)
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_BIT (0x00000004)
+
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_LSB (1)
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_MASK (0x00000002)
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_BIT (0x00000002)
+
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_LSB (0)
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_MASK (0x00000001)
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_BIT (0x00000001)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_LSB (15)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_MASK (0x00008000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_BIT (0x00008000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_LSB (14)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_MASK (0x00004000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_BIT (0x00004000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_LSB (13)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_MASK (0x00002000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_BIT (0x00002000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_LSB (12)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_MASK (0x00001000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_BIT (0x00001000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_LSB (11)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_MASK (0x00000800)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_BIT (0x00000800)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_LSB (10)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_MASK (0x00000400)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_BIT (0x00000400)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_LSB (9)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_MASK (0x00000200)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_BIT (0x00000200)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_LSB (8)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_MASK (0x00000100)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_BIT (0x00000100)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_LSB (7)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_MASK (0x00000080)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_BIT (0x00000080)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_LSB (6)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_MASK (0x00000040)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_BIT (0x00000040)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_LSB (5)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_MASK (0x00000020)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_BIT (0x00000020)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_LSB (4)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_MASK (0x00000010)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_BIT (0x00000010)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_LSB (3)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_MASK (0x00000008)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_BIT (0x00000008)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_LSB (2)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_MASK (0x00000004)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_BIT (0x00000004)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_LSB (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_MASK (0x00000002)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_BIT (0x00000002)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_LSB (0)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_MASK (0x00000001)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_BIT (0x00000001)
+
+#define DBG_FLAG_SEL_DBG_FLAG3_SEL_LSB (24)
+#define DBG_FLAG_SEL_DBG_FLAG3_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG3_SEL_MASK (0xFF000000)
+
+#define DBG_FLAG_SEL_DBG_FLAG2_SEL_LSB (16)
+#define DBG_FLAG_SEL_DBG_FLAG2_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG2_SEL_MASK (0x00FF0000)
+
+#define DBG_FLAG_SEL_DBG_FLAG1_SEL_LSB (8)
+#define DBG_FLAG_SEL_DBG_FLAG1_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG1_SEL_MASK (0x0000FF00)
+
+#define DBG_FLAG_SEL_DBG_FLAG0_SEL_LSB (0)
+#define DBG_FLAG_SEL_DBG_FLAG0_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG0_SEL_MASK (0x000000FF)
+
+#define DBG_TRIG_SEL_DBG_TRIG_SEL_LSB (0)
+#define DBG_TRIG_SEL_DBG_TRIG_SEL_WIDTH (8)
+#define DBG_TRIG_SEL_DBG_TRIG_SEL_MASK (0x000000FF)
+
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_LSB (0)
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_LSB (0)
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_WIDTH (1)
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_MASK (0x00000001)
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_BIT (0x00000001)
+
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_LSB (0)
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_WIDTH (1)
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_MASK (0x00000001)
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_BIT (0x00000001)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxbrp.h b/mcu/interface/l1/cl1/common/HW/cphevdorxbrp.h
new file mode 100644
index 0000000..6b214c1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxbrp.h
@@ -0,0 +1,511 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RXBRP_H_
+#define _CPH_EVDO_RXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if (defined(__MD93__))||(defined(__MD95__))
+#define RXBRP_C_EVDO_REG_BASE (0xAD230000)
+#else
+#define RXBRP_C_EVDO_REG_BASE (0xACA30000)
+#endif
+
+#define RXBRP_C_EVDO_end (RXBRP_C_EVDO_REG_BASE + 0x0204 + 1*4)
+
+
+
+#define DBRP_EVDO_START ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0000))
+#define DBRP_EVDO_DONE ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0004))
+#define DBRP_EVDO_DONE_VEC ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0008))
+#define DBRP_EVDO_CH_DET ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x000C))
+#define DBRP_EVDO_HARQ_INFO ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0010))
+#define DBRP_EVDO_C2I_SCAL_QPSK ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0014))
+#define DBRP_EVDO_C2I_SCAL_8PSK ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0018))
+#define DBRP_EVDO_C2I_SCAL_16QAM ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x001C))
+#define DBRP_EVDO_HARQ_DBG ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00A0))
+#define DBRP_EVDO_C2I_RD ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00A4))
+#define DBRP_EVDO_C2I_RD_ADDR ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00A8))
+#define DBRP_EVDO_C2I_RD_DATA ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00AC))
+#define DBRP_EVDO_HARQ_RD ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00B0))
+#define DBRP_EVDO_HARQ_RD_ADDR ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00B4))
+#define DBRP_EVDO_HARQ_RD_DATA ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00B8))
+#define DBRP_EVDO_HARQ_ABSACC_03 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00BC))
+#define DBRP_EVDO_HARQ_ABSACC_47 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00C0))
+#define DBRP_EVDO_DBG0 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00D0))
+#define DBRP_EVDO_PWR_CFG ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00F0))
+#define DBRP_EVDO_HARQ_PARAM ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0100))
+#define DBRP_EVDO_CH0_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0104))
+#define DBRP_EVDO_CH0_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0108))
+#define DBRP_EVDO_CH0_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x010C))
+#define DBRP_EVDO_CH1_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0110))
+#define DBRP_EVDO_CH1_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0114))
+#define DBRP_EVDO_CH1_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0118))
+#define DBRP_EVDO_CH2_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x011C))
+#define DBRP_EVDO_CH2_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0120))
+#define DBRP_EVDO_CH2_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0124))
+#define DBRP_EVDO_CH3_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0128))
+#define DBRP_EVDO_CH3_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x012C))
+#define DBRP_EVDO_CH3_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0130))
+#define DBRP_EVDO_C2I_PARAM0 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0200))
+#define DBRP_EVDO_C2I_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0204))
+
+
+#define DBRP_EVDO_START_EVDO_START_LSB (15)
+#define DBRP_EVDO_START_EVDO_START_WIDTH (1)
+#define DBRP_EVDO_START_EVDO_START_MASK (0x00008000)
+#define DBRP_EVDO_START_EVDO_START_BIT (0x00008000)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_LSB (16)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_WIDTH (1)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_MASK (0x00010000)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_BIT (0x00010000)
+
+#define DBRP_EVDO_DONE_EVDO_DONE_LSB (0)
+#define DBRP_EVDO_DONE_EVDO_DONE_WIDTH (1)
+#define DBRP_EVDO_DONE_EVDO_DONE_MASK (0x00000001)
+#define DBRP_EVDO_DONE_EVDO_DONE_BIT (0x00000001)
+
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_LSB (1)
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_WIDTH (1)
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_MASK (0x00000002)
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_BIT (0x00000002)
+
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_LSB (0)
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_WIDTH (1)
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_MASK (0x00000001)
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_BIT (0x00000001)
+
+#define DBRP_EVDO_CH_DET_CH3_EN_LSB (3)
+#define DBRP_EVDO_CH_DET_CH3_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH3_EN_MASK (0x00000008)
+#define DBRP_EVDO_CH_DET_CH3_EN_BIT (0x00000008)
+
+#define DBRP_EVDO_CH_DET_CH2_EN_LSB (2)
+#define DBRP_EVDO_CH_DET_CH2_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH2_EN_MASK (0x00000004)
+#define DBRP_EVDO_CH_DET_CH2_EN_BIT (0x00000004)
+
+#define DBRP_EVDO_CH_DET_CH1_EN_LSB (1)
+#define DBRP_EVDO_CH_DET_CH1_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH1_EN_MASK (0x00000002)
+#define DBRP_EVDO_CH_DET_CH1_EN_BIT (0x00000002)
+
+#define DBRP_EVDO_CH_DET_CH0_EN_LSB (0)
+#define DBRP_EVDO_CH_DET_CH0_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH0_EN_MASK (0x00000001)
+#define DBRP_EVDO_CH_DET_CH0_EN_BIT (0x00000001)
+
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_LSB (3)
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_WIDTH (1)
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_MASK (0x00000008)
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_BIT (0x00000008)
+
+#define DBRP_EVDO_HARQ_INFO_INTERLANCE_LSB (1)
+#define DBRP_EVDO_HARQ_INFO_INTERLANCE_WIDTH (2)
+#define DBRP_EVDO_HARQ_INFO_INTERLANCE_MASK (0x00000006)
+
+#define DBRP_EVDO_HARQ_INFO_NDI_LSB (0)
+#define DBRP_EVDO_HARQ_INFO_NDI_WIDTH (1)
+#define DBRP_EVDO_HARQ_INFO_NDI_MASK (0x00000001)
+#define DBRP_EVDO_HARQ_INFO_NDI_BIT (0x00000001)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_LSB (31)
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_WIDTH (1)
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_MASK (0x80000000)
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_BIT (0x80000000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_SHIFT_C2I_LSB (24)
+#define DBRP_EVDO_C2I_SCAL_QPSK_SHIFT_C2I_WIDTH (5)
+#define DBRP_EVDO_C2I_SCAL_QPSK_SHIFT_C2I_MASK (0x1F000000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_3_LSB (18)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_3_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_3_MASK (0x00FC0000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_2_LSB (12)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_2_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_2_MASK (0x0003F000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_1_LSB (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_1_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_1_MASK (0x00000FC0)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_0_LSB (0)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_0_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_0_MASK (0x0000003F)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_LSB (31)
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_WIDTH (1)
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_MASK (0x80000000)
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_BIT (0x80000000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_SHIFT_C2I_LSB (24)
+#define DBRP_EVDO_C2I_SCAL_8PSK_SHIFT_C2I_WIDTH (5)
+#define DBRP_EVDO_C2I_SCAL_8PSK_SHIFT_C2I_MASK (0x1F000000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_3_LSB (18)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_3_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_3_MASK (0x00FC0000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_2_LSB (12)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_2_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_2_MASK (0x0003F000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_1_LSB (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_1_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_1_MASK (0x00000FC0)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_0_LSB (0)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_0_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_0_MASK (0x0000003F)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_LSB (31)
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_WIDTH (1)
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_MASK (0x80000000)
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_BIT (0x80000000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_SHIFT_C2I_LSB (24)
+#define DBRP_EVDO_C2I_SCAL_16QAM_SHIFT_C2I_WIDTH (5)
+#define DBRP_EVDO_C2I_SCAL_16QAM_SHIFT_C2I_MASK (0x1F000000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_3_LSB (18)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_3_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_3_MASK (0x00FC0000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_2_LSB (12)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_2_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_2_MASK (0x0003F000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_1_LSB (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_1_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_1_MASK (0x00000FC0)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_0_LSB (0)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_0_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_0_MASK (0x0000003F)
+
+#define DBRP_EVDO_HARQ_DBG_EN_LSB (0)
+#define DBRP_EVDO_HARQ_DBG_EN_WIDTH (1)
+#define DBRP_EVDO_HARQ_DBG_EN_MASK (0x00000001)
+#define DBRP_EVDO_HARQ_DBG_EN_BIT (0x00000001)
+
+#define DBRP_EVDO_C2I_RD_TRG_LSB (0)
+#define DBRP_EVDO_C2I_RD_TRG_WIDTH (1)
+#define DBRP_EVDO_C2I_RD_TRG_MASK (0x00000001)
+#define DBRP_EVDO_C2I_RD_TRG_BIT (0x00000001)
+
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_LSB (15)
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_WIDTH (1)
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_MASK (0x00008000)
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_BIT (0x00008000)
+
+#define DBRP_EVDO_C2I_RD_ADDR_MEM_ADDR_LSB (0)
+#define DBRP_EVDO_C2I_RD_ADDR_MEM_ADDR_WIDTH (6)
+#define DBRP_EVDO_C2I_RD_ADDR_MEM_ADDR_MASK (0x0000003F)
+
+#define DBRP_EVDO_C2I_RD_DATA_MEM_DATA_LSB (0)
+#define DBRP_EVDO_C2I_RD_DATA_MEM_DATA_WIDTH (12)
+#define DBRP_EVDO_C2I_RD_DATA_MEM_DATA_MASK (0x00000FFF)
+
+#define DBRP_EVDO_HARQ_RD_TRG_LSB (0)
+#define DBRP_EVDO_HARQ_RD_TRG_WIDTH (1)
+#define DBRP_EVDO_HARQ_RD_TRG_MASK (0x00000001)
+#define DBRP_EVDO_HARQ_RD_TRG_BIT (0x00000001)
+
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_LSB (15)
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_WIDTH (1)
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_MASK (0x00008000)
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_BIT (0x00008000)
+
+#define DBRP_EVDO_HARQ_RD_ADDR_MEM_ADDR_LSB (0)
+#define DBRP_EVDO_HARQ_RD_ADDR_MEM_ADDR_WIDTH (11)
+#define DBRP_EVDO_HARQ_RD_ADDR_MEM_ADDR_MASK (0x000007FF)
+
+#define DBRP_EVDO_HARQ_RD_DATA_MEM_DATA_LSB (0)
+#define DBRP_EVDO_HARQ_RD_DATA_MEM_DATA_WIDTH (32)
+#define DBRP_EVDO_HARQ_RD_DATA_MEM_DATA_MASK (0xFFFFFFFF)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_3_LSB (24)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_3_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_3_MASK (0x7F000000)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_2_LSB (16)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_2_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_2_MASK (0x007F0000)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_1_LSB (8)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_1_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_1_MASK (0x00007F00)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_0_LSB (0)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_0_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_0_MASK (0x0000007F)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_7_LSB (24)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_7_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_7_MASK (0x7F000000)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_6_LSB (16)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_6_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_6_MASK (0x007F0000)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_5_LSB (8)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_5_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_5_MASK (0x00007F00)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_4_LSB (0)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_4_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_4_MASK (0x0000007F)
+
+#define DBRP_EVDO_DBG0_DET_CHNL_ITER_LSB (12)
+#define DBRP_EVDO_DBG0_DET_CHNL_ITER_WIDTH (2)
+#define DBRP_EVDO_DBG0_DET_CHNL_ITER_MASK (0x00003000)
+
+#define DBRP_EVDO_DBG0_MAIN_FSM_CS_LSB (0)
+#define DBRP_EVDO_DBG0_MAIN_FSM_CS_WIDTH (9)
+#define DBRP_EVDO_DBG0_MAIN_FSM_CS_MASK (0x000001FF)
+
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_LSB (15)
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_WIDTH (1)
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_MASK (0x00008000)
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_BIT (0x00008000)
+#define DBRP_EVDO_HARQ_PARAM_HARQ_BUF_SIZE_LSB (16)
+#define DBRP_EVDO_HARQ_PARAM_HARQ_BUF_SIZE_WIDTH (13)
+#define DBRP_EVDO_HARQ_PARAM_HARQ_BUF_SIZE_MASK (0x1FFF0000)
+
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_LSB (5)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_WIDTH (1)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_MASK (0x00000020)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_BIT (0x00000020)
+
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT1_SIZE_LSB (3)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT1_SIZE_WIDTH (2)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT1_SIZE_MASK (0x00000018)
+
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT0_SIZE_LSB (0)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT0_SIZE_WIDTH (2)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT0_SIZE_MASK (0x00000003)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH0_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH0_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH0_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH0_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH0_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH0_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH0_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH0_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH0_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH0_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH0_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH0_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH1_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH1_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH1_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH1_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH1_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH1_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH1_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH1_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH1_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH1_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH1_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH1_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH2_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH2_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH2_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH2_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH2_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH2_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH2_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH2_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH2_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH2_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH2_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH2_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH3_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH3_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH3_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH3_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH3_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH3_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH3_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH3_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH3_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH3_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH3_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH3_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT1_LSB (16)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT1_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT1_MASK (0x0FFF0000)
+
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT0_LSB (0)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT0_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT0_MASK (0x00000FFF)
+
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT3_LSB (16)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT3_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT3_MASK (0x0FFF0000)
+
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT2_LSB (0)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT2_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT2_MASK (0x00000FFF)
+
+
+#endif //#ifndef _CPH_EVDO_RXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen.h
new file mode 100644
index 0000000..1b6cd4b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphevdorxeventgen_93.h"
+#elif defined(__MD95__)
+#include "cphevdorxeventgen_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphevdorxeventgen_97.h"
+#else
+#error "[ERROR] Invalid MD generation" modification for build error
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_93.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_93.h
new file mode 100644
index 0000000..2d107e7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_93.h
@@ -0,0 +1,587 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_EVENTGEN_H_
+#define _CPH_EVDO_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_EVENTGEN_REG_BASE (0xA7070000)
+#define STDO_RX_EVENTGEN_end (STDO_RX_EVENTGEN_REG_BASE + 0x3000 + 34*4)
+
+
+#define STDO_RXBRP_EVENT_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0000))
+#define STDO_RXBRP_EVENT_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0004))
+#define STDO_uSIP_IRQ_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0008))
+#define STDO_uSIP_IRQ_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x000C))
+#define STDO_uSIP_IRQ_CLR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0010))
+#define STDO_uSIP_IRQ_SRC ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0014))
+#define STDO_uSIP_IRQ_ISR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0018))
+#define STDO_RXDFE_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x001C))
+#define STDO_RXDFE_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0020))
+#define STDO_DBG_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0024))
+#define STDO_DBG_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0028))
+#define STDO_TTR_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x002C))
+#define STDO_TTR_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0030))
+#define STDO_DVFS_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0034))
+#define STDO_RX_BSIRD_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define STDO_RX_BSI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 44
+#define STDO_RX_MIPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 76
+#define STDO_RX_BPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 33
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define STDO_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define STDO_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define STDO_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define STDO_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define STDO_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define STDO_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define STDO_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define STDO_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define STDO_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define STDO_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define STDO_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define STDO_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define STDO_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define STDO_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define STDO_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define STDO_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define STDO_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define STDO_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define STDO_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define STDO_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define STDO_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define STDO_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define STDO_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define STDO_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define STDO_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define STDO_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define STDO_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define STDO_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define STDO_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define STDO_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define STDO_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define STDO_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define STDO_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define STDO_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define STDO_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define STDO_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define STDO_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define STDO_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define STDO_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define STDO_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define STDO_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define STDO_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define STDO_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define STDO_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define STDO_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define STDO_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define STDO_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define STDO_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define STDO_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define STDO_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define STDO_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define STDO_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define STDO_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define STDO_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define STDO_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define STDO_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define STDO_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define STDO_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define STDO_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define STDO_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define STDO_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define STDO_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define STDO_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define STDO_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define STDO_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define STDO_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define STDO_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define STDO_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define STDO_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define STDO_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define STDO_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define STDO_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define STDO_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define STDO_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define STDO_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define STDO_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define STDO_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define STDO_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define STDO_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define STDO_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define STDO_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define STDO_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define STDO_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define STDO_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define STDO_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define STDO_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define STDO_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define STDO_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define STDO_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define STDO_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define STDO_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define STDO_RXDFE_ON_EVENT_EN_LSB (31)
+#define STDO_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RXDFE_OFF_EVENT_EN_LSB (31)
+#define STDO_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DBG_ON_EVENT_EN_LSB (31)
+#define STDO_DBG_ON_EVENT_EN_WIDTH (1)
+#define STDO_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_DBG_OFF_EVENT_EN_LSB (31)
+#define STDO_DBG_OFF_EVENT_EN_WIDTH (1)
+#define STDO_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_TTR_ON_EVENT_EN_LSB (31)
+#define STDO_TTR_ON_EVENT_EN_WIDTH (1)
+#define STDO_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_TTR_OFF_EVENT_EN_LSB (31)
+#define STDO_TTR_OFF_EVENT_EN_WIDTH (1)
+#define STDO_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DVFS_EVENT_EN_LSB (31)
+#define STDO_DVFS_EVENT_EN_WIDTH (1)
+#define STDO_DVFS_EVENT_EN_MASK (0x80000000)
+#define STDO_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DVFS_EVENT_MODE_LSB (30)
+#define STDO_DVFS_EVENT_MODE_WIDTH (1)
+#define STDO_DVFS_EVENT_MODE_MASK (0x40000000)
+#define STDO_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSIRD_EVENT_EN_LSB (31)
+#define STDO_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSI_EVENT_EN_LSB (31)
+#define STDO_RX_BSI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_MIPI_EVENT_EN_LSB (31)
+#define STDO_RX_MIPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BPI_EVENT_EN_LSB (31)
+#define STDO_RX_BPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_EVDO_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_95.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_95.h
new file mode 100644
index 0000000..17cfaf1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_95.h
@@ -0,0 +1,587 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_EVENTGEN_H_
+#define _CPH_EVDO_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_EVENTGEN_REG_BASE (0xA6220000)
+#define STDO_RX_EVENTGEN_end (STDO_RX_EVENTGEN_REG_BASE + 0x0130 + 1*4)
+
+
+#define STDO_RXBRP_EVENT_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0000))
+#define STDO_RXBRP_EVENT_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0004))
+#define STDO_uSIP_IRQ_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0008))
+#define STDO_uSIP_IRQ_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x000C))
+#define STDO_uSIP_IRQ_CLR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0010))
+#define STDO_uSIP_IRQ_SRC ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0014))
+#define STDO_uSIP_IRQ_ISR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0018))
+#define STDO_RXDFE_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x001C))
+#define STDO_RXDFE_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0020))
+#define STDO_DBG_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0024))
+#define STDO_DBG_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0028))
+#define STDO_TTR_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x002C))
+#define STDO_TTR_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0030))
+#define STDO_DVFS_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0034))
+#define STDO_RX_BSIRD_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define STDO_RX_BSI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 44
+#define STDO_RX_MIPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 76
+#define STDO_RX_BPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 33
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define STDO_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define STDO_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define STDO_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define STDO_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define STDO_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define STDO_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define STDO_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define STDO_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define STDO_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define STDO_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define STDO_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define STDO_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define STDO_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define STDO_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define STDO_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define STDO_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define STDO_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define STDO_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define STDO_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define STDO_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define STDO_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define STDO_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define STDO_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define STDO_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define STDO_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define STDO_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define STDO_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define STDO_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define STDO_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define STDO_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define STDO_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define STDO_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define STDO_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define STDO_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define STDO_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define STDO_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define STDO_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define STDO_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define STDO_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define STDO_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define STDO_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define STDO_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define STDO_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define STDO_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define STDO_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define STDO_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define STDO_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define STDO_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define STDO_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define STDO_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define STDO_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define STDO_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define STDO_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define STDO_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define STDO_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define STDO_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define STDO_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define STDO_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define STDO_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define STDO_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define STDO_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define STDO_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define STDO_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define STDO_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define STDO_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define STDO_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define STDO_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define STDO_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define STDO_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define STDO_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define STDO_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define STDO_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define STDO_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define STDO_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define STDO_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define STDO_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define STDO_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define STDO_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define STDO_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define STDO_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define STDO_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define STDO_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define STDO_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define STDO_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define STDO_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define STDO_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define STDO_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define STDO_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define STDO_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define STDO_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define STDO_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define STDO_RXDFE_ON_EVENT_EN_LSB (31)
+#define STDO_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RXDFE_OFF_EVENT_EN_LSB (31)
+#define STDO_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DBG_ON_EVENT_EN_LSB (31)
+#define STDO_DBG_ON_EVENT_EN_WIDTH (1)
+#define STDO_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_DBG_OFF_EVENT_EN_LSB (31)
+#define STDO_DBG_OFF_EVENT_EN_WIDTH (1)
+#define STDO_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_TTR_ON_EVENT_EN_LSB (31)
+#define STDO_TTR_ON_EVENT_EN_WIDTH (1)
+#define STDO_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_TTR_OFF_EVENT_EN_LSB (31)
+#define STDO_TTR_OFF_EVENT_EN_WIDTH (1)
+#define STDO_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DVFS_EVENT_EN_LSB (31)
+#define STDO_DVFS_EVENT_EN_WIDTH (1)
+#define STDO_DVFS_EVENT_EN_MASK (0x80000000)
+#define STDO_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DVFS_EVENT_MODE_LSB (30)
+#define STDO_DVFS_EVENT_MODE_WIDTH (1)
+#define STDO_DVFS_EVENT_MODE_MASK (0x40000000)
+#define STDO_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSIRD_EVENT_EN_LSB (31)
+#define STDO_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSI_EVENT_EN_LSB (31)
+#define STDO_RX_BSI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_MIPI_EVENT_EN_LSB (31)
+#define STDO_RX_MIPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BPI_EVENT_EN_LSB (31)
+#define STDO_RX_BPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_EVDO_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_97.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_97.h
new file mode 100644
index 0000000..1899a14
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_97.h
@@ -0,0 +1,369 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_EVENTGEN_H_
+#define _CPH_EVDO_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_EVENTGEN_REG_BASE (0xA8210000)
+
+
+#define STDO_RX_EVENTGEN_end (STDO_RX_EVENTGEN_REG_BASE + 0x0100 + 1*4)
+
+
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0000))
+#define STDO_RXBRP_EVENT_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0004))
+#define STDO_RXDFE_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x001C))
+#define STDO_RXDFE_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0020))
+#define STDO_DBG_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0024))
+#define STDO_DBG_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0028))
+#define STDO_TTR_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x002C))
+#define STDO_TTR_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0030))
+#define STDO_DVFS_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0034))
+#define STDO_WDG_EN ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0040))
+#define STDO_WDG_BOUND_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0044))
+#define STDO_WDG_CHKPT_UNCHK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0048))
+#define STDO_WDG_CHKPT_TIME_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x004C))
+#define STDO_WDG_URGENT_SW_CLR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0060))
+#define STDO_WDG_DBG ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0064))
+#define STDO_uSIP_IRQ_OFFSET_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0080))
+#define STDO_uSIP_IRQ_MASK_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0084))
+#define STDO_uSIP_IRQ_CLR_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0088))
+#define STDO_uSIP_IRQ_SRC_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x008C))
+#define STDO_uSIP_IRQ_ISR_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0090))
+#define STDO_uSIP_IRQ_OFFSET_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00A0))
+#define STDO_uSIP_IRQ_MASK_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00A4))
+#define STDO_uSIP_IRQ_CLR_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00A8))
+#define STDO_uSIP_IRQ_SRC_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00AC))
+#define STDO_uSIP_IRQ_ISR_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00B0))
+#define STDO_uSIP_IRQ_OFFSET_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00C0))
+#define STDO_uSIP_IRQ_MASK_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00C4))
+#define STDO_uSIP_IRQ_CLR_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00C8))
+#define STDO_uSIP_IRQ_SRC_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00CC))
+#define STDO_uSIP_IRQ_ISR_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00D0))
+#define STDO_uSIP_IRQ_OFFSET_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00E0))
+#define STDO_uSIP_IRQ_MASK_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00E4))
+#define STDO_uSIP_IRQ_CLR_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00E8))
+#define STDO_uSIP_IRQ_SRC_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00EC))
+#define STDO_uSIP_IRQ_ISR_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00F0))
+#define STDO_uSIP_IRQ_STATUS ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0100))
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define STDO_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define STDO_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define STDO_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define STDO_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define STDO_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define STDO_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define STDO_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define STDO_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define STDO_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define STDO_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define STDO_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define STDO_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define STDO_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define STDO_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define STDO_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define STDO_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define STDO_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define STDO_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define STDO_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define STDO_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define STDO_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define STDO_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define STDO_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define STDO_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define STDO_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define STDO_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define STDO_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define STDO_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define STDO_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define STDO_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define STDO_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_RXDFE_ON_EVENT_EN_LSB (31)
+#define STDO_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RXDFE_OFF_EVENT_EN_LSB (31)
+#define STDO_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DBG_ON_EVENT_EN_LSB (31)
+#define STDO_DBG_ON_EVENT_EN_WIDTH (1)
+#define STDO_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_DBG_OFF_EVENT_EN_LSB (31)
+#define STDO_DBG_OFF_EVENT_EN_WIDTH (1)
+#define STDO_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_TTR_ON_EVENT_EN_LSB (31)
+#define STDO_TTR_ON_EVENT_EN_WIDTH (1)
+#define STDO_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_TTR_OFF_EVENT_EN_LSB (31)
+#define STDO_TTR_OFF_EVENT_EN_WIDTH (1)
+#define STDO_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DVFS_EVENT_EN_LSB (31)
+#define STDO_DVFS_EVENT_EN_WIDTH (1)
+#define STDO_DVFS_EVENT_EN_MASK (0x80000000)
+#define STDO_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DVFS_EVENT_MODE_LSB (30)
+#define STDO_DVFS_EVENT_MODE_WIDTH (1)
+#define STDO_DVFS_EVENT_MODE_MASK (0x40000000)
+#define STDO_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_WDG_EN_WDG_EN_LSB (0)
+#define STDO_WDG_EN_WDG_EN_WIDTH (1)
+#define STDO_WDG_EN_WDG_EN_MASK (0x00000001)
+#define STDO_WDG_EN_WDG_EN_BIT (0x00000001)
+
+#define STDO_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_LSB (3)
+#define STDO_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_WIDTH (11)
+#define STDO_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_MASK (0x00003FF8)
+
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_LSB (0)
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_WIDTH (1)
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_MASK (0x00000001)
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_BIT (0x00000001)
+
+#define STDO_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_LSB (3)
+#define STDO_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_WIDTH (17)
+#define STDO_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_MASK (0x000FFFF8)
+
+#define STDO_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_0_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_0_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_0_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_0_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_0_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_0_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_0_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_0_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_0_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_0_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_0_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_0_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_1_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_1_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_1_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_1_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_1_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_1_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_1_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_1_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_1_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_1_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_1_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_1_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_2_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_2_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_2_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_2_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_2_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_2_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_2_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_2_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_2_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_2_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_2_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_2_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_3_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_3_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_3_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_3_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_3_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_3_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_3_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_3_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_3_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_3_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_3_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_3_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_LSB (3)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_LSB (2)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_LSB (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_LSB (0)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_EVDO_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxslp.h b/mcu/interface/l1/cl1/common/HW/cphevdorxslp.h
new file mode 100644
index 0000000..3dcbd76
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxslp.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_SLP_H_
+#define _CPH_EVDO_RX_SLP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_SLP_REG_BASE (0x00000000)
+
+#define STDO_RX_SLP_end (STDO_RX_SLP_REG_BASE + 0xA60F0060 + 1*4)
+
+
+
+#define STDO_SM_CON ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0000))
+#define STDO_SM_PAUSE_TIME ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0004))
+#define STDO_SM_STA ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0008))
+#define STDO_SM_CFG ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F000C))
+#define STDO_SM_START_TIME ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0010))
+#define STDO_SM_SW_WAKE_CON ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0014))
+#define STDO_SM_STEP_FRAC ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0018))
+#define STDO_SM_SYSCNT_F32K_INT ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F001C))
+#define STDO_SM_SYSCNT_F32K_FRAC ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0020))
+#define STDO_SM_SUPFRM_F32K_L ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0024))
+#define STDO_SM_SUPFRM_F32K_H ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0028))
+#define STDO_SM_SLEEP_OFFSET ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F002C))
+#define STDO_SM_TIME_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0030))
+#define STDO_SM_SUPFRM_TIME_L_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0034))
+#define STDO_SM_SUPFRM_TIME_H_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0038))
+#define STDO_SM_TIME_SLTBD ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F003C))
+#define STDO_SM_SUPFRM_TIME_L_SLTBD ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0040))
+#define STDO_SM_SUPFRM_TIME_H_SLTBD ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0044))
+#define STDO_SM_TIME_WAKEUP_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0048))
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F004C))
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0050))
+#define STDO_SM_FINAL_PAUSE_DURATION ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0054))
+#define STDO_SM_PRESLP_CNT ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0058))
+#define STDO_SM_SLT_START_F32K ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F005C))
+#define STDO_SM_WAKEUP_START_F32K ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0060))
+
+
+#define STDO_SM_CON_CLR_CNT_LSB (15)
+#define STDO_SM_CON_CLR_CNT_WIDTH (1)
+#define STDO_SM_CON_CLR_CNT_MASK (0x00008000)
+#define STDO_SM_CON_CLR_CNT_BIT (0x00008000)
+
+#define STDO_SM_CON_PAUSE_START_LSB (1)
+#define STDO_SM_CON_PAUSE_START_WIDTH (1)
+#define STDO_SM_CON_PAUSE_START_MASK (0x00000002)
+#define STDO_SM_CON_PAUSE_START_BIT (0x00000002)
+
+#define STDO_SM_CON_PAUSE_MODE_LSB (0)
+#define STDO_SM_CON_PAUSE_MODE_WIDTH (1)
+#define STDO_SM_CON_PAUSE_MODE_MASK (0x00000001)
+#define STDO_SM_CON_PAUSE_MODE_BIT (0x00000001)
+
+#define STDO_SM_PAUSE_TIME_PAUSE_TIME_LSB (0)
+#define STDO_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32)
+#define STDO_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF)
+
+#define STDO_SM_STA_SLP_EXIT_CPL_LSB (7)
+#define STDO_SM_STA_SLP_EXIT_CPL_WIDTH (1)
+#define STDO_SM_STA_SLP_EXIT_CPL_MASK (0x00000080)
+#define STDO_SM_STA_SLP_EXIT_CPL_BIT (0x00000080)
+
+#define STDO_SM_STA_PAUSE_CPL_LSB (6)
+#define STDO_SM_STA_PAUSE_CPL_WIDTH (1)
+#define STDO_SM_STA_PAUSE_CPL_MASK (0x00000040)
+#define STDO_SM_STA_PAUSE_CPL_BIT (0x00000040)
+
+#define STDO_SM_CFG_SW_WAKE_EN_LSB (8)
+#define STDO_SM_CFG_SW_WAKE_EN_WIDTH (1)
+#define STDO_SM_CFG_SW_WAKE_EN_MASK (0x00000100)
+#define STDO_SM_CFG_SW_WAKE_EN_BIT (0x00000100)
+
+#define STDO_SM_CFG_IRQ_EN_LSB (1)
+#define STDO_SM_CFG_IRQ_EN_WIDTH (1)
+#define STDO_SM_CFG_IRQ_EN_MASK (0x00000002)
+#define STDO_SM_CFG_IRQ_EN_BIT (0x00000002)
+
+#define STDO_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define STDO_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define STDO_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_LSB (0)
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1)
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001)
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001)
+
+#define STDO_SM_STEP_FRAC_STEP_INT_LSB (18)
+#define STDO_SM_STEP_FRAC_STEP_INT_WIDTH (9)
+#define STDO_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000)
+
+#define STDO_SM_STEP_FRAC_STEP_FRAC_LSB (0)
+#define STDO_SM_STEP_FRAC_STEP_FRAC_WIDTH (18)
+#define STDO_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF)
+
+#define STDO_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0)
+#define STDO_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20)
+#define STDO_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF)
+
+#define STDO_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0)
+#define STDO_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18)
+#define STDO_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF)
+
+#define STDO_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0)
+#define STDO_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32)
+#define STDO_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0)
+#define STDO_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4)
+#define STDO_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F)
+
+#define STDO_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14)
+#define STDO_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC)
+
+#define STDO_SM_TIME_START_SM_TIME_START_LSB (0)
+#define STDO_SM_TIME_START_SM_TIME_START_WIDTH (20)
+#define STDO_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF)
+
+#define STDO_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32)
+#define STDO_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4)
+#define STDO_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F)
+
+#define STDO_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0)
+#define STDO_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20)
+#define STDO_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF)
+
+#define STDO_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define STDO_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32)
+#define STDO_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define STDO_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4)
+#define STDO_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F)
+
+#define STDO_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0)
+#define STDO_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20)
+#define STDO_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF)
+
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32)
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4)
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F)
+
+#define STDO_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0)
+#define STDO_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32)
+#define STDO_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF)
+
+#define STDO_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0)
+#define STDO_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6)
+#define STDO_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F)
+
+#define STDO_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0)
+#define STDO_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6)
+#define STDO_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F)
+
+#define STDO_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0)
+#define STDO_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32)
+#define STDO_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_EVDO_RX_SLP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg.h
new file mode 100644
index 0000000..736a8d5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphevdoschreg_93.h"
+#elif defined(__MD95__)
+#include "cphevdoschreg_95.h"
+#else
+#include "cphevdoschreg_97.h"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg_93.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_93.h
new file mode 100644
index 0000000..a40b930
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_93.h
@@ -0,0 +1,591 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_SCH_H_
+#define _CPH_EVDO_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_CDO_REG_BASE (0xA7850000)
+
+#define CS_CDO_end (CS_CDO_REG_BASE + 0x0800 + 1*4)
+
+
+
+#define SRDO_START ((APBADDR32)(CS_CDO_REG_BASE + 0x0000))
+#define SRDO_PAUSE ((APBADDR32)(CS_CDO_REG_BASE + 0x0004))
+#define SRDO_RST ((APBADDR32)(CS_CDO_REG_BASE + 0x0008))
+#define SRDO_INBUF_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x000C))
+#define SRDO_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0010))
+#define SRDO_MEM_SEL ((APBADDR32)(CS_CDO_REG_BASE + 0x0014))
+#define SRDO_GENSTAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0018))
+#define SRDO_GENSTAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x001C))
+#define SRDO_PATHMAINT ((APBADDR32)(CS_CDO_REG_BASE + 0x0020))
+#define SRDO_INBUF_ADR ((APBADDR32)(CS_CDO_REG_BASE + 0x0024))
+#define SRDO_INBUF_DAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0028))
+#define SRDO_STATUS0 ((APBADDR32)(CS_CDO_REG_BASE + 0x002C))
+#define SRDO_PLTINFO_CLR0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0030))
+#define SRDO_PLTINFO_CLR1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0034))
+#define SRDO_PATHINFO_CLR ((APBADDR32)(CS_CDO_REG_BASE + 0x0038))
+#define SRDO_ACQ_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x003C))
+#define SRDO_TSTCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0040))
+#define SRDO_CLKCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0048))
+#define SRDO_STATUS1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0050))
+#define SRDO_INBUF_DAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0054))
+#define SRDO_FNDO_MEMCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0058))
+#define SRDO_THRESH ((APBADDR32)(CS_CDO_REG_BASE + 0x005C))
+#define SRDO_TST_DBG ((APBADDR32)(CS_CDO_REG_BASE + 0x0060))
+#define SRDO_DONE ((APBADDR32)(CS_CDO_REG_BASE + 0x0064))
+#define SRDO_PATHINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0080))
+#define SRDO_PLTLIST ((APBADDR32)(CS_CDO_REG_BASE + 0x0100))
+#define SRDO_PLTINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0200))
+#define SRDO_PATHBUF ((APBADDR32)(CS_CDO_REG_BASE + 0x0800))
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*HWD_SRDO_START*/
+#define START_START_SHIFT 0 /* [0] */
+#define START_SRDO_START_DLY_EN_SHIFT 1 /* [1] */
+#define START_SRDO_START_DLY_CNT_SHIFT 2 /* [21:2] */
+
+#define START_START_MASK 0x00000001 << START_START_SHIFT
+#define START_SRDO_START_DLY_EN_MASK 0x00000001 << START_SRDO_START_DLY_EN_SHIFT
+#define START_SRDO_START_DLY_CNT_MASK 0x000FFFFF << START_SRDO_START_DLY_CNT_SHIFT
+
+
+/*HWD_SRDO_PAUSE*/
+#define PAUSE_PAUSE_SHIFT 0 /* [0] */
+#define PAUSE_PAUSE_MASK 0x00000001 << PAUSE_PAUSE_SHIFT
+
+/*HWD_SRDO_RST*/
+#define RST_RST_SHIFT 0 /* [0] */
+#define RST_RST_MASK 0x00000001 << RST_RST_SHIFT
+
+/*HWD_SRDO_INBUF_CTL*/
+#define INBUF_CTL_ANTENNA_INIT_EN_SHIFT 19 /* [19] */
+#define INBUF_CTL_ANTENNA_INIT_SHIFT 18 /* [18] */
+#define INBUF_CTL_IIR_A_IB_SHIFT 16 /* [17:16] */
+#define INBUF_CTL_DUAL_SHIFT 15 /* [15] */
+#define INBUF_CTL_BURST_SHIFT 14 /* [14] */
+#define INBUF_CTL_ANT_MODE_SHIFT 12 /* [13:12] */
+#define INBUF_CTL_CAPTURE_SHIFT 11 /* [11] */
+#define INBUF_CTL_CAPLEN_SHIFT 8 /* [10:8] */
+#define INBUF_CTL_BUFFCAPT_SHIFT 4 /* [7:4] */
+#define INBUF_CTL_BUFFCAPINT_SHIFT 0 /* [3:0] */
+
+#define INBUF_ANTENNA_INIT_EN_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_EN_SHIFT
+#define INBUF_ANTENNA_INIT_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_SHIFT
+#define INBUF_CTL_IIR_A_IB_MASK 0x00000003 << INBUF_CTL_IIR_A_IB_SHIFT
+#define INBUF_CTL_DUAL_MASK 0x00000001 << INBUF_CTL_DUAL_SHIFT
+#define INBUF_CTL_BURST_MASK 0x00000001 << INBUF_CTL_BURST_SHIFT
+#define INBUF_CTL_ANT_MODE_MASK 0x00000003 << INBUF_CTL_ANT_MODE_SHIFT
+#define INBUF_CTL_CAPTURE_MASK 0x00000001 << INBUF_CTL_CAPTURE_SHIFT
+#define INBUF_CTL_CAPLEN_MASK 0x00000007 << INBUF_CTL_CAPLEN_SHIFT
+#define INBUF_CTL_BUFFCAPT_MASK 0x0000000f << INBUF_CTL_BUFFCAPT_SHIFT
+#define INBUF_CTL_BUFFCAPINT_MASK 0x0000000f << INBUF_CTL_BUFFCAPINT_SHIFT
+
+
+/*HWD_SRDO_CTL*/
+#define CTL_CLEAR_SHIFT 9 /* [9] */
+#define CTL_ACQMODE_SHIFT 8 /* [8] */
+#define CTL_SEARCH_SET_SHIFT 6 /* [7:6] */
+#define CTL_SEARCH_N_SHIFT 0 /* [5:0] */
+
+#define CTL_CLEAR_MASK 0x00000001 << CTL_CLEAR_SHIFT
+#define CTL_ACQMODE_MASK 0x00000001 << CTL_ACQMODE_SHIFT
+#define CTL_SEARCH_SET_MASK 0x00000003 << CTL_SEARCH_SET_SHIFT
+#define CTL_SEARCH_N_MASK 0x0000003f << CTL_SEARCH_N_SHIFT
+
+/*HWD_SRDO_GENSTAT0*/
+#define GENSTAT0_COHLEN_SHIFT 17 /* [18:17] */
+#define GENSTAT0_PASSCNT1_SHIFT 12 /* [16:12] */
+#define GENSTAT0_PASSCNT2_SHIFT 6 /* [11:6] */
+#define GENSTAT0_SHIFT1_SHIFT 3 /* [5:3] */
+#define GENSTAT0_SHIFT2_SHIFT 0 /* [2:0] */
+
+#define GENSTAT0_COHLEN_MASK 0x00000003 << GENSTAT0_COHLEN_SHIFT
+#define GENSTAT0_PASSCNT1_MASK 0x0000001f << GENSTAT0_PASSCNT1_SHIFT
+#define GENSTAT0_PASSCNT2_MASK 0x0000003f << GENSTAT0_PASSCNT2_SHIFT
+#define GENSTAT0_SHIFT1_MASK 0x00000007 << GENSTAT0_SHIFT1_SHIFT
+#define GENSTAT0_SHIFT2_MASK 0x00000007 << GENSTAT0_SHIFT2_SHIFT
+
+/*HWD_SRDO_GENSTAT1*/
+#define GENSTAT1_THRESH1M_SHIFT 8 /* [15:8] */
+#define GENSTAT1_THRESH2M_SHIFT 0 /* [7:0] */
+#define GENSTAT1_THRESH1M_MASK 0x000000ff << GENSTAT1_THRESH1M_SHIFT
+#define GENSTAT1_THRESH2M_MASK 0x000000ff << GENSTAT1_THRESH2M_SHIFT
+
+/*HWD_SRDO_PATHMAINT*/
+#define PATHMAINT_PATHMAINT_MODE_SHIFT 3 /* [3] */
+#define PATHMAINT_CLR_NUMSEARCH_SHIFT 2 /* [2] */
+#define PATHMAINT_IIR_A_SHIFT 0 /* [1:0] */
+#define PATHMAINT_PATHMAINT_MODE_MASK 0x00000001 << PATHMAINT_PATHMAINT_MODE_SHIFT
+#define PATHMAINT_CLR_NUMSEARCH_MASK 0x00000001 << PATHMAINT_CLR_NUMSEARCH_SHIFT
+#define PATHMAINT_IIR_A_MASK 0x00000003 << PATHMAINT_IIR_A_SHIFT
+
+/*HWD_SRDO_INBUF0_ADR*/
+#define INBUF_ADR_INBUF_ADR_SHIFT 0 /* [13:0] */
+#define INBUF_ADR_INBUF_ADR_MASK 0x00003fff << INBUF_ADR_INBUF_ADR_SHIFT
+
+/*HWD_SRDO_INBUF_DAT*/
+#define INBUF_DAT_INBUF_DAT0_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT0_MASK 0x000fffff << INBUF_DAT_INBUF_DAT0_SHIFT
+
+/*HWD_SRDO_INBUF_DAT1*/
+#define INBUF_DAT_INBUF_DAT1_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT1_MASK 0x000fffff << INBUF_DAT_INBUF_DAT1_SHIFT
+
+
+/*HWD_SRDO_STATUS0*/
+#define STATUS0_ANTENNA_SHIFT 24 /* [24] */
+#define STATUS0_BUSY_SHIFT 23 /* [23] */
+#define STATUS0_INMAG_INST_SHIFT 15 /* [22:15] */
+#define STATUS0_INMAG_IIR_SHIFT 7 /* [14:7] */
+#define STATUS0_BUFCAPTMHS_SHIFT 0 /* [6:0] */
+
+#define STATUS0_ANTENNA_MASK 0x00000001 << STATUS0_ANTENNA_SHIFT
+#define STATUS0_BUSY_MASK 0x00000001 << STATUS0_BUSY_SHIFT
+#define STATUS0_INMAG_INST_MASK 0x000000ff << STATUS0_INMAG_INST_SHIFT
+#define STATUS0_INMAG_IIR_MASK 0x000000ff << STATUS0_INMAG_IIR_SHIFT
+#define STATUS0_BUFCAPTMHS_MASK 0x0000007f << STATUS0_BUFCAPTMHS_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR1*/
+#define PLTINFO_CLR1_CLR_SHIFT 0 /* [23:0] */
+#define PLTINFO_CLR1_CLR_MASK 0x00ffffff << PLTINFO_CLR1_CLR_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR0*/
+#define PLTINFO_CLR0_CLR_SHIFT 0 /* [31:0] */
+#define PLTINFO_CLR0_CLR_MASK 0xffffffff << PLTINFO_CLR0_CLR_SHIFT
+
+/*HWD_SRDO_PATHINFO_CLR*/
+#define PATHINFO_CLR_CLR_SHIFT 0 /* [19:0] */
+#define PATHINFO_CLR_CLR_MASK 0x000fffff << PATHINFO_CLR_CLR_SHIFT
+
+/*HWD_SRDO_ACQ_CTL*/
+#define ACQ_CTL_ACQ_WIN_SHIFT 11 /* [20:11] */
+#define ACQ_CTL_ACQ_OFFSET_SHIFT 0 /* [10:0] */
+#define ACQ_CTL_ACQ_WIN_MASK 0x000003ff << ACQ_CTL_ACQ_WIN_SHIFT
+#define ACQ_CTL_ACQ_OFFSET_MASK 0x000007ff << ACQ_CTL_ACQ_OFFSET_SHIFT
+
+/*HWD_SRDO_TSTCTL*/
+#define TSTCTL_INBUF_TST_MODE_SHIFT 0 /* [0] */
+#define TSTCTL_INBUF_TST_MODE_MASK 1 << TSTCTL_INBUF_TST_MODE_SHIFT
+
+/*HWD_SRDO_STATUS1, NOTE: start from bit 7*/
+#define STATUS1_INMAG_INST1_SHIFT 15 /* [22:15] */
+#define STATUS1_INMAG_IIR1_SHIFT 7 /* [14:7] */
+#define STATUS1_INMAG_INST1_MASK 0x000000ff << STATUS1_INMAG_INST1_SHIFT
+#define STATUS1_INMAG_IIR1_MASK 0x000000ff << STATUS1_INMAG_IIR1_SHIFT
+
+
+/*HWD_SRDO_TSTSEL*/
+#define TSTSEL_TST_SEL_SHIFT 0 /* [7:0] */
+#define TSTSEL_TST_SEL_MASK 0x000000ff << TSTSEL_TST_SEL_SHIFT
+
+/*HWD_SRDO_PATHINFO*/
+#define PATHINFO_MAX 20
+#define PATHINFO_LEN 4 /* byte */
+
+#define PATHINFO_ENABLE_SHIFT 22 /* [22] */
+#define PATHINFO_KEEP_SHIFT 21 /* [21] */
+#define PATHINFO_WIN_SHIFT 17 /* [20:17] */
+#define PATHINFO_PILOTPNNUM_SHIFT 8 /* [16:8] */
+#define PATHINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PATHINFO_ENABLE_MASK 0x00000001 << PATHINFO_ENABLE_SHIFT
+#define PATHINFO_KEEP_MASK 0x00000001 << PATHINFO_KEEP_SHIFT
+#define PATHINFO_WIN_MASK 0x0000000f << PATHINFO_WIN_SHIFT
+#define PATHINFO_PILOTPNNUM_MASK 0x000001ff << PATHINFO_PILOTPNNUM_SHIFT
+#define PATHINFO_SUMMAG_MASK 0x00000ff << PATHINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PLTLIST*/
+#define PLTLIST_MAX 56
+#define PLTLIST_LEN 4 /* byte */
+#define PLTLIST_ENABLE_SHIFT 26 /* [26] */
+#define PLTLIST_KEEP_SHIFT 25 /* [25] */
+#define PLTLIST_WIN_SHIFT 21 /* [24:21] */
+#define PLTLIST_ALWAYS_SEARCH_SHIFT 20 /* [20] */
+#define PLTLIST_PILOT_PN_SHIFT 11 /* [19:11] */
+#define PLTLIST_OFFSET_SHIFT 0 /* [10:0] */
+#define PLTLIST_WIN_MASK 0x0000000f << PLTLIST_WIN_SHIFT
+#define PLTLIST_ALWAYS_SEARCH_MASK 0x00000001 << PLTLIST_ALWAYS_SEARCH_SHIFT
+#define PLTLIST_PILOT_PN_MASK 0x000001ff << PLTLIST_PILOT_PN_SHIFT
+#define PLTLIST_OFFSET_MASK 0x000007ff << PLTLIST_OFFSET_SHIFT
+
+/*HWD_SRDO_PLTINFO*/
+#define PLTINFO_MAX 56
+#define PLTINFO_LEN 4 /* byte */
+#define PLTINFO_NUMSEARCH_SHIFT 8 /* [11:8] */
+#define PLTINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PLTINFO_NUMSEARCH_MASK 0x0000000f << PLTINFO_NUMSEARCH_SHIFT
+#define PLTINFO_SUMMAG_MASK 0x000000ff << PLTINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PATHBUF*/
+#define PATHBUF_MAX 16 /* total 16 path for each path ( 20 ) */
+#define PATHBUF_LEN 4 /* byte */
+#define PATHBUF_PATH_VALID_SHIFT 24 /* [24] */
+#define PATHBUF_NUMAVG_SHIFT 21 /* [23:21] */
+#define PATHBUF_ANTENNA_SHIFT 20 /* [20] */
+#define PATHBUF_OFFSET_SHIFT 8 /* [19:8] */
+#define PATHBUF_STAT_SHIFT 0 /* [7:0] */
+#define PATHBUF_PATH_VALID_MASK 0x00000001 << PATHBUF_PATH_VALID_SHIFT
+#define PATHBUF_NUMAVG_MASK 0x00000007 << PATHBUF_NUMAVG_SHIFT
+#define PATHBUF_ANTENNA_MASK 0x00000001 << PATHBUF_ANTENNA_SHIFT
+#define PATHBUF_OFFSET_MASK 0x00000fff << PATHBUF_OFFSET_SHIFT
+#define PATHBUF_STAT_MASK 0x000000ff << PATHBUF_STAT_SHIFT
+
+/*HWD_SRDO_CLKCTL*/
+#define CLKCTL_CLK_MODE_SHIFT 1 /* [1] */
+#define CLKCTL_CLKENB_SHIFT 0 /* [0] */
+#define CLKCTL_CLK_MODE_MASK (0x1 << CLKCTL_CLK_MODE_SHIFT)
+#define CLKCTL_CLKENB_MASK (0x1 << CLKCTL_CLKENB_SHIFT)
+
+/*SRDO_DONE*/
+#define SRDO_DONE_DONE_SHIFT 0
+#define SRDO_DONE_DONE_MASK 0x00000001 << SRDO_DONE_DONE_SHIFT
+
+#endif //#ifndef _CPH_EVDO_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg_95.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_95.h
new file mode 100644
index 0000000..b84391a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_95.h
@@ -0,0 +1,599 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_SCH_H_
+#define _CPH_EVDO_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_CDO_REG_BASE (0xA7880000)
+
+#define CS_CDO_end (CS_CDO_REG_BASE + 0x0800 + 1*4)
+
+
+
+#define SRDO_START ((APBADDR32)(CS_CDO_REG_BASE + 0x0000))
+#define SRDO_PAUSE ((APBADDR32)(CS_CDO_REG_BASE + 0x0004))
+#define SRDO_RST ((APBADDR32)(CS_CDO_REG_BASE + 0x0008))
+#define SRDO_INBUF_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x000C))
+#define SRDO_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0010))
+#define SRDO_MEM_SEL ((APBADDR32)(CS_CDO_REG_BASE + 0x0014))
+#define SRDO_GENSTAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0018))
+#define SRDO_GENSTAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x001C))
+#define SRDO_PATHMAINT ((APBADDR32)(CS_CDO_REG_BASE + 0x0020))
+#define SRDO_INBUF_ADR ((APBADDR32)(CS_CDO_REG_BASE + 0x0024))
+#define SRDO_INBUF_DAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0028))
+#define SRDO_STATUS0 ((APBADDR32)(CS_CDO_REG_BASE + 0x002C))
+#define SRDO_PLTINFO_CLR0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0030))
+#define SRDO_PLTINFO_CLR1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0034))
+#define SRDO_PATHINFO_CLR ((APBADDR32)(CS_CDO_REG_BASE + 0x0038))
+#define SRDO_ACQ_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x003C))
+#define SRDO_TSTCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0040))
+#define SRDO_CLKCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0048))
+#define SRDO_STATUS1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0050))
+#define SRDO_INBUF_DAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0054))
+#define SRDO_FNDO_MEMCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0058))
+#define SRDO_THRESH ((APBADDR32)(CS_CDO_REG_BASE + 0x005C))
+#define SRDO_TST_DBG ((APBADDR32)(CS_CDO_REG_BASE + 0x0060))
+#define SRDO_DONE ((APBADDR32)(CS_CDO_REG_BASE + 0x0064))
+#define SRDO_PATHINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0080))
+#define SRDO_PLTLIST ((APBADDR32)(CS_CDO_REG_BASE + 0x0100))
+#define SRDO_PLTINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0200))
+#define SRDO_PATHBUF ((APBADDR32)(CS_CDO_REG_BASE + 0x0800))
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*HWD_SRDO_START*/
+#define START_START_SHIFT 0 /* [0] */
+#define START_SRDO_START_DLY_EN_SHIFT 1 /* [1] */
+#define START_SRDO_START_DLY_CNT_SHIFT 2 /* [21:2] */
+
+#define START_START_MASK 0x00000001 << START_START_SHIFT
+#define START_SRDO_START_DLY_EN_MASK 0x00000001 << START_SRDO_START_DLY_EN_SHIFT
+#define START_SRDO_START_DLY_CNT_MASK 0x000FFFFF << START_SRDO_START_DLY_CNT_SHIFT
+
+
+/*HWD_SRDO_PAUSE*/
+#define PAUSE_PAUSE_SHIFT 0 /* [0] */
+#define PAUSE_PAUSE_MASK 0x00000001 << PAUSE_PAUSE_SHIFT
+
+/*HWD_SRDO_RST*/
+#define RST_RST_SHIFT 0 /* [0] */
+#define RST_RST_MASK 0x00000001 << RST_RST_SHIFT
+
+/*HWD_SRDO_INBUF_CTL*/
+#define INBUF_CTL_ANTENNA_INIT_EN_SHIFT 19 /* [19] */
+#define INBUF_CTL_ANTENNA_INIT_SHIFT 18 /* [18] */
+#define INBUF_CTL_IIR_A_IB_SHIFT 16 /* [17:16] */
+#define INBUF_CTL_DUAL_SHIFT 15 /* [15] */
+#define INBUF_CTL_BURST_SHIFT 14 /* [14] */
+#define INBUF_CTL_ANT_MODE_SHIFT 12 /* [13:12] */
+#define INBUF_CTL_CAPTURE_SHIFT 11 /* [11] */
+#define INBUF_CTL_CAPLEN_SHIFT 8 /* [10:8] */
+#define INBUF_CTL_BUFFCAPT_SHIFT 4 /* [7:4] */
+#define INBUF_CTL_BUFFCAPINT_SHIFT 0 /* [3:0] */
+
+#define INBUF_ANTENNA_INIT_EN_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_EN_SHIFT
+#define INBUF_ANTENNA_INIT_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_SHIFT
+#define INBUF_CTL_IIR_A_IB_MASK 0x00000003 << INBUF_CTL_IIR_A_IB_SHIFT
+#define INBUF_CTL_DUAL_MASK 0x00000001 << INBUF_CTL_DUAL_SHIFT
+#define INBUF_CTL_BURST_MASK 0x00000001 << INBUF_CTL_BURST_SHIFT
+#define INBUF_CTL_ANT_MODE_MASK 0x00000003 << INBUF_CTL_ANT_MODE_SHIFT
+#define INBUF_CTL_CAPTURE_MASK 0x00000001 << INBUF_CTL_CAPTURE_SHIFT
+#define INBUF_CTL_CAPLEN_MASK 0x00000007 << INBUF_CTL_CAPLEN_SHIFT
+#define INBUF_CTL_BUFFCAPT_MASK 0x0000000f << INBUF_CTL_BUFFCAPT_SHIFT
+#define INBUF_CTL_BUFFCAPINT_MASK 0x0000000f << INBUF_CTL_BUFFCAPINT_SHIFT
+
+
+/*HWD_SRDO_CTL*/
+#define CTL_CLEAR_SHIFT 9 /* [9] */
+#define CTL_ACQMODE_SHIFT 8 /* [8] */
+#define CTL_SEARCH_SET_SHIFT 6 /* [7:6] */
+#define CTL_SEARCH_N_SHIFT 0 /* [5:0] */
+
+#define CTL_CLEAR_MASK 0x00000001 << CTL_CLEAR_SHIFT
+#define CTL_ACQMODE_MASK 0x00000001 << CTL_ACQMODE_SHIFT
+#define CTL_SEARCH_SET_MASK 0x00000003 << CTL_SEARCH_SET_SHIFT
+#define CTL_SEARCH_N_MASK 0x0000003f << CTL_SEARCH_N_SHIFT
+
+/*HWD_SRDO_GENSTAT0*/
+#define GENSTAT0_COHLEN_SHIFT 17 /* [18:17] */
+#define GENSTAT0_PASSCNT1_SHIFT 12 /* [16:12] */
+#define GENSTAT0_PASSCNT2_SHIFT 6 /* [11:6] */
+#define GENSTAT0_SHIFT1_SHIFT 3 /* [5:3] */
+#define GENSTAT0_SHIFT2_SHIFT 0 /* [2:0] */
+
+#define GENSTAT0_COHLEN_MASK 0x00000003 << GENSTAT0_COHLEN_SHIFT
+#define GENSTAT0_PASSCNT1_MASK 0x0000001f << GENSTAT0_PASSCNT1_SHIFT
+#define GENSTAT0_PASSCNT2_MASK 0x0000003f << GENSTAT0_PASSCNT2_SHIFT
+#define GENSTAT0_SHIFT1_MASK 0x00000007 << GENSTAT0_SHIFT1_SHIFT
+#define GENSTAT0_SHIFT2_MASK 0x00000007 << GENSTAT0_SHIFT2_SHIFT
+
+/*HWD_SRDO_GENSTAT1*/
+#define GENSTAT1_THRESH1M_SHIFT 8 /* [15:8] */
+#define GENSTAT1_THRESH2M_SHIFT 0 /* [7:0] */
+#define GENSTAT1_THRESH1M_MASK 0x000000ff << GENSTAT1_THRESH1M_SHIFT
+#define GENSTAT1_THRESH2M_MASK 0x000000ff << GENSTAT1_THRESH2M_SHIFT
+
+/*HWD_SRDO_PATHMAINT*/
+#define PATHMAINT_PATHMAINT_MODE_SHIFT 3 /* [3] */
+#define PATHMAINT_CLR_NUMSEARCH_SHIFT 2 /* [2] */
+#define PATHMAINT_IIR_A_SHIFT 0 /* [1:0] */
+#define PATHMAINT_PATHMAINT_MODE_MASK 0x00000001 << PATHMAINT_PATHMAINT_MODE_SHIFT
+#define PATHMAINT_CLR_NUMSEARCH_MASK 0x00000001 << PATHMAINT_CLR_NUMSEARCH_SHIFT
+#define PATHMAINT_IIR_A_MASK 0x00000003 << PATHMAINT_IIR_A_SHIFT
+
+/*HWD_SRDO_INBUF0_ADR*/
+#define INBUF_ADR_INBUF_ADR_SHIFT 0 /* [13:0] */
+#define INBUF_ADR_INBUF_ADR_MASK 0x00003fff << INBUF_ADR_INBUF_ADR_SHIFT
+
+/*HWD_SRDO_INBUF_DAT*/
+#define INBUF_DAT_INBUF_DAT0_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT0_MASK 0x000fffff << INBUF_DAT_INBUF_DAT0_SHIFT
+
+/*HWD_SRDO_INBUF_DAT1*/
+#define INBUF_DAT_INBUF_DAT1_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT1_MASK 0x000fffff << INBUF_DAT_INBUF_DAT1_SHIFT
+
+
+/*HWD_SRDO_STATUS0*/
+#define STATUS0_ANTENNA_SHIFT 24 /* [24] */
+#define STATUS0_BUSY_SHIFT 23 /* [23] */
+#define STATUS0_INMAG_INST_SHIFT 15 /* [22:15] */
+#define STATUS0_INMAG_IIR_SHIFT 7 /* [14:7] */
+#define STATUS0_BUFCAPTMHS_SHIFT 0 /* [6:0] */
+
+#define STATUS0_ANTENNA_MASK 0x00000001 << STATUS0_ANTENNA_SHIFT
+#define STATUS0_BUSY_MASK 0x00000001 << STATUS0_BUSY_SHIFT
+#define STATUS0_INMAG_INST_MASK 0x000000ff << STATUS0_INMAG_INST_SHIFT
+#define STATUS0_INMAG_IIR_MASK 0x000000ff << STATUS0_INMAG_IIR_SHIFT
+#define STATUS0_BUFCAPTMHS_MASK 0x0000007f << STATUS0_BUFCAPTMHS_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR1*/
+#define PLTINFO_CLR1_CLR_SHIFT 0 /* [23:0] */
+#define PLTINFO_CLR1_CLR_MASK 0x00ffffff << PLTINFO_CLR1_CLR_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR0*/
+#define PLTINFO_CLR0_CLR_SHIFT 0 /* [31:0] */
+#define PLTINFO_CLR0_CLR_MASK 0xffffffff << PLTINFO_CLR0_CLR_SHIFT
+
+/*HWD_SRDO_PATHINFO_CLR*/
+#define PATHINFO_CLR_CLR_SHIFT 0 /* [19:0] */
+#define PATHINFO_CLR_CLR_MASK 0x000fffff << PATHINFO_CLR_CLR_SHIFT
+
+/*HWD_SRDO_ACQ_CTL*/
+#define ACQ_CTL_ACQ_WIN_SHIFT 11 /* [20:11] */
+#define ACQ_CTL_ACQ_OFFSET_SHIFT 0 /* [10:0] */
+#define ACQ_CTL_ACQ_WIN_MASK 0x000003ff << ACQ_CTL_ACQ_WIN_SHIFT
+#define ACQ_CTL_ACQ_OFFSET_MASK 0x000007ff << ACQ_CTL_ACQ_OFFSET_SHIFT
+
+/*HWD_SRDO_TSTCTL*/
+#define TSTCTL_INBUF_TST_MODE_SHIFT 0 /* [0] */
+#define TSTCTL_INBUF_TST_MODE_MASK 1 << TSTCTL_INBUF_TST_MODE_SHIFT
+
+/*HWD_SRDO_STATUS1, NOTE: start from bit 7*/
+#define STATUS1_INMAG_INST1_SHIFT 15 /* [22:15] */
+#define STATUS1_INMAG_IIR1_SHIFT 7 /* [14:7] */
+#define STATUS1_INMAG_INST1_MASK 0x000000ff << STATUS1_INMAG_INST1_SHIFT
+#define STATUS1_INMAG_IIR1_MASK 0x000000ff << STATUS1_INMAG_IIR1_SHIFT
+
+
+/*HWD_SRDO_TSTSEL*/
+#define TSTSEL_TST_SEL_SHIFT 0 /* [7:0] */
+#define TSTSEL_TST_SEL_MASK 0x000000ff << TSTSEL_TST_SEL_SHIFT
+
+/*HWD_SRDO_PATHINFO*/
+#define PATHINFO_MAX 20
+#define PATHINFO_LEN 4 /* byte */
+
+#define PATHINFO_ENABLE_SHIFT 22 /* [22] */
+#define PATHINFO_KEEP_SHIFT 21 /* [21] */
+#define PATHINFO_WIN_SHIFT 17 /* [20:17] */
+#define PATHINFO_PILOTPNNUM_SHIFT 8 /* [16:8] */
+#define PATHINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PATHINFO_ENABLE_MASK 0x00000001 << PATHINFO_ENABLE_SHIFT
+#define PATHINFO_KEEP_MASK 0x00000001 << PATHINFO_KEEP_SHIFT
+#define PATHINFO_WIN_MASK 0x0000000f << PATHINFO_WIN_SHIFT
+#define PATHINFO_PILOTPNNUM_MASK 0x000001ff << PATHINFO_PILOTPNNUM_SHIFT
+#define PATHINFO_SUMMAG_MASK 0x00000ff << PATHINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PLTLIST*/
+#define PLTLIST_MAX 56
+#define PLTLIST_LEN 4 /* byte */
+#define PLTLIST_ENABLE_SHIFT 26 /* [26] */
+#define PLTLIST_KEEP_SHIFT 25 /* [25] */
+#define PLTLIST_WIN_SHIFT 21 /* [24:21] */
+#define PLTLIST_ALWAYS_SEARCH_SHIFT 20 /* [20] */
+#define PLTLIST_PILOT_PN_SHIFT 11 /* [19:11] */
+#define PLTLIST_OFFSET_SHIFT 0 /* [10:0] */
+#define PLTLIST_WIN_MASK 0x0000000f << PLTLIST_WIN_SHIFT
+#define PLTLIST_ALWAYS_SEARCH_MASK 0x00000001 << PLTLIST_ALWAYS_SEARCH_SHIFT
+#define PLTLIST_PILOT_PN_MASK 0x000001ff << PLTLIST_PILOT_PN_SHIFT
+#define PLTLIST_OFFSET_MASK 0x000007ff << PLTLIST_OFFSET_SHIFT
+
+/*HWD_SRDO_PLTINFO*/
+#define PLTINFO_MAX 56
+#define PLTINFO_LEN 4 /* byte */
+#define PLTINFO_NUMSEARCH_SHIFT 8 /* [11:8] */
+#define PLTINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PLTINFO_NUMSEARCH_MASK 0x0000000f << PLTINFO_NUMSEARCH_SHIFT
+#define PLTINFO_SUMMAG_MASK 0x000000ff << PLTINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PATHBUF*/
+#define PATHBUF_MAX 16 /* total 16 path for each path ( 20 ) */
+#define PATHBUF_LEN 4 /* byte */
+#define PATHBUF_PATH_VALID_SHIFT 24 /* [24] */
+#define PATHBUF_NUMAVG_SHIFT 21 /* [23:21] */
+#define PATHBUF_ANTENNA_SHIFT 20 /* [20] */
+#define PATHBUF_OFFSET_SHIFT 8 /* [19:8] */
+#define PATHBUF_STAT_SHIFT 0 /* [7:0] */
+#define PATHBUF_PATH_VALID_MASK 0x00000001 << PATHBUF_PATH_VALID_SHIFT
+#define PATHBUF_NUMAVG_MASK 0x00000007 << PATHBUF_NUMAVG_SHIFT
+#define PATHBUF_ANTENNA_MASK 0x00000001 << PATHBUF_ANTENNA_SHIFT
+#define PATHBUF_OFFSET_MASK 0x00000fff << PATHBUF_OFFSET_SHIFT
+#define PATHBUF_STAT_MASK 0x000000ff << PATHBUF_STAT_SHIFT
+
+/*HWD_SRDO_CLKCTL*/
+#define CLKCTL_CLK_MODE_SHIFT 1 /* [1] */
+#define CLKCTL_CLKENB_SHIFT 0 /* [0] */
+#define CLKCTL_CLK_MODE_MASK (0x1 << CLKCTL_CLK_MODE_SHIFT)
+#define CLKCTL_CLKENB_MASK (0x1 << CLKCTL_CLKENB_SHIFT)
+
+/*SRDO_DONE*/
+#define SRDO_DONE_DONE_SHIFT 0
+#define SRDO_DONE_DONE_MASK 0x00000001 << SRDO_DONE_DONE_SHIFT
+
+#endif //#ifndef _CPH_EVDO_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg_97.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_97.h
new file mode 100644
index 0000000..e30df2b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_97.h
@@ -0,0 +1,600 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_SCH_97_H_
+#define _CPH_EVDO_SCH_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_CDO_REG_BASE (0xA9880000)
+
+#define CS_CDO_end (CS_CDO_REG_BASE + 0x0800 + 1*4)
+
+
+
+#define SRDO_START ((APBADDR32)(CS_CDO_REG_BASE + 0x0000))
+#define SRDO_PAUSE ((APBADDR32)(CS_CDO_REG_BASE + 0x0004))
+#define SRDO_RST ((APBADDR32)(CS_CDO_REG_BASE + 0x0008))
+#define SRDO_INBUF_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x000C))
+#define SRDO_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0010))
+#define SRDO_MEM_SEL ((APBADDR32)(CS_CDO_REG_BASE + 0x0014))
+#define SRDO_GENSTAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0018))
+#define SRDO_GENSTAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x001C))
+#define SRDO_PATHMAINT ((APBADDR32)(CS_CDO_REG_BASE + 0x0020))
+#define SRDO_INBUF_ADR ((APBADDR32)(CS_CDO_REG_BASE + 0x0024))
+#define SRDO_INBUF_DAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0028))
+#define SRDO_STATUS0 ((APBADDR32)(CS_CDO_REG_BASE + 0x002C))
+#define SRDO_PLTINFO_CLR0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0030))
+#define SRDO_PLTINFO_CLR1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0034))
+#define SRDO_PATHINFO_CLR ((APBADDR32)(CS_CDO_REG_BASE + 0x0038))
+#define SRDO_ACQ_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x003C))
+#define SRDO_TSTCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0040))
+#define SRDO_CLKCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0048))
+#define SRDO_STATUS1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0050))
+#define SRDO_INBUF_DAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0054))
+#define SRDO_FNDO_MEMCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0058))
+#define SRDO_THRESH ((APBADDR32)(CS_CDO_REG_BASE + 0x005C))
+#define SRDO_TST_DBG ((APBADDR32)(CS_CDO_REG_BASE + 0x0060))
+#define SRDO_DONE ((APBADDR32)(CS_CDO_REG_BASE + 0x0064))
+#define SRDO_PATHINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0080))
+#define SRDO_PLTLIST ((APBADDR32)(CS_CDO_REG_BASE + 0x0100))
+#define SRDO_PLTINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0200))
+#define SRDO_PATHBUF ((APBADDR32)(CS_CDO_REG_BASE + 0x0800))
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*HWD_SRDO_START*/
+#define START_START_SHIFT 0 /* [0] */
+#define START_SRDO_START_DLY_EN_SHIFT 1 /* [1] */
+#define START_SRDO_START_DLY_CNT_SHIFT 2 /* [21:2] */
+
+#define START_START_MASK 0x00000001 << START_START_SHIFT
+#define START_SRDO_START_DLY_EN_MASK 0x00000001 << START_SRDO_START_DLY_EN_SHIFT
+#define START_SRDO_START_DLY_CNT_MASK 0x000FFFFF << START_SRDO_START_DLY_CNT_SHIFT
+
+
+/*HWD_SRDO_PAUSE*/
+#define PAUSE_PAUSE_SHIFT 0 /* [0] */
+#define PAUSE_PAUSE_MASK 0x00000001 << PAUSE_PAUSE_SHIFT
+
+/*HWD_SRDO_RST*/
+#define RST_RST_SHIFT 0 /* [0] */
+#define RST_RST_MASK 0x00000001 << RST_RST_SHIFT
+
+/*HWD_SRDO_INBUF_CTL*/
+#define INBUF_CTL_ANTENNA_INIT_EN_SHIFT 19 /* [19] */
+#define INBUF_CTL_ANTENNA_INIT_SHIFT 18 /* [18] */
+#define INBUF_CTL_IIR_A_IB_SHIFT 16 /* [17:16] */
+#define INBUF_CTL_DUAL_SHIFT 15 /* [15] */
+#define INBUF_CTL_BURST_SHIFT 14 /* [14] */
+#define INBUF_CTL_ANT_MODE_SHIFT 12 /* [13:12] */
+#define INBUF_CTL_CAPTURE_SHIFT 11 /* [11] */
+#define INBUF_CTL_CAPLEN_SHIFT 8 /* [10:8] */
+#define INBUF_CTL_BUFFCAPT_SHIFT 4 /* [7:4] */
+#define INBUF_CTL_BUFFCAPINT_SHIFT 0 /* [3:0] */
+
+#define INBUF_ANTENNA_INIT_EN_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_EN_SHIFT
+#define INBUF_ANTENNA_INIT_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_SHIFT
+#define INBUF_CTL_IIR_A_IB_MASK 0x00000003 << INBUF_CTL_IIR_A_IB_SHIFT
+#define INBUF_CTL_DUAL_MASK 0x00000001 << INBUF_CTL_DUAL_SHIFT
+#define INBUF_CTL_BURST_MASK 0x00000001 << INBUF_CTL_BURST_SHIFT
+#define INBUF_CTL_ANT_MODE_MASK 0x00000003 << INBUF_CTL_ANT_MODE_SHIFT
+#define INBUF_CTL_CAPTURE_MASK 0x00000001 << INBUF_CTL_CAPTURE_SHIFT
+#define INBUF_CTL_CAPLEN_MASK 0x00000007 << INBUF_CTL_CAPLEN_SHIFT
+#define INBUF_CTL_BUFFCAPT_MASK 0x0000000f << INBUF_CTL_BUFFCAPT_SHIFT
+#define INBUF_CTL_BUFFCAPINT_MASK 0x0000000f << INBUF_CTL_BUFFCAPINT_SHIFT
+
+
+/*HWD_SRDO_CTL*/
+#define CTL_CLEAR_SHIFT 9 /* [9] */
+#define CTL_ACQMODE_SHIFT 8 /* [8] */
+#define CTL_SEARCH_SET_SHIFT 6 /* [7:6] */
+#define CTL_SEARCH_N_SHIFT 0 /* [5:0] */
+
+#define CTL_CLEAR_MASK 0x00000001 << CTL_CLEAR_SHIFT
+#define CTL_ACQMODE_MASK 0x00000001 << CTL_ACQMODE_SHIFT
+#define CTL_SEARCH_SET_MASK 0x00000003 << CTL_SEARCH_SET_SHIFT
+#define CTL_SEARCH_N_MASK 0x0000003f << CTL_SEARCH_N_SHIFT
+
+/*HWD_SRDO_GENSTAT0*/
+#define GENSTAT0_COHLEN_SHIFT 17 /* [18:17] */
+#define GENSTAT0_PASSCNT1_SHIFT 12 /* [16:12] */
+#define GENSTAT0_PASSCNT2_SHIFT 6 /* [11:6] */
+#define GENSTAT0_SHIFT1_SHIFT 3 /* [5:3] */
+#define GENSTAT0_SHIFT2_SHIFT 0 /* [2:0] */
+
+#define GENSTAT0_COHLEN_MASK 0x00000003 << GENSTAT0_COHLEN_SHIFT
+#define GENSTAT0_PASSCNT1_MASK 0x0000001f << GENSTAT0_PASSCNT1_SHIFT
+#define GENSTAT0_PASSCNT2_MASK 0x0000003f << GENSTAT0_PASSCNT2_SHIFT
+#define GENSTAT0_SHIFT1_MASK 0x00000007 << GENSTAT0_SHIFT1_SHIFT
+#define GENSTAT0_SHIFT2_MASK 0x00000007 << GENSTAT0_SHIFT2_SHIFT
+
+/*HWD_SRDO_GENSTAT1*/
+#define GENSTAT1_THRESH1M_SHIFT 8 /* [15:8] */
+#define GENSTAT1_THRESH2M_SHIFT 0 /* [7:0] */
+#define GENSTAT1_THRESH1M_MASK 0x000000ff << GENSTAT1_THRESH1M_SHIFT
+#define GENSTAT1_THRESH2M_MASK 0x000000ff << GENSTAT1_THRESH2M_SHIFT
+
+/*HWD_SRDO_PATHMAINT*/
+#define PATHMAINT_PATHMAINT_MODE_SHIFT 3 /* [3] */
+#define PATHMAINT_CLR_NUMSEARCH_SHIFT 2 /* [2] */
+#define PATHMAINT_IIR_A_SHIFT 0 /* [1:0] */
+#define PATHMAINT_PATHMAINT_MODE_MASK 0x00000001 << PATHMAINT_PATHMAINT_MODE_SHIFT
+#define PATHMAINT_CLR_NUMSEARCH_MASK 0x00000001 << PATHMAINT_CLR_NUMSEARCH_SHIFT
+#define PATHMAINT_IIR_A_MASK 0x00000003 << PATHMAINT_IIR_A_SHIFT
+
+/*HWD_SRDO_INBUF0_ADR*/
+#define INBUF_ADR_INBUF_ADR_SHIFT 0 /* [13:0] */
+#define INBUF_ADR_INBUF_ADR_MASK 0x00003fff << INBUF_ADR_INBUF_ADR_SHIFT
+
+/*HWD_SRDO_INBUF_DAT*/
+#define INBUF_DAT_INBUF_DAT0_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT0_MASK 0x000fffff << INBUF_DAT_INBUF_DAT0_SHIFT
+
+/*HWD_SRDO_INBUF_DAT1*/
+#define INBUF_DAT_INBUF_DAT1_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT1_MASK 0x000fffff << INBUF_DAT_INBUF_DAT1_SHIFT
+
+
+/*HWD_SRDO_STATUS0*/
+#define STATUS0_ANTENNA_SHIFT 24 /* [24] */
+#define STATUS0_BUSY_SHIFT 23 /* [23] */
+#define STATUS0_INMAG_INST_SHIFT 15 /* [22:15] */
+#define STATUS0_INMAG_IIR_SHIFT 7 /* [14:7] */
+#define STATUS0_BUFCAPTMHS_SHIFT 0 /* [6:0] */
+
+#define STATUS0_ANTENNA_MASK 0x00000001 << STATUS0_ANTENNA_SHIFT
+#define STATUS0_BUSY_MASK 0x00000001 << STATUS0_BUSY_SHIFT
+#define STATUS0_INMAG_INST_MASK 0x000000ff << STATUS0_INMAG_INST_SHIFT
+#define STATUS0_INMAG_IIR_MASK 0x000000ff << STATUS0_INMAG_IIR_SHIFT
+#define STATUS0_BUFCAPTMHS_MASK 0x0000007f << STATUS0_BUFCAPTMHS_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR1*/
+#define PLTINFO_CLR1_CLR_SHIFT 0 /* [23:0] */
+#define PLTINFO_CLR1_CLR_MASK 0x00ffffff << PLTINFO_CLR1_CLR_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR0*/
+#define PLTINFO_CLR0_CLR_SHIFT 0 /* [31:0] */
+#define PLTINFO_CLR0_CLR_MASK 0xffffffff << PLTINFO_CLR0_CLR_SHIFT
+
+/*HWD_SRDO_PATHINFO_CLR*/
+#define PATHINFO_CLR_CLR_SHIFT 0 /* [19:0] */
+#define PATHINFO_CLR_CLR_MASK 0x000fffff << PATHINFO_CLR_CLR_SHIFT
+
+/*HWD_SRDO_ACQ_CTL*/
+#define ACQ_CTL_ACQ_WIN_SHIFT 11 /* [20:11] */
+#define ACQ_CTL_ACQ_OFFSET_SHIFT 0 /* [10:0] */
+#define ACQ_CTL_ACQ_WIN_MASK 0x000003ff << ACQ_CTL_ACQ_WIN_SHIFT
+#define ACQ_CTL_ACQ_OFFSET_MASK 0x000007ff << ACQ_CTL_ACQ_OFFSET_SHIFT
+
+/*HWD_SRDO_TSTCTL*/
+#define TSTCTL_INBUF_TST_MODE_SHIFT 0 /* [0] */
+#define TSTCTL_INBUF_TST_MODE_MASK 1 << TSTCTL_INBUF_TST_MODE_SHIFT
+
+/*HWD_SRDO_STATUS1, NOTE: start from bit 7*/
+#define STATUS1_INMAG_INST1_SHIFT 15 /* [22:15] */
+#define STATUS1_INMAG_IIR1_SHIFT 7 /* [14:7] */
+#define STATUS1_INMAG_INST1_MASK 0x000000ff << STATUS1_INMAG_INST1_SHIFT
+#define STATUS1_INMAG_IIR1_MASK 0x000000ff << STATUS1_INMAG_IIR1_SHIFT
+
+
+/*HWD_SRDO_TSTSEL*/
+#define TSTSEL_TST_SEL_SHIFT 0 /* [7:0] */
+#define TSTSEL_TST_SEL_MASK 0x000000ff << TSTSEL_TST_SEL_SHIFT
+
+/*HWD_SRDO_PATHINFO*/
+#define PATHINFO_MAX 20
+#define PATHINFO_LEN 4 /* byte */
+
+#define PATHINFO_ENABLE_SHIFT 22 /* [22] */
+#define PATHINFO_KEEP_SHIFT 21 /* [21] */
+#define PATHINFO_WIN_SHIFT 17 /* [20:17] */
+#define PATHINFO_PILOTPNNUM_SHIFT 8 /* [16:8] */
+#define PATHINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PATHINFO_ENABLE_MASK 0x00000001 << PATHINFO_ENABLE_SHIFT
+#define PATHINFO_KEEP_MASK 0x00000001 << PATHINFO_KEEP_SHIFT
+#define PATHINFO_WIN_MASK 0x0000000f << PATHINFO_WIN_SHIFT
+#define PATHINFO_PILOTPNNUM_MASK 0x000001ff << PATHINFO_PILOTPNNUM_SHIFT
+#define PATHINFO_SUMMAG_MASK 0x00000ff << PATHINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PLTLIST*/
+#define PLTLIST_MAX 56
+#define PLTLIST_LEN 4 /* byte */
+#define PLTLIST_ENABLE_SHIFT 26 /* [26] */
+#define PLTLIST_KEEP_SHIFT 25 /* [25] */
+#define PLTLIST_WIN_SHIFT 21 /* [24:21] */
+#define PLTLIST_ALWAYS_SEARCH_SHIFT 20 /* [20] */
+#define PLTLIST_PILOT_PN_SHIFT 11 /* [19:11] */
+#define PLTLIST_OFFSET_SHIFT 0 /* [10:0] */
+#define PLTLIST_WIN_MASK 0x0000000f << PLTLIST_WIN_SHIFT
+#define PLTLIST_ALWAYS_SEARCH_MASK 0x00000001 << PLTLIST_ALWAYS_SEARCH_SHIFT
+#define PLTLIST_PILOT_PN_MASK 0x000001ff << PLTLIST_PILOT_PN_SHIFT
+#define PLTLIST_OFFSET_MASK 0x000007ff << PLTLIST_OFFSET_SHIFT
+
+/*HWD_SRDO_PLTINFO*/
+#define PLTINFO_MAX 56
+#define PLTINFO_LEN 4 /* byte */
+#define PLTINFO_NUMSEARCH_SHIFT 8 /* [11:8] */
+#define PLTINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PLTINFO_NUMSEARCH_MASK 0x0000000f << PLTINFO_NUMSEARCH_SHIFT
+#define PLTINFO_SUMMAG_MASK 0x000000ff << PLTINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PATHBUF*/
+#define PATHBUF_MAX 16 /* total 16 path for each path ( 20 ) */
+#define PATHBUF_LEN 4 /* byte */
+#define PATHBUF_PATH_VALID_SHIFT 24 /* [24] */
+#define PATHBUF_NUMAVG_SHIFT 21 /* [23:21] */
+#define PATHBUF_ANTENNA_SHIFT 20 /* [20] */
+#define PATHBUF_OFFSET_SHIFT 8 /* [19:8] */
+#define PATHBUF_STAT_SHIFT 0 /* [7:0] */
+#define PATHBUF_PATH_VALID_MASK 0x00000001 << PATHBUF_PATH_VALID_SHIFT
+#define PATHBUF_NUMAVG_MASK 0x00000007 << PATHBUF_NUMAVG_SHIFT
+#define PATHBUF_ANTENNA_MASK 0x00000001 << PATHBUF_ANTENNA_SHIFT
+#define PATHBUF_OFFSET_MASK 0x00000fff << PATHBUF_OFFSET_SHIFT
+#define PATHBUF_STAT_MASK 0x000000ff << PATHBUF_STAT_SHIFT
+
+/*HWD_SRDO_CLKCTL*/
+#define CLKCTL_CLK_MODE_SHIFT 1 /* [1] */
+#define CLKCTL_CLKENB_SHIFT 0 /* [0] */
+#define CLKCTL_CLK_MODE_MASK (0x1 << CLKCTL_CLK_MODE_SHIFT)
+#define CLKCTL_CLKENB_MASK (0x1 << CLKCTL_CLKENB_SHIFT)
+
+/*SRDO_DONE*/
+#define SRDO_DONE_DONE_SHIFT 0
+#define SRDO_DONE_DONE_MASK 0x00000001 << SRDO_DONE_DONE_SHIFT
+#endif //#ifndef _CPH_EVDO_SCH_97_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdotxbrp.h b/mcu/interface/l1/cl1/common/HW/cphevdotxbrp.h
new file mode 100644
index 0000000..c87a5ad
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdotxbrp.h
@@ -0,0 +1,791 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_TX_BRP_H_
+#define _CPH_EVDO_TX_BRP_H_
+
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXBRP_EVDO_REG_BASE (0xa8018000)
+#else
+#define TXBRP_EVDO_REG_BASE (0xa8818000)
+#endif
+
+#define TXBRP_EVDO_end (TXBRP_EVDO_REG_BASE + 0x0408 + 1*4)
+
+
+
+#define TXBRP_WORK_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0000))
+#define TXBRP_GLOBAL_IRQ ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0008))
+#define TXBRP_GLOBAL_IRQ_MASK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x000c))
+#define TXBRP_GLOBAL_IRQ_CLR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0010))
+#define TXBRP_DO_IRQ ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0038))
+#define TXBRP_DO_IRQ_MASK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x003c))
+#define TXBRP_DO_IRQ_CLR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0040))
+#define TXBRP_SW_CKEN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0050))
+#define TXBRP_CLK_CTRLSEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0054))
+#define TXBRP_DEBUG_REG_BANK_SEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0058))
+#define TXBRP_MEM_TEST_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x005c))
+#define TXBRP_TRIGGER_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0060))
+#define TXBRP_DI_SWAP_EN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0064))
+#define TXBRP_DI_TEST_CFG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0068))
+#define TXBRP_I_REG_ULTRA_PRE_EN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x006c))
+#define TXBRP_I_REG_BEGIN_ULTRA_CNT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0070))
+#define TXBRP_I_REG_ULTRA_WATER_MARK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0074))
+#define TXBRP_DI_DEBUG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0078))
+#define TXBRP_DEBUG_TRIG_SEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x007c))
+#define TXBRP_DEBUG_0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0080))
+#define TXBRP_DEBUG_1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0084))
+#define TXBRP_ENC_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0090))
+#define TXBRP_CRC_DBG_FLAG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0094))
+#define TXBRP_INTLV_B_LWT_ST_0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0098))
+#define TXBRP_INTLV_B_LWT_ST_1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x009c))
+#define TXBRP_CTRL_FSM_STATE1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a0))
+#define TXBRP_CTRL_FSM_STATE2 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a4))
+#define TXBRP_RM_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a8))
+#define TXBRP_RUMAP_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00ac))
+#define TXBRP_TEST_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00c4))
+#define TXBRP_CRP_SW_READ_CTRL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00c8))
+#define TXBRP_C2K_READ_RST ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00cc))
+#define TXBRP_EVDO_START ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00ec))
+#define TXBRP_DO_TX_ENABLE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0110))
+#define TXBRP_DO_RRI_DATA_ACK0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0114))
+#define TXBRP_DO_RRI_DATA_ACK1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0118))
+#define TXBRP_DO_RRI_DATA_ACK2 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x011c))
+#define TXBRP_DO_CHNL_TYPE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0124))
+#define TXBRP_DO_PROTOCOL_SUBTYP ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x012c))
+#define TXBRP_DO_TX_BYTE_SWAP ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0130))
+#define TXBRP_DO_TX_TEST3 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0134))
+#define TXBRP_EVDO_CHNL_BASE_ADDR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x014c))
+#define TXBRP_DO_RRI_DATA_NAK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0150))
+#define TXBRP_EVDO_CHNL_BASE_ADDR1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0154))
+#define TXBRP_DO_INTERLACE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0158))
+#define TXBRP_DBG_CRC32 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03bc))
+#define TXBRP_DBG_CRC32_RSLT_I ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03c0))
+#define TXBRP_DBG_CRC32_RSLT_Q ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03c4))
+#if defined(__MD93__)||defined(__MD95__)
+#define TXBRP_EVDO_SUBTYPE2_HLARQ_RESULT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0408))
+#else
+#define TXBRP_EVDO_SUBTYPE2_HLARQ_RESULT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0404))
+#endif
+
+#define WORK_MODE_WORK_MODE_LSB (0)
+#define WORK_MODE_WORK_MODE_WIDTH (5)
+#define WORK_MODE_WORK_MODE_MASK (0x0000001F)
+
+#define GLOBAL_IRQ_DI_ERR_IRQ_LSB (3)
+#define GLOBAL_IRQ_DI_ERR_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_DI_ERR_IRQ_MASK (0x00000008)
+#define GLOBAL_IRQ_DI_ERR_IRQ_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_LSB (2)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_MASK (0x00000004)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_LSB (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_MASK (0x00000002)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MODE_IRQ_LSB (0)
+#define GLOBAL_IRQ_MODE_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_IRQ_MASK (0x00000001)
+#define GLOBAL_IRQ_MODE_IRQ_BIT (0x00000001)
+
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_LSB (3)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_MASK (0x00000008)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_LSB (2)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_MASK (0x00000004)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_LSB (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_MASK (0x00000002)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_LSB (0)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_MASK (0x00000001)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_BIT (0x00000001)
+
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_LSB (3)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_MASK (0x00000008)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_BIT (0x00000008)
+
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_LSB (2)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_MASK (0x00000004)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_BIT (0x00000004)
+
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_LSB (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_MASK (0x00000002)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_BIT (0x00000002)
+
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_LSB (0)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_MASK (0x00000001)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_BIT (0x00000001)
+
+#define DO_IRQ_DO_TRIG_ERR_LSB (2)
+#define DO_IRQ_DO_TRIG_ERR_WIDTH (1)
+#define DO_IRQ_DO_TRIG_ERR_MASK (0x00000004)
+#define DO_IRQ_DO_TRIG_ERR_BIT (0x00000004)
+
+#define DO_IRQ_DO_RD_ERR_LSB (1)
+#define DO_IRQ_DO_RD_ERR_WIDTH (1)
+#define DO_IRQ_DO_RD_ERR_MASK (0x00000002)
+#define DO_IRQ_DO_RD_ERR_BIT (0x00000002)
+
+#define DO_IRQ_DO_DONE_LSB (0)
+#define DO_IRQ_DO_DONE_WIDTH (1)
+#define DO_IRQ_DO_DONE_MASK (0x00000001)
+#define DO_IRQ_DO_DONE_BIT (0x00000001)
+
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_LSB (2)
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_WIDTH (1)
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_MASK (0x00000004)
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_BIT (0x00000004)
+
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_LSB (1)
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_WIDTH (1)
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_MASK (0x00000002)
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_BIT (0x00000002)
+
+#define DO_IRQ_MASK_DO_DONE_MASK_LSB (0)
+#define DO_IRQ_MASK_DO_DONE_MASK_WIDTH (1)
+#define DO_IRQ_MASK_DO_DONE_MASK_MASK (0x00000001)
+#define DO_IRQ_MASK_DO_DONE_MASK_BIT (0x00000001)
+
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_LSB (2)
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_WIDTH (1)
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_MASK (0x00000004)
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_BIT (0x00000004)
+
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_LSB (1)
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_WIDTH (1)
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_MASK (0x00000002)
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_BIT (0x00000002)
+
+#define DO_IRQ_CLR_DO_DONE_CLR_LSB (0)
+#define DO_IRQ_CLR_DO_DONE_CLR_WIDTH (1)
+#define DO_IRQ_CLR_DO_DONE_CLR_MASK (0x00000001)
+#define DO_IRQ_CLR_DO_DONE_CLR_BIT (0x00000001)
+
+#define TXBRP_SW_CKEN_APB_SW_CKEN_LSB (10)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_MASK (0x00000400)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_BIT (0x00000400)
+
+#define TXBRP_SW_CKEN_OB_SW_CKEN_LSB (9)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_MASK (0x00000200)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_BIT (0x00000200)
+
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_LSB (8)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_MASK (0x00000100)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_BIT (0x00000100)
+
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_LSB (7)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_MASK (0x00000080)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_BIT (0x00000080)
+
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_LSB (6)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_MASK (0x00000040)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_BIT (0x00000040)
+
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_LSB (5)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_MASK (0x00000020)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_BIT (0x00000020)
+
+#define TXBRP_SW_CKEN_RM_SW_CKEN_LSB (4)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_MASK (0x00000010)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_BIT (0x00000010)
+
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_LSB (3)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_MASK (0x00000008)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_BIT (0x00000008)
+
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_LSB (2)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_MASK (0x00000004)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_BIT (0x00000004)
+
+#define TXBRP_SW_CKEN_DI_SW_CKEN_LSB (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_MASK (0x00000002)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_BIT (0x00000002)
+
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_LSB (0)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_MASK (0x00000001)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_LSB (10)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_MASK (0x00000400)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_BIT (0x00000400)
+
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_LSB (9)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_MASK (0x00000200)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_BIT (0x00000200)
+
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_LSB (8)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_MASK (0x00000100)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_BIT (0x00000100)
+
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_LSB (7)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_MASK (0x00000080)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_BIT (0x00000080)
+
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_LSB (6)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_MASK (0x00000040)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_BIT (0x00000040)
+
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_LSB (5)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_MASK (0x00000020)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_BIT (0x00000020)
+
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_LSB (4)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_MASK (0x00000010)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_BIT (0x00000010)
+
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_LSB (3)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_MASK (0x00000008)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_BIT (0x00000008)
+
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_LSB (2)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_MASK (0x00000004)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_BIT (0x00000004)
+
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_LSB (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_MASK (0x00000002)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_BIT (0x00000002)
+
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_LSB (0)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_MASK (0x00000001)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_BIT (0x00000001)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_LSB (24)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_MASK (0xFF000000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_LSB (16)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_MASK (0x00FF0000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_LSB (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_LSB (0)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_MASK (0x000000FF)
+
+#define MEM_TEST_MODE_MEM_TEST_MODE_LSB (0)
+#define MEM_TEST_MODE_MEM_TEST_MODE_WIDTH (1)
+#define MEM_TEST_MODE_MEM_TEST_MODE_MASK (0x00000001)
+#define MEM_TEST_MODE_MEM_TEST_MODE_BIT (0x00000001)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_LSB (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_MASK (0x00000002)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_BIT (0x00000002)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_LSB (0)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_MASK (0x00000001)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_BIT (0x00000001)
+
+#define DI_SWAP_EN_DI_SWAP_EN_LSB (0)
+#define DI_SWAP_EN_DI_SWAP_EN_WIDTH (3)
+#define DI_SWAP_EN_DI_SWAP_EN_MASK (0x00000007)
+
+#define DI_TEST_CFG_DI_TEST_MODE_EN_LSB (10)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_WIDTH (1)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_MASK (0x00000400)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_BIT (0x00000400)
+
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_LSB (8)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_WIDTH (2)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_MASK (0x00000300)
+
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_LSB (0)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_WIDTH (8)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_MASK (0x000000FF)
+
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_LSB (0)
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_WIDTH (1)
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_MASK (0x00000001)
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_BIT (0x00000001)
+
+#define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_LSB (0)
+#define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_WIDTH (3)
+#define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_MASK (0x00000007)
+
+#define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_LSB (0)
+#define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_WIDTH (3)
+#define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_MASK (0x00000007)
+
+#define DI_DEBUG_DMA0_STATE_LSB (20)
+#define DI_DEBUG_DMA0_STATE_WIDTH (2)
+#define DI_DEBUG_DMA0_STATE_MASK (0x00300000)
+
+#define DI_DEBUG_RAM_RD_STATE_LSB (16)
+#define DI_DEBUG_RAM_RD_STATE_WIDTH (2)
+#define DI_DEBUG_RAM_RD_STATE_MASK (0x00030000)
+
+#define DI_DEBUG_O_DMA0_UTR_LSB (13)
+#define DI_DEBUG_O_DMA0_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_UTR_MASK (0x00002000)
+#define DI_DEBUG_O_DMA0_UTR_BIT (0x00002000)
+
+#define DI_DEBUG_O_DMA0_PTR_UTR_LSB (12)
+#define DI_DEBUG_O_DMA0_PTR_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_PTR_UTR_MASK (0x00001000)
+#define DI_DEBUG_O_DMA0_PTR_UTR_BIT (0x00001000)
+
+#define DI_DEBUG_O_DMA0_RD_REQ_LSB (10)
+#define DI_DEBUG_O_DMA0_RD_REQ_WIDTH (1)
+#define DI_DEBUG_O_DMA0_RD_REQ_MASK (0x00000400)
+#define DI_DEBUG_O_DMA0_RD_REQ_BIT (0x00000400)
+
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_LSB (9)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_WIDTH (1)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_MASK (0x00000200)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_BIT (0x00000200)
+
+#define DI_DEBUG_RAM_FULL_LSB (8)
+#define DI_DEBUG_RAM_FULL_WIDTH (1)
+#define DI_DEBUG_RAM_FULL_MASK (0x00000100)
+#define DI_DEBUG_RAM_FULL_BIT (0x00000100)
+
+#define DI_DEBUG_CHECK_DONE_LSB (7)
+#define DI_DEBUG_CHECK_DONE_WIDTH (1)
+#define DI_DEBUG_CHECK_DONE_MASK (0x00000080)
+#define DI_DEBUG_CHECK_DONE_BIT (0x00000080)
+
+#define DI_DEBUG_DI_OUT_BIT_FINISH_LSB (6)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_WIDTH (1)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_MASK (0x00000040)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_BIT (0x00000040)
+
+#define DI_DEBUG_RAM_ALL_RDATA_READ_LSB (5)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_WIDTH (1)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_MASK (0x00000020)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_BIT (0x00000020)
+
+#define DI_DEBUG_DI_BUSY_LSB (4)
+#define DI_DEBUG_DI_BUSY_WIDTH (1)
+#define DI_DEBUG_DI_BUSY_MASK (0x00000010)
+#define DI_DEBUG_DI_BUSY_BIT (0x00000010)
+
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_LSB (3)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_MASK (0x00000008)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_BIT (0x00000008)
+
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_LSB (2)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_WIDTH (1)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_MASK (0x00000004)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_BIT (0x00000004)
+
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_LSB (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_MASK (0x00000002)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_BIT (0x00000002)
+
+#define DI_DEBUG_CRC_BUF_OUT_SEL_LSB (0)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_MASK (0x00000001)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_BIT (0x00000001)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_LSB (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_MASK (0x000000FF)
+
+#define TXBRP_DEBUG_0_TXBRP_DEBUG_0_LSB (0)
+#define TXBRP_DEBUG_0_TXBRP_DEBUG_0_WIDTH (32)
+#define TXBRP_DEBUG_0_TXBRP_DEBUG_0_MASK (0xFFFFFFFF)
+
+#define TXBRP_DEBUG_1_TXBRP_DEBUG_1_LSB (0)
+#define TXBRP_DEBUG_1_TXBRP_DEBUG_1_WIDTH (32)
+#define TXBRP_DEBUG_1_TXBRP_DEBUG_1_MASK (0xFFFFFFFF)
+
+#define ENC_FSM_STATE_wt_conv_state_LSB (17)
+#define ENC_FSM_STATE_wt_conv_state_WIDTH (3)
+#define ENC_FSM_STATE_wt_conv_state_MASK (0x000E0000)
+
+#define ENC_FSM_STATE_lte_state_LSB (13)
+#define ENC_FSM_STATE_lte_state_WIDTH (4)
+#define ENC_FSM_STATE_lte_state_MASK (0x0001E000)
+
+#define ENC_FSM_STATE_codec_dis_state_LSB (10)
+#define ENC_FSM_STATE_codec_dis_state_WIDTH (3)
+#define ENC_FSM_STATE_codec_dis_state_MASK (0x00001C00)
+
+#define ENC_FSM_STATE_codec_en_state_LSB (6)
+#define ENC_FSM_STATE_codec_en_state_WIDTH (4)
+#define ENC_FSM_STATE_codec_en_state_MASK (0x000003C0)
+
+#define ENC_FSM_STATE_codec_w_state_LSB (3)
+#define ENC_FSM_STATE_codec_w_state_WIDTH (3)
+#define ENC_FSM_STATE_codec_w_state_MASK (0x00000038)
+
+#define ENC_FSM_STATE_codec_state_LSB (0)
+#define ENC_FSM_STATE_codec_state_WIDTH (3)
+#define ENC_FSM_STATE_codec_state_MASK (0x00000007)
+
+#define CRC_DBG_FLAG_crc_len_dbg_LSB (26)
+#define CRC_DBG_FLAG_crc_len_dbg_WIDTH (5)
+#define CRC_DBG_FLAG_crc_len_dbg_MASK (0x7C000000)
+
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_LSB (25)
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_WIDTH (1)
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_MASK (0x02000000)
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_BIT (0x02000000)
+
+#define CRC_DBG_FLAG_cqi_or_data_dbg_LSB (24)
+#define CRC_DBG_FLAG_cqi_or_data_dbg_WIDTH (1)
+#define CRC_DBG_FLAG_cqi_or_data_dbg_MASK (0x01000000)
+#define CRC_DBG_FLAG_cqi_or_data_dbg_BIT (0x01000000)
+
+#define CRC_DBG_FLAG_crc_state_dbg_LSB (16)
+#define CRC_DBG_FLAG_crc_state_dbg_WIDTH (6)
+#define CRC_DBG_FLAG_crc_state_dbg_MASK (0x003F0000)
+
+#define CRC_DBG_FLAG_bit_cnt_dbg_LSB (0)
+#define CRC_DBG_FLAG_bit_cnt_dbg_WIDTH (15)
+#define CRC_DBG_FLAG_bit_cnt_dbg_MASK (0x00007FFF)
+
+#define INTLV_B_LWT_ST_0_lte_wen_st_LSB (15)
+#define INTLV_B_LWT_ST_0_lte_wen_st_WIDTH (3)
+#define INTLV_B_LWT_ST_0_lte_wen_st_MASK (0x00038000)
+
+#define INTLV_B_LWT_ST_0_ts_w_state_LSB (12)
+#define INTLV_B_LWT_ST_0_ts_w_state_WIDTH (3)
+#define INTLV_B_LWT_ST_0_ts_w_state_MASK (0x00007000)
+
+#define INTLV_B_LWT_ST_0_ts_r_state_LSB (9)
+#define INTLV_B_LWT_ST_0_ts_r_state_WIDTH (3)
+#define INTLV_B_LWT_ST_0_ts_r_state_MASK (0x00000E00)
+
+#define INTLV_B_LWT_ST_0_pp_w_state_upa_LSB (6)
+#define INTLV_B_LWT_ST_0_pp_w_state_upa_WIDTH (3)
+#define INTLV_B_LWT_ST_0_pp_w_state_upa_MASK (0x000001C0)
+
+#define INTLV_B_LWT_ST_0_pp_w_state_dch_LSB (3)
+#define INTLV_B_LWT_ST_0_pp_w_state_dch_WIDTH (3)
+#define INTLV_B_LWT_ST_0_pp_w_state_dch_MASK (0x00000038)
+
+#define INTLV_B_LWT_ST_0_sec_intlv_state_LSB (0)
+#define INTLV_B_LWT_ST_0_sec_intlv_state_WIDTH (3)
+#define INTLV_B_LWT_ST_0_sec_intlv_state_MASK (0x00000007)
+
+#define INTLV_B_LWT_ST_1_clm_cnt_LSB (25)
+#define INTLV_B_LWT_ST_1_clm_cnt_WIDTH (5)
+#define INTLV_B_LWT_ST_1_clm_cnt_MASK (0x3E000000)
+
+#define INTLV_B_LWT_ST_1_row_cnt_LSB (22)
+#define INTLV_B_LWT_ST_1_row_cnt_WIDTH (3)
+#define INTLV_B_LWT_ST_1_row_cnt_MASK (0x01C00000)
+
+#define INTLV_B_LWT_ST_1_blk_cnt_LSB (14)
+#define INTLV_B_LWT_ST_1_blk_cnt_WIDTH (8)
+#define INTLV_B_LWT_ST_1_blk_cnt_MASK (0x003FC000)
+
+#define INTLV_B_LWT_ST_1_sec_reqo_LSB (13)
+#define INTLV_B_LWT_ST_1_sec_reqo_WIDTH (1)
+#define INTLV_B_LWT_ST_1_sec_reqo_MASK (0x00002000)
+#define INTLV_B_LWT_ST_1_sec_reqo_BIT (0x00002000)
+
+#define INTLV_B_LWT_ST_1_ppr_req_upa_LSB (9)
+#define INTLV_B_LWT_ST_1_ppr_req_upa_WIDTH (4)
+#define INTLV_B_LWT_ST_1_ppr_req_upa_MASK (0x00001E00)
+
+#define INTLV_B_LWT_ST_1_ppr_read_done_upa_LSB (5)
+#define INTLV_B_LWT_ST_1_ppr_read_done_upa_WIDTH (4)
+#define INTLV_B_LWT_ST_1_ppr_read_done_upa_MASK (0x000001E0)
+
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_LSB (4)
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_WIDTH (1)
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_MASK (0x00000010)
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_BIT (0x00000010)
+
+#define INTLV_B_LWT_ST_1_ppr_req_dch_LSB (3)
+#define INTLV_B_LWT_ST_1_ppr_req_dch_WIDTH (1)
+#define INTLV_B_LWT_ST_1_ppr_req_dch_MASK (0x00000008)
+#define INTLV_B_LWT_ST_1_ppr_req_dch_BIT (0x00000008)
+
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_LSB (2)
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_WIDTH (1)
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_MASK (0x00000004)
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_BIT (0x00000004)
+
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_LSB (1)
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_WIDTH (1)
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_MASK (0x00000002)
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_BIT (0x00000002)
+
+#define INTLV_B_LWT_ST_1_dch_edch_mode_LSB (0)
+#define INTLV_B_LWT_ST_1_dch_edch_mode_WIDTH (1)
+#define INTLV_B_LWT_ST_1_dch_edch_mode_MASK (0x00000001)
+#define INTLV_B_LWT_ST_1_dch_edch_mode_BIT (0x00000001)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_LSB (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_WIDTH (6)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_MASK (0x03F00000)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_WIDTH (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_MASK (0x000FFFFF)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_LSB (16)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_WIDTH (4)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_MASK (0x000F0000)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_LSB (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_WIDTH (9)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_MASK (0x0000FF80)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_WIDTH (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_MASK (0x0000007F)
+
+#define RM_FSM_STATE_BIT_SEP_STATE_LSB (16)
+#define RM_FSM_STATE_BIT_SEP_STATE_WIDTH (3)
+#define RM_FSM_STATE_BIT_SEP_STATE_MASK (0x00070000)
+
+#define RM_FSM_STATE_BC_STATE_LSB (0)
+#define RM_FSM_STATE_BC_STATE_WIDTH (16)
+#define RM_FSM_STATE_BC_STATE_MASK (0x0000FFFF)
+
+#define RUMAP_FSM_STATE_BUF_STATE_LSB (5)
+#define RUMAP_FSM_STATE_BUF_STATE_WIDTH (1)
+#define RUMAP_FSM_STATE_BUF_STATE_MASK (0x00000020)
+#define RUMAP_FSM_STATE_BUF_STATE_BIT (0x00000020)
+
+#define RUMAP_FSM_STATE_RU_MAP_STATE_LSB (0)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_WIDTH (5)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_MASK (0x0000001F)
+
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_LSB (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_MASK (0x00000002)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_BIT (0x00000002)
+
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_LSB (0)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_MASK (0x00000001)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_BIT (0x00000001)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_LSB (13)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_MASK (0x00006000)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_LSB (11)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_MASK (0x00001800)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_LSB (9)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_MASK (0x00000600)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_LSB (7)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_MASK (0x00000180)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_LSB (5)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_MASK (0x00000060)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_LSB (4)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_MASK (0x00000010)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_BIT (0x00000010)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_LSB (3)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_MASK (0x00000008)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_BIT (0x00000008)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_LSB (2)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_MASK (0x00000004)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_BIT (0x00000004)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_LSB (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_MASK (0x00000002)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_BIT (0x00000002)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_LSB (0)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_MASK (0x00000001)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_BIT (0x00000001)
+
+#define C2K_READ_RST_C2K_READ_RST_LSB (0)
+#define C2K_READ_RST_C2K_READ_RST_WIDTH (1)
+#define C2K_READ_RST_C2K_READ_RST_MASK (0x00000001)
+#define C2K_READ_RST_C2K_READ_RST_BIT (0x00000001)
+
+#define EVDO_START_EVDO_START_LSB (0)
+#define EVDO_START_EVDO_START_WIDTH (1)
+#define EVDO_START_EVDO_START_MASK (0x00000001)
+#define EVDO_START_EVDO_START_BIT (0x00000001)
+
+#define DO_TX_ENABLE_Transmitter_Enable_LSB (0)
+#define DO_TX_ENABLE_Transmitter_Enable_WIDTH (1)
+#define DO_TX_ENABLE_Transmitter_Enable_MASK (0x00000001)
+#define DO_TX_ENABLE_Transmitter_Enable_BIT (0x00000001)
+
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_LSB (3)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_MASK (0x00000078)
+
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_LSB (0)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_WIDTH (3)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_MASK (0x00000007)
+
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_LSB (3)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_MASK (0x00000078)
+
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_LSB (0)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_WIDTH (3)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_MASK (0x00000007)
+
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_LSB (6)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_WIDTH (1)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_MASK (0x00000040)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_BIT (0x00000040)
+
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_LSB (2)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_MASK (0x0000003C)
+
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_LSB (0)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_WIDTH (2)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_MASK (0x00000003)
+
+#define DO_CHNL_TYPE_Channel_type_LSB (0)
+#define DO_CHNL_TYPE_Channel_type_WIDTH (1)
+#define DO_CHNL_TYPE_Channel_type_MASK (0x00000001)
+#define DO_CHNL_TYPE_Channel_type_BIT (0x00000001)
+
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_LSB (0)
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_WIDTH (1)
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_MASK (0x00000001)
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_BIT (0x00000001)
+
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_LSB (0)
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_WIDTH (1)
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_MASK (0x00000001)
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_BIT (0x00000001)
+
+#define DO_TX_TEST3_TX_ROW_ROT_LSB (0)
+#define DO_TX_TEST3_TX_ROW_ROT_WIDTH (1)
+#define DO_TX_TEST3_TX_ROW_ROT_MASK (0x00000001)
+#define DO_TX_TEST3_TX_ROW_ROT_BIT (0x00000001)
+
+#define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_LSB (0)
+#define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_WIDTH (32)
+#define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_LSB (2)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_MASK (0x0000003C)
+
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_LSB (0)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_WIDTH (2)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_MASK (0x00000003)
+
+#define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_LSB (0)
+#define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_WIDTH (32)
+#define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_MASK (0xFFFFFFFF)
+
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_LSB (0)
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_WIDTH (1)
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_MASK (0x00000001)
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_BIT (0x00000001)
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
+
+#endif //#ifndef _CPH_EVDO_TX_BRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdotxcrp.h b/mcu/interface/l1/cl1/common/HW/cphevdotxcrp.h
new file mode 100644
index 0000000..dfa8a61
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdotxcrp.h
@@ -0,0 +1,449 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_TXCRP_H_
+#define _CPH_EVDO_TXCRP_H_
+
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_C_EVDO_REG_BASE (0xA8100000)
+#else
+#define TXCRP_C_EVDO_REG_BASE (0xA8900000)
+#endif
+
+#define TXCRP_C_EVDO_end (TXCRP_C_EVDO_REG_BASE + 0x50110 + 1*4)
+
+
+
+#define TXCRP_DO_RRI_DATA_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50000))
+#define TXCRP_DO_RRI_DATA_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50004))
+#define TXCRP_DO_RRI_DATA_2_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50008))
+#define TXCRP_DO_RRI_DATA_2_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5000C))
+#define TXCRP_DO_DRC_COVER_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50010))
+#define TXCRP_DO_DRC_COVER_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50014))
+#define TXCRP_DO_DSC_DATA_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50018))
+#define TXCRP_DO_DSC_DATA_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5001C))
+#define TXCRP_DO_TX_LONG_PN_INITIAL1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50020))
+#define TXCRP_DO_TX_LONG_PN_INITIAL2 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50024))
+#define TXCRP_DO_LD_OFFSET ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50028))
+#define TXCRP_DO_RD_BASE_ADDR_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5002C))
+#define TXCRP_DO_RD_BASE_ADDR_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50030))
+#define TXCRP_DO_CHNL_TYPE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50034))
+#define TXCRP_DO_PROTOCOL_SUBTYP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50038))
+#define TXCRP_DO_TX_ENABLE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5003C))
+#define TXCRP_DO_TX_IQ_INV ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50040))
+#define TXCRP_DO_TX_LONG_PN_MASK2 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50044))
+#define TXCRP_DO_TX_LONG_PN_MASK1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50048))
+#define TXCRP_DO_LONGPN_LOAD ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5004C))
+#define TXCRP_DO_DRC_BOOST_LEN ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50050))
+#define TXCRP_DO_DSC_BOOST_LEN ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50054))
+#define TXCRP_DO_AUXPLT_MINPYLD ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50058))
+#define TXCRP_DO_PLT_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5005C))
+#define TXCRP_DO_AUXPLT_SCALE_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50060))
+#define TXCRP_DO_AUXPLT_SCALE_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50064))
+#define TXCRP_DO_RRI_SCALE_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50068))
+#define TXCRP_DO_RRI_SCALE_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5006C))
+#define TXCRP_DO_DSC_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50070))
+#define TXCRP_DO_DSC_SCALE_BOOST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50074))
+#define TXCRP_DO_DRC_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50078))
+#define TXCRP_DO_DRC_SCALE_BOOST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5007C))
+#define TXCRP_DO_BOOST_SELECT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50080))
+#define TXCRP_DO_DSC_SCALE_INDICATE_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50084))
+#define TXCRP_DO_DSC_SCALE_INDICATE_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50088))
+#define TXCRP_DO_DRC_SCALE_INDICATE_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5008C))
+#define TXCRP_DO_DRC_SCALE_INDICATE_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50090))
+#define TXCRP_DO_ACK_SCALE_SUP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50094))
+#define TXCRP_DO_ACK_SCALE_MUP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50098))
+#define TXCRP_DO_DATA_SCALE0_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5009C))
+#define TXCRP_DO_DATA_SCALE1_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A0))
+#define TXCRP_DO_DATA_SCALE2_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A4))
+#define TXCRP_DO_DATA_SCALE3_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A8))
+#define TXCRP_DO_DATA_SCALE0_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500AC))
+#define TXCRP_DO_DATA_SCALE1_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B0))
+#define TXCRP_DO_DATA_SCALE2_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B4))
+#define TXCRP_DO_DATA_SCALE3_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B8))
+#define TXCRP_DO_KS_TRIGGER ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500BC))
+#define TXCRP_DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C0))
+#define TXCRP_DO_DRC_SELECT_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C4))
+#define TXCRP_DO_DRC_SELECT_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C8))
+#define TXCRP_DO_SW_RST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500CC))
+#define TXCRP_DO_PREPLT_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D0))
+#define TXCRP_DO_ACK_ENABLE_BIT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D4))
+#define TXCRP_DO_ACK_DATA ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D8))
+#define TXCRP_DO_DATA_SCALE_KS_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500DC))
+#define TXCRP_DO_DATA_SCALE_KS_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E0))
+#define TXCRP_DO_TX_FREEZE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E4))
+#define TXCRP_DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E8))
+#define TXCRP_DO_TX_TEST_MODE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500EC))
+#define TXCRP_DO_TX_TEST0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F0))
+#define TXCRP_DO_TX_TEST1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F4))
+#define TXCRP_DO_DRC_LENGTH ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F8))
+#define TXCRP_DO_DRC_GATING ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500FC))
+#define TXCRP_STATE_Q ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50100))
+#define TXCRP_DO_TX_FSM ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50104))
+#define TXCRP_DRC_DATA_I ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50108))
+#define TXCRP_DOTXCRP_FSM_IS_BUSY ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5010C))
+#define TXCRP_CDO_CHIP_COUNT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50110))
+#define TXCRP_CDO_TICK_COUNT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50114))
+#define TXCRP_RAKE_TXCRP_REV_ACK_BIT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50118))
+#define TXCRP_TXCRP_KS0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5011C))
+#define TXCRP_TXCRP_KS1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50120))
+#define TXCRP_CDO_KS_VALUE_EXP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50124))
+#define TXCRP_CDO_KS_VALUE_MANTISSA ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50128))
+
+
+#define DO_RRI_DATA_0_DO_RRI_DATA_0_LSB (0)
+#define DO_RRI_DATA_0_DO_RRI_DATA_0_WIDTH (7)
+#define DO_RRI_DATA_0_DO_RRI_DATA_0_MASK (0x0000007F)
+
+#define DO_RRI_DATA_1_DO_RRI_DATA_1_LSB (0)
+#define DO_RRI_DATA_1_DO_RRI_DATA_1_WIDTH (7)
+#define DO_RRI_DATA_1_DO_RRI_DATA_1_MASK (0x0000007F)
+
+#define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_LSB (0)
+#define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_WIDTH (7)
+#define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_MASK (0x0000007F)
+
+#define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_LSB (0)
+#define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_WIDTH (7)
+#define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_MASK (0x0000007F)
+
+#define DO_DRC_COVER_0_DO_DRC_COVER_0_LSB (0)
+#define DO_DRC_COVER_0_DO_DRC_COVER_0_WIDTH (4)
+#define DO_DRC_COVER_0_DO_DRC_COVER_0_MASK (0x0000000F)
+
+#define DO_DRC_COVER_1_DO_DRC_COVER_1_LSB (0)
+#define DO_DRC_COVER_1_DO_DRC_COVER_1_WIDTH (4)
+#define DO_DRC_COVER_1_DO_DRC_COVER_1_MASK (0x0000000F)
+
+#define DO_DSC_DATA_0_DO_DSC_DATA_0_LSB (0)
+#define DO_DSC_DATA_0_DO_DSC_DATA_0_WIDTH (4)
+#define DO_DSC_DATA_0_DO_DSC_DATA_0_MASK (0x0000000F)
+
+#define DO_DSC_DATA_1_DO_DSC_DATA_1_LSB (0)
+#define DO_DSC_DATA_1_DO_DSC_DATA_1_WIDTH (4)
+#define DO_DSC_DATA_1_DO_DSC_DATA_1_MASK (0x0000000F)
+
+#define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_LSB (0)
+#define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_WIDTH (32)
+#define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_MASK (0xFFFFFFFF)
+
+#define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_LSB (0)
+#define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_WIDTH (10)
+#define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_MASK (0x000003FF)
+
+#define DO_LD_OFFSET_DO_LD_OFFSET_LSB (0)
+#define DO_LD_OFFSET_DO_LD_OFFSET_WIDTH (15)
+#define DO_LD_OFFSET_DO_LD_OFFSET_MASK (0x00007FFF)
+
+#define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_LSB (0)
+#define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_WIDTH (11)
+#define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_MASK (0x000007FF)
+
+#define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_LSB (0)
+#define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_WIDTH (11)
+#define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_MASK (0x000007FF)
+
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_LSB (0)
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_WIDTH (1)
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_MASK (0x00000001)
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_BIT (0x00000001)
+
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_LSB (0)
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_WIDTH (1)
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_MASK (0x00000001)
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_BIT (0x00000001)
+
+#define DO_TX_ENABLE_DO_TX_ENABLE_LSB (0)
+#define DO_TX_ENABLE_DO_TX_ENABLE_WIDTH (1)
+#define DO_TX_ENABLE_DO_TX_ENABLE_MASK (0x00000001)
+#define DO_TX_ENABLE_DO_TX_ENABLE_BIT (0x00000001)
+
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_LSB (0)
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_WIDTH (1)
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_MASK (0x00000001)
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_BIT (0x00000001)
+
+#define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_LSB (0)
+#define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_WIDTH (10)
+#define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_MASK (0x000003FF)
+
+#define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_LSB (0)
+#define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_WIDTH (32)
+#define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_MASK (0xFFFFFFFF)
+
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_LSB (0)
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_WIDTH (1)
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_MASK (0x00000001)
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_BIT (0x00000001)
+
+#define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_LSB (0)
+#define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_WIDTH (6)
+#define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_MASK (0x0000003F)
+
+#define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_LSB (0)
+#define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_WIDTH (7)
+#define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_MASK (0x0000007F)
+
+#define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_LSB (0)
+#define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_WIDTH (4)
+#define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_MASK (0x0000000F)
+
+#define DO_PLT_SCALE_DO_PLT_SCALE_LSB (0)
+#define DO_PLT_SCALE_DO_PLT_SCALE_WIDTH (9)
+#define DO_PLT_SCALE_DO_PLT_SCALE_MASK (0x000001FF)
+
+#define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_LSB (0)
+#define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_WIDTH (13)
+#define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_MASK (0x00001FFF)
+
+#define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_LSB (0)
+#define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_WIDTH (13)
+#define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_MASK (0x00001FFF)
+
+#define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_LSB (0)
+#define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_WIDTH (9)
+#define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_MASK (0x000001FF)
+
+#define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_LSB (0)
+#define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_WIDTH (9)
+#define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_MASK (0x000001FF)
+
+#define DO_DSC_SCALE_DO_DSC_SCALE_LSB (0)
+#define DO_DSC_SCALE_DO_DSC_SCALE_WIDTH (9)
+#define DO_DSC_SCALE_DO_DSC_SCALE_MASK (0x000001FF)
+
+#define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_LSB (0)
+#define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_WIDTH (9)
+#define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_MASK (0x000001FF)
+
+#define DO_DRC_SCALE_DO_DRC_SCALE_LSB (0)
+#define DO_DRC_SCALE_DO_DRC_SCALE_WIDTH (9)
+#define DO_DRC_SCALE_DO_DRC_SCALE_MASK (0x000001FF)
+
+#define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_LSB (0)
+#define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_WIDTH (9)
+#define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_MASK (0x000001FF)
+
+#define DO_BOOST_SELECT_DO_BOOST_SELECT_LSB (0)
+#define DO_BOOST_SELECT_DO_BOOST_SELECT_WIDTH (2)
+#define DO_BOOST_SELECT_DO_BOOST_SELECT_MASK (0x00000003)
+
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_LSB (0)
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_WIDTH (1)
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_MASK (0x00000001)
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_BIT (0x00000001)
+
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_LSB (0)
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_WIDTH (1)
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_MASK (0x00000001)
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_BIT (0x00000001)
+
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_LSB (0)
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_WIDTH (1)
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_MASK (0x00000001)
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_BIT (0x00000001)
+
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_LSB (0)
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_WIDTH (1)
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_MASK (0x00000001)
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_BIT (0x00000001)
+
+#define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_LSB (0)
+#define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_WIDTH (9)
+#define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_MASK (0x000001FF)
+
+#define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_LSB (0)
+#define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_WIDTH (9)
+#define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_MASK (0x000001FF)
+
+#define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_LSB (0)
+#define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_WIDTH (11)
+#define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_LSB (0)
+#define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_WIDTH (11)
+#define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_LSB (0)
+#define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_WIDTH (11)
+#define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_LSB (0)
+#define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_WIDTH (11)
+#define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_LSB (0)
+#define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_WIDTH (11)
+#define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_LSB (0)
+#define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_WIDTH (11)
+#define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_LSB (0)
+#define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_WIDTH (11)
+#define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_LSB (0)
+#define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_WIDTH (11)
+#define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_MASK (0x000007FF)
+
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_LSB (0)
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_WIDTH (1)
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_MASK (0x00000001)
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_BIT (0x00000001)
+
+#define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_LSB (0)
+#define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_WIDTH (3)
+#define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_MASK (0x00000007)
+
+#define DO_DRC_SELECT_0_DO_DRC_SELECT_0_LSB (0)
+#define DO_DRC_SELECT_0_DO_DRC_SELECT_0_WIDTH (2)
+#define DO_DRC_SELECT_0_DO_DRC_SELECT_0_MASK (0x00000003)
+
+#define DO_DRC_SELECT_1_DO_DRC_SELECT_1_LSB (0)
+#define DO_DRC_SELECT_1_DO_DRC_SELECT_1_WIDTH (2)
+#define DO_DRC_SELECT_1_DO_DRC_SELECT_1_MASK (0x00000003)
+
+#define DO_SW_RST_DO_SW_RST_LSB (0)
+#define DO_SW_RST_DO_SW_RST_WIDTH (1)
+#define DO_SW_RST_DO_SW_RST_MASK (0x00000001)
+#define DO_SW_RST_DO_SW_RST_BIT (0x00000001)
+
+#define DO_PREPLT_SCALE_DO_PREPLT_SCALE_LSB (0)
+#define DO_PREPLT_SCALE_DO_PREPLT_SCALE_WIDTH (9)
+#define DO_PREPLT_SCALE_DO_PREPLT_SCALE_MASK (0x000001FF)
+
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_LSB (0)
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_WIDTH (1)
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_MASK (0x00000001)
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_BIT (0x00000001)
+
+#define DO_ACK_DATA_DO_ACK_DATA_LSB (0)
+#define DO_ACK_DATA_DO_ACK_DATA_WIDTH (2)
+#define DO_ACK_DATA_DO_ACK_DATA_MASK (0x00000003)
+
+#define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_LSB (0)
+#define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_WIDTH (11)
+#define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_LSB (0)
+#define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_WIDTH (11)
+#define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_MASK (0x000007FF)
+
+#define DO_TX_FREEZE_DO_TX_FREEZE_LSB (0)
+#define DO_TX_FREEZE_DO_TX_FREEZE_WIDTH (1)
+#define DO_TX_FREEZE_DO_TX_FREEZE_MASK (0x00000001)
+#define DO_TX_FREEZE_DO_TX_FREEZE_BIT (0x00000001)
+
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_LSB (0)
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_WIDTH (1)
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_MASK (0x00000001)
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_BIT (0x00000001)
+
+#define DO_TX_TEST_MODE_DO_TX_TEST_MODE_LSB (0)
+#define DO_TX_TEST_MODE_DO_TX_TEST_MODE_WIDTH (3)
+#define DO_TX_TEST_MODE_DO_TX_TEST_MODE_MASK (0x00000007)
+
+#define DO_TX_TEST0_DO_TX_TEST0_LSB (0)
+#define DO_TX_TEST0_DO_TX_TEST0_WIDTH (1)
+#define DO_TX_TEST0_DO_TX_TEST0_MASK (0x00000001)
+#define DO_TX_TEST0_DO_TX_TEST0_BIT (0x00000001)
+
+#define DO_TX_TEST1_DO_TX_TEST1_LSB (0)
+#define DO_TX_TEST1_DO_TX_TEST1_WIDTH (4)
+#define DO_TX_TEST1_DO_TX_TEST1_MASK (0x0000000F)
+
+#define DO_DRC_LENGTH_DO_DRC_LENGTH_LSB (0)
+#define DO_DRC_LENGTH_DO_DRC_LENGTH_WIDTH (2)
+#define DO_DRC_LENGTH_DO_DRC_LENGTH_MASK (0x00000003)
+
+#define DO_DRC_GATING_DO_DRC_GATING_LSB (0)
+#define DO_DRC_GATING_DO_DRC_GATING_WIDTH (1)
+#define DO_DRC_GATING_DO_DRC_GATING_MASK (0x00000001)
+#define DO_DRC_GATING_DO_DRC_GATING_BIT (0x00000001)
+
+#define STATE_Q_STATE_Q_LSB (0)
+#define STATE_Q_STATE_Q_WIDTH (5)
+#define STATE_Q_STATE_Q_MASK (0x0000001F)
+
+#define DO_TX_FSM_DO_TX_FSM_LSB (0)
+#define DO_TX_FSM_DO_TX_FSM_WIDTH (7)
+#define DO_TX_FSM_DO_TX_FSM_MASK (0x0000007F)
+
+#define DRC_DATA_I_DRC_DATA_I_LSB (0)
+#define DRC_DATA_I_DRC_DATA_I_WIDTH (4)
+#define DRC_DATA_I_DRC_DATA_I_MASK (0x0000000F)
+
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_LSB (0)
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_WIDTH (1)
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_MASK (0x00000001)
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_BIT (0x00000001)
+
+#define CDO_CHIP_COUNT_CDO_CHIP_COUNT_LSB (0)
+#define CDO_CHIP_COUNT_CDO_CHIP_COUNT_WIDTH (11)
+#define CDO_CHIP_COUNT_CDO_CHIP_COUNT_MASK (0x000007FF)
+
+#define CDO_TICK_COUNT_CDO_TICK_COUNT_LSB (0)
+#define CDO_TICK_COUNT_CDO_TICK_COUNT_WIDTH (6)
+#define CDO_TICK_COUNT_CDO_TICK_COUNT_MASK (0x0000003F)
+
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_LSB (0)
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_WIDTH (1)
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_MASK (0x00000001)
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_BIT (0x00000001)
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
+
+#endif //#ifndef _CPH_EVDO_TXCRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdotxtimerreg.h b/mcu/interface/l1/cl1/common/HW/cphevdotxtimerreg.h
new file mode 100644
index 0000000..21af45d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdotxtimerreg.h
@@ -0,0 +1,356 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_TX_TIMER_H_
+#define _CPH_EVDO_TX_TIMER_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define DFE_W_TTR_DO_REG_BASE (0xA61B0000)
+#else
+#define DFE_W_TTR_DO_REG_BASE (0xA8190000)
+#endif
+#define DFE_W_TTR_end (DFE_W_TTR_DO_REG_BASE + 0x00F0)
+
+
+#define TX_TIMER_DO_SR_OFFSET0 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0000))
+#define TX_TIMER_DO_SR_OFFSET1 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0004))
+#define TX_TIMER_DO_RX_TX_LOG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0050))
+#define TX_TIMER_DO_TX_TIME_MON2 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0064))
+#define TX_TIMER_DO_FRAME_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0070))
+#define TX_TIMER_DO_TXRXDELAY ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0074))
+#define TX_TIMER_DO_RA_DLY ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0078))
+#define TX_TIMER_DO_CDO_TTR_CRP_WIN_ON ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0080))
+#define TX_TIMER_DO_CDO_TTR_CRP_WIN_OFF ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0084))
+#if defined(__MD93__)||defined(__MD95__) /* The registers deleted in 97E1, it is moved to Txdfe-die, configed by RFD */
+#define TX_TIMER_DO_CDO_TTR_TXDFE_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0088))
+#define TX_TIMER_DO_CDO_TTR_TXDFE_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x008C))
+#endif
+#define TX_TIMER_DO_CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0090))
+#define TX_TIMER_DO_CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0094))
+#if defined(__MD93__)||defined(__MD95__) /* The registers deleted in 97E1, it is moved to Txdfe-die, configed by RFD */
+#define TX_TIMER_DO_CDO_TTR_TXDAC_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0098))
+#define TX_TIMER_DO_CDO_TTR_TXDAC_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x009C))
+#endif
+#define TX_TIMER_DO_CDO_TTR_TXBRP_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C0))
+#define TX_TIMER_DO_CDO_TTR_TXCRP_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C4))
+#define TX_TIMER_DO_CDO_TTR_KS_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C8))
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0100))
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0110))
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0114))
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0118))
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x011C))
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0120))
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0124))
+#define TX_TIMER_TTR_WIN_DBG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x012c))
+#endif
+
+#define SR_Offset_SR_Offset_TRG_EN_LSB (20)
+#define SR_Offset_SR_Offset_TRG_EN_WIDTH (1)
+#define SR_Offset_SR_Offset_TRG_EN_MASK (0x00100000)
+#define SR_Offset_SR_Offset_TRG_EN_BIT (0x00100000)
+
+#define SR_Offset_SR_Offset_LSB (0)
+#define SR_Offset_SR_Offset_WIDTH (16)
+#define SR_Offset_SR_Offset_MASK (0x0000FFFF)
+
+#define Frame_Offset_Frame_Offset_LSB (0)
+#define Frame_Offset_Frame_Offset_WIDTH (20)
+#define Frame_Offset_Frame_Offset_MASK (0x000FFFFF)
+
+#define TxRxDelay_TxRxDelay_LSB (0)
+#define TxRxDelay_TxRxDelay_WIDTH (20)
+#define TxRxDelay_TxRxDelay_MASK (0x000FFFFF)
+
+#define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_LSB (0)
+#define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_WIDTH (3)
+#define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_MASK (0x00000007)
+
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_LSB (0)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_WIDTH (20)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_MASK (0x000FFFFF)
+
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_LSB (0)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_WIDTH (20)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_WIDTH (12)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_MASK (0x00000FFF)
+#endif
+
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+#endif
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_LSB (28)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_LSB (22)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_MASK (0x00400000)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_BIT (0x00400000)
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_LSB (20)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_WIDTH (2)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_LSB (28)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_LSB (22)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_MASK (0x00400000)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_BIT (0x00400000)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_LSB (20)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_WIDTH (2)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_WIDTH (12)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_MASK (0x00000FFF)
+
+
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_LSB (28)
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_WIDTH (1)
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_LSB (22)
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_WIDTH (1)
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_MASK (0x00400000)
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_BIT (0x00400000)
+
+#define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_LSB (20)
+#define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_WIDTH (2)
+#define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+
+#define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_WIDTH (12)
+#define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_MASK (0x00000FFF)
+
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_LSB (1)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_WIDTH (1)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_MASK (0x00000002)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_BIT (0x00000002)
+
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_LSB (0)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_WIDTH (1)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_BIT (0x00000001)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_LSB (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_MASK (0x00000002)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_BIT (0x00000001)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_WIDTH (32)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_MASK (0xFFFFFFFF)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_LSB (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_MASK (0x00000002)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_BIT (0x00000001)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_WIDTH (32)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_MASK (0xFFFFFFFF)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_LSB (28)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_MASK (0x10000000)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_BIT (0x10000000)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_LSB (27)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_MASK (0x08000000)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_BIT (0x08000000)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_WIDTH (20)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_LSB (28)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_MASK (0x10000000)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_LSB (27)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_MASK (0x08000000)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_BIT (0x08000000)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_WIDTH (20)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_LSB (0)
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_WIDTH (1)
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_BIT (0x00000001)
+#endif
+
+#endif //#ifndef _CPH_EVDO_TX_TIMER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg.h
new file mode 100644
index 0000000..618b0f1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphfesysmemconfigreg_93.h"
+#elif defined(__MD95__)
+#include "cphfesysmemconfigreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphfesysmemconfigreg_97.h"
+#else
+#include "cphfesysmemconfigreg_97.h"/*#error "[ERROR] Invalid MD generation" modification for build error*/
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_93.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_93.h
new file mode 100644
index 0000000..27b290c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_93.h
@@ -0,0 +1,250 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_FESYS_MEM_CONFIG_REG_H_
+#define _CPH_FESYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MEM_CONFIG_FESYS_REG_BASE (0xA6110000)
+
+#define MEM_CONFIG_FESYS_end (MEM_CONFIG_FESYS_REG_BASE + 0x410 + 1*4)
+
+
+
+#define SW_TYPE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x000))
+#define SW_PWDN_C0_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x004))
+#define GROUP_PWDN_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x008))
+#define WAITING_FLAG_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x00c))
+#define MBIST_MEM_ISOINTB_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x010))
+#define MBIST_MEM_PD_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x014))
+#define MBIST_PROT_STA_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x018))
+#define SRAMC_AO_IDLE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x01c))
+#define SW_TYPE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x100))
+#define SW_PWDN_C0_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x104))
+#define GROUP_PWDN_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x108))
+#define WAITING_FLAG_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x10c))
+#define SRAMC_AO_IDLE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x110))
+#define SW_TYPE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x200))
+#define SW_PWDN_C0_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x204))
+#define SW_PWDN_C1_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x208))
+#define SW_PWDN_C2_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x20c))
+#define SW_PWDN_C3_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x210))
+#define SW_PWDN_C4_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x214))
+#define GROUP_PWDN_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x218))
+#define WAITING_FLAG_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x21c))
+#define SRAMC_AO_IDLE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x220))
+#define SW_TYPE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x300))
+#define SW_PWDN_C0_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x304))
+#define SW_PWDN_C1_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x308))
+#define SW_PWDN_C2_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x30c))
+#define SW_PWDN_C3_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x310))
+#define SW_PWDN_C4_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x314))
+#define GROUP_PWDN_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x318))
+#define WAITING_FLAG_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x31c))
+#define SRAMC_AO_IDLE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x320))
+#define SW_TYPE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x400))
+#define SW_PWDN_C0_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x404))
+#define GROUP_PWDN_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x408))
+#define WAITING_FLAG_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x40c))
+#define SRAMC_AO_IDLE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x410))
+
+
+#define SW_TYPE_MDL1AO_M_LSB (0)
+#define SW_TYPE_MDL1AO_M_WIDTH (2)
+#define SW_TYPE_MDL1AO_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MDL1AO_M_LSB (0)
+#define SW_PWDN_C0_MDL1AO_M_WIDTH (2)
+#define SW_PWDN_C0_MDL1AO_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MDL1AO_M_LSB (0)
+#define GROUP_PWDN_MDL1AO_M_WIDTH (2)
+#define GROUP_PWDN_MDL1AO_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MDL1AO_M_LSB (0)
+#define WAITING_FLAG_MDL1AO_M_WIDTH (1)
+#define WAITING_FLAG_MDL1AO_M_MASK (0x00000001)
+#define WAITING_FLAG_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_ISOINTB_MDL1AO_M_LSB (0)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_PD_MDL1AO_M_LSB (0)
+#define MBIST_MEM_PD_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_PD_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_PD_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_PROT_STA_MDL1AO_M_LSB (0)
+#define MBIST_PROT_STA_MDL1AO_M_WIDTH (1)
+#define MBIST_PROT_STA_MDL1AO_M_MASK (0x00000001)
+#define MBIST_PROT_STA_MDL1AO_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MDL1AO_M_LSB (0)
+#define SRAMC_AO_IDLE_MDL1AO_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MDL1AO_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MDL1AO_M_BIT (0x00000001)
+
+#define SW_TYPE_MD2G_M_LSB (0)
+#define SW_TYPE_MD2G_M_WIDTH (2)
+#define SW_TYPE_MD2G_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MD2G_M_LSB (0)
+#define SW_PWDN_C0_MD2G_M_WIDTH (2)
+#define SW_PWDN_C0_MD2G_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MD2G_M_LSB (0)
+#define GROUP_PWDN_MD2G_M_WIDTH (2)
+#define GROUP_PWDN_MD2G_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MD2G_M_LSB (0)
+#define WAITING_FLAG_MD2G_M_WIDTH (1)
+#define WAITING_FLAG_MD2G_M_MASK (0x00000001)
+#define WAITING_FLAG_MD2G_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MD2G_M_LSB (0)
+#define SRAMC_AO_IDLE_MD2G_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MD2G_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MD2G_M_BIT (0x00000001)
+
+#define SW_TYPE_TXSYS_M_LSB (0)
+#define SW_TYPE_TXSYS_M_WIDTH (9)
+#define SW_TYPE_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C0_TXSYS_M_LSB (0)
+#define SW_PWDN_C0_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C0_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C1_TXSYS_M_LSB (0)
+#define SW_PWDN_C1_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C1_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C2_TXSYS_M_LSB (0)
+#define SW_PWDN_C2_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C2_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C3_TXSYS_M_LSB (0)
+#define SW_PWDN_C3_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C3_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C4_TXSYS_M_LSB (0)
+#define SW_PWDN_C4_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C4_TXSYS_M_MASK (0x000001FF)
+
+#define GROUP_PWDN_TXSYS_M_LSB (0)
+#define GROUP_PWDN_TXSYS_M_WIDTH (9)
+#define GROUP_PWDN_TXSYS_M_MASK (0x000001FF)
+
+#define WAITING_FLAG_TXSYS_M_LSB (0)
+#define WAITING_FLAG_TXSYS_M_WIDTH (5)
+#define WAITING_FLAG_TXSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_TXSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_TXSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_TXSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_TXSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_CSSYS_M_LSB (0)
+#define SW_TYPE_CSSYS_M_WIDTH (6)
+#define SW_TYPE_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C0_CSSYS_M_LSB (0)
+#define SW_PWDN_C0_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C0_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C1_CSSYS_M_LSB (0)
+#define SW_PWDN_C1_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C1_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C2_CSSYS_M_LSB (0)
+#define SW_PWDN_C2_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C2_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C3_CSSYS_M_LSB (0)
+#define SW_PWDN_C3_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C3_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C4_CSSYS_M_LSB (0)
+#define SW_PWDN_C4_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C4_CSSYS_M_MASK (0x0000003F)
+
+#define GROUP_PWDN_CSSYS_M_LSB (0)
+#define GROUP_PWDN_CSSYS_M_WIDTH (6)
+#define GROUP_PWDN_CSSYS_M_MASK (0x0000003F)
+
+#define WAITING_FLAG_CSSYS_M_LSB (0)
+#define WAITING_FLAG_CSSYS_M_WIDTH (5)
+#define WAITING_FLAG_CSSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_CSSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_CSSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_CSSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_CSSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_RXDFE_M_LSB (0)
+#define SW_TYPE_RXDFE_M_WIDTH (2)
+#define SW_TYPE_RXDFE_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_RXDFE_M_LSB (0)
+#define SW_PWDN_C0_RXDFE_M_WIDTH (2)
+#define SW_PWDN_C0_RXDFE_M_MASK (0x00000003)
+
+#define GROUP_PWDN_RXDFE_M_LSB (0)
+#define GROUP_PWDN_RXDFE_M_WIDTH (2)
+#define GROUP_PWDN_RXDFE_M_MASK (0x00000003)
+
+#define WAITING_FLAG_RXDFE_M_LSB (0)
+#define WAITING_FLAG_RXDFE_M_WIDTH (1)
+#define WAITING_FLAG_RXDFE_M_MASK (0x00000001)
+#define WAITING_FLAG_RXDFE_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_RXDFE_M_LSB (0)
+#define SRAMC_AO_IDLE_RXDFE_M_WIDTH (1)
+#define SRAMC_AO_IDLE_RXDFE_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_RXDFE_M_BIT (0x00000001)
+
+
+#endif /*_CPH_FESYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_95.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_95.h
new file mode 100644
index 0000000..27b290c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_95.h
@@ -0,0 +1,250 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_FESYS_MEM_CONFIG_REG_H_
+#define _CPH_FESYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MEM_CONFIG_FESYS_REG_BASE (0xA6110000)
+
+#define MEM_CONFIG_FESYS_end (MEM_CONFIG_FESYS_REG_BASE + 0x410 + 1*4)
+
+
+
+#define SW_TYPE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x000))
+#define SW_PWDN_C0_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x004))
+#define GROUP_PWDN_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x008))
+#define WAITING_FLAG_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x00c))
+#define MBIST_MEM_ISOINTB_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x010))
+#define MBIST_MEM_PD_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x014))
+#define MBIST_PROT_STA_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x018))
+#define SRAMC_AO_IDLE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x01c))
+#define SW_TYPE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x100))
+#define SW_PWDN_C0_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x104))
+#define GROUP_PWDN_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x108))
+#define WAITING_FLAG_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x10c))
+#define SRAMC_AO_IDLE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x110))
+#define SW_TYPE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x200))
+#define SW_PWDN_C0_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x204))
+#define SW_PWDN_C1_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x208))
+#define SW_PWDN_C2_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x20c))
+#define SW_PWDN_C3_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x210))
+#define SW_PWDN_C4_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x214))
+#define GROUP_PWDN_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x218))
+#define WAITING_FLAG_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x21c))
+#define SRAMC_AO_IDLE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x220))
+#define SW_TYPE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x300))
+#define SW_PWDN_C0_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x304))
+#define SW_PWDN_C1_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x308))
+#define SW_PWDN_C2_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x30c))
+#define SW_PWDN_C3_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x310))
+#define SW_PWDN_C4_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x314))
+#define GROUP_PWDN_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x318))
+#define WAITING_FLAG_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x31c))
+#define SRAMC_AO_IDLE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x320))
+#define SW_TYPE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x400))
+#define SW_PWDN_C0_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x404))
+#define GROUP_PWDN_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x408))
+#define WAITING_FLAG_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x40c))
+#define SRAMC_AO_IDLE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x410))
+
+
+#define SW_TYPE_MDL1AO_M_LSB (0)
+#define SW_TYPE_MDL1AO_M_WIDTH (2)
+#define SW_TYPE_MDL1AO_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MDL1AO_M_LSB (0)
+#define SW_PWDN_C0_MDL1AO_M_WIDTH (2)
+#define SW_PWDN_C0_MDL1AO_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MDL1AO_M_LSB (0)
+#define GROUP_PWDN_MDL1AO_M_WIDTH (2)
+#define GROUP_PWDN_MDL1AO_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MDL1AO_M_LSB (0)
+#define WAITING_FLAG_MDL1AO_M_WIDTH (1)
+#define WAITING_FLAG_MDL1AO_M_MASK (0x00000001)
+#define WAITING_FLAG_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_ISOINTB_MDL1AO_M_LSB (0)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_PD_MDL1AO_M_LSB (0)
+#define MBIST_MEM_PD_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_PD_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_PD_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_PROT_STA_MDL1AO_M_LSB (0)
+#define MBIST_PROT_STA_MDL1AO_M_WIDTH (1)
+#define MBIST_PROT_STA_MDL1AO_M_MASK (0x00000001)
+#define MBIST_PROT_STA_MDL1AO_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MDL1AO_M_LSB (0)
+#define SRAMC_AO_IDLE_MDL1AO_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MDL1AO_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MDL1AO_M_BIT (0x00000001)
+
+#define SW_TYPE_MD2G_M_LSB (0)
+#define SW_TYPE_MD2G_M_WIDTH (2)
+#define SW_TYPE_MD2G_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MD2G_M_LSB (0)
+#define SW_PWDN_C0_MD2G_M_WIDTH (2)
+#define SW_PWDN_C0_MD2G_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MD2G_M_LSB (0)
+#define GROUP_PWDN_MD2G_M_WIDTH (2)
+#define GROUP_PWDN_MD2G_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MD2G_M_LSB (0)
+#define WAITING_FLAG_MD2G_M_WIDTH (1)
+#define WAITING_FLAG_MD2G_M_MASK (0x00000001)
+#define WAITING_FLAG_MD2G_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MD2G_M_LSB (0)
+#define SRAMC_AO_IDLE_MD2G_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MD2G_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MD2G_M_BIT (0x00000001)
+
+#define SW_TYPE_TXSYS_M_LSB (0)
+#define SW_TYPE_TXSYS_M_WIDTH (9)
+#define SW_TYPE_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C0_TXSYS_M_LSB (0)
+#define SW_PWDN_C0_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C0_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C1_TXSYS_M_LSB (0)
+#define SW_PWDN_C1_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C1_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C2_TXSYS_M_LSB (0)
+#define SW_PWDN_C2_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C2_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C3_TXSYS_M_LSB (0)
+#define SW_PWDN_C3_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C3_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C4_TXSYS_M_LSB (0)
+#define SW_PWDN_C4_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C4_TXSYS_M_MASK (0x000001FF)
+
+#define GROUP_PWDN_TXSYS_M_LSB (0)
+#define GROUP_PWDN_TXSYS_M_WIDTH (9)
+#define GROUP_PWDN_TXSYS_M_MASK (0x000001FF)
+
+#define WAITING_FLAG_TXSYS_M_LSB (0)
+#define WAITING_FLAG_TXSYS_M_WIDTH (5)
+#define WAITING_FLAG_TXSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_TXSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_TXSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_TXSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_TXSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_CSSYS_M_LSB (0)
+#define SW_TYPE_CSSYS_M_WIDTH (6)
+#define SW_TYPE_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C0_CSSYS_M_LSB (0)
+#define SW_PWDN_C0_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C0_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C1_CSSYS_M_LSB (0)
+#define SW_PWDN_C1_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C1_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C2_CSSYS_M_LSB (0)
+#define SW_PWDN_C2_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C2_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C3_CSSYS_M_LSB (0)
+#define SW_PWDN_C3_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C3_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C4_CSSYS_M_LSB (0)
+#define SW_PWDN_C4_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C4_CSSYS_M_MASK (0x0000003F)
+
+#define GROUP_PWDN_CSSYS_M_LSB (0)
+#define GROUP_PWDN_CSSYS_M_WIDTH (6)
+#define GROUP_PWDN_CSSYS_M_MASK (0x0000003F)
+
+#define WAITING_FLAG_CSSYS_M_LSB (0)
+#define WAITING_FLAG_CSSYS_M_WIDTH (5)
+#define WAITING_FLAG_CSSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_CSSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_CSSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_CSSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_CSSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_RXDFE_M_LSB (0)
+#define SW_TYPE_RXDFE_M_WIDTH (2)
+#define SW_TYPE_RXDFE_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_RXDFE_M_LSB (0)
+#define SW_PWDN_C0_RXDFE_M_WIDTH (2)
+#define SW_PWDN_C0_RXDFE_M_MASK (0x00000003)
+
+#define GROUP_PWDN_RXDFE_M_LSB (0)
+#define GROUP_PWDN_RXDFE_M_WIDTH (2)
+#define GROUP_PWDN_RXDFE_M_MASK (0x00000003)
+
+#define WAITING_FLAG_RXDFE_M_LSB (0)
+#define WAITING_FLAG_RXDFE_M_WIDTH (1)
+#define WAITING_FLAG_RXDFE_M_MASK (0x00000001)
+#define WAITING_FLAG_RXDFE_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_RXDFE_M_LSB (0)
+#define SRAMC_AO_IDLE_RXDFE_M_WIDTH (1)
+#define SRAMC_AO_IDLE_RXDFE_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_RXDFE_M_BIT (0x00000001)
+
+
+#endif /*_CPH_FESYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_97.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_97.h
new file mode 100644
index 0000000..a36b2dd
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_97.h
@@ -0,0 +1,140 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_FESYS_MEM_CONFIG_REG_H_
+#define _CPH_FESYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MEM_CONFIG_FESYS_REG_BASE (0xA8100000)
+
+#define MEM_CONFIG_FESYS_end (MEM_CONFIG_FESYS_REG_BASE + 0x410 + 1*4)
+
+
+
+#define CSSYS_SW_TYPE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x000))
+#define CSSYS_WAIT_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x004))
+#define CSSYS_GROUP_PWDN_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x008))
+#define CSSYS_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x00c))
+#define CSSYS_SW_PWDN_0_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x010))
+#define CSSYS_SW_PWDN_1_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x014))
+#define CSSYS_SW_PWDN_2_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x018))
+#define CSSYS_SW_PWDN_3_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x01c))
+#define CSSYS_SW_PWDN_4_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x020))
+#define DFESYS_PWR_WRAP_SW_TYPE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x024))
+#define DFESYS_PWR_WRAP_WAIT_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x028))
+#define DFESYS_PWR_WRAP_GROUP_PWDN_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x02C))
+#define DFESYS_PWR_WRAP_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x030))
+#define DFESYS_PWR_WRAP_SW_PWDN_0_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x034))
+#define DFESYS_PWR_WRAP_SW_PWDN_1_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x038))
+#define DFESYS_PWR_WRAP_SW_PWDN_2_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x03C))
+#define DFESYS_PWR_WRAP_SW_PWDN_3_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x040))
+#define DFESYS_PWR_WRAP_SW_PWDN_4_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x044))
+#define DFESYS_PWR_WRAP_SW_PWDN_5_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x048))
+#define DFESYS_PWR_WRAP_SW_PWDN_6_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x04C))
+
+#define CSSYS_WAIT_ADDR_C3 (0x00000008)
+#define CSSYS_WAIT_ADDR_C4 (0x00000010)
+
+#define SW_TYPE_CSSYS_M_LSB (0)
+#define SW_TYPE_CSSYS_M_WIDTH (6)
+#define SW_TYPE_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C0_CSSYS_M_LSB (0)
+#define SW_PWDN_C0_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C0_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C1_CSSYS_M_LSB (0)
+#define SW_PWDN_C1_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C1_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C2_CSSYS_M_LSB (0)
+#define SW_PWDN_C2_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C2_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C3_CSSYS_M_LSB (0)
+#define SW_PWDN_C3_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C3_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C4_CSSYS_M_LSB (0)
+#define SW_PWDN_C4_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C4_CSSYS_M_MASK (0x0000003F)
+
+#define GROUP_PWDN_CSSYS_M_LSB (0)
+#define GROUP_PWDN_CSSYS_M_WIDTH (6)
+#define GROUP_PWDN_CSSYS_M_MASK (0x0000003F)
+
+#define WAITING_FLAG_CSSYS_M_LSB (0)
+#define WAITING_FLAG_CSSYS_M_WIDTH (5)
+#define WAITING_FLAG_CSSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_CSSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_CSSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_CSSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_CSSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_RXDFE_M_LSB (0)
+#define SW_TYPE_RXDFE_M_WIDTH (2)
+#define SW_TYPE_RXDFE_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_RXDFE_M_LSB (0)
+#define SW_PWDN_C0_RXDFE_M_WIDTH (2)
+#define SW_PWDN_C0_RXDFE_M_MASK (0x00000003)
+
+#define GROUP_PWDN_RXDFE_M_LSB (0)
+#define GROUP_PWDN_RXDFE_M_WIDTH (2)
+#define GROUP_PWDN_RXDFE_M_MASK (0x00000003)
+
+#define WAITING_FLAG_RXDFE_M_LSB (0)
+#define WAITING_FLAG_RXDFE_M_WIDTH (1)
+#define WAITING_FLAG_RXDFE_M_MASK (0x00000001)
+#define WAITING_FLAG_RXDFE_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_RXDFE_M_LSB (0)
+#define SRAMC_AO_IDLE_RXDFE_M_WIDTH (1)
+#define SRAMC_AO_IDLE_RXDFE_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_RXDFE_M_BIT (0x00000001)
+
+
+#endif /*_CPH_FESYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphid.h b/mcu/interface/l1/cl1/common/HW/cphid.h
new file mode 100644
index 0000000..3cd6e1d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphid.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_ID_H_
+#define _CPH_ID_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define ID_CW_REG_BASE (0xAC000000)/*TBD*/
+
+
+#define ID_CW_end (ID_CW_REG_BASE + 0x010C + 1*4)
+
+#define PEIT_CW_REG_BASE (0xAC351000)/*TBD*/
+#define CMD_RAM_CW_REG_BASE (0xAC002000)/*TBD*/
+
+
+#define ID_CON ((APBADDR32)(ID_CW_REG_BASE + 0x0000))
+#define ID_CFG_0 ((APBADDR32)(ID_CW_REG_BASE + 0x0004))
+#define ID_CFG_1 ((APBADDR32)(ID_CW_REG_BASE + 0x0008))
+#define ID_CFG_C2K ((APBADDR32)(ID_CW_REG_BASE + 0x000C))
+#define ID_LOAD_POS_FAST ((APBADDR32)(ID_CW_REG_BASE + 0x0010))
+#define ID_LOAD_POS_SLOW ((APBADDR32)(ID_CW_REG_BASE + 0x0014))
+#define ID_LOAD_POS_FAST_DO ((APBADDR32)(ID_CW_REG_BASE + 0x0018))
+#define ID_LOAD_POS_SLOW_DO ((APBADDR32)(ID_CW_REG_BASE + 0x001C))
+#define ID_DESP_BATCH ((APBADDR32)(ID_CW_REG_BASE + 0x0020))
+#define ID_DBG_0 ((APBADDR32)(ID_CW_REG_BASE + 0x0100))
+#define ID_DBG_1 ((APBADDR32)(ID_CW_REG_BASE + 0x0104))
+#define ID_DBG_2 ((APBADDR32)(ID_CW_REG_BASE + 0x0108))
+
+#endif //#ifndef _CPH_D2BIF_H_
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg.h
new file mode 100644
index 0000000..1823c48
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphmdrxsysmemconfigreg_93.h"
+#elif defined(__MD95__)
+#include "cphmdrxsysmemconfigreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphmdrxsysmemconfigreg_97.h"
+#else
+#include "cphmdrxsysmemconfigreg_97.h"/*#error "[ERROR] Invalid MD generation" modification for build error*/
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_93.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_93.h
new file mode 100644
index 0000000..fe7f56d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_93.h
@@ -0,0 +1,358 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+#define _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDRXAO_MEM_CONFIG_REG_BASE (0xA6120000)
+
+#define MDRXAO_MEM_CONFIG_end (MDRXAO_MEM_CONFIG_REG_BASE + 0xd4 + 1*4)
+
+
+
+#define DMC_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x0))
+#define SCQ_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4))
+#define BRP_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8))
+#define BIGRAM_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc))
+#define RAKE_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x10))
+#define DMC_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x14))
+#define SCQ_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x18))
+#define SCQ_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x1c))
+#define BRP_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x20))
+#define BRP_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x24))
+#define BRP_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x28))
+#define BRP_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x2c))
+#define BRP_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x30))
+#define BIGRAM_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x34))
+#define BIGRAM_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x38))
+#define BIGRAM_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x3c))
+#define BIGRAM_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x40))
+#define BIGRAM_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x44))
+#define RAKE_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x48))
+#define RAKE_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4c))
+#define RAKE_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x50))
+#define DMC_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x54))
+#define SCQ_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x58))
+#define BRP_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x5c))
+#define BIGRAM_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x60))
+#define RAKE_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x64))
+#define DMC_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x68))
+#define BRAM_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x74))
+#define BRAM_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x78))
+#define BRAM_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x7c))
+#define BRAM_WAIT_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x80))
+#define BRAM_WAIT_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x84))
+#define RAKE_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x9c))
+#define RAKE_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa0))
+#define RAKE_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa4))
+#define SRAM_CTRL_AO_IDLE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa8))
+#define RAKE_PM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb0))
+#define RAKE_PM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb4))
+#define SCQ_SPM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc0))
+#define SCQ_SPM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc4))
+#define CK_IDLE_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd0))
+#define CK_IDLE_DBG_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd4))
+
+
+#define DMC_SW_TYPE_GP_TYPE_LSB (0)
+#define DMC_SW_TYPE_GP_TYPE_WIDTH (1)
+#define DMC_SW_TYPE_GP_TYPE_MASK (0x00000001)
+#define DMC_SW_TYPE_GP_TYPE_BIT (0x00000001)
+
+#define SCQ_SW_TYPE_GP_TYPE_LSB (0)
+#define SCQ_SW_TYPE_GP_TYPE_WIDTH (11)
+#define SCQ_SW_TYPE_GP_TYPE_MASK (0x000007FF)
+
+#define BRP_SW_TYPE_GP_TYPE_LSB (0)
+#define BRP_SW_TYPE_GP_TYPE_WIDTH (6)
+#define BRP_SW_TYPE_GP_TYPE_MASK (0x0000003F)
+
+#define BIGRAM_SW_TYPE_GP_TYPE_LSB (0)
+#define BIGRAM_SW_TYPE_GP_TYPE_WIDTH (3)
+#define BIGRAM_SW_TYPE_GP_TYPE_MASK (0x00000007)
+
+#define RAKE_SW_TYPE_GP_TYPE_LSB (0)
+#define RAKE_SW_TYPE_GP_TYPE_WIDTH (8)
+#define RAKE_SW_TYPE_GP_TYPE_MASK (0x000000FF)
+
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_WIDTH (1)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000001)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_BIT (0x00000001)
+
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_WIDTH (11)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000007FF)
+
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_WIDTH (11)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000007FF)
+
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_WIDTH (6)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_WIDTH (6)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_WIDTH (6)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_WIDTH (6)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_WIDTH (6)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_MASK (0x0000003F)
+
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_WIDTH (3)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_WIDTH (3)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_WIDTH (3)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_WIDTH (3)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_WIDTH (3)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_MASK (0x00000007)
+
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_WIDTH (8)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_WIDTH (8)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_WIDTH (8)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_MASK (0x000000FF)
+
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_WIDTH (1)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000001)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_BIT (0x00000001)
+
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_WIDTH (11)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000007FF)
+
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_WIDTH (6)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_MASK (0x0000003F)
+
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_WIDTH (3)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000007)
+
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_WIDTH (8)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000000FF)
+
+#define DMC_WAIT_C0_WAIT_C0_LSB (0)
+#define DMC_WAIT_C0_WAIT_C0_WIDTH (1)
+#define DMC_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define DMC_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C0_WAIT_C0_LSB (0)
+#define BRAM_WAIT_C0_WAIT_C0_WIDTH (1)
+#define BRAM_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define BRAM_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C1_WAIT_C1_LSB (0)
+#define BRAM_WAIT_C1_WAIT_C1_WIDTH (1)
+#define BRAM_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define BRAM_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define BRAM_WAIT_C2_WAIT_C2_LSB (0)
+#define BRAM_WAIT_C2_WAIT_C2_WIDTH (1)
+#define BRAM_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define BRAM_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define BRAM_WAIT_C3_WAIT_C3_LSB (0)
+#define BRAM_WAIT_C3_WAIT_C3_WIDTH (1)
+#define BRAM_WAIT_C3_WAIT_C3_MASK (0x00000001)
+#define BRAM_WAIT_C3_WAIT_C3_BIT (0x00000001)
+
+#define BRAM_WAIT_C4_WAIT_C4_LSB (0)
+#define BRAM_WAIT_C4_WAIT_C4_WIDTH (1)
+#define BRAM_WAIT_C4_WAIT_C4_MASK (0x00000001)
+#define BRAM_WAIT_C4_WAIT_C4_BIT (0x00000001)
+
+#define RAKE_WAIT_C0_WAIT_C0_LSB (0)
+#define RAKE_WAIT_C0_WAIT_C0_WIDTH (1)
+#define RAKE_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define RAKE_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define RAKE_WAIT_C1_WAIT_C1_LSB (0)
+#define RAKE_WAIT_C1_WAIT_C1_WIDTH (1)
+#define RAKE_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define RAKE_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define RAKE_WAIT_C2_WAIT_C2_LSB (0)
+#define RAKE_WAIT_C2_WAIT_C2_WIDTH (1)
+#define RAKE_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define RAKE_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_LSB (2)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_MASK (0x00000004)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_BIT (0x00000004)
+
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_LSB (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_MASK (0x00000002)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_BIT (0x00000002)
+
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_LSB (0)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_MASK (0x00000001)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_LSB (0)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_WIDTH (1)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_MASK (0x00000001)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_LSB (0)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_WIDTH (1)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_MASK (0x00000001)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_LSB (0)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_WIDTH (1)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_LSB (0)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_WIDTH (1)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_BIT (0x00000001)
+
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_LSB (6)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_MASK (0x00000040)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_BIT (0x00000040)
+
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_LSB (5)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_MASK (0x00000020)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_BIT (0x00000020)
+
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_LSB (4)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_MASK (0x00000010)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_BIT (0x00000010)
+
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_LSB (3)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_MASK (0x00000008)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_BIT (0x00000008)
+
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_LSB (2)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_MASK (0x00000004)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_BIT (0x00000004)
+
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_LSB (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_MASK (0x00000002)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_BIT (0x00000002)
+
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_LSB (0)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_MASK (0x00000001)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_BIT (0x00000001)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_LSB (6)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000040)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000040)
+
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_LSB (5)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000020)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000020)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_LSB (4)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_MASK (0x00000010)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_BIT (0x00000010)
+
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_LSB (3)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_MASK (0x00000008)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_BIT (0x00000008)
+
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_LSB (2)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_MASK (0x00000004)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_BIT (0x00000004)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_LSB (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000002)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000002)
+
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_LSB (0)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000001)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000001)
+
+
+#endif /*_CPH_MDRXSYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_95.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_95.h
new file mode 100644
index 0000000..fe7f56d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_95.h
@@ -0,0 +1,358 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+#define _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDRXAO_MEM_CONFIG_REG_BASE (0xA6120000)
+
+#define MDRXAO_MEM_CONFIG_end (MDRXAO_MEM_CONFIG_REG_BASE + 0xd4 + 1*4)
+
+
+
+#define DMC_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x0))
+#define SCQ_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4))
+#define BRP_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8))
+#define BIGRAM_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc))
+#define RAKE_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x10))
+#define DMC_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x14))
+#define SCQ_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x18))
+#define SCQ_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x1c))
+#define BRP_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x20))
+#define BRP_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x24))
+#define BRP_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x28))
+#define BRP_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x2c))
+#define BRP_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x30))
+#define BIGRAM_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x34))
+#define BIGRAM_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x38))
+#define BIGRAM_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x3c))
+#define BIGRAM_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x40))
+#define BIGRAM_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x44))
+#define RAKE_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x48))
+#define RAKE_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4c))
+#define RAKE_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x50))
+#define DMC_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x54))
+#define SCQ_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x58))
+#define BRP_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x5c))
+#define BIGRAM_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x60))
+#define RAKE_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x64))
+#define DMC_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x68))
+#define BRAM_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x74))
+#define BRAM_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x78))
+#define BRAM_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x7c))
+#define BRAM_WAIT_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x80))
+#define BRAM_WAIT_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x84))
+#define RAKE_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x9c))
+#define RAKE_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa0))
+#define RAKE_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa4))
+#define SRAM_CTRL_AO_IDLE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa8))
+#define RAKE_PM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb0))
+#define RAKE_PM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb4))
+#define SCQ_SPM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc0))
+#define SCQ_SPM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc4))
+#define CK_IDLE_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd0))
+#define CK_IDLE_DBG_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd4))
+
+
+#define DMC_SW_TYPE_GP_TYPE_LSB (0)
+#define DMC_SW_TYPE_GP_TYPE_WIDTH (1)
+#define DMC_SW_TYPE_GP_TYPE_MASK (0x00000001)
+#define DMC_SW_TYPE_GP_TYPE_BIT (0x00000001)
+
+#define SCQ_SW_TYPE_GP_TYPE_LSB (0)
+#define SCQ_SW_TYPE_GP_TYPE_WIDTH (11)
+#define SCQ_SW_TYPE_GP_TYPE_MASK (0x000007FF)
+
+#define BRP_SW_TYPE_GP_TYPE_LSB (0)
+#define BRP_SW_TYPE_GP_TYPE_WIDTH (6)
+#define BRP_SW_TYPE_GP_TYPE_MASK (0x0000003F)
+
+#define BIGRAM_SW_TYPE_GP_TYPE_LSB (0)
+#define BIGRAM_SW_TYPE_GP_TYPE_WIDTH (3)
+#define BIGRAM_SW_TYPE_GP_TYPE_MASK (0x00000007)
+
+#define RAKE_SW_TYPE_GP_TYPE_LSB (0)
+#define RAKE_SW_TYPE_GP_TYPE_WIDTH (8)
+#define RAKE_SW_TYPE_GP_TYPE_MASK (0x000000FF)
+
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_WIDTH (1)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000001)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_BIT (0x00000001)
+
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_WIDTH (11)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000007FF)
+
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_WIDTH (11)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000007FF)
+
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_WIDTH (6)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_WIDTH (6)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_WIDTH (6)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_WIDTH (6)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_WIDTH (6)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_MASK (0x0000003F)
+
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_WIDTH (3)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_WIDTH (3)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_WIDTH (3)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_WIDTH (3)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_WIDTH (3)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_MASK (0x00000007)
+
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_WIDTH (8)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_WIDTH (8)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_WIDTH (8)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_MASK (0x000000FF)
+
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_WIDTH (1)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000001)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_BIT (0x00000001)
+
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_WIDTH (11)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000007FF)
+
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_WIDTH (6)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_MASK (0x0000003F)
+
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_WIDTH (3)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000007)
+
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_WIDTH (8)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000000FF)
+
+#define DMC_WAIT_C0_WAIT_C0_LSB (0)
+#define DMC_WAIT_C0_WAIT_C0_WIDTH (1)
+#define DMC_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define DMC_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C0_WAIT_C0_LSB (0)
+#define BRAM_WAIT_C0_WAIT_C0_WIDTH (1)
+#define BRAM_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define BRAM_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C1_WAIT_C1_LSB (0)
+#define BRAM_WAIT_C1_WAIT_C1_WIDTH (1)
+#define BRAM_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define BRAM_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define BRAM_WAIT_C2_WAIT_C2_LSB (0)
+#define BRAM_WAIT_C2_WAIT_C2_WIDTH (1)
+#define BRAM_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define BRAM_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define BRAM_WAIT_C3_WAIT_C3_LSB (0)
+#define BRAM_WAIT_C3_WAIT_C3_WIDTH (1)
+#define BRAM_WAIT_C3_WAIT_C3_MASK (0x00000001)
+#define BRAM_WAIT_C3_WAIT_C3_BIT (0x00000001)
+
+#define BRAM_WAIT_C4_WAIT_C4_LSB (0)
+#define BRAM_WAIT_C4_WAIT_C4_WIDTH (1)
+#define BRAM_WAIT_C4_WAIT_C4_MASK (0x00000001)
+#define BRAM_WAIT_C4_WAIT_C4_BIT (0x00000001)
+
+#define RAKE_WAIT_C0_WAIT_C0_LSB (0)
+#define RAKE_WAIT_C0_WAIT_C0_WIDTH (1)
+#define RAKE_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define RAKE_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define RAKE_WAIT_C1_WAIT_C1_LSB (0)
+#define RAKE_WAIT_C1_WAIT_C1_WIDTH (1)
+#define RAKE_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define RAKE_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define RAKE_WAIT_C2_WAIT_C2_LSB (0)
+#define RAKE_WAIT_C2_WAIT_C2_WIDTH (1)
+#define RAKE_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define RAKE_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_LSB (2)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_MASK (0x00000004)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_BIT (0x00000004)
+
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_LSB (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_MASK (0x00000002)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_BIT (0x00000002)
+
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_LSB (0)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_MASK (0x00000001)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_LSB (0)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_WIDTH (1)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_MASK (0x00000001)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_LSB (0)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_WIDTH (1)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_MASK (0x00000001)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_LSB (0)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_WIDTH (1)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_LSB (0)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_WIDTH (1)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_BIT (0x00000001)
+
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_LSB (6)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_MASK (0x00000040)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_BIT (0x00000040)
+
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_LSB (5)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_MASK (0x00000020)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_BIT (0x00000020)
+
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_LSB (4)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_MASK (0x00000010)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_BIT (0x00000010)
+
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_LSB (3)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_MASK (0x00000008)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_BIT (0x00000008)
+
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_LSB (2)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_MASK (0x00000004)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_BIT (0x00000004)
+
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_LSB (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_MASK (0x00000002)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_BIT (0x00000002)
+
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_LSB (0)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_MASK (0x00000001)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_BIT (0x00000001)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_LSB (6)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000040)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000040)
+
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_LSB (5)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000020)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000020)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_LSB (4)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_MASK (0x00000010)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_BIT (0x00000010)
+
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_LSB (3)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_MASK (0x00000008)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_BIT (0x00000008)
+
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_LSB (2)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_MASK (0x00000004)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_BIT (0x00000004)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_LSB (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000002)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000002)
+
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_LSB (0)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000001)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000001)
+
+
+#endif /*_CPH_MDRXSYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_97.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_97.h
new file mode 100644
index 0000000..ddf18ec
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_97.h
@@ -0,0 +1,205 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+#define _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDRXAO_MEM_CONFIG_REG_BASE (0xA8110000)
+
+#define MDRXAO_MEM_CONFIG_end (MDRXAO_MEM_CONFIG_REG_BASE + 0x9c + 1*4)
+
+
+
+#define RAKE_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x0))
+#define RAKE_WAIT_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4))
+#define RAKE_GROUP_PWDN_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8))
+#define RAKE_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc))
+#define RAKE_SW_PWDN_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x10))
+#define RAKE_SW_PWDN_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x14))
+#define RAKE_SW_PWDN_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x18))
+#define INRMM_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x1c))
+#define INRMM_WAIT_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x20))
+#define INRMM_GROUP_PWDN_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x24))
+#define INRMM_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x28))
+#define INRMM_SW_PWDN_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x2c))
+#define INRMM_SW_PWDN_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x30))
+#define INRMM_SW_PWDN_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x34))
+#define INRMM_SW_PWDN_3_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x38))
+#define INRMM_SW_PWDN_4_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x3c))
+#define INRMM_SW_PWDN_5_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x40))
+#define INRMM_SW_PWDN_6_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x44))
+#define INRMM_SW_PWDN_7_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x48))
+#define BRP_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4c))
+#define BRP_WAIT_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x50))
+#define BRP_GROUP_PWDN_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x54))
+#define BRP_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x58))
+#define BRP_SW_PWDN_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x5c))
+#define BRP_SW_PWDN_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x60))
+#define BRP_SW_PWDN_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x64))
+#define BRP_SW_PWDN_3_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x68))
+#define BRP_SW_PWDN_4_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x6C))
+#define MDRXSYS_EFUSE_S2P_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x70))
+#define MDRXSYS_EFUSE_S2P_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x74))
+#define MDRXSYS_EFUSE_S2P_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x78))
+#define MDRXSYS_EFUSE_S2P_3_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x7c))
+#define MDRXSYS_EFUSE_S2P_4_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x80))
+#define MDRXSYS_EFUSE_S2P_5_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x84))
+#define MDRXSYS_EFUSE_S2P_6_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x88))
+#define MDRXSYS_EFUSE_S2P_7_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8C))
+#define MDRXSYS_EFUSE_S2P_8_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x90))
+#define MDRXSYS_EFUSE_S2P_9_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x94))
+#define MDRXSYS_EFUSE_S2P_10_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x98))
+#define MDRXSYS_EFUSE_S2P_RX_RESET_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x9C))
+
+
+#define RAKE_SW_TYPE_LSB (0)
+#define RAKE_SW_TYPE_WIDTH (7)
+#define RAKE_SW_TYPE_MASK (0x0000007F)
+#define RAKE_SW_TYPE_BIT (0x0000007F)
+
+#define RAKE_SW_PWDN_0_ADDR_LSB (0)
+#define RAKE_SW_PWDN_0_WIDTH (7)
+#define RAKE_SW_PWDN_0_MASK (0x0000007F)
+#define RAKE_SW_PWDN_0_BIT (0x0000007F)
+
+#define RAKE_SW_PWDN_1_ADDR_LSB (0)
+#define RAKE_SW_PWDN_1_WIDTH (7)
+#define RAKE_SW_PWDN_1_MASK (0x0000007F)
+#define RAKE_SW_PWDN_1_BIT (0x0000007F)
+
+#define RAKE_SW_PWDN_2_ADDR_LSB (0)
+#define RAKE_SW_PWDN_2_WIDTH (7)
+#define RAKE_SW_PWDN_2_MASK (0x0000007F)
+#define RAKE_SW_PWDN_2_BIT (0x0000007F)
+
+#define INRMM_SW_TYPE_LSB (0)
+#define INRMM_SW_TYPE_WIDTH (15)
+#define INRMM_SW_TYPE_MASK (0x00007FFF)
+#define INRMM_SW_TYPE_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_0_ADDR_LSB (0)
+#define INRMM_SW_PWDN_0_WIDTH (15)
+#define INRMM_SW_PWDN_0_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_0_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_1_ADDR_LSB (0)
+#define INRMM_SW_PWDN_1_WIDTH (15)
+#define INRMM_SW_PWDN_1_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_1_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_2_ADDR_LSB (0)
+#define INRMM_SW_PWDN_2_WIDTH (15)
+#define INRMM_SW_PWDN_2_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_2_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_3_ADDR_LSB (0)
+#define INRMM_SW_PWDN_3_WIDTH (15)
+#define INRMM_SW_PWDN_3_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_3_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_4_ADDR_LSB (0)
+#define INRMM_SW_PWDN_4_WIDTH (15)
+#define INRMM_SW_PWDN_4_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_4_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_5_ADDR_LSB (0)
+#define INRMM_SW_PWDN_5_WIDTH (15)
+#define INRMM_SW_PWDN_5_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_5_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_6_ADDR_LSB (0)
+#define INRMM_SW_PWDN_6_WIDTH (15)
+#define INRMM_SW_PWDN_6_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_6_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_7_ADDR_LSB (0)
+#define INRMM_SW_PWDN_7_WIDTH (15)
+#define INRMM_SW_PWDN_7_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_7_BIT (0x00007FFF)
+
+#define BRP_SW_TYPE_LSB (0)
+#define BRP_SW_TYPE_WIDTH (8)
+#define BRP_SW_TYPE_MASK (0x000000FF)
+#define BRP_SW_TYPE_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_0_ADDR_LSB (0)
+#define BRP_SW_PWDN_0_WIDTH (8)
+#define BRP_SW_PWDN_0_MASK (0x000000FF)
+#define BRP_SW_PWDN_0_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_1_ADDR_LSB (0)
+#define BRP_SW_PWDN_1_WIDTH (8)
+#define BRP_SW_PWDN_1_MASK (0x000000FF)
+#define BRP_SW_PWDN_1_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_2_ADDR_LSB (0)
+#define BRP_SW_PWDN_2_WIDTH (8)
+#define BRP_SW_PWDN_2_MASK (0x000000FF)
+#define BRP_SW_PWDN_2_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_3_ADDR_LSB (0)
+#define BRP_SW_PWDN_3_WIDTH (8)
+#define BRP_SW_PWDN_3_MASK (0x000000FF)
+#define BRP_SW_PWDN_3_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_4_ADDR_LSB (0)
+#define BRP_SW_PWDN_4_WIDTH (8)
+#define BRP_SW_PWDN_4_MASK (0x000000FF)
+#define BRP_SW_PWDN_4_BIT (0x000000FF)
+
+#define BRP_WAIT_ADDR_C3 (0x00000008)
+#define BRP_WAIT_ADDR_C4 (0x00000010)
+
+#define INRMM_WAIT_ADDR_C3 (0x00000008)
+#define INRMM_WAIT_ADDR_C4 (0x00000010)
+
+#define RAKE_WAIT_ADDR_C1 (0x00000002)
+#define RAKE_WAIT_ADDR_C2 (0x00000004)
+
+
+
+
+#endif /*_CPH_MDRXSYS_MEM_CONFIG_REG_H_*/
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg.h b/mcu/interface/l1/cl1/common/HW/cphmrsg.h
new file mode 100644
index 0000000..8bfa90e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphmrsg_93.h"
+#elif defined(__MD95__)
+#include "cphmrsg_95.h"
+#elif defined(__MD97__)
+#include "cphmrsg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg_93.h b/mcu/interface/l1/cl1/common/HW/cphmrsg_93.h
new file mode 100644
index 0000000..8e7ac2d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg_93.h
@@ -0,0 +1,243 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MRSG_H_
+#define _CPH_MRSG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MRSG_REG_BASE (0xA7110000)
+
+#define MRSG_end (MRSG_REG_BASE + 0x00000038 + 1*4)
+
+
+
+#define MRSG_PUMP_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000000))
+#define MRSG_IQ_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000008))
+#define MRSG_IQ_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000000C))
+#define MRSG_IQ_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000010))
+#define MRSG_FIFO_UFLOW ((APBADDR32)(MRSG_REG_BASE + 0x00000014))
+#define MRSG_RSSI_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000018))
+#define MRSG_RSSI_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000001C))
+#define MRSG_RSSI_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000020))
+#define MRSG_MODE_SWITCH ((APBADDR32)(MRSG_REG_BASE + 0x00000024))
+#define MRSG_SW_RST ((APBADDR32)(MRSG_REG_BASE + 0x00000028))
+#define MRSG_DDR_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x0000002C))
+#define MRSG_CHECKSUM_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000030))
+#define MRSG_CHECKSUM_LEN ((APBADDR32)(MRSG_REG_BASE + 0x00000034))
+#define MRSG_CHECKSUM ((APBADDR32)(MRSG_REG_BASE + 0x00000038))
+
+
+#define MRSG_PUMP_CTRL_PUMP_EN_LSB (0)
+#define MRSG_PUMP_CTRL_PUMP_EN_WIDTH (1)
+#define MRSG_PUMP_CTRL_PUMP_EN_MASK (0x00000001)
+#define MRSG_PUMP_CTRL_PUMP_EN_BIT (0x00000001)
+
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_LSB (0)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_WIDTH (32)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_IQ_LENGTH_IQ_LENGTH_LSB (0)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_WIDTH (24)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_MASK (0x00FFFFFF)
+
+#define MRSG_IQ_PARA_DLY_A1C1_LSB (7)
+#define MRSG_IQ_PARA_DLY_A1C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A1C1_MASK (0x00000380)
+
+#define MRSG_IQ_PARA_RSH_A1C1_LSB (5)
+#define MRSG_IQ_PARA_RSH_A1C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A1C1_MASK (0x00000060)
+
+#define MRSG_IQ_PARA_DLY_A0C1_LSB (2)
+#define MRSG_IQ_PARA_DLY_A0C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A0C1_MASK (0x0000001C)
+
+#define MRSG_IQ_PARA_RSH_A0C1_LSB (0)
+#define MRSG_IQ_PARA_RSH_A0C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A0C1_MASK (0x00000003)
+
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_LSB (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_MASK (0x00000002)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_BIT (0x00000002)
+
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_LSB (0)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_MASK (0x00000001)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_BIT (0x00000001)
+
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_LSB (0)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_WIDTH (32)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_LSB (0)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_WIDTH (16)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_MASK (0x0000FFFF)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_LSB (13)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_MASK (0x0000E000)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_LSB (8)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_MASK (0x00001F00)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_LSB (5)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_MASK (0x000000E0)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_LSB (0)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_MASK (0x0000001F)
+
+#define MRSG_MODE_SWITCH_RXD_ON_LSB (15)
+#define MRSG_MODE_SWITCH_RXD_ON_WIDTH (1)
+#define MRSG_MODE_SWITCH_RXD_ON_MASK (0x00008000)
+#define MRSG_MODE_SWITCH_RXD_ON_BIT (0x00008000)
+
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_LSB (13)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_MASK (0x00002000)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_BIT (0x00002000)
+
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_LSB (12)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_MASK (0x00001000)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_BIT (0x00001000)
+
+#define MRSG_MODE_SWITCH_PCH_W_LSB (11)
+#define MRSG_MODE_SWITCH_PCH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_MASK (0x00000800)
+#define MRSG_MODE_SWITCH_PCH_W_BIT (0x00000800)
+
+#define MRSG_MODE_SWITCH_DFE_DBG_LSB (10)
+#define MRSG_MODE_SWITCH_DFE_DBG_WIDTH (1)
+#define MRSG_MODE_SWITCH_DFE_DBG_MASK (0x00000400)
+#define MRSG_MODE_SWITCH_DFE_DBG_BIT (0x00000400)
+
+#define MRSG_MODE_SWITCH_INR_L_LSB (9)
+#define MRSG_MODE_SWITCH_INR_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_L_MASK (0x00000200)
+#define MRSG_MODE_SWITCH_INR_L_BIT (0x00000200)
+
+#define MRSG_MODE_SWITCH_INR_Cdo_LSB (8)
+#define MRSG_MODE_SWITCH_INR_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_Cdo_MASK (0x00000100)
+#define MRSG_MODE_SWITCH_INR_Cdo_BIT (0x00000100)
+
+#define MRSG_MODE_SWITCH_INR_C1x_LSB (7)
+#define MRSG_MODE_SWITCH_INR_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_C1x_MASK (0x00000080)
+#define MRSG_MODE_SWITCH_INR_C1x_BIT (0x00000080)
+
+#define MRSG_MODE_SWITCH_INR_T_LSB (6)
+#define MRSG_MODE_SWITCH_INR_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_T_MASK (0x00000040)
+#define MRSG_MODE_SWITCH_INR_T_BIT (0x00000040)
+
+#define MRSG_MODE_SWITCH_INR_W_LSB (5)
+#define MRSG_MODE_SWITCH_INR_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_W_MASK (0x00000020)
+#define MRSG_MODE_SWITCH_INR_W_BIT (0x00000020)
+
+#define MRSG_MODE_SWITCH_CSH_L_LSB (4)
+#define MRSG_MODE_SWITCH_CSH_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_L_MASK (0x00000010)
+#define MRSG_MODE_SWITCH_CSH_L_BIT (0x00000010)
+
+#define MRSG_MODE_SWITCH_CSH_Cdo_LSB (3)
+#define MRSG_MODE_SWITCH_CSH_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_Cdo_MASK (0x00000008)
+#define MRSG_MODE_SWITCH_CSH_Cdo_BIT (0x00000008)
+
+#define MRSG_MODE_SWITCH_CSH_C1x_LSB (2)
+#define MRSG_MODE_SWITCH_CSH_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_C1x_MASK (0x00000004)
+#define MRSG_MODE_SWITCH_CSH_C1x_BIT (0x00000004)
+
+#define MRSG_MODE_SWITCH_CSH_T_LSB (1)
+#define MRSG_MODE_SWITCH_CSH_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_T_MASK (0x00000002)
+#define MRSG_MODE_SWITCH_CSH_T_BIT (0x00000002)
+
+#define MRSG_MODE_SWITCH_CSH_W_LSB (0)
+#define MRSG_MODE_SWITCH_CSH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_W_MASK (0x00000001)
+#define MRSG_MODE_SWITCH_CSH_W_BIT (0x00000001)
+
+#define MRSG_SW_RST_RST_LSB (0)
+#define MRSG_SW_RST_RST_WIDTH (1)
+#define MRSG_SW_RST_RST_MASK (0x00000001)
+#define MRSG_SW_RST_RST_BIT (0x00000001)
+
+#define MRSG_DDR_CTRL_DDR_ON_LSB (0)
+#define MRSG_DDR_CTRL_DDR_ON_WIDTH (1)
+#define MRSG_DDR_CTRL_DDR_ON_MASK (0x00000001)
+#define MRSG_DDR_CTRL_DDR_ON_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_CTRL_checksum_done_LSB (31)
+#define MRSG_CHECKSUM_CTRL_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_checksum_done_MASK (0x80000000)
+#define MRSG_CHECKSUM_CTRL_checksum_done_BIT (0x80000000)
+
+#define MRSG_CHECKSUM_CTRL_start_checksum_LSB (0)
+#define MRSG_CHECKSUM_CTRL_start_checksum_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_start_checksum_MASK (0x00000001)
+#define MRSG_CHECKSUM_CTRL_start_checksum_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_LEN_checksum_len_LSB (0)
+#define MRSG_CHECKSUM_LEN_checksum_len_WIDTH (32)
+#define MRSG_CHECKSUM_LEN_checksum_len_MASK (0xFFFFFFFF)
+
+#define MRSG_CHECKSUM_tx_checksum_LSB (16)
+#define MRSG_CHECKSUM_tx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_tx_checksum_MASK (0xFFFF0000)
+
+#define MRSG_CHECKSUM_rx_checksum_LSB (0)
+#define MRSG_CHECKSUM_rx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_rx_checksum_MASK (0x0000FFFF)
+
+
+#endif //#ifndef _CPH_MRSG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg_95.h b/mcu/interface/l1/cl1/common/HW/cphmrsg_95.h
new file mode 100644
index 0000000..e421059
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg_95.h
@@ -0,0 +1,266 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MRSG_H_
+#define _CPH_MRSG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MRSG_REG_BASE (0xA7110000)
+
+#define MRSG_end (MRSG_REG_BASE + 0x00000040 + 1*4)
+
+
+
+#define MRSG_PUMP_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000000))
+#define MRSG_IQ_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000008))
+#define MRSG_IQ_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000000C))
+#define MRSG_IQ_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000010))
+#define MRSG_FIFO_UFLOW ((APBADDR32)(MRSG_REG_BASE + 0x00000014))
+#define MRSG_RSSI_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000018))
+#define MRSG_RSSI_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000001C))
+#define MRSG_RSSI_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000020))
+#define MRSG_MODE_SWITCH ((APBADDR32)(MRSG_REG_BASE + 0x00000024))
+#define MRSG_SW_RST ((APBADDR32)(MRSG_REG_BASE + 0x00000028))
+#define MRSG_DDR_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x0000002C))
+#define MRSG_CHECKSUM_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000030))
+#define MRSG_CHECKSUM_LEN ((APBADDR32)(MRSG_REG_BASE + 0x00000034))
+#define MRSG_CHECKSUM ((APBADDR32)(MRSG_REG_BASE + 0x00000038))
+#define MRSG_TICKGEN_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000040))
+
+
+#define MRSG_PUMP_CTRL_PUMP_EN_LSB (0)
+#define MRSG_PUMP_CTRL_PUMP_EN_WIDTH (1)
+#define MRSG_PUMP_CTRL_PUMP_EN_MASK (0x00000001)
+#define MRSG_PUMP_CTRL_PUMP_EN_BIT (0x00000001)
+
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_LSB (0)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_WIDTH (32)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_IQ_LENGTH_IQ_LENGTH_LSB (0)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_WIDTH (24)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_MASK (0x00FFFFFF)
+
+#define MRSG_IQ_PARA_DLY_A1C1_LSB (7)
+#define MRSG_IQ_PARA_DLY_A1C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A1C1_MASK (0x00000380)
+
+#define MRSG_IQ_PARA_RSH_A1C1_LSB (5)
+#define MRSG_IQ_PARA_RSH_A1C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A1C1_MASK (0x00000060)
+
+#define MRSG_IQ_PARA_DLY_A0C1_LSB (2)
+#define MRSG_IQ_PARA_DLY_A0C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A0C1_MASK (0x0000001C)
+
+#define MRSG_IQ_PARA_RSH_A0C1_LSB (0)
+#define MRSG_IQ_PARA_RSH_A0C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A0C1_MASK (0x00000003)
+
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_LSB (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_MASK (0x00000002)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_BIT (0x00000002)
+
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_LSB (0)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_MASK (0x00000001)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_BIT (0x00000001)
+
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_LSB (0)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_WIDTH (32)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_LSB (0)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_WIDTH (16)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_MASK (0x0000FFFF)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_LSB (13)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_MASK (0x0000E000)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_LSB (8)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_MASK (0x00001F00)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_LSB (5)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_MASK (0x000000E0)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_LSB (0)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_MASK (0x0000001F)
+
+#define MRSG_MODE_SWITCH_RXD_ON_LSB (15)
+#define MRSG_MODE_SWITCH_RXD_ON_WIDTH (1)
+#define MRSG_MODE_SWITCH_RXD_ON_MASK (0x00008000)
+#define MRSG_MODE_SWITCH_RXD_ON_BIT (0x00008000)
+
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_LSB (13)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_MASK (0x00002000)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_BIT (0x00002000)
+
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_LSB (12)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_MASK (0x00001000)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_BIT (0x00001000)
+
+#define MRSG_MODE_SWITCH_PCH_W_LSB (11)
+#define MRSG_MODE_SWITCH_PCH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_MASK (0x00000800)
+#define MRSG_MODE_SWITCH_PCH_W_BIT (0x00000800)
+
+#define MRSG_MODE_SWITCH_DFE_DBG_LSB (10)
+#define MRSG_MODE_SWITCH_DFE_DBG_WIDTH (1)
+#define MRSG_MODE_SWITCH_DFE_DBG_MASK (0x00000400)
+#define MRSG_MODE_SWITCH_DFE_DBG_BIT (0x00000400)
+
+#define MRSG_MODE_SWITCH_INR_L_LSB (9)
+#define MRSG_MODE_SWITCH_INR_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_L_MASK (0x00000200)
+#define MRSG_MODE_SWITCH_INR_L_BIT (0x00000200)
+
+#define MRSG_MODE_SWITCH_INR_Cdo_LSB (8)
+#define MRSG_MODE_SWITCH_INR_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_Cdo_MASK (0x00000100)
+#define MRSG_MODE_SWITCH_INR_Cdo_BIT (0x00000100)
+
+#define MRSG_MODE_SWITCH_INR_C1x_LSB (7)
+#define MRSG_MODE_SWITCH_INR_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_C1x_MASK (0x00000080)
+#define MRSG_MODE_SWITCH_INR_C1x_BIT (0x00000080)
+
+#define MRSG_MODE_SWITCH_INR_T_LSB (6)
+#define MRSG_MODE_SWITCH_INR_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_T_MASK (0x00000040)
+#define MRSG_MODE_SWITCH_INR_T_BIT (0x00000040)
+
+#define MRSG_MODE_SWITCH_INR_W_LSB (5)
+#define MRSG_MODE_SWITCH_INR_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_W_MASK (0x00000020)
+#define MRSG_MODE_SWITCH_INR_W_BIT (0x00000020)
+
+#define MRSG_MODE_SWITCH_CSH_L_LSB (4)
+#define MRSG_MODE_SWITCH_CSH_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_L_MASK (0x00000010)
+#define MRSG_MODE_SWITCH_CSH_L_BIT (0x00000010)
+
+#define MRSG_MODE_SWITCH_CSH_Cdo_LSB (3)
+#define MRSG_MODE_SWITCH_CSH_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_Cdo_MASK (0x00000008)
+#define MRSG_MODE_SWITCH_CSH_Cdo_BIT (0x00000008)
+
+#define MRSG_MODE_SWITCH_CSH_C1x_LSB (2)
+#define MRSG_MODE_SWITCH_CSH_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_C1x_MASK (0x00000004)
+#define MRSG_MODE_SWITCH_CSH_C1x_BIT (0x00000004)
+
+#define MRSG_MODE_SWITCH_CSH_T_LSB (1)
+#define MRSG_MODE_SWITCH_CSH_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_T_MASK (0x00000002)
+#define MRSG_MODE_SWITCH_CSH_T_BIT (0x00000002)
+
+#define MRSG_MODE_SWITCH_CSH_W_LSB (0)
+#define MRSG_MODE_SWITCH_CSH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_W_MASK (0x00000001)
+#define MRSG_MODE_SWITCH_CSH_W_BIT (0x00000001)
+
+#define MRSG_SW_RST_RST_LSB (0)
+#define MRSG_SW_RST_RST_WIDTH (1)
+#define MRSG_SW_RST_RST_MASK (0x00000001)
+#define MRSG_SW_RST_RST_BIT (0x00000001)
+
+#define MRSG_DDR_CTRL_DDR_ON_LSB (0)
+#define MRSG_DDR_CTRL_DDR_ON_WIDTH (1)
+#define MRSG_DDR_CTRL_DDR_ON_MASK (0x00000001)
+#define MRSG_DDR_CTRL_DDR_ON_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_LSB (31)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_MASK (0x80000000)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_BIT (0x80000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_LSB (30)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_MASK (0x40000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_BIT (0x40000000)
+
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_LSB (29)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_MASK (0x20000000)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_BIT (0x20000000)
+
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_LSB (28)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_MASK (0x10000000)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_BIT (0x10000000)
+
+#define MRSG_CHECKSUM_CTRL_start_checksum_LSB (0)
+#define MRSG_CHECKSUM_CTRL_start_checksum_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_start_checksum_MASK (0x00000001)
+#define MRSG_CHECKSUM_CTRL_start_checksum_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_LEN_checksum_len_LSB (0)
+#define MRSG_CHECKSUM_LEN_checksum_len_WIDTH (32)
+#define MRSG_CHECKSUM_LEN_checksum_len_MASK (0xFFFFFFFF)
+
+#define MRSG_CHECKSUM_tx_checksum_LSB (16)
+#define MRSG_CHECKSUM_tx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_tx_checksum_MASK (0xFFFF0000)
+
+#define MRSG_CHECKSUM_rx_checksum_LSB (0)
+#define MRSG_CHECKSUM_rx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_rx_checksum_MASK (0x0000FFFF)
+
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_LSB (4)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_WIDTH (1)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_MASK (0x00000010)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_BIT (0x00000010)
+
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_LSB (0)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_WIDTH (4)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_MASK (0x0000000F)
+
+#endif //#ifndef _CPH_MRSG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg_97.h b/mcu/interface/l1/cl1/common/HW/cphmrsg_97.h
new file mode 100644
index 0000000..ef1b0a1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg_97.h
@@ -0,0 +1,268 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MRSG_H_
+#define _CPH_MRSG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MRSG_REG_BASE (0xA8D60000)
+
+#define MRSG_end (MRSG_REG_BASE + 0x00000040 + 1*4)
+
+
+
+#define MRSG_PUMP_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000000))
+#define MRSG_IQ_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000008))
+#define MRSG_IQ_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000000C))
+#define MRSG_IQ_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000010))
+#define MRSG_FIFO_UFLOW ((APBADDR32)(MRSG_REG_BASE + 0x00000014))
+#define MRSG_RSSI_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000018))
+#define MRSG_RSSI_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000001C))
+#define MRSG_RSSI_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000020))
+#define MRSG_MODE_SWITCH ((APBADDR32)(MRSG_REG_BASE + 0x00000024))
+#define MRSG_SW_RST ((APBADDR32)(MRSG_REG_BASE + 0x00000028))
+#define MRSG_DDR_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x0000002C))
+#define MRSG_CHECKSUM_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000030))
+#define MRSG_CHECKSUM_LEN ((APBADDR32)(MRSG_REG_BASE + 0x00000034))
+#define MRSG_CHECKSUM ((APBADDR32)(MRSG_REG_BASE + 0x00000038))
+#define MRSG_TICKGEN_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000040))
+#define MRSG_LGAIN_DUR_LEN_GTH ((APBADDR32)(MRSG_REG_BASE + 0x00000044))
+
+
+
+#define MRSG_PUMP_CTRL_PUMP_EN_LSB (0)
+#define MRSG_PUMP_CTRL_PUMP_EN_WIDTH (1)
+#define MRSG_PUMP_CTRL_PUMP_EN_MASK (0x00000001)
+#define MRSG_PUMP_CTRL_PUMP_EN_BIT (0x00000001)
+
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_LSB (0)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_WIDTH (32)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_IQ_LENGTH_IQ_LENGTH_LSB (0)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_WIDTH (24)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_MASK (0x00FFFFFF)
+
+#define MRSG_IQ_PARA_DLY_A1C1_LSB (7)
+#define MRSG_IQ_PARA_DLY_A1C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A1C1_MASK (0x00000380)
+
+#define MRSG_IQ_PARA_RSH_A1C1_LSB (5)
+#define MRSG_IQ_PARA_RSH_A1C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A1C1_MASK (0x00000060)
+
+#define MRSG_IQ_PARA_DLY_A0C1_LSB (2)
+#define MRSG_IQ_PARA_DLY_A0C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A0C1_MASK (0x0000001C)
+
+#define MRSG_IQ_PARA_RSH_A0C1_LSB (0)
+#define MRSG_IQ_PARA_RSH_A0C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A0C1_MASK (0x00000003)
+
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_LSB (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_MASK (0x00000002)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_BIT (0x00000002)
+
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_LSB (0)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_MASK (0x00000001)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_BIT (0x00000001)
+
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_LSB (0)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_WIDTH (32)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_LSB (0)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_WIDTH (16)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_MASK (0x0000FFFF)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_LSB (13)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_MASK (0x0000E000)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_LSB (8)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_MASK (0x00001F00)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_LSB (5)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_MASK (0x000000E0)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_LSB (0)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_MASK (0x0000001F)
+
+#define MRSG_MODE_SWITCH_RXD_ON_LSB (15)
+#define MRSG_MODE_SWITCH_RXD_ON_WIDTH (1)
+#define MRSG_MODE_SWITCH_RXD_ON_MASK (0x00008000)
+#define MRSG_MODE_SWITCH_RXD_ON_BIT (0x00008000)
+
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_LSB (13)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_MASK (0x00002000)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_BIT (0x00002000)
+
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_LSB (12)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_MASK (0x00001000)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_BIT (0x00001000)
+
+#define MRSG_MODE_SWITCH_PCH_W_LSB (11)
+#define MRSG_MODE_SWITCH_PCH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_MASK (0x00000800)
+#define MRSG_MODE_SWITCH_PCH_W_BIT (0x00000800)
+
+#define MRSG_MODE_SWITCH_DFE_DBG_LSB (10)
+#define MRSG_MODE_SWITCH_DFE_DBG_WIDTH (1)
+#define MRSG_MODE_SWITCH_DFE_DBG_MASK (0x00000400)
+#define MRSG_MODE_SWITCH_DFE_DBG_BIT (0x00000400)
+
+#define MRSG_MODE_SWITCH_INR_L_LSB (9)
+#define MRSG_MODE_SWITCH_INR_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_L_MASK (0x00000200)
+#define MRSG_MODE_SWITCH_INR_L_BIT (0x00000200)
+
+#define MRSG_MODE_SWITCH_INR_Cdo_LSB (8)
+#define MRSG_MODE_SWITCH_INR_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_Cdo_MASK (0x00000100)
+#define MRSG_MODE_SWITCH_INR_Cdo_BIT (0x00000100)
+
+#define MRSG_MODE_SWITCH_INR_C1x_LSB (7)
+#define MRSG_MODE_SWITCH_INR_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_C1x_MASK (0x00000080)
+#define MRSG_MODE_SWITCH_INR_C1x_BIT (0x00000080)
+
+#define MRSG_MODE_SWITCH_INR_T_LSB (6)
+#define MRSG_MODE_SWITCH_INR_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_T_MASK (0x00000040)
+#define MRSG_MODE_SWITCH_INR_T_BIT (0x00000040)
+
+#define MRSG_MODE_SWITCH_INR_W_LSB (5)
+#define MRSG_MODE_SWITCH_INR_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_W_MASK (0x00000020)
+#define MRSG_MODE_SWITCH_INR_W_BIT (0x00000020)
+
+#define MRSG_MODE_SWITCH_CSH_L_LSB (4)
+#define MRSG_MODE_SWITCH_CSH_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_L_MASK (0x00000010)
+#define MRSG_MODE_SWITCH_CSH_L_BIT (0x00000010)
+
+#define MRSG_MODE_SWITCH_CSH_Cdo_LSB (3)
+#define MRSG_MODE_SWITCH_CSH_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_Cdo_MASK (0x00000008)
+#define MRSG_MODE_SWITCH_CSH_Cdo_BIT (0x00000008)
+
+#define MRSG_MODE_SWITCH_CSH_C1x_LSB (2)
+#define MRSG_MODE_SWITCH_CSH_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_C1x_MASK (0x00000004)
+#define MRSG_MODE_SWITCH_CSH_C1x_BIT (0x00000004)
+
+#define MRSG_MODE_SWITCH_CSH_T_LSB (1)
+#define MRSG_MODE_SWITCH_CSH_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_T_MASK (0x00000002)
+#define MRSG_MODE_SWITCH_CSH_T_BIT (0x00000002)
+
+#define MRSG_MODE_SWITCH_CSH_W_LSB (0)
+#define MRSG_MODE_SWITCH_CSH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_W_MASK (0x00000001)
+#define MRSG_MODE_SWITCH_CSH_W_BIT (0x00000001)
+
+#define MRSG_SW_RST_RST_LSB (0)
+#define MRSG_SW_RST_RST_WIDTH (1)
+#define MRSG_SW_RST_RST_MASK (0x00000001)
+#define MRSG_SW_RST_RST_BIT (0x00000001)
+
+#define MRSG_DDR_CTRL_DDR_ON_LSB (0)
+#define MRSG_DDR_CTRL_DDR_ON_WIDTH (1)
+#define MRSG_DDR_CTRL_DDR_ON_MASK (0x00000001)
+#define MRSG_DDR_CTRL_DDR_ON_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_LSB (31)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_MASK (0x80000000)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_BIT (0x80000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_LSB (30)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_MASK (0x40000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_BIT (0x40000000)
+
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_LSB (29)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_MASK (0x20000000)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_BIT (0x20000000)
+
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_LSB (28)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_MASK (0x10000000)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_BIT (0x10000000)
+
+#define MRSG_CHECKSUM_CTRL_start_checksum_LSB (0)
+#define MRSG_CHECKSUM_CTRL_start_checksum_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_start_checksum_MASK (0x00000001)
+#define MRSG_CHECKSUM_CTRL_start_checksum_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_LEN_checksum_len_LSB (0)
+#define MRSG_CHECKSUM_LEN_checksum_len_WIDTH (32)
+#define MRSG_CHECKSUM_LEN_checksum_len_MASK (0xFFFFFFFF)
+
+#define MRSG_CHECKSUM_tx_checksum_LSB (16)
+#define MRSG_CHECKSUM_tx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_tx_checksum_MASK (0xFFFF0000)
+
+#define MRSG_CHECKSUM_rx_checksum_LSB (0)
+#define MRSG_CHECKSUM_rx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_rx_checksum_MASK (0x0000FFFF)
+
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_LSB (4)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_WIDTH (1)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_MASK (0x00000010)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_BIT (0x00000002)
+
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_LSB (0)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_WIDTH (4)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_MASK (0x0000000F)
+
+#endif //#ifndef _CPH_MRSG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg.h
new file mode 100644
index 0000000..42a0ef6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphrakesysglbconreg_93.h"
+#elif defined(__MD95__)
+#include "cphrakesysglbconreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphrakesysglbconreg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_93.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_93.h
new file mode 100644
index 0000000..0d88fc0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_93.h
@@ -0,0 +1,367 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
+#define _CPH_RAKESYS_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RAKESYS_GLOBAL_CON_REG_BASE (0xAC200000)
+
+#define RAKESYS_GLOBAL_CON_end (RAKESYS_GLOBAL_CON_REG_BASE + 0x90 + 1*4)
+
+
+
+#define RAKE_PWR_AWARE ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x0))
+#define CG_CON ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x4))
+#define CG_SET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x8))
+#define CG_CLR ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xC))
+#define CG_CON_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x10))
+#define CG_SET_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x14))
+#define CG_CLR_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x18))
+#define CG_CON_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x20))
+#define CG_SET_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x24))
+#define CG_CLR_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x28))
+#define CG_CON_COMB ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x30))
+#define AXI_BUS_CFG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x40))
+#define RAKE_PM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x50))
+#define RAKE_DM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x54))
+#define RAKE_CLKCNT_CTRL ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x60))
+#define RAKE_CK_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x64))
+#define RAKE_IC_DIV3_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x68))
+#define RAKE_IC_32X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x6C))
+#define RAKE_IC_8X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x70))
+#define RAKE_DBGBUS_MUX ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x80))
+#define RAKE_DUMMY_REG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x90))
+
+
+#define RAKE_PWR_AWARE_RESERVED4_LSB (21)
+#define RAKE_PWR_AWARE_RESERVED4_WIDTH (11)
+#define RAKE_PWR_AWARE_RESERVED4_MASK (0xFFE00000)
+
+#define RAKE_PWR_AWARE_RESERVED3_LSB (20)
+#define RAKE_PWR_AWARE_RESERVED3_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED3_MASK (0x00100000)
+#define RAKE_PWR_AWARE_RESERVED3_BIT (0x00100000)
+
+#define RAKE_PWR_AWARE_BUS_ATB_LSB (19)
+#define RAKE_PWR_AWARE_BUS_ATB_WIDTH (1)
+#define RAKE_PWR_AWARE_BUS_ATB_MASK (0x00080000)
+#define RAKE_PWR_AWARE_BUS_ATB_BIT (0x00080000)
+
+#define RAKE_PWR_AWARE_RESERVED2_LSB (14)
+#define RAKE_PWR_AWARE_RESERVED2_WIDTH (5)
+#define RAKE_PWR_AWARE_RESERVED2_MASK (0x0007C000)
+
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_LSB (13)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_MASK (0x00002000)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_BIT (0x00002000)
+
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_LSB (12)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_MASK (0x00001000)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_BIT (0x00001000)
+
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_LSB (11)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_MASK (0x00000800)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_BIT (0x00000800)
+
+#define RAKE_PWR_AWARE_RESERVED1_LSB (10)
+#define RAKE_PWR_AWARE_RESERVED1_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED1_MASK (0x00000400)
+#define RAKE_PWR_AWARE_RESERVED1_BIT (0x00000400)
+
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_LSB (9)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_MASK (0x00000200)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_BIT (0x00000200)
+
+#define RAKE_PWR_AWARE_RAKE_LOADER_LSB (8)
+#define RAKE_PWR_AWARE_RAKE_LOADER_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOADER_MASK (0x00000100)
+#define RAKE_PWR_AWARE_RAKE_LOADER_BIT (0x00000100)
+
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_LSB (7)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_MASK (0x00000080)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_BIT (0x00000080)
+
+#define RAKE_PWR_AWARE_RAKE_BRIF_LSB (6)
+#define RAKE_PWR_AWARE_RAKE_BRIF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_BRIF_MASK (0x00000040)
+#define RAKE_PWR_AWARE_RAKE_BRIF_BIT (0x00000040)
+
+#define RAKE_PWR_AWARE_RESERVED0_LSB (5)
+#define RAKE_PWR_AWARE_RESERVED0_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED0_MASK (0x00000020)
+#define RAKE_PWR_AWARE_RESERVED0_BIT (0x00000020)
+
+#define RAKE_PWR_AWARE_RAKE_EXT_LSB (4)
+#define RAKE_PWR_AWARE_RAKE_EXT_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_EXT_MASK (0x00000010)
+#define RAKE_PWR_AWARE_RAKE_EXT_BIT (0x00000010)
+
+#define RAKE_PWR_AWARE_RAKE_DESP_LSB (3)
+#define RAKE_PWR_AWARE_RAKE_DESP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESP_MASK (0x00000008)
+#define RAKE_PWR_AWARE_RAKE_DESP_BIT (0x00000008)
+
+#define RAKE_PWR_AWARE_RAKE_DESIG_LSB (2)
+#define RAKE_PWR_AWARE_RAKE_DESIG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESIG_MASK (0x00000004)
+#define RAKE_PWR_AWARE_RAKE_DESIG_BIT (0x00000004)
+
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_LSB (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_MASK (0x00000002)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_BIT (0x00000002)
+
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_LSB (0)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_MASK (0x00000001)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_BIT (0x00000001)
+
+#define CG_CON_RESERVED5_LSB (2)
+#define CG_CON_RESERVED5_WIDTH (30)
+#define CG_CON_RESERVED5_MASK (0xFFFFFFFC)
+
+#define CG_CON_RAKE_BRIF_CG_CON_LSB (1)
+#define CG_CON_RAKE_BRIF_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_BRIF_CG_CON_MASK (0x00000002)
+#define CG_CON_RAKE_BRIF_CG_CON_BIT (0x00000002)
+
+#define CG_CON_RAKE_CORE_CG_CON_LSB (0)
+#define CG_CON_RAKE_CORE_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_CORE_CG_CON_MASK (0x00000001)
+#define CG_CON_RAKE_CORE_CG_CON_BIT (0x00000001)
+
+#define CG_SET_RESERVED6_LSB (2)
+#define CG_SET_RESERVED6_WIDTH (30)
+#define CG_SET_RESERVED6_MASK (0xFFFFFFFC)
+
+#define CG_SET_RAKE_BRIF_CG_CON_SET_LSB (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_MASK (0x00000002)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_BIT (0x00000002)
+
+#define CG_SET_RAKE_CORE_CG_CON_SET_LSB (0)
+#define CG_SET_RAKE_CORE_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_CORE_CG_CON_SET_MASK (0x00000001)
+#define CG_SET_RAKE_CORE_CG_CON_SET_BIT (0x00000001)
+
+#define CG_CLR_RESERVED7_LSB (2)
+#define CG_CLR_RESERVED7_WIDTH (30)
+#define CG_CLR_RESERVED7_MASK (0xFFFFFFFC)
+
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_LSB (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_MASK (0x00000002)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_BIT (0x00000002)
+
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_LSB (0)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_MASK (0x00000001)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_BIT (0x00000001)
+
+#define CG_CON_1X_RESERVED8_LSB (2)
+#define CG_CON_1X_RESERVED8_WIDTH (30)
+#define CG_CON_1X_RESERVED8_MASK (0xFFFFFFFC)
+
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_LSB (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_MASK (0x00000002)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_BIT (0x00000002)
+
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_LSB (0)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_MASK (0x00000001)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_BIT (0x00000001)
+
+#define CG_SET_1X_RESERVED9_LSB (2)
+#define CG_SET_1X_RESERVED9_WIDTH (30)
+#define CG_SET_1X_RESERVED9_MASK (0xFFFFFFFC)
+
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_LSB (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_MASK (0x00000002)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_BIT (0x00000002)
+
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_LSB (0)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_MASK (0x00000001)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_BIT (0x00000001)
+
+#define CG_CLR_1X_RESERVED10_LSB (2)
+#define CG_CLR_1X_RESERVED10_WIDTH (30)
+#define CG_CLR_1X_RESERVED10_MASK (0xFFFFFFFC)
+
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_LSB (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_MASK (0x00000002)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_BIT (0x00000002)
+
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_LSB (0)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_MASK (0x00000001)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_BIT (0x00000001)
+
+#define CG_CON_DO_RESERVED11_LSB (2)
+#define CG_CON_DO_RESERVED11_WIDTH (30)
+#define CG_CON_DO_RESERVED11_MASK (0xFFFFFFFC)
+
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_LSB (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_MASK (0x00000002)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_BIT (0x00000002)
+
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_LSB (0)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_MASK (0x00000001)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_BIT (0x00000001)
+
+#define CG_SET_DO_RESERVED12_LSB (2)
+#define CG_SET_DO_RESERVED12_WIDTH (30)
+#define CG_SET_DO_RESERVED12_MASK (0xFFFFFFFC)
+
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_LSB (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_MASK (0x00000002)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_BIT (0x00000002)
+
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_LSB (0)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_MASK (0x00000001)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_BIT (0x00000001)
+
+#define CG_CLR_DO_RESERVED13_LSB (2)
+#define CG_CLR_DO_RESERVED13_WIDTH (30)
+#define CG_CLR_DO_RESERVED13_MASK (0xFFFFFFFC)
+
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_LSB (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_MASK (0x00000002)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_BIT (0x00000002)
+
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_LSB (0)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_MASK (0x00000001)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_BIT (0x00000001)
+
+#define CG_CON_COMB_RESERVED14_LSB (2)
+#define CG_CON_COMB_RESERVED14_WIDTH (30)
+#define CG_CON_COMB_RESERVED14_MASK (0xFFFFFFFC)
+
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_LSB (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_MASK (0x00000002)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_BIT (0x00000002)
+
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_LSB (0)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_MASK (0x00000001)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_BIT (0x00000001)
+
+#define AXI_BUS_CFG_RESERVED15_LSB (5)
+#define AXI_BUS_CFG_RESERVED15_WIDTH (27)
+#define AXI_BUS_CFG_RESERVED15_MASK (0xFFFFFFE0)
+
+#define AXI_BUS_CFG_SAMP_SEL_LSB (4)
+#define AXI_BUS_CFG_SAMP_SEL_WIDTH (1)
+#define AXI_BUS_CFG_SAMP_SEL_MASK (0x00000010)
+#define AXI_BUS_CFG_SAMP_SEL_BIT (0x00000010)
+
+#define AXI_BUS_CFG_SLV_SYNC_SEL_LSB (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define AXI_BUS_CFG_MST_SYNC_SEL_LSB (0)
+#define AXI_BUS_CFG_MST_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RAKE_PM_CHK_RAKE_PM_CHK_LSB (0)
+#define RAKE_PM_CHK_RAKE_PM_CHK_WIDTH (32)
+#define RAKE_PM_CHK_RAKE_PM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_DM_CHK_RAKE_DM_CHK_LSB (0)
+#define RAKE_DM_CHK_RAKE_DM_CHK_WIDTH (32)
+#define RAKE_DM_CHK_RAKE_DM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_LSB (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_MASK (0x00000002)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_BIT (0x00000002)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_LSB (0)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_MASK (0x00000001)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_BIT (0x00000001)
+
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_LSB (0)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_WIDTH (32)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_LSB (0)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_WIDTH (32)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_LSB (0)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_WIDTH (32)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_LSB (0)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_WIDTH (32)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_LSB (0)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_WIDTH (4)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_MASK (0x0000000F)
+
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_LSB (0)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_WIDTH (32)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_MASK (0xFFFFFFFF)
+
+
+#endif /*#ifndef _CPH_RAKESYS_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_95.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_95.h
new file mode 100644
index 0000000..0d88fc0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_95.h
@@ -0,0 +1,367 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
+#define _CPH_RAKESYS_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RAKESYS_GLOBAL_CON_REG_BASE (0xAC200000)
+
+#define RAKESYS_GLOBAL_CON_end (RAKESYS_GLOBAL_CON_REG_BASE + 0x90 + 1*4)
+
+
+
+#define RAKE_PWR_AWARE ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x0))
+#define CG_CON ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x4))
+#define CG_SET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x8))
+#define CG_CLR ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xC))
+#define CG_CON_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x10))
+#define CG_SET_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x14))
+#define CG_CLR_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x18))
+#define CG_CON_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x20))
+#define CG_SET_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x24))
+#define CG_CLR_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x28))
+#define CG_CON_COMB ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x30))
+#define AXI_BUS_CFG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x40))
+#define RAKE_PM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x50))
+#define RAKE_DM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x54))
+#define RAKE_CLKCNT_CTRL ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x60))
+#define RAKE_CK_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x64))
+#define RAKE_IC_DIV3_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x68))
+#define RAKE_IC_32X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x6C))
+#define RAKE_IC_8X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x70))
+#define RAKE_DBGBUS_MUX ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x80))
+#define RAKE_DUMMY_REG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x90))
+
+
+#define RAKE_PWR_AWARE_RESERVED4_LSB (21)
+#define RAKE_PWR_AWARE_RESERVED4_WIDTH (11)
+#define RAKE_PWR_AWARE_RESERVED4_MASK (0xFFE00000)
+
+#define RAKE_PWR_AWARE_RESERVED3_LSB (20)
+#define RAKE_PWR_AWARE_RESERVED3_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED3_MASK (0x00100000)
+#define RAKE_PWR_AWARE_RESERVED3_BIT (0x00100000)
+
+#define RAKE_PWR_AWARE_BUS_ATB_LSB (19)
+#define RAKE_PWR_AWARE_BUS_ATB_WIDTH (1)
+#define RAKE_PWR_AWARE_BUS_ATB_MASK (0x00080000)
+#define RAKE_PWR_AWARE_BUS_ATB_BIT (0x00080000)
+
+#define RAKE_PWR_AWARE_RESERVED2_LSB (14)
+#define RAKE_PWR_AWARE_RESERVED2_WIDTH (5)
+#define RAKE_PWR_AWARE_RESERVED2_MASK (0x0007C000)
+
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_LSB (13)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_MASK (0x00002000)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_BIT (0x00002000)
+
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_LSB (12)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_MASK (0x00001000)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_BIT (0x00001000)
+
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_LSB (11)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_MASK (0x00000800)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_BIT (0x00000800)
+
+#define RAKE_PWR_AWARE_RESERVED1_LSB (10)
+#define RAKE_PWR_AWARE_RESERVED1_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED1_MASK (0x00000400)
+#define RAKE_PWR_AWARE_RESERVED1_BIT (0x00000400)
+
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_LSB (9)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_MASK (0x00000200)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_BIT (0x00000200)
+
+#define RAKE_PWR_AWARE_RAKE_LOADER_LSB (8)
+#define RAKE_PWR_AWARE_RAKE_LOADER_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOADER_MASK (0x00000100)
+#define RAKE_PWR_AWARE_RAKE_LOADER_BIT (0x00000100)
+
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_LSB (7)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_MASK (0x00000080)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_BIT (0x00000080)
+
+#define RAKE_PWR_AWARE_RAKE_BRIF_LSB (6)
+#define RAKE_PWR_AWARE_RAKE_BRIF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_BRIF_MASK (0x00000040)
+#define RAKE_PWR_AWARE_RAKE_BRIF_BIT (0x00000040)
+
+#define RAKE_PWR_AWARE_RESERVED0_LSB (5)
+#define RAKE_PWR_AWARE_RESERVED0_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED0_MASK (0x00000020)
+#define RAKE_PWR_AWARE_RESERVED0_BIT (0x00000020)
+
+#define RAKE_PWR_AWARE_RAKE_EXT_LSB (4)
+#define RAKE_PWR_AWARE_RAKE_EXT_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_EXT_MASK (0x00000010)
+#define RAKE_PWR_AWARE_RAKE_EXT_BIT (0x00000010)
+
+#define RAKE_PWR_AWARE_RAKE_DESP_LSB (3)
+#define RAKE_PWR_AWARE_RAKE_DESP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESP_MASK (0x00000008)
+#define RAKE_PWR_AWARE_RAKE_DESP_BIT (0x00000008)
+
+#define RAKE_PWR_AWARE_RAKE_DESIG_LSB (2)
+#define RAKE_PWR_AWARE_RAKE_DESIG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESIG_MASK (0x00000004)
+#define RAKE_PWR_AWARE_RAKE_DESIG_BIT (0x00000004)
+
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_LSB (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_MASK (0x00000002)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_BIT (0x00000002)
+
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_LSB (0)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_MASK (0x00000001)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_BIT (0x00000001)
+
+#define CG_CON_RESERVED5_LSB (2)
+#define CG_CON_RESERVED5_WIDTH (30)
+#define CG_CON_RESERVED5_MASK (0xFFFFFFFC)
+
+#define CG_CON_RAKE_BRIF_CG_CON_LSB (1)
+#define CG_CON_RAKE_BRIF_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_BRIF_CG_CON_MASK (0x00000002)
+#define CG_CON_RAKE_BRIF_CG_CON_BIT (0x00000002)
+
+#define CG_CON_RAKE_CORE_CG_CON_LSB (0)
+#define CG_CON_RAKE_CORE_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_CORE_CG_CON_MASK (0x00000001)
+#define CG_CON_RAKE_CORE_CG_CON_BIT (0x00000001)
+
+#define CG_SET_RESERVED6_LSB (2)
+#define CG_SET_RESERVED6_WIDTH (30)
+#define CG_SET_RESERVED6_MASK (0xFFFFFFFC)
+
+#define CG_SET_RAKE_BRIF_CG_CON_SET_LSB (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_MASK (0x00000002)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_BIT (0x00000002)
+
+#define CG_SET_RAKE_CORE_CG_CON_SET_LSB (0)
+#define CG_SET_RAKE_CORE_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_CORE_CG_CON_SET_MASK (0x00000001)
+#define CG_SET_RAKE_CORE_CG_CON_SET_BIT (0x00000001)
+
+#define CG_CLR_RESERVED7_LSB (2)
+#define CG_CLR_RESERVED7_WIDTH (30)
+#define CG_CLR_RESERVED7_MASK (0xFFFFFFFC)
+
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_LSB (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_MASK (0x00000002)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_BIT (0x00000002)
+
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_LSB (0)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_MASK (0x00000001)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_BIT (0x00000001)
+
+#define CG_CON_1X_RESERVED8_LSB (2)
+#define CG_CON_1X_RESERVED8_WIDTH (30)
+#define CG_CON_1X_RESERVED8_MASK (0xFFFFFFFC)
+
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_LSB (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_MASK (0x00000002)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_BIT (0x00000002)
+
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_LSB (0)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_MASK (0x00000001)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_BIT (0x00000001)
+
+#define CG_SET_1X_RESERVED9_LSB (2)
+#define CG_SET_1X_RESERVED9_WIDTH (30)
+#define CG_SET_1X_RESERVED9_MASK (0xFFFFFFFC)
+
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_LSB (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_MASK (0x00000002)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_BIT (0x00000002)
+
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_LSB (0)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_MASK (0x00000001)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_BIT (0x00000001)
+
+#define CG_CLR_1X_RESERVED10_LSB (2)
+#define CG_CLR_1X_RESERVED10_WIDTH (30)
+#define CG_CLR_1X_RESERVED10_MASK (0xFFFFFFFC)
+
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_LSB (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_MASK (0x00000002)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_BIT (0x00000002)
+
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_LSB (0)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_MASK (0x00000001)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_BIT (0x00000001)
+
+#define CG_CON_DO_RESERVED11_LSB (2)
+#define CG_CON_DO_RESERVED11_WIDTH (30)
+#define CG_CON_DO_RESERVED11_MASK (0xFFFFFFFC)
+
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_LSB (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_MASK (0x00000002)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_BIT (0x00000002)
+
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_LSB (0)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_MASK (0x00000001)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_BIT (0x00000001)
+
+#define CG_SET_DO_RESERVED12_LSB (2)
+#define CG_SET_DO_RESERVED12_WIDTH (30)
+#define CG_SET_DO_RESERVED12_MASK (0xFFFFFFFC)
+
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_LSB (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_MASK (0x00000002)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_BIT (0x00000002)
+
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_LSB (0)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_MASK (0x00000001)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_BIT (0x00000001)
+
+#define CG_CLR_DO_RESERVED13_LSB (2)
+#define CG_CLR_DO_RESERVED13_WIDTH (30)
+#define CG_CLR_DO_RESERVED13_MASK (0xFFFFFFFC)
+
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_LSB (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_MASK (0x00000002)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_BIT (0x00000002)
+
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_LSB (0)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_MASK (0x00000001)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_BIT (0x00000001)
+
+#define CG_CON_COMB_RESERVED14_LSB (2)
+#define CG_CON_COMB_RESERVED14_WIDTH (30)
+#define CG_CON_COMB_RESERVED14_MASK (0xFFFFFFFC)
+
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_LSB (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_MASK (0x00000002)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_BIT (0x00000002)
+
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_LSB (0)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_MASK (0x00000001)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_BIT (0x00000001)
+
+#define AXI_BUS_CFG_RESERVED15_LSB (5)
+#define AXI_BUS_CFG_RESERVED15_WIDTH (27)
+#define AXI_BUS_CFG_RESERVED15_MASK (0xFFFFFFE0)
+
+#define AXI_BUS_CFG_SAMP_SEL_LSB (4)
+#define AXI_BUS_CFG_SAMP_SEL_WIDTH (1)
+#define AXI_BUS_CFG_SAMP_SEL_MASK (0x00000010)
+#define AXI_BUS_CFG_SAMP_SEL_BIT (0x00000010)
+
+#define AXI_BUS_CFG_SLV_SYNC_SEL_LSB (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define AXI_BUS_CFG_MST_SYNC_SEL_LSB (0)
+#define AXI_BUS_CFG_MST_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RAKE_PM_CHK_RAKE_PM_CHK_LSB (0)
+#define RAKE_PM_CHK_RAKE_PM_CHK_WIDTH (32)
+#define RAKE_PM_CHK_RAKE_PM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_DM_CHK_RAKE_DM_CHK_LSB (0)
+#define RAKE_DM_CHK_RAKE_DM_CHK_WIDTH (32)
+#define RAKE_DM_CHK_RAKE_DM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_LSB (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_MASK (0x00000002)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_BIT (0x00000002)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_LSB (0)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_MASK (0x00000001)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_BIT (0x00000001)
+
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_LSB (0)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_WIDTH (32)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_LSB (0)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_WIDTH (32)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_LSB (0)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_WIDTH (32)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_LSB (0)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_WIDTH (32)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_LSB (0)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_WIDTH (4)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_MASK (0x0000000F)
+
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_LSB (0)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_WIDTH (32)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_MASK (0xFFFFFFFF)
+
+
+#endif /*#ifndef _CPH_RAKESYS_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_97.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_97.h
new file mode 100644
index 0000000..267e6c2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_97.h
@@ -0,0 +1,504 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
+#define _CPH_RAKESYS_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RAKESYS_GLOBAL_CON_REG_BASE (0xACE00000)
+
+
+#define RAKESYS_GLOBAL_CON_end (RAKESYS_GLOBAL_CON_REG_BASE + 0xc0 + 1*4)
+
+
+
+
+#define RAKE_PWR_AWARE ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x0))
+#define CG_CON ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x4))
+#define CG_SET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x8))
+#define CG_CLR ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xC))
+#define CG_CON_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x10))
+#define CG_SET_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x14))
+#define CG_CLR_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x18))
+#define CG_CON_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x20))
+#define CG_SET_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x24))
+#define CG_CLR_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x28))
+#define CG_CON_COMB ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x30))
+#define CG_CON_RES ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x34))
+#define CG_SET_RES ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x38))
+#define CG_CLR_RES ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x3C))
+#define AXI_BUS_CFG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x40))
+#define RAKE_PM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x50))
+#define RAKE_DM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x54))
+#define RAKE_CLKCNT_CTRL ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x60))
+#define RAKE_CK_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x64))
+#define RAKE_IC_DIV3_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x68))
+#define RAKE_IC_32X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x6C))
+#define RAKE_IC_8X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x70))
+#define RAKE_DBGBUS_MUX ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x80))
+#define RAKE_DUMMY_REG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x90))
+#define RAKE_CPU_SW_RESET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xa0))
+#define AXI2SRAM_STATUS ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xb0))
+#define SCQ_AXI2SRAM_BFABLE_EN ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xc0))
+
+
+#define RAKE_PWR_AWARE_RESERVED4_LSB (21)
+#define RAKE_PWR_AWARE_RESERVED4_WIDTH (11)
+#define RAKE_PWR_AWARE_RESERVED4_MASK (0xFFE00000)
+
+#define RAKE_PWR_AWARE_RESERVED3_LSB (20)
+#define RAKE_PWR_AWARE_RESERVED3_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED3_MASK (0x00100000)
+#define RAKE_PWR_AWARE_RESERVED3_BIT (0x00100000)
+
+#define RAKE_PWR_AWARE_BUS_ATB_LSB (19)
+#define RAKE_PWR_AWARE_BUS_ATB_WIDTH (1)
+#define RAKE_PWR_AWARE_BUS_ATB_MASK (0x00080000)
+#define RAKE_PWR_AWARE_BUS_ATB_BIT (0x00080000)
+
+#define RAKE_PWR_AWARE_RESERVED2_LSB (14)
+#define RAKE_PWR_AWARE_RESERVED2_WIDTH (5)
+#define RAKE_PWR_AWARE_RESERVED2_MASK (0x0007C000)
+
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_LSB (13)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_MASK (0x00002000)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_BIT (0x00002000)
+
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_LSB (12)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_MASK (0x00001000)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_BIT (0x00001000)
+
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_LSB (11)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_MASK (0x00000800)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_BIT (0x00000800)
+
+#define RAKE_PWR_AWARE_RESERVED1_LSB (10)
+#define RAKE_PWR_AWARE_RESERVED1_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED1_MASK (0x00000400)
+#define RAKE_PWR_AWARE_RESERVED1_BIT (0x00000400)
+
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_LSB (9)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_MASK (0x00000200)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_BIT (0x00000200)
+
+#define RAKE_PWR_AWARE_RAKE_LOADER_LSB (8)
+#define RAKE_PWR_AWARE_RAKE_LOADER_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOADER_MASK (0x00000100)
+#define RAKE_PWR_AWARE_RAKE_LOADER_BIT (0x00000100)
+
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_LSB (7)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_MASK (0x00000080)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_BIT (0x00000080)
+
+#define RAKE_PWR_AWARE_RAKE_BRIF_LSB (6)
+#define RAKE_PWR_AWARE_RAKE_BRIF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_BRIF_MASK (0x00000040)
+#define RAKE_PWR_AWARE_RAKE_BRIF_BIT (0x00000040)
+
+#define RAKE_PWR_AWARE_RESERVED0_LSB (5)
+#define RAKE_PWR_AWARE_RESERVED0_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED0_MASK (0x00000020)
+#define RAKE_PWR_AWARE_RESERVED0_BIT (0x00000020)
+
+#define RAKE_PWR_AWARE_RAKE_EXT_LSB (4)
+#define RAKE_PWR_AWARE_RAKE_EXT_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_EXT_MASK (0x00000010)
+#define RAKE_PWR_AWARE_RAKE_EXT_BIT (0x00000010)
+
+#define RAKE_PWR_AWARE_RAKE_DESP_LSB (3)
+#define RAKE_PWR_AWARE_RAKE_DESP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESP_MASK (0x00000008)
+#define RAKE_PWR_AWARE_RAKE_DESP_BIT (0x00000008)
+
+#define RAKE_PWR_AWARE_RAKE_DESIG_LSB (2)
+#define RAKE_PWR_AWARE_RAKE_DESIG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESIG_MASK (0x00000004)
+#define RAKE_PWR_AWARE_RAKE_DESIG_BIT (0x00000004)
+
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_LSB (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_MASK (0x00000002)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_BIT (0x00000002)
+
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_LSB (0)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_MASK (0x00000001)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_BIT (0x00000001)
+
+#define CG_CON_RESERVED5_LSB (3)
+#define CG_CON_RESERVED5_WIDTH (29)
+#define CG_CON_RESERVED5_MASK (0xFFFFFFF8)
+
+#define CG_CON_RAKE_MEM_CG_CON_LSB (2)
+#define CG_CON_RAKE_MEM_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_MEM_CG_CON_MASK (0x00000004)
+#define CG_CON_RAKE_MEM_CG_CON_BIT (0x00000004)
+
+#define CG_CON_RAKE_BRIF_CG_CON_LSB (1)
+#define CG_CON_RAKE_BRIF_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_BRIF_CG_CON_MASK (0x00000002)
+#define CG_CON_RAKE_BRIF_CG_CON_BIT (0x00000002)
+
+#define CG_CON_RAKE_CORE_CG_CON_LSB (0)
+#define CG_CON_RAKE_CORE_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_CORE_CG_CON_MASK (0x00000001)
+#define CG_CON_RAKE_CORE_CG_CON_BIT (0x00000001)
+
+#define CG_SET_RESERVED6_LSB (3)
+#define CG_SET_RESERVED6_WIDTH (29)
+#define CG_SET_RESERVED6_MASK (0xFFFFFFF8)
+
+#define CG_SET_RAKE_MEM_CG_CON_SET_LSB (2)
+#define CG_SET_RAKE_MEM_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_MEM_CG_CON_SET_MASK (0x00000004)
+#define CG_SET_RAKE_MEM_CG_CON_SET_BIT (0x00000004)
+
+#define CG_SET_RAKE_BRIF_CG_CON_SET_LSB (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_MASK (0x00000002)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_BIT (0x00000002)
+
+#define CG_SET_RAKE_CORE_CG_CON_SET_LSB (0)
+#define CG_SET_RAKE_CORE_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_CORE_CG_CON_SET_MASK (0x00000001)
+#define CG_SET_RAKE_CORE_CG_CON_SET_BIT (0x00000001)
+
+#define CG_CLR_RESERVED7_LSB (3)
+#define CG_CLR_RESERVED7_WIDTH (29)
+#define CG_CLR_RESERVED7_MASK (0xFFFFFFF8)
+
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_LSB (2)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_MASK (0x00000004)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_BIT (0x00000004)
+
+#define CG_CLR_rake_brif_cg_con_clr_LSB (1)
+#define CG_CLR_rake_brif_cg_con_clr_WIDTH (1)
+#define CG_CLR_rake_brif_cg_con_clr_MASK (0x00000002)
+#define CG_CLR_rake_brif_cg_con_clr_BIT (0x00000002)
+
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_LSB (0)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_MASK (0x00000001)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_BIT (0x00000001)
+
+#define CG_CON_1X_RESERVED8_LSB (3)
+#define CG_CON_1X_RESERVED8_WIDTH (29)
+#define CG_CON_1X_RESERVED8_MASK (0xFFFFFFF8)
+
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_LSB (2)
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_MASK (0x00000004)
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_BIT (0x00000004)
+
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_LSB (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_MASK (0x00000002)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_BIT (0x00000002)
+
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_LSB (0)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_MASK (0x00000001)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_BIT (0x00000001)
+
+#define CG_SET_1X_RESERVED9_LSB (3)
+#define CG_SET_1X_RESERVED9_WIDTH (29)
+#define CG_SET_1X_RESERVED9_MASK (0xFFFFFFF8)
+
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_LSB (2)
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_MASK (0x00000004)
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_BIT (0x00000004)
+
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_LSB (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_MASK (0x00000002)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_BIT (0x00000002)
+
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_LSB (0)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_MASK (0x00000001)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_BIT (0x00000001)
+
+#define CG_CLR_1X_RESERVED10_LSB (3)
+#define CG_CLR_1X_RESERVED10_WIDTH (29)
+#define CG_CLR_1X_RESERVED10_MASK (0xFFFFFFF8)
+
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_LSB (2)
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_MASK (0x00000004)
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_BIT (0x00000004)
+
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_LSB (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_MASK (0x00000002)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_BIT (0x00000002)
+
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_LSB (0)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_MASK (0x00000001)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_BIT (0x00000001)
+
+#define CG_CON_DO_RESERVED11_LSB (3)
+#define CG_CON_DO_RESERVED11_WIDTH (29)
+#define CG_CON_DO_RESERVED11_MASK (0xFFFFFFF8)
+
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_LSB (2)
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_MASK (0x00000004)
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_BIT (0x00000004)
+
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_LSB (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_MASK (0x00000002)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_BIT (0x00000002)
+
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_LSB (0)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_MASK (0x00000001)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_BIT (0x00000001)
+
+#define CG_SET_DO_RESERVED12_LSB (3)
+#define CG_SET_DO_RESERVED12_WIDTH (29)
+#define CG_SET_DO_RESERVED12_MASK (0xFFFFFFF8)
+
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_LSB (2)
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_MASK (0x00000004)
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_BIT (0x00000004)
+
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_LSB (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_MASK (0x00000002)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_BIT (0x00000002)
+
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_LSB (0)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_MASK (0x00000001)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_BIT (0x00000001)
+
+#define CG_CLR_DO_RESERVED13_LSB (3)
+#define CG_CLR_DO_RESERVED13_WIDTH (29)
+#define CG_CLR_DO_RESERVED13_MASK (0xFFFFFFF8)
+
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_LSB (2)
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_MASK (0x00000004)
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_BIT (0x00000004)
+
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_LSB (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_MASK (0x00000002)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_BIT (0x00000002)
+
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_LSB (0)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_MASK (0x00000001)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_BIT (0x00000001)
+
+#define CG_CON_COMB_RESERVED14_LSB (3)
+#define CG_CON_COMB_RESERVED14_WIDTH (29)
+#define CG_CON_COMB_RESERVED14_MASK (0xFFFFFFF8)
+
+
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_LSB (2)
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_MASK (0x00000004)
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_BIT (0x00000004)
+
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_LSB (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_MASK (0x00000002)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_BIT (0x00000002)
+
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_LSB (0)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_MASK (0x00000001)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_BIT (0x00000001)
+
+#define CG_CON_RES_RESERVED15_LSB (3)
+#define CG_CON_RES_RESERVED15_WIDTH (29)
+#define CG_CON_RES_RESERVED15_MASK (0xFFFFFFF8)
+
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_LSB (2)
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_WIDTH (1)
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_MASK (0x00000004)
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_BIT (0x00000004)
+
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_LSB (1)
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_WIDTH (1)
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_MASK (0x00000002)
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_BIT (0x00000002)
+
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_LSB (0)
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_WIDTH (1)
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_MASK (0x00000001)
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_BIT (0x00000001)
+
+#define CG_SET_RES_RESERVED16_LSB (3)
+#define CG_SET_RES_RESERVED16_WIDTH (29)
+#define CG_SET_RES_RESERVED16_MASK (0xFFFFFFF8)
+
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_LSB (2)
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_WIDTH (1)
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_MASK (0x00000004)
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_BIT (0x00000004)
+
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_LSB (1)
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_WIDTH (1)
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_MASK (0x00000002)
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_BIT (0x00000002)
+
+
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_LSB (0)
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_WIDTH (1)
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_MASK (0x00000001)
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_BIT (0x00000001)
+
+#define CG_CLR_RES_RESERVED17_LSB (3)
+#define CG_CLR_RES_RESERVED17_WIDTH (29)
+#define CG_CLR_RES_RESERVED17_MASK (0xFFFFFFF8)
+
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_LSB (2)
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_WIDTH (1)
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_MASK (0x00000004)
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_BIT (0x00000004)
+
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_LSB (1)
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_WIDTH (1)
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_MASK (0x00000002)
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_BIT (0x00000002)
+
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_LSB (0)
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_WIDTH (1)
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_MASK (0x00000001)
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_BIT (0x00000001)
+
+#define AXI_BUS_CFG_RESERVED18_LSB (5)
+#define AXI_BUS_CFG_RESERVED18_WIDTH (27)
+#define AXI_BUS_CFG_RESERVED18_MASK (0xFFFFFFE0)
+
+#define AXI_BUS_CFG_SAMP_SEL_LSB (4)
+#define AXI_BUS_CFG_SAMP_SEL_WIDTH (1)
+#define AXI_BUS_CFG_SAMP_SEL_MASK (0x00000010)
+#define AXI_BUS_CFG_SAMP_SEL_BIT (0x00000010)
+
+#define AXI_BUS_CFG_SLV_SYNC_SEL_LSB (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define AXI_BUS_CFG_MST_SYNC_SEL_LSB (0)
+#define AXI_BUS_CFG_MST_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RAKE_PM_CHK_RAKE_PM_CHK_LSB (0)
+#define RAKE_PM_CHK_RAKE_PM_CHK_WIDTH (32)
+#define RAKE_PM_CHK_RAKE_PM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_DM_CHK_RAKE_DM_CHK_LSB (0)
+#define RAKE_DM_CHK_RAKE_DM_CHK_WIDTH (32)
+#define RAKE_DM_CHK_RAKE_DM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_LSB (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_MASK (0x00000002)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_BIT (0x00000002)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_LSB (0)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_MASK (0x00000001)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_BIT (0x00000001)
+
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_LSB (0)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_WIDTH (32)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_LSB (0)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_WIDTH (32)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_LSB (0)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_WIDTH (32)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_LSB (0)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_WIDTH (32)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_LSB (0)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_WIDTH (4)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_MASK (0x0000000F)
+
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_LSB (0)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_WIDTH (32)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_MASK (0xFFFFFFFF)
+
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_LSB (1)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_WIDTH (1)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_MASK (0x00000002)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_BIT (0x00000002)
+
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_LSB (0)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_WIDTH (1)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_MASK (0x00000001)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_BIT (0x00000001)
+
+#define AXI2SRAM_STATUS_AXI2SRAM_STATUS_LSB (0)
+#define AXI2SRAM_STATUS_AXI2SRAM_STATUS_WIDTH (32)
+#define AXI2SRAM_STATUS_AXI2SRAM_STATUS_MASK (0xFFFFFFFF)
+
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_LSB (0)
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_WIDTH (1)
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_MASK (0x00000001)
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_BIT (0x00000001)
+
+
+
+#endif //#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrtttxtimerreg.h b/mcu/interface/l1/cl1/common/HW/cphrtttxtimerreg.h
new file mode 100644
index 0000000..e8037fc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrtttxtimerreg.h
@@ -0,0 +1,341 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RTT_TX_TIMER_H_
+#define _CPH_RTT_TX_TIMER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define DFE_W_TTR_REG_BASE (0xA61A0000)
+#else
+#define DFE_W_TTR_REG_BASE (0xA8180000)
+#endif
+
+#define C1X_TTR_SR_OFFSET_0 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0000))
+#define C1X_TTR_SR_OFFSET_1 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0004))
+#define C1X_TTR_FORCE_TTR_MODE ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0010))
+#define C1X_TTR_PHASE_ACC_ADJ ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0020))
+#define C1X_TTR_U_TX_DATA_OFFSET ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0024))
+#define C1X_TTR_RX_TX_LOG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0050))
+#define C1X_TTR_RX_TIME_MON0 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0054))
+#define C1X_TTR_RX_TIME_MON1 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0058))
+#define C1X_TTR_TX_TIME_MON0 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x005C))
+#define C1X_TTR_TX_TIME_MON1 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0060))
+#define C1X_TTR_TX_TIME_MON2 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0064))
+#define C1X_TTR_CNT_ADJ ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0068))
+
+#define C1X_TTR_FRAME_OFFSET ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0070))
+#define C1X_TTR_TXRXDELAY ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0074))
+#define C1X_TTR_RA_DLY ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0078))
+
+#define C1X_TTR_CRP_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0080))
+#define C1X_TTR_CRP_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0084))
+
+#if defined(__MD93__)||defined(__MD95__)
+#define C1X_TTR_TXDFE_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0088))
+#define C1X_TTR_TXDFE_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x008C))
+#endif
+
+#define C1X_TTR_TXCRP_FIFO_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0090))
+#define C1X_TTR_TXCRP_FIFO_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0094))
+
+#if defined(__MD93__)||defined(__MD95__)
+#define C1X_TTR_TXDAC_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0098))
+#define C1X_TTR_TXDAC_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x009C))
+#endif
+
+#define C1X_TTR_TXBRP_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00C0))
+#define C1X_TTR_TXCRP_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00C4))
+#define C1X_TTR_KS_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00C8))
+
+#define C1X_TTR_FRM_BOUNDARY ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00D0))
+#define C1X_TTR_DEBUG_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00F0))
+
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0100))
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0110))
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0114))
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0118))
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x011C))
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0120))
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0124))
+#define C1X_TX_TIMER_TTR_WIN_DBG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x012c))
+#endif
+
+#define USE_RX_SR_OffSET_LSB (20)
+#define USE_RX_SR_OffSET_WIDTH (1)
+#define USE_RX_SR_OffSET_MASK (0x00100000)
+#define USE_RX_SR_OffSET_BIT (0x00100000)
+
+#define SR_OFFSET_LSB (0)
+#define SR_OFFSET_WIDTH (16)
+#define SR_OFFSET_MASK (0x0000FFFF)
+
+#define TX_CNT_WO_TX_DELAY_LSB (0)
+#define TX_CNT_WO_TX_DELAY_WIDTH (20)
+#define TX_CNT_WO_TX_DELAY_MASK (0x000FFFFF)
+
+#define TX_CNT_W_TX_DELAY_LSB (0)
+#define TX_CNT_W_TX_DELAY_WIDTH (20)
+#define TX_CNT_W_TX_DELAY_MASK (0x000FFFFF)
+
+#define FRAME_OFFSET_LSB (0)
+#define FRAME_OFFSET_WIDTH (20)
+#define FRAME_OFFSET_MASK (0x000FFFFF)
+
+#define TXRXDELAY_LSB (0)
+#define TXRXDELAY_WIDTH (20)
+#define TXRXDELAY_MASK (0x000FFFFF)
+
+#define RA_DLY_LSB (0)
+#define RA_DLY_WIDTH (20)
+#define RA_DLY_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXDFE_WIN_ON_CMPR_ON_LSB (28)
+#define TXDFE_WIN_ON_CMPR_ON_WIDTH (1)
+#define TXDFE_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define TXDFE_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define TXDFE_WIN_ON_TRG_EN_LSB (27)
+#define TXDFE_WIN_ON_TRG_EN_WIDTH (1)
+#define TXDFE_WIN_ON_TRG_EN_MASK (0x08000000)
+#define TXDFE_WIN_ON_TRG_EN_BIT (0x08000000)
+
+#define TXDFE_WIN_ON_SYSTEM_TIME_LSB (0)
+#define TXDFE_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define TXDFE_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXDFE_WIN_OFF_CMPR_ON_LSB (28)
+#define TXDFE_WIN_OFF_CMPR_ON_WIDTH (1)
+#define TXDFE_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define TXDFE_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TXDFE_WIN_OFF_TRG_EN_LSB (27)
+#define TXDFE_WIN_OFF_TRG_EN_WIDTH (1)
+#define TXDFE_WIN_OFF_TRG_EN_MASK (0x08000000)
+#define TXDFE_WIN_OFF_TRG_EN_BIT (0x08000000)
+
+#define TXDFE_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define TXDFE_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define TXDFE_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+#endif
+
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_LSB (28)
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_WIDTH (1)
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define TXCRP_FIFO_WIN_ON_TRG_EN_LSB (27)
+#define TXCRP_FIFO_WIN_ON_TRG_EN_WIDTH (1)
+#define TXCRP_FIFO_WIN_ON_TRG_EN_MASK (0x08000000)
+#define TXCRP_FIFO_WIN_ON_TRG_EN_BIT (0x08000000)
+
+#define TXCRP_FIFO_WIN_ON_SYSTEM_TIME_LSB (0)
+#define TXCRP_FIFO_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define TXCRP_FIFO_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_LSB (28)
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_WIDTH (1)
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_LSB (27)
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_WIDTH (1)
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_MASK (0x08000000)
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_BIT (0x08000000)
+
+#define TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXDAC_WIN_ON_CMPR_ON_LSB (28)
+#define TXDAC_WIN_ON_CMPR_ON_WIDTH (1)
+#define TXDAC_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define TXDAC_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define TXDAC_WIN_ON_TRG_EN_LSB (27)
+#define TXDAC_WIN_ON_TRG_EN_WIDTH (1)
+#define TXDAC_WIN_ON_TRG_EN_MASK (0x08000000)
+#define TXDAC_WIN_ON_TRG_EN_BIT (0x08000000)
+
+#define TXDAC_WIN_ON_SYSTEM_TIME_LSB (0)
+#define TXDAC_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define TXDAC_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXDAC_WIN_OFF_CMPR_ON_LSB (28)
+#define TXDAC_WIN_OFF_CMPR_ON_WIDTH (1)
+#define TXDAC_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define TXDAC_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TXDAC_WIN_OFF_TRG_EN_LSB (27)
+#define TXDAC_WIN_OFF_TRG_EN_WIDTH (1)
+#define TXDAC_WIN_OFF_TRG_EN_MASK (0x08000000)
+#define TXDAC_WIN_OFF_TRG_EN_BIT (0x08000000)
+
+#define TXDAC_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define TXDAC_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define TXDAC_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+#endif
+
+#define TXBRP_STR_CMPR_ON_LSB (28)
+#define TXBRP_STR_CMPR_ON_WIDTH (1)
+#define TXBRP_STR_CMPR_ON_MASK (0x10000000)
+#define TXBRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define TXBRP_STR_SINGLE_TRIGGER_LSB (27)
+#define TXBRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define TXBRP_STR_SINGLE_TRIGGER_MASK (0x08000000)
+#define TXBRP_STR_SINGLE_TRIGGER_BIT (0x08000000)
+
+#define TXBRP_STR_SYSTEM_TIME_LSB (0)
+#define TXBRP_STR_SYSTEM_TIME_WIDTH (20)
+#define TXBRP_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXCRP_STR_CMPR_ON_LSB (28)
+#define TXCRP_STR_CMPR_ON_WIDTH (1)
+#define TXCRP_STR_CMPR_ON_MASK (0x10000000)
+#define TXCRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define TXCRP_STR_SINGLE_TRIGGER_LSB (27)
+#define TXCRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define TXCRP_STR_SINGLE_TRIGGER_MASK (0x08000000)
+#define TXCRP_STR_SINGLE_TRIGGER_BIT (0x08000000)
+
+#define TXCRP_STR_SYSTEM_TIME_LSB (0)
+#define TXCRP_STR_SYSTEM_TIME_WIDTH (20)
+#define TXCRP_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define KS_STR_CMPR_ON_LSB (28)
+#define KS_STR_CMPR_ON_WIDTH (1)
+#define KS_STR_CMPR_ON_MASK (0x10000000)
+#define KS_STR_CMPR_ON_BIT (0x10000000)
+
+#define KS_STR_SINGLE_TRIGGER_LSB (27)
+#define KS_STR_SINGLE_TRIGGER_WIDTH (1)
+#define KS_STR_SINGLE_TRIGGER_MASK (0x08000000)
+#define KS_STR_SINGLE_TRIGGER_BIT (0x08000000)
+
+#define KS_STR_AUTO_TRIGGER_LSB (20)
+#define KS_STR_AUTO_TRIGGER_WIDTH (2)
+#define KS_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+#define KS_STR_SYSTEM_TIME_LSB (0)
+#define KS_STR_SYSTEM_TIME_WIDTH (20)
+#define KS_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_LSB (1)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_MASK (0x00000002)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_BIT (0x00000002)
+
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_BIT (0x00000001)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_LSB (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_MASK (0x00000002)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_BIT (0x00000001)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_WIDTH (32)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_MASK (0xFFFFFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_LSB (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_MASK (0x00000002)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_BIT (0x00000001)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_WIDTH (32)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_MASK (0xFFFFFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_LSB (28)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_MASK (0x10000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_BIT (0x10000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_LSB (27)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_MASK (0x08000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_BIT (0x08000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_WIDTH (20)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_LSB (28)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_MASK (0x10000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_BIT (0x10000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_LSB (27)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_MASK (0x08000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_BIT (0x08000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_WIDTH (20)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_BIT (0x00000001)
+#endif
+
+#endif //#ifndef _CPH_RTT_TX_TIMER_H_
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpbusconfig.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpbusconfig.h
new file mode 100644
index 0000000..a017072
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpbusconfig.h
@@ -0,0 +1,405 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_BUS_CONFIG_H_
+#define _CPH_RXBRP_BUS_CONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD95__)
+#define RXBRP_BUS_CONFIG_REG_BASE (0xAD160000)
+#else
+#define RXBRP_BUS_CONFIG_REG_BASE (0xAC960000)
+#endif
+
+#define RXBRP_BUS_CONFIG_end (RXBRP_BUS_CONFIG_REG_BASE + 0x00a4 + 1*4)
+
+
+
+#define RXBRP_BUS_CONFIG0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0000))
+#define RXBRP_BUS_CONFIG1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0004))
+#define RXBRP_BUS_CONFIG2 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0008))
+#define RXBRP_BUS_CONFIG3 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x000c))
+#define RXBRP_BUS_CONFIG4 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0010))
+#define RXBRP_BUS_CONFIG5 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0014))
+#define RXBRP_BUS_CONFIG6 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0018))
+#define RXBRP_BUS_CONFIG7 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x001c))
+#define RXBRP_BUS_CONFIG8 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0020))
+#define RXBRP_BUS_CONFIG9 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0024))
+#define RXBRP_BUS_CONFIG10 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0028))
+#define RXBRP_BUS_STATUS0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0030))
+#define RXBRP_BUS_STATUS1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0034))
+#define RXBRP_BUS_STATUS2 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0038))
+#define RXBRP_BUS_CONFIG11 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0040))
+#define RXBRP_BUS_CONFIG12 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0044))
+#define RXBRP_BUS_CONFIG13 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0048))
+#define RXBRP_BUS_CONFIG14 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x004c))
+#define RXBRP_SLV_BUS_CONFIG0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0080))
+#define RXBRP_SLV_BUS_STATUS0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x00a0))
+#define RXBRP_SLV_BUS_STATUS1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x00a4))
+
+
+#define RXBRP_BUS_CONFIG0_FLUSH_THRE_LSB (30)
+#define RXBRP_BUS_CONFIG0_FLUSH_THRE_WIDTH (2)
+#define RXBRP_BUS_CONFIG0_FLUSH_THRE_MASK (0xC0000000)
+
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_LSB (29)
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_MASK (0x20000000)
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_BIT (0x20000000)
+
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_LSB (28)
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_MASK (0x10000000)
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_BIT (0x10000000)
+
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_LSB (27)
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_MASK (0x08000000)
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_BIT (0x08000000)
+
+#define RXBRP_BUS_CONFIG0_DMA_MODE_LSB (26)
+#define RXBRP_BUS_CONFIG0_DMA_MODE_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_DMA_MODE_MASK (0x04000000)
+#define RXBRP_BUS_CONFIG0_DMA_MODE_BIT (0x04000000)
+
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_LSB (25)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_MASK (0x02000000)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_BIT (0x02000000)
+
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_LSB (24)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_MASK (0x01000000)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_BIT (0x01000000)
+
+#define RXBRP_BUS_CONFIG0_SPLIT_DIS_LSB (18)
+#define RXBRP_BUS_CONFIG0_SPLIT_DIS_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_SPLIT_DIS_MASK (0x00FC0000)
+
+#define RXBRP_BUS_CONFIG0_CHNL_DISABLE_LSB (12)
+#define RXBRP_BUS_CONFIG0_CHNL_DISABLE_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_CHNL_DISABLE_MASK (0x0003F000)
+
+#define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_LSB (6)
+#define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_MASK (0x00000FC0)
+
+#define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_LSB (0)
+#define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_MASK (0x0000003F)
+
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_LSB (30)
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_MASK (0x40000000)
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_BIT (0x40000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_LSB (29)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_MASK (0x20000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_BIT (0x20000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_LSB (28)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_MASK (0x10000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_BIT (0x10000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_LSB (27)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_MASK (0x08000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_BIT (0x08000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_LSB (26)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_MASK (0x04000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_BIT (0x04000000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_LSB (25)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_MASK (0x02000000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_BIT (0x02000000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_LSB (24)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_MASK (0x01000000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_BIT (0x01000000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_LSB (23)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_MASK (0x00800000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_BIT (0x00800000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_LSB (22)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_MASK (0x00400000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_BIT (0x00400000)
+
+#define RXBRP_BUS_CONFIG1_RG_DBG_SEL_LSB (12)
+#define RXBRP_BUS_CONFIG1_RG_DBG_SEL_WIDTH (8)
+#define RXBRP_BUS_CONFIG1_RG_DBG_SEL_MASK (0x000FF000)
+
+#define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_LSB (10)
+#define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_WIDTH (2)
+#define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_MASK (0x00000C00)
+
+#define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_LSB (8)
+#define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_WIDTH (2)
+#define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_MASK (0x00000300)
+
+#define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_LSB (2)
+#define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_WIDTH (4)
+#define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_MASK (0x0000003C)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_LSB (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_MASK (0x00000002)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_BIT (0x00000002)
+
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_LSB (0)
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_MASK (0x00000001)
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_BIT (0x00000001)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_LSB (23)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_MASK (0x00800000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_BIT (0x00800000)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_LSB (22)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_MASK (0x00400000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_BIT (0x00400000)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_LSB (21)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_MASK (0x00200000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_BIT (0x00200000)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_LSB (20)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_MASK (0x00100000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_BIT (0x00100000)
+
+#define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_LSB (18)
+#define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_WIDTH (2)
+#define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_MASK (0x000C0000)
+
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_LSB (17)
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_MASK (0x00020000)
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_BIT (0x00020000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_LSB (16)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_MASK (0x00010000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_BIT (0x00010000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_LSB (15)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_MASK (0x00008000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_BIT (0x00008000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_LSB (14)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_MASK (0x00004000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_BIT (0x00004000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_LSB (13)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_MASK (0x00002000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_BIT (0x00002000)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_LSB (12)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_MASK (0x00001000)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_BIT (0x00001000)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_LSB (11)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_MASK (0x00000800)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_BIT (0x00000800)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_LSB (10)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_MASK (0x00000400)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_BIT (0x00000400)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_LSB (9)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_MASK (0x00000200)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_BIT (0x00000200)
+
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_LSB (8)
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_MASK (0x00000100)
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_BIT (0x00000100)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_LSB (7)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_MASK (0x00000080)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_BIT (0x00000080)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_LSB (6)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_MASK (0x00000040)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_BIT (0x00000040)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_LSB (5)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_MASK (0x00000020)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_BIT (0x00000020)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_LSB (4)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_MASK (0x00000010)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_BIT (0x00000010)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_LSB (3)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_MASK (0x00000008)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_BIT (0x00000008)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_LSB (2)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_MASK (0x00000004)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_BIT (0x00000004)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_LSB (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_MASK (0x00000002)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_BIT (0x00000002)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_LSB (0)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_MASK (0x00000001)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_BIT (0x00000001)
+
+#define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_LSB (0)
+#define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_WIDTH (32)
+#define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_LSB (0)
+#define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_WIDTH (32)
+#define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_LSB (0)
+#define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_WIDTH (32)
+#define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_LSB (0)
+#define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_WIDTH (32)
+#define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_STATUS0_STA0_LSB (0)
+#define RXBRP_BUS_STATUS0_STA0_WIDTH (32)
+#define RXBRP_BUS_STATUS0_STA0_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_STATUS1_STA1_LSB (0)
+#define RXBRP_BUS_STATUS1_STA1_WIDTH (32)
+#define RXBRP_BUS_STATUS1_STA1_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_STATUS2_STA2_LSB (0)
+#define RXBRP_BUS_STATUS2_STA2_WIDTH (32)
+#define RXBRP_BUS_STATUS2_STA2_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_LSB (5)
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_WIDTH (1)
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_MASK (0x00000020)
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_BIT (0x00000020)
+
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_LSB (4)
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_WIDTH (1)
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_MASK (0x00000010)
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_BIT (0x00000010)
+
+#define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_LSB (2)
+#define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_WIDTH (2)
+#define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_LSB (0)
+#define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_WIDTH (2)
+#define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RXBRP_SLV_BUS_STATUS0_STA0_LSB (0)
+#define RXBRP_SLV_BUS_STATUS0_STA0_WIDTH (32)
+#define RXBRP_SLV_BUS_STATUS0_STA0_MASK (0xFFFFFFFF)
+
+#define RXBRP_SLV_BUS_STATUS1_STA1_LSB (0)
+#define RXBRP_SLV_BUS_STATUS1_STA1_WIDTH (1)
+#define RXBRP_SLV_BUS_STATUS1_STA1_MASK (0x00000001)
+#define RXBRP_SLV_BUS_STATUS1_STA1_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXBRP_BUS_CONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg.h
new file mode 100644
index 0000000..d83011c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphrxbrpglbconreg_93.h"
+#elif defined(__MD95__)
+#include "cphrxbrpglbconreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphrxbrpglbconreg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_93.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_93.h
new file mode 100644
index 0000000..c3dc23a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_93.h
@@ -0,0 +1,1401 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_GLB_CON_REG_H_
+#define _CPH_RXBRP_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_GLOBAL_CON_REG_BASE (0xAD110000)
+
+#define RXBRP_GLOBAL_CON_end (RXBRP_GLOBAL_CON_REG_BASE + 0x0184 + 1*4)
+
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0000))
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0004))
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0008))
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x000C))
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0010))
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0014))
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0018))
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x001C))
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0020))
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0024))
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0028))
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x002C))
+#define RXBRP_GLOBAL_L_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0030))
+#define RXBRP_GLOBAL_WCT_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0034))
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0038))
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x003C))
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0040))
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0044))
+#define RXBRP_GLOBAL_GPIO_EN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0048))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x004C))
+#define RXBRP_GLOBAL_ASSERT_IRQ ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0050))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0054))
+#define RXBRP_GLOBAL_WT_DEBUG ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0058))
+#define RXBRP_GLOBAL_RESERVED_OUT ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x005C))
+#define RXBRP_GLOBAL_RESERVED_IN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0060))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0100))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0104))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0108))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x010C))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0110))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0114))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0118))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x011C))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0120))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0124))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0128))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x012C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0130))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0134))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0138))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x013C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0140))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0144))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0148))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x014C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0150))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0154))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0158))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x015C))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0160))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0164))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0168))
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x016C))
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0170))
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0174))
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0178))
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x017C))
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0180))
+#define RXBRP_GLOBAL_DCM_DBG_SEL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0184))
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_LSB (0)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_WIDTH (1)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_MASK (0x00000001)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_LSB (3)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_MASK (0x00000008)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_LSB (3)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_MASK (0x00000008)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_LSB (3)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_MASK (0x00000008)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_LSB (8)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_LSB (7)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_LSB (11)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_MASK (0x00000800)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_LSB (10)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_MASK (0x00000400)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_LSB (9)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_MASK (0x00000200)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_LSB (8)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_MASK (0x00000100)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_LSB (7)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_MASK (0x00000080)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_LSB (6)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_LSB (5)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_LSB (3)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_MASK (0x00000008)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_LSB (2)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_LSB (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_MASK (0x00000002)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_LSB (0)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_MASK (0x00000001)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_LSB (5)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_MASK (0x00000020)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_LSB (4)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_MASK (0x00000010)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_LSB (3)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_MASK (0x00000008)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_LSB (2)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_MASK (0x00000004)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_LSB (0)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_WIDTH (4)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_MASK (0x0000000F)
+
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_LSB (0)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_WIDTH (5)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_MASK (0x0000001F)
+
+
+#endif /*_CPH_RXBRP_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_95.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_95.h
new file mode 100644
index 0000000..8ef5e4e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_95.h
@@ -0,0 +1,1430 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_GLB_CON_REG_H_
+#define _CPH_RXBRP_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_GLOBAL_CON_REG_BASE (0xAD110000)
+
+#define RXBRP_GLOBAL_CON_end (RXBRP_GLOBAL_CON_REG_BASE + 0x0184 + 1*4)
+
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0000))
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0004))
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0008))
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x000C))
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0010))
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0014))
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0018))
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x001C))
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0020))
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0024))
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0028))
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x002C))
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0030))
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0034))
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0038))
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x003C))
+#define RXBRP_GLOBAL_L_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0040))
+#define RXBRP_GLOBAL_WCT_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0044))
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0048))
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x004C))
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0050))
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0054))
+#define RXBRP_GLOBAL_GPIO_EN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0058))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x005C))
+#define RXBRP_GLOBAL_ASSERT_IRQ ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0060))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0064))
+#define RXBRP_GLOBAL_WT_DEBUG ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0068))
+#define RXBRP_GLOBAL_RESERVED_OUT ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x006C))
+#define RXBRP_GLOBAL_RESERVED_IN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0070))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0100))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0104))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0108))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x010C))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0110))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0114))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0118))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x011C))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0120))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0124))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0128))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x012C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0130))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0134))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0138))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x013C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0140))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0144))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0148))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x014C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0150))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0154))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0158))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x015C))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0160))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0164))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0168))
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x016C))
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0170))
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0174))
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0178))
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x017C))
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0180))
+#define RXBRP_GLOBAL_DCM_DBG_SEL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0184))
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_LSB (0)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_WIDTH (1)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_MASK (0x00000001)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_LSB (8)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_LSB (7)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_LSB (11)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_MASK (0x00000800)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_LSB (10)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_MASK (0x00000400)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_LSB (9)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_MASK (0x00000200)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_LSB (8)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_MASK (0x00000100)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_LSB (7)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_MASK (0x00000080)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_LSB (6)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_LSB (5)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_LSB (3)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_MASK (0x00000008)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_LSB (2)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_LSB (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_MASK (0x00000002)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_LSB (0)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_MASK (0x00000001)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_LSB (4)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_MASK (0x00000010)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_LSB (3)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_MASK (0x00000008)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_LSB (2)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_MASK (0x00000004)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_LSB (0)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_WIDTH (4)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_MASK (0x0000000F)
+
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_LSB (0)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_WIDTH (5)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_MASK (0x0000001F)
+
+
+#endif /*_CPH_RXBRP_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_97.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_97.h
new file mode 100644
index 0000000..8fb27bf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_97.h
@@ -0,0 +1,1430 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_GLB_CON_REG_H_
+#define _CPH_RXBRP_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_GLOBAL_CON_REG_BASE (0xAC910000)
+
+#define RXBRP_GLOBAL_CON_end (RXBRP_GLOBAL_CON_REG_BASE + 0x0184 + 1*4)
+
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0000))
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0004))
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0008))
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x000C))
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0010))
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0014))
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0018))
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x001C))
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0020))
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0024))
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0028))
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x002C))
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0030))
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0034))
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0038))
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x003C))
+#define RXBRP_GLOBAL_L_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0040))
+#define RXBRP_GLOBAL_WCT_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0044))
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0048))
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x004C))
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0050))
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0054))
+#define RXBRP_GLOBAL_GPIO_EN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0058))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x005C))
+#define RXBRP_GLOBAL_ASSERT_IRQ ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0060))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0064))
+#define RXBRP_GLOBAL_WT_DEBUG ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0068))
+#define RXBRP_GLOBAL_RESERVED_OUT ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x006C))
+#define RXBRP_GLOBAL_RESERVED_IN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0070))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0100))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0104))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0108))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x010C))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0110))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0114))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0118))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x011C))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0120))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0124))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0128))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x012C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0130))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0134))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0138))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x013C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0140))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0144))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0148))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x014C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0150))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0154))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0158))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x015C))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0160))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0164))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0168))
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x016C))
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0170))
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0174))
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0178))
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x017C))
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0180))
+#define RXBRP_GLOBAL_DCM_DBG_SEL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0184))
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_LSB (0)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_WIDTH (1)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_MASK (0x00000001)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_LSB (8)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_LSB (7)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_LSB (11)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_MASK (0x00000800)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_LSB (10)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_MASK (0x00000400)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_LSB (9)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_MASK (0x00000200)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_LSB (8)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_MASK (0x00000100)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_LSB (7)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_MASK (0x00000080)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_LSB (6)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_LSB (5)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_LSB (3)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_MASK (0x00000008)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_LSB (2)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_LSB (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_MASK (0x00000002)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_LSB (0)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_MASK (0x00000001)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_LSB (4)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_MASK (0x00000010)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_LSB (3)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_MASK (0x00000008)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_LSB (2)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_MASK (0x00000004)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_LSB (0)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_WIDTH (4)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_MASK (0x0000000F)
+
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_LSB (0)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_WIDTH (5)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_MASK (0x0000001F)
+
+
+#endif /*_CPH_RXBRP_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfe2cs_rxsel.h b/mcu/interface/l1/cl1/common/HW/cphrxdfe2cs_rxsel.h
new file mode 100644
index 0000000..2a928a0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfe2cs_rxsel.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXDFE2CS_RXSEL_REG_97_H_
+#define _CPH_RXDFE2CS_RXSEL_REG_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE2CS_RXSEL_REG_BASE (0xA8DB0000)
+
+#define RXDFE2CS_RXSEL_REG_end (RXDFE2CS_RXSEL_REG_BASE + 0x0060 + 1*4)
+
+
+#define C2K1X_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x0))
+#define C2KDO_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x4))
+#define TDD_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x8))
+#define W_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0xC))
+#define NR_CS_DATA_SEL_0 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x10))
+#define NR_CS_DATA_SEL_1 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x14))
+#define NR_CS_TRANS_START_TIMER_CC0 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x18))
+#define NR_CS_TRANS_START_TIMER_CC1 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x1C))
+#define NR_CS_TRANS_START_TIMER_CC2 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x20))
+#define NR_CS_TRANS_START_TIMER_CC3 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x24))
+#define NR_CS_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x28))
+#define RXDFE2CS_NR_SC_GALS_CFG ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x2C))
+#define RXDFE2CS_DBG ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x30))
+
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_LSB (31)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_WIDTH (1)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_MASK (0x80000000)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_BIT (0x80000000)
+
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_LSB (30)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_WIDTH (1)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_MASK (0x40000000)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_BIT (0x40000000)
+
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_sel_LSB (0)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_sel_WIDTH (5)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_sel_MASK (0x0000001F)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_LSB (31)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_WIDTH (1)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_MASK (0x80000000)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_BIT (0x80000000)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_LSB (30)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_WIDTH (1)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_MASK (0x40000000)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_BIT (0x40000000)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_div_LSB (8)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_div_WIDTH (5)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_div_MASK (0x00001F00)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_main_LSB (0)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_main_WIDTH (5)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_main_MASK (0x0000001F)
+
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_LSB (31)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_WIDTH (1)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_MASK (0x80000000)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_BIT (0x80000000)
+
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_LSB (0)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_WIDTH (1)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_MASK (0x00000001)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_BIT (0x00000001)
+
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_LSB (31)
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_MASK (0x80000000)
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_BIT (0x80000000)
+
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_LSB (30)
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_MASK (0x40000000)
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_BIT (0x40000000)
+
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_LSB (4)
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_MASK (0x00000010)
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_BIT (0x00000010)
+
+#define W_CS_SEL_CTRL_w_cs_data_delay_LSB (0)
+#define W_CS_SEL_CTRL_w_cs_data_delay_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_data_delay_MASK (0x00000001)
+#define W_CS_SEL_CTRL_w_cs_data_delay_BIT (0x00000001)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a1_LSB (24)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a1_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a1_MASK (0x1F000000)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a0_LSB (16)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a0_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a0_MASK (0x001F0000)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a1_LSB (8)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a1_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a1_MASK (0x00001F00)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a0_LSB (0)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a0_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a0_MASK (0x0000001F)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a1_LSB (24)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a1_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a1_MASK (0x1F000000)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a0_LSB (16)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a0_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a0_MASK (0x001F0000)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a1_LSB (8)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a1_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a1_MASK (0x00001F00)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a0_LSB (0)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a0_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a0_MASK (0x0000001F)
+
+#define NR_CS_TRANS_START_TIMER_CC0_nr_cs_data_trans_start_timer_cc0_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC0_nr_cs_data_trans_start_timer_cc0_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC0_nr_cs_data_trans_start_timer_cc0_MASK (0x3FFFFFFF)
+
+#define NR_CS_TRANS_START_TIMER_CC1_nr_cs_data_trans_start_timer_cc1_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC1_nr_cs_data_trans_start_timer_cc1_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC1_nr_cs_data_trans_start_timer_cc1_MASK (0x3FFFFFFF)
+
+#define NR_CS_TRANS_START_TIMER_CC2_nr_cs_data_trans_start_timer_cc2_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC2_nr_cs_data_trans_start_timer_cc2_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC2_nr_cs_data_trans_start_timer_cc2_MASK (0x3FFFFFFF)
+
+#define NR_CS_TRANS_START_TIMER_CC3_nr_cs_data_trans_start_timer_cc3_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC3_nr_cs_data_trans_start_timer_cc3_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC3_nr_cs_data_trans_start_timer_cc3_MASK (0x3FFFFFFF)
+
+#define NR_CS_CTRL_nr_cs_data_trans_en_LSB (31)
+#define NR_CS_CTRL_nr_cs_data_trans_en_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_trans_en_MASK (0x80000000)
+#define NR_CS_CTRL_nr_cs_data_trans_en_BIT (0x80000000)
+
+#define NR_CS_CTRL_nr_cs_data_trans_rate_LSB (8)
+#define NR_CS_CTRL_nr_cs_data_trans_rate_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_trans_rate_MASK (0x00000100)
+#define NR_CS_CTRL_nr_cs_data_trans_rate_BIT (0x00000100)
+
+#define NR_CS_CTRL_nr_cs_data_iq_swap_LSB (4)
+#define NR_CS_CTRL_nr_cs_data_iq_swap_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_iq_swap_MASK (0x00000010)
+#define NR_CS_CTRL_nr_cs_data_iq_swap_BIT (0x00000010)
+
+#define NR_CS_CTRL_nr_cs_data_trans_mode_LSB (0)
+#define NR_CS_CTRL_nr_cs_data_trans_mode_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_trans_mode_MASK (0x00000001)
+#define NR_CS_CTRL_nr_cs_data_trans_mode_BIT (0x00000001)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_LSB (4)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_WIDTH (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_MASK (0x00000010)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_BIT (0x00000010)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_LSB (3)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_WIDTH (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_MASK (0x00000008)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_BIT (0x00000008)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_mst_sync_sel_LSB (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_mst_sync_sel_WIDTH (2)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_mst_sync_sel_MASK (0x00000006)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_LSB (0)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_WIDTH (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_MASK (0x00000001)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_BIT (0x00000001)
+
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_stimer_LSB (2)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_stimer_WIDTH (30)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_stimer_MASK (0xFFFFFFFC)
+
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_LSB (0)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_WIDTH (1)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_MASK (0x00000001)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXDFE2CS_RXSEL_REG_97_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfeatimer.h b/mcu/interface/l1/cl1/common/HW/cphrxdfeatimer.h
new file mode 100644
index 0000000..c50bce9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfeatimer.h
@@ -0,0 +1,91 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_DFE_ATTIMER_H_
+#define _CPH_RX_DFE_ATTIMER_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_ATIMER_REG_BASE (0xA70D0000)
+
+#define RXDFE_ATIMER_end (RXDFE_ATIMER_REG_BASE + 0x00000004 + 1*4)
+
+
+
+#define RG_RXDFE_ATIMER_TRG ((APBADDR32)(RXDFE_ATIMER_REG_BASE + 0x00000000))
+#define RG_RXDFE_ATIMER_RO ((APBADDR32)(RXDFE_ATIMER_REG_BASE + 0x00000004))
+
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_LSB (31)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_MASK (0x80000000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_BIT (0x80000000)
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_LSB (30)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_MASK (0x40000000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_BIT (0x40000000)
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_LSB (16)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_MASK (0x00010000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_BIT (0x00010000)
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_LSB (15)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_MASK (0x00008000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_BIT (0x00008000)
+
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_LSB (31)
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_WIDTH (1)
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_MASK (0x80000000)
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_BIT (0x80000000)
+
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_LSB (16)
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_WIDTH (1)
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_MASK (0x00010000)
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_BIT (0x00010000)
+
+
+#endif //#ifndef _CPH_RX_DFE_ATTIMER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h b/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h
new file mode 100644
index 0000000..9ad21f9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h
@@ -0,0 +1,153 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_DFE_FCCALTC_H_
+#define _CPH_RX_DFE_FCCALTC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FCCALTC_REG_BASE (0xA70B0000)
+
+#define RXDFE_FCCALTC_end (RXDFE_FCCALTC_REG_BASE + 0x00000A00 + 1*4)
+
+
+
+#define RG_RXDFE_FCCALTC_OFFSET(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 4
+#define RG_RXDFE_FCCALTC_TQ_SEL(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000200 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_TRG(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000280 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000300 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000600))
+#define RG_RXDFE_FCCALTC_LPM_CFG ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000800))
+#define RG_RXDFE_FCCALTC_LPM_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000810 + (n)*4)) //n is from 0 to 1
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000820 + (n)*4)) //n is from 0 to 1
+#define RG_RXDFE_FCCALTC_IRQ ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000A00))
+
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_LSB (16)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_MASK (0x00FF0000)
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_LSB (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_MASK (0x0000FF00)
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_LSB (0)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_MASK (0x000000FF)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_LSB (24)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_WIDTH (2)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_MASK (0x03000000)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_LSB (16)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_WIDTH (5)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_MASK (0x001F0000)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_LSB (8)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_WIDTH (5)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_MASK (0x00001F00)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_BIT (0x00000001)
+
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_LSB (31)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_MASK (0x80000000)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_BIT (0x80000000)
+
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_LSB (30)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_MASK (0x40000000)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_BIT (0x40000000)
+
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_LSB (24)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_MASK (0x01000000)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_BIT (0x01000000)
+
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_WIDTH (8)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_MASK (0x000000FF)
+
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_WIDTH (12)
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_MASK (0x00000FFF)
+
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_LSB (4)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_MASK (0x00000010)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_BIT (0x00000010)
+
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_WIDTH (4)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_MASK (0x0000000F)
+
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_WIDTH (4)
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_MASK (0x0000000F)
+
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_LSB (16)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_MASK (0x00010000)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_BIT (0x00010000)
+
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_BIT (0x00000001)
+
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_LSB (16)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_MASK (0x00010000)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_BIT (0x00010000)
+
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_LSB (0)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_WIDTH (1)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RX_DFE_FCCALTC_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig.h b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig.h
new file mode 100644
index 0000000..b48d146
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig.h
@@ -0,0 +1,40 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphrxdfesysconfig_93.h"
+#else /*MD95,MD97, after MD97 mybe need update */
+#include "cphrxdfesysconfig_95.h"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_93.h b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_93.h
new file mode 100644
index 0000000..3b23c5b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_93.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXDEF_SYSCONFIG_H_
+#define _CPH_RXDEF_SYSCONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFESYS_CONFIG_REG_BASE (0xA7010000)
+
+#define RXDFESYS_CONFIG_end (RXDFESYS_CONFIG_REG_BASE + 0x00000180 + 1*4)
+
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_PCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000080 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000100))
+#define RG_RXDFESYS_DDR_ENA_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000180))
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_LSB (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_MASK (0x00000002)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_BIT (0x00000002)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_LSB (0)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_MASK (0x00000001)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXDEF_SYSCONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_95.h b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_95.h
new file mode 100644
index 0000000..3b23c5b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_95.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXDEF_SYSCONFIG_H_
+#define _CPH_RXDEF_SYSCONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFESYS_CONFIG_REG_BASE (0xA7010000)
+
+#define RXDFESYS_CONFIG_end (RXDFESYS_CONFIG_REG_BASE + 0x00000180 + 1*4)
+
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_PCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000080 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000100))
+#define RG_RXDFESYS_DDR_ENA_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000180))
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_LSB (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_MASK (0x00000002)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_BIT (0x00000002)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_LSB (0)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_MASK (0x00000001)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXDEF_SYSCONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxmmeventgen.h b/mcu/interface/l1/cl1/common/HW/cphrxmmeventgen.h
new file mode 100644
index 0000000..cb42709
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxmmeventgen.h
@@ -0,0 +1,161 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_MM_EVENT_GEN_H_
+#define _CPH_RX_MM_EVENT_GEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MM_RX_RF_EVENTGEN_REG_BASE (0x00000000)
+
+#define MM_RX_RF_EVENTGEN_end (MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + 32*4)
+
+
+
+#define MM_EVENTGEN_LTE_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0000))
+#define MM_EVENTGEN_FDD_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0004))
+#define MM_EVENTGEN_GSM_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0008))
+#define MM_EVENTGEN_BSI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x000C))
+#define MM_EVENTGEN_BSI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0010))
+#define MM_EVENTGEN_BSI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0014 + (n)*4)) //n is from 0 to 31
+#define MM_EVENTGEN_LTE_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1000))
+#define MM_EVENTGEN_FDD_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1004))
+#define MM_EVENTGEN_GSM_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1008))
+#define MM_EVENTGEN_MIPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x100C))
+#define MM_EVENTGEN_MIPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1010))
+#define MM_EVENTGEN_MIPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1014 + (n)*4)) //n is from 0 to 31
+#define MM_EVENTGEN_LTE_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2000))
+#define MM_EVENTGEN_FDD_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2004))
+#define MM_EVENTGEN_GSM_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2008))
+#define MM_EVENTGEN_BPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x200C))
+#define MM_EVENTGEN_BPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2010))
+#define MM_EVENTGEN_BPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + (n)*4)) //n is from 0 to 31
+
+
+#define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_LSB (0)
+#define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_WIDTH (20)
+#define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_LSB (0)
+#define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_WIDTH (16)
+#define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_MASK (0x0000FFFF)
+
+#define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_LSB (0)
+#define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_WIDTH (14)
+#define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_MASK (0x00003FFF)
+
+#define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_LSB (0)
+#define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_WIDTH (32)
+#define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_LSB (0)
+#define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_WIDTH (32)
+#define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BSI_EVENT_MODE_LSB (29)
+#define MM_EVENTGEN_BSI_EVENT_MODE_WIDTH (3)
+#define MM_EVENTGEN_BSI_EVENT_MODE_MASK (0xE0000000)
+
+#define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_LSB (0)
+#define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_WIDTH (20)
+#define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_LSB (0)
+#define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_WIDTH (20)
+#define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_LSB (0)
+#define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_WIDTH (16)
+#define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_MASK (0x0000FFFF)
+
+#define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_LSB (0)
+#define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_WIDTH (14)
+#define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_MASK (0x00003FFF)
+
+#define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_LSB (0)
+#define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_WIDTH (32)
+#define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_LSB (0)
+#define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_WIDTH (32)
+#define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_MIPI_EVENT_MODE_LSB (29)
+#define MM_EVENTGEN_MIPI_EVENT_MODE_WIDTH (3)
+#define MM_EVENTGEN_MIPI_EVENT_MODE_MASK (0xE0000000)
+
+#define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_LSB (0)
+#define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_WIDTH (20)
+#define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_LSB (0)
+#define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_WIDTH (20)
+#define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_LSB (0)
+#define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_WIDTH (16)
+#define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_MASK (0x0000FFFF)
+
+#define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_LSB (0)
+#define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_WIDTH (14)
+#define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_MASK (0x00003FFF)
+
+#define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_LSB (0)
+#define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_WIDTH (32)
+#define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_LSB (0)
+#define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_WIDTH (32)
+#define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BPI_EVENT_MODE_LSB (29)
+#define MM_EVENTGEN_BPI_EVENT_MODE_WIDTH (3)
+#define MM_EVENTGEN_BPI_EVENT_MODE_MASK (0xE0000000)
+
+#define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_LSB (0)
+#define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_WIDTH (20)
+#define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_MASK (0x000FFFFF)
+
+
+#endif //#ifndef _CPH_RX_MM_EVENT_GEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphslpctrl.h b/mcu/interface/l1/cl1/common/HW/cphslpctrl.h
new file mode 100644
index 0000000..7f7d795
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphslpctrl.h
@@ -0,0 +1,211 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHSLPCTRL_H_
+#define _CPHSLPCTRL_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if (defined(__MD93__)||defined(__MD95__))
+#define ST_SM_REG_BASE (0xA60D0000)/*SM REG BASE 93&95*/
+#elif defined(__MD97__) || defined(__MD97P__)
+#define ST_SM_REG_BASE (0xA80D0000)/*SM REG BASE 97*/
+#endif
+
+#define ST_SM_CON(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000000))
+#define ST_SM_PAUSE_TIME(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000004))
+#define ST_SM_STA(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000008))
+#define ST_SM_CFG(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000000C))
+#define ST_SM_START_TIME(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000010))
+#define ST_SM_SW_WAKE_CON(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000014))
+#define ST_SM_STEP_FRAC(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000018))
+#define ST_SM_SYSCNT_F32K_INT(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000001C))
+#define ST_SM_SYSCNT_F32K_FRAC(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000020))
+#define ST_SM_SUPFRM_F32K_L(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000024))
+#define ST_SM_SUPFRM_F32K_H(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000028))
+#define ST_SM_SLEEP_OFFSET(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000002C))
+#define ST_SM_TIME_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000030))
+#define ST_SM_SUPFRM_TIME_L_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000034))
+#define ST_SM_SUPFRM_TIME_H_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000038))
+#define ST_SM_TIME_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000003C))
+#define ST_SM_SUPFRM_TIME_L_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000040))
+#define ST_SM_SUPFRM_TIME_H_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000044))
+#define ST_SM_TIME_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000048))
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000004C))
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000050))
+#define ST_SM_FINAL_PAUSE_DURATION(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000054))
+#define ST_SM_PRESLP_CNT(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000058))
+#define ST_SM_SLT_START_F32K(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000005C))
+#define ST_SM_WAKEUP_START_F32K(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000060))
+
+
+#define ST_SM_CON_CLR_CNT_LSB (15)
+#define ST_SM_CON_CLR_CNT_WIDTH (1)
+#define ST_SM_CON_CLR_CNT_MASK (0x00008000)
+#define ST_SM_CON_CLR_CNT_BIT (0x00008000)
+
+#define ST_SM_CON_PAUSE_START_LSB (1)
+#define ST_SM_CON_PAUSE_START_WIDTH (1)
+#define ST_SM_CON_PAUSE_START_MASK (0x00000002)
+#define ST_SM_CON_PAUSE_START_BIT (0x00000002)
+
+#define ST_SM_CON_PAUSE_MODE_LSB (0)
+#define ST_SM_CON_PAUSE_MODE_WIDTH (1)
+#define ST_SM_CON_PAUSE_MODE_MASK (0x00000001)
+#define ST_SM_CON_PAUSE_MODE_BIT (0x00000001)
+
+#define ST_SM_PAUSE_TIME_PAUSE_TIME_LSB (0)
+#define ST_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32)
+#define ST_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF)
+
+#define ST_SM_STA_SLP_EXIT_CPL_LSB (7)
+#define ST_SM_STA_SLP_EXIT_CPL_WIDTH (1)
+#define ST_SM_STA_SLP_EXIT_CPL_MASK (0x00000080)
+#define ST_SM_STA_SLP_EXIT_CPL_BIT (0x00000080)
+
+#define ST_SM_STA_PAUSE_CPL_LSB (6)
+#define ST_SM_STA_PAUSE_CPL_WIDTH (1)
+#define ST_SM_STA_PAUSE_CPL_MASK (0x00000040)
+#define ST_SM_STA_PAUSE_CPL_BIT (0x00000040)
+
+#define ST_SM_CFG_SW_WAKE_EN_LSB (8)
+#define ST_SM_CFG_SW_WAKE_EN_WIDTH (1)
+#define ST_SM_CFG_SW_WAKE_EN_MASK (0x00000100)
+#define ST_SM_CFG_SW_WAKE_EN_BIT (0x00000100)
+
+#define ST_SM_CFG_IRQ_EN_LSB (1)
+#define ST_SM_CFG_IRQ_EN_WIDTH (1)
+#define ST_SM_CFG_IRQ_EN_MASK (0x00000002)
+#define ST_SM_CFG_IRQ_EN_BIT (0x00000002)
+
+#define ST_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_SM_SW_WAKE_CON_SW_EVENT_LSB (0)
+#define ST_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1)
+#define ST_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001)
+#define ST_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001)
+
+#define ST_SM_STEP_FRAC_STEP_INT_LSB (18)
+#define ST_SM_STEP_FRAC_STEP_INT_WIDTH (9)
+#define ST_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000)
+
+#define ST_SM_STEP_FRAC_STEP_FRAC_LSB (0)
+#define ST_SM_STEP_FRAC_STEP_FRAC_WIDTH (18)
+#define ST_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF)
+
+#define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0)
+#define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20)
+#define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF)
+
+#define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0)
+#define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18)
+#define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF)
+
+#define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0)
+#define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32)
+#define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0)
+#define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4)
+#define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F)
+
+#define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14)
+#define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC)
+
+#define ST_SM_TIME_START_SM_TIME_START_LSB (0)
+#define ST_SM_TIME_START_SM_TIME_START_WIDTH (20)
+#define ST_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF)
+
+#define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32)
+#define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4)
+#define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F)
+
+#define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0)
+#define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20)
+#define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF)
+
+#define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32)
+#define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4)
+#define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F)
+
+#define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0)
+#define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20)
+#define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF)
+
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32)
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4)
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F)
+
+#define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0)
+#define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32)
+#define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF)
+
+#define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0)
+#define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6)
+#define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F)
+
+#define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0)
+#define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6)
+#define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F)
+
+#define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0)
+#define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32)
+#define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF)
+
+
+#endif /* _CPHSLPCTRL_H_ */
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h b/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h
new file mode 100644
index 0000000..4dd9ed0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h
@@ -0,0 +1,177 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_COMMON_TXCRP_H_
+#define _CPH_COMMON_TXCRP_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_INTERNAL_REG_BASE (0xA8170000)
+#else
+#define TXCRP_INTERNAL_REG_BASE (0xA8970000)
+#endif
+
+#define MODE_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0000))
+#define CRC_EN ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0004))
+#define CRC_LENGTH ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0008))
+#define CRC_OUT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x000C))
+#define CRC_MOD_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0010))
+#define TD_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0014))
+#define TD_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0018))
+#define FDD_SW_TIMER_GTXCRP_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x001C))
+#define FDD_SW_TIMER_WTXHCH_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0020))
+#define FDD_SW_TIMER_WTXCQI_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0024))
+#define FDD_SW_TTR_GTXCRP_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0028))
+#define FDD_SW_TTR_WTXHCH_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x002C))
+#define FDD_SW_TTR_WTXCQI_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0030))
+#define FDD_SW_TTR_SLOT_CNT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0034))
+#define C1X_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0038))
+#define C1X_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x003C))
+#define WRBRPMEM_TEST_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0040))
+#define WRBRPMEM_TEST_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0044))
+#define DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x004C))
+#define DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0050))
+#define DO_KS_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0054))
+#define DO_TX_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0058))
+#define TESTMODE_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x005C))
+#define TESTMODE_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0060))
+#define KS_SEL_CONFIG ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0064))
+#define MODE_SEL_ADDR_MIS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0068))
+#define IRQ_MODE_SEL_ADDR_MIS_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x006C))
+#define IRQ_MODE_CHANGE_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0070))
+#define TXCRP_MODE_SETERR_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0074))
+#define TXCRP_IRQ_STATUS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0078))
+#define TXCRP_IRQ_MASK ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x007C))
+#define INFO_BRP_RU1_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0080))
+#define INFO_BRP_RU1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0084))
+#define INFO_BRP_RU2_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x008C))
+#define INFO_BRP_RU2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0090))
+#define DBG_BUS_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0094))
+#define DUMMY_CRP ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0098))
+#define RAKE_LOG_COUNTER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x009C))
+#define RAKELOG_0 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A0))
+#define RAKELOG_1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A4))
+#define RAKELOG_2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A8))
+#define RAKELOG_3 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00AC))
+#define RAKELOG_4 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00B0))
+#if defined(__MD97__)
+#define TXCRP_KS0_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x010C))
+#define TXCRP_KS1_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0110))
+#endif
+
+#define MODE_SEL_LSB (0)
+#define MODE_SEL_WIDTH (5)
+#define MODE_SEL_MASK (0x0000001F)
+
+#define MODE_SEL_ADDR_MIS_LSB (0)
+#define MODE_SEL_ADDR_MIS_WIDTH (1)
+#define MODE_SEL_ADDR_MIS_MASK (0x00000001)
+#define MODE_SEL_ADDR_MIS_BIT (0x00000001)
+
+#define MODE_SEL_ADDR_MIS_CLR_LSB (0)
+#define MODE_SEL_ADDR_MIS_CLR_WIDTH (1)
+#define MODE_SEL_ADDR_MIS_CLR_MASK (0x00000001)
+#define MODE_SEL_ADDR_MIS_CLR_BIT (0x00000001)
+
+#define CRC_EN_LSB (0)
+#define CRC_EN_WIDTH (1)
+#define CRC_EN_MASK (0x00000001)
+#define CRC_EN_BIT (0x00000001)
+
+#define CRC_LENGTH_LSB (0)
+#define CRC_LENGTH_WIDTH (20)
+#define CRC_LENGTH_MASK (0x000FFFFF)
+
+#define CRC_OUT_LSB (0)
+#define CRC_OUT_WIDTH (32)
+#define CRC_OUT_MASK (0xFFFFFFFF)
+
+#define INFO_RU1_ADDR_LSB (0)
+#define INFO_RU1_ADDR_WIDTH (13)
+#define INFO_RU1_ADDR_MASK (0x00001FFF)
+
+#define RU1_ADDR0_DATA_LSB (24)
+#define RU1_ADDR0_DATA_WIDTH (8)
+#define RU1_ADDR0_DATA_MASK (0xFF000000)
+
+#define RU1_ADDR1_DATA_LSB (16)
+#define RU1_ADDR1_DATA_WIDTH (8)
+#define RU1_ADDR1_DATA_MASK (0x00FF0000)
+
+#define RU1_ADDR2_DATA_LSB (8)
+#define RU1_ADDR2_DATA_WIDTH (8)
+#define RU1_ADDR2_DATA_MASK (0x0000FF00)
+
+#define RU1_ADDR3_DATA_LSB (0)
+#define RU1_ADDR3_DATA_WIDTH (8)
+#define RU1_ADDR3_DATA_MASK (0x000000FF)
+
+#define INFO_RU2_ADDR_LSB (0)
+#define INFO_RU2_ADDR_WIDTH (13)
+#define INFO_RU2_ADDR_MASK (0x00001FFF)
+
+#define RU2_ADDR0_DATA_LSB (24)
+#define RU2_ADDR0_DATA_WIDTH (8)
+#define RU2_ADDR0_DATA_MASK (0xFF000000)
+
+#define RU2_ADDR1_DATA_LSB (16)
+#define RU2_ADDR1_DATA_WIDTH (8)
+#define RU2_ADDR1_DATA_MASK (0x00FF0000)
+
+#define RU2_ADDR2_DATA_LSB (8)
+#define RU2_ADDR2_DATA_WIDTH (8)
+#define RU2_ADDR2_DATA_MASK (0x0000FF00)
+
+#define RU2_ADDR3_DATA_LSB (0)
+#define RU2_ADDR3_DATA_WIDTH (8)
+#define RU2_ADDR3_DATA_MASK (0x000000FF)
+
+#define DBG_BUS_SEL_LSB (0)
+#define DBG_BUS_SEL_WIDTH (4)
+#define DBG_BUS_SEL_MASK (0x0000000F)
+
+#define CRP_LSB (0)
+#define CRP_WIDTH (32)
+#define CRP_MASK (0xFFFFFFFF)
+
+#endif //#ifndef _CPH_COMMON_TXCRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb.h
new file mode 100644
index 0000000..84f7631
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxdfebb_93.h"
+#elif defined(__MD95__)
+#include "cphtxdfebb_95.h"
+#elif defined(__MD97__)
+#include "cphtxdfebb_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb_93.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_93.h
new file mode 100644
index 0000000..8bb0174
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_93.h
@@ -0,0 +1,270 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXDFE_BB_H_
+#define _CPH_TXDFE_BB_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define TXDFE_BB_REG_REG_BASE (0XA8300000)
+
+#define TXDFE_BB_REG_end (TXDFE_BB_REG_REG_BASE + 0x64 + 1*4)
+#define TXDFE_BB_L_CCA_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0))
+#define TXDFE_BB_L_GROUP_SEL_WIN0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x4))
+#define TXDFE_BB_L_GROUP_SEL_WIN1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x8))
+#define TXDFE_BB_DATA_RATE_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0xc))
+#define TXDFE_BB_DATA_RATE_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x10))
+#define TXDFE_BB_SW_CON_WIN ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x14))
+#define TXDFE_BB_SW_CON_MODE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x18))
+#define TXDFE_BB_L_CON_DEL_CAL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x1c))
+#define TXDFE_BB_SW_CON_SINE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x20))
+#define TXDFE_BB_SRC_FIFO_PTR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x24))
+#define TXDFE_BB_WTC_NCO_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x28))
+#define TXDFE_BB_L_NCO_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x2c))
+#define TXDFE_BB_L_NCO_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x30))
+#define TXDFE_BB_L_NCO_CON2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x34))
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x38))
+#define TXDFE_BB_SW_PAPR_TH ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x3c))
+#define TXDFE_BB_CFR_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x40))
+#define TXDFE_BB_CFR_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x44))
+#define TXDFE_BB_CRC_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x48))
+#define TXDFE_BB_CRC_OUT_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x4c))
+#define TXDFE_BB_CRC_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x50))
+#define TXDFE_BB_CRC_OUT_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x54))
+#define TXDFE_BB_C2K_IS95_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x58))
+#define TXDFE_BB_FPGA_CON_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x5c))
+#define TXDFE_BB_IRQ_MASK ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x60))
+#define TxDFE_BB_DBG_SEL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x64))
+
+
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_LSB (0)
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_WIDTH (1)
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_MASK (0x00000001)
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_BIT (0x00000001)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_WIDTH (1)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_MASK (0x00000001)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_BIT (0x00000001)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_WIDTH (1)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_MASK (0x00000001)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_BIT (0x00000001)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_CCA_BW_REAL_G0_LSB (6)
+#define TXDFE_BB_DATA_RATE_G0_RG_CCA_BW_REAL_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_CCA_BW_REAL_G0_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_LSB (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_LSB (0)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_CCA_BW_REAL_G1_LSB (6)
+#define TXDFE_BB_DATA_RATE_G1_RG_CCA_BW_REAL_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_CCA_BW_REAL_G1_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_LSB (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_LSB (0)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_MASK (0x00000007)
+
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_LSB (0)
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_WIDTH (1)
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_LSB (0)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_WIDTH (32)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_LSB (0)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_LSB (0)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_INIT_PHASE_LSB (0)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_INIT_PHASE_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_INIT_PHASE_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_LSB (0)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_WIDTH (1)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_MASK (0x00000001)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_BIT (0x00000001)
+
+#define TXDFE_BB_SW_PAPR_TH_RG_TXDFE_BB_SW_PAPR_RED_A_LSB (0)
+#define TXDFE_BB_SW_PAPR_TH_RG_TXDFE_BB_SW_PAPR_RED_A_WIDTH (12)
+#define TXDFE_BB_SW_PAPR_TH_RG_TXDFE_BB_SW_PAPR_RED_A_MASK (0x00000FFF)
+
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_SQRT_COEFF_LSB (2)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_SQRT_COEFF_WIDTH (3)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_SQRT_COEFF_MASK (0x0000001C)
+
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_ON_LSB (0)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_ON_WIDTH (2)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_ON_MASK (0x00000003)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W4_LSB (24)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W4_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W4_MASK (0x3F000000)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W3_LSB (18)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W3_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W3_MASK (0x00FC0000)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W2_LSB (12)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W2_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W2_MASK (0x0003F000)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W1_LSB (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W1_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W1_MASK (0x00000FC0)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W0_LSB (0)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W0_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W0_MASK (0x0000003F)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_LSB (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_MASK (0x00000002)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_BIT (0x00000002)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_LSB (0)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_MASK (0x00000001)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_BIT (0x00000001)
+
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_LSB (1)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_WIDTH (1)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_MASK (0x00000002)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_BIT (0x00000002)
+
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_LSB (0)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_WIDTH (1)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_MASK (0x00000001)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_BIT (0x00000001)
+
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_LSB (4)
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_WIDTH (1)
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_MASK (0x00000010)
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_BIT (0x00000010)
+
+#define TxDFE_BB_DBG_SEL_RG_DBG_SEL_LSB (0)
+#define TxDFE_BB_DBG_SEL_RG_DBG_SEL_WIDTH (4)
+#define TxDFE_BB_DBG_SEL_RG_DBG_SEL_MASK (0x0000000F)
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb_95.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_95.h
new file mode 100644
index 0000000..10dea4f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_95.h
@@ -0,0 +1,1028 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXDFE_BB_H_
+#define _CPH_TXDFE_BB_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define TXDFE_BB_REG_REG_BASE (0xA8302000)
+
+#define TXDFE_BB_REG_end (TXDFE_BB_REG_REG_BASE + 0xFFC + 1*4)
+
+#define TXDFE_BB_GLB_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x000))
+#define TXDFE_BB_DATA_RATE_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x004))
+#define TXDFE_BB_DATA_RATE_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x008))
+#define TXDFE_BB_DATA_RATE_G2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x00C))
+#define TXDFE_BB_L_GROUP_SEL_WIN0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x010))
+#define TXDFE_BB_L_GROUP_SEL_WIN1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x014))
+#define TXDFE_BB_L_GROUP_SEL_WIN2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x018))
+#define TXDFE_BB_L_NCO_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x01C))
+#define TXDFE_BB_L_NCO_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x020))
+#define TXDFE_BB_L_NCO_CON2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x024))
+#define TXDFE_BB_L_NCO_CON3 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x028))
+#define TXDFE_BB_L_NCO_CON4 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x02C))
+#define TXDFE_BB_L_NCO_CON5 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x030))
+#define TXDFE_BB_SW_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x034))
+#define TXDFE_BB_SW_CON_SINE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x038))
+#define TXDFE_BB_L_CON_DEL_CAL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x03C))
+#define TXDFE_BB_SRC_FIFO_PTR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x040))
+#define TXDFE_BB_WTC_NCO_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x044))
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x048))
+#define TXDFE_BB_C2K_IS95_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x04C))
+#define TXDFE_BB_CRC_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x050))
+#define TXDFE_BB_CRC_OUT_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x054))
+#define TXDFE_BB_CRC_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x058))
+#define TXDFE_BB_CRC_OUT_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x05C))
+#define TXDFE_BB_CRC_CON2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x060))
+#define TXDFE_BB_CRC_OUT_G2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x064))
+#define TXDFE_BB_PCC_INFO ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x068))
+#define TXDFE_BB_PCC_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x06C))
+#define TXDFE_BB_TEST_SEL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x070))
+#define TXDFE_BB_WIN_ERR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x074))
+#define TXDFE_BB_DBG_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x080))
+#define TXDFE_BB_DBG_1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x084))
+#define TXDFE_BB_DBG_2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x088))
+#define TXDFE_BB_DBG_3 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x08C))
+#define TXDFE_BB_DBG_4 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x090))
+#define TXDFE_BB_DBG_5 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x094))
+#define TXDFE_BB_DBG_6 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x098))
+#define TXDFE_BB_DBG_7 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x09C))
+#define TXDFE_BB_DBG_8 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0A0))
+#define TXDFE_BB_DBG_9 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0A4))
+#define TXDFE_BB_DBG_10 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0A8))
+#define TXDFE_BB_DBG_11 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0AC))
+#define TXDFE_BB_DBG_12 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0B0))
+#define TXDFE_BB_DBG_13 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0B4))
+#define TXDFE_BB_DBG_14 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0B8))
+#define TXDFE_BB_DBG_15 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0BC))
+#define TXDFE_BB_DBG_16 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0C0))
+#define TXDFE_BB_FPGA_CON_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x100))
+#define TXDFE_BB_P0_CFR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x800))
+#define TXDFE_BB_P0_CFR_ROM_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x804))
+#define TXDFE_BB_P0_CFR_ROM_1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x808))
+#define TXDFE_BB_P0_CFR_ROM_2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x80C))
+#define TXDFE_BB_P1_CFR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x810))
+#define TXDFE_BB_P1_CFR_ROM_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x814))
+#define TXDFE_BB_P1_CFR_ROM_1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x818))
+#define TXDFE_BB_P1_CFR_ROM_2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x81C))
+#define TXDFE_BB_P0_CFR_SW_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x820))
+#define TXDFE_BB_P0_CFR_SW_MODE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x824))
+#define TXDFE_BB_P1_CFR_SW_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x830))
+#define TXDFE_BB_P1_CFR_SW_MODE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x834))
+#define TXDFE_BB_REG_PROTECT ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0xFFC))
+
+
+
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_LSB (4)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_MASK (0x00000010)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_BIT (0x00000010)
+
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_LSB (0)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_MASK (0x00000001)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_BIT (0x00000001)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_LSB (6)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_LSB (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_LSB (0)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_LSB (6)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_LSB (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_LSB (0)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_LSB (6)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_LSB (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_LSB (0)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_MASK (0x00000007)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_MASK (0x00000003)
+
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_LSB (0)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_LSB (0)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_LSB (0)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_LSB (0)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_LSB (0)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_LSB (0)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_LSB (4)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_MASK (0x00000010)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_BIT (0x00000010)
+
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_LSB (0)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_LSB (0)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_WIDTH (32)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_LSB (0)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_WIDTH (1)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_MASK (0x00000001)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_BIT (0x00000001)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_LSB (8)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_WIDTH (24)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_LSB (4)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_WIDTH (3)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_LSB (0)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_WIDTH (1)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_LSB (0)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_LSB (0)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_WIDTH (7)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_MASK (0x0000007F)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_LSB (4)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_WIDTH (1)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_MASK (0x00000010)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_BIT (0x00000010)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_LSB (0)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_WIDTH (3)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_MASK (0x00000007)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_LSB (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_WIDTH (1)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_MASK (0x00000010)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_BIT (0x00000010)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_LSB (0)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_WIDTH (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_LSB (0)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_WIDTH (1)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_MASK (0x00000001)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_BIT (0x00000001)
+
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_LSB (31)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_WIDTH (1)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_MASK (0x80000000)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_BIT (0x80000000)
+
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_LSB (0)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_WIDTH (21)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_MASK (0x001FFFFF)
+
+#define TXDFE_BB_DBG_1_RG_DBG_1_LSB (0)
+#define TXDFE_BB_DBG_1_RG_DBG_1_WIDTH (32)
+#define TXDFE_BB_DBG_1_RG_DBG_1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_2_RG_DBG_2_LSB (0)
+#define TXDFE_BB_DBG_2_RG_DBG_2_WIDTH (32)
+#define TXDFE_BB_DBG_2_RG_DBG_2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_3_RG_DBG_3_LSB (0)
+#define TXDFE_BB_DBG_3_RG_DBG_3_WIDTH (32)
+#define TXDFE_BB_DBG_3_RG_DBG_3_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_4_RG_DBG_4_LSB (0)
+#define TXDFE_BB_DBG_4_RG_DBG_4_WIDTH (32)
+#define TXDFE_BB_DBG_4_RG_DBG_4_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_5_RG_DBG_5_LSB (0)
+#define TXDFE_BB_DBG_5_RG_DBG_5_WIDTH (32)
+#define TXDFE_BB_DBG_5_RG_DBG_5_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_6_RG_DBG_6_LSB (0)
+#define TXDFE_BB_DBG_6_RG_DBG_6_WIDTH (32)
+#define TXDFE_BB_DBG_6_RG_DBG_6_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_7_RG_DBG_7_LSB (0)
+#define TXDFE_BB_DBG_7_RG_DBG_7_WIDTH (32)
+#define TXDFE_BB_DBG_7_RG_DBG_7_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_8_RG_DBG_8_LSB (0)
+#define TXDFE_BB_DBG_8_RG_DBG_8_WIDTH (32)
+#define TXDFE_BB_DBG_8_RG_DBG_8_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_9_RG_DBG_9_LSB (0)
+#define TXDFE_BB_DBG_9_RG_DBG_9_WIDTH (32)
+#define TXDFE_BB_DBG_9_RG_DBG_9_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_10_RG_DBG_10_LSB (0)
+#define TXDFE_BB_DBG_10_RG_DBG_10_WIDTH (32)
+#define TXDFE_BB_DBG_10_RG_DBG_10_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_11_RG_DBG_11_LSB (0)
+#define TXDFE_BB_DBG_11_RG_DBG_11_WIDTH (32)
+#define TXDFE_BB_DBG_11_RG_DBG_11_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_12_RG_DBG_12_LSB (0)
+#define TXDFE_BB_DBG_12_RG_DBG_12_WIDTH (32)
+#define TXDFE_BB_DBG_12_RG_DBG_12_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_13_RG_DBG_13_LSB (0)
+#define TXDFE_BB_DBG_13_RG_DBG_13_WIDTH (32)
+#define TXDFE_BB_DBG_13_RG_DBG_13_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_14_RG_DBG_14_LSB (0)
+#define TXDFE_BB_DBG_14_RG_DBG_14_WIDTH (32)
+#define TXDFE_BB_DBG_14_RG_DBG_14_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_15_RG_DBG_15_LSB (0)
+#define TXDFE_BB_DBG_15_RG_DBG_15_WIDTH (32)
+#define TXDFE_BB_DBG_15_RG_DBG_15_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_16_RG_DBG_16_LSB (0)
+#define TXDFE_BB_DBG_16_RG_DBG_16_WIDTH (32)
+#define TXDFE_BB_DBG_16_RG_DBG_16_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_LSB (24)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_WIDTH (2)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_MASK (0x03000000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_LSB (16)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_MASK (0x001F0000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_LSB (8)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_MASK (0x00001F00)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_LSB (0)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_MASK (0x00000001)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_LSB (0)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_WIDTH (1)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_LSB (0)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_WIDTH (1)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_LSB (16)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_LSB (16)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+
+
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_LSB (4)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_MASK (0x00000010)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_BIT (0x00000010)
+
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_LSB (0)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_MASK (0x00000001)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_BIT (0x00000001)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_LSB (6)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_LSB (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_LSB (0)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_LSB (6)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_LSB (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_LSB (0)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_LSB (6)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_LSB (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_LSB (0)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_MASK (0x00000007)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_MASK (0x00000003)
+
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_LSB (0)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_LSB (0)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_LSB (0)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_LSB (0)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_LSB (0)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_LSB (0)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_LSB (4)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_MASK (0x00000010)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_BIT (0x00000010)
+
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_LSB (0)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_LSB (0)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_WIDTH (32)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_LSB (0)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_WIDTH (1)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_MASK (0x00000001)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_BIT (0x00000001)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_LSB (8)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_WIDTH (24)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_LSB (4)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_WIDTH (3)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_LSB (0)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_WIDTH (1)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_LSB (0)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_LSB (0)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_WIDTH (7)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_MASK (0x0000007F)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_LSB (4)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_WIDTH (1)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_MASK (0x00000010)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_BIT (0x00000010)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_LSB (0)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_WIDTH (3)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_MASK (0x00000007)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_LSB (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_WIDTH (1)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_MASK (0x00000010)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_BIT (0x00000010)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_LSB (0)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_WIDTH (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_LSB (0)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_WIDTH (1)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_MASK (0x00000001)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_BIT (0x00000001)
+
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_LSB (31)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_WIDTH (1)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_MASK (0x80000000)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_BIT (0x80000000)
+
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_LSB (0)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_WIDTH (21)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_MASK (0x001FFFFF)
+
+#define TXDFE_BB_DBG_1_RG_DBG_1_LSB (0)
+#define TXDFE_BB_DBG_1_RG_DBG_1_WIDTH (32)
+#define TXDFE_BB_DBG_1_RG_DBG_1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_2_RG_DBG_2_LSB (0)
+#define TXDFE_BB_DBG_2_RG_DBG_2_WIDTH (32)
+#define TXDFE_BB_DBG_2_RG_DBG_2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_3_RG_DBG_3_LSB (0)
+#define TXDFE_BB_DBG_3_RG_DBG_3_WIDTH (32)
+#define TXDFE_BB_DBG_3_RG_DBG_3_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_4_RG_DBG_4_LSB (0)
+#define TXDFE_BB_DBG_4_RG_DBG_4_WIDTH (32)
+#define TXDFE_BB_DBG_4_RG_DBG_4_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_5_RG_DBG_5_LSB (0)
+#define TXDFE_BB_DBG_5_RG_DBG_5_WIDTH (32)
+#define TXDFE_BB_DBG_5_RG_DBG_5_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_6_RG_DBG_6_LSB (0)
+#define TXDFE_BB_DBG_6_RG_DBG_6_WIDTH (32)
+#define TXDFE_BB_DBG_6_RG_DBG_6_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_7_RG_DBG_7_LSB (0)
+#define TXDFE_BB_DBG_7_RG_DBG_7_WIDTH (32)
+#define TXDFE_BB_DBG_7_RG_DBG_7_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_8_RG_DBG_8_LSB (0)
+#define TXDFE_BB_DBG_8_RG_DBG_8_WIDTH (32)
+#define TXDFE_BB_DBG_8_RG_DBG_8_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_9_RG_DBG_9_LSB (0)
+#define TXDFE_BB_DBG_9_RG_DBG_9_WIDTH (32)
+#define TXDFE_BB_DBG_9_RG_DBG_9_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_10_RG_DBG_10_LSB (0)
+#define TXDFE_BB_DBG_10_RG_DBG_10_WIDTH (32)
+#define TXDFE_BB_DBG_10_RG_DBG_10_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_11_RG_DBG_11_LSB (0)
+#define TXDFE_BB_DBG_11_RG_DBG_11_WIDTH (32)
+#define TXDFE_BB_DBG_11_RG_DBG_11_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_12_RG_DBG_12_LSB (0)
+#define TXDFE_BB_DBG_12_RG_DBG_12_WIDTH (32)
+#define TXDFE_BB_DBG_12_RG_DBG_12_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_13_RG_DBG_13_LSB (0)
+#define TXDFE_BB_DBG_13_RG_DBG_13_WIDTH (32)
+#define TXDFE_BB_DBG_13_RG_DBG_13_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_14_RG_DBG_14_LSB (0)
+#define TXDFE_BB_DBG_14_RG_DBG_14_WIDTH (32)
+#define TXDFE_BB_DBG_14_RG_DBG_14_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_15_RG_DBG_15_LSB (0)
+#define TXDFE_BB_DBG_15_RG_DBG_15_WIDTH (32)
+#define TXDFE_BB_DBG_15_RG_DBG_15_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_16_RG_DBG_16_LSB (0)
+#define TXDFE_BB_DBG_16_RG_DBG_16_WIDTH (32)
+#define TXDFE_BB_DBG_16_RG_DBG_16_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_LSB (24)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_WIDTH (2)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_MASK (0x03000000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_LSB (16)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_MASK (0x001F0000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_LSB (8)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_MASK (0x00001F00)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_LSB (0)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_MASK (0x00000001)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_LSB (0)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_WIDTH (1)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_LSB (0)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_WIDTH (1)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_LSB (16)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_LSB (16)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb_97.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_97.h
new file mode 100644
index 0000000..3f32c62
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_97.h
@@ -0,0 +1,399 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* FILE NAME: : cphtxdfebbd
+* DESCRIPTION: Txdfebb D-die related registers
+*
+*****************************************************************************/
+
+
+
+#ifndef _CPH_TXDFE_BB_D_H_
+#define _CPH_TXDFE_BB_D_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXDFE_D_CC0_REG_BASE (0XA8AB2000)
+
+
+#define TXDFE_D_CC0_end (TXDFE_D_CC0_REG_BASE + 0x248 + 1*4)
+
+
+
+
+
+
+#define TXDFE_BB_REG_PROTECT ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x000))
+#define TXDFE_BB_GLB_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x004))
+#define TXDFE_BB_SW_CON_SINE ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x008))
+#define TXDFE_BB_L_CON_DEL_CAL ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x00C))
+#define TXDFE_BB_SRC_FIFO_PTR_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x010))
+#define TXDFE_BB_C2K_IS95_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x014))
+#define TXDFE_BB_CRC_CON0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x018))
+#define TXDFE_BB_CRC_OUT_G0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x01C))
+#define TXDFE_BB_CRC_CON1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x020))
+#define TXDFE_BB_CRC_OUT_G1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x024))
+#define TXDFE_BB_CRC_CON2 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x028))
+#define TXDFE_BB_CRC_OUT_G2 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x02C))
+#define TXDFE_BB_PCC_INFO ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x030))
+#define TXDFE_BB_PCC_CON0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x034))
+#define SERDES_TICK_DELAY ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x038))
+#define IRQ_STATUS ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x040))
+#define IRQ_MASK ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x044))
+#define IRQ_CLEAR ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x048))
+#define TXDFE_BB_TEST_SEL ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x04C))
+#define TXDFE_BB_DBG_0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x050))
+#define TXDFE_BB_DBG_1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x054))
+#define TXDFE_BB_DBG_2 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x058))
+#define TXDFE_BB_DBG_3 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x05C))
+#define TXDFE_BB_DBG_4 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x060))
+#define TXDFE_BB_DBG_5 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x064))
+#define TXDFE_BB_DBG_6 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x068))
+#define TXDFE_BB_DBG_7 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x06C))
+#define TXDFE_BB_DBG_8 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x070))
+#define TXDFE_BB_DBG_9 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x074))
+#define TXDFE_BB_DBG_10 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x078))
+#define TXDFE_BB_DBG_11 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x07C))
+#define TXDFE_BB_DBG_12 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x080))
+#define TXDFE_BB_DBG_13 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x084))
+#define TXDFE_BB_DBG_14 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x088))
+#define TXDFE_BB_DBG_15 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x08C))
+#define FIR_SUP_CON_G0_PART0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x090))
+#define FIR_SUP_CON_G0_PART1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x094))
+#define TXDFE_WIN_REG_PROTECT ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x100))
+#define TQ_0_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x110))
+#define SERDES_PRE_EN_ON_0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x200))
+#define SERDES_EN_OFF_0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x218))
+#define SERDES_EN_ON_OFFSET ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x230))
+#define SERDES_PRE_EN_OFF_OFFSET ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x234))
+#define SERDES_WIN_ENABLE ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x238)) /* SW can use it or not*/
+#define TXDFE_D_SERDES_PRE_EN_SW ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x240))
+#define TXDFE_D_SERDES_EN_SW ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x244))
+#define TXDFE_D_DFE_WIN_SW ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x248))
+
+
+
+
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_LSB (4)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_MASK (0x00000010)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_BIT (0x00000010)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_LSB (0)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_0_LSB (0)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_0_WIDTH (7)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_0_MASK (0x0000007F)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_LSB (4)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_WIDTH (1)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_MASK (0x00000010)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_BIT (0x00000010)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_0_LSB (0)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_0_WIDTH (3)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_0_MASK (0x00000007)
+
+#define SERDES_TICK_DELAY_SERDES_TICK_DELAY_LSB (0)
+#define SERDES_TICK_DELAY_SERDES_TICK_DELAY_WIDTH (5)
+#define SERDES_TICK_DELAY_SERDES_TICK_DELAY_MASK (0x0000001F)
+
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_LSB (1)
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_WIDTH (1)
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_MASK (0x00000002)
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_BIT (0x00000002)
+
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_LSB (0)
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_WIDTH (1)
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_MASK (0x00000001)
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_BIT (0x00000001)
+
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_LSB (1)
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_WIDTH (1)
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_MASK (0x00000002)
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_BIT (0x00000002)
+
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_LSB (0)
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_WIDTH (1)
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_MASK (0x00000001)
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_BIT (0x00000001)
+
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_LSB (1)
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_WIDTH (1)
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_MASK (0x00000002)
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_BIT (0x00000002)
+
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_LSB (0)
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_WIDTH (1)
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_MASK (0x00000001)
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_BIT (0x00000001)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_LSB (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_WIDTH (1)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_MASK (0x00000010)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_BIT (0x00000010)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_LSB (0)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_WIDTH (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_DBG_0_RG_DBG_0_LSB (0)
+#define TXDFE_BB_DBG_0_RG_DBG_0_WIDTH (32)
+#define TXDFE_BB_DBG_0_RG_DBG_0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_1_RG_DBG_1_LSB (0)
+#define TXDFE_BB_DBG_1_RG_DBG_1_WIDTH (32)
+#define TXDFE_BB_DBG_1_RG_DBG_1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_2_RG_DBG_2_LSB (0)
+#define TXDFE_BB_DBG_2_RG_DBG_2_WIDTH (32)
+#define TXDFE_BB_DBG_2_RG_DBG_2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_3_RG_DBG_3_LSB (0)
+#define TXDFE_BB_DBG_3_RG_DBG_3_WIDTH (32)
+#define TXDFE_BB_DBG_3_RG_DBG_3_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_4_RG_DBG_4_LSB (0)
+#define TXDFE_BB_DBG_4_RG_DBG_4_WIDTH (32)
+#define TXDFE_BB_DBG_4_RG_DBG_4_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_5_RG_DBG_5_LSB (0)
+#define TXDFE_BB_DBG_5_RG_DBG_5_WIDTH (32)
+#define TXDFE_BB_DBG_5_RG_DBG_5_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_6_RG_DBG_6_LSB (0)
+#define TXDFE_BB_DBG_6_RG_DBG_6_WIDTH (32)
+#define TXDFE_BB_DBG_6_RG_DBG_6_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_7_RG_DBG_7_LSB (0)
+#define TXDFE_BB_DBG_7_RG_DBG_7_WIDTH (32)
+#define TXDFE_BB_DBG_7_RG_DBG_7_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_8_RG_DBG_8_LSB (0)
+#define TXDFE_BB_DBG_8_RG_DBG_8_WIDTH (32)
+#define TXDFE_BB_DBG_8_RG_DBG_8_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_9_RG_DBG_9_LSB (0)
+#define TXDFE_BB_DBG_9_RG_DBG_9_WIDTH (32)
+#define TXDFE_BB_DBG_9_RG_DBG_9_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_10_RG_DBG_10_LSB (0)
+#define TXDFE_BB_DBG_10_RG_DBG_10_WIDTH (32)
+#define TXDFE_BB_DBG_10_RG_DBG_10_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_11_RG_DBG_11_LSB (0)
+#define TXDFE_BB_DBG_11_RG_DBG_11_WIDTH (32)
+#define TXDFE_BB_DBG_11_RG_DBG_11_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_12_RG_DBG_12_LSB (0)
+#define TXDFE_BB_DBG_12_RG_DBG_12_WIDTH (32)
+#define TXDFE_BB_DBG_12_RG_DBG_12_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_13_RG_DBG_13_LSB (0)
+#define TXDFE_BB_DBG_13_RG_DBG_13_WIDTH (32)
+#define TXDFE_BB_DBG_13_RG_DBG_13_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_14_RG_DBG_14_LSB (0)
+#define TXDFE_BB_DBG_14_RG_DBG_14_WIDTH (32)
+#define TXDFE_BB_DBG_14_RG_DBG_14_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_15_RG_DBG_15_LSB (0)
+#define TXDFE_BB_DBG_15_RG_DBG_15_WIDTH (32)
+#define TXDFE_BB_DBG_15_RG_DBG_15_MASK (0xFFFFFFFF)
+
+#define FIR_SUP_CON_G0_PART0_FIR_SUP_LEN_CTRL_G0_PART0_LSB (0)
+#define FIR_SUP_CON_G0_PART0_FIR_SUP_LEN_CTRL_G0_PART0_WIDTH (32)
+#define FIR_SUP_CON_G0_PART0_FIR_SUP_LEN_CTRL_G0_PART0_MASK (0xFFFFFFFF)
+
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_LSB (22)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_WIDTH (1)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_MASK (0x00400000)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_BIT (0x00400000)
+
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_GAIN_G0_LSB (10)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_GAIN_G0_WIDTH (12)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_GAIN_G0_MASK (0x003FFC00)
+
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_LEN_CTRL_G0_PART1_LSB (0)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_LEN_CTRL_G0_PART1_WIDTH (3)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_LEN_CTRL_G0_PART1_MASK (0x00000007)
+
+#define TXDFE_WIN_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_WIN_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_WIN_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+
+#define TQ_0_CON_RG_TQ_0_TRG_LSB (0)
+#define TQ_0_CON_RG_TQ_0_TRG_WIDTH (1)
+#define TQ_0_CON_RG_TQ_0_TRG_MASK (0x00000001)
+
+#define TQ_0_CON_RG_TQ_0_RST_LSB (1)
+#define TQ_0_CON_RG_TQ_0_RST_WIDTH (1)
+#define TQ_0_CON_RG_TQ_0_RST_MASK (0x00000002)
+
+#define TQ_0_CON_RG_G0_LSB (2)
+#define TQ_0_CON_RG_G0_WIDTH (12)
+#define TQ_0_CON_RG_G0_MASK (0x000007FC)
+
+#define SERDES_PRE_EN_ON_0_LSB (0)
+#define SERDES_PRE_EN_ON_0_WIDTH (21)
+#define SERDES_PRE_EN_ON_0_MASK (0x0001FFFF)
+
+#define SERDES_EN_OFF_0_LSB (0)
+#define SERDES_EN_OFF_0_WIDTH (21)
+#define SERDES_EN_OFF_0_MASK (0x0001FFFF)
+
+#define SERDES_EN_ON_OFFSET_LSB (0)
+#define SERDES_EN_ON_OFFSET_WIDTH (10)
+#define SERDES_EN_ON_OFFSET_MASK (0x000003FF)
+
+#define SERDES_PRE_EN_OFF_OFFSET_LSB (0)
+#define SERDES_PRE_EN_OFF_OFFSET_WIDTH (10)
+#define SERDES_PRE_EN_OFF_OFFSET_MASK (0x000003FF)
+
+#define SERDES_WIN_ENABLE_SERDES_PRE_EN_ON_0_ENABLE_LSB (0)
+#define SERDES_WIN_ENABLE_SERDES_PRE_EN_ON_0_ENABLE_WIDTH (1)
+#define SERDES_WIN_ENABLE_SERDES_PRE_EN_ON_0_ENABLE_MASK (0x00000001)
+
+#define SERDES_WIN_ENABLE_SERDES_EN_OFF_0_ENABLE_LSB (6)
+#define SERDES_WIN_ENABLE_SERDES_EN_OFF_0_ENABLE_WIDTH (1)
+#define SERDES_WIN_ENABLE_SERDES_EN_OFF_0_ENABLE_MASK (0x00000040)
+
+#define TXDFE_D_SERDES_PRE_EN_0_SW_LSB (0)
+#define TXDFE_D_SERDES_PRE_EN_0_SW_WIDTH (1)
+#define TXDFE_D_SERDES_PRE_EN_0_SW_MASK (0x00000001)
+
+#define TXDFE_D_SERDES_EN_0_SW_LSB (0)
+#define TXDFE_D_SERDES_EN_0_SW_WIDTH (1)
+#define TXDFE_D_SERDES_EN_0_SW_MASK (0x00000001)
+
+#define TXDFE_D_DFE_WIN_0_SW_LSB (0)
+#define TXDFE_D_DFE_WIN_0_SW_WIDTH (1)
+#define TXDFE_D_DFE_WIN_0_SW_MASK (0x00000001)
+
+
+
+#endif //#define _CPH_TXDFE_BB_D_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl.h
new file mode 100644
index 0000000..fd92af6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfig0reg_resctrl_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfigreg0_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphdfesysglbconfigreg0.h"
+#else
+#include "cphdfesysglbconfigreg0.h"/*#error "[ERROR] Invalid MD generation" For build error*/
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_93.h
new file mode 100644
index 0000000..25f9c96
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_93.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON0_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define TXSYS_CK_DIV_DBG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0018))
+#define DEBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DEBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC0_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define TXBRP_CC1_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0030))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP0_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP1_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x003c))
+#define TXBRP_CC0_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBRP_CC1_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define MASK_TXCRP_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0058))
+#define MASK_TXBRP_MAS_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x005c))
+#define MASK_TXBRP_SLV_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define SW_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x007c))
+#define MASK_MDAO_TXSYS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+
+#define DIV_TXBRP_DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_DIV_TXBRP_WIDTH (2)
+#define DIV_TXBRP_DIV_TXBRP_MASK (0x00000003)
+
+#define DIV_TXCRP_DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_LSB (0)
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_WIDTH (3)
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_MASK (0x00000007)
+
+#define DEBUG_SEL_DEBUG_SEL_3_LSB (24)
+#define DEBUG_SEL_DEBUG_SEL_3_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_3_MASK (0x0F000000)
+
+#define DEBUG_SEL_DEBUG_SEL_2_LSB (16)
+#define DEBUG_SEL_DEBUG_SEL_2_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_2_MASK (0x000F0000)
+
+#define DEBUG_SEL_DEBUG_SEL_1_LSB (8)
+#define DEBUG_SEL_DEBUG_SEL_1_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_1_MASK (0x00000F00)
+
+#define DEBUG_SEL_DEBUG_SEL_0_LSB (0)
+#define DEBUG_SEL_DEBUG_SEL_0_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_0_MASK (0x0000000F)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (4)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define DEBUG_WITH_CK_DEBUG_WITH_CK_LSB (0)
+#define DEBUG_WITH_CK_DEBUG_WITH_CK_WIDTH (5)
+#define DEBUG_WITH_CK_DEBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_LSB (0)
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_LSB (0)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_LSB (16)
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_LSB (0)
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_LSB (16)
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_LSB (0)
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_BIT (0x00000001)
+
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_LSB (0)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_WIDTH (1)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_MASK (0x00000001)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_95.h
new file mode 100644
index 0000000..d91cda8
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_95.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON0_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define DUBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DUBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0020))
+#define DUBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS_CFG0 ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define TXBRP_CC1_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0030))/*93stay*/
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP1_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x003c))/*93stay*/
+#define TXBRP_CC_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))/*93stay--*/
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define MASK_TXCRP_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0058))
+#define MASK_TXBRP_MAS_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x005c))
+#define MASK_TXBRP_SLV_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060))/*--93stay*/
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define SW_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x007c))/*93stay--*/
+#define MASK_MDAO_TXSYS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))/*--93stay*/
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+
+#define DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_MASK (0x00000001)
+
+#define DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_LSB (0)/*93stay--*/
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_WIDTH (3)
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_MASK (0x00000007)/*--93stay*/
+
+#define DUBUG_SEL_3_LSB (24)
+#define DUBUG_SEL_3_WIDTH (4)
+#define DUBUG_SEL_3_MASK (0x0F000000)
+
+#define DUBUG_SEL_2_LSB (16)
+#define DUBUG_SEL_2_WIDTH (4)
+#define DUBUG_SEL_2_MASK (0x000F0000)
+
+#define DUBUG_SEL_1_LSB (8)
+#define DUBUG_SEL_1_WIDTH (4)
+#define DUBUG_SEL_1_MASK (0x00000F00)
+
+#define DUBUG_SEL_0_LSB (0)
+#define DUBUG_SEL_0_WIDTH (4)
+#define DUBUG_SEL_0_MASK (0x0000000F)
+
+#define DUBUG_TRIG_SEL_LSB (0)
+#define DUBUG_TRIG_SEL_WIDTH (1)
+#define DUBUG_TRIG_SEL_MASK (0x00000001)
+
+#define DUBUG_WITH_CK_LSB (0)
+#define DUBUG_WITH_CK_WIDTH (5)
+#define DUBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC_SW_CKEN_LSB (0)
+#define TXBRP_CC_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_LSB (0)/*93stay--*/
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_BIT (0x00000001)/*--93stay*/
+
+#define SW_RAKE_DATA_LSB (8)
+#define SW_RAKE_DATA_WIDTH (11)
+#define SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define SW_RAKE_ADDR_LSB (4)
+#define SW_RAKE_ADDR_WIDTH (4)
+#define SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define SW_RAKE_RSV_LSB (1)
+#define SW_RAKE_RSV_WIDTH (3)
+#define SW_RAKE_RSV_MASK (0x0000000E)
+
+#define SW_VLD_TGL_LSB (0)
+#define SW_VLD_TGL_WIDTH (1)
+#define SW_VLD_TGL_MASK (0x00000001)
+#define SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_LSB (0)/*93stay--*/
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_BIT (0x00000001)/*--93stay*/
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_LSB (0)/*93stay--*/
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_BIT (0x00000001)
+
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_BIT (0x00000001)/*--93stay*/
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)/*93stay--*/
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_LSB (0)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_WIDTH (1)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_MASK (0x00000001)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_BIT (0x00000001)/*--93stay*/
+
+#define R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl.h
new file mode 100644
index 0000000..c714ade
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfig1reg_resctrl_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfig1reg_resctrl_95.h"
+#elif defined(__MD97__)
+#include "cphdfesysglbconfigreg1.h"
+#else
+#include "cphdfesysglbconfigreg1.h"/*#error "[ERROR] Invalid MD generation" For build error*/
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_93.h
new file mode 100644
index 0000000..8828d1b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_93.h
@@ -0,0 +1,151 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON1_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON1_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define BUS_BUS2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002c))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+//To remove the redefinition warning, the following 2 register are also defined in cphtxsysglbconfig1reg_resctrl.h, need to check with DE is the CODA correct
+//#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+//#define DEBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007C))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define INTRA_BAND_CA ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+
+
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_LSB (0)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_WIDTH (1)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_MASK (0x00000001)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_BIT (0x00000001)
+
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_LSB (0)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_WIDTH (1)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_BIT (0x00000001)
+
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_LSB (0)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_LSB (0)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)
+
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_LSB (0)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_WIDTH (1)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_MASK (0x00000001)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_BIT (0x00000001)
+
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (4)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_BIT (0x00000001)
+
+#define INTRA_BAND_CA_INTRA_BAND_CA_LSB (0)
+#define INTRA_BAND_CA_INTRA_BAND_CA_WIDTH (2)
+#define INTRA_BAND_CA_INTRA_BAND_CA_MASK (0x00000003)
+
+
+#endif /*_CPH_TXSYS_GLB_CON1_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_95.h
new file mode 100644
index 0000000..8828d1b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_95.h
@@ -0,0 +1,151 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON1_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON1_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define BUS_BUS2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002c))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+//To remove the redefinition warning, the following 2 register are also defined in cphtxsysglbconfig1reg_resctrl.h, need to check with DE is the CODA correct
+//#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+//#define DEBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007C))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define INTRA_BAND_CA ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+
+
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_LSB (0)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_WIDTH (1)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_MASK (0x00000001)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_BIT (0x00000001)
+
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_LSB (0)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_WIDTH (1)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_BIT (0x00000001)
+
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_LSB (0)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_LSB (0)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)
+
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_LSB (0)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_WIDTH (1)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_MASK (0x00000001)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_BIT (0x00000001)
+
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (4)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_BIT (0x00000001)
+
+#define INTRA_BAND_CA_INTRA_BAND_CA_LSB (0)
+#define INTRA_BAND_CA_INTRA_BAND_CA_WIDTH (2)
+#define INTRA_BAND_CA_INTRA_BAND_CA_MASK (0x00000003)
+
+
+#endif /*_CPH_TXSYS_GLB_CON1_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0.h
new file mode 100644
index 0000000..5821576
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfigreg0_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfigreg0_95.h"
+#else
+#error "[ERROR] Invalid MD generation" /* The module have delete in 97, which is moved to dfesysconfigreg0 module */
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_93.h
new file mode 100644
index 0000000..b38875c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_93.h
@@ -0,0 +1,246 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CONFIG_H_
+#define _CPH_TXSYS_GLB_CONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define TXSYS_CK_DIV_DBG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0018))
+#define DUBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DUBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0020))
+#define DUBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC0_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define TXBRP_CC1_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0030))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP0_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP1_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x003c))
+#define TXBRP_CC0_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBRP_CC1_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define MASK_TXCRP_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0058))
+#define MASK_TXBRP_MAS_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x005c))
+#define MASK_TXBRP_SLV_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+
+#define DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_WIDTH (2)
+#define DIV_TXBRP_MASK (0x00000003)
+
+#define DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define TXSYS_CK_DIV_DBG_SEL_LSB (0)
+#define TXSYS_CK_DIV_DBG_SEL_WIDTH (2)
+#define TXSYS_CK_DIV_DBG_SEL_MASK (0x00000003)
+
+#define DUBUG_SEL_3_LSB (24)
+#define DUBUG_SEL_3_WIDTH (4)
+#define DUBUG_SEL_3_MASK (0x0F000000)
+
+#define DUBUG_SEL_2_LSB (16)
+#define DUBUG_SEL_2_WIDTH (4)
+#define DUBUG_SEL_2_MASK (0x000F0000)
+
+#define DUBUG_SEL_1_LSB (8)
+#define DUBUG_SEL_1_WIDTH (4)
+#define DUBUG_SEL_1_MASK (0x00000F00)
+
+#define DUBUG_SEL_0_LSB (0)
+#define DUBUG_SEL_0_WIDTH (4)
+#define DUBUG_SEL_0_MASK (0x0000000F)
+
+#define DUBUG_TRIG_SEL_LSB (0)
+#define DUBUG_TRIG_SEL_WIDTH (4)
+#define DUBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define DUBUG_WITH_CK_LSB (0)
+#define DUBUG_WITH_CK_WIDTH (5)
+#define DUBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC0_SW_CKEN_LSB (0)
+#define TXBRP_CC0_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_SW_CKEN_LSB (0)
+#define TXBRP_CC1_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define SW_RAKE_DATA_LSB (8)
+#define SW_RAKE_DATA_WIDTH (11)
+#define SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define SW_RAKE_ADDR_LSB (4)
+#define SW_RAKE_ADDR_WIDTH (4)
+#define SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define SW_RAKE_RSV_LSB (1)
+#define SW_RAKE_RSV_WIDTH (3)
+#define SW_RAKE_RSV_MASK (0x0000000E)
+
+#define SW_VLD_TGL_LSB (0)
+#define SW_VLD_TGL_WIDTH (1)
+#define SW_VLD_TGL_MASK (0x00000001)
+#define SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP0_TXBRP_SW_RESET_LSB (16)
+#define TXBRP0_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP0_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP0_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP0_TXSRP_SW_RESET_LSB (0)
+#define TXBRP0_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP0_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP0_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP1_TXBRP_SW_RESET_LSB (16)
+#define TXBRP1_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP1_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP1_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP1_TXSRP_SW_RESET_LSB (0)
+#define TXBRP1_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP1_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP1_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXCRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP_MAS_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_MAS_BUS_IDLE_BIT (0x00000001)
+
+#define MASK_TXBRP_SLV_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_SLV_BUS_IDLE_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+#endif //#ifndef _CPH_TXSYS_GLB_CONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_95.h
new file mode 100644
index 0000000..892fb10
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_95.h
@@ -0,0 +1,221 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CONFIG_H_
+#define _CPH_TXSYS_GLB_CONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100 + 1*4)
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define DUBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DUBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0020))
+#define DUBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS_CFG0 ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP_CC_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+#define DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_MASK (0x00000001)
+
+#define DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define DUBUG_SEL_3_LSB (24)
+#define DUBUG_SEL_3_WIDTH (4)
+#define DUBUG_SEL_3_MASK (0x0F000000)
+
+#define DUBUG_SEL_2_LSB (16)
+#define DUBUG_SEL_2_WIDTH (4)
+#define DUBUG_SEL_2_MASK (0x000F0000)
+
+#define DUBUG_SEL_1_LSB (8)
+#define DUBUG_SEL_1_WIDTH (4)
+#define DUBUG_SEL_1_MASK (0x00000F00)
+
+#define DUBUG_SEL_0_LSB (0)
+#define DUBUG_SEL_0_WIDTH (4)
+#define DUBUG_SEL_0_MASK (0x0000000F)
+
+#define DUBUG_TRIG_SEL_LSB (0)
+#define DUBUG_TRIG_SEL_WIDTH (1)
+#define DUBUG_TRIG_SEL_MASK (0x00000001)
+
+#define DUBUG_WITH_CK_LSB (0)
+#define DUBUG_WITH_CK_WIDTH (5)
+#define DUBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC_SW_CKEN_LSB (0)
+#define TXBRP_CC_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define SW_RAKE_DATA_LSB (8)
+#define SW_RAKE_DATA_WIDTH (11)
+#define SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define SW_RAKE_ADDR_LSB (4)
+#define SW_RAKE_ADDR_WIDTH (4)
+#define SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define SW_RAKE_RSV_LSB (1)
+#define SW_RAKE_RSV_WIDTH (3)
+#define SW_RAKE_RSV_MASK (0x0000000E)
+
+#define SW_VLD_TGL_LSB (0)
+#define SW_VLD_TGL_WIDTH (1)
+#define SW_VLD_TGL_MASK (0x00000001)
+#define SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_BIT (0x00000001)
+#endif //#ifndef _CPH_TXSYS_GLB_CONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1.h
new file mode 100644
index 0000000..0ce6366
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfigreg1_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfigreg1_95.h"
+#else
+#error "[ERROR] Invalid MD generation" /* The module have delete in 97, which is moved to dfesysconfigreg1 module */
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_93.h
new file mode 100644
index 0000000..33613b0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_93.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLBCON_CONFIG1_H_
+#define _CPH_TXSYS_GLBCON_CONFIG1_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0088)
+
+
+
+
+#define BUS_BUS_2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_RF_BBTX_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0028))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002C))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TXDFE_RF_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0034))
+#define TXDFE_RF_BBTX_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0038))
+#define TXDFE_BB_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x003c))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define FDD_TTR_F13M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0050))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TDD_TTR_F4P3M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0058))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+#define TXK_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))
+#define TXSYS_DEBUG_BUS_CFG1 ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))
+#define LTE_TTR0_F104M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0080))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define LTE_TTR1_F104M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0088))
+#define INTRA_BAND_CA ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_95.h
new file mode 100644
index 0000000..7cc1592
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_95.h
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLBCON_CONFIG1_H_
+#define _CPH_TXSYS_GLBCON_CONFIG1_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0094 + 1*4)
+
+
+
+
+#define BUS_BUS_2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002C))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+#define TXET_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))
+#define TXSYS_DEBUG_BUS_CFG1 ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+#define TXSYS_DEBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define LTE_TTR2_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0088))
+#define AMSC_REF_B0_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x008c))
+#define AMSC_REF_B1_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0090))
+#define AMSC_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0094))
+
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/c2k_dma_model_api.h b/mcu/interface/l1/cl1/common/c2k_dma_model_api.h
new file mode 100644
index 0000000..9854182
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/c2k_dma_model_api.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * c2k_dma_model_api.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * C2K DMA hardware model api header file
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _C2K_DMA_MODEL_API_H
+#define _C2K_DMA_MODEL_API_H
+
+#include "kal_general_types.h"
+
+/*-----------------**
+** Register Access **
+**-----------------*/
+
+extern void hwd_write(kal_uint32 reg, kal_int16 data);
+extern kal_int16 hwd_read(kal_uint32 reg);
+extern void hwd_set_bit(kal_uint32 reg, kal_uint32 bit_mask);
+extern void hwd_clear_bit(kal_uint32 reg, kal_uint32 bit_mask);
+
+/* 32-Bit Register MACROS - used by USB */
+extern void hwd_write_32(kal_uint32 reg, kal_int32 data);
+extern kal_int32 hwd_read_32(kal_uint32 reg);
+extern void hwd_set_bit_32(kal_uint32 reg, kal_uint32 bit_mask);
+extern void hwd_reset_bit_32(kal_uint32 reg, kal_uint32 bit_mask);
+
+/* 16-Bit Register MACROS */
+extern void hwd_write_16(kal_uint32 reg, kal_int16 data);
+extern kal_int16 hwd_read_16(kal_uint32 reg);
+extern void hwd_set_bit_16(kal_uint32 reg, kal_uint16 bit_mask);
+extern void hwd_reset_bit_16(kal_uint32 reg, kal_uint16 bit_mask);
+
+/* 8-Bit Register MACROS - used by EBI */
+extern void hwd_write_8(kal_uint32 reg, kal_int8 data);
+extern kal_int8 hwd_read_8(kal_uint32 reg);
+extern void hwd_set_bit_8(kal_uint32 reg, kal_uint8 bit_mask);
+extern void hwd_reset_bit_8(kal_uint32 reg, kal_uint8 bit_mask);
+
+#endif /* _C2K_DMA_MODEL_API_H */
diff --git a/mcu/interface/l1/cl1/common/c2k_rsva_enums.h b/mcu/interface/l1/cl1/common/c2k_rsva_enums.h
new file mode 100644
index 0000000..4b3d5bb
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/c2k_rsva_enums.h
@@ -0,0 +1,136 @@
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * c2k_rsva_enums.h
+ *
+ * Project:
+ * --------
+ * SRLTE
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ******************************************************************************/
+#ifndef _C2K_RSVA_ENUMS_H_
+#define _C2K_RSVA_ENUMS_H_
+
+
+// #ifdef __CDMA2000_RAT__
+
+/*----------------------------------------------------------------------------*/
+/* MD3 CSS <--> MD1 RSVAC */
+/*----------------------------------------------------------------------------*/
+
+typedef enum {
+ CSS_FREQ_SCAN_FINISHED,
+ CSS_FREQ_SCAN_PREEMPTED
+}css_freq_scan_stop_cause_enum;
+
+typedef enum {
+ CSS_E911_CALL,
+ CSS_USER_TRIGGER_SEARCH,
+ CSS_ORDINARY_SEARCH,
+ CSS_FREQ_SCAN_NULL
+}css_freq_scan_type_enum;
+
+
+/*----------------------------------------------------------------------------*/
+/* MD3 PSW <--> MD1 RSVAS */
+/*----------------------------------------------------------------------------*/
+typedef enum {
+ RSVAS_ID_NONE = 0x00FFFFFF
+
+ ,RSVAS_ID_SIM1_GAS = 0x010000FF
+ ,RSVAS_ID_SIM1_UAS = 0x020001FF
+ ,RSVAS_ID_SIM1_EAS = 0x030002FF
+ ,RSVAS_ID_SIM1_EVDO = 0x040003FF
+ ,RSVAS_ID_SIM1_1XRTT = 0x050004FF
+ ,RSVAS_ID_SIM1_NAS = 0x0600FF01
+ ,RSVAS_ID_SIM1_L4C = 0x0700FF02
+
+ ,RSVAS_ID_SIM2_GAS = 0x080100FF
+ ,RSVAS_ID_SIM2_UAS = 0x090101FF
+ ,RSVAS_ID_SIM2_EAS = 0x0A0102FF
+ ,RSVAS_ID_SIM2_EVDO = 0x0B0103FF
+ ,RSVAS_ID_SIM2_1XRTT = 0x0C0104FF
+ ,RSVAS_ID_SIM2_NAS = 0x0D01FF01
+ ,RSVAS_ID_SIM2_L4C = 0x0E01FF02
+
+ ,RSVAS_ID_SIM3_GAS = 0x0F0200FF
+ ,RSVAS_ID_SIM3_UAS = 0x100201FF
+ ,RSVAS_ID_SIM3_EAS = 0x110202FF
+ ,RSVAS_ID_SIM3_EVDO = 0x120203FF
+ ,RSVAS_ID_SIM3_1XRTT = 0x130204FF
+ ,RSVAS_ID_SIM3_NAS = 0x1402FF01
+ ,RSVAS_ID_SIM3_L4C = 0x1502FF02
+
+ ,RSVAS_ID_SIM4_GAS = 0x160300FF
+ ,RSVAS_ID_SIM4_UAS = 0x170301FF
+ ,RSVAS_ID_SIM4_EAS = 0x180302FF
+ ,RSVAS_ID_SIM4_EVDO = 0x190303FF
+ ,RSVAS_ID_SIM4_1XRTT = 0x1A0304FF
+ ,RSVAS_ID_SIM4_NAS = 0x1B03FF01
+ ,RSVAS_ID_SIM4_L4C = 0x1C03FF02
+
+} rsvas_id_enum;
+
+
+typedef enum {
+ RSVAS_SIM1 = 0
+ ,RSVAS_SIM2 = 1
+ ,RSVAS_SIM3 = 2
+ ,RSVAS_SIM4 = 3
+ ,RSVAS_SIM_NONE = 0xFF
+} rsvas_sim_enum;
+
+/**
+ * For GEN95 & 97
+ */
+typedef enum {
+ RSVAS_SUSPEND_AFTER_ABORT,
+ RSVAS_VIRTUAL_IDLE_AFTER_ABORT,
+ RSVAS_ABORT_ACTION_NONE
+} rsvas_abort_action_enum;
+// #endif /* __CDMA2000_RAT__ */
+
+#endif /* _C2K_RSVA_ENUMS_H_ */
diff --git a/mcu/interface/l1/cl1/common/c2k_rsva_struct.h b/mcu/interface/l1/cl1/common/c2k_rsva_struct.h
new file mode 100644
index 0000000..57d94a1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/c2k_rsva_struct.h
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * c2k_rsva_struct.h
+ *
+ * Project:
+ * --------
+ * SRLTE
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ******************************************************************************/
+#ifndef _C2K_RSVA_STRUCT_H_
+#define _C2K_RSVA_STRUCT_H_
+
+#include "c2k_rsva_enums.h"
+
+// #ifdef __CDMA2000_RAT__
+
+/*----------------------------------------------------------------------------*/
+/* MD3 CSS <--> MD1 RSVAC */
+/*----------------------------------------------------------------------------*/
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ css_freq_scan_type_enum freq_scan_type;
+ kal_bool is_full_band;
+ kal_uint8 session_id; /* session id */
+}css_rsvac_frequency_scan_start_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ css_freq_scan_stop_cause_enum cause;
+ /* preemption session id, only used when cause=CSS_FREQ_SCAN_PREEMPTED */
+ /* always release the resource when cause=CSS_FREQ_SCAN_FINISHED */
+ kal_uint8 session_id; /* session id */
+}css_rsvac_frequency_scan_stop_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ css_freq_scan_type_enum freq_scan_type;
+ kal_bool is_full_band;
+ kal_uint8 session_id; /* session id */
+}css_rsvac_frequency_scan_modify_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 session_id; /* session id */
+#ifdef MTK_PLT_ON_PC_IT
+ kal_uint8 padding;
+#endif
+}rsvac_css_frequency_scan_accept_ind_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 preempt_session_id; /* preemption session id */
+}rsvac_css_frequency_scan_preempt_ind_struct;
+
+
+/*----------------------------------------------------------------------------*/
+/* MD3 PSW <--> MD1 RSVAS */
+/*----------------------------------------------------------------------------*/
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 peer_service_priority;
+ rsvas_sim_enum sim_in_transfer;
+} rsvas_cas_suspend_service_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 peer_service_priority;
+ rsvas_abort_action_enum action;
+} rsvas_cas_abort_service_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 peer_service_priority;
+ rsvas_sim_enum sim_in_transfer;
+} rsvas_cas_virtual_suspend_service_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ rsvas_sim_enum sim_in_transfer;
+} rsvas_cas_virtual_resume_service_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+} rsvas_cas_resume_service_req_struct;
+
+
+// #endif /* __CDMA2000_RAT__ */
+
+#endif /* _C2K_RSVA_STRUCT_H_ */
diff --git a/mcu/interface/l1/cl1/common/cl1_cc_public.h b/mcu/interface/l1/cl1/common/cl1_cc_public.h
new file mode 100644
index 0000000..a8decc3
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1_cc_public.h
@@ -0,0 +1,66 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1_cc_public.h
+ *
+ * Project:
+ * --------
+ * UMOLYA_Software
+ *
+ * Description:
+ * ------------
+ * CL1 public interface declare
+ *****************************************************************************/
+#ifndef _CL1_CC_PUBLIC_H_
+#define _CL1_CC_PUBLIC_H_
+
+#include "kal_general_types.h"
+
+
+extern kal_bool CL1_IS_C2K_EXIST(void);
+extern void CL1_FORCE_SLEEP(void);
+extern void CL1_ErrorCheck_TxBRP_WorkMode_Conflict_Assert_1xRTT(void);
+extern void CL1_ErrorCheck_TxBRP_WorkMode_Conflict_Assert_EVDO(void);
+
+#if defined(__CDMA2000_RAT__) /* C2K is built */
+extern void C2k1xRTT_l1_slp_info(kal_uint64 *working_time, kal_uint32 *wakeup_cnt, kal_uint32 *sleep_cnt);
+extern void C2kEVDO_l1_slp_info(kal_uint64 *working_time, kal_uint32 *wakeup_cnt, kal_uint32 *sleep_cnt);
+#endif
+
+#endif //#ifndef _CL1_CC_PUBLIC_H_
diff --git a/mcu/interface/l1/cl1/common/cl1_nvram_id.h b/mcu/interface/l1/cl1/common/cl1_nvram_id.h
new file mode 100644
index 0000000..3e3ca42
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1_nvram_id.h
@@ -0,0 +1,732 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1_nvram_id.h
+ *
+ * Project:
+ * --------
+ * 93
+ *
+ * Description:
+ * ------------
+ * C2K NVRAM item infomation provided to NVRAM, MMRF, and C2K itself.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#if defined(__MD93__) || defined(__MD95__)
+#define MIPI_RX_EVENT_MAX_NUM (9 +1)
+#define MIPI_RX_DATA_MAX_NUM (18 +1)
+#define MIPI_TX_EVENT_MAX_NUM (12 +1)
+#define MIPI_TX_DATA_MAX_NUM (36 +1)
+#define MIPI_TPC_EVENT_MAX_NUM (9 +1)
+#define MIPI_TPC_DATA_MAX_NUM (5 +1)
+#define MIPI_PA_SECTION_DATA_MAX_NUM C2K_MIPI_SUBBAND_NUM
+#define MIPI_ETM_TX_EVENT_MAX_NUM MIPI_TX_EVENT_MAX_NUM
+#define MIPI_ETM_TX_DATA_MAX_NUM MIPI_TX_DATA_MAX_NUM
+#define MIPI_ETM_TPC_EVENT_MAX_NUM MIPI_TPC_EVENT_MAX_NUM
+#define MIPI_ETM_TPC_DATA_MAX_NUM MIPI_TPC_DATA_MAX_NUM
+#define MIPI_ETM_PA_SECTION_DATA_MAX_NUM C2K_MIPI_SUBBAND_NUM
+
+#define MIPI_TAS_EVENT_MAX_NUM (10)
+#define MIPI_TAS_DATA_MAX_NUM (20)
+
+#define MIPI_ELNA_EVENT_MAX_NUM (10)
+#define MIPI_ELNA_DATA_MAX_NUM (20)
+
+#define MIPI_DAT_EVENT_MAX_NUM MIPI_TAS_EVENT_MAX_NUM
+#define MIPI_DAT_DATA_MAX_NUM MIPI_TAS_DATA_MAX_NUM
+/* NVRAM ID definition of items in C2K RF custom file */
+/* Common Parameters */
+/* 0 */NVRAM_ITEM_RF_CUST(CUST_PARAM, , 1, CUST_PARAM_T, 1, NULL)
+/* BPI Configurations */
+/* 1 */NVRAM_ITEM_RF_CUST(CUST_BPI_CFG, BAND_A, MAX_BAND_NUM, CUST_BPI_CFG_T, 1, NULL)
+/* 2 */NVRAM_ITEM_RF_CUST(CUST_BPI_CFG, BAND_B, MAX_BAND_NUM, CUST_BPI_CFG_T, 1, NULL)
+/* 3 */NVRAM_ITEM_RF_CUST(CUST_BPI_CFG, BAND_C, MAX_BAND_NUM, CUST_BPI_CFG_T, 1, NULL)
+/* 4 */NVRAM_ITEM_RF_CUST(CUST_BPI_CFG, BAND_D, MAX_BAND_NUM, CUST_BPI_CFG_T, 1, NULL)
+/* 5 */NVRAM_ITEM_RF_CUST(CUST_BPI_CFG, BAND_E, MAX_BAND_NUM, CUST_BPI_CFG_T, 1, NULL)
+
+/* TAS Configurations */
+//NVRAM_ITEM_RF_CUST(RF_CUST_TAS, DBM_RF_CUST_TAS_SIZE, hwdRfCustomTas, hwdRfCustTasInput, HwdRfCustTasProcess)
+//NVRAM_ITEM_RF_CUST(RF_CUST_TAS_BY_RAT, DBM_RF_CUST_TAS_BY_RAT_SIZE, C2K_TAS_FEATURE_BY_RAT, C2K_TAS_FEATURE_BY_RAT_INPUT, HwdRfCustTasByRatProcess)
+
+/////////////////////// GENARAL_NAME, RF_BAND, REC, TYPE, , TYPE NUM, FUNC
+
+/* MIPI Configurations */
+/* 6 */ NVRAM_ITEM_MIPI(MIPI_PARAM, , 1, MIPI_PARAM_T, 1, NULL)
+
+/* 7 */ NVRAM_ITEM_MIPI(MIPI_RX_EVENT, BAND_A, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_RX_EVENT_MAX_NUM, NULL)
+/* 8 */ NVRAM_ITEM_MIPI(MIPI_RX_EVENT, BAND_B, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_RX_EVENT_MAX_NUM, NULL)
+/* 9 */ NVRAM_ITEM_MIPI(MIPI_RX_EVENT, BAND_C, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_RX_EVENT_MAX_NUM, NULL)
+/* 10 */NVRAM_ITEM_MIPI(MIPI_RX_EVENT, BAND_D, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_RX_EVENT_MAX_NUM, NULL)
+/* 11 */NVRAM_ITEM_MIPI(MIPI_RX_EVENT, BAND_E, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_RX_EVENT_MAX_NUM, NULL)
+
+/* 12 */NVRAM_ITEM_MIPI(MIPI_RX_DATA, BAND_A, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_RX_DATA_MAX_NUM, NULL)
+/* 13 */NVRAM_ITEM_MIPI(MIPI_RX_DATA, BAND_B, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_RX_DATA_MAX_NUM, NULL)
+/* 14 */NVRAM_ITEM_MIPI(MIPI_RX_DATA, BAND_C, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_RX_DATA_MAX_NUM, NULL)
+/* 15 */NVRAM_ITEM_MIPI(MIPI_RX_DATA, BAND_D, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_RX_DATA_MAX_NUM, NULL)
+/* 16 */NVRAM_ITEM_MIPI(MIPI_RX_DATA, BAND_E, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_RX_DATA_MAX_NUM, NULL)
+
+/* 17 */NVRAM_ITEM_MIPI(MIPI_TX_EVENT, BAND_A, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TX_EVENT_MAX_NUM, NULL)
+/* 18 */NVRAM_ITEM_MIPI(MIPI_TX_EVENT, BAND_B, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TX_EVENT_MAX_NUM, NULL)
+/* 19 */NVRAM_ITEM_MIPI(MIPI_TX_EVENT, BAND_C, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TX_EVENT_MAX_NUM, NULL)
+/* 20 */NVRAM_ITEM_MIPI(MIPI_TX_EVENT, BAND_D, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TX_EVENT_MAX_NUM, NULL)
+/* 21 */NVRAM_ITEM_MIPI(MIPI_TX_EVENT, BAND_E, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TX_EVENT_MAX_NUM, NULL)
+
+/* 22 */NVRAM_ITEM_MIPI(MIPI_TX_DATA, BAND_A, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TX_DATA_MAX_NUM, NULL)
+/* 23 */NVRAM_ITEM_MIPI(MIPI_TX_DATA, BAND_B, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TX_DATA_MAX_NUM, NULL)
+/* 24 */NVRAM_ITEM_MIPI(MIPI_TX_DATA, BAND_C, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TX_DATA_MAX_NUM, NULL)
+/* 25 */NVRAM_ITEM_MIPI(MIPI_TX_DATA, BAND_D, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TX_DATA_MAX_NUM, NULL)
+/* 26 */NVRAM_ITEM_MIPI(MIPI_TX_DATA, BAND_E, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TX_DATA_MAX_NUM, NULL)
+
+/* 27 */NVRAM_ITEM_MIPI(MIPI_TPC_EVENT, BAND_A, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TPC_EVENT_MAX_NUM, NULL)
+/* 28 */NVRAM_ITEM_MIPI(MIPI_TPC_EVENT, BAND_B, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TPC_EVENT_MAX_NUM, NULL)
+/* 29 */NVRAM_ITEM_MIPI(MIPI_TPC_EVENT, BAND_C, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TPC_EVENT_MAX_NUM, NULL)
+/* 30 */NVRAM_ITEM_MIPI(MIPI_TPC_EVENT, BAND_D, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TPC_EVENT_MAX_NUM, NULL)
+/* 31 */NVRAM_ITEM_MIPI(MIPI_TPC_EVENT, BAND_E, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TPC_EVENT_MAX_NUM, NULL)
+
+/* 32 */NVRAM_ITEM_MIPI(MIPI_TPC_DATA, BAND_A, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_TPC_DATA_MAX_NUM, NULL)
+/* 33 */NVRAM_ITEM_MIPI(MIPI_TPC_DATA, BAND_B, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_TPC_DATA_MAX_NUM, NULL)
+/* 34 */NVRAM_ITEM_MIPI(MIPI_TPC_DATA, BAND_C, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_TPC_DATA_MAX_NUM, NULL)
+/* 35 */NVRAM_ITEM_MIPI(MIPI_TPC_DATA, BAND_D, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_TPC_DATA_MAX_NUM, NULL)
+/* 36 */NVRAM_ITEM_MIPI(MIPI_TPC_DATA, BAND_E, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_TPC_DATA_MAX_NUM, NULL)
+
+/* 37 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_1XRTT, BAND_A, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 38 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_1XRTT, BAND_B, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 39 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_1XRTT, BAND_C, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 40 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_1XRTT, BAND_D, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 41 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_1XRTT, BAND_E, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+
+/* 42 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_EVDO, BAND_A, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 43 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_EVDO, BAND_B, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 44 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_EVDO, BAND_C, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 45 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_EVDO, BAND_D, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 46 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DATA_EVDO, BAND_E, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+
+/* MIPI Configuration -- ETM */
+/* 47 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_EVENT, BAND_A, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TX_EVENT_MAX_NUM, NULL)
+/* 48 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_EVENT, BAND_B, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TX_EVENT_MAX_NUM, NULL)
+/* 49 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_EVENT, BAND_C, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TX_EVENT_MAX_NUM, NULL)
+/* 50 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_EVENT, BAND_D, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TX_EVENT_MAX_NUM, NULL)
+/* 51 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_EVENT, BAND_E, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TX_EVENT_MAX_NUM, NULL)
+
+/* 52 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_DATA, BAND_A, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_ETM_TX_DATA_MAX_NUM, NULL)
+/* 53 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_DATA, BAND_B, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_ETM_TX_DATA_MAX_NUM, NULL)
+/* 54 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_DATA, BAND_C, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_ETM_TX_DATA_MAX_NUM, NULL)
+/* 55 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_DATA, BAND_D, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_ETM_TX_DATA_MAX_NUM, NULL)
+/* 56 */NVRAM_ITEM_MIPI(MIPI_ETM_TX_DATA, BAND_E, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_ETM_TX_DATA_MAX_NUM, NULL)
+
+/* 57 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_EVENT, BAND_A, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TPC_EVENT_MAX_NUM, NULL)
+/* 58 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_EVENT, BAND_B, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TPC_EVENT_MAX_NUM, NULL)
+/* 59 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_EVENT, BAND_C, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TPC_EVENT_MAX_NUM, NULL)
+/* 60 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_EVENT, BAND_D, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TPC_EVENT_MAX_NUM, NULL)
+/* 61 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_EVENT, BAND_E, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_ETM_TPC_EVENT_MAX_NUM, NULL)
+
+/* 62 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_DATA, BAND_A, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_ETM_TPC_DATA_MAX_NUM, NULL)
+/* 63 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_DATA, BAND_B, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_ETM_TPC_DATA_MAX_NUM, NULL)
+/* 64 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_DATA, BAND_C, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_ETM_TPC_DATA_MAX_NUM, NULL)
+/* 65 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_DATA, BAND_D, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_ETM_TPC_DATA_MAX_NUM, NULL)
+/* 66 */NVRAM_ITEM_MIPI(MIPI_ETM_TPC_DATA, BAND_E, MAX_BAND_NUM, MIPI_DATA_TABLE_T, MIPI_ETM_TPC_DATA_MAX_NUM, NULL)
+
+/* 67 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_1XRTT, BAND_A, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 68 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_1XRTT, BAND_B, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 69 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_1XRTT, BAND_C, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 70 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_1XRTT, BAND_D, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 71 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_1XRTT, BAND_E, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+
+
+/* 72 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_EVDO, BAND_A, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 73 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_EVDO, BAND_B, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 74 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_EVDO, BAND_C, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 75 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_EVDO, BAND_D, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 76 */NVRAM_ITEM_MIPI(MIPI_ETM_PA_SECTION_DATA_EVDO, BAND_E, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_ETM_PA_SECTION_DATA_MAX_NUM, NULL)
+
+/* Calibration Data */
+/* 77 */NVRAM_ITEM_RF_CAL(AFC_DATA, , 1, AFC_DATA_T, 1, NULL)
+
+/* 78 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_A, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 79 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_B, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 80 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_C, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 81 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_D, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 82 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_E, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+
+/* 83 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_A, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 84 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_B, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 85 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_C, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 86 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_D, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 87 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_E, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+
+/* 88 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_A, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 89 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_B, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 90 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_C, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 91 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_D, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 92 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_E, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+
+/* 93 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_A, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 94 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_B, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 95 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_C, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 96 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_D, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 97 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_E, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+
+ /** Tx PA gain frequency and temperature compensation cal data*/
+/* 98 */ NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_A, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 99 */ NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_B, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 100 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_C, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 101 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_D, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 102 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_E, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 103 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_A, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 104 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_B, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 105 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_C, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 106 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_D, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 107 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_E, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+
+/* 108 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_A, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 109 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_B, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 110 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_C, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 111 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_D, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 112 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_E, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 113 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_A, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 114 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_B, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 115 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_C, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 116 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_D, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 117 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_E, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+
+
+/* 118 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 119 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 120 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 121 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 122 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 123 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 124 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 125 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 126 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 127 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+
+/* 128 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 129 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 130 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 131 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 132 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 133 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 134 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 135 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 136 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 137 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+
+ /** Rx pathloss compensation cal data in high power mode*/
+/* 148 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 149 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 150 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 151 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 152 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 153 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 154 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 155 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 156 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 157 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+
+/* 168 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 169 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 170 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 171 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 172 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 173 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 174 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 175 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 176 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 177 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+
+/* 188 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 189 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 190 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 191 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 192 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 193 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 194 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 195 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 196 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 197 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+
+/* 198 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_A, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 199 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_B, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 200 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_C, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 201 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_D, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 202 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_E, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+
+/* 213 */NVRAM_ITEM_RF_POC(POC_FINAL, BAND_A, MAX_BAND_NUM, POC_FINAL_T, 1, NULL)
+/* 214 */NVRAM_ITEM_RF_POC(POC_FINAL, BAND_B, MAX_BAND_NUM, POC_FINAL_T, 1, NULL)
+/* 215 */NVRAM_ITEM_RF_POC(POC_FINAL, BAND_C, MAX_BAND_NUM, POC_FINAL_T, 1, NULL)
+/* 216 */NVRAM_ITEM_RF_POC(POC_FINAL, BAND_D, MAX_BAND_NUM, POC_FINAL_T, 1, NULL)
+/* 217 */NVRAM_ITEM_RF_POC(POC_FINAL, BAND_E, MAX_BAND_NUM, POC_FINAL_T, 1, NULL)
+
+///TODO: TAS
+/***
+C2K_CUSTOM_TAS_FEATURE_BY_RAT_T CL1D_RF_ TAS_FEATURE_BY_RAT_T
+C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T CL1D_RF_ TAS_FE_ROUTE_DATABASE_T
+C2K_CUSTOM_TAS_FE_CAT_A_T CL1D_RF_ TAS_FE_CAT_A_T
+C2K_CUSTOM_TAS_FE_CAT_B_T CL1D_RF_ TAS_FE_CAT_B_T
+C2K_CUSTOM_TAS_FE_CAT_C_T CL1D_RF_ TAS_FE_CAT_C_T
+C2K_TUNER_FE_ROUTE_TABLE CL1D_RF_ TUNER_FE_ROUTE_TABLE
+C2K_CUSTOM_TUNER_BAND_T CL1D_RF_ TUNER_BAND_T
+C2K_CUSTOM_TAS_CFG_T
+
+MIPI_EVENT_TABLE_T
+MIPI_DATA_SUBBAND_TABLE_T
+***/
+/*** TAS BPI ***//* VAR */
+/* 218 */NVRAM_ITEM_RF_TAS_VAR(CUST_TAS_FEATURE, , 1, TAS_FEATURE_BY_RAT_T, 1, NULL)
+#ifdef __MD93__
+/* 219 */NVRAM_ITEM_RF_TAS_VAR(CUST_TAS_FE_ROUTE_DATABASE, , 1, TAS_FE_ROUTE_DATABASE_T, 1, NULL)
+/* 220 */NVRAM_ITEM_RF_TAS_VAR(CUST_TAS_FE_CAT_A, , 1, TAS_FE_CAT_A_T, 1, NULL)
+/* 221 */NVRAM_ITEM_RF_TAS_VAR(CUST_TAS_FE_CAT_B, , 1, TAS_FE_CAT_B_T, 1, NULL)
+/* 222 */NVRAM_ITEM_RF_TAS_VAR(CUST_TAS_FE_CAT_C, , 1, TAS_FE_CAT_C_T, 1, NULL)
+/* 223 */NVRAM_ITEM_RF_TAS_VAR(CUST_TUNER_FE_ROUTE_TABLE, , 1, TUNER_FE_ROUTE_TABLE, 1, NULL)
+/* 224 */NVRAM_ITEM_RF_TAS_VAR(CUST_TUNER, BAND_A, MAX_BAND_NUM, TUNER_BAND_T, 1, NULL)
+/* 225 */NVRAM_ITEM_RF_TAS_VAR(CUST_TUNER, BAND_B, MAX_BAND_NUM, TUNER_BAND_T, 1, NULL)
+/* 226 */NVRAM_ITEM_RF_TAS_VAR(CUST_TUNER, BAND_C, MAX_BAND_NUM, TUNER_BAND_T, 1, NULL)
+/* 227 */NVRAM_ITEM_RF_TAS_VAR(CUST_TUNER, BAND_D, MAX_BAND_NUM, TUNER_BAND_T, 1, NULL)
+/* 228 */NVRAM_ITEM_RF_TAS_VAR(CUST_TUNER, BAND_E, MAX_BAND_NUM, TUNER_BAND_T, 1, NULL)
+
+/*** TAS MIPI ***//* ARRAY */
+/* 229 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_EVENT, BAND_A, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 230 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_EVENT, BAND_B, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 231 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_EVENT, BAND_C, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 232 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_EVENT, BAND_D, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 233 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_EVENT, BAND_E, MAX_BAND_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 234 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_DATA, BAND_A, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 235 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_DATA, BAND_B, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 236 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_DATA, BAND_C, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 237 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_DATA, BAND_D, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 238 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TUNER_ROUTE_DATA, BAND_E, MAX_BAND_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+
+/* 239 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_A, Route0, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 240 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_A, Route1, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 241 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_A, Route2, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 242 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_A, Route3, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 243 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_A, Route0, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 244 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_A, Route1, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 245 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_A, Route2, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 246 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_A, Route3, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+
+/* 247 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_B, Route0, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 248 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_B, Route1, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 249 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_B, Route2, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 250 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_B, Route3, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 251 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_B, Route0, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 252 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_B, Route1, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 253 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_B, Route2, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 254 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_B, Route3, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+
+/* 255 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_C, Route0, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 256 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_C, Route1, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 257 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_C, Route2, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 258 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_EVENT_CAT_C, Route3, MAX_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_TAS_EVENT_MAX_NUM, NULL)
+/* 259 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_C, Route0, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 260 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_C, Route1, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 261 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_C, Route2, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+/* 262 */NVRAM_ITEM_RF_TAS_ARRAY(CUST_TAS_DATA_CAT_C, Route3, MAX_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_TAS_DATA_MAX_NUM, NULL)
+#endif
+/**ELNA**/
+/*ELNA config&bpi data*/
+/* 264 */NVRAM_ITEM_ELNA_VAR(CUST_ELNA_CFG, , 1, CUST_ELNA_CFG_T, 1, NULL)
+/**TX POWER**/
+/* TX power back off */
+/* 285 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_A, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 286 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_B, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 287 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_C, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 288 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_D, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 289 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_E, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* TX power offset */
+#if defined(__TX_POWER_OFFSET_SUPPORT__)
+/* 290 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_A, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 291 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_B, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 292 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_C, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 293 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_D, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 294 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_E, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+#endif
+/*TAS TST*/
+/* 295 */NVRAM_ITEM_RF_TAS_TST(TAS_TST_CONFIG, , 1, TAS_TST_CONFIG_T, 1, NULL)
+#if IS_C2K_DAT_RFD_CTRL_EN
+/* DAT */
+/* 296 */NVRAM_ITEM_RF_TAS_VAR(DAT_FE_ROUTE_DATABASE, , 1, DAT_FE_ROUTE_DATABASE_T, 1, NULL)
+/* 297 */NVRAM_ITEM_RF_TAS_VAR(DAT_FE_CAT_A_DATABASE, , 1, DAT_FE_CAT_A_T, 1, NULL)
+/* 298 */NVRAM_ITEM_RF_TAS_VAR(DAT_FE_CAT_B_DATABASE, , 1, DAT_FE_CAT_B_T, 1, NULL)
+
+/* 299 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route0, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 300 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route1, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 301 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route2, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 302 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route3, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 303 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route4, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 304 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route5, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 305 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route6, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 306 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route7, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 307 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route8, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 308 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_A, DAT_CAT_A_Route9, MAX_DAT_CAT_A_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+
+/* 309 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route0, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 310 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route1, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 311 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route2, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 312 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route3, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 313 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route4, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 314 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route5, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 315 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route6, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 316 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route7, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 317 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route8, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 318 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_A, DAT_CAT_A_Route9, MAX_DAT_CAT_A_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+
+/* 319 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route0, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 320 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route1, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 321 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route2, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 322 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route3, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 323 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route4, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 324 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route5, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 325 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route6, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 326 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route7, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 327 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route8, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 328 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route9, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 329 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route10, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 330 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route11, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 331 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route12, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 332 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route13, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 333 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route14, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 334 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route15, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 335 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route16, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 336 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route17, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 337 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route18, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 338 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route19, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 339 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route20, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 340 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route21, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 341 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route22, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 342 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route23, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 343 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route24, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 344 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route25, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 345 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route26, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 346 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route27, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 347 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route28, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 348 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route29, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 349 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route30, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 350 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route31, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 351 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route32, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 352 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route33, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 353 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route34, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 354 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route35, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 355 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route36, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 356 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route37, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 357 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route38, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+/* 358 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_EVENT_CAT_B, DAT_CAT_B_Route39, MAX_DAT_CAT_B_Route_NUM, MIPI_EVENT_TABLE_T, MIPI_DAT_EVENT_MAX_NUM, NULL)
+
+/* 369 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route0, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 370 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route1, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 371 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route2, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 372 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route3, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 373 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route4, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 374 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route5, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 375 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route6, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 376 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route7, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 377 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route8, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 378 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route9, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 379 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route10, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 380 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route11, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 381 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route12, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 382 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route13, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 383 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route14, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 384 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route15, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 385 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route16, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 386 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route17, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 387 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route18, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 388 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route19, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 389 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route20, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 390 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route21, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 391 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route22, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 392 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route23, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 393 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route24, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 394 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route25, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 395 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route26, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 396 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route27, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 397 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route28, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 398 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route29, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 399 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route30, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 400 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route31, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 401 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route32, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 402 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route33, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 403 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route34, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 404 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route35, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 405 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route36, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 406 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route37, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 407 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route38, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+/* 408 */NVRAM_ITEM_RF_TAS_ARRAY(DAT_MIPI_DATA_CAT_B, DAT_CAT_B_Route39, MAX_DAT_CAT_B_Route_NUM, MIPI_DATA_SUBBAND_TABLE_T, MIPI_DAT_DATA_MAX_NUM, NULL)
+#endif
+/* SAR TX power offset */
+#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
+/* 409 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_A, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 410 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_B, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 411 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_C, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 412 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_D, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 413 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_E, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+#endif
+/*DPD*/
+/* 414 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_A, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 415 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_B, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 416 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_C, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 417 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_D, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 418 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_E, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 419 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_A, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 420 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_B, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 421 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_C, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 422 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_D, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 423 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_E, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 424 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_A, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 425 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_B, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 426 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_C, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 427 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_D, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 428 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_E, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 429 */NVRAM_ITEM_RF_CUST(PCFE_DPD_OTFC_CUSTOM_PARA, , 1, PCFE_DPD_OTFC_CUSTOM_PARA_T, 1, NULL)
+
+/* 430 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_1XRTT, BAND_A, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 431 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_1XRTT, BAND_B, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 432 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_1XRTT, BAND_C, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 433 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_1XRTT, BAND_D, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 434 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_1XRTT, BAND_E, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+
+/* 435 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_EVDO, BAND_A, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 436 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_EVDO, BAND_B, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 437 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_EVDO, BAND_C, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 438 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_EVDO, BAND_D, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+/* 439 */NVRAM_ITEM_MIPI(MIPI_PA_SECTION_DPD_DATA_EVDO, BAND_E, MAX_BAND_NUM, TPC_SECTION_TABLE_T, MIPI_PA_SECTION_DATA_MAX_NUM, NULL)
+#ifdef __MD95__
+/* 440 */NVRAM_ITEM_RF_TAS_VAR(CUST_ANT_FE_ROUTE_DATABASE, ,1, ANT_FE_ROUTE_DATABASE_T, 1, NULL)
+/* 441 */NVRAM_ITEM_RF_TAS_VAR(CUST_UTAS_ALGORITHM_PARAMETER, ,1, UTAS_ALGORITHM_PARAMETER_T, 1, NULL)
+#endif
+#if IS_C2K_UDAT_SUPPORT
+/* 442 */NVRAM_ITEM_RF_TAS_VAR(CUST_DAT_ANT_TUNER_ROUTE_DATABASE, ,1, DAT_ANT_TUNER_ROUTE_DATABASE_T, 1, NULL)
+#endif
+#endif
+
+#if (defined(__MD97__) || defined(__MD97P__))
+
+#define MIPI_TAS_EVENT_MAX_NUM (10)
+#define MIPI_TAS_DATA_MAX_NUM (20)
+
+#define MIPI_ELNA_EVENT_MAX_NUM (10)
+#define MIPI_ELNA_DATA_MAX_NUM (20)
+
+#define MIPI_DAT_EVENT_MAX_NUM MIPI_TAS_EVENT_MAX_NUM
+#define MIPI_DAT_DATA_MAX_NUM MIPI_TAS_DATA_MAX_NUM
+/* NVRAM ID definition of items in C2K RF custom file */
+/* Common Parameters */
+/* 0 */NVRAM_ITEM_RF_CUST(CUST_PARAM, , 1, CUST_PARAM_T, 1, NULL)
+
+/* Calibration Data */
+/* 77 */NVRAM_ITEM_RF_CAL(AFC_DATA, , 1, AFC_DATA_T, 1, NULL)
+
+/* 78 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_A, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 79 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_B, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 80 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_C, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 81 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_D, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 82 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_1XRTT, BAND_E, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+
+/* 83 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_A, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 84 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_B, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 85 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_C, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 86 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_D, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+/* 87 */NVRAM_ITEM_RF_CAL(TX_APT_PA_CONTEXT_EVDO, BAND_E, MAX_BAND_NUM, TX_APT_PA_CONTEXT_T, 1, NULL)
+
+/* 88 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_A, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 89 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_B, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 90 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_C, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 91 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_D, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 92 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_1XRTT, BAND_E, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+
+/* 93 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_A, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 94 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_B, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 95 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_C, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 96 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_D, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+/* 97 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_CONTEXT_EVDO, BAND_E, MAX_BAND_NUM, TX_DPD_PA_CONTEXT_T, 1, NULL)
+
+ /** Tx PA gain frequency and temperature compensation cal data*/
+/* 98 */ NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_A, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 99 */ NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_B, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 100 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_C, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 101 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_D, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 102 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_1XRTT, BAND_E, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 103 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_A, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 104 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_B, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 105 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_C, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 106 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_D, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+/* 107 */NVRAM_ITEM_RF_CAL(TX_APT_PA_GAIN_COMP_EVDO, BAND_E, MAX_BAND_NUM, TX_APT_PA_GAIN_COMP_T, 1, NULL)
+
+/* 108 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_A, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 109 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_B, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 110 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_C, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 111 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_D, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 112 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_1XRTT, BAND_E, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 113 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_A, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 114 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_B, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 115 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_C, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 116 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_D, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+/* 117 */NVRAM_ITEM_RF_CAL(TX_DPD_PA_GAIN_COMP_EVDO, BAND_E, MAX_BAND_NUM, TX_DPD_PA_GAIN_COMP_T, 1, NULL)
+
+
+/* 118 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 119 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 120 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 121 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 122 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_1XRTT, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 123 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 124 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 125 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 126 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+/* 127 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_EVDO, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_T, 1, NULL)
+
+/* 128 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 129 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 130 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 131 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 132 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_1XRTT, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 133 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_A, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 134 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_B, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 135 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_C, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 136 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_D, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+/* 137 */NVRAM_ITEM_RF_CAL(DET_COUPLE_LOSS_COMP_EVDO, BAND_E, MAX_BAND_NUM, DET_COUPLE_LOSS_COMP_T, 1, NULL)
+
+ /** Rx pathloss compensation cal data in high power mode*/
+/* 148 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 149 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 150 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 151 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 152 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_HPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 153 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 154 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 155 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 156 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 157 */NVRAM_ITEM_RF_CAL(MAIN_RX_PATH_LOSS_LPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+
+/* 168 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 169 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 170 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 171 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 172 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_HPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 173 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 174 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 175 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 176 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 177 */NVRAM_ITEM_RF_CAL(DIV_RX_PATH_LOSS_LPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+
+/* 188 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 189 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 190 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 191 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 192 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_HPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 193 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_A, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 194 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_B, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 195 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_C, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 196 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_D, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+/* 197 */NVRAM_ITEM_RF_CAL(SHDR_RX_PATH_LOSS_LPM, BAND_E, MAX_BAND_NUM, RX_PATH_LOSS_COMP_T, 1, NULL)
+
+/* 198 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_A, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 199 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_B, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 200 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_C, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 201 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_D, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+/* 202 */NVRAM_ITEM_RF_CAL(AGPS_GROUP_DELAY, BAND_E, MAX_BAND_NUM, AGPS_GROUP_DELAY_T, 1, NULL)
+
+/*TAS*/
+/* 218 */NVRAM_ITEM_RF_TAS_VAR(CUST_TAS_FEATURE, , 1, TAS_FEATURE_T, 1, NULL)
+/* 441 */NVRAM_ITEM_RF_TAS_VAR(CUST_UTAS_ALGORITHM_PARAMETER, , 1, UTAS_ALGORITHM_PARAMETER_T, 1, NULL)
+
+/**TX POWER**/
+/* TX power back off */
+/* 285 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_A, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 286 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_B, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 287 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_C, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 288 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_D, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* 289 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_BACK_OFF,BAND_E, MAX_BAND_NUM, TX_POWER_BACK_OFF_T,1,NULL)
+/* TX power offset */
+#if defined(__TX_POWER_OFFSET_SUPPORT__)
+/* 290 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_A, MAX_BAND_NUM, SWTP_TX_POWER_OFFSET_T,1,NULL)
+/* 291 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_B, MAX_BAND_NUM, SWTP_TX_POWER_OFFSET_T,1,NULL)
+/* 292 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_C, MAX_BAND_NUM, SWTP_TX_POWER_OFFSET_T,1,NULL)
+/* 293 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_D, MAX_BAND_NUM, SWTP_TX_POWER_OFFSET_T,1,NULL)
+/* 294 */NVRAM_ITEM_TX_POWER_VAR(TX_POWER_OFFSET,BAND_E, MAX_BAND_NUM, SWTP_TX_POWER_OFFSET_T,1,NULL)
+#endif
+
+/* SAR TX power offset */
+#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
+/* 409 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_A, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 410 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_B, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 411 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_C, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 412 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_D, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+/* 413 */NVRAM_ITEM_TX_POWER_VAR(SAR_TX_POWER_OFFSET,BAND_E, MAX_BAND_NUM, SAR_TX_POWER_OFFSET_T,1,NULL)
+#endif
+/*DPD*/
+/* 414 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_A, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 415 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_B, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 416 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_C, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 417 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_D, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 418 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_1XRTT, BAND_E, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 419 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_A, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 420 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_B, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 421 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_C, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 422 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_D, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 423 */NVRAM_ITEM_RF_POC(TX_DPD_AM_PM_COMP_EVDO, BAND_E, MAX_BAND_NUM, TX_DPD_AM_PM_LUT_DATA_T, 1, NULL)
+/* 424 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_A, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 425 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_B, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 426 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_C, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 427 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_D, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 428 */NVRAM_ITEM_RF_CUST(DPD_COMMON_CTRL, BAND_E, MAX_BAND_NUM, DPD_COMMON_CTRL_T, 1, NULL)
+/* 429 */NVRAM_ITEM_RF_CUST(PCFE_DPD_OTFC_CUSTOM_PARA, , 1, PCFE_DPD_OTFC_CUSTOM_PARA_T, 1, NULL)
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+/* 444 */NVRAM_ITEM_RF_TAS_VAR(CUST_RF_HOPPING, , 1, HOPPING_DATA_BASE_T, 1, NULL)
+#endif
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cl1_rtb_api.h b/mcu/interface/l1/cl1/common/cl1_rtb_api.h
new file mode 100644
index 0000000..e200cf8
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1_rtb_api.h
@@ -0,0 +1,50 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2017
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef CL1_RTB_API_H
+#define CL1_RTB_API_H
+/*****************************************************************************
+
+ FUNCTION NAME: Cl1_AssertFunction
+
+ DESCRIPTION: RTBA Provide this API for RTB to call to pass the assert information to CL1
+
+ PARAMETERS: Assert Cause - Indicate assert cause of RTB
+ SimIndex - Current SIM Index
+ Para1/Para2 - The assert related information
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Cl1_AssertFunction(RTB_ASSERT_CAUSE AssertCause, RTB_SIM_INDEX SimIndex, kal_uint32 Para1, kal_uint32 Para2);
+
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/cl1_timertype.h b/mcu/interface/l1/cl1/common/cl1_timertype.h
new file mode 100644
index 0000000..d063517
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1_timertype.h
@@ -0,0 +1,60 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+CL1_TIMER_TYPE(CTimerNone),
+CL1_TIMER_TYPE(CTimerXL1IcsPilot),
+CL1_TIMER_TYPE(CTimerXL1IcsSync),
+CL1_TIMER_TYPE(CTimerXL1NsltPchOvhd),
+CL1_TIMER_TYPE(CTimerXL1NsltInterMeas),
+CL1_TIMER_TYPE(CTimerXL1AfltMeas),
+CL1_TIMER_TYPE(CTimerXL1SltCci),
+CL1_TIMER_TYPE(CTimerXL1SltQpch_1),
+CL1_TIMER_TYPE(CTimerXL1SltQpch_2),
+CL1_TIMER_TYPE(CTimerXL1SltPch),
+CL1_TIMER_TYPE(CTimerXL1SltPchLostDet),
+CL1_TIMER_TYPE(CTimerXL1SltnterMeas),
+CL1_TIMER_TYPE(CTimerXL1ConnectPsRx),
+CL1_TIMER_TYPE(CTimerXL1ConnectInterMeas),
+CL1_TIMER_TYPE(CTimerXL1ConnectAfltMeas),
+CL1_TIMER_TYPE(CTimerEvL1IcsPilot),
+CL1_TIMER_TYPE(CTimerEvL1IcsSync),
+CL1_TIMER_TYPE(CTimerEvL1NsltCC),
+CL1_TIMER_TYPE(CTimerEvL1SltPch),
+CL1_TIMER_TYPE(CTimerEvL1InterMeas),
+CL1_TIMER_TYPE(CTimerEvL1ConnectRx),
+CL1_TIMER_TYPE(CTimerEvL1ConnectInterMeas),
+CL1_TIMER_TYPE(CTimerEvStdbyMeas),
+CL1_TIMER_TYPE(CTimerEvStdbySync),
+CL1_TIMER_TYPE(CTimerEvStdbyCgi),
+CL1_TIMER_TYPE(CTimerEnd),
diff --git a/mcu/interface/l1/cl1/common/cl1common.h b/mcu/interface/l1/cl1/common/cl1common.h
new file mode 100644
index 0000000..e913054
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1common.h
@@ -0,0 +1,97 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1COMMON_H_
+#define _CL1COMMON_H_
+
+//#define C2K_COSIM_TST_ON_PC 1
+#define MDM_TM_STR_BUF0 0
+
+#include "sysdefs.h"
+#ifdef MTK_C2K_COSIM
+#include "mdm_trc.h"
+#endif
+
+
+//#if !defined (C2K_COSIM_TST_ON_PC)
+typedef unsigned int intbool;
+//#endif
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#ifndef OK
+#define OK 1
+#endif
+
+#ifndef ERROR
+#define ERROR1 0
+#endif
+
+#ifndef FAIL
+#define FAIL 0
+#endif
+
+#ifndef PASS
+#define PASS 1
+#endif
+
+#ifndef OKAY
+#define OKAY 1
+#endif
+
+#if defined (C2K_COSIM_TST_ON_PC)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#else
+#endif
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/cl1d_interface.h b/mcu/interface/l1/cl1/common/cl1d_interface.h
new file mode 100644
index 0000000..0d84e42
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1d_interface.h
@@ -0,0 +1,60 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_interface.h
+ *
+ * Project:
+ * --------
+ * MT6293
+ *
+ * Description:
+ * ------------
+ * CL1D Interface
+ *
+ * Author:
+ * -------
+ *
+ *
+ *------------------------------------------------------------------------------
+ *******************************************************************************/
+
+/* For MMRF */
+#define is_c2k_exist KAL_TRUE
+#define CL1D_IS_C2K_EXIST() ((kal_bool)is_c2k_exist)
+
diff --git a/mcu/interface/l1/cl1/common/cl1fhhscevtid.h b/mcu/interface/l1/cl1/common/cl1fhhscevtid.h
new file mode 100644
index 0000000..c762304
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1fhhscevtid.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1FHHSCEVTID_H_
+#define _CL1FHHSCEVTID_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1fhhscevtid.h
+*
+* DESCRIPTION :
+*
+*
+************************************************************************************/
+
+#define FH_HSC_EVT_ID_HEADER_1X (0x0080)
+#define FH_HSC_EVT_ID_HEADER_DO (0x0100)
+#define FH_HSC_EVT_ID_HEADER_MASK (0x0180)
+
+#define FH_HSC_EVT_ID_HEADER_COMMON (FH_HSC_EVT_ID_HEADER_1X | FH_HSC_EVT_ID_HEADER_DO)
+
+#if ((FH_HSC_EVT_ID_HEADER_MASK & FR_EVT_ID_HEADER_DEST_MASK) != 0)
+ #error "EVT ID header bits assign conflict!!!"
+#endif
+
+
+/* This HdrMask is for Sleep RI usage*/
+#define FH_HSC_EVT_ID_DEFINE(Id, Val, HdrMask) FR_EVT_ID_DEFINE(Id, (HdrMask | Val), FH_HSC)
+
+
+/*----------------------------------------------------------------------------
+ Global Defines
+----------------------------------------------------------------------------*/
+
+/* Sample */
+FH_HSC_EVT_ID_DEFINE(EVT_ID_XX_TO_FH_HSC_SAMPLE, 0x00, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_MPA_REQ, 0x01, FH_HSC_EVT_ID_HEADER_COMMON)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_MPA_RELEASE, 0x02, FH_HSC_EVT_ID_HEADER_COMMON)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_DEQUEUE_EVENT, 0x03, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_SLEEPOVER_INT_COMP, 0x04, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_MMO_GAP_REQ, 0x05, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_DO_SLEEP_CMD, 0x06, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_RMC_STOP_ACK, 0x07, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_DO_SLOTTED_SET, 0x08, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_DO_WAKE_CMD, 0x09, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_1X_SLEEP_CMD, 0x0A, FH_HSC_EVT_ID_HEADER_1X)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_1X_WAKE_CMD, 0x0B, FH_HSC_EVT_ID_HEADER_1X)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_OOSA_SLEEP, 0x0C, FH_HSC_EVT_ID_HEADER_COMMON)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_1X_PRIORITY_BOOST, 0x0D, FH_HSC_EVT_ID_HEADER_1X)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_EVSTANDBY_SLEEP, 0x0E, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_EVSTANDBY_WAKE, 0x0F, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_1X_SLOTTED_SET, 0x10, FH_HSC_EVT_ID_HEADER_1X)
+
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_DO_PRIORITY_BOOST, 0x20, FH_HSC_EVT_ID_HEADER_DO)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_DENY_PATTERN_IND, 0x21, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_PREEMPT_TRIG_IND, 0x22, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_RBS_SCENARIO_CONTROL_CONFIG_IND, 0x23, 0)
+
+FH_HSC_EVT_ID_DEFINE(EVT_ID_RTBA_TO_HSC_DENY_IND, 0x30, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_RTBA_UT_CHAN_STATUS_CHECK, 0x31, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_RTBA_UT_TO_FH_HSC_IND_CHECK, 0x32, 0)
+FH_HSC_EVT_ID_DEFINE(EVT_ID_RTBSTUB_UT_TO_RTBA_IND_CHECK, 0x33, 0)
+
+FH_HSC_EVT_ID_DEFINE(EVT_ID_SM_UT_MON_DEEP_TEST, 0x34, 0)
+
+FH_HSC_EVT_ID_DEFINE(EVT_ID_HSC_MPA_OP_MODE_SET, 0x35, 0)
+
+
+
+
+/* MUST be less than 127 (0x7F) !!! */
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+
+
+
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/cl1fhrtbaconstant.h b/mcu/interface/l1/cl1/common/cl1fhrtbaconstant.h
new file mode 100644
index 0000000..f9d1f93
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1fhrtbaconstant.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1FHRTBACONSTANT_H_
+#define _CL1FHRTBACONSTANT_H_
+
+#ifdef MTK_DEV_93M_PREIT
+
+
+/*****************************************************************************
+
+ FILE NAME: cl1fhrtbaconstant.h
+
+ DESCRIPTION:
+
+ This file contains the constant definition of RTBA module in 93m
+
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Definitions
+*----------------------------------------------------------------------------*/
+#define FEC_DDL_RX_MARGIN (850)
+#define FEC_DDL_TRX_MARGIN (950)
+#define FEC_DDL_RX_MARGIN_CONN_STANDBY_MEAS (5000)
+
+/** Define for the RTBA Channel related block info. */
+#define RTBA_BASIC_BLOCK_LENGTH (20000) /** The RTBA basic block length in us unit. */
+#define RTBA_XL1_ICS_SYNC_SMALL_BLOCK_LENGTH (80000/3) /** The XL1 sync channel small block reserve length, in us unit. */
+#define RTBA_XL1_CONN_PS_RX_BLOCK_LENGTH (RTBA_BASIC_BLOCK_LENGTH * 6) /** The XL1 connect ps block length. */
+#define RTBA_XL1_SLT_PCH_LOST_DET_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The XL1 PCH Lost block length. */
+#define RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The XL1 non-slotted PCH overhead block length. */
+#define RTBA_XL1_NSLT_PCH_LONG_BLOCK_LENGTH (RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH * 16)
+
+#ifdef MTK_CBP_SYNC_OPTIMIZE
+#define XL1_MINI_ACQ_FAST_AGC_ICS_LENGTH (3500)
+#endif
+
+#define XL1_MINI_ACQ_FAST_AGC_LENGTH (5750) /** The XL1 mini acquisition length,which needs to be added to RTB block
+ when previously preempt, in us unit. */
+#define RTBA_EVL1_ICS_SYNC_SMALL_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 Sync pch channel basic block length in us unit. */
+#define RTBA_EVL1_NSLT_CC_OVHD_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 non-slotted pch channel basic block length in us unit. */
+#define RTBA_EVL1_CONN_RX_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 Connect Rx channel basic block length in us unit. */
+
+#define RTBA_XL1_BRP_TAIL_MARGIN_20MS (3*1250) /** 1xRTT's BRP Tail Margin for 20ms frame size (3PCG).*/
+#define RTBA_XL1_BRP_TAIL_MARGIN_26MS (3*1667) /** 1xRTT's BRP Tail Margin for 26ms frame size (3PCG).*/
+#define RTBA_XL1_BRP_TAIL_MARGIN_20MS_TRAFFIC (6*1250) /** 1xRTT's BRP Tail Margin for 20ms FCH frame size (3PCG).*/
+
+#define RTBA_SCHE_FAKE_MARGIN_20MS (1250) /** The fake margin for RTBA schedule for RC control.*/
+#define RTBA_SCHE_FAKE_MARGIN_26MS (1667) /** The fake margin for RTBA schedule for RC control.*/
+
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS (1250) /** The check dsp idle margin for RC control.*/
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS (1667) /** The check dsp idle margin for RC control.*/
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS_LONG (6250) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 5*1250.*/
+
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_LONG (10000) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 6*1667us.*/
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED (6666) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 4*1667us.*/
+
+
+#define RTBA_SCHE_HSC_PREEMPT_ADVANCE_OFFSET (RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED) /** Indicate the HSC preempt gap for HSC fully/div preemption.*/
+#define RTBA_INVALID_GAP_START_TIME (0xFFFFFFFF)
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cl1fhrtbadefs.h b/mcu/interface/l1/cl1/common/cl1fhrtbadefs.h
new file mode 100644
index 0000000..9cea605
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1fhrtbadefs.h
@@ -0,0 +1,724 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1FHRTBADEFS_H_
+#define _CL1FHRTBADEFS_H_
+
+#ifdef MTK_DEV_93M_PREIT
+
+
+#include "kal_public_defs.h"
+#include "systyp.h"
+
+/*****************************************************************************
+
+ FILE NAME: cl1fhrtbadefs.h
+
+ DESCRIPTION:
+
+ This file contains the data type definition of RTBA module in 93m
+
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Definitions
+*----------------------------------------------------------------------------*/
+#if 0
+/* under construction !*/
+#else
+#define C2K_SRLTE_RTBA_ON C2K_SRLTE_ON
+#endif
+
+#ifndef MTK_PLT_ON_PC
+//#define MTK_DEV_93M_RTBA_BYPASS_ENABLE
+#endif
+
+#define MTK_DEV_93M_RTBA_RBS_ENABLE
+#define MTK_DEV_93M_RTBA_HPS_TRIG_ENABLE
+#define MTK_DEV_93M_RTBA_RBS_SCENARIO_CONTROL_ENABLE
+
+#define PNULL (void*)(0)
+
+#define DUMMY_FRC_INPUT (0xFFFFFFFF)
+#define DUMMY_FRAME_NUM_INPUT (0xFFFFFFFF)
+#define FRAME_NUM_WRAP (0xFFFFFFFF)
+#define MAX_FRAME_NUM (0x100000000L)
+#define INVALID_GAP_END_FRC (DUMMY_FRC_INPUT)
+#define INVALID_SLT_PCH_CONFIG (0x0)
+
+
+
+#define FRC_ADD(a, b) ((a + b)& C2K_FRC_WRAP)
+#define FRC_MINUS(late,early) (((late) + MAX_FRC_CNT - (early))& C2K_FRC_WRAP)
+#define FRAME_ADD(a, b) ((a + b)& FRAME_NUM_WRAP)
+#define FRAME_MINUS(late,early) (((late) + MAX_FRAME_NUM - (early))& FRAME_NUM_WRAP)
+
+
+/** Define for the Starvation timer. */
+#define RTBA_XL1_ICS_SYNC_STARVATION_TIMER (450) /** The XL1 sync channel starvation timer length in ms unit. */
+#define RTBA_XL1_NSLT_PCH_OVHD_STARVATION_TIMER (100) /** The XL1 nslt pch channel starvation timer length in ms unit. */
+#define RTBA_STARVATION_TIMER_FACTOR (10)
+#define RTBA_XL1_SLT_PCH_LOST_DET_STARVATION_TIMER (1000) /** The XL1 slt pch lost detect channel starvation timer length in ms unit. */
+#define RTBA_XL1_CONN_PS_RX_STARVATION_TIMER (3000) /** The XL1 connect ps channel starvation timer length in ms unit. */
+
+#define RTBA_EVL1_ICS_SYNC_STARVATION_TIMER (180) /** The EvL1 sync channel starvation timer length in ms unit. */
+#define RTBA_EVL1_STDBY_LTE_IDLE_SYNC_STARVATION_TIMER (500) /** The EvStandby sync channel starvation timer length in ms unit. */
+#define RTBA_EVL1_CONN_RX_STARVATION_TIMER (2000) /** The EvL1 connect channel starvation timer length in ms unit. */
+
+#define RTBA_CMD_FIFO_NUM (8)
+#define RTBA_TOTAL_BLOCK_NUM (2)
+#define RTBA_SCHE_BLOCK_INDEX (0) /** This index stores the block which is to be scheduled.*/
+#define RTBA_ACTIVE_BLOCK_INDEX (1) /** This index stores the block which is active/running.*/
+
+#define RTBA_SHIFT_NUM1 (1)
+#define RTBA_SHIFT_NUM2 (14)
+#define RTBA_SECCHAN_SHIFT_NUM1 (31)
+
+#define Preempt_offset_Time_Min (1)
+#define Preempt_offset_Time_Max (3)
+#define Resume_offset_Time_Min (2)
+#define Resume_offset_Time_Max (4)
+
+/** set slt_pch_channel execute time, unit:20ms*/
+#define SLT_PCH_EXECUTE_FRAME_NUM (10)
+#define NSLT_PCH_LONG_BLOCK_EXECUTE_FRAME_NUM (17)
+#define NSLT_PCH_SHORT_BLOCK_EXECUTE_FRAME_NUM (1)
+
+
+/** Set the channel attribute flag.*/
+#define RTBA_PRIMARY_CHAN_BN 0x0001
+#define RTBA_SECONDARY_CHAN_BN 0x0002
+
+#define RTBA_RF_ON_MARGIN_INDEX (0)
+#define RTBA_RF_OFF_MARGIN_INDEX (1)
+
+#ifdef MTK_DEV_93M_RTBA_RBS_SCENARIO_CONTROL_ENABLE
+#define RBS_SCEN_EVDO_RTB_PREEMPTION (0x00000001)
+#define RBS_SCEN_EVDO_RTB_RESUME (0x00000002)
+#define RBS_SCEN_1xRTT_RESYNC_RTB_GRANT (0x00000004)
+#define RBS_SCEN_1xRTT_RTB_PREEMPTION (0x00000008)
+#define RBS_SCEN_1xRTT_RTB_RESUME (0x000000010)
+#define RTBA_ABS_VALUE(a) (((a) < 0) ? (-(a)) : (a))
+#endif
+/*----------------------------------------------------------------------------
+Macros Definition
+----------------------------------------------------------------------------*/
+#define RTBA_GET_SIM_INDEX(Mode) (gRtbaSimIndexRecord[Mode])
+/** For RTBA to set/get the byPass interaction with RTB. */
+#define RTBA_BYPASS_SET(Mode, ByPass) (gRtbaByPassMode[Mode] = ByPass)
+#define RTBA_BYPASS_GET(Mode) (gRtbaByPassMode[Mode])
+/** For RTBA to enable/disable the starvation flag. */
+#define RTBA_STARVATION_TRIGGER(Mode, Enable) (gRtbaScheInfo[Mode].PrimaryChanPara.StarvationTrigger = Enable)
+#define RTBA_STARVATION_STATUS(Mode) (gRtbaScheInfo[Mode].PrimaryChanPara.StarvationTrigger)
+
+/** For RTBA to set/get the starvation timer active/inactive status. */
+#define RTBA_STARVATION_TIMER_STATUS_SET(Mode, Active) (gRtbaStarvationFlag[Mode] = Active)
+#define RTBA_STRAVATION_TIMER_STATUS_GET(Mode) (gRtbaStarvationFlag[Mode])
+
+/** For RTBA to set/get the gate mode. */
+#define RTBA_GATE_MODE_SET(Mode, ModeType) (gRtbaGateModeStatus[Mode] = ModeType)
+#define RTBA_GATE_MODE_GET(Mode) (gRtbaGateModeStatus[Mode])
+
+#define RTBA_RC_CONTROL_MARGIN_GET(Channel,MarginType) (gRtbaRcMarginTbl[Channel][MarginType])
+
+#define RF_ON_MARGIN() (RtbaCl1GetRFOnMarginInfo())
+#define RF_OFF_MARGIN() (RtbaCl1GetRFOffMarginInfo())
+
+/*----------------------------------------------------------------------------
+* Enums
+*----------------------------------------------------------------------------*/
+/** The Enum of the RTBA channel based on the schedule type. */
+typedef enum
+{
+ /****************** Schedule Type 0 ********************************************************/
+ RTBA_XL1_ICS_PILOT_CHAN = 0, /** ICS Pilot Acq Channel. */
+ RTBA_XL1_SINGLE_INTER_MEAS_CHAN, /** Slotted Inter-Meas Channel after QPCH. */
+ RTBA_XL1_SLT_CCI_CHAN, /** Slotted CCI Channel. */
+ RTBA_XL1_SLT_QPCH1_CHAN, /** Slotted QPCH1 Channle. */
+ RTBA_XL1_SLT_QPCH2_CHAN, /** Slotted QPCH2 Channle. */
+ RTBA_XL1_ICS_RSSI_SCAN_CHAN, /** ICS RSSI Scan Channel**/
+ RTBA_EVL1_ICS_PILOT_CHAN, /** ICS Pilot Acq Channel. */
+ RTBA_EVL1_STDBY_LTE_IDLE_MEAS_CHAN, /** Standby Meas Channel in LTE Idle Gap. */
+ RTBA_EVL1_STDBY_LTE_CONN_MEAS_CHAN, /** Standby Meas Channel in LTE Connect Gap. */
+ RTBA_EVL1_STDBY_CGI_MEAS_CHAN, /** Standby CGI Meas Channel. */
+
+ /****************** Schedule Type 1 ********************************************************/
+ RTBA_XL1_SLT_PCH_CHAN, /** 1xRTT's Slotted PCH Channle. */
+ RTBA_EVL1_SLT_PCH_CHAN, /** EVDO's Slotted PCH Channle. */
+
+ /****************** Schedule Type 2 ********************************************************/
+ RTBA_XL1_ICS_SYNC_CHAN, /** 1xRTT ICS Sync Acq Channel. */
+ RTBA_XL1_ICS_SYNC_OPTIMIZE_CHAN, /** 1xRTT ICS Sync Acq Channel with optimization schedule manner. */
+ RTBA_EVL1_ICS_SYNC_CHAN, /** EVDO ICS Sync Acq Channel. */
+ RTBA_EVL1_STDBY_LTE_IDLE_SYNC_CHAN, /** Standby Sync Channel in LTE Idle Gap. */
+ RTBA_EVL1_STDBY_LTE_CONN_SYNC_CHAN, /** Standby Sync Channel in LTE Connect Auto Gap. */
+ RTBA_EVL1_STDBY_CGI_SYNC_CHAN, /** Standby CGI Sync Channel. */
+
+ /****************** Schedule Type 3 ********************************************************/
+ RTBA_XL1_NSLT_PCH_OVHD_CHAN, /** Non-Slotted PCh Channel. */
+
+ /****************** Schedule Type 4 ********************************************************/
+ RTBA_XL1_NSLT_PCH_EARLY_WAKUP_CHAN, /** Non-Slotted PCh ChannelRegistered in early wakeup. */
+ RTBA_XL1_SLT_PCH_LOST_DET_CHAN, /** Slotted PCH Lost Detect Channle. */
+ RTBA_XL1_CONN_PS_RX_CHAN, /** Connect PS Rx. */
+ RTBA_EVL1_NSLT_CC_OVHD_CHAN, /** Non-Slotted CC Channel. */
+ RTBA_EVL1_CONN_RX_CHAN, /** Connect PS Rx. */
+ RTBA_EVL1_STDBY_CGI_CHAN, /** Standby CGI Channel. */
+ RTBA_PRIMARY_CHAN_END,
+
+ /****************** Secondary Channel ********************************************************/
+ RTBA_CL1_CHAN_SECONDARY_START,
+ RTBA_XL1_NSLT_INTER_MEAS_CHAN, /** Non-Slotted Inter-Meas Channel. */
+ RTBA_XL1_AFLT_MEAS_CHAN, /** AFLT Meas Channel. */
+ RTBA_XL1_SLT_INTER_MEAS_CHAN, /** Slotted Inter-Meas Channel with PCH_Lost channel. */
+ RTBA_XL1_CONN_INTER_MEAS_CHAN, /** Connect Inter Meas. */
+ RTBA_XL1_CONN_AFLT_CHAN, /** Connect AFLT Meas. */
+ RTBA_EVL1_RAKE_DDL_CHAN,
+ RTBA_EVL1_INTER_MEAS_CHAN, /** Slotted Inter-Meas Channel. */
+ RTBA_EVL1_CONN_INTER_MEAS_CHAN, /** Connect Inter Meas. */
+ RTBA_CL1_CHAN_SECONDARY_END,
+ RTBA_CL1_CHAN_NUM = RTBA_CL1_CHAN_SECONDARY_END
+}RtbaCl1ChannelTypeT;
+
+typedef enum
+{
+ RTBA_SCHEDULE_TYPE_0, /** Schedule Type 0: Single Reservation wo retry; RF stop needed.*/
+ RTBA_SCHEDULE_TYPE_1, /** Schedule Type 1: Single Reservation wo retry; Kick by cl1 or HSC; Small block schedule after.*/
+ RTBA_SCHEDULE_TYPE_2, /** Schedule Type 2: Continue Reservation with retry; Small block schedule after.*/
+ RTBA_SCHEDULE_TYPE_3, /** Schedule Type 3: Continue Reservation with retry; Small + long block switch.*/
+ RTBA_SCHEDULE_TYPE_4, /** Schedule Type 4: Continue Reservation with retry; normal block continue reservation*/
+ RTBA_SCHEDULE_TYPE_NUM
+}RtbaChannelScheTypeT;
+
+/** The Enum of the protect reason. */
+typedef enum
+{
+ UNPROTECTION,
+ PROTECT_1XRTT_PS,
+ PROTECT_EVDO_PS
+}RtbaProtecReasonT;
+
+/** The Scheduled Indication Type Send by RTBA to CL1. */
+typedef enum
+{
+ RTBA_INVALID_IND,
+ RTBA_GRANT_IND,
+ RTBA_PREEMPT_IND,
+ RTBA_RESUME_IND,
+ RTBA_RF_STOP_IND,
+ RC_OFF_CMPLT_IND
+}RtbaIndTypeT;
+
+/** The RTBA reserve length calc reference type.*/
+typedef enum
+{
+ FIRST_BLOCK_SCHE, /** Indicate this block is the first block of RTBA register.*/
+ RESUME_BLOCK_SCHE, /** Indicate this block is the resume block of RTBA register.*/
+ ACTIVE_BLOCK_SCHE /** Indicate this block is the active block of RTBA register.*/
+}RtbaResLenScheTypeT;
+
+/** The scheduled indication sending time and type. */
+typedef struct
+{
+ RtbaCl1ChannelTypeT Channel; /** The RTBA Channel. */
+ RtbaIndTypeT RtbaInd;
+ SysSFrameTimeT ScheTime;
+}RtbaScheIndTypeT;
+
+/** The RTBA Channel Status Enum. */
+typedef enum
+{
+ INACTIVE_STATUS,
+ REGISTER_PEND_STATUS,
+ PREEMPTED_STATUS,
+ GRANT_PEND_STATUS,
+ ACTIVE_STATUS,
+}RtbaChannelStatusT;
+
+/** RTBA Priority Index Enum.*/
+typedef enum
+{
+ RTBA_PRIO_INDEX_0,
+ RTBA_PRIO_INDEX_1,
+ RTBA_PRIO_INDEX_NUM
+}RtbaPriorityTypeT;
+
+typedef enum
+{
+ RTBA_GATE_MODE_ON,
+ RTBA_GATE_MODE_OFF
+}RtbaGateModeTypeT;
+
+typedef struct
+{
+ kal_uint32 GapEndTime;
+} RtbaGateModeRecordInfoT;
+
+typedef enum
+{
+ RTBA_GATE_MODE_ENABLE,
+ RTBA_GATE_MODE_DISABLE,
+ RTBA_MMO_GAP_OFFER_ENABLE,
+ RTBA_MMO_GAP_OFFER_DISABLE,
+ RTBA_MMO_GAP_OFFER_DISABLE_BY_RSVAS_SUSPEND,
+ RTBA_MMO_GAP_OFFER_DISABLE_BY_RMC_INIT_DONE
+} RtbaGateModeReasonT;
+
+/** RTBA Margin Combination for RC Control.*/
+typedef enum
+{
+ RTBA_FAKE_SCHE_MARGIN,
+ RTBA_FEC_DDL_MARGIN,
+ RTBA_CHECK_DSP_IDLE_MARGIN,
+ RC_CONTROL_MARGIN_NUM
+}RtbaRcContrilMarginT;
+
+#ifdef SYS_OPTION_TX_TAS_ENABLE
+typedef enum
+{
+ RTBA_TAS_BACK_OFF_DISABLE,
+ RTBA_TAS_BACK_OFF_ENABLE,
+ RTBA_TAS_BACK_OFF_UNKNOWN
+}RtbaTasQueryResultT;
+#endif
+
+
+/** RTBA RC Timing Structure.*/
+typedef struct
+{
+ SysSFrameTimeT FirstEventTiming;
+ kal_bool FakeFlag;
+ RtbaCl1ChannelTypeT Cl1Channel;
+}RtbaRcTimingTypeT;
+
+typedef void (*RtbaCbFunc)(RtbaIndTypeT RtbaInd, RtbaRcTimingTypeT RcTiming);
+
+typedef void (*RtbaQueryRsltProcFunc)(SysAirInterfaceT Mode, kal_bool ReserveSuccess,kal_uint32 AvailableTime);
+
+typedef void (*RtbaSeFnEvtFunc) (kal_uint32 Param);
+
+/** The RTBA RC Control Reference Timing.*/
+typedef struct
+{
+ kal_uint32 RtbaRfStopRefTiming;
+ kal_uint32 RtbaPreemptRefTiming;
+ kal_uint32 RtbaResumeGrantRefTiming;
+} RtbaScheRefTimeTypeT;
+
+/** Channel's RTB block information. */
+typedef struct
+{
+ RtbaCl1ChannelTypeT Channel; /** The scheduled channel type in RTBA. */
+ kal_uint32 ChannelPrio; /** Indicate the channel priority. */
+ kal_uint32 StartTime; /** Indicate the start time of channel in FRC. */
+ kal_uint32 EndTime; /** Indicate the end time of the channel in FRC. */
+ kal_uint32 ReserveLen; /** Indicate the reserve length of this channel. */
+ kal_uint32 PostProcessMargin; /** Indicate the channel post process margin.*/
+ kal_uint32 ActualReserveLen; /** The actual reserve length of the channel. */
+}RtbaChannelBlkInfoT;
+
+
+/** The Primary Channel Specific parameters used. */
+typedef struct
+{
+ RtbaChannelStatusT PreStatus; /** Indicate the channel's previous status. */
+ RtbaChannelStatusT Status; /** Indicate the channel status. */
+ RtbaChannelBlkInfoT PriChannelInfo[RTBA_TOTAL_BLOCK_NUM]; /** Indicate the channel information of schedule block and pending block. */
+ RtbaScheRefTimeTypeT ScheRefTime; /** The RTBA schedule reference time.*/
+ RtbaChannelScheTypeT ScheType; /** Indicate the channel schedule type.*/
+ kal_bool LongBlk; /** Indicate this is the long blk. */
+ kal_bool StarvationTrigger; /** Indicate the starvation triggered. */
+ kal_bool PriChanRegistered; /** Indicate the channel is registered to RTB.*/
+ RtbaCbFunc PriCallBackFunc; /** The Primary channel call back function pointer.*/
+ kal_uint32 QueryFrameNum; /** Indicate the query frame number.*/
+ kal_bool ScheRangeFlag; /** Indicate the RTBA needs to self-schedule the RTB block in the range of GapEndFRC.*/
+ kal_uint32 GapEndFRC; /** Indicate the gap end FRC time for specific channels.*/
+ kal_bool KickQueryByHsc; /** Indicate the Kick Query is triggered by HSC, no need to call back execute.*/
+ kal_bool ForceRtbReject; /** Indicate whether to force reject the RTB query result.*/
+}RtbaPriChannelParaT;
+
+
+/** The Secondary Channel Specific parameters used. */
+typedef struct
+{
+ RtbaChannelStatusT PreStatus; /** Indicate the channel's previous status. */
+ RtbaChannelStatusT Status; /** Indicate the channel status. */
+ RtbaChannelBlkInfoT SecChannelInfo; /** Indicate the channel information of scheduled secondary block.*/
+ RtbaCbFunc SecCallBackFunc; /** The Secondary channel call back function pointer.*/
+}RtbaSecChannelParaT;
+
+/** The RTBA internal data structure for schedule including channel information. */
+typedef struct
+{
+ RtbaPriChannelParaT PrimaryChanPara; /** The primary channel parameters. */
+ RtbaSecChannelParaT SecondaryChanPara; /** The secondary channel parameters, used for inter-meas block along with PCH continues block. */
+}RtbaScheInfoT;
+
+/** defines the RTBA API command types. */
+typedef enum
+{
+ RTBA_CMD_NONE,
+ RTBA_CMD_REG_PRIMARY,
+ RTBA_CMD_REG_SECONDARY,
+ RTBA_CMD_CANCEL_CHANEL,
+ RTBA_CMD_PRIO_BOOST,
+ RTBA_CMD_SMALL_BLK_REG,
+ RTBA_CMD_CHANNELCHANGE,
+ RTBA_CMD_PROTECT_CFG,
+ RTBA_CMD_KICK_QUERY,
+ RTBA_CMD_CANCEL_ALL,
+ RTBA_CMD_CANCEL_QUERY,
+ RTBA_CMD_GATE_MODE_REQ,
+ RTBA_CMD_ADJUST_CHAN_POS,
+ RTBA_CMD_CALC_PAGE_POS
+}RtbaCmdTypeT;
+
+typedef struct
+{
+ RtbaCmdTypeT Fifo[RTBA_CMD_FIFO_NUM];
+ kal_uint8 fifo_index;
+}RtbaCmdFifoTypeT;
+
+/** RTBA use this to record the Cl1's Primary Channel regisger information in ADS.*/
+typedef struct
+{
+ RtbaCl1ChannelTypeT Cl1Channel;
+ kal_bool StartTimeValid;
+ kal_uint32 StartTime;
+ kal_uint32 ReserveLen;
+ kal_uint32 GapEndFRC;
+ kal_uint32 PostProcessMargin;
+ RtbaCbFunc RtbaCallBackFunc;
+} RtbaPriRegisterReqAdsTypeT;
+
+/** RTBA use this to record the Cl1's Secondary Channel regisger information in ADS.*/
+typedef struct
+{
+ RtbaCl1ChannelTypeT Cl1Channel;
+ kal_bool StartTimeValid;
+ kal_uint32 StartTime;
+ kal_uint32 ReserveLen;
+ RtbaCbFunc RtbaCallBackFunc;
+} RtbaSecRegisterReqAdsTypeT;
+
+/** RTBA use this to record the Cl1's cancel information in ADS.*/
+typedef struct
+{
+ RtbaCl1ChannelTypeT Cl1Channel;
+ kal_bool CancelAll;
+} RtbaCancelReqAdsTypeT;
+
+/** RTBA use this to record the CL1's channel protection cfg.*/
+typedef struct
+{
+ kal_bool ProtectionTrig;
+} RtbaChannelProtectAdsTypeT;
+
+/** RTBA use this to record the to be changed channel protection cfg.*/
+typedef struct
+{
+ kal_bool ChannelChangePending;
+ RtbaCl1ChannelTypeT DestChannel;
+} RtbaChannelChangeAdsTypeT;
+
+/** RTBA use this to record the to be changed channel priority.*/
+typedef struct
+{
+ RtbaCl1ChannelTypeT PrioChannel;
+} RtbaChannelPrioBoostAdsTypeT;
+
+/** RTBA use this to record the gate mode releated Ads.*/
+typedef struct
+{
+ RtbaGateModeReasonT Reason;
+ kal_uint32 GapLen;
+} RtbaGateModeReqAdsTypeT;
+
+/** RTBA use this structure to record the channel adjust ads.*/
+typedef struct
+{
+ kal_uint32 NewStartTime;
+ kal_uint32 ReserveLen;
+} RtbaAdjustChanPosAdsTypeT;
+
+/** RTBA use this structure to record the small block register ads.*/
+typedef struct
+{
+ kal_bool QueryResult;
+ kal_uint32 NextavailableTime;
+} RtbaScheSmallBlkRegTypeT;
+typedef struct
+{
+ RtbaPriRegisterReqAdsTypeT PriamaryRegAds;
+ RtbaSecRegisterReqAdsTypeT SecondaryRegAds;
+ RtbaCancelReqAdsTypeT CancelAllAds;
+ RtbaCancelReqAdsTypeT CancelChannelAds;
+ RtbaChannelProtectAdsTypeT ProtectAds;
+ RtbaChannelChangeAdsTypeT ChannelChangeAds;
+ RtbaChannelPrioBoostAdsTypeT BoostChannelAds;
+ RtbaGateModeReqAdsTypeT GateModeReqAds;
+ RtbaAdjustChanPosAdsTypeT ChannelAdjPosAds;
+ RtbaScheSmallBlkRegTypeT SmallBlkRegAds;
+} RtbaCmdReqAdsTypeT;
+
+/** defines for RTBA Higher Timer Query Request ads send to RTB.*/
+typedef struct
+{
+ kal_int16 ChannelType;
+ kal_int32 StartTime;
+ kal_int32 CheckLen;
+ kal_int32 ChannelPrio;
+ kal_int32 PostProcessMargin;
+} RtbaHighTimerQueryInfoTypeT;
+
+typedef struct
+{
+ kal_int16 ChannelType;
+ kal_int32 StartTime;
+ kal_int32 ReserveLen;
+ kal_int32 ChannelPrio;
+} RtbaRegisrerInfoTypeT;
+
+typedef struct
+{
+ RtbaCl1ChannelTypeT Channel;
+ kal_bool DeniedByRtb;
+ kal_bool TimeValid;
+ kal_uint32 AvailableTime;
+} RtbaDeniedIndTypeT;
+
+typedef enum
+{
+ RTBA_SCHE_SEFN_STARTVATION,
+ RTBA_SCHE_SEFN_RF_STOP_IND,
+ RTBA_SCHE_SEFN_SYNC_RESERVE_END_IND,
+ RTBA_SCHE_SEFN_MMO_GAP_DISABLE,
+ RTBA_SEFN_SCHE_NUM
+}RtbaScheSefnTypeT;
+
+/* RTBA Gate Mode Req event structure */
+typedef struct
+{
+ SysAirInterfaceT Owner; /* 1xRTT or EVDO */
+ RtbaGateModeReasonT Reason; /* Gate Mode Reason */
+ kal_uint32 GapLen; /* Gap Length for MMO GAP OFFER ENABLE.*/
+}RtbaGateModeEventTypeT;
+
+typedef void (*RtbaScheSefnFunction)(kal_uint32 Parm);
+
+#define MERGE_STR(x,y) x##y /* ex : if x=123 and y=456, then MERGE_STR(x,y)=123456 */
+#define CL1_TIMER_TYPE(x) MERGE_STR(r,x)
+
+//MD1 and MD3 compiles independently. Therefore, MD1 should copy the MD3's files on MD1 side.
+typedef enum
+{
+ CL1_TIMER_TYPE(CTimerInit) = -1,
+ #include "cl1_timertype.h"
+ CL1_TIMER_TYPE(CTimerNum)
+}RtbTimerTypeT;
+
+#undef MERGE_STR
+#undef CL1_TIMER_TYPE
+
+typedef struct
+{
+ kal_uint32 ChannelBitMap; /*mapping C2K's channel type*/
+ kal_uint16 IsPeriodic; /*indicate the deny pattern is periodic or not*/
+ kal_uint16 PatternBitMap; /*mapping deny pattern*/
+}RbsDenyPatternParaT;
+
+typedef struct
+{
+ kal_uint16 RbsPatternInfo[RTBA_PRIMARY_CHAN_END]; /*Record PatternBitMap bases on channel type*/
+ kal_uint32 IsPeriodicMap; /*mapping channel's PatternBitMap is periodic or not*/
+}RbsDenyPatternInfoTypeT;
+
+/* HSC preempt trigger action type*/
+typedef enum
+{
+ HSC_PREEMPT_HYBRID_TYPE,
+ HSC_PREEMPT_SHDR_TYPE,
+ HSC_PREEMPT_EARLY_WAKEUP_TYPE,
+ HSC_PREEMPT_TYPE_NUM
+}HscActionParaE;
+
+typedef struct
+{
+ kal_uint32 ChannelBitMap; /* mapping C2K's channel type*/
+ kal_bool GrantPreemptTrig; /* Indicate RTBA grant or preempt to trigger Hsc preempt flow*/
+ kal_uint8 TimingBitMap; /* mapping block num and then judge whether to trigger Hsc preempt flow*/
+ kal_uint8 PreemptTimeOffset; /* preempt timing offset after trigger*/
+ kal_uint8 ResumeTimeOffset; /* resume timing offset after trigger*/
+ HscActionParaE HscActionType; /* indicate active type, hybrid,SHDR or early wakeup*/
+}HscPreemptTrigParaT;
+
+typedef struct
+{
+ kal_bool GrantPreemptTrig; /* Indicate RTBA grant or preempt to trigger Hsc preempt flow*/
+ kal_uint8 TimingBitMap[RTBA_PRIMARY_CHAN_END]; /* Record timing bit map bases on different channel type*/
+ kal_uint8 PreemptTimeOffset; /* preempt timing offset after trigger*/
+ kal_uint8 ResumeTimeOffset; /* resume timing offset after trigger*/
+ HscActionParaE HscActionType; /* indicate active type, hybrid,SHDR or early wakeup*/
+ kal_bool SecChanHscTrig; /* indicate whether secondary channel need to trigger HSC preempt*/
+}HscPreemptTrigInfoTypeT;
+
+typedef struct
+{
+ kal_uint32 LastPagingTime; /* Indicate Last paging receiving time*/
+ kal_uint32 Slot_cycle; /* Indicate 1xRTT DRX cycle*/
+ kal_bool Calc_Page; /* Indicate RTBA to calculate Paging position*/
+ kal_bool Sche_Page; /* Indicate RTBA to query resources without minAcceptLenght*/
+ kal_bool Adjust_Len; /* Indicate RTBA to adjust Nslt_pch channel length*/
+}RtbaSltPchScheParaT;
+
+typedef struct
+{
+ kal_uint32 LastPagingTime; /* Indicate Last paging receiving time*/
+ kal_uint32 Slot_cycle; /* Indicate 1xRTT DRX cycle*/
+ kal_bool Calc_Page; /* Indicate RTBA to calculate Paging position*/
+}RtbaSltPchParaT;
+typedef enum
+{
+ DO_RTB_PREEMPTION_AND_1xRTT_HYBRID_RESYNC_ACCEPT,
+ DO_RTB_PREEMPTION_AND_1xRTT_SHDR_RESYNC_ACCEPT,
+ DO_RTB_RESUME_AND_1xRTT_HYBRID_RESYNC_ACCEPT,
+ DO_RTB_RESUME_AND_1xRTT_SHDR_RESYNC_ACCEPT,
+ DO_RTB_PREEMPTION_AND_1xRTT_RTB_PREEMPT,
+ DO_RTB_RESUME_AND_1xRTT_RTB_PREEMPT,
+ DO_RTB_PREEMPTION_AND_1xRTT_RTB_RESUME,
+ DO_RTB_RESUME_AND_1xRTT_RTB_RESUME,
+ RTT_TIMING_CHANGE_SYNCTIME_CALC_TEST,
+ EVDO_TIMING_CHANGE_SYNCTIME_CALC_TEST,
+ FIRST_FRAME_TICK_POSITION_TST_1,
+ FIRST_FRAME_TICK_POSITION_TST_2,
+}RbsScenarioConfigTypeT;
+typedef struct
+{
+ RbsScenarioConfigTypeT RbsScenCfg;
+ kal_int32 TimingOffset;
+}RbsScenConfigParaT;
+typedef enum
+{
+ /** The initial state for RBS scenario control module.*/
+ RBS_SCEN_CTRL_NULL,
+
+ /** Indicate the RBS scenario parameter is configured but the pre-condition may not meet.*/
+ RBS_SCEN_CTRL_CONFIGED,
+
+ /** Indicate the RBS scenario pre-condition has meet, RTBA will start to re-schedule the RTB block to fulfill the RBS scenario.*/
+ RBS_SCEN_CTRL_TRIGGERED,
+
+ /** Indicate the RTB Block has been re-scheduled for scenario control.*/
+ RBS_SCEN_CTRL_RTB_RESCHED,
+
+ /** Indicate the channel has receive RTB grant.*/
+ RBS_SCEN_CTRL_SCHE_RTB_GRANT,
+
+ /** Indicate the channel has receive RTB preempt.*/
+ RBS_SCEN_CTRL_SCHE_RTB_PREEMPT,
+
+ /** Indicate the channel has receive RTB resume.*/
+ RBS_SCEN_CTRL_SCHE_RTB_RESUME,
+
+ /** Indicate the RBS scenario has achieved the scenario type configure.*/
+ RBS_SCEN_CTRL_FINISHED
+}RbsScenCtrlStateTypeT;
+
+typedef struct
+{
+ RbsScenarioConfigTypeT RbsScenarioConfig;
+ kal_int32 TimingOffset;
+} RbsScenarioControlParaT;
+
+typedef struct
+{
+ /** The RBS scenario control parameters.*/
+ RbsScenarioControlParaT RbsScenCtrlPara;
+ /** The Do state for RBS scenario control module.*/
+ RbsScenCtrlStateTypeT DoRbsState;
+ /** The 1xRTT state for RBS scenario control module.*/
+ RbsScenCtrlStateTypeT RttRbsState;
+ /** 1xRTT event reference time.*/
+ kal_uint32 RttEventRefTime;
+ /** EVDO event reference time.*/
+ kal_uint32 EvdoEventRefTime;
+ /** 1xRTT System Event Timing.*/
+ SysSFrameTimeT RttEventSysTime;
+ /** EVDO System Event Timing.*/
+ SysSFrameTimeT DoEventSysTime;
+ /** The RBS Scenario control bitmap collection.*/
+ kal_uint32 RbsScenCtrlBitmap;
+ /** The Record Target RBS scenario control bitmap.*/
+ kal_uint32 TargetRbsScenCtrlBitmap;
+ /** Indicate the event timing is adjusted by RTBA schedule.*/
+ kal_bool SpecificEvtTimingSet;
+} RbsScenarioControlScheInfoT;
+
+typedef enum
+{
+ CTimer_None,
+ CTimer_XL1IcsPiolt,
+ CTimer_XL1IcsSync,
+ CTimer_XL1NsltPchOvhd,
+ CTimer_XL1NsltInterMeas,
+ CTimer_XL1AfltMeas,
+ CTimer_XL1SltCci,
+ CTimer_XL1SltQpch_1,
+ CTimer_XL1SltQpch_2,
+ CTimer_XL1SltPch,
+ CTimer_XL1SltPchLostDet,
+ CTimer_XL1SltnterMeas,
+ CTimer_XL1ConnectPsRx,
+ CTimer_XL1ConnectInterMeas,
+ CTimer_XL1ConnectAfltMeas,
+ CTimer_EvL1IcsPilot,
+ CTimer_EvL1IcsSync,
+ CTimer_EvL1NsltCC,
+ CTimer_EvL1SltPch,
+ CTimer_EvL1InterMeas,
+ CTimer_EvL1ConnectRx,
+ CTimer_EvL1ConnectInterMeas,
+ CTimer_EvStdbyMeas,
+ CTimer_EvStdbySync,
+ CTimer_EvStdbyCgi,
+ CTimer_End
+}RtbTimerTypeE;
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cl1fhrtbaif.h b/mcu/interface/l1/cl1/common/cl1fhrtbaif.h
new file mode 100644
index 0000000..7e7296b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1fhrtbaif.h
@@ -0,0 +1,475 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1FHRTBAIF_H_
+#define _CL1FHRTBAIF_H_
+
+#ifdef MTK_DEV_93M_PREIT
+
+/*****************************************************************************
+
+ FILE NAME: cl1fhrtbaif.h
+
+ DESCRIPTION:
+
+ This file contains the message type and apis of RTBA for other modules.
+
+*****************************************************************************/
+
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "cl1fhrtbadefs.h"
+#define RTBA_PRI_CHANNEL_STATUS_GET(Mode) (RtbaChannelStatusGet(Mode,KAL_TRUE))
+
+#ifdef MTK_DEV_93M_RTBA_RBS_SCENARIO_CONTROL_ENABLE
+#define RBS_SCEN_CTRL_SPECIFIC_TIMING_SET(Enable) (gRtbaRbsScenCtrlScheInfo.SpecificEvtTimingSet = Enable)
+#define RBS_SCEN_CTRL_SPECIFIC_TIMING_GET() (gRtbaRbsScenCtrlScheInfo.SpecificEvtTimingSet)
+#endif
+
+/** The RF reserve end indication from RTBA. */
+typedef struct
+{
+ RtbaCl1ChannelTypeT Cl1Channel; /**The Rf Reserve End Ind received RTBA channel. */
+} Cl1RtbaRfReserveEndIndMsgT;
+#ifdef MTK_DEV_93M_RTBA_RBS_SCENARIO_CONTROL_ENABLE
+typedef struct
+{
+ kal_bool RbsScenCheckPass; /**The Rf Reserve End Ind received RTBA channel. */
+} RtbaRbsScenCtrlRptIndMsgT;
+#endif
+
+/*----------------------------------------------------------------------------
+* RTBA global APIs
+*----------------------------------------------------------------------------*/
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaInit
+
+ DESCRIPTION: The RTBA initialization function
+
+ PARAMETERS:
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaInit(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1SwitchActiveRatReq
+
+ DESCRIPTION: CL1 inform RTBA the rat status
+
+ PARAMETERS: SysAirInterface - 1xRTT or EVDO Activate - Indicate the mode is active or not
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1SwitchActiveRatReq(SysAirInterfaceT mode, kal_bool Activate);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1RegReq
+
+ DESCRIPTION: CL1 register channel on RTBA
+
+ PARAMETERS: mode - Indicate 1xRTT or EVDO
+ Cl1Channel - CL1 registered channel in RTBA
+ StartTimeValid - Indicate the start time is valid, if not, RTBA will try
+ to reserve the resource as soon as possible
+ StartTime - The start time of this channel in FRC
+ ReserveLen - The needed reserve length of this channel,in us unit
+ GapEndFRC - The gap end FRC time used by GM
+ *RtbaCallBackFunc - The channel specified call back funtion
+ HwState - Indicate RF On/Off
+
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1RegReq(SysAirInterfaceT Mode, RtbaCl1ChannelTypeT Cl1Channel,
+ kal_bool StartTimeValid, kal_uint32 StartTime, kal_uint32 ReserveLen, kal_uint32 GapEndFRC,
+ RtbaCbFunc RtbaCallBackFunc);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1RegWithPostProcessMarginReq
+
+ DESCRIPTION: CL1 register channel on RTBA
+
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ Cl1Channel - CL1 registered channel in RTBA
+ StartTimeValid - Indicate the start time is valid, if not, RTBA will try
+ to reserve the resource as soon as possible
+ StartTime - The start time of this channel in FRC
+ ReserveLen - The needed reserve length of this channel,in us unit
+ GapEndFRC - The gap end FRC time used by GM
+ PostProcessMargin - The post process margin for this channel
+ *RtbaCallBackFunc - The channel specified call back funtion
+
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1RegWithPostProcessMarginReq(SysAirInterfaceT Mode, RtbaCl1ChannelTypeT Cl1Channel,
+ kal_bool StartTimeValid, kal_uint32 StartTime, kal_uint32 ReserveLen, kal_uint32 GapEndFRC, kal_uint32 PostProcessMargin,
+ RtbaCbFunc RtbaCallBackFunc);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1ProtectionCfgReq
+
+ DESCRIPTION: CL1 Protect the channel on RTBA
+
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ ProtectReason - The channel protection reason
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1ProtectionCfgReq(SysAirInterfaceT Mode, RtbaProtecReasonT ProtectReason);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1CancelReq
+
+ DESCRIPTION: CL1 cancel the channel on RTBA
+
+ PARAMETERS: mode - Indicate 1xRTT or EVDO
+ CancelAll - True - Cancel all registered all reserve channel, False - Not cancel all
+ Cl1Channel - CL1 cancel channel in RTBA
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1CancelReq(SysAirInterfaceT Mode, kal_bool CancelAll, RtbaCl1ChannelTypeT Cl1Channel);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1CancelQueryReq
+
+ DESCRIPTION: CL1 cancel the query on RTBA
+
+ PARAMETERS: mode - Indicate 1xRTT or EVDO
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1CancelQueryReq(SysAirInterfaceT Mode);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1ChannelChangeReq
+
+ DESCRIPTION: CL1 change the channel to new channel on RTBA
+
+ PARAMETERS: mode - Indicate 1xRTT or EVDO
+ Cl1Channel - CL1 changed channel in RTBA
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1ChannelChangeReq(SysAirInterfaceT Mode, RtbaCl1ChannelTypeT Cl1Channel);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1KickQueryReq
+
+ DESCRIPTION: CL1 use this API to kick RTBA to query with RTB
+
+ PARAMETERS: Mode - Indicate the 1xRTT or EVDO mode
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1KickQueryReq(SysAirInterfaceT Mode);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaHscKickQueryReq
+
+ DESCRIPTION: HSC use this API to kick RTBA to query with RTB
+
+ PARAMETERS: Mode - Indicate the 1xRTT or EVDO mode
+ *ChannelType - HSC use this API to query the registered RTB channel, the queryied channel type is returned
+ *RxOnTime - The RF on time in C2K system time unit, valid only when the return value is true
+ *RxOffTime - The RF off time in C2K system time unit, valid only when the return value is true and the channel type is QPCH1/2 and CCI
+
+ RETURNED VALUES: The Query Result is success or not
+*****************************************************************************/
+extern kal_bool RtbaHscKickQueryReq(SysAirInterfaceT Mode, RtbaCl1ChannelTypeT *ChannelType, SysSFrameTimeT *RxOnTime, SysSFrameTimeT *RxOffTime);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaQueryEvdoDFSEndTime
+
+ DESCRIPTION: L1D use this API to get the EVDO's DFS End time and to calc the delay frame number
+
+ PARAMETERS:
+ RETURNED VALUES: The delayed frame number(20ms Frame size 0- no delay, 1- delay 20ms)
+*****************************************************************************/
+extern kal_uint8 RtbaQueryEvdoDFSEndTime(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaProcessSimIndexInfoMsg
+
+ DESCRIPTION: RTBA use this API to process the sim index information from VAL
+
+ PARAMETERS:
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaProcessSimIndexInfoMsg(void *MsgDataP);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaProcessMMOGapDisableMsg
+
+ DESCRIPTION: RTBA use this API to provide to HSC for help to disable MMO GAP
+
+ PARAMETERS:
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaProcessMMOGapDisableMsg(void *MsgDataP);
+
+
+#ifdef MTK_PLT_ON_PC_IT
+/*****************************************************************************
+
+ FUNCTION NAME: CBSSimIndexInfoMsg
+
+ DESCRIPTION: CBS use this API to process the sim index information from VAL
+
+ PARAMETERS:
+ RETURNED VALUES:
+*****************************************************************************/
+extern void CBSSimIndexInfoMsg(kal_bool C2KInSIM2);
+#endif
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaChannelPrioBoostReq
+
+ DESCRIPTION: RTBA provide this API for CL1 to raise the channel priority tempory for once time
+
+ PARAMETERS: Mode - Indicate the 1xRTT or EVDO mode
+ Cl1Channel - CL1 channel in RTBA to boost the priority
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaChannelPrioBoostReq(SysAirInterfaceT Mode, RtbaCl1ChannelTypeT Cl1Channel);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaGateModeReq
+
+ DESCRIPTION: RTBA Provide this API to CL1 to enable/disable the gate mode
+
+ PARAMETERS: Mode - Indicate the 1xRTT or EVDO mode
+ Reason - Indicate the gate mode enable/disble reason
+ GapLen - If the gate mode enable for MMO gap offer, the provided GAP length
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaGateModeReq(SysAirInterfaceT Mode, RtbaGateModeReasonT Reason, kal_uint32 GapLen);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaReadSimIndex
+
+ DESCRIPTION: RTBA use this API to provide sim index.
+
+ PARAMETERS:
+ RETURNED VALUES: current sim index
+*****************************************************************************/
+extern kal_uint32 RtbaReadSimIndex(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaEventHandler
+
+ DESCRIPTION: RTBA Event Handler main function
+
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaEventHandler(SysAirInterfaceT Mode);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaQueryScheduler
+
+ DESCRIPTION: RTBA Query Scheduler main function
+
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaQueryScheduler(SysAirInterfaceT Mode);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaQueryActiveBlockInfo
+
+ DESCRIPTION: RTBA Provide this API for other module to query the active block running in RTBA
+
+ PARAMETERS: Mode - Indicate to RTBA for query which mode's active channel
+ *BlockStartTime - If the channel is active, return the block start time in RTBA in system time format
+ - Only valid when the API returns KAL_TRUE
+
+ RETURNED VALUES: True - For Current Mode, the channel is active and user can get the block start time in *BlockStartTime
+ False - Currently no channel is active for this mode
+*****************************************************************************/
+extern kal_bool RtbaQueryActiveBlockInfo(SysAirInterfaceT Mode, kal_uint32 *BlockStartTime);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaProcGateModeReqEvent
+
+ DESCRIPTION: RTBA Provide this API for HSC/L1D to call for gate mode request event handle
+
+ PARAMETERS: EvtPtr - The pointer to the gate mode request
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaProcGateModeReqEvent(RtbaGateModeEventTypeT *EvtPtr);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1AdjustChannelPositionReq
+
+ DESCRIPTION: RTBA Provide this API for L1D to adjust the channel block schedule start time
+
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ StartTime - The new start time indicated by L1
+ ReserveLength - The channel reserve length indicated by L1
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1AdjustChannelPositionReq(SysAirInterfaceT Mode, kal_uint32 StartTime, kal_uint32 ReserveLen);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1GetRFOnMarginInfo
+
+ DESCRIPTION:
+
+ PARAMETERS:
+
+ RETURNED VALUES: The RF on margin
+*****************************************************************************/
+extern kal_uint32 RtbaCl1GetRFOnMarginInfo(void);
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1GetRFOffMarginInfo
+
+ DESCRIPTION:
+ PARAMETERS:
+
+ RETURNED VALUES: The RF off margin
+*****************************************************************************/
+extern kal_uint32 RtbaCl1GetRFOffMarginInfo(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: RtbaCl1PreClearReservationReq
+
+ DESCRIPTION: RTBA provide this API for CL1 to pre-clear reservation before the real cancel request is called
+ PARAMETERS:
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1PreClearReservationReq(SysAirInterfaceT Mode);
+
+/*****************************************************************************
+ FUNCTION NAME: RtbaCl1PreCancelReq
+
+ DESCRIPTION: RTBA provide this API for CL1 to pre-cancel the RF stop event before the real cancel request is called
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaCl1PreCancelReq(SysAirInterfaceT Mode);
+
+/*******************************************************************************
+
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ lastPagingTime - indicate lastPagingTime, unit 20ms
+ Slot_cycle - indicate slot_cycle of DRX
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaSltPchPositonReq(SysAirInterfaceT Mode, kal_uint32 LastPagingTime, kal_uint32 Slot_Cycle);
+#ifdef SYS_OPTION_TX_TAS_ENABLE
+/*****************************************************************************
+ FUNCTION NAME: RtbaTasBackOffQuery
+
+ DESCRIPTION: RTBA provide this API for TAS to query whether can execute
+ RF tuner or not
+ PARAMETERS: Mode - Indicate 1xRTT or EVDO
+ MinReserveLength -Indicate the the Min Length of TAS RF
+ Tuner
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void RtbaTasBackOffQuery(SysAirInterfaceT Mode, kal_uint32 MinReserveLength, RtbaTasQueryResultT* QueryResult);
+#endif
+
+/*****************************************************************************
+
+ FUNCTION NAME: RbsDenyPatternInfoRecord
+
+ DESCRIPTION: this API is used for recoding script infomation
+
+ PARAMETERS: pDenyPattern - point to script infomation
+
+ RETURNED VALUES:
+
+*****************************************************************************/
+#ifdef MTK_DEV_93M_RTBA_RBS_ENABLE
+extern void RbsDenyPatternInfoRecord(kal_uint8* pDenyPattern);
+#endif
+/*****************************************************************************
+
+ FUNCTION NAME: HscPreemptTrigInfoRecord
+
+ DESCRIPTION: this API is used for recoding script infomation
+
+ PARAMETERS: pHscPreemptTrig - point to script infomation
+
+ RETURNED VALUES:
+
+*****************************************************************************/
+#ifdef MTK_DEV_93M_RTBA_HPS_TRIG_ENABLE
+extern void HscPreemptTrigInfoRecord(kal_uint8* pHscPreemptTrig);
+#endif
+
+#ifdef MTK_DEV_93M_RTBA_RBS_SCENARIO_CONTROL_ENABLE
+extern void RtbaCl1RbsScenarioControlReq(RbsScenarioControlParaT *pRbsScenCtrlPara);
+#endif
+#endif
+#endif
diff --git a/mcu/interface/l1/cl1/common/cl1fr.h b/mcu/interface/l1/cl1/common/cl1fr.h
new file mode 100644
index 0000000..d36c278
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1fr.h
@@ -0,0 +1,152 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* FILE NAME : cl1fr.h
+*
+* DESCRIPTION :
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+
+#ifndef _CL1FR_H_
+#define _CL1FR_H_
+
+#include "cl1frevtid.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "c2k_defs.h"
+#ifndef MTK_PLT_ON_PC
+#ifdef __MD93__
+#define IRQ_C2K_FR_FH_SWI_CODE IRQ_SW_LISR15_CODE
+#elif defined (__MD95__)
+#define IRQ_C2K_FR_FH_SWI_CODE IRQ_SW_LISR8_CODE
+#else
+#define IRQ_C2K_FR_FH_SWI_CODE IRQ_SW_LISR8_CODE
+#endif
+
+#endif
+
+/* Frame tick related */
+typedef enum
+{
+ NORMAL_DOMAIN,
+ FRAMETICK_REGULAR,
+ FRAMETICK_HSC = FRAMETICK_REGULAR,
+ FRAMETICK_L1D,
+ FRAMETICK_RMC,
+ FRAMEHANDLER_IN_SWI,
+ FRAMEHANDLER_IN_PCGSLOT,
+ PCG_IRQ,
+ SLOT_IRQ,
+ RCPRI_IRQ,
+ OTHER_IRQ,
+
+ FR_MOD_MAX_NUM
+} FrModuleT;
+
+#if (CUR_GEN>=MD_GEN95)
+/*Running IRQ LISR location*/
+typedef enum
+{
+ LOC_HWD_WAKE_DO_LISR,
+ LOC_SYS_DO_SLOT_LISR,
+ LOC_SYS_DO_HALF_SLOT_LISR,
+ LOC_SYS_DO_HALF_SLOT_LISR_2,
+ LOC_FRAME_HANDLER_SWI_LISR,
+ LOC_SYS_FTIMER_DO_LISR,
+ LOC_LISR_RUN_MAX_NUM
+} IrqLisrRunT;
+#endif
+
+
+typedef struct
+{
+ kal_bool UseDm;
+ kal_bool Processed;
+ kal_uint16 EvtId;
+ kal_uint16 EvtLength; /* In byte */
+ kal_uint32 TimeStamp; /* In FRC */
+ kal_uint8* DataPtr;
+} EvtDataT;
+
+#define M_Fr2ByteAlign(x) ((((x) + 1) >> 1) << 1)
+#define M_Fr4ByteAlign(x) ((((x) + 3) >> 2) << 2)
+
+
+#define M_SetShOngoingFlag(Interface) {gShOngoing[Interface] = KAL_TRUE;}
+#define M_ClrShOngoingFlag(Interface) {gShOngoing[Interface] = KAL_FALSE;}
+#define M_IsShOngoing(Interface) (gShOngoing[Interface] == KAL_TRUE)
+
+
+extern kal_uint32 gSwiBitmap;
+extern kal_bool gShOngoing[SYS_MODE_MAX];
+extern kal_uint32 gFhSwiOwnerBitmap;
+
+extern void FrSendEvent(FrModuleT Src, FrModuleT Dest, FrEvtIdT EvtId, kal_bool UseDm, kal_uint8* DataPtr, kal_uint16 Length);
+extern void __FrIrqSendMsg(FrModuleT Src, module_type DestMod, msg_type MsgId, kal_bool UseDm, kal_uint8* DataPtr, kal_uint16 Length);
+extern void FrEventExecutor(FrModuleT Execution);
+extern void FrFhSwiEventExecutor(void);
+extern void FrFhSwiTrigger(SysAirInterfaceT Mode);
+extern void FrSwiTriggerHisr(void);
+extern void FrFhMsgDeliverHisr(void);
+extern void FrShMsgDeliverHisr(void);
+extern void FrRrMsgDeliverHisr(void);
+extern kal_bool FrEvtQueueEmpty(FrModuleT Module);
+extern kal_bool FrMsgQueueEmpty(FrModuleT Module);
+extern kal_bool FrAllQueueEmpty(void);
+
+#if (CUR_GEN>=MD_GEN95)
+extern void FrSamePrioIRQProcess(kal_bool mask,IrqLisrRunT IrqLisrRunLoc);
+#endif
+
+/* 2Bytes alignment is to make sure sizeof(XXX_msg_struct)=sizeof(LOCAL_PARA_HDR)+sizeof(msg),
+ because LOCAL_PARA_HDR has a uint16 item, sizeof(XXX_msg_struct) must be even number.
+ if the sizeof(msg) is odd, the equation is not fullfilled.
+*/
+#define FrIrqSendMsg(Src, DestMod, MsgId, UseDm, DataPtr, Length) \
+ __FrIrqSendMsg(Src, DestMod, MsgId, UseDm, DataPtr, M_Fr2ByteAlign(Length))
+
+#endif
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
diff --git a/mcu/interface/l1/cl1/common/cl1frevtid.h b/mcu/interface/l1/cl1/common/cl1frevtid.h
new file mode 100644
index 0000000..0d73450
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1frevtid.h
@@ -0,0 +1,77 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+
+#ifndef _CL1FREVTID_H_
+#define _CL1FREVTID_H_
+
+
+#define FR_EVT_ID_HEADER_FH_HSC (0x0200)
+#define FR_EVT_ID_HEADER_FH_XL1 (0x0400)
+#define FR_EVT_ID_HEADER_FH_RMC (0x0800)
+#define FR_EVT_ID_HEADER_XL1_SH (0x1000)
+#define FR_EVT_ID_HEADER_EVL1_SH (0x2000)
+#define FR_EVT_ID_HEADER_RCP_RI (0x4000)
+#define FR_EVT_ID_HEADER_TST (0x8000)
+
+#define FR_EVT_ID_HEADER_DEST_MASK (0x7E00)
+
+
+
+
+#define FR_EVT_ID_DEFINE(Id, Num, Header) Id=(FR_EVT_ID_HEADER_##Header|Num),
+typedef enum
+{
+ #include "cl1frtstevtid.h"
+ #include "cl1fhhscevtid.h"
+ #include "xl1fhevtid.h"
+ #include "evl1fhevtid.h"
+ #include "xl1shevtid.h"
+ #include "evl1shevtid.h"
+ #include "rcprievtid.h"
+
+ FR_EVT_ID_INVALID = 0xFFFF
+} FrEvtIdT;
+#undef FR_EVT_ID_DEFINE
+
+#endif
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
diff --git a/mcu/interface/l1/cl1/common/cl1frtstevtid.h b/mcu/interface/l1/cl1/common/cl1frtstevtid.h
new file mode 100644
index 0000000..bb4e4c4
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1frtstevtid.h
@@ -0,0 +1,74 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#if defined(MTK_DEV_93M_PREIT) && defined(MTK_PLT_ON_PC) && defined(MTK_PLT_ON_PC_IT)
+
+
+FR_EVT_ID_DEFINE(EVT_ID_TST_TASK_TO_FT_1, 0x00, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_TASK_TO_FT_2, 0x01, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_PCG_TO_FT_1, 0x02, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_PCG_TO_FT_2, 0x03, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SLOT_TO_FT_1, 0x04, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SLOT_TO_FT_2, 0x05, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_WAKE_TO_FT_1, 0x06, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_WAKE_TO_FT_2, 0x07, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_TASK_TO_PCG_1, 0x08, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_TASK_TO_PCG_2, 0x09, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_FT_TO_PCG_1, 0x0A, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_FT_TO_PCG_2, 0x0B, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SWI_TO_PCG_1, 0x0C, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SWI_TO_PCG_2, 0x0D, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SLOT_TO_PCG_1, 0x0E, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SLOT_TO_PCG_2, 0x0F, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_WAKE_TO_PCG_1, 0x10, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_WAKE_TO_PCG_2, 0x11, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_TASK_TO_SLOT_1, 0x12, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_TASK_TO_SLOT_2, 0x13, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_FT_TO_SLOT_1, 0x14, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_FT_TO_SLOT_2, 0x15, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SWI_TO_SLOT_1, 0x16, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_SWI_TO_SLOT_2, 0x17, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_PCG_TO_SLOT_1, 0x18, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_PCG_TO_SLOT_2, 0x19, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_WAKE_TO_SLOT_1, 0x1A, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_WAKE_TO_SLOT_2, 0x1B, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_UT_TRIG_TASK_TO_FT, 0x1C, TST)
+FR_EVT_ID_DEFINE(EVT_ID_TST_UT_TRIG_TASK_TO_SLOT, 0x1D, TST)
+
+
+
+/* MUST be less than 255 (0xFF) !!! */
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/cl1nbif.h b/mcu/interface/l1/cl1/common/cl1nbif.h
new file mode 100644
index 0000000..5c5e491
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1nbif.h
@@ -0,0 +1,155 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1nbif.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * global definition of NBIF calculaion.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#ifndef _CL1NBIF_H_
+#define _CL1NBIF_H_
+
+#include "kal_general_types.h"
+#include "sysapi.h"
+
+/*----------------------------------------------------------------------------
+ Global Defines And Macros
+----------------------------------------------------------------------------*/
+
+/* parameter of MSG_ID_L1D_MMAFC_NBIF_RX_ON_MSG */
+typedef PACKED_PREFIX struct
+{
+ SysAirInterfaceT Interface;
+ kal_uint8 Path;
+ kal_uint32 Channel;
+ SysCdmaBandT BandClass;
+ kal_int32 FoeHz; /*FOE adjusted by PLL, in Hz. A positive FOE means MS's clock is faster than BS */
+
+} PACKED_PREFIX Cl1NbifRxOnMsgT;
+
+/* parameter of MSG_ID_L1D_MMAFC_NBIF_RX_OFF_MSG */
+typedef PACKED_PREFIX struct
+{
+ SysAirInterfaceT Interface;
+ kal_uint8 Path;
+
+} PACKED_PREFIX Cl1NbifRxOffMsgT;
+
+/* parameter of MSG_ID_L1D_MMAFC_NBIF_FOE_UPDATE_MSG */
+typedef PACKED_PREFIX struct
+{
+ SysAirInterfaceT Interface;
+ kal_int32 FoeHz; /* FOE adjusted by PLL, in Hz. A positive FOE means MS's clock is faster than BS */
+
+} PACKED_PREFIX Cl1NbifFoeUpdateMsgT;
+
+/*----------------------------------------------------------------------------
+ Local Defines and Macros
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Local Typedefs
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Local Variables
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Local Function Prototypes
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+
+extern void Cl1NbifInit(void);
+extern void Cl1CalcNbifRxOn(Cl1NbifRxOnMsgT *MsgParam);
+extern void Cl1NbifFoeAdjust(Cl1NbifFoeUpdateMsgT *MsgParam);
+extern void Cl1CalcNbifRxOff(Cl1NbifRxOffMsgT *MsgParam);
+#if (defined(MTK_PLT_ON_PC_IT))||(defined(MTK_C2K_L1_TST))
+extern void Cl1TstPhyUtNbif1CalcCoef(SysAirInterfaceT Interface, kal_int32 FSpurHz, kal_int32 *NbifAI, kal_int32 *NbifAQ, kal_uint32 *NbifP);
+#endif
+
+/*****************************************************************************
+ Code Section
+*****************************************************************************/
+
+/*****************************************************************************
+* $Log: l1dnbif.h $
+*
+* 01 24 2017 yingqi.liu
+* [MOLY00226403] [Bianco Bring-up][6293][C2K] Modify NBIF and test code after PHY UT.
+*
+* .
+*
+* 11 09 2016 sue.zhong
+* [MOLY00208435] [6293][C2K]Sync C2K code to UMOLYA TRUNK
+*
+* Update C2K L1 source
+*****************************************************************************/
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
diff --git a/mcu/interface/l1/cl1/common/cl1rcapi.h b/mcu/interface/l1/cl1/common/cl1rcapi.h
new file mode 100644
index 0000000..f7da7d7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1rcapi.h
@@ -0,0 +1,125 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1_RCAPI_H_
+#define _CL1_RCAPI_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1rcapi.h
+*
+* DESCRIPTION : extern RC API
+*
+*
+************************************************************************************/
+#include "cl1rcreq.h"
+
+#if defined(__FPGA__) || defined(CL1_RC_DRV_DSP_SLEEP_FLOW_ONLY)
+#define CL1_RC_DRV_BOOTUP_TEMP
+#endif
+
+#if defined(MT6739) /* if ZION */
+#define C2K_DVFS_TX_CONTROL
+#endif
+
+typedef enum
+{
+ CL1_RC_SEQ_RAKE_DEACT_NULL,
+ CL1_RC_SEQ_RAKE_DEACT_WAIT,
+ CL1_RC_SEQ_RAKE_DEACT_SCHE,
+ CL1_RC_SEQ_RAKE_DEACT_EXE,
+ CL1_RC_SEQ_RAKE_DEACT_STAT_NUM
+}Cl1RcSeqRakeDeactStateT;
+
+typedef enum
+{
+ CL1_RC_SEQ_RAKE_DEACT_RCOFF_EVT,
+ CL1_RC_SEQ_RAKE_DEACT_D2BIFOFF_EVT,
+ CL1_RC_SEQ_RAKE_DEACT_CLR_EVT,
+ CL1_RC_SEQ_RAKE_DEACT_EVT_NUM
+}Cl1RcSeqRakeDeactEvtT;
+
+extern void Cl1RcInit(void);
+
+extern void Cl1RcReqInit(void);
+
+extern void Cl1ShRcSeqRttPeriodicalTrigger(void);
+
+extern void Cl1ShRcSeqEvdoPeriodicalTrigger(void);
+
+#if (defined(__MTK_TARGET__)&&(defined(__MD97__)||defined(__MD97P__))&&defined(CL1_RC_DRV_BOOTUP_TEMP)) || (defined(MT6763)||defined(MT6739))
+extern void Cl1RcdForceAllOn(void);
+#endif
+
+#if defined(__MD93__)||defined(__MD95__)
+extern void Cl1RcdTxRcOnNsftMode(void);
+#endif
+
+extern kal_uint8 Cl1RcReqRxOn(Cl1RcReqRxOnT *RxOn);
+
+extern void Cl1RcReqRxOff(Cl1RcReqRxOffT *RxOff);
+
+extern kal_uint8 Cl1RcReqTxOn(Cl1RcReqTxOnOffT *TxOn);
+
+extern void Cl1RcReqTxOff(Cl1RcReqTxOnOffT *TxOff);
+
+extern void Cl1RcReqSchOff(Cl1RcReqSchOffT *SchOff);
+
+extern void Cl1RcUtilGetRfOnTime(Cl1RcReqRxOnT *RxOn,SysSFrameTimeT * RfActionTime);
+
+extern void Cl1ShRcRakeOffTrigger(SysAirInterfaceT Mode);
+
+extern void Cl1RcdRakeOff(SysAirInterfaceT Mode);
+
+extern void Cl1RcdHwInit(void);
+
+extern void Cl1RcdBrpsysDvitReset(SysAirInterfaceT Mode);
+
+extern void Cl1RcSeqRakeDeactSchedule(SysAirInterfaceT Mode, Cl1RcSeqRakeDeactEvtT Evt);
+
+extern void Cl1RcdBrpsysTurboReset(SysAirInterfaceT Mode);
+
+extern void Cl1RcUtilRfOnMergeNotification(SysAirInterfaceT Mode);
+
+extern void Cl1RcdPartialBypassConf(SysAirInterfaceT Mode, kal_uint32 Conf1, kal_uint32 Conf2, kal_uint32 Conf3);
+
+extern void Cl1RcReqModemDvfsScenSet(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr, Cl1RcdDvfsScenT Scen);
+
+extern void Cl1RcReqModemDvfsScenCancel(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr);
+
+extern void Cl1RcdCssysSramOnOff(SysAirInterfaceT Mode,kal_bool Off);
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/cl1rcreq.h b/mcu/interface/l1/cl1/common/cl1rcreq.h
new file mode 100644
index 0000000..a6a7e15
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1rcreq.h
@@ -0,0 +1,299 @@
+ /*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1_RC_REQ_H_
+#define _CL1_RC_REQ_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1rcreq.h
+*
+* DESCRIPTION : This file contains data type definitions about RC Req
+*
+*
+************************************************************************************/
+
+/*Essential Definitions*/
+#include "sysdefs.h"
+#include "sysapi.h"
+#include "sysfrc.h"
+#include "cl1fr.h"
+#include "cl1fhrtbadefs.h"
+#include "cl1fhrtbaconstant.h"
+#include "hscapi.h"
+
+#if defined(MTK_DEV_93M_PREIT) && defined(MTK_PLT_ON_PC) && defined(MTK_PLT_ON_PC_IT) && defined(MTK_DEV_93M_C2K_L1_UT)
+#define CL1_RC_UNIT_TEST
+#endif
+
+#ifdef CL1_RC_UNIT_TEST
+#define M_CL1_RC_UT_LOG(a,b) Cl1RcUtLoggingBitmap(a,b)
+#else
+#define M_CL1_RC_UT_LOG(a,b)
+#endif
+
+
+
+/******************************** FEATURES MACROS ********************************/
+
+/*Define this macro to enable flow only, no rcd function invoked*/
+/*#define CL1_RC_REQ_SEQ_FLOW_ONLY (0)*/
+
+/*Define this macro to enable power control, but real api will be redefined as dummy function*/
+/*#define CL1_RC_DRV_PWR_CTRL_FLOW_ONLY (1)*/
+
+/*Define this macro to enable clock control, but no real hw will be accessed if this is macro defined*/
+/*#define CL1_RC_DRV_CLK_CTRL_FLOW_ONLY (2)*/
+
+/*Define this macro to enable sram control, but no real hw will be accessed if this is macro defined*/
+/*#define CL1_RC_DRV_SRAM_CTRL_FLOW_ONLY (3)*/
+
+/*Define this macro to enable modem dvfs, should be compatible with the flow only option enabled in dvfs driver*/
+/*#define CL1_RC_DRV_MODEM_DVFS_FLOW_ONLY (4)*/
+
+/*Define this macro to enable dsp sleep flow control, but real api will be redefined as dummy function*/
+/* #define CL1_RC_DRV_DSP_SLEEP_FLOW_ONLY (5) */
+
+/*Define this macro to enable dsp sleep flow control, but real api will be redefined as dummy function*/
+/* #define CL1_RC_DRV_DSP_DDL_FLOW_ONLY (6) */
+
+/******************************** Local Const Definitions ********************************/
+
+#define CL1_RC_PCG_DURATION (1536 << 3)
+#define CL1_RC_SLOT_DURATION (2048 << 3)
+
+#define CL1_RC_SFRAME_PCG_NUM (64)
+#define CL1_RC_SFRAME_SLOT_NUM (48)
+
+/*DDL duration in 1/8 chip unit*/
+#define CL1_RC_FEC_RX_DDL_DURATION (8356) /*unit is 1/8 chip*/
+#define CL1_RC_FEC_TRX_DDL_DURATION (9339) /*unit is 1/8 chip*/
+#define CL1_RC_RAKE_MD32_DDL_DURATION (47262) /*unit is 1/8 chip*/
+
+/*Different period to return to Arbiter to help decide how many TSs to protect*/
+#define CL1_RC_REQ_TXON_PERIOD (3)
+
+/* This macro used for RC internal Tx off flow schedule, value 3 is to guarantee that turn off Tx RC HW after Tx path off */
+#define CL1_RC_REQ_TXOFF_DELAY_PERIOD (3) /* 3 lots */
+
+#define CL1_RC_REQ_EVDO_TXOFF_DELAY_DURATION (CL1_RC_REQ_TXOFF_DELAY_PERIOD*1666) /* 3*1666=4998us, EVDO slot:1666us */
+#define CL1_RC_REQ_1XRTT_TXOFF_DELAY_DURATION (CL1_RC_REQ_TXOFF_DELAY_PERIOD*1250) /* 3*1250=3750us, 1xRTT slot:1250us */
+
+#if (CL1_RC_REQ_EVDO_TXOFF_DELAY_DURATION) > (CL1_IF_EVDO_RC_REQ_TXOFF_DELAY*1000)
+#error ("CL1_RC_REQ_EVDO_TXOFF_DELAY_DURATION) > (CL1_IF_EVDO_RC_REQ_TXOFF_DELAY*1000")
+#endif
+
+#if (CL1_RC_REQ_1XRTT_TXOFF_DELAY_DURATION) > (CL1_IF_1XRTT_RC_REQ_TXOFF_DELAY*1000)
+#error ("CL1_RC_REQ_1XRTT_TXOFF_DELAY_DURATION) > (CL1_IF_1XRTT_RC_REQ_TXOFF_DELAY*1000")
+#endif
+
+/*The maximum length of the request queue*/
+#define CL1_RC_REQ_QDEPTH (2)
+
+/*If the ongoing is 0xFF, the queue is empty*/
+#define CL1_RC_REQ_QEMPTY (0xFF)
+
+/*Magic number for optimize div3*/
+#define CL1_RC_DIV3_MAGIC_NUM (0xAAAAAAAB)
+
+#define CL1_RC_DIV3(Num) ((kal_uint32)((((kal_uint64)(Num))*CL1_RC_DIV3_MAGIC_NUM) >> 33))
+
+#define Cl1RcReqEchipOffset2TsNum(Mode, EchipOffset) (SysFrameSizeIs26ms(Mode)? ((EchipOffset) >> 14):(CL1_RC_DIV3(EchipOffset >> 12)))
+
+#define Cl1RcReqGetTsLength(Mode) (SysFrameSizeIs26ms(Mode)? CL1_RC_SLOT_DURATION : CL1_RC_PCG_DURATION)
+
+#define CL1_RC_REQ_FEC_HRT_MARGIN 1966 /*(200*6144/625)*/
+/******************************** Local Enumerations ********************************/
+
+typedef enum
+{
+ CL1_RC_SEQ_GROUP_TYPE_RX,
+ CL1_RC_SEQ_GROUP_TYPE_TX,
+ CL1_RC_SEQ_GROUP_TYPE_NUM
+}Cl1RcSeqGrpTypeT;
+
+/*Different type will lead to different RX ON RCsequence*/
+typedef enum
+{
+ CL1_RC_REQ_RXON_SCHONLY,
+ CL1_RC_REQ_RXON_CHANNELRX,
+ CL1_RC_REQ_RXON_STDBYMEAS,
+ CL1_RC_REQ_RXON_TYPENUM
+}Cl1RcReqRxOnTypeT;
+
+/*Different type means different resource to OFF*/
+typedef enum
+{
+ CL1_RC_REQ_RXOFF_SCHONLY,
+ CL1_RC_REQ_RXOFF_CHANNELRX,
+ CL1_RC_REQ_RXOFF_TYPENUM
+}Cl1RcReqRxOffTypeT;
+
+/*Different enum means different receiver of RC OFF COMPLETE EVENT*/
+typedef enum
+{
+ CL1_RC_REQ_OFF_COMPLETE_NOIND = 0, /*No need to send indication after RC OFF complete*/
+ CL1_RC_REQ_OFF_COMPLETE_2RI, /*Send indication to sleep RI after RC OFF complete*/
+ CL1_RC_REQ_OFF_COMPLETE_2NORMAL, /*Send indication to FT after RC OFF complete*/
+ CL1_RC_REQ_OFF_COMPELTE_TYPE_NUM
+}Cl1RcReqEndIndT;
+
+typedef enum
+{
+ CL1_RC_REQ_PARALLEL,
+ CL1_RC_REQ_CANCEL_ONGOING,
+ CL1_RC_REQ_PEND,
+ CL1_RC_REQ_INVALID,
+ CL1_RC_REQ_MERGE,
+ CL1_RC_REQ_ARB_NUM
+}Cl1RcReqArbT;
+
+typedef enum
+{
+ CL1_RC_REQ_RXON,
+ CL1_RC_REQ_RXOFF,
+ CL1_RC_REQ_TXON,
+ CL1_RC_REQ_TXOFF,
+ CL1_RC_REQ_SCHOFF,
+ CL1_RC_REQ_TYPENUM
+}Cl1RcReqTypeT;
+
+typedef enum
+{
+ CL1_RC_REQ_MODEM_DVFS_SET_RC,
+ CL1_RC_REQ_MODEM_DVFS_SET_HL,
+ CL1_RC_REQ_MODEM_DVFS_SET_NUM,
+}Cl1RcReqModemDvfsUsrT;
+
+typedef enum
+{
+ CL1_RCD_DVFS_SCEN_DEFAULT,
+ CL1_RCD_DVFS_SCEN_CHANNELTX,
+ CL1_RCD_DVFS_SCEN_CHANNELRX,
+ CL1_RCD_DVFS_SCEN_SCHONLY,
+ CL1_RCD_DVFS_SCEN_NUM
+}Cl1RcdDvfsScenT;
+
+/******************************** Local Structures ********************************/
+
+/*Define the RX ON request*/
+typedef struct
+{
+ RtbaRcTimingTypeT RtbTiming;
+ kal_bool RakeDdlInd; /*False: Need not to do Rake DDL; True: Need to do Rake DDL*/
+ kal_bool RcCotnrol; /*False: RF operation only; TRUE: RF operation with RC operation;*/
+ SysAirInterfaceT Mode;
+}Cl1RcReqRxOnT;
+
+/*Define the RX OFF request*/
+typedef struct
+{
+ SysSFrameTimeT EventTime;
+ Cl1RcReqEndIndT EndIndication;
+ SysAirInterfaceT Mode;
+}Cl1RcReqRxOffT;
+
+/*Define the TX ON/OFF request*/
+typedef struct
+{
+ SysSFrameTimeT EventTime;
+ kal_bool TxForAccess;
+ SysAirInterfaceT Mode;
+}Cl1RcReqTxOnOffT;
+
+/*A func ptr which should pooint to the function by which we can judge whether SCH post process is ongoing*/
+typedef kal_bool (*Cl1RcSchPostProcStatusFuncPtr)(void);
+
+/*Define the SCH OFF request*/
+typedef struct
+{
+ SysAirInterfaceT Mode;
+}Cl1RcReqSchOffT;
+
+/* RX/TX Req Data Stored */
+
+/*Define this union to merge the two kinds of request to simplify data manage and save memory*/
+typedef union
+{
+ Cl1RcReqRxOnT RxOnReq;
+ Cl1RcReqRxOffT RxOffReq;
+}Cl1RcReqRxOnOffT;
+
+typedef struct
+{
+ Cl1RcReqTypeT RcReqType;
+ Cl1RcReqRxOnOffT RcReqInfo;
+}Cl1RcReqRxOnOffInfoT;
+
+
+typedef struct
+{
+ Cl1RcReqRxOnOffInfoT Cl1RcReqRxQ[CL1_RC_REQ_QDEPTH];
+ kal_uint8 Ongoing;
+ kal_bool Pending;
+}Cl1RcReqRxOnOffInfoQueT;
+
+
+typedef struct
+{
+ Cl1RcReqTypeT RcReqType;
+ Cl1RcReqTxOnOffT RcReqInfo;
+}Cl1RcReqTxOnOffInfoT;
+
+
+typedef struct
+{
+ Cl1RcReqTxOnOffInfoT Cl1RcReqTxQ[CL1_RC_REQ_QDEPTH];
+ kal_uint8 Ongoing;
+ kal_bool Pending;
+}Cl1RcReqTxOnOffInfoQueT;
+
+
+/*********************************** RcReq internal functions ***********************************/
+void Cl1RcReqInit(void);
+void Cl1RcTestDDLStart(void);
+
+//void Cl1RcReqRxOnParse(Cl1RcReqRxOnT *RxOn, Cl1RcSeqRxParaT *RcSeq);
+
+//void Cl1RcReqRxOffParse(Cl1RcReqRxOffT *RxOff, Cl1RcSeqRxParaT *RcSeq);
+
+kal_bool Cl1RcReqRxEnque(Cl1RcReqRxOnOffInfoQueT *InfoQ, Cl1RcReqTypeT RcReqType, Cl1RcReqRxOnOffT *ReqInfo);
+
+void Cl1RcReqModemDvfsScenSet(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr, Cl1RcdDvfsScenT Scen);
+
+void Cl1RcReqModemDvfsScenCancel(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr);
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cl1shradarb.h b/mcu/interface/l1/cl1/common/cl1shradarb.h
new file mode 100644
index 0000000..42143cd
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1shradarb.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1_SH_RAD_ARB_H_
+#define _CL1_SH_RAD_ARB_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1shradarb.h
+*
+* DESCRIPTION : Radio arbiter interface defination
+*
+* HISTORY :
+* See Log at end of file
+*
+************************************************************************************/
+
+
+#include "cl1shrfc.h"
+
+/*----------------------------------------------------------------------------
+ Global Defines
+----------------------------------------------------------------------------*/
+
+
+typedef RfcActionT RadArbActionT;
+
+typedef RfcActionTimeT RadArbActionTimeT;
+
+typedef RfcActionReqT RadArbReqRfT;
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+void Cl1ShArbInit(void);
+void Cl1ShArbTaskTxRfReq (RadArbReqRfT *RadArbReqRfPtr);
+void Cl1ShArbFrTickRfReq(RadArbReqRfT *RadArbReqRfPtr);
+void Cl1ShArbMain( SysAirInterfaceT Interface);
+void Cl1ShArbEvtHandler(kal_uint8 *DataPtr);
+void Cl1ShArbShRfRdyInd (SysAirInterfaceT Interface);
+void Cl1ShArbClearFreezeReq(SysAirInterfaceT Interface);
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/cl1shrakearb.h b/mcu/interface/l1/cl1/common/cl1shrakearb.h
new file mode 100644
index 0000000..1cc2ee7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1shrakearb.h
@@ -0,0 +1,112 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1_SH_RAKE_ARB_H_
+#define _CL1_SH_RAKE_ARB_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1shrakearb.h
+*
+* DESCRIPTION : SHRH RAKE arbiter interface defination
+*
+* HISTORY :
+* See Log at end of file
+*
+* Author: Vincent
+*
+************************************************************************************/
+
+
+#include "cl1shrfc.h"
+
+/*----------------------------------------------------------------------------
+ Global Defines
+----------------------------------------------------------------------------*/
+#define CL1_RAKE_ACTIVE_MODE_1X (0x01)
+#define CL1_RAKE_ACTIVE_MODE_DO (0x02)
+#define CL1_RAKE_ACTIVE_MODE_BOTH (0x03)
+#define CL1_RAKE_ACTIVE_MODE_NULL (0x00)
+
+typedef enum
+{
+ CL1_RAKE_ARB_RET_NULL = 0,
+ CL1_RAKE_ARB_RET_ON_FIRST,
+ CL1_RAKE_ARB_RET_ON_2ND,
+ CL1_RAKE_ARB_RET_OFF_LAST,
+ CL1_RAKE_ARB_RET_OFF_FIRST,
+ CL1_RAKE_ARB_RET_MAX
+} Cl1ShRakeArbRet;
+
+typedef enum
+{
+ CL1_RAKE_ARB_EVT_PRE_ON = 0,
+ CL1_RAKE_ARB_EVT_ON,
+ CL1_RAKE_ARB_EVT_OFF,
+ CL1_RAKE_ARB_EVT_OFF_WIRC,
+ CL1_RAKE_ARB_EVT_MAX
+} Cl1ShRakeArbEventType;
+
+typedef enum
+{
+ CL1_RAKE_ARB_ST_NULL = 0,
+ CL1_RAKE_ARB_ST_PREON,
+ CL1_RAKE_ARB_ST_PREON_PREON,
+ CL1_RAKE_ARB_ST_ON,
+ CL1_RAKE_ARB_ST_ON_PREON,
+ CL1_RAKE_ARB_ST_ON_ON,
+ CL1_RAKE_ARB_ST_MAX
+} Cl1ShRakeArbInterStateT;
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+void Cl1ShRakeArbInit(void);
+Cl1ShRakeArbRet Cl1ShRakeArb(SysAirInterfaceT mode,Cl1ShRakeArbEventType event);
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif/*_CL1_SH_RAKE_ARB_H_*/
+
+
diff --git a/mcu/interface/l1/cl1/common/cl1shrfc.h b/mcu/interface/l1/cl1/common/cl1shrfc.h
new file mode 100644
index 0000000..62dfff5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1shrfc.h
@@ -0,0 +1,294 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1_SH_RFC_H_
+#define _CL1_SH_RFC_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1shrfc.h
+*
+* DESCRIPTION : RF control interface defination
+*
+* HISTORY :
+* See Log at end of file
+*
+************************************************************************************/
+
+
+#include "kal_public_api.h"
+#include "sysapi.h"
+#include "cl1rcapi.h"
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+#include "../rfd/cl1_rf_tas_public.h"
+#include "cl1d_rf_common_defs.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ Global Defines
+----------------------------------------------------------------------------*/
+/* Pll settling time In Echip, TBD, would be replaced by RFD interface*/
+#define RFC_PLL_TIM_ECHIP (246*8)
+
+#if defined( __MD93__)||defined( __MD95__)
+#define RFC_DO_RXPATH_DELAY (128)
+#else
+#if defined(MT6297)
+#define RFC_DO_RXPATH_DELAY (213)
+#elif defined(MT6885) || defined(MT6873)
+#define RFC_DO_RXPATH_DELAY (193)
+#else
+#define RFC_DO_RXPATH_DELAY (193)
+#endif
+#endif
+
+/**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/
+#ifdef __MD93__
+#define RFC_DO_TRXPATH_DELAY (278) //Same as DO_TXRXDELAY
+#elif defined __MD95__
+#define RFC_DO_TRXPATH_DELAY (273) //Same as DO_TXRXDELAY
+#else
+/**Used to Other Setting ,for example MD97*/
+#if defined(MT6297)
+#define RFC_DO_TRXPATH_DELAY (419) //Same as DO_TXRXDELAY /**415 -->419, Tx Transmite Error change from 0.5us to 0.05us for Apollo*/
+#elif defined(MT6885)|| defined(MT6873)
+#define RFC_DO_TRXPATH_DELAY (402) //Same as DO_TXRXDELAY /**419 -->399, Tx Transmite Error change from 1.9us to 0.05us for Petrus*/
+#else
+#define RFC_DO_TRXPATH_DELAY (402) //Same as DO_TXRXDELAY
+#endif
+
+#endif
+
+/**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/
+#ifdef __MD93__
+#define RFC_RTT_TRXPATH_DELAY (278) //Same as RTT_TXRXDELAY_INIT
+#define RFC_RTT_RXPATH_DELAY (128)
+#elif defined __MD95__
+#define RFC_RTT_TRXPATH_DELAY (273) //Same as RTT_TXRXDELAY_INIT
+#define RFC_RTT_RXPATH_DELAY (128)
+#else
+/**Used to Other Setting ,for example MD97*/
+#if defined(MT6297)
+#define RFC_RTT_TRXPATH_DELAY (419) //Same as RTT_TXRXDELAY_INIT /**415 -->419, Tx Transmite Error change from 0.5us to 0.05us for Apollo*/
+#define RFC_RTT_RXPATH_DELAY (213)
+#elif defined(MT6885) || defined(MT6873)
+#define RFC_RTT_TRXPATH_DELAY (402) //Same as RTT_TXRXDELAY_INIT /**419 -->399, Tx Transmite Error change from 1.9us to 0.05us for Petrus*/
+#define RFC_RTT_RXPATH_DELAY (193)
+#else
+#define RFC_RTT_TRXPATH_DELAY (402) //Same as RTT_TXRXDELAY_INIT
+#define RFC_RTT_RXPATH_DELAY (193)
+#endif
+#endif
+
+#define RFC_RTT_TXPATH_DELAY (RFC_RTT_TRXPATH_DELAY - RFC_RTT_RXPATH_DELAY)
+
+#define RFC_RTT_GATE_ON_OFF_DELAY (400/*TBD*/)
+
+
+/* 80ms Period length in Echip*/
+#define RFC_80MS_PERIOD 0xC0000
+
+/* PCG Period Length In Echip*/
+#define RFC_RTT_PCG_PERIOD (1536*8)
+
+/* Slot Period Length In Echip*/
+#define RFC_EVDO_SLOT_PERIOD (2048*8)
+
+
+typedef enum
+{
+ RFC_PATH_RxM = 0,
+ RFC_PATH_RxD,
+ RFC_PATH_RxS,
+ RFC_PATH_Tx,
+ RFC_MAX_PATH
+}RfcPathTypT;
+
+typedef enum
+{
+ RFC_FREEZE_NONE = 0,
+ RFC_TX_FREEZE,
+ RFC_TX_UNFREEZE,
+}RfcFreezeTypT;
+
+
+typedef enum
+{
+ RFC_TASK_REQUEST = 0,
+ RFC_FRAME_REQUEST,
+ RFC_SLOT_PCG_REQUEST
+}RfcRequestTypT;
+
+
+typedef enum
+{
+ RFC_PATH_OFF,
+ RFC_PATH_OFF_ONGOING,
+ RFC_PATH_ON,
+ RFC_PATH_ON_ONGOING
+}RfcPathStatusT;
+
+
+typedef enum
+{
+ RFC_PATH_RC_OFF,
+ RFC_PATH_RC_ONGOING,
+ RFC_PATH_RC_ON
+}RfcPathRcStatusT;
+
+
+typedef enum
+{
+ RFC_IDLE,
+ RFC_1X_MAIN_ONLY,
+ RFC_1X_DIV_ONLY,
+ RFC_1X_DIV_RX,
+ RFC_DO_MAIN_ONLY,
+ RFC_DO_DIV_ONLY,
+ RFC_DO_DIV_RX,
+ RFC_SHDR,
+ RFC_1X_DFS,
+ RFC_DO_DFS
+}RfcScenarioT;
+
+
+typedef enum
+{
+ ACTION_OFF = 0,
+ ACTION_ON = 1,
+ ACTION_NUM = 2
+}RfcActionOnOffT;
+
+typedef struct
+{
+ SysAirInterfaceT Interface;
+ SysCdmaBandT Band;
+ kal_uint16 Chan;
+ RfcPathTypT Path;
+ RfcActionOnOffT ActionTyp;
+ RfcRequestTypT RequestTyp;
+ void* CommonParmPtr;
+}RfcActionT;
+
+
+typedef struct
+{
+ /* 80ms timing, in echip*/
+ kal_int32 Timing;
+
+ /* Super Frame number*/
+ kal_uint64 SuperFrame;
+
+ /* Immaction, if TRUE, "Timing&SuperFrame" would be obmitted*/
+ kal_bool ImmAction;
+}RfcActionTimeT;
+
+
+typedef struct
+{
+ /* Req Timing Info, Filled Rx Modules(RTBA) in FH
+ * if "RcCtrl" is TRUE, filled with RC timing.
+ * Otherwise, filled with RF timing.
+ */
+ RtbaRcTimingTypeT ReqTiming;
+
+ /* Rake Ddl Indication , for Rx Only*/
+ kal_bool RakeDdlInd;
+
+ /* Rc Control Indication*/
+ kal_bool RcCtrl;
+
+ /* Used for Rc RxOff with "RcCtrl"== TRUE Only*/
+ Cl1RcReqEndIndT EndIndication;
+
+ /* Access Tx Indication*/
+ kal_bool AcTxInd;
+
+ /* Action body*/
+ RfcActionT Action;
+
+ /* Action Timing, Filled by Tx Modules in Task(Without RTBA)
+ * "ImmAction" is valid for both Tx and Rx immedaite action.
+ */
+ RfcActionTimeT ActionTiming;
+}RfcActionReqT;
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+extern C2K_CUSTOM_TAS_STATE_E AntCurrentState[RF_Band_NUM_MAX];
+extern C2K_CUSTOM_TAS_STATE_E GetAntCurrentState(SysCdmaBandT band);
+#endif
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+void Cl1ShRfcInit(void);
+void Cl1ShRfcActionReq(RfcActionReqT *ActionReqPtr);
+void Cl1ShRfcMain(SysAirInterfaceT Interface);
+void Cl1ShRfcStatChange(kal_uint32 Param);
+void Cl1ShRfcRcStatToOff(kal_uint32 Param);
+void Cl1ShRfcRcStatToOn(kal_uint32 Param);
+RfcPathStatusT Cl1ShRfcRfStatGet(SysAirInterfaceT Interface, RfcPathTypT Path);
+RfcScenarioT Cl1ShRfcScenarioGet(void);
+void Cl1ShRfcTxFreezeReq(SysAirInterfaceT Interface);
+void Cl1ShRfcTxUnFreezeReq(SysAirInterfaceT Interface);
+kal_bool Cl1ShRfcTxFreezeReqCheck(SysAirInterfaceT Interface);
+RfcPathRcStatusT Cl1ShRfcRcStatGet(SysAirInterfaceT Interface, RfcPathTypT Path);
+void Cl1RfcGetNextRxBoundary(SysAirInterfaceT Interface, kal_int32 *EchipTime, kal_uint64 *SuperFrame);
+void Cl1ShRfcRcReq(SysAirInterfaceT Interface, RfcPathTypT Path, RfcActionOnOffT ActionTyp, RtbaRcTimingTypeT *RcReqTimingPtr, Cl1RcReqEndIndT EndIndication, kal_bool RakeDdlInd, kal_bool AcTxInd);
+void Cl1ShRfcrRxPathInfoGet(SysAirInterfaceT Interface, kal_uint16 *BandPtr, kal_uint16 *ChanPtr);
+void Cl1ShRfcTxOnTimingLogging(void);
+
+#ifdef SYS_OPTION_TX_TAS_ENABLE
+kal_bool Cl1ShRfcOnlyRfImmediateOn(SysAirInterfaceT CurrInterface, kal_uint16 CurrBand,
+ kal_uint16 CurrChan);
+kal_bool Cl1ShRfcOnlyRfImmediateOff(SysAirInterfaceT CurrInterface, kal_uint16 CurrBand,
+ kal_uint16 CurrChan);
+#endif
+#ifdef MTK_DEV_TEMP_C2K_OTFC
+extern kal_uint8 Cl1ShTxDpdOtfcHistoryRecPush(SysAirInterfaceT Interface, kal_uint32 Channel, SysCdmaBandT BandClass);
+extern kal_uint8 Cl1ShTxDpdOtfcGetHistoryRecIdx(SysAirInterfaceT Interface, kal_uint32 Channel, SysCdmaBandT BandClass);
+#endif
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cl1sleep.h b/mcu/interface/l1/cl1/common/cl1sleep.h
new file mode 100644
index 0000000..aded35e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1sleep.h
@@ -0,0 +1,123 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1SLEEP_H_
+#define _CL1SLEEP_H_
+/*****************************************************************************
+
+ FILE NAME: hwdsleep.h
+
+ DESCRIPTION:
+ Interface to hwdsleep.c
+
+*****************************************************************************/
+
+#include "sysapi.h"
+
+/*------------------------------------------------------------------------
+ * exported data
+ *------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Global Defines and Macros
+----------------------------------------------------------------------------*/
+#define PAUSE_CMD_SW_MARGIN (1500) /* 5T 32K SW Margin */
+#define PAUSE_CMD_MARGIN (1500 + PAUSE_CMD_SW_MARGIN) /* 3T 32K + 2T uncertanty + 5T SW Margin */
+
+typedef struct
+{
+ kal_bool SleepState; /* Indicate whether UE is in sleep state */
+ kal_uint32 WakeTime; /* record wake up time */
+ kal_uint64 WakeDuration; /* record total wake duration after UE boot up */
+} Cl1WakeInfoT;
+
+typedef struct
+{
+ kal_uint8 CurrentIdx; /* Indicate current index */
+ Cl1WakeInfoT WakeInfo[2]; /* record wake info, 2 index for ping-pang buffer for corner case query in sleep or wake up boundary */
+ kal_uint32 WakeCnt; /* record total wake counts after UE boot up */
+ kal_uint32 SleepCnt; /* record total sleep counts after UE boot up */
+} Cl1SleepEmInfoT;
+
+extern Cl1SleepEmInfoT gCl1SleepEmInfo[SYS_MODE_MAX];
+
+/* Clock Control Blocks */
+typedef enum
+{
+ HWD_BLK_CTRL_PPP_HA,
+ HWD_BLK_CTRL_1X_SYSTIME,
+ HWD_BLK_CTRL_DO_SYSTIME,
+
+ HWD_BLK_CTRL_FT_CTRL,
+ HWD_BLK_CTRL_RF_CTRL,
+
+ HWD_BLK_CTRL_NUM_BLOCKS
+} HwdBlkControlBlocksT;
+
+#ifndef MTK_PLT_ON_PC
+#define IRQ_WAKE1X_IRQ_CODE IRQ_ST1x_WAKEUP_IRQ_CODE
+#define IRQ_WAKEDO_IRQ_CODE IRQ_STDO_WAKEUP_IRQ_CODE
+#else
+#define IRQ_WAKE1X_IRQ_CODE OSC_ISR_SRC_CUSTOM10
+#define IRQ_WAKEDO_IRQ_CODE OSC_ISR_SRC_CUSTOM11
+#endif
+
+/*------------------------------------------------------------------------
+ * exported functions
+ *------------------------------------------------------------------------*/
+
+extern void HwdSleepInit(void);
+extern kal_bool HwdEnterCbpDeepSleepCheck(SysAirInterfaceT Interface) ;
+extern void HwdWakeupSlpCtrl( SysAirInterfaceT Interface ) ;
+extern void HwdDeepSleepClearCancellingFlag(SysAirInterfaceT Interface);
+extern kal_bool HwdIsBlockConfigValid( HwdBlkControlBlocksT Block );
+extern kal_bool HwdCheckDeepSleepMode( SysAirInterfaceT Interface);
+extern kal_bool HwdCheckDeepSleepHWMode(SysAirInterfaceT Interface);
+extern void HwdSleepOverHisr1x(void);
+extern void HwdSleepOverHisrDO(void);
+extern void HwdSleepSetCalValue(SysAirInterfaceT Interface, kal_uint32 CalValue);
+extern kal_uint32 HwdSleepCalcCalValue(SysAirInterfaceT Interface, kal_uint32 ScCnt, kal_uint32 FcFreq, kal_uint32 FcCnt);
+extern void HwdSleepSetSlpOffset(SysAirInterfaceT Interface, kal_int16 Offset);
+extern kal_uint32 HwdSleepTimesGet(SysAirInterfaceT Interface);
+extern void Cl1SmTick(SysAirInterfaceT Interface);
+extern void HwdDeepSleepRecover(void);
+extern void Cl1_slp_info_calc(SysAirInterfaceT Interface, kal_uint64 *working_time, kal_uint32 *wakeup_cnt, kal_uint32 *sleep_cnt);
+
+/*****************************************************************************
+ * End of file
+ *****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cl1tskll1aapi.h b/mcu/interface/l1/cl1/common/cl1tskll1aapi.h
new file mode 100644
index 0000000..56f5763
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tskll1aapi.h
@@ -0,0 +1,420 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1TSKLL1AAPI_H_
+#define _CL1TSKLL1AAPI_H_
+
+#ifdef MTK_DEV_93M_PREIT
+
+/*****************************************************************************
+
+ FILE NAME: cl1tskll1aapi.h
+
+ DESCRIPTION:
+
+ This file contains the message type and apis of LL1A for other modules.
+
+*****************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "cl1tskll1adefs.h"
+
+
+/*----------------------------------------------------------------------------
+* Definitions
+*----------------------------------------------------------------------------*/
+#define GAP_SESSION_IN_PERIOD (6) /** The maximum number of gap session in one gap notify ind. */
+
+#define GAP_MARGIN_FOR_STANDBY (10000) /** The Gap margin for Standby rat when EVDO in active.*/
+#define GAP_MARGIN_FOR_STANDBY_OVERLAP (20000) /** The header or end Gap margin for Standby rat when EVDO in active.*/
+
+extern Ll1aScheInfoT gLl1aScheInfo;
+
+#define LL1A_GAP_SERVICE_STATUS_SET(Enable) (gLl1aScheInfo.GapServiceEnable = Enable)
+#define LL1A_GAP_SERVICE_STATUS_GET() (gLl1aScheInfo.GapServiceEnable)
+
+#define LL1A_GAP_OFFERED_STATUS_SET(Status) (gLl1aScheInfo.GapOfferedStatus = Status)
+#define LL1A_GAP_OFFERED_STATUS_GET() (gLl1aScheInfo.GapOfferedStatus)
+
+
+/*----------------------------------------------------------------------------
+ Message Formats structure
+----------------------------------------------------------------------------*/
+/**********************************************RMC Interface Related*********************************/
+
+/** Rmc Rat Status Ind. */
+typedef struct
+{
+ RmcRatStatusT RatStatus; /* Flight/Standby/Active. */
+} Ll1aRmcRatStatusIndMsgT;
+
+/** Rmc Mode Status Ind. */
+typedef struct
+{
+ RmcModeStatusT ModeStatus; /* NULL/IDLE/CONNECTED. */
+ kal_uint16 DrxCycleLength;/* When IDLE Mode, this value is valid and in slot unit. */
+} Ll1aRmcModeStatusIndMsgT;
+
+/** Rmc Inter-Freq Number. */
+typedef struct
+{
+ kal_uint8 FreqNum; /** EVDO in active, the number of higher priority inter-freq.*/
+ /** When HPS off, the freq_num is equal to zero. */
+} Ll1aRmcActiveMeasInfoIndMsgT;
+
+/** EvStandby Send the standby meas config to LL1A, including the meas purpose and meas type. */
+typedef struct
+{
+ kal_uint8 MeasPurpose; /** Bit0 - Meas On/Off, Bit1 - Cell Search On/Off. */
+ kal_uint8 TickBitMap; /** Bit0 - TICK_BITMAP_MPSR, Bit1 - TICK_BITMAP_HPS, Bit2 - TICK_BITMAP_LPS, Bit3 - TICK_BITMAP_RES. */
+ kal_uint8 FreqNum; /** This need EvStandby to fill it with different Meas On/Off and Thps On/Off Combination. */
+ kal_uint8 IsPeriodResetBitMap; /** Bit0 - RANK BIT Bit1 - HIGH PRIORITY BIT. */
+ kal_uint8 Tid; /** The Tid for this standby meas request. */
+} Ll1aEvStandbyMeasReqMsgT;
+
+/** This is a gap session stricture, with the start time and duration in EVDO's system time format. */
+typedef struct
+{
+ kal_uint32 GapSessionStartTime; /** The Start Time of Standby Gap. The start time is based on FRC time.*/
+ /* modify it to kal_uint32 to keep same with 91 for EVL1 flow */
+ kal_uint32 GapSessionLength; /** The Length of Standby Gap. The start time is based on FRC time.*/
+} GapSessionTypeT;
+
+
+/** The EvStandby' Gap Notify Ind Structure. */
+typedef struct
+{
+ kal_uint8 Tid; /** The Tid for this gap notify ind. */
+ kal_uint8 GapSessionNum; /** 1 - For Idle Gap; 1 < number <=6 - For Connect Gap. */
+ GapSessionTypeT GapSession[GAP_SESSION_IN_PERIOD]; /** LL1A will inform all the gap session time to Gap Manager. */
+ kal_uint8 MeasTid; /** Indicate the measurement tid for standby meas module. */
+ kal_uint8 HpsTid; /** Indicate the Hps tid for standby meas module. */
+ kal_uint8 TickBitmap; /** Bit0 - Tmrasure, Bit1 - Thps. */
+ kal_bool is_conn_gap; /* indicate whether is LTE connect normal gap */
+} EvStandbyLl1aGapNotifyIndMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ EvStandbyLl1aGapNotifyIndMsgT msg;
+} evstandby_ll1a_gap_notify_ind_msg_struct;
+
+
+/** The EvStandby' Measure done Ind Structure. */
+typedef struct
+{
+ kal_uint8 Tid; /** Indicate the measure done tid to which gap pattern period sent before.*/
+ kal_uint8 TickBitmap; /** Bit0 - TICK_BITMAP_MPSR, Bit1 - TICK_BITMAP_HPS, Bit2 - TICK_BITMAP_LPS, Bit3 - TICK_BITMAP_RES. */
+ kal_uint8 cell_list_status_bitmap; /* cell_list_status_bitmap - bit 0 is set to 1, if no cell found in cell list */
+} Ll1aEvStandbyMeasDoneIndMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aEvStandbyMeasDoneIndMsgT msg;
+} Ll1aEvStandbyMeasDoneIndMsgT_HDR;
+
+/** The EvStandby Auto-Gap Cnf Structure. */
+typedef struct
+{
+ kal_bool Success; /** Indicate the auto-gap requeset for EvStandby is success or fail. */
+ kal_int32 ValidPeriod; /** The valid auto-gap period from LL1, in usc unit. */
+ kal_uint32 AutoTime; /** Return the AutoTime to GM.*/
+} EvStandbyLl1aAutoGapCnfMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ EvStandbyLl1aAutoGapCnfMsgT msg;
+} evstandby_ll1a_auto_gap_cnf_msg_struct;
+
+typedef struct
+{
+ Ll1aActiveGapPatternTypeT ActiveGap;
+ kal_uint32 GapStartTime;
+ kal_uint32 GapLen;
+}Ll1aGapPatternIndMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aGapPatternIndMsgT msg;
+}Ll1aGapPatternMsgT_HDR;
+
+typedef struct
+{
+ kal_bool Enable; /** Indicate RMC GM needs specific gap length for standby ICS.*/
+ kal_uint16 GapLen; /** The needed specific gap length, in ms unit.*/
+} EvStandbyLl1aSpecificGapRegMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ EvStandbyLl1aSpecificGapRegMsgT msg;
+}EvStandbyLl1aSpecificGapRegMsgT_HDR;
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aHscGapPatternOfferReq
+
+ DESCRIPTION: This is used by EvSpage to call when gap offer enable flag is set
+
+ PARAMETERS: IsDrxCycle -- Indicate whether the gap is in a new DRX cycle
+ StartTime -- The Idle Gap Start Time in 32Kcnt
+ GapLen -- The Idle Gap length in 32Kcnt
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Ll1aHscGapPatternOfferReq(Ll1aActiveGapPatternTypeT GapType, kal_bool IsDrxCycle, kal_uint32 StartTime, kal_uint32 GapLen);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aHscProcMmoGapPatternOfferReq
+
+ DESCRIPTION: This is used by LL1A to process the MMO gap offer to MLL1
+
+ PARAMETERS: MsgPtr -- The message pointer for MMO gap received from frame handler
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Ll1aHscProcMmoGapPatternOfferReq(void *MsgPtr);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aHscProcGapStopReq
+
+ DESCRIPTION: This is used by EvSpage to call when EvSpage needs to perform early wakeup
+ and needs LL1A helps to stop standby rat's gap(if previously gap pattern is offered).
+ When this API is called, LL1A will send gap stop request to LL1 automatically
+ and wait for gap stop cnf from LL1.
+ PARAMETERS: void
+ RETURNED VALUES:
+*****************************************************************************/
+extern kal_bool Ll1aHscProcGapStopReq(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscProcLl1aMsg
+
+ DESCRIPTION: This is the LL1A message process function entry in HSC task.
+ PARAMETERS: *MsgDataP - Message Data Pointer
+ MsgId - The defined message id
+ MsgSize - The message size
+ RETURNED VALUES: TRUE - Processed
+*****************************************************************************/
+extern kal_bool HscProcLl1aMsg(void *MsgDataP, kal_uint32 MsgId, kal_uint32 MsgSize);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aModeStatusGet
+
+ DESCRIPTION: The API provide by LL1A to get the RMC Mode Status
+ PARAMETERS: void
+
+ RETURNED VALUES: RmcModeStatusT
+
+*****************************************************************************/
+extern RmcModeStatusT Ll1aModeStatusGet(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aModeStatusSet
+
+ DESCRIPTION: The API provide by LL1A to set the RMC Mode Status
+ PARAMETERS: RmcModeStatus
+
+ RETURNED VALUES: void
+
+*****************************************************************************/
+extern void Ll1aModeStatusSet(RmcModeStatusT RmcModeStatus);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aDrxCycleLenGet
+
+ DESCRIPTION: The API provide by LL1A to get the RMC DRX cycle length
+ PARAMETERS: void
+
+ RETURNED VALUES: uint16
+
+*****************************************************************************/
+extern kal_uint16 Ll1aDrxCycleLenGet(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aDrxCycleLenSet
+
+ DESCRIPTION: The API provide by LL1A to set the RMC DRX cycle length
+ PARAMETERS: uint16
+
+ RETURNED VALUES: void
+
+*****************************************************************************/
+extern void Ll1aDrxCycleLenSet(kal_uint16 DrxCycleLen);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aRatStateGet
+
+ DESCRIPTION: The API provide by LL1A to get the sLl1aScheInfo.RatState
+ PARAMETERS: void
+
+ RETURNED VALUES: bool
+
+*****************************************************************************/
+extern Ll1aStateTypeT Ll1aRatStateGet(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aRatStateSet
+
+ DESCRIPTION: The API provide by LL1A to set the sLl1aScheInfo.RsvasSuspend
+ PARAMETERS: bool
+
+ RETURNED VALUES: void
+
+*****************************************************************************/
+extern void Ll1aRatStateSet(Ll1aStateTypeT RatState);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aInit
+
+ DESCRIPTION: The LL1A Initialise function
+
+ PARAMETERS:
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Ll1aInit(void);
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aInitForVzwMmo
+
+ DESCRIPTION: The LL1A Initialise function
+
+ PARAMETERS:
+
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Ll1aInitForVzwMmo(void);
+
+#ifdef C2K_LL1_STUB_TARGET_SUPPORT
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aEvStandbySetLTEInfo
+
+ DESCRIPTION: EvStandby use this API to set the LTE's info
+ Pattern.
+ PARAMETERS:
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Ll1aEvStandbySetLTEInfo(void *MsgDataP);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aEvStandbySetGapLengthInfo
+
+ DESCRIPTION: EvStandby use this API to set the LTE's gap length info from script
+ Pattern.
+ PARAMETERS:
+ RETURNED VALUES:
+*****************************************************************************/
+extern void Ll1aEvStandbySetGapLengthInfo(void *MsgDataP);
+
+#endif
+
+extern L1dModeStatusT Ll1aL1dModeStatusGet(void);
+extern void Ll1aL1dModeStatusSet(L1dModeStatusT L1dModeStatus);
+
+
+extern RmcRatStatusT Ll1aRmcRatStatusGet(void);
+extern void Ll1aRmcRatStatusSet(RmcRatStatusT RmcRatStatus);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aDoStandbyMeasTickBitmapGet
+
+ DESCRIPTION: The API provide by LL1A to get the sLl1aMeasTickBitmap
+ PARAMETERS: void
+
+ RETURNED VALUES: bool
+
+*****************************************************************************/
+extern kal_uint8 Ll1aDoStandbyMeasTickBitmapGet(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aDoStandbyMeasTickBitmapSet
+
+ DESCRIPTION: The API provide by LL1A to set the sLl1aMeasTickBitmap
+ PARAMETERS: bool
+
+ RETURNED VALUES: void
+
+*****************************************************************************/
+extern void Ll1aDoStandbyMeasTickBitmapSet(kal_uint8 MeasTickBitmap);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aDoStandbyMeasPurposeBitmapGet
+
+ DESCRIPTION: The API provide by LL1A to get the sLl1aMeasPurposeBitmap
+ PARAMETERS: void
+
+ RETURNED VALUES: bool
+
+*****************************************************************************/
+extern kal_uint8 Ll1aDoStandbyMeasPurposeBitmapGet(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: Ll1aDoStandbyMeasPurposeBitmapSet
+
+ DESCRIPTION: The API provide by LL1A to set the sLl1aMeasPurposeBitmap
+ PARAMETERS: bool
+
+ RETURNED VALUES: void
+
+*****************************************************************************/
+extern void Ll1aDoStandbyMeasPurposeBitmapSet(kal_uint8 MeasPurposeBitmap);
+
+
+#endif /** End of MTK_DEV_C2K_IRAT. */
+#endif
diff --git a/mcu/interface/l1/cl1/common/cl1tskll1adefs.h b/mcu/interface/l1/cl1/common/cl1tskll1adefs.h
new file mode 100644
index 0000000..653321f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tskll1adefs.h
@@ -0,0 +1,245 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1TSKLL1ADEFS_H_
+#define _CL1TSKLL1ADEFS_H_
+
+
+#ifdef MTK_DEV_93M_PREIT
+#include "kal_public_defs.h"
+#include "systyp.h"
+#include "valapi.h"
+
+
+/*****************************************************************************
+
+ FILE NAME: cl1tskll1adefs.h
+
+ DESCRIPTION:
+
+ This file contains the data type definition of LL1A module in 93m
+
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Definitions
+*----------------------------------------------------------------------------*/
+#define PNULL (void*)(0)
+
+#define TICK_BITMAP_LPS (0x01)
+#define TICK_BITMAP_HPS (0x02)
+#define TICK_BITMAP_RES (0x04)
+#define TICK_BITMAP_MPSR (0x08)
+
+#define LL1A_MEAS_PURPOSE_CELL_SEARCH (0x02)
+#define LL1A_MEAS_PURPOSE_MEASURE (0x01)
+
+#define C2K_SRLTE_LL1A_ON C2K_SRLTE_ON
+
+#ifndef MTK_PLT_ON_PC
+//#define MTK_DEV_93M_LL1A_BYPASS_ENABLE
+//#define C2K_LL1_STUB_TARGET_SUPPORT
+#endif
+
+
+
+
+
+
+/*----------------------------------------------------------------------------
+Macros Definition
+----------------------------------------------------------------------------*/
+
+
+
+
+
+
+
+
+
+
+/*----------------------------------------------------------------------------
+* Enums
+*----------------------------------------------------------------------------*/
+/** The EVDO's Rat Status Enum. */
+typedef enum
+{
+ RAT_FLIGHT,
+ RAT_STANDBY,
+ RAT_ACTIVE,
+ RAT_PSEUDO_FLIGHT,
+ RAT_PSEUDO_ACTIVE,
+ RAT_NULL
+}RmcRatStatusT;
+
+/** The LL1A's Internal State Definition. */
+typedef enum
+{
+ LL1A_FLIGHT,
+ LL1A_STANDBY,
+ LL1A_ACTIVE,
+ LL1A_RAT_MODE_INIT,
+ LL1A_SUSPEND
+}Ll1aStateTypeT;
+
+/** The EVDO's mode status enmu. */
+typedef enum
+{
+ RMC_MODE_BEGIN,
+ RMC_NULL_MODE,
+ RMC_IDLE_MODE,
+ RMC_CONNECT_MODE
+}RmcModeStatusT;
+
+/** The 1xRTT's mode status enmu. */
+typedef enum
+{
+ L1D_NON_DATA_CONNECTED_MODE,
+ L1D_DATA_CONNECTED_MODE
+}L1dModeStatusT;
+
+/** LL1A gap offered status.*/
+typedef enum
+{
+ GAP_NOT_OFFERED,
+ GAP_OFFERED,
+ WAIT_FOR_GAP_STOP_CNF
+}Ll1aGapOfferedStatusT;
+
+/** LL1A autogap available status.*/
+typedef enum
+{
+ AUTO_GAP_STATUS_UNKNOWN,
+ AUTO_GAP_STATUS_AVAIL,
+ AUTO_GAP_STATUS_UNAVAIL
+}Ll1aAutoGapAvailStatusT;
+
+/** LL1A autogap request state.*/
+typedef enum
+{
+ AUTO_GAP_NULL,
+ AUTO_GAP_REQ_PENDING,
+ AUTO_GAP_WAIT_RESULT,
+ AUTO_GAP_ACTIVE
+}Ll1aAutoGapReqStateT;
+
+/** LL1A Active Gap Pattern type.*/
+typedef enum
+{
+ ACTIVE_NULL_GAP,
+ ACTIVE_IDLE_GAP,
+ ACTIVE_MMO_GAP
+}Ll1aActiveGapPatternTypeT;
+
+typedef struct
+{
+ kal_uint32 RttGapLen; /* 1xRTT ps connect gap length for LTE MMO : unit ms */
+ kal_uint32 EvdoGapLen; /* EVDO connect gap length for LTE MMO : unit ms */
+ kal_bool RtbaMmoGapEnable; /* TRUE:LL1A have sent enable to RTBA; FALSE: LL1A have sent disable to RTBA */
+}Ll1aC2kConnGapT;
+
+/** L1d Mode Status Ind. */
+typedef struct
+{
+ L1dModeStatusT L1dModeStatus; /* Non_Data/Data. */
+}Ll1aL1dModeStatusIndMsgT;
+
+/** LL1A's internal parameters definiton.*/
+typedef struct
+{
+ Ll1aStateTypeT RatState; /** LL1A's internal RatState. */
+ RmcRatStatusT RmcRatStatus; /** LL1A record the rat status of EVDO.*/
+ RmcModeStatusT RmcModeStatus; /** RMC's Mode Status restored in LL1A. */
+ L1dModeStatusT L1dModeStatus; /** L1D's mode status recorded in LL1A */
+
+ Ll1aGapOfferedStatusT GapOfferedStatus; /** Indicate the gap offered status for evdo active. */
+ SysAirInterfaceT GapOfferedOwner; /** Indicate the gap offered owner for evdo or rtt active. */
+ Ll1aAutoGapAvailStatusT AutoGapAvailStatus; /** Indicate the auto-gap available information for evdo standby. */
+ Ll1aAutoGapReqStateT AutoGapReqState; /** Indicate the auto-gap request state for evdo standby. */
+ kal_uint8 GapIgnoreFlag; /** Indicate the whether needs to ignore the active gap pattern ind or standby gap notify ind.
+ Bit0 - Ignore the active gap pattern when set as 1; Bit1 - Ignore the standby gap notify when set as 1.*/
+ kal_bool GapServiceEnable; /** Indicate the gap service enable status. */
+ kal_uint8 GapStopSuspendEvent; /** To record the gap stop req and gap suspend req event.*/
+ kal_uint32 AutoGapStartTime; /** The GM need LL1A to return the auto time.*/
+ kal_uint16 DrxCycleLen; /** LL1A Needs to record the DrxCycle Length for evdo active idle mode.*/
+ kal_bool IsC2kOnSim2; /* to indicate EVDO in SIM1 or SIM2 */
+}Ll1aScheInfoT;
+
+//#ifdef C2K_LL1_STUB_TARGET_SUPPORT /* for NWSIM UT/IT build in elt_msg_struct.h */
+/** The 1xRTT's mode status enmu. */
+typedef enum
+{
+ LTE_ACTIVE_NULL,
+ LTE_ACTIVE_IDLE,
+ LTE_ACTIVE_CONNECT
+}Ll1aLteStubModeT;
+
+
+/* Ll1a stub definitaion for target standby */
+typedef struct
+{
+ Ll1aLteStubModeT LteMode; /* LTE active mode. */
+ kal_bool StopGapInGapRange; /* whether need LL1A send stop gap to EVL1 during gap range */
+}Ll1aLteActiveInfoT;
+
+/* Ll1a stub definitaion for target standby */
+typedef struct
+{
+ kal_uint32 NullGapLen; /* LTE active Null gap length, Max is 5000000, Uint:us . */
+ kal_uint32 IdleGapLen; /* LTE active Idle gap length, Max is 10000000, Uint:us . */
+ kal_uint32 ConnGapLen; /* LTE active Connect gap length, Max is 6000, Uint:us . */
+ kal_uint32 AutoGapLen; /* LL1A send auto gap stop with this length when has offer auto gap to EVL1,Max is 600000 Uint:us . */
+}Ll1aStandbyGapLenIndT;
+
+
+/* Ll1a stub definitaion for target standby */
+typedef struct
+{
+ Ll1aLteActiveInfoT LteActiveInfo; /* LTE active info. */
+ kal_uint16 NormalGapCnt; /* to record how many gaps have sent to EVL1 */
+ kal_uint16 AutoGapCnt; /* to record how many gaps have sent to EVL1 */
+ Ll1aStandbyGapLenIndT GapLength; /* to record gap length from script indication */
+}Ll1aStubInfoT;
+
+
+//#endif
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+#endif
diff --git a/mcu/interface/l1/cl1/common/cl1tst_em_evl1.h b/mcu/interface/l1/cl1/common/cl1tst_em_evl1.h
new file mode 100644
index 0000000..a966719
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tst_em_evl1.h
@@ -0,0 +1,120 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSKAL_TRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1TST_EM_EVL1_H_
+#define _CL1TST_EM_EVL1_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1tst_em_evl1.h.
+*
+* DESCRIPTION : evl1 EM design Msgid and funtion declaration
+*
+*
+************************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#ifndef MTK_DEV_93M_C2K_L1_UT
+#ifdef __MODEM_EM_MODE__
+#define __EVL1_EM_MODE__
+#include "em_public_struct_evl1.h"
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+typedef struct
+{
+ em_info_enum em_info;
+ em_evl1_cell_switch_info_struct Msg;
+} em_evl1_cell_switch_info_temp_struct;
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+/* EM_ID Switch for EVL1 */
+#define EVL1_EM_ID_NUM (EM_EVL1_INFO_END - EM_EVL1_INFO_BEGIN + 1)
+extern kal_bool evl1_em_on_s[EVL1_EM_ID_NUM] ;
+extern kal_uint8 TxAcEmFrameNum ;
+extern em_evl1_acc_data_rate_info_struct TxAcEvl1EmMsg;
+
+
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+void Evl1EmUpdateReqMsg(local_para_struct *local_para_ptr);
+void EvlSendEmProcGeneralInfoInd(em_evl1_general_info_struct *EmMsgPtr);
+void Evl1SendEmProcTxagcPwrInfoInd(void);
+void Evl1SendEmProcCellSwitchInfoInd(void);
+void Evl1SendEmProcRxagcInfoInd(void);
+void Evl1SendEmProcAfcInfoInd(void);
+void Evl1SendEmProcMbpSectorInfoInd(void);
+void Evl1SendEmProcFmpFingerInfoInd(void);
+void Evl1SendEmProcFmpSectorInfoInd(void);
+void Evl1SendEmProcTimingTrackStatusInd(void);
+void Evl1SendEmProcSchStatusInd(void);
+void Evl1SendEmProcSchPilotUpdateInfoInd(void);
+void Evl1SendEmProcSchResultInfoInd(void);
+void Evl1SendEmProcAccDataRateInfoInd(void);
+void Evl1SendEmProcTrafficRriValueInfoInd(void);
+void Evl1SendEmTxAgcPwrMsgToCl1tst(void *EmPwrP, kal_uint16 EmRepCtrl);
+void Evl1SendEmTimingTrackStatusMsgToCl1tst(kal_int16 EmStAdjDir);
+void Evl1EmGeneralInfoCollectAndReport(void);
+void Evl1SendEmTxAccDataRateMsgToCl1tst(kal_uint16 EmTxAcDataRate);
+void Evl1SendEmTxTrafficRriInfoMsgToCl1tst(kal_uint16 EmTxRriDataAck, kal_uint16 EmTxRriDataNak, kal_uint16 EmSubtype);
+void Evl1EmGeneralInfoUpdateSet(void);
+#ifdef __TC10_IPC_CDMA_SUPPORT__
+void Evl1SendEmProcRfPdInfoInd(void);
+#endif
+
+#endif
+#endif
+#endif
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
+
+
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstcommon.h b/mcu/interface/l1/cl1/common/cl1tstcommon.h
new file mode 100644
index 0000000..a97e13a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstcommon.h
@@ -0,0 +1,131 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tstcommon.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the log IQ functions.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+*
+*
+*
+*
+*
+*
+*
+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_COMMON_H_
+#define _CL1TST_COMMON_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "sysapi.h"
+
+/** FhcStatusE.
+ * Indicates the FHC status.
+ */
+typedef enum
+{
+ FHC_STATUS_STOP, /** Stop */
+ FHC_STATUS_RUNING /** Running */
+} FhcStatusE;
+
+/** define DPD status */
+typedef enum
+{
+ CL1TST_DPD_STATUS_STOP, /** Stop */
+ CL1TST_DPD_STATUS_RUNING /** Running */
+} Cl1TstDpdStatusE;
+
+/** define Delay cal status */
+typedef enum
+{
+ CL1TST_DLY_STATUS_STOP, /** Stop */
+ CL1TST_DLY_STATUS_RUNING /** Running */
+} Cl1TstDlyStatusE;
+
+/*----------------------------------------------------------------------------
+ global fucction
+----------------------------------------------------------------------------*/
+extern kal_bool Cl1FhcStatusCheck(FhcStatusE Status);
+extern kal_bool Cl1TstDpdStatusCheck(Cl1TstDpdStatusE Status);
+extern kal_bool Cl1TstDlyStatusCheck(Cl1TstDlyStatusE Status);
+extern void Cl1TstDpdInit(void);
+extern void Cl1TstDlyInit(void);
+extern void Cl1TstCalInit(kal_uint8 RfMode);
+extern void Cl1TstCalDeInit(kal_uint8 RfMode);
+
+extern void Cl1TstTxOnTimeCalc(SysSFrameTimeT * SFramePtr);
+extern kal_uint8 Cl1TstRfModeCalc(kal_uint8 RfMode, kal_uint8 DbgInfo);
+extern void Cl1TstCfgTimeCalc(SysSFrameTimeT * SFramePtr);
+
+extern void Cl1TstXl1TxhOn(void);
+extern void Cl1TstXl1TxhOff(void);
+extern void Cl1TstEvl1TxhOn(void);
+extern void Cl1TstEvl1TxhOff(void);
+
+extern void Cl1TstDpdFacIsr(void);
+extern void Cl1TstDlyLabIsr(void);
+extern void Cl1FhcMain(void);
+
+#endif /* _CL1TST_DPD_COM_H_ */
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstdlysrch.h b/mcu/interface/l1/cl1/common/cl1tstdlysrch.h
new file mode 100644
index 0000000..2ea55f4
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstdlysrch.h
@@ -0,0 +1,151 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygene header ********************************************************//**
+ *
+ * @file cl1tstdlysrch.h
+ * @{
+ *//***************************************************************************/
+
+#ifndef __CL1TSTDLYSRCH_H__
+#define __CL1TSTDLYSRCH_H__
+
+/*******************************************************************************
+* Includes
+*******************************************************************************/
+
+/*******************************************************************************
+* Defines
+*******************************************************************************/
+
+/*******************************************************************************
+* Enums
+*******************************************************************************/
+
+/*******************************************************************************
+* Structures
+*******************************************************************************/
+
+/*******************************************************************************
+* Interface Prototypes
+*******************************************************************************/
+
+extern kal_uint16 Cl1TstDpdPathDlyMain(void);
+
+#define CL1TST_DLY_SRCH_HSLOT_CNT 32
+
+#define CL1TST_REF_DFE_DLY_TR_MIN 0 /* HW limitation. */
+#define CL1TST_REF_DFE_DLY_TR_MAX 94 /* HW limitation. */
+
+#define CL1TST_CORR_LEFT_SHIFT_BIT_FOR_SIGN_BIT 4
+#define CL1TST_CORR_ABS_RIGHT_SHIFT_BIT 8
+#define CL1TST_NUM_TR_VALUE_DECIMAL_POINT 8
+
+#define CL1TST_PROTECTION_SF_CNT_NUM 1200
+
+#define CL1TST_DPD_DLY_SRCH_RANGE 5
+
+#define CL1TST_GD_MEAS_SAMPLE 1700
+#define CL1TST_GD_WAIT_SAMPLE 64
+#define CL1TST_GD_SHIFT 3
+
+/** define Delay search status */
+typedef enum
+{
+
+ CL1TST_DLY_SRCH_FSM_BB_ENABLE,
+ CL1TST_DLY_SRCH_FSM_TXON_TPC,
+
+ CL1TST_DLY_SRCH_FSM_WAIT_INIT,
+
+ CL1TST_DLY_SRCH_FSM_FIRST_TRIG,
+ CL1TST_DLY_SRCH_FSM_SWEEP_DLY,
+
+ CL1TST_DLY_SRCH_FSM_TXOFF,
+ CL1TST_DLY_SRCH_FSM_BB_DISABLE,
+
+ CL1TST_DLY_SRCH_FSM_DO_TXH_INIT,
+
+ CL1TST_DLY_SRCH_FSM_INVALID,
+ CL1TST_DLY_SRCH_FSM_NUM
+} Cl1TstDlyStateE;
+
+typedef struct
+{
+ kal_uint8 BandClass;
+ kal_uint16 ChanNum;
+} Cl1TstDlyFreqInfoT;
+
+typedef struct
+{
+ /* DPD delay search start request */
+ CRfTestCmd_StartDpdPathDelaySearch_ReqInfo StartInfo;
+
+ kal_bool DlySrchFlag;
+ kal_bool TimeOutFlag;
+ kal_bool SrchFailFlag;
+ Cl1TstDlyStateE DlyState;
+
+ Cl1TstDlyStatusE DlyStatus;
+
+ kal_int16 BbEnCnt;
+ kal_int16 TxOnCnt;
+ kal_int16 TxOffCnt;
+ kal_int16 TxSthCnt;
+
+ Cl1TstDlyFreqInfoT FreqInfo;
+
+ kal_int16 TrValue;
+ kal_int16 TrIniValue;
+ kal_int16 TrEndValue;
+ kal_int16 TrOptValue;
+
+ kal_uint32 AccumTr;
+ kal_uint32 CorrOpt;
+ kal_uint32 CorrMin;
+
+ kal_uint16 HSlotCnt;
+} Cl1DlyDataT;
+
+#endif /* #ifndef __LDPDCALDLYMAIN_H__ */
+
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstdpd.h b/mcu/interface/l1/cl1/common/cl1tstdpd.h
new file mode 100644
index 0000000..c710f48
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstdpd.h
@@ -0,0 +1,276 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tstdpd.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the log IQ functions.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+*
+ * removed!
+ * removed!
+*
+*
+*
+*
+*
+*
+*
+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_DPD_H_
+#define _CL1TST_DPD_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "sysapi.h"
+
+#define CL1TST_DPD_RETRY_LIMIT 3
+#define CL1TST_DPD_REF_TEMP_INDEX 4
+#define CL1TST_DPD_FACTORY_DIFF 12
+
+/** define DPD state */
+typedef enum
+{
+ CL1TST_DPD_FSM_IDLE = 0,
+ CL1TST_DPD_FSM_TX_ON_TPC = 1,
+ CL1TST_DPD_FSM_TPC = 2,
+ CL1TST_DPD_FSM_TX_OFF = 3,
+ CL1TST_DPD_FSM_GAIN_QUERY = 4,
+ CL1TST_DPD_FSM_TX_OFF_WAIT = 5,
+ CL1TST_DPD_FSM_NUM
+} Cl1TstDpdStateE;
+
+/* 8-level PA dc2dc for DPD calibration */
+typedef enum
+{
+ CL1TST_DPD_PA_IDX0 = 0,
+ CL1TST_DPD_PA_IDX1 = 1,
+ CL1TST_DPD_PA_IDX2 = 2,
+ CL1TST_DPD_PA_IDX3 = 3,
+ CL1TST_DPD_PA_IDX4 = 4,
+ CL1TST_DPD_PA_IDX5 = 5,
+ CL1TST_DPD_PA_IDX6 = 6,
+ CL1TST_DPD_PA_IDX7 = 7,
+ CL1TST_DPD_PA_NULL = 0x7f
+} Cl1TstDpdPaIdxE;
+
+/* PA level-7 index */
+typedef enum
+{
+ CL1TST_DPD_L7_IDX0 = 0,
+ CL1TST_DPD_L7_IDX1 = 1,
+ CL1TST_DPD_L7_NULL = 0x7f
+} Cl1TstDpdL7IdxE;
+
+/* define System time structure */
+typedef struct Cl1DpdSysTimeTag
+{
+ /* Slot number */
+ kal_uint8 Slot;
+
+ /* half slot boundary system time */
+ kal_uint32 Time;
+} Cl1DpdSysTimeT;
+
+/* define target time structure */
+typedef struct Cl1DpdTargetTimeTag
+{
+ /* Slot number */
+ kal_uint64 SupFram;
+
+ /* system time */
+ kal_uint32 SysTime;
+} Cl1DpdTargetTimeT;
+
+typedef struct
+{
+ kal_uint8 BandClass;
+ kal_uint16 ChanNum;
+} Cl1TstDpdFreqParaT;
+
+/** This structure is updated by Algo driver */
+typedef struct Cl1TstDpdAlgoUpdParaTag
+{
+ /** PA table index */
+ kal_uint8 PaTbIdx;
+
+ /** 0: the first level 7
+ 1: the second level level 7 */
+ kal_uint8 PaL7Idx;
+
+ /** target power */
+ kal_int16 Peak;
+
+ /** PA gain (include compensation) */
+ kal_int16 PaGain;
+
+} Cl1TstDpdAlgoUpdParaT;
+
+/** This structure is updated by RF driver */
+typedef struct Cl1TstDpdRfdUpdParaTag
+{
+ /** target power */
+ kal_int16 Prf;
+
+ /** PA gain (include compensation) */
+ kal_int16 PaGain;
+
+ /** PA gain compensation */
+ kal_int16 PaGainComp;
+
+ /** Coupler loss (include compensation) */
+ kal_int16 CouplerLoss;
+
+} Cl1TstDpdRfdUpdParaT;
+
+/** This structure is used to store UPC HW information in EVDO and 1xRTT mode. */
+typedef struct Cl1TstDpdUpcInfoTag
+{
+ /** PGA gain */
+ kal_int16 PgaGain;
+
+ /** DET path PGA gain */
+ kal_int16 DetGain;
+
+ /** BB gain */
+ kal_int16 BbGain;
+} Cl1TstDpdUpcInfoT;
+
+/** This structure is used to store Fail Info. */
+typedef struct Cl1TstDpdFailInfoTag
+{
+ kal_uint8 Status;
+
+ /** Fail Rat */
+ kal_uint8 CurRfMode;
+
+ /** Fail band class */
+ kal_uint8 CurBandClass;
+
+ /** Fail channel number */
+ kal_uint16 CurChanNum;
+
+ /** Fail PA index */
+ kal_uint16 CurPaIdx;
+
+ /** Fail PA Gain */
+ kal_int16 CurPaGain;
+} Cl1TstDpdFailInfoT;
+
+typedef struct
+{
+ CRfTestCmd_StartDpd_ReqInfo StartInfo;
+ Cl1TstTxDpdStartPduT StartPdu[CL1D_RF_BAND_CLASS_MAX];
+
+ Cl1TstDpdStatusE DpdStatus;
+
+ Cl1TstDpdStateE DpdState;
+
+ Cl1DpdSysTimeT SysTime;
+
+ SysSFrameTimeT TarTime;
+
+ Cl1TstDpdFreqParaT FreqPara;
+
+ Cl1TstDpdAlgoUpdParaT AlgoUpdPara;
+
+ Cl1TstDpdRfdUpdParaT RfdUpdPara;
+
+ Cl1TstDpdUpcInfoT UpcInfo;
+
+ MMDPD_FAC_PGA_PARAM_T *p_target_pga_table;
+
+ /* The parameters for FXP and PA calibration result pointer */
+ DPD_FXP_PARAM FxpPara;
+
+ /* To restore the calibrated PA gain result temperarily */
+ kal_int16 PaGain[CL1TST_DPD_FREQ_NUM][CL1TST_DPD_PA_NUM];
+
+ Cl1TstDpdFailInfoT FailInfo;
+
+ kal_int16 TrValue;
+ kal_uint8 QueryCnt;
+ kal_uint8 TxOnFlag;
+ kal_uint8 TxOffCnt;
+
+ kal_uint8 query;
+
+ kal_bool rf_tx_fec_wakeup_flag;
+
+ kal_uint8 fxp_retry_count;
+
+ kal_uint16 WaitSmples;
+ kal_uint16 DpdThUpper;
+ kal_uint16 TestMode;
+ kal_uint16 InitMode;
+ kal_uint16 TestCnt3;
+ kal_uint32 HSlotCnt;
+
+} Cl1DpdDataT;
+
+/*----------------------------------------------------------------------------
+ global fucction
+----------------------------------------------------------------------------*/
+extern void Cl1TstDpdFacMain(void);
+
+#endif /* _CL1TST_DPD_H_ */
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstdpdif.h b/mcu/interface/l1/cl1/common/cl1tstdpdif.h
new file mode 100644
index 0000000..d919fee
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstdpdif.h
@@ -0,0 +1,291 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tstdpdif.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the log IQ functions.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+*
+*
+*
+*
+*
+*
+*
+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_DPD_IF_H_
+#define _CL1TST_DPD_IF_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "cl1_rf_public.h"
+
+#define CL1TST_DPD_FREQ_NUM 16
+#define CL1TST_DPD_PA_NUM 8
+#define CL1TST_DPD_BAND_MAX 22
+
+#define CL1TST_DPD_CHAN_INVALID 65535
+
+typedef enum
+{
+ CL1TST_DPD_CMD_STATUS_INVALID = 0,
+ CL1TST_DPD_CMD_STATUS_SUCCESS = 1,
+ CL1TST_DPD_CMD_STATUS_FAILURE = 2,
+ CL1TST_DPD_CMD_STATUS_PDU_SIZE_ERR = 3,
+ CL1TST_DPD_CMD_STATUS_PARAM_ERR = 4
+}Cl1TstDpdFacCmdStatusE;
+
+typedef enum
+{
+ CL1TST_DLY_SRCH_CMD_STATUS_INVALID = 0,
+ CL1TST_DLY_SRCH_CMD_STATUS_SUCCESS = 1,
+ CL1TST_DLY_SRCH_CMD_STATUS_TIMEOUT = 2,
+ CL1TST_DLY_SRCH_CMD_STATUS_SRCH_FAIL = 3
+} Cl1TstDlySrchCmdStatusE;
+
+//======= DPD Fac setting (all)/ getting PDU =========/
+
+/** define Tx DPD calibration data (all) structure */
+typedef struct
+{
+ /* PA context */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_CONTEXT_XX_BAND_X_LID */
+ CL1D_RF_TX_DPD_PA_CONTEXT_T TxDpdPaCtx;
+
+ /* PA gain temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_GAIN_COMP_XX_BAND_X_LID */
+ CL1D_RF_TX_DPD_PA_GAIN_COMP_T TxDpdPaComp;
+
+ /* Coupler loss temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_COMP_XX_BAND_X_LID */
+ CL1D_RF_TX_DPD_AM_PM_LUT_DATA_T TxDpdAmPmLut;
+
+} Cl1TstTxDpdCalAllPduT;
+
+//======= DPD Fac setting (part) PDU===================/
+
+/** define Tx DPD calibration data (partial) structure */
+typedef struct
+{
+ /* PA context */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_CONTEXT_XX_BAND_X_LID */
+ CL1D_RF_TX_DPD_PA_CONTEXT_T TxDpdPaCtx;
+
+ /* PA gain temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_GAIN_COMP_XX_BAND_X_LID */
+ CL1D_RF_TX_DPD_PA_GAIN_COMP_T TxDpdPaComp;
+
+} Cl1TstTxDpdCalPartPduT;
+
+//======= DPD Fac start==============================/
+typedef struct
+{
+ kal_uint16 AptRefChan;
+ kal_int16 tpc_wanted_p_offset;
+}Cl1TstTxDpdStartPduT;
+
+/* DPD factory start request */
+typedef struct
+{
+ /* Current temperature index */
+ kal_uint8 TempIdx;
+
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Band number */
+ kal_uint8 BandNum;
+
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_StartDpd_ReqInfo;
+
+/* DPD factory start confirm */
+typedef struct
+{
+ kal_uint8 BandNum;
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+ kal_uint8 Status;
+ kal_uint8 CurBandClass;
+ kal_uint16 CurChanNum;
+ kal_uint16 CurPaIdx;
+ kal_uint16 CurPaGain;
+
+}CRfTestCmd_StartDpd_CnfInfo;
+
+//======= DPD Fac setting==============/
+
+/* DPD factory data setting request */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNv;
+
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Band number */
+ kal_uint8 BandNum;
+
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+
+}CRfTestCmd_SetDpdAll_ReqInfo;
+
+/* DPD factory data setting confirm */
+typedef struct
+{
+ kal_uint8 BandNum;
+ kal_uint8 SetStatus;
+}CRfTestCmd_SetDpdAll_CnfInfo;
+
+//======= DPD Fac getting==============/
+
+/* DPD factory data getting request */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ kal_uint8 BandNum;
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_GetDpdAll_ReqInfo;
+
+/* DPD factory data getting confirm */
+typedef struct
+{
+ kal_uint8 BandNum;
+ kal_uint8 GetStatus;
+}CRfTestCmd_GetDpdAll_CnfInfo;
+
+/***************************** Delay search ***************************/
+/* DPD delay search start request */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ kal_uint8 SrchTimes;
+ kal_uint8 BandNum;
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_StartDpdPathDelaySearch_ReqInfo;
+
+//======= Delay search setting==============/
+
+/* DPD delay search data setting request */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ kal_uint8 BandNum;
+
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_SetDpdPathDelaySearch_ReqInfo;
+
+/* DPD delay search data setting pdu (one band) */
+typedef struct
+{
+ kal_uint8 BandClass;
+ kal_uint16 ChanNum[CL1TST_DPD_FREQ_NUM];
+ kal_int16 DpdTr[CL1TST_DPD_FREQ_NUM];
+}Cl1TstDpdPathDlyPduT;
+
+/* DPD delay search data setting pdu */
+typedef struct
+{
+ Cl1TstDpdPathDlyPduT DlyReq[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_SetDpdPathDelaySearch_ReqPdu;
+
+/* DPD delay search data setting confirm */
+typedef struct
+{
+ kal_uint8 BandNum;
+ kal_uint8 SetStatus;
+}CRfTestCmd_SetDpdPathDelaySearch_CnfInfo;
+
+//======= Delay search getting==============/
+
+/* DPD delay search data getting request */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ kal_uint8 BandNum;
+ kal_uint8 BandClass[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_GetDpdPathDelaySearch_ReqInfo;
+
+/* DPD delay search data getting confirm */
+typedef struct
+{
+ kal_uint8 BandNum;
+ kal_uint8 GetStatus;
+}CRfTestCmd_GetDpdPathDelaySearch_CnfInfo;
+
+/* DPD delay search data getting pdu */
+typedef struct
+{
+ Cl1TstDpdPathDlyPduT DlyRsp[CL1TST_DPD_BAND_MAX];
+}CRfTestCmd_GetDpdPathDelaySearch_CnfPdu;
+
+#endif /* _CL1TST_DPD_IF_H_ */
+
diff --git a/mcu/interface/l1/cl1/common/cl1tsteltif.h b/mcu/interface/l1/cl1/common/cl1tsteltif.h
new file mode 100644
index 0000000..9026c0f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tsteltif.h
@@ -0,0 +1,878 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tsteltif.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the elt if functions declare.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
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+*
+*
+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_ELT_IF_H_
+#define _CL1TST_ELT_IF_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "cl1tstmetaif.h"
+
+/* RCP_ETS_TX_AVAILABLE_PWR_TEST_MODE_MSG*/
+typedef enum
+{
+ TXAGC_CTRL_TYPE_STOP = 0,
+ TXAGC_CTRL_TYPE_START = 1,
+ TXAGC_CTRL_TYPE_GET_TX_PWR = 2,
+ TXAGC_CTRL_TYPE_INVALID = 0xFF
+} RcpTstTxAgcCtrlTypeT;
+
+/** define the transmission signal type enumeration */
+typedef enum
+{
+ CL1TST_ELT_TX_SIG_TYPE_1X = 1,
+ CL1TST_ELT_TX_SIG_TYPE_DO_PILOT = 2,
+ CL1TST_ELT_TX_SIG_TYPE_DO_ST2 = 3,
+ CL1TST_ELT_TX_SIG_TYPE_DO_PHYUT = 4,
+ CL1TST_ELT_TX_SIG_TYPE_RF_TONE = 6,
+ CL1TST_ELT_TX_SIG_TYPE_BB_TONE = 7
+} Cl1TstEltTxSigTypeT;
+
+
+typedef enum
+{
+ CL1TST_NULL = 0,
+ CL1TST_OVERHEADMESSAGE_TEST = 1,
+ CL1TST_FTCCRC_TEST = 2,
+ CL1TST_PHY_UT_TEST = 3,
+ CL1TST_FTCCRC_SINGLE_TEST = 4,
+ CL1TST_FCCCRC_TEST = 5
+} Cl1TstCfgTypeT;
+
+typedef enum
+{
+ CL1TST_SUCCESSFULL = 0,
+ CL1TST_FAIL = 1
+} Cl1TstRspResultT;
+
+/** define the Pwr mode enumeration (Or APT, DPD) */
+typedef enum
+{
+ CL1TST_PWR_MODE_ETM,
+ CL1TST_PWR_MODE_APT,
+ CL1TST_PWR_MODE_DPD
+} Cl1TstPwrModeT;
+
+typedef struct
+{
+ kal_uint16 FtcPerStatic;
+ kal_uint16 FccPerStatic;
+ kal_uint32 FtcTotalFwdPacketsCount;
+ kal_uint32 FtcTotalFwdGoodPacketsCount;
+ kal_uint32 FccTotalFwdPacketsCount;
+ kal_uint8 PreambleMacId;
+ kal_uint8 DrcIndex;
+ kal_uint32 RspFramConut;
+}Cl1TstRspInfoT;
+
+
+/** define RF transmitter control command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: OFF, 1: ON */
+ kal_uint8 Action;
+
+ /* 0: TXDFE RF tone for 1xRTT and EVDO
+ 1: TXDFE BB signal tone for 1xRTT and EVDO
+ 2: reverse 1xRTT signal for 1xRTT
+ 3: reverse EVDO pilot only for EVDO
+ 4: reverse EVDO subtype2 for EVDO */
+ kal_uint8 SigType;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Channel Number to turn on*/
+ kal_uint16 ChannelNum;
+
+ /* Power reference used for open loop estimation in 1/64dBm@S9.6 unit.*/
+ kal_int16 PwrRef;
+
+ /* Frequency offset for RF tone transmission */
+ kal_uint32 FreqOffset;
+
+ /* BB tone configuration parameters */
+ kal_uint32 BbToneCfg;
+
+ Cl1Tst1xSigParaT RttSigPara;
+
+ /* total frequency offset error in Hz*/
+ kal_int32 FoeHz;
+
+ /* Open loop correct gain with S0.16 unit*/
+ kal_int32 OlCorrGain;
+
+ /* Open loop max slew with S2.6 unit*/
+ kal_int32 OlMaxSlew;
+
+ /* RPC combine with U5.0*/
+ kal_uint16 RpcCombThr;
+
+ /* RSSI value with filter in 1/64dBm@S7.6 unit.*/
+ kal_int16 RssiWiFilter;
+
+ /* TXAGC SW mode control
+ bit[7:0]: rpc_bit_src_sel, 1: sw mode, 0: normal mode
+ bit[15:8]: ks_value_src_sel, 1: sw mode, 0: normal mode
+ bit[23:16]: rpc_sym_pos_sel, 1: sw mode, 0: normal mode
+ */
+ kal_uint32 TxAgcSwMode;
+
+ /* Tx Agc control flag */
+ kal_uint8 TxAgcFlag;
+
+ /* TX AGC control type,
+ 0: stop sw txagc,
+ 1: start sw txagc */
+ kal_uint8 CtrlType;
+
+ /* Access/ Traffic channel */
+ kal_uint8 ChanType;
+
+ /* PHY subtype */
+ kal_uint8 PhySubType;
+
+ /* Power reference used for open loop estimation in 1/64dBm@S9.6 unit.*/
+ kal_int16 PowerBase; /* Q6 dB */
+
+ /* Bit0: trans ind TRUE/FALSE,
+ Bit4: Close loop parameters enable/disable */
+ kal_uint16 TestBmp;
+
+ /* close loop step up size in 1/64dB@S2.6 unit */
+ kal_int16 ClStepUp;
+
+ /* close loop step down size in 1/64dB@S2.6 unit */
+ kal_int16 ClStepDown;
+
+ /* close loop adjustment limited in 1/64dB@S8.6 unit */
+ kal_int16 ClAdjMax;
+
+ /* close loop adjustment limited in 1/64dB@S8.6 unit */
+ kal_int16 ClAdjMin;
+
+ /* maximum transmit power adjustment in 1/64dB@S5.6 unit, set zero
+ if not use it */
+ kal_int16 MaxPwrAdj;
+
+ /* KS value in SW mode with S6.6 unit*/
+ kal_uint16 PcgVldPat; //Indicate PCG valid pattern
+
+ /* RPC bit in SW mode with U2.0 unit*/
+ kal_uint16 RpcBitSw;
+
+ /* KS value in SW mode with S6.6 unit*/
+ kal_int16 KsValueSw;
+
+ /* Indicate RPC symbol position */
+ kal_uint16 RpcSymPosSw[16]; //1xRTT only
+
+ /* bitmap indicate RC configuration for 16 PCGs */
+ kal_uint16 RcCfgPat; // 1xRTT only, bitmap indicate RC configuration for 16 PCGs
+
+ kal_uint16 Reserved;
+
+} Cl1TstTransmitCtrlEltCmdT;
+
+typedef struct
+{
+ /*For EVDO*/
+ Cl1TstTransmitCtrlCmdT Msg;
+ kal_uint16 EvChannelType;
+ kal_uint16 EvProtocolSubtype;
+ kal_uint16 EvAuxPilotMiniPayload;
+ kal_uint16 EvDrcGating;
+ kal_uint16 EvDrcBoostLength;
+ kal_uint16 EvDscBoostLength;
+ kal_uint16 EvDrcLength;
+ kal_uint16 EvFrameOffset;
+ /*subype0:0,0,1:9.6K,2:19.2k,3:38.4k,4:76.8k, 5:153.6 */
+ kal_uint16 EvDataRate;
+ kal_uint16 EvDRCCover;
+ kal_uint16 EvDRCCover1;
+ kal_uint16 EvDRCCover2;
+ kal_uint16 EvDRCValue;
+ kal_uint16 EvDRCValue1;
+ kal_uint16 EvDSCValue;
+ kal_uint16 EvDSCValue1;
+ kal_uint16 EvDSCValue2;
+ kal_uint16 EvAckEnalble;
+ kal_uint16 EvAckUserType;
+ kal_uint16 EvAckBits;
+ kal_uint16 EvAckBits1;
+ kal_uint16 EvAckSuScale;
+ kal_uint16 EvAckMuScale;
+ kal_uint16 EvPreSlot;
+ kal_uint16 EvCapFrame;
+} Cl1TstTransmitCtrlCmdPhyUT;
+
+/** define temperature back off data structure */
+typedef struct
+{
+ kal_uint8 Band;
+ kal_int8 Temperature;
+ kal_int16 BackOff;
+} Cl1TstTempBackOffDataT;
+
+/** define temperature back off set command structure */
+typedef struct
+{
+ Cl1TstTempBackOffDataT BackOffData;
+} Cl1TstTempBackOffSetCmdT;
+
+/** define temperature back off set response structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTempBackOffSetRspT;
+
+/** define temperature back off get command structure */
+typedef struct
+{
+ /* band class */
+ kal_uint8 Band;
+ kal_uint8 Reserved1;
+ kal_uint16 Reserved2;
+} Cl1TstTempBackOffGetCmdT;
+
+/** define temperature back off get response structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Back off data */
+ Cl1TstTempBackOffDataT BackOffData;
+} Cl1TstTempBackOffGetRspT;
+
+typedef struct
+{
+ /* TX AGC control type,
+ 0: stop sw txagc,
+ 1: start sw txagc,
+ 2: obtain current request power */
+ kal_uint8 CtrlType;
+
+ /* Tx slot */
+ kal_uint8 TxSlot;
+
+ /* Access/ Traffic channel */
+ kal_uint8 ChanType;
+
+ /* PHY subtype */
+ kal_uint8 PhySubType;
+
+ /* Power reference used for open loop estimation in 1/64dBm@S9.6 unit.*/
+ kal_int16 PowerBase; /* Q6 dB */
+
+ /* Bit0: trans ind TRUE/FALSE,
+ Bit4: Close loop parameters enable/disable */
+ kal_uint16 TestBmp;
+
+ /* close loop step up size in 1/64dB@S2.6 unit */
+ kal_int16 ClStepUp;
+
+ /* close loop step down size in 1/64dB@S2.6 unit */
+ kal_int16 ClStepDown;
+
+ /* close loop adjustment limited in 1/64dB@S8.6 unit */
+ kal_int16 ClAdjMax;
+
+ /* close loop adjustment limited in 1/64dB@S8.6 unit */
+ kal_int16 ClAdjMin;
+
+ /* maximum transmit power adjustment in 1/64dB@S5.6 unit, set zero
+ if not use it */
+ kal_int16 MaxPwrAdj;
+
+ /* RPC bit in SW mode with U2.0 unit*/
+ kal_uint16 RpcBitSw; /* Q6 dB */
+
+ /* KS value in SW mode with S6.6 unit*/
+ kal_int16 KsValueSw; /* Q6 dB */
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} RcpTstTxAgcCtrlCmdT;
+
+/** define Tx AGC test ctrl message */
+typedef struct
+{
+ kal_uint16 CtrlType; //1: start TxAGC test, 0: Stop TxAGC test
+ kal_uint16 PcgVldPat; //Indicate PCG valid pattern
+ kal_uint16 RpcBitSw; //RPC bit in SW mode with U2.0 unit
+ kal_uint16 RpcSymPosSw[16]; //Indicate RPC symbol position
+ kal_int16 KsValueSw; //KS value in SW mode with S6.6 unit
+ kal_uint16 ClStepUp; //Step size of close loop adjustment for increment
+ kal_uint16 ClStepDown; //Step size of close loop adjustment for decrement
+ kal_uint16 GatePat; //GateOn/Off pattern
+ kal_int16 ClAdjMax; //Maximum close loop accumulation
+ kal_int16 ClAdjMin; //Minimum close loop accumulation
+ kal_int16 MaxPwrAdj; //Maximum power adjustment
+ kal_uint16 RcCfgPat; //RC configuration per slot basis
+ kal_uint16 TxAgcCfgSlot;//Indicate TxAGC configuration start Slot
+
+} L1dTstTxAgcCtrlCmdT;
+
+
+/** define Tx AGC test ctrl message response */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} L1dTstTxAgcCtrlRspT;
+
+typedef struct
+{
+ /* Preemption type:,
+ 0: stop preemption,
+ 1: start RTB/HSC preemption, */
+ kal_uint8 Preempt;
+} RcpTxSthRtbHscPreemptCtrlCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAntennaTestModeRspT;
+
+typedef struct
+{
+ kal_uint32 CfgData;
+} TxDfeBbToneCfgCmdT;
+
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} TxDfeBbToneCfgRspT;
+
+typedef struct
+{
+ kal_uint32 CfgData;
+} TxDfeBbNcoCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} TxDfeBbNcoCfgRspT;
+
+/** define SNR query command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+} Cl1TstRxSnrQueryCmdT;
+
+/** define SNR query confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Main antenna Rx Main Ant SNR, unit is Q5 dBm */
+ kal_uint16 RxMainAntSnr;
+
+ /* Diversity antenna Rx power, unit is Q5 dBm */
+ kal_uint16 RxDivAntSnr;
+
+} Cl1TstRxSnrQueryRspT;
+
+/** define Ec/Io query command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+} Cl1TstRxEcIoQueryCmdT;
+
+/** define Ec/Io query confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Main antenna Rx power, unit is Q5 dBm */
+ kal_int16 RxMainAntEcIo;
+
+ /* Diversity antenna Rx power, unit is Q5 dBm */
+ kal_int16 RxDivAntEcIo;
+
+} Cl1TstRxEcIoQueryRspT;
+
+/** define ICS SYNC command ELT msg */
+typedef struct
+{
+/*
+0: ics wo afc wo 1x
+1: ics wi afc wo 1x
+2: ics wo afc wi 1x
+3: ics wi afc wi 1x
+4: ics wo signal
+5: ics wi strong signal
+6: ics foe
+7: ics preempt
+0xf----->valid(no test )*/
+ kal_uint16 caseId ;
+ kal_uint16 Dummy ;
+
+} EltTstIcsTstCaseIdCfgT;
+
+typedef struct
+{
+ kal_bool RcpDbgEn; /* 1->RCP subchannel in Debug mode, 0->normal mode */
+ kal_bool RcpDbgVal;
+ kal_bool ArqDbgEn; /* 1->H/LARQ subchannel in Debug mode, 0->normal mode */
+ kal_bool ArqDbgVal;
+}EltTstMcdDebugMsgT;
+
+
+typedef struct
+{
+ SysCdmaBandT Band;
+ kal_uint16 Chan;
+ kal_uint8 TriggerSource; /* 0->IDP; 1->RUP */
+}EltRmcInterhoTstCfgT;
+
+typedef struct
+{
+ kal_uint16 ResePilotPN;
+}EltRmcIntrahoTstCfgT;
+
+
+typedef struct
+{
+ kal_uint8 DoSignalValidFlag;
+} EltTstStbDoSignalCfgT;
+
+
+typedef struct
+{
+ kal_uint8 RttTimingValid;
+ kal_uint8 DoTimingValid;
+} EltTstStbTimingCfgT;
+
+typedef struct
+{
+ kal_uint8 temp_type;
+} EltTstReadTempT;
+
+
+/** define temperature get response structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Get temperature*/
+ CL1D_RF_TEMPERATURE_QUERY_T Temperature;
+} Cl1TstReadTempRspT;
+
+typedef struct
+{
+ kal_uint8 State;
+ kal_uint8 DfsType;
+ kal_uint8 ChanIndex;
+} Cl1TstRmcDfsMeasDoneRspT;
+
+
+typedef struct
+{
+ kal_bool result;/* 1->Pass, 0->Fail */
+}EltC2kPhyUtTstRptT;
+
+typedef struct
+{
+ kal_bool CrcResult;/* 1->Pass, 0->Fail */
+ kal_uint8 PreambleMacId;
+ kal_uint8 DrcIndex;
+}EltC2kPhyUtRxCaseTstRptT;
+
+typedef struct
+{
+ kal_bool RESET_EN;
+ kal_bool EQ_MODE_L1_EN;
+ kal_uint32 EQ_MODE;
+ kal_bool MMSE_FLAG_L1_EN;
+ kal_uint32 MMSE_FLAG;
+ kal_bool ITER_NUM_L1_EN;
+ kal_uint32 ITER_NUM;
+ kal_bool ALPHA_FILTER_MODE_L1_EN;
+ kal_uint32 ALPHA_FILTER_MODE;
+ kal_bool DATA_FTM_L1_EN;
+ kal_uint32 DATA_FRAC;
+ kal_uint32 C2I_FRAC;
+ kal_bool PRE_COURSE_L1_EN;
+ kal_uint32 PRE_COURSE;
+ kal_bool CORR_LEN_L1_EN;
+ kal_uint32 CORR_LEN;
+ kal_bool ALPHA_SHIFT_L1_EN;
+ kal_uint32 ALPHA_SHIFT;
+ kal_bool WIN_ADD_BD_L1_EN;
+ kal_uint32 WIN_ADD_BD;
+ kal_bool PD_MATRIX_NOISE_L1_EN;
+ kal_uint32 PD_MATRIX_NOISE;
+}EltTstCuifCfgT;
+
+
+typedef struct
+{
+ Cl1TstCfgTypeT TestType;
+}EltTstCfgT;
+
+typedef struct
+{
+ Cl1TstCfgTypeT TestType;
+ Cl1TstRspResultT TestResult;
+ Cl1TstRspInfoT TestRspInfo;
+}EltTstRspT;
+
+typedef struct
+{
+ kal_uint8 IsStbOnlyMode;
+} EltTstStbOnlyModeCfgT;
+
+typedef struct
+{
+ SysAirInterfaceT Mode;
+ kal_uint32 Cl1RcdPwrCtrlPartialBypassConf;
+ kal_uint32 Cl1RcdClkCtrlPartialBypassConf;
+ kal_uint32 Cl1RcdSramCtrlPartialBypassConf;
+} Cl1RcdPartialBypassConfT;
+
+typedef struct
+{
+ CL1D_RF_TPC_SECTION_TABLE_T Table[C2K_MIPI_SUBBAND_NUM];
+} NvEditorMipiPaSectionDataTableT;
+
+/** define TPC MIPI codeword Setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* To update, 0:ETM, 1:APT, 2:DPD */
+ kal_uint8 PwrMode;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* TpcMipi*/
+ NvEditorMipiPaSectionDataTableT TpcMipi;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+} Cl1TstSetTpcMipiCwCmdT;
+
+/** define TPC MIPI codeword setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetTpcMipiCwRspT;
+
+/** define TPC MIPI codeword getting command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* To update, 0:ETM, 1:APT, 2:DPD */
+ kal_uint8 PwrMode;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstGetTpcMipiCwCmdT;
+
+/** define MIPI codeword getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* TPC MIPI data */
+ NvEditorMipiPaSectionDataTableT TpcMipi;
+} Cl1TstGetTpcMipiCwRspT;
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+extern void Cl1TstEltIfGetRfPlatInfo(Cl1TstGetRfPlatInfoCmdT *Ptr);
+extern void Cl1TstEltIfRfdTestModeReq(Cl1TstRfdTestModeReqCmdT *Ptr);
+extern void Cl1TstEltIfRfdInitReq(Cl1TstRfdInitReqCmdT *Ptr);
+extern void Cl1TstEltIfSetMipiCodeWord(Cl1TstSetMipiCodeWordCmdT *Ptr);
+extern void Cl1TstEltIfGetMipiCodeWord(Cl1TstGetMipiCodeWordCmdT *Ptr);
+extern void Cl1TstEltIfSetSpiData(Cl1TstSetSpiDataCmdT *Ptr);
+extern void Cl1TstEltIfGetSpiData(Cl1TstGetSpiDataCmdT *Ptr);
+extern void Cl1TstEltIfSetTpcMipiCodeWord(Cl1TstSetTpcMipiCwCmdT *Ptr);
+extern void Cl1TstEltIfGetTpcMipiCodeWord(Cl1TstGetTpcMipiCwCmdT *Ptr);
+extern void Cl1TstEltIfTransmitCtrl(Cl1TstTransmitCtrlEltCmdT *Ptr);
+extern void Cl1TstEltIfReceiveCtrl(Cl1TstReceiveCtrlCmdT *Ptr);
+extern void Cl1TstEltIfAfcConfig(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstEltIfTxAgcConfig(Cl1TstTxAgcConfigCmdT *Ptr);
+extern void Cl1TstEltIfTxPowerQuery(Cl1TstTxPowerQueryCmdT *Ptr);
+extern void Cl1TstEltIfRxAgcConfig(Cl1TstRxAgcConfigCmdT *Ptr);
+extern void Cl1TstEltIfRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr);
+extern void Cl1TstEltIfRxSnrQuery(Cl1TstRxSnrQueryCmdT *Ptr);
+extern void Cl1TstEltIfRxEcIoQuery(Cl1TstRxEcIoQueryCmdT *Ptr);
+extern void Cl1TstEltIfAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
+extern void Cl1TstEltIfAfcCalDataGet(Cl1TstAfcCalDataGetCmdT *Ptr);
+extern void Cl1TstEltIfRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
+extern void Cl1TstEltIfRxCalDataGet(Cl1TstRxCalDataGetCmdT *Ptr);
+extern void Cl1TstEltIfTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
+extern void Cl1TstEltIfTxCalDataGet(Cl1TstTxCalDataGetCmdT *Ptr);
+#ifndef __MD93__
+extern void Cl1TstEltIfLnaCalPwrPointGet(Cl1TstLnaCalPwrPointGetCmdT *Ptr);
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+extern void Cl1TstEltIfRxGainGet(Cl1TstRxGainGetCmdT *Ptr);
+extern void Cl1TstEltIfTxGainGet(Cl1TstTxGainGetCmdT *Ptr);
+extern void Cl1TstEltIfSetBpiData(Cl1TstSetBpiDataCmdT *Ptr);
+extern void Cl1TstEltIfGetBpiData(Cl1TstGetBpiDataCmdT *Ptr);
+extern void Cl1TstEltIfRxAgcFixManualConfig(Cl1TstRxAgcFixManualConfigCmdT *MsgPtr);
+#endif
+extern void Cl1TstEltIfFhcStart(Cl1TstFhcStartCmdT *Ptr);
+extern void Cl1TstEltIfTempBackOffSet(Cl1TstTempBackOffSetCmdT *Ptr);
+extern void Cl1TstEltIfTempBackOffGet(Cl1TstTempBackOffGetCmdT *Ptr);
+extern void Cl1tstEltIfRcpAccRtbPreempt(RcpTxSthRtbHscPreemptCtrlCmdT *Ptr);
+extern void Cl1tstEltIfRcpTxAgcCtrl(RcpTstTxAgcCtrlCmdT *Ptr);
+extern void Cl1tstEltIfL1dTxAgcCtrl(L1dTstTxAgcCtrlCmdT *Ptr);
+extern void Cl1tstEltIfTxDfeBbToneCfg(TxDfeBbToneCfgCmdT *Ptr);
+extern void Cl1tstEltIfTxDfeBbNcoCfg(TxDfeBbNcoCfgCmdT *Ptr);
+extern void Cl1TstEltIfIcsCaseIdCfg(EltTstIcsTstCaseIdCfgT *Ptr);
+extern void Cl1TstEltIfMcdDbgMsg(EltTstMcdDebugMsgT *MsgPtr);
+extern void Cl1TstEltRmcInterhoTstCfg(EltRmcInterhoTstCfgT *Ptr);
+extern void Cl1TstEltRmcIntrahoTstCfg(EltRmcIntrahoTstCfgT * Ptr);
+extern void Cl1TstEltIfStbDoSignalCfg(EltTstStbDoSignalCfgT *Ptr);
+extern void Cl1TstEltIfStbTimingCfg(EltTstStbTimingCfgT *Ptr);
+extern void Cl1PhyUtRptToScrip(EltC2kPhyUtTstRptT *CheckRptMsg);
+extern void Cl1PhyUtRxCaseRptToScript(EltC2kPhyUtRxCaseTstRptT *CheckRptMsg);
+extern void Cl1TestDfsMeasDone(Cl1TstRmcDfsMeasDoneRspT *CheckRptMsg);
+extern void Cl1TstEltIfSendMsg(ilm_struct *rsp_ilm_ptr);
+extern void Cl1TstEltIfCuifCfg(EltTstCuifCfgT *MsgPtr);
+extern void Cl1SendTstResp(Cl1TstCfgTypeT Type,Cl1TstRspResultT Result,Cl1TstRspInfoT *RspInfo);
+extern void Cl1TstEltIfStbOnlyModeCfg(EltTstStbOnlyModeCfgT *MsgPtr);
+extern void Cl1TstEltIfRcPartialBypassConf(Cl1RcdPartialBypassConfT* MsgPtr);
+#endif /* _CL1TST_ELT_IF_H_ */
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstl1psif.h b/mcu/interface/l1/cl1/common/cl1tstl1psif.h
new file mode 100644
index 0000000..d855c51
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstl1psif.h
@@ -0,0 +1,363 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tstl1psif.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the log IQ functions.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+*
+*
+*
+*
+*
+*
+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_L1PS_IF_H_
+#define _CL1TST_L1PS_IF_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "cl1tsteltif.h"
+#include "valapi.h"
+
+
+typedef enum
+{
+ CL1_DISABLE_MODE = 0,
+ CL1_MAINRX_ONLY_MODE = 1,
+ CL1_DIVERSITYRX_ONLY_MODE,
+ CL1_DUAL_MODE,
+ CL1_TESTMODE_NUM
+} Cl1AntennaTestModeT;
+
+typedef enum
+{
+ H_ANT = 0,
+ L_ANT_1,
+ L_ANT_2,
+ INVALID_ANT = 255
+} Cl1MainAntennaInfoT;
+
+typedef struct
+{
+ Cl1AntennaTestModeT AntTestMode;
+} Cl1TstAntennaTestModeMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1TstAntennaTestModeMsgT msg;
+}cl1tst_val_rx_test_mode_msg_struct;
+
+typedef struct
+{
+ ValCl1tstReqModeT Mode;
+ kal_uint16 Channel;
+ kal_uint8 Band;
+ kal_int8 TxPower;/*Q0*/
+ ValCl1tstTxSigTypeT TxSigType;
+} Cl1tstValRxTxPwrDetectMsgT;
+
+/** define Tx CDMA channel contorl message*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstValRxTxPwrDetectMsgT Msg;
+} cl1tst_val_rxtx_pwr_detect_msg_struct;
+
+typedef struct
+{
+ kal_uint8 RatType;
+ kal_bool MonitoringReq;
+} Cl1tstValGetAntInfoReqMsgT;
+
+/** define Tx CDMA channel contorl message*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstValGetAntInfoReqMsgT Msg;
+} cl1tst_val_get_ant_info_req_msg_struct;
+
+typedef struct
+{
+ kal_uint8 RatType;
+ kal_uint8 AntennaIndex;
+} Cl1tstTasMainPathSwitchInfoMsgT;
+
+/** define Tx CDMA channel contorl message*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstTasMainPathSwitchInfoMsgT Msg;
+} cl1tst_tas_main_path_switch_info_msg_struct;
+
+#ifdef __RF_SCAN_FOR_DESENSE_TEST__
+typedef struct
+{
+ kal_uint8 RatType;/*1xRTT or EVDO*/
+ kal_uint8 Band;
+ kal_uint16 Channel;
+ kal_bool TxOnFlag;
+ kal_int8 TxPower;/*Q0*/
+ kal_uint8 RepeatTimes;
+} Cl1tstValRxScanMsgT;
+
+/** define Tx CDMA channel contorl message*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstValRxScanMsgT Msg;
+} cl1tst_val_rx_scan_msg_struct;
+#endif
+
+#ifdef __EM_MAX_TX_POWER_SUPPORT__
+/*MSG_ID_CL1TST_VAL_MAX_TX_PWR_SET_MSG: define Max TxPower Adjust Offset set message : */
+typedef struct
+{
+ kal_uint8 Band;
+ kal_int16 MaxTxPwrOffset; /* Adjust Max TxPower for test*/
+} Cl1tstValMaxTxPwrSetMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstValMaxTxPwrSetMsgT Msg;
+} cl1tst_val_max_tx_pwr_set_msg_struct;
+#endif
+
+#ifdef MTK_DEV_ENGINEER_MODE
+/**MSG_ID_CL1TST_RCP_TX_TRANSMIT_CTRL_MSG */
+typedef struct
+{
+ RfTstControlActionT Action;
+ kal_uint16 Channel;
+ kal_uint8 Band;
+ kal_int8 TxPower;/*Q0*/
+ Cl1TstTxSigTypeT TxSigType;
+} Cl1TstRcpRxTxTransmitCtrlMsgT;
+
+/** define Tx CDMA channel contorl message*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1TstRcpRxTxTransmitCtrlMsgT Msg;
+} cl1tst_rcp_tx_transmit_ctrl_msg_struct;
+#endif
+
+typedef struct
+{
+ kal_uint32 SetResult;
+} Cl1tstSetMobileIdRspT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstSetMobileIdRspT Msg;
+} cl1tst_set_mobile_id_rsp_msg_struct;
+
+typedef struct
+{
+ kal_uint64 Meid;
+ kal_uint32 Esn;
+} Cl1tstGetMobileIdRspT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstGetMobileIdRspT Msg;
+} cl1tst_get_mobile_id_rsp_msg_struct;
+
+#if (defined(MTK_PLT_ON_PC_IT))||(defined(MTK_C2K_L1_TST))
+
+typedef struct
+{
+ kal_bool result;/* 1->Pass, 0->Fail */
+}Cl1tstPhyUtTstRptT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Cl1tstPhyUtTstRptT msg;
+} Cl1TstPhyutRptMsgStruct;
+#endif
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+extern void Cl1TstRxTestModeSetCtrl(Cl1TstAntennaTestModeMsgT *MsgPtr);
+extern void Cl1TstValRxTxPwrDetect(Cl1tstValRxTxPwrDetectMsgT *MsgPtr);
+#ifdef __RF_SCAN_FOR_DESENSE_TEST__
+extern void Cl1TstValRxScan(Cl1tstValRxScanMsgT *MsgPtr);
+#endif
+#ifdef MTK_DEV_ENGINEER_MODE
+extern void Cl1tstRcpTxTransmitCtrl(Cl1TstRcpRxTxTransmitCtrlMsgT *MsgPtr);
+#endif
+extern void Cl1TstValGetAntInfoReq(Cl1tstValGetAntInfoReqMsgT *MsgPtr);
+extern void Cl1TstValGetAntInfoInd(Cl1tstTasMainPathSwitchInfoMsgT *MsgPtr);
+extern void Cl1TstFhcReportToFt(void);
+extern Cl1AntennaTestModeT Cl1TstGetAntennaTestMode(SysCdmaBandT CurrentBand);
+extern kal_bool Cl1TstDiversityOnlyTestCtrl(void);
+extern kal_bool Cl1TstMainOnlyTestCtrl(void);
+extern kal_bool IsTestModeValid(Cl1AntennaTestModeT AntTestMode);
+extern kal_bool Cl1TstRfIsDiversityCompiledIn(void);
+extern void Cl1TstEltIfTempRead(EltTstReadTempT *MsgPtr);
+#if (defined(MTK_PLT_ON_PC_IT))||(defined(MTK_C2K_L1_TST))
+extern void Cl1TstShPhyutReport(Cl1tstPhyUtTstRptT *MsgPtr);
+#endif
+extern kal_bool Cl1TstRxDiversityOnlyTestEnable(SysCdmaBandT CurrentBand);
+extern kal_bool Cl1TstRfCustRxDiversityEnable(SysCdmaBandT CurrentBand);
+
+extern void Cl1TstNstPowerUpProc(Cl1TstNstPowerUpCmdT *Ptr);
+extern void Cl1TstNstTchFerCfgProc(Cl1TstNstTchFerCfgCmdT *Ptr);
+extern void Cl1TstNstTxPwrMeasCfgProc(Cl1TstNstTxPwrMeasCfgCmdT *Ptr);
+extern void Cl1TstNstRxPwrMeasCfgProc(Cl1TstNstRxPwrMeasCfgCmdT *Ptr);
+extern void Cl1TstNstListSetCfgProc(Cl1TstNstListSetCfgCmdT *Ptr);
+extern void Cl1TstNstEnterTestModeProc(Cl1TstNstEnterTestModeCmdT *Ptr);
+extern void Cl1TstNstExitTestModeProc(Cl1TstNstExitTestModeCmdT *Ptr);
+
+extern void Cl1TstNstPowerUpCnfProcess(PswNstPowerupAckRspMsgT *MsgPtr);
+extern void Cl1TstNstTchFerCfgCnfProcess(PswNstTchFerCfgCnfMsgT *MsgPtr);
+extern void Cl1TstNstTxMeasCfgCnfProcess(PswNstTransmitTchAckMsgT *MsgPtr);
+extern void Cl1TstNstRxMeasCfgCnfProcess(PswNstRxPwrRespMsgT *MsgPtr);
+extern void Cl1TstNstListSetCfgCnfProcess(PswNstListSetRespMsgT *MsgPtr);
+
+extern void Cl1tstL4CEnterFacModeReqPro(msg_type msg_id);
+extern void Cl1tstL4CEnterNorModeReqPro(msg_type msg_id);
+extern void Cl1tstSetMobileIdRspPro(Cl1tstSetMobileIdRspT *Ptr);
+extern void Cl1tstGetMobileIdRspPro(Cl1tstGetMobileIdRspT *Ptr);
+
+extern void Cl1TstRxAntTestModeSetProc(Cl1TstRxAntTestModeSetCmdT *Ptr);
+#endif /* _CL1TST_L1PS_IF_H_ */
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstmetaif.h b/mcu/interface/l1/cl1/common/cl1tstmetaif.h
new file mode 100644
index 0000000..9cb49e2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstmetaif.h
@@ -0,0 +1,1943 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tstmetaif.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the log IQ functions.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+*
+*
+*
+*
+*
+*
+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_META_IF_H_
+#define _CL1TST_META_IF_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "ft_msg_common.h"
+#include "cl1d_rf_public.h"
+#include "systyp.h"
+#include "cl1_rf_public.h"
+
+#define CL1TST_TEMP_SECTION_NUM 8
+#define CL1TST_FREQ_SECTION_NUM 16
+#define CL1TST_RX_PATH_NUM 3
+#define CL1TST_POWER_MODE_NUM 2
+#define CL1TST_LNA_MODE_NUM 8
+#define CL1TST_PA_SECTION_NUM 8
+#define CL1TST_PA_MODE_NUM 3
+
+#define CL1TST_FHC_TX_ELEMENT_NUM 1000
+#define CL1TST_FHC_RX_ELEMENT_NUM 1000
+
+#define CL1TST_RX_PATH_MAIN (1 << 0)
+#define CL1TST_RX_PATH_DIV (1 << 1)
+#define CL1TST_RX_PATH_SHDR (1 << 2)
+
+#define CL1TST_CAL_RSSI_WIN_ECHIP 0x1000 /* unit E chip (512 chips) */
+#define CL1TST_SUP_FRAME_LEN_ECHIP ST_9M_CNTS_PER_80MS /* unit E chip (80 ms) */
+#define CL1TST_SLOT_LEN_ECHIP ST_9M_CNTS_PER_1PT67MS /* unit E chip (1.66666 ms) */
+#define CL1TST_PCG_LEN_ECHIP ST_9M_CNTS_PER_1PT25MS /* unit E chip (1.25 ms) */
+#define CL1TST_HALF_SLOT_LEN_ECHIP 0x2000 /* unit E chip (1.66666 ms)/2 */
+#define CL1TST_HALF_SLOT_LEN_US 0x341 /* unit us (0.83333 ms) */
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+#define CL1TST_FIVE_PCG_LEN_US 0x186A /* unit us (6.25 ms) */
+#endif
+#define CL1TST_QUART_SLOT_LEN_ECHIP 0x1000 /* unit E chip (1.66666 ms)/4 */
+#define CL1TST_TRC_RSSI_WIN_NUM 12 /* 5ms */
+#define CL1TST_RX_ON_HRT_ECHIP 0x7AE /* unit E chip (200 us), TBD */
+#define CL1TST_RX_DELAY_ECHIP 20 /* unit E chip (20chip), TBD */
+
+#define CL1TST_MOD_HALF_SLOT_ECHIP(A) (A & 0x000001FFF)
+#define CL1TST_MOD_SLOT_ECHIP(A) (A & 0x000003FFF)
+#define CL1TST_MOD_CAL_RSSI_WIN_ECHIP(A) (A & 0x000000FFF)
+
+#define CL1TST_MOD_SUP_FRAME_ECHIP(A) while (A >= ST_9M_CNTS_PER_80MS) \
+ { \
+ A -=ST_9M_CNTS_PER_80MS; \
+ }
+
+
+#define CL1TST_NST_MAX_LIST_NUM 50
+#define CL1TST_NST_MAX_TX_PWR_COUNT 20
+#define CL1TST_NST_MAX_RX_PWR_COUNT 20
+#define CL1TST_RF_BAND_NUM_MAX 5
+#if defined( __MD93__)||defined( __MD95__)
+#define CL1TST_93M_95M_RXAGC_CFG_DELAY 14 /*in 93M and 95M, cfg complete after 10.84ms, and after 1slot,dsp send rssi to IA(after 12.5ms), delay 14ms to make sure rssi is readed after cfg really set*/
+#else
+#define CL1TST_97M_RXAGC_CFG_DELAY 7 /*in 97M,invoking cfg Api in n slot(or pcg). cfg take affect in slot(pcg)n+1,RFD get rssi in n+2 slot(pcg), L1 get it in n+3 slot(pcg), delay 7ms to rssi is readed after cfg really set*/
+#endif
+
+
+/** Tx power differ between bb sine tone and modulate signal if bb sine freq sel is 6 and AMP is 1/2 */
+#define CL1TST_TX_DIFFER_BB_TONE_MODULDATE_SIG (84)
+
+/** define RFD test mode enumeration */
+typedef enum
+{
+ CL1TST_RFD_RX_TST_MODE = 0,
+ CL1TST_RFD_TX_TST_MODE = 1,
+ CL1TST_RFD_META_MODE = 2,
+ CL1TST_RFD_INVALID = 0xFF
+} Cl1TstRfdTstModeT;
+
+typedef enum
+{
+ CL1TST_RX_AGC_FSM_ICS = 0,
+ CL1TST_RX_AGC_FSM_CAL = 1,
+ CL1TST_RX_AGC_FSM_INVALID = 0x7FFF
+}Cl1TstRxAgcFsmT;
+
+/* this enum is TBD (temp use) */
+typedef enum
+{
+ MIPI0,
+ MIPI1,
+ MIPI2,
+ MIPI3,
+ MIPI_END,
+ BSI1 = MIPI_END,
+ BSI_NAME_MAX,
+ BSI_NAME_INVALID = BSI_NAME_MAX
+} BsiNameT;
+
+/** define the RF mode enumeration */
+typedef enum
+{
+ CL1TST_RF_MODE_1XRTT,
+ CL1TST_RF_MODE_EVDO
+} Cl1TstRfModeT;
+
+/** define the RX agc control mode */
+typedef enum
+{
+ CL1TST_RX_AGC_AUTO = 0,
+ CL1TST_RX_AGC_MANUAL = 1
+} Cl1TstRxAgcModeT;
+
+/** define the command action enumeration */
+typedef enum
+{
+ CL1TST_ACTION_OFF,
+ CL1TST_ACTION_ON
+} Cl1TstActionT;
+
+/** define the NVRAM operation enumeration */
+typedef enum
+{
+ CL1TST_NV_NOT_UPDATE,
+ CL1TST_NV_UPDATE,
+ CL1TST_NV_INVALID = 0xFF
+} Cl1TstNvOptT;
+
+/** define the step indication enumeration */
+typedef enum
+{
+ CL1TST_FHC_STEP_IND_NORMAL, /* next step is normal step */
+ CL1TST_FHC_STEP_IND_RETUNE, /* next step is retune step */
+ CL1TST_FHC_STEP_IND_END, /* current step is last step */
+ CL1TST_FHC_STEP_IND_SWITCH, /* next step is switch step */
+ CL1TST_FHC_STEP_IND_NUM
+} Cl1TstFhcStepIndT;
+
+/** define the transmission signal type enumeration */
+typedef enum
+{
+ CL1TST_TX_SIG_TYPE_RF_TONE,
+ CL1TST_TX_SIG_TYPE_BB_TONE,
+ CL1TST_TX_SIG_TYPE_1X,
+ CL1TST_TX_SIG_TYPE_DO_PILOT,
+ CL1TST_TX_SIG_TYPE_DO_ST2
+} Cl1TstTxSigTypeT;
+
+/** define the command execute status enumeration */
+typedef enum
+{
+ CL1TST_REQ_SUCCESS,
+ CL1TST_REQ_FAILURE,
+ CL1TST_REQ_NOT_SUPPORT,
+ CL1TST_REQ_INVALID = 0x7FFFFFFF
+} Cl1TstReqStatusE;
+
+/** define the command Nst Cmd Status enumeration */
+typedef enum
+{
+ CL1TST_NST_CMD_SUCCESS,
+ CL1TST_NST_CMD_FAILURE_CMD,
+ CL1TST_NST_CMD_FAILURE_ICS,
+
+ CL1TST_NST_CMD_FAILURE_SYNC,
+
+ CL1TST_NST_CMD_FAILURE_TCH,
+
+ CL1TST_NST_CMD_FAILURE_HHO,
+ CL1TST_NST_CMD_FAILURE_NOT_SUPPORT,
+ CL1TST_NST_CMD_INVALID = 0x7FFFFFFF
+} Cl1TstNstCmdStatusE;
+
+
+/* CL1TST command type */
+typedef enum
+{
+ CL1TST_CMD_GET_RF_PLAT_INFO =0,
+ CL1TST_CMD_RFD_TEST_MODE_REQ =1,
+ CL1TST_CMD_RFD_INIT_REQ =2,
+ CL1TST_CMD_SET_MIPI_CW =3,
+ CL1TST_CMD_GET_MIPI_CW =4,
+ CL1TST_CMD_SET_SPI_DATA =5,
+ CL1TST_CMD_GET_SPI_DATA =6,
+ CL1TST_CMD_TRANSMIT_CTRL =7,
+ CL1TST_CMD_RECEIVE_CTRL =8,
+ CL1TST_CMD_AFC_CONFIG =9,
+ CL1TST_CMD_TX_AGC_CONFIG =10,
+ CL1TST_CMD_TX_POWER_QUERY =11,
+ CL1TST_CMD_RX_AGC_CONFIG =12,
+ CL1TST_CMD_RX_RSSI_QUERY =13,
+ CL1TST_CMD_AFC_CAL_DATA_SET =14,
+ CL1TST_CMD_AFC_CAL_DATA_GET =15,
+ CL1TST_CMD_RX_CAL_DATA_SET =16,
+ CL1TST_CMD_RX_CAL_DATA_GET =17,
+ CL1TST_CMD_TX_CAL_DATA_SET =18,
+ CL1TST_CMD_TX_CAL_DATA_GET =19,
+ CL1TST_CMD_FHC_START =20,
+ CL1TST_CMD_DPD_PA_DATA_SET =21,
+ CL1TST_CMD_DPD_PA_DATA_GET =22,
+ CL1TST_CMD_DPD_AM_PM_DATA_SET =23,
+ CL1TST_CMD_DPD_AM_PM_DATA_GET =24,
+ CL1TST_CMD_DPD_FAC_START =25,
+#ifndef __MD93__
+ CL1TST_CMD_RX_LNA_PWR_RANGE_GET =26,
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+ CL1TST_CMD_RX_GAIN_GET =27,
+ CL1TST_CMD_TX_GAIN_GET =28,
+ CL1TST_CMD_SET_BPI_DATA =29,
+ CL1TST_CMD_GET_BPI_DATA =30,
+ CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG =31,
+ CL1TST_CMD_RXDFE_IQ_DUMP_CFG =32,
+ CL1TST_CMD_TXDFE_IQ_DUMP_CFG =33,
+ CL1TST_CMD_TXKDFE_IQ_DUMP_CFG =34,
+ CL1TST_CMD_RXTXDFE_IQ_DUMP_QUERY =35,
+#endif
+
+ CL1TST_CMD_FACTORY_MODE_REQ =40,
+ CL1TST_CMD_NORMAL_MODE_REQ =41,
+ CL1TST_CMD_SET_MEID =42,
+ CL1TST_CMD_GET_MEID =43,
+ CL1TST_CMD_UBIN_INIT =44,
+ CL1TST_CMD_UBIN_DEINIT =45,
+
+ CL1TST_CMD_NST_POWER_UP =0x100,
+ CL1TST_CMD_NST_TCH_FER_CFG =0x101,
+ CL1TST_CMD_NST_TX_PWR_MEAS_CFG =0x102,
+ CL1TST_CMD_NST_RX_PWR_MEAS_CFG =0x103,
+ CL1TST_CMD_NST_LIST_MODE_SET_CFG =0x104,
+ CL1TST_CMD_NST_ENTER_TEST_MODE =0x105,
+ CL1TST_CMD_NST_EXIT_TEST_MODE =0x106,
+
+ CL1TST_CMD_RX_ANT_TESTMODE_SET_REQ =0x120,
+
+ CL1TST_CMD_TARGET_ASSERT =0x3E8,
+
+ CL1TST_CMD_INVALID =0x7FFFFFFF
+} Cl1TstCmdTypeE;
+
+#if 0
+#ifdef MTK_PLT_ON_PC_IT
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+/** define RF platform information getting command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstGetRfPlatInfoCmdT;
+
+/** define RF platform information for calibration */
+typedef struct
+{
+ kal_uint16 RfId;
+ kal_uint16 XoType;
+ kal_uint32 BandSupportBmp; // Band support bitmap
+ kal_uint32 RxDivSupportBmp;// RXD band support bitmap
+
+ kal_uint32 MipiSupportBmp; // MIPI band support bitmap
+ kal_uint32 DpdSupportBmp; // DPD band support bitmap
+ kal_uint32 RxSynthNum; // 1: main+div, 2: main+div+SHDR
+ kal_uint32 C2kNsftCapability; // Bit0 indicate the List Nsft Support: 0 means modmem is not support List Nsft; 1: modmem is support List Nsft(5Frame Tx Meas);
+#ifndef __MD93__
+ kal_uint32 OtherCapability; //bit0 used indicate if using cw for rx cal: 0 is disable, 1 is enable, other bits reserved.
+#endif
+}Cl1TstPlatInfoFacT;
+
+/** define RF platform information getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Platform info for factory calibration */
+ Cl1TstPlatInfoFacT PlatInfoFac;
+}Cl1TstGetRfPlatInfoRspT;
+
+/** define RFD test mode request structure */
+typedef struct
+{
+ /** [in] - 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /** [in] - 1: test mode enable
+ 0: test mode disablein */
+ kal_uint8 TstModeEn;
+
+ /** [in] - bit0: RX test mode
+ bit1: TX test mode
+ bit2: META mode
+ Note: just one bit can be set/clear every time
+ */
+ kal_uint8 TstModeBmp;
+
+ /** [in] - 1: L1 normal mode enable */
+ kal_uint8 L1NorModeEn;
+} Cl1TstRfdTestModeReqCmdT;
+
+/** define RFD test mode confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRfdTestModeReqRspT;
+
+/** define RF driver init command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstRfdInitReqCmdT;
+
+/** define RF driver init response structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRfdInitReqRspT;
+
+/** define MIPI codeword setting command structure */
+typedef struct
+{
+ kal_uint16 MipiPort;
+ kal_uint16 Reserved;
+ kal_uint32 MipiUsid;
+ kal_uint32 MipiAddr;
+ kal_uint32 MipiData;
+} Cl1TstSetMipiCodeWordCmdT;
+
+/** define MIPI codeword setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetMipiCodeWordRspT;
+
+/** define MIPI codeword getting command structure */
+typedef struct
+{
+ kal_uint16 MipiPort;
+ kal_uint16 Reserved;
+ kal_uint32 MipiUsid;
+ kal_uint32 MipiAddr;
+} Cl1TstGetMipiCodeWordCmdT;
+
+/** define MIPI codeword getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* MIPI data */
+ kal_uint32 MipiData;
+} Cl1TstGetMipiCodeWordRspT;
+
+/** define SPI data setting command structure */
+typedef struct
+{
+ kal_uint16 SpiId;
+ kal_uint16 Reserved;
+ kal_uint32 SpiAddr;
+ kal_uint32 SpiData;
+} Cl1TstSetSpiDataCmdT;
+
+/** define SPI data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetSpiDataRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ kal_uint16 SpiId;
+ kal_uint16 Reserved;
+ kal_uint32 SpiAddr;
+} Cl1TstGetSpiDataCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* SPI data */
+ kal_uint32 SpiData;
+} Cl1TstGetSpiDataRspT;
+
+/** define 1xRTT signal parameters */
+typedef struct
+{
+ /* Only for RTT */
+ /**0->RC1,1->RC2, etc*/
+ kal_uint8 RevRc;
+ /* Only for RTT */
+ //0: ACCESS, 1: FCH 2: FCH+SCH
+ kal_uint8 ChnType;
+ /* Only for RTT */
+ /**0->Full,1->Half Rate, etc*/
+ kal_uint8 FchRate;
+ /* Only for RTT */
+ kal_uint8 SchRate;
+
+ /* Only for RTT */
+ kal_uint16 GatePat; //GateOn/Off pattern
+
+ /* Only for RTT */
+ kal_uint16 FpcPat; //FPC pattern
+
+ /* Only for RTT */
+ kal_uint16 TxPreamble;
+
+ /* Only for RTT */
+ kal_uint16 LcmLow;
+
+ /* Only for RTT */
+ kal_uint16 SchWc; //Walsh code for SCH channel
+
+ /* Only for RTT */
+ kal_uint16 RaDly; //RA chip delay for access transmission
+
+ /* Only for RTT */
+ kal_uint16 TurboEn; //Indicate Turbo or CC encode for SCH channel
+ kal_uint16 Reserved;
+
+} Cl1Tst1xSigParaT;
+
+/** define RF transmitter control command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: OFF, 1: ON */
+ kal_uint8 Action;
+
+ /* 0: TXDFE RF tone for 1xRTT and EVDO
+ 1: TXDFE BB signal tone for 1xRTT and EVDO
+ 2: reverse 1xRTT signal for 1xRTT
+ 3: reverse EVDO pilot only for EVDO
+ 4: reverse EVDO subtype2 for EVDO */
+ kal_uint8 SigType;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Channel Number to turn on*/
+ kal_uint16 ChannelNum;
+
+ /* Reserved */
+ kal_uint16 Reserved1;
+
+ /* Frequency offset for RF tone transmission */
+ kal_uint32 FreqOffset;
+
+ /* BB tone configuration parameters */
+ kal_uint32 BbToneCfg;
+
+ Cl1Tst1xSigParaT RttSigPara;
+
+} Cl1TstTransmitCtrlCmdT;
+
+/** define RF transmitter control confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTransmitCtrlRspT;
+
+/** define RF receive control command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: OFF, 1: ON */
+ kal_uint8 Action;
+
+ /* bit0 for Main, bit1 for Div, bit2 for SHDR */
+ kal_uint8 PathBitmap;
+
+ /* Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Channel number to turn on*/
+ kal_uint16 ChannelNum;
+
+ /* Rx AGC FSM, 0 : Auto(RSSI scan) 1: calibration */
+ kal_uint16 RxAgcFsm;
+
+} Cl1TstReceiveCtrlCmdT;
+
+/** define RF receive control confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstReceiveCtrlRspT;
+
+/** define AFC configure command structure */
+typedef struct
+{
+ /* Manual for auto mode*/
+ kal_uint8 CtrlMode;
+
+ /* Cap Id valid indication*/
+ kal_uint8 CapIdValid;
+
+ /* Cap Id*/
+ kal_uint16 CapId;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* AFC DAC valid indication*/
+ kal_uint8 DacValid;
+
+ /*AFC DAC value*/
+ kal_uint16 DacValue;
+} Cl1TstAfcConfigCmdT;
+
+/** define AFC configure confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstAfcConfigRspT;
+
+/** define Tx AGC configuration command structure for RF test and traditional calibration */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: APT mode, 1: DPD mode */
+ kal_uint8 PaType;
+
+ /* 0: fix power 1: manual mode */
+ kal_uint8 CtrlMode;
+
+ /* ILPC enable or disable */
+ kal_uint8 IlpcEnable;
+
+ /* PA table index */
+ kal_uint8 PaTblIdx;
+
+ /* PA mode, 0: high, 1: middle, 2: low */
+ kal_uint8 PaMode;
+
+ /* Tx Power in dBm for fix power, Q5*/
+ kal_int16 TxPwr;
+
+ /* Tx Power in dBm for calibration, Q5*/
+ kal_int16 TxPwrCal;
+
+ /* PA gain, Q5 dBm */
+ kal_int16 PaGain;
+
+ /* Coupler loss, Q5 dB */
+ kal_int16 CpLoss;
+
+ /* AM */
+ kal_int16 Am;
+
+ /* PM */
+ kal_int16 Pm;
+
+ /* 0/1*/
+ kal_uint8 Vm1;
+
+ /*0/1*/
+ kal_uint8 Vm2;
+
+ /* voltage, in unit of mV*/
+ kal_uint16 Vcc;
+
+} Cl1TstTxAgcConfigCmdT;
+
+/** define Tx AGC configuration confirm structure for RF test and traditional calibration */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTxAgcConfigRspT;
+
+/** define DDPC result getting command structure */
+typedef struct
+{
+ kal_uint8 Reserved;
+} Cl1TstTxPowerQueryCmdT;
+
+/** define DDPC result getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Tx power, unit is Q5 dBm */
+ kal_int16 Power;
+ kal_int16 Reserved;
+} Cl1TstTxPowerQueryRspT;
+
+/** define Rx AGC configuration command structure for RF test and traditional calibration */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+
+ /* 0: Auto, 1: Manual for calibration and test, 2: RSSI scan */
+ kal_uint8 CtrlMode;
+
+ /* 0: high power mode, 1: low power mode */
+ kal_uint8 PwrMode;
+
+ /* 0: stage 0, 1: stage 1....5: stage 5 */
+ kal_uint8 LnaMode;
+
+#ifdef __MD93__
+ kal_uint8 Reserved1;
+#else
+ /* 0: disable, 1: enable */
+ kal_uint8 DigGainFix;
+#endif
+
+ /* Reserved */
+ kal_uint16 Reserved2;
+
+} Cl1TstRxAgcConfigCmdT;
+
+/** define Rx AGC configuration confirm structure for RF test and traditional calibration */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAgcConfigRspT;
+
+
+/** define RSSI query command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+} Cl1TstRxRssiQueryCmdT;
+
+/** define RSSI query confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Main antenna Rx power, unit is Q5 dBm */
+ kal_int16 RxMainPower;
+
+ /* Diversity antenna Rx power, unit is Q5 dBm */
+ kal_int16 RxDivPower;
+
+} Cl1TstRxRssiQueryRspT;
+
+/** define AFC calibration data setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* Reserved */
+ kal_uint8 Reserved1;
+
+ /* Reserved */
+ kal_uint16 Reserved2;
+
+ /* AFC calibration data */
+ CL1D_RF_AFC_DATA_T AfcCalData;
+
+} Cl1TstAfcCalDataSetCmdT;
+
+/** define AFC calibration data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstAfcCalDataSetRspT;
+
+/** define AFC calibration data getting command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstAfcCalDataGetCmdT;
+
+/** define AFC calibration data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* AFC calibration data */
+ /* LID:NVRAM_EF_CL1_AFC_DATA__LID */
+ CL1D_RF_AFC_DATA_T AfcCalData;
+
+} Cl1TstAfcCalDataGetRspT;
+
+/** define Rx calibration data structure */
+typedef struct
+{
+ /* High power mode path loss */
+ /* LID NVRAM_EF_CL1_MAIN_RX_PATH_LOSS_HPM_BAND_X_LID */
+ CL1D_RF_RX_PATH_LOSS_COMP_T RxPLossHPM;
+
+ /* Low power mode path loss */
+ /* LID:NVRAM_EF_CL1_MAIN_RX_PATH_LOSS_LPM_BAND_X_LID */
+ CL1D_RF_RX_PATH_LOSS_COMP_T RxPLossLPM;
+} Cl1TstRxCalDataT;
+
+/** define Rx calibration data setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* CDMA Band Class to turn on */
+ kal_uint8 BandClass;
+
+ /* path bitmap, bit0--main, bit1--diversity, bit2--SHDR */
+ kal_uint8 PathBmp;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* Rx calibration data */
+ Cl1TstRxCalDataT RxCalData;
+
+} Cl1TstRxCalDataSetCmdT;
+
+/** define Rx calibration data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxCalDataSetRspT;
+
+/** define Rx calibration data getting command structure */
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* path bitmap, bit0--main, bit1--diversity, bit2--SHDR */
+ kal_uint8 PathBmp;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstRxCalDataGetCmdT;
+
+/** define Rx calibration data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Rx calibration data */
+ Cl1TstRxCalDataT RxCalData;
+
+} Cl1TstRxCalDataGetRspT;
+
+/** define Tx calibration data structure */
+typedef struct
+{
+ /* PA context */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_CONTEXT_XX_BAND_X_LID */
+ CL1D_RF_TX_APT_PA_CONTEXT_T TxAptPaCtx;
+
+ /* PA gain temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_GAIN_COMP_XX_BAND_X_LID */
+ CL1D_RF_TX_APT_PA_GAIN_COMP_T TxAptPaGainComp;
+
+ /* Coupler loss temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_COMP_XX_BAND_X_LID */
+ CL1D_RF_DET_COUPLE_LOSS_COMP_T CplLossComp;
+
+ /* Coupler loss, Q5 dB */
+ /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_XX_BAND_X_LID */
+ CL1D_RF_DET_COUPLE_LOSS_T CplLoss;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+} Cl1TstTxCalDataT;
+
+/** define Tx calibration data setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* Tx calibration data */
+ Cl1TstTxCalDataT TxCalData;
+
+} Cl1TstTxCalDataSetCmdT;
+
+/** define Tx calibration data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTxCalDataSetRspT;
+
+/** define Tx calibration data getting command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstTxCalDataGetCmdT;
+
+/** define Tx calibration data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Tx calibration data */
+ Cl1TstTxCalDataT TxCalData;
+
+} Cl1TstTxCalDataGetRspT;
+
+#ifndef __MD93__
+/** define Lna calibration power point getting command structure */
+typedef struct
+{
+ /* Band Num to cal */
+ kal_uint8 BandNum;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass[RF_Band_NUM_MAX];
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstLnaCalPwrPointGetCmdT;
+
+/** define Lna calibration power point and range confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Lna calibration power point and range */
+ CL1D_RF_RX_LNA_CALIBRATION_POWER_AND_RANGE_T LnaCalPwrPoint[RF_Band_NUM_MAX];
+
+} Cl1TstLnaCalPwrPointGetRspT;
+#endif
+
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+/** define Rx Agc Gain getting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType;
+ CL1D_RF_PATH_E Path;
+}Cl1TstRxGainGetCmdT;
+
+/** define Rx Agc Gain getting command structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ CL1D_RF_AGC_ALGO_RESULT_QUERY_T RxGainPara;
+}Cl1TstRxGainGetRspT;
+
+/** define Tx Agc Gain getting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType;
+}Cl1TstTxGainGetCmdT;
+
+/** define Tx Agc Gain getting command structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ CL1D_RF_TPC_ALGO_RESULT_QUERY_T TxGainPara;
+}Cl1TstTxGainGetRspT;
+
+/** define SPI data setting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType; // is need add Reserved?
+ kal_uint32 BpiData;
+} Cl1TstSetBpiDataCmdT;
+
+/** define SPI data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetBpiDataRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType;
+} Cl1TstGetBpiDataCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* SPI data */
+ kal_uint32 BpiData;
+} Cl1TstGetBpiDataRspT;
+
+/** define Rx AGC configuration command structure for RF test and traditional calibration */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+
+ /* 0: fixed gain, 1:manual */
+ kal_uint8 TestMode;
+
+ /* C2K RX AGC FSM type, 0:FAST, 1:STEADY, 2:ICS, 3:CAL, 4:FIX_GAIN*/
+ kal_uint8 AgcFsm;
+
+ /* 0: high power mode, 1: low power mode */
+ kal_uint8 PwrMode;
+
+ /* 0: stage 0, 1: stage 1....5: stage 5 */
+ kal_uint8 LnaMode;
+
+ /** PGA index of CL1D_RF_PGA_INDEX_E */
+ kal_uint8 PgaIndex;
+
+ /* indicate which parameters to be fixed, bit0: rf gain, bit1: rf DC, bit2: digital gain, bit3: digital DC */
+ kal_uint8 AgcDcFixBmp;
+
+ /* digital gain in DB2 format, S5.5*/
+ kal_uint32 DigGain;
+} Cl1TstRxAgcFixManualConfigCmdT;
+
+/** define Rx AGC configuration confirm structure for RF test and traditional calibration */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAgcFixManualConfigRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ /* Rat,0:1x,1:DO */
+ kal_uint32 RatType;
+ /* PathBitMap*/
+ kal_uint32 PathBmp;
+ /* Dump node*/
+ kal_uint32 DumpNode;
+ /* IQ number*/
+ kal_uint32 IqNum;
+} Cl1TstRxDfeIqDumpCfgCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /*Total block size */
+ kal_uint32 BufferSize;
+ /*bock number */
+ kal_uint32 BlockNum;
+} Cl1TstRxDfeIqDumpCfgRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ /* Rat,0:1x,1:DO */
+ kal_uint32 RatType;
+ /** [in] - BB or RF or MRX**/
+ kal_uint32 DumpSel;
+ /** [in] - For TXDFE_BB:0:bb input; 1:firad input; 2:src input; 3:cic1x input; 4:cic2x input; 5:nco input; 6:nco ouput
+ For TXDFE_RF:0:gain_bb; 1:dpd comp; 2:gain bkf; 3:ga comp; 4:ad comp; 5:main phase r delay; 6:main dc; 7:main fi; 8:main fd**/
+ kal_uint32 NodeSel;
+ /* IQ number*/
+ kal_uint32 IqNum;
+} Cl1TstTxDfeIqDumpCfgCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /*Total block size */
+ kal_uint32 BufferSize;
+ /*bock number */
+ kal_uint32 BlockNum;
+} Cl1TstTxDfeIqDumpCfgRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ /* Rat,0:1x,1:DO */
+ kal_uint32 RatType;
+ /** [in] - 0:TXK_REF; 1:TXDFE_BB; 2:TXDFE_RF; 3:TXDFE_ET; 4:TXK_DET**/
+ kal_uint32 DumpSel;
+ /** [in] - For TXK DET: 0:det afifo out; 1:det cic out; 2:det out;
+ For TXK REF: 0:ref scale out; 1:ref i delay out; 2:ref f delay out; 3:ref dcm out**/
+ kal_uint32 NodeSel;
+ /* IQ number*/
+ kal_uint32 IqNum;
+} Cl1TstTxkDfeIqDumpCfgCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /*Total block size */
+ kal_uint32 BufferSize;
+ /*bock number */
+ kal_uint32 BlockNum;
+} Cl1TstTxkDfeIqDumpCfgRspT;
+
+typedef struct
+{
+ kal_uint32 BlockIndex;
+} Cl1TstRxTxDfeIqDumpQryCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /* last block flag */
+ kal_uint16 LastBlockInd;
+ /* partial block size */
+ kal_uint16 PtBlockSize;
+ /* block offset */
+ kal_uint32 BlockOffset;
+ /* Data buffer*/
+ kal_uint32 Data[CL1TST_RX_TX_IQ_DUMP_NUM];
+} Cl1TstRxTxDfeIqDumpQryRspT;
+#endif
+
+/** define FHC start common data structure */
+typedef struct
+{
+ /* Tx RX delay for FHC, unit us (> 10us) */
+ kal_uint16 TxRxDelay;
+
+ /* Tx step length, unit us (>= 1000us and <= 20000 us) */
+ kal_uint16 TxStepLength;
+
+ /* Tx retune length, unit us (>= 500us) */
+ kal_uint16 TxRetuLength;
+
+ /* RF mode switch length, unit us, the integer multiple of step length */
+ kal_uint16 RfMSwhLength;
+
+ /* Rx step length, unit us (>= 1000us and <= 20000 us) */
+ kal_uint16 RxStepLength;
+
+ /* Rx retune length, unit us (>= 500us) */
+ kal_uint16 RxRetuLength;
+
+} Cl1TstFhcCommonT;
+
+/** define Tx calibration element structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Step indication, 0: next step is normal step,
+ 1: next step is retune step,
+ 2: the current step is the last step,
+ 3: next step is RF mode switch step
+ */
+ kal_uint8 StepInd;
+
+ /* CDMA band class */
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* CDMA channel */
+ kal_uint16 ChanNum;
+
+ /* RF calibration power points, dBm, Q5 */
+ kal_int16 TxPwr;
+
+} Cl1TstFhcTxElementT;
+
+/** define Rx calibration element structure */
+typedef struct
+{
+ /* Step indication, 0: next step is normal step,
+ 1: next step is retune step,
+ 2: the current step is the last step
+ */
+ kal_uint8 StepInd;
+
+ /* CDMA band class */
+ kal_uint8 BandClass;
+
+ /* CDMA channel */
+ kal_uint16 ChanNum;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitmap;
+
+ /* Power mode, 0: high power mode, 1: low power mode */
+ kal_uint8 PwrMode;
+
+ /* LNA mode, 0~7 */
+ kal_uint8 LnaMode;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+} Cl1TstFhcRxElementT;
+
+/** define FHC calibration start command structure */
+typedef struct
+{
+ /* FHC calibration common data */
+ Cl1TstFhcCommonT CommonData;
+
+ /* Reserved */
+ kal_uint16 Reserved1;
+
+ /* Tx calibration elements number (1~1000) */
+ kal_uint16 TxElementNum;
+
+ /* Tx calibration elements */
+ Cl1TstFhcTxElementT TxElement[CL1TST_FHC_TX_ELEMENT_NUM];
+
+ /* Reserved */
+ kal_uint16 Reserved2;
+
+ /* Rx calibration elements number (1~1000) */
+ kal_uint16 RxElementNum;
+
+ /* Rx calibration elements */
+ Cl1TstFhcRxElementT RxElement[CL1TST_FHC_RX_ELEMENT_NUM];
+
+} Cl1TstFhcStartCmdT;
+
+/** define FHC report result structure */
+typedef struct
+{
+ /* power detect result number */
+ kal_uint16 PdetNum;
+
+ /* RSSI number */
+ kal_uint16 RssiNum;
+
+ /* power detect result, unit is Q5 dBm */
+ kal_int16 Pdet[CL1TST_FHC_TX_ELEMENT_NUM];
+
+ /* Main antenna RSSI, unit is Q5 dBm */
+ kal_int16 RssiMain[CL1TST_FHC_RX_ELEMENT_NUM];
+
+ /* Diversity antenna RSSI, unit is Q5 dBm */
+ kal_int16 RssiDiv[CL1TST_FHC_RX_ELEMENT_NUM];
+} Cl1TstFhcRptDataT;
+
+/** define FHC calibration start confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* FHC report result */
+ Cl1TstFhcRptDataT RptData;
+} Cl1TstFhcStartRspT;
+
+/** define 1xrtt NST Relation command and confirm structure */
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+ /* CDMA Walsh Code Channel*/
+ kal_uint8 CodeChan;
+ /* CDMA Radio configuration,1 is RC1, 2 is RC2 Etc*/
+ kal_uint8 RadioConfig;
+} Cl1TstNstPowerUpCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstPowerUpRspT;
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+ /* Number of Fer cacualte Frames*/
+ kal_uint16 NumFrames;
+ /* Flag of Enable AFC Config*/
+ kal_bool EnableAFC;
+} Cl1TstNstTchFerCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+ kal_uint16 BadFrames;
+ kal_uint16 TotalFrames;
+} Cl1TstNstTchFerCfgRspT;
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+ /* Tx Power Level ,unint is Q6*/
+ kal_uint16 TxPwrQ6;
+} Cl1TstNstTxPwrMeasCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstTxPwrMeasCfgRspT;
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+} Cl1TstNstRxPwrMeasCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+ /* Current PN Offset */
+ kal_uint16 PnOffset;
+ /* Current Aset Pilot Strength */
+ kal_int16 Strength;
+ /* Current Main Ant Rx Power,unit is Q5 */
+ kal_int16 MainRxPwrQ5;
+ /* Current Div Ant Rx Power,unit is Q5 */
+ kal_int16 DivRxPwrQ5;
+} Cl1TstNstRxPwrMeasCfgRspT;
+
+typedef struct
+{
+ /* Total Count of NST List */
+ kal_uint8 Count;
+ /* Num of frame offset */
+ kal_uint8 Offset[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Walsh Code Channel*/
+ kal_uint8 CodeChan[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Radio configuration,1 is RC1, 2 is RC2 Etc*/
+ kal_uint8 RadioConfig[CL1TST_NST_MAX_LIST_NUM];
+
+ /* Number of Fer cacualte Frames*/
+ kal_uint16 NumFrames[CL1TST_NST_MAX_LIST_NUM];
+ /* Count of Meas Tx Pwr Level for Per Freq Chan*/
+ kal_uint8 TxPwrCount[CL1TST_NST_MAX_LIST_NUM];
+ /* Meas Tx Pwr Level for Per Freq Chan*/
+ kal_uint16 TxPwrLevelQ6[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_TX_PWR_COUNT];
+ /* Count of Meas Rx Pwr Level for Per Freq Chan*/
+ kal_uint8 RxPwrCount[CL1TST_NST_MAX_LIST_NUM];
+} Cl1TstNstListSetCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+ /* Total Count of NST List */
+ kal_uint8 Count;
+ /* Index of list */
+ kal_uint8 Index[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel[CL1TST_NST_MAX_LIST_NUM];
+ /* Number of Bad Frames for Per Freq Chan */
+ kal_uint8 BadFrames[CL1TST_NST_MAX_LIST_NUM];
+ /* Number of Total Meas Frames for Per Freq Chan */
+ kal_uint8 TotalFrames[CL1TST_NST_MAX_LIST_NUM];
+ /* Current Main Ant Rx Power,unit is Q5 */
+ kal_int16 MainRxPwrQ5[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_RX_PWR_COUNT];
+ /* Current Div Ant Rx Power,unit is Q5 */
+ kal_int16 DivRxPwrQ5[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_RX_PWR_COUNT];
+} Cl1TstNstListSetCfgRspT;
+
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstNstEnterTestModeCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstEnterTestModeRspT;
+
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstNstExitTestModeCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstExitTestModeRspT;
+
+/** define enter factory mode request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstFactoryModeReqCmdT;
+
+/** define enter factory mode confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstFactoryModeReqRspT;
+
+/** define enter normal mode request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstNormalModeReqCmdT;
+
+/** define enter normal mode confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstNormalModeReqRspT;
+
+typedef struct
+{
+ kal_uint32 Meid_L;
+ kal_uint32 Meid_H;
+} Cl1TstSetMeidCmdT;
+
+/** define MEID setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetMeidRspT;
+
+/** define MEID getting command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstGetMeidCmdT;
+
+/** define MEID getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* MEID data */
+ kal_uint32 Meid_L;
+ kal_uint32 Meid_H;
+
+ /* ESN data */
+ kal_uint32 Esn;
+} Cl1TstGetMeidRspT;
+
+/** define UBIN init request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstUbinInitCmdT;
+
+/** define UBIN init confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstUbinInitRspT;
+
+/** define UBIN De init request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstUbinDeInitCmdT;
+
+/** define UBIN Deinit confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstUbinDeInitRspT;
+
+
+
+typedef struct
+{
+ /* Ant Test Mode Set:0 means disable test Mode,1 means Main Rx Only,and
+ * 2 means Div Rx Only Mode,3 means Dual Mode(Main+Div).*/
+ kal_uint32 AntTestMode;
+} Cl1TstRxAntTestModeSetCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAntTestModeSetRspT;
+
+
+#if 0
+#ifdef MTK_PLT_ON_PC_IT
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+/* C2K meta interface command union */
+typedef union
+{
+ Cl1TstGetRfPlatInfoCmdT GetRfPlatInfoCmd; // for CL1TST_CMD_GET_RF_PLATFORM_INFO
+ Cl1TstRfdTestModeReqCmdT RfdTestModeReqCmd; // for CL1TST_CMD_RFD_ENTER_TEST_MODE
+ Cl1TstRfdInitReqCmdT RfdInitReqCmd; // for CL1TST_CMD_RFD_INIT_REQ
+ Cl1TstSetMipiCodeWordCmdT SetMipiCodeWordCmd; // for CL1TST_CMD_SET_MIPI_CW
+ Cl1TstGetMipiCodeWordCmdT GetMipiCodeWordCmd; // for CL1TST_CMD_GET_MIPI_CW
+ Cl1TstSetSpiDataCmdT SetSpiDataCmd; // for CL1TST_CMD_SET_SPI_DATA
+ Cl1TstGetSpiDataCmdT GetSpiDataCmd; // for CL1TST_CMD_GET_SPI_DATA
+ Cl1TstTransmitCtrlCmdT TransmitCtrlCmd; // for CL1TST_CMD_TRANSMIT_CTRL
+ Cl1TstReceiveCtrlCmdT ReceiveCtrlCmd; // for CL1TST_CMD_RECEIVE_CTRL
+ Cl1TstAfcConfigCmdT AfcConfigCmd; // for CL1TST_CMD_AFC_CONFIG
+ Cl1TstTxAgcConfigCmdT TxAgcConfigCmd; // for CL1TST_CMD_TX_AGC_CONFIG
+ Cl1TstTxPowerQueryCmdT TxPowerQueryCmd; // for CL1TST_CMD_TX_POWER_QUERY
+ Cl1TstRxAgcConfigCmdT RxAgcConfigCmd; // for CL1TST_CMD_RX_AGC_CONFIG
+ Cl1TstRxRssiQueryCmdT RxRssiQueryCmd; // for CL1TST_CMD_RX_RSSI_QUERY
+ Cl1TstAfcCalDataSetCmdT AfcCalDataSetCmd; // for CL1TST_CMD_AFC_CAL_DATA_SET
+ Cl1TstAfcCalDataGetCmdT AfcCalDataGetCmd; // for CL1TST_CMD_AFC_CAL_DATA_GET
+ Cl1TstRxCalDataSetCmdT RxCalDataSetCmd; // for CL1TST_CMD_RX_CAL_DATA_SET
+ Cl1TstRxCalDataGetCmdT RxCalDataGetCmd; // for CL1TST_CMD_RX_CAL_DATA_GET
+ Cl1TstTxCalDataSetCmdT TxCalDataSetCmd; // for CL1TST_CMD_TX_CAL_DATA_SET
+ Cl1TstTxCalDataGetCmdT TxCalDataGetCmd; // for CL1TST_CMD_TX_CAL_DATA_GET
+#ifndef __MD93__
+ Cl1TstLnaCalPwrPointGetCmdT LnaCalPwrPointGetCmd; // for CL1TST_CMD_RX_LNA_PWR_RANGE_GET
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+ Cl1TstRxGainGetCmdT RxGainGetCmd; // for CL1TST_CMD_RX_GAIN_GET
+ Cl1TstTxGainGetCmdT TxGainGetCmd; // for CL1TST_CMD_TX_GAIN_GET
+ Cl1TstSetBpiDataCmdT SetBpiDataCmd; // for CL1TST_CMD_SET_BPI_DATA
+ Cl1TstGetBpiDataCmdT GetBpiDataCmd; // for CL1TST_CMD_GET_BPI_DATA
+ Cl1TstRxAgcFixManualConfigCmdT RxAgcFixManualConfigCmd; // for CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG
+ Cl1TstRxDfeIqDumpCfgCmdT RxDfeIqDumpCfgCmd; // for CL1TST_CMD_RXDFE_IQ_DUMP_CFG
+ Cl1TstTxDfeIqDumpCfgCmdT TxDfeIqDumpCfgCmd; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
+ Cl1TstTxkDfeIqDumpCfgCmdT TxkDfeIqDumpCfgCmd; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
+ Cl1TstRxTxDfeIqDumpQryCmdT RxTxDfeIqDumpQryCmd; // for CL1TST_CMD_RXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY
+#endif
+
+ Cl1TstFhcStartCmdT FhcStartCmd; // for CL1TST_CMD_FHC_START
+ Cl1TstFactoryModeReqCmdT FactoryModeReqCmd; // for CL1TST_CMD_FACTORY_MODE_REQ
+ Cl1TstNormalModeReqCmdT NormalModeReqCmd; // for CL1TST_CMD_NORMAL_MODE_REQ
+ Cl1TstSetMeidCmdT SetMeidCmd; // for CL1TST_CMD_SET_MEID
+ Cl1TstGetMeidCmdT GetMeidCmd; // for CL1TST_CMD_GET_MEID
+ Cl1TstUbinInitCmdT UbinInitCmd; // for CL1TST_CMD_UBIN_INIT
+ Cl1TstUbinDeInitCmdT UbinDeInitCmd; // for CL1TST_CMD_UBIN_DEINIT
+
+ Cl1TstNstPowerUpCmdT NstPowerUpCmd;
+ Cl1TstNstTchFerCfgCmdT NstTchFerCfgCmd;
+ Cl1TstNstTxPwrMeasCfgCmdT NstTxPwrMeasCfgCmd;
+
+ Cl1TstNstRxPwrMeasCfgCmdT NstRxPwrMeasCfgCmd;
+ Cl1TstNstListSetCfgCmdT NstListSetCfgCmd;
+ Cl1TstNstEnterTestModeCmdT NstEnterTestModeCmd;
+ Cl1TstNstExitTestModeCmdT NstExitTestModeCmd;
+
+ Cl1TstRxAntTestModeSetCmdT RxAntTestModeSetCmd;
+}Cl1TstCmdParam;
+
+/* C2K meta interface confirm union */
+typedef union
+{
+ Cl1TstGetRfPlatInfoRspT GetRfPlatInfoRsp; // for CL1TST_CMD_GET_RF_PLATFORM_INFO
+ Cl1TstRfdTestModeReqRspT RfdTestModeReqRsp; // for CL1TST_CMD_RFD_EXIT_TEST_MODE
+ Cl1TstRfdInitReqRspT RfdInitReqRsp; // for CL1TST_CMD_RFD_INIT_REQ
+ Cl1TstSetMipiCodeWordRspT SetMipiCodeWordRsp; // for CL1TST_CMD_SET_MIPI_CW
+ Cl1TstGetMipiCodeWordRspT GetMipiCodeWordRsp; // for CL1TST_CMD_GET_MIPI_CW
+ Cl1TstSetSpiDataRspT SetSpiDataRsp; // for CL1TST_CMD_SET_SPI_DATA
+ Cl1TstGetSpiDataRspT GetSpiDataRsp; // for CL1TST_CMD_GET_SPI_DATA
+ Cl1TstTransmitCtrlRspT TransmitCtrlRsp; // for CL1TST_CMD_TRANSMIT_CTRL
+ Cl1TstReceiveCtrlRspT ReceiveCtrlRsp; // for CL1TST_CMD_RECEIVE_CTRL
+ Cl1TstAfcConfigRspT AfcConfigRsp; // for CL1TST_CMD_AFC_CONFIG
+ Cl1TstTxAgcConfigRspT TxAgcConfigRsp; // for CL1TST_CMD_TX_AGC_CONFIG
+ Cl1TstTxPowerQueryRspT TxPowerQueryRsp; // for CL1TST_CMD_TX_POWER_QUERY
+ Cl1TstRxAgcConfigRspT RxAgcConfigRsp; // for CL1TST_CMD_RX_AGC_CONFIG
+ Cl1TstRxRssiQueryRspT RxRssiQueryRsp; // for CL1TST_CMD_RX_RSSI_QUERY
+ Cl1TstAfcCalDataSetRspT AfcCalDataSetRsp; // for CL1TST_CMD_AFC_CAL_DATA_SET
+ Cl1TstAfcCalDataGetRspT AfcCalDataGetRsp; // for CL1TST_CMD_AFC_CAL_DATA_GET
+ Cl1TstRxCalDataSetRspT RxCalDataSetRsp; // for CL1TST_CMD_RX_CAL_DATA_SET
+ Cl1TstRxCalDataGetRspT RxCalDataGetRsp; // for CL1TST_CMD_RX_CAL_DATA_GET
+ Cl1TstTxCalDataSetRspT TxCalDataSetRsp; // for CL1TST_CMD_TX_CAL_DATA_SET
+ Cl1TstTxCalDataGetRspT TxCalDataGetRsp; // for CL1TST_CMD_TX_CAL_DATA_GET
+#ifndef __MD93__
+ Cl1TstLnaCalPwrPointGetRspT LnaCalPwrPointGetRsp; // for CL1TST_CMD_RX_LNA_PWR_RANGE_GET
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+ Cl1TstRxGainGetRspT RxGainGetRsp; // for CL1TST_CMD_RX_GAIN_GET
+ Cl1TstTxGainGetRspT TxGainGetRsp; // for CL1TST_CMD_TX_GAIN_GET
+ Cl1TstSetBpiDataRspT SetBpiDataRsp; // for CL1TST_CMD_SET_BPI_DATA
+ Cl1TstGetBpiDataRspT GetBpiDataRsp; // for CL1TST_CMD_GET_BPI_DATA
+ Cl1TstRxAgcFixManualConfigRspT RxAgcFixManualConfigRsp; // for CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG
+ Cl1TstRxDfeIqDumpCfgRspT RxDfeIqDumpCfgRsp; // for CL1TST_CMD_RXDFE_IQ_DUMP_CFG
+ Cl1TstTxDfeIqDumpCfgRspT TxDfeIqDumpCfgRsp; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
+ Cl1TstTxkDfeIqDumpCfgRspT TxkDfeIqDumpCfgRsp; // for CL1TST_CMD_TXkDFE_IQ_DUMP_CFG
+ Cl1TstRxTxDfeIqDumpQryRspT RxTxDfeIqDumpQryRsp; // for CL1TST_CMD_RXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXkDFE_IQ_DUMP_QUERY
+#endif
+
+ Cl1TstFhcStartRspT FhcStartRsp; // for CL1TST_CMD_FHC_START
+ Cl1TstFactoryModeReqRspT FactoryModeReqRsp; // for CL1TST_CMD_FACTORY_MODE_REQ
+ Cl1TstNormalModeReqRspT NormalModeReqRsp; // for CL1TST_CMD_NORMAL_MODE_REQ
+ Cl1TstSetMeidRspT SetMeidRsp; // for CL1TST_CMD_SET_MEID
+ Cl1TstGetMeidRspT GetMeidRsp; // for CL1TST_CMD_GET_MEID
+ Cl1TstUbinInitRspT UbinInitRsp; // for CL1TST_CMD_UBIN_INIT
+ Cl1TstUbinDeInitRspT UbinDeInitRsp; // for CL1TST_CMD_UBIN_DEINIT
+
+ Cl1TstNstPowerUpRspT NstPowerUpRsp;
+ Cl1TstNstTchFerCfgRspT NstTchFerCfgRsp;
+ Cl1TstNstTxPwrMeasCfgRspT NstTxPwrMeasCfgRsp;
+
+ Cl1TstNstRxPwrMeasCfgRspT NstRxPwrMeasCfgRsp;
+ Cl1TstNstListSetCfgRspT NstListSetCfgRsp;
+ Cl1TstNstEnterTestModeRspT NstEnterTestModeRsp;
+ Cl1TstNstExitTestModeRspT NstExitTestModeRsp;
+
+ Cl1TstRxAntTestModeSetRspT RxAntTestModeSetRsp;
+}Cl1TstRspParam;
+
+/* FT peer buffer request structure */
+typedef struct
+{
+ Cl1TstCmdTypeE Type;
+ Cl1TstCmdParam Para;
+}FT_CRF_PEER_CMD;
+
+/* FT peer buffer confirm structure */
+typedef struct
+{
+ Cl1TstCmdTypeE Type;
+ Cl1TstRspParam Para;
+}FT_CRF_PEER_RSP;
+
+/* struct definition for FT request & confirm */
+typedef FT_H FT_CRF_LOCAL_PARA;
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+extern void CL1TST_ALLOC_MSG_CC(ilm_struct* ilm_ptr, kal_uint32 local_param_size, kal_uint32 peer_pdu_size);
+extern void CL1TST_SEND_MSG_TO_FT(ilm_struct *ilm_ptr);
+extern void CL1TST_BackupFtHeader(kal_uint16 taken);
+extern void CL1TST_SetFtHeader(FT_CRF_LOCAL_PARA *rsp_loc);
+
+extern void Cl1TstRfdTestModeReqPro(Cl1TstRfdTestModeReqCmdT *Ptr);
+
+extern void Cl1TstTxPathOnTimingCalc(kal_uint8 RfMode,
+ kal_uint16 RaDly,
+ kal_uint32 *TxStartOfst,
+ kal_uint32 *RxStartOfst);
+
+extern void Cl1TstTxPathOffTimingCalc(kal_uint8 RfMode,
+ kal_uint32 *TxStartOfst,
+ kal_uint32 *RxStartOfst);
+
+extern void Cl1TstTxPathOn1xSigPro(kal_uint8 Action, Cl1Tst1xSigParaT *Ptr, kal_bool FlagL1d);
+
+extern kal_uint8 Cl1TstDoActionQuery(kal_uint8 Action);
+
+extern void Cl1TstTransmitCtrlPathPro(Cl1TstTransmitCtrlCmdT *Ptr);
+extern void Cl1TstTransmitCtrlSigPro(Cl1TstTransmitCtrlCmdT *Ptr, kal_bool L1dFlag);
+extern void Cl1TstReceiveCtrlPathPro(Cl1TstReceiveCtrlCmdT *Ptr);
+extern void Cl1TstAfcConfigPro(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstAfcConfigPro(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstTxAgcConfigPro(Cl1TstTxAgcConfigCmdT *Ptr);
+extern void Cl1TstRxAgcConfigPro(Cl1TstRxAgcConfigCmdT *Ptr);
+extern void CltstAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
+extern void CltstAfcCalDataGet(CL1D_RF_AFC_DATA_T *Ptr);
+extern void CltstRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
+extern void CltstRxCalDataGet(Cl1TstRxCalDataGetCmdT *GetPtr, Cl1TstRxCalDataT *DatPtr);
+extern void CltstTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
+extern void CltstTxCalDataGet(Cl1TstTxCalDataGetCmdT *GetPtr, Cl1TstTxCalDataT *DatPtr);
+extern void Cl1tstTxDfeBbToneCfg(kal_uint32 CfgData);
+extern void Cl1TstRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr,
+ CL1D_RF_AGC_RSSI_QUERY_T *AdsPtr);
+extern void Cl1TstRxRssiQueryPduFill(Cl1TstRxRssiQueryCmdT *Ptr,
+ CL1D_RF_AGC_RSSI_QUERY_T *AdsPtr,
+ Cl1TstRxRssiQueryRspT *RspPdu);
+extern void Cl1TstMetaIfGetRfPlatInfo(Cl1TstGetRfPlatInfoCmdT *Ptr);
+extern void Cl1TstMetaIfRfdTestModeReq(Cl1TstRfdTestModeReqCmdT *Ptr);
+extern void Cl1TstMetaIfRfdInitReq(Cl1TstRfdInitReqCmdT *Ptr);
+extern void Cl1TstMetaIfSetMipiCodeWord(Cl1TstSetMipiCodeWordCmdT *Ptr);
+extern void Cl1TstMetaIfGetMipiCodeWord(Cl1TstGetMipiCodeWordCmdT *Ptr);
+extern void Cl1TstMetaIfSetSpiData(Cl1TstSetSpiDataCmdT *Ptr);
+extern void Cl1TstMetaIfGetSpiData(Cl1TstGetSpiDataCmdT *Ptr);
+extern void Cl1TstMetaIfTransmitCtrl(Cl1TstTransmitCtrlCmdT *Ptr);
+extern void Cl1TstMetaIfReceiveCtrl(Cl1TstReceiveCtrlCmdT *Ptr);
+extern void Cl1TstMetaIfAfcConfig(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstMetaIfTxAgcConfig(Cl1TstTxAgcConfigCmdT *Ptr);
+extern void Cl1TstMetaIfTxPowerQuery(Cl1TstTxPowerQueryCmdT *Ptr);
+extern void Cl1TstMetaIfRxAgcConfig(Cl1TstRxAgcConfigCmdT *Ptr);
+extern void Cl1TstMetaIfRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr);
+extern void Cl1TstMetaIfAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
+extern void Cl1TstMetaIfAfcCalDataGet(Cl1TstAfcCalDataGetCmdT *Ptr);
+extern void Cl1TstMetaIfRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
+extern void Cl1TstMetaIfRxCalDataGet(Cl1TstRxCalDataGetCmdT *Ptr);
+extern void Cl1TstMetaIfTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
+extern void Cl1TstMetaIfTxCalDataGet(Cl1TstTxCalDataGetCmdT *Ptr);
+#ifndef __MD93__
+extern void Cl1TstMetaIfLnaCalPwrPointGet(Cl1TstLnaCalPwrPointGetCmdT *Ptr);
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+extern void Cl1TstMetaIfRxGainGet(Cl1TstRxGainGetCmdT *Ptr);
+extern void Cl1TstMetaIfTxGainGet(Cl1TstTxGainGetCmdT *Ptr);
+extern void Cl1TstMetaIfSetBpiData(Cl1TstSetBpiDataCmdT *Ptr);
+extern void Cl1TstMetaIfGetBpiData(Cl1TstGetBpiDataCmdT *Ptr);
+extern void Cl1TstRxAgcFixManualConfigPro(Cl1TstRxAgcFixManualConfigCmdT *Ptr);
+extern void Cl1TstMetaIfRxAgcFixManualConfig(Cl1TstRxAgcFixManualConfigCmdT *Ptr);
+extern void Cl1TstMetaIfRxDfeIqDumpCfg(Cl1TstRxDfeIqDumpCfgCmdT *Ptr);
+extern void Cl1TstMetaIfTxDfeIqDumpCfg(Cl1TstTxDfeIqDumpCfgCmdT *Ptr);
+extern void Cl1TstMetaIfTxkDfeIqDumpCfg(Cl1TstTxkDfeIqDumpCfgCmdT *Ptr);
+extern void Cl1TstMetaIfRxTxDfeIqDumpQry(Cl1TstRxTxDfeIqDumpQryCmdT *Ptr);
+#endif
+extern void Cl1TstMetaIfFhcStart(Cl1TstFhcStartCmdT *Ptr);
+extern void Cl1tstMetaIfFactoryModeReq(Cl1TstFactoryModeReqCmdT * Ptr);
+extern void Cl1tstMetaIfNormalModeReq(Cl1TstNormalModeReqCmdT * Ptr);
+extern void Cl1TstMetaIfSetMeid(Cl1TstSetMeidCmdT *Ptr);
+extern void Cl1TstMetaIfGetMeid(Cl1TstGetMeidCmdT *Ptr);
+extern void Cl1TstMetaIfUbinInit(Cl1TstUbinInitCmdT *Ptr);
+extern void Cl1TstMetaIfUbinDeInit(Cl1TstUbinDeInitCmdT *Ptr);
+extern void Cl1TstMetaIfTargetAssert();
+extern kal_uint32 CltstNvOperBmpGet(kal_uint8 UpdateNvram);
+extern kal_bool Cl1tstDoTrigTxSlpRsmDlyQuery();
+extern void Cl1tstDoTrigTxSlpRsmDlyClear();
+
+#endif /* _CL1TST_META_IF_H_ */
+
diff --git a/mcu/interface/l1/cl1/common/cl1tstphyutmain.h b/mcu/interface/l1/cl1/common/cl1tstphyutmain.h
new file mode 100644
index 0000000..20b6786
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1tstphyutmain.h
@@ -0,0 +1,162 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1TSTPHYUTMAIN_H_
+#define _CL1TSTPHYUTMAIN_H_
+
+#ifndef MTK_PLT_ON_PC_IT
+typedef enum
+{
+ CL1_PHYUT_MOD_EVL1_FLBSRP,
+ CL1_PHYUT_MOD_EVL1_SCH,
+ CL1_PHYUT_MOD_EVL1_RLBSRP,
+ CL1_PHYUT_MOD_1XL1_FLBSRP,
+ CL1_PHYUT_MOD_1XL1_SCH,
+ CL1_PHYUT_MOD_1XL1_RLBSRP,
+ CL1_PHYUT_MOD_EVL1_FRONTEND,
+ CL1_PHYUT_MOD_1XL1_FRONTEND,
+ CL1_PHYUT_MOD_DUAL_MODE,
+ CL1_PHYUT_MOD_COSIM,
+ CL1_PHYUT_MOD_RXTIMER,
+ CL1_PHYUT_MOD_SLPCTRL,
+ CL1_PHYUT_MOD_NUM
+} Cl1PhyUtModIdT;
+
+typedef enum
+{
+ CL1_PHYUT_MOD_CASE_01,
+ CL1_PHYUT_MOD_CASE_02,
+ CL1_PHYUT_MOD_CASE_03,
+ CL1_PHYUT_MOD_CASE_04,
+ CL1_PHYUT_MOD_CASE_05,
+ CL1_PHYUT_MOD_CASE_06,
+ CL1_PHYUT_MOD_CASE_07,
+ CL1_PHYUT_MOD_CASE_08,
+ CL1_PHYUT_MOD_CASE_09,
+ CL1_PHYUT_MOD_CASE_10,
+ CL1_PHYUT_MOD_CASE_11,
+ CL1_PHYUT_MOD_CASE_12,
+ CL1_PHYUT_MOD_CASE_13,
+ CL1_PHYUT_MOD_CASE_14,
+ CL1_PHYUT_MOD_CASE_15,
+ CL1_PHYUT_MOD_CASE_16,
+ CL1_PHYUT_MOD_CASE_17,
+ CL1_PHYUT_MOD_CASE_18,
+ CL1_PHYUT_MOD_CASE_19,
+ CL1_PHYUT_MOD_CASE_20,
+ CL1_PHYUT_MOD_CASE_21,
+ CL1_PHYUT_MOD_CASE_22,
+ CL1_PHYUT_MOD_CASE_23,
+ CL1_PHYUT_MOD_CASE_24,
+ CL1_PHYUT_MOD_CASE_25,
+ CL1_PHYUT_MOD_CASE_26,
+ CL1_PHYUT_MOD_CASE_27,
+ CL1_PHYUT_MOD_CASE_28,
+ CL1_PHYUT_MOD_CASE_29,
+ CL1_PHYUT_MOD_CASE_30,
+ CL1_PHYUT_MOD_CASE_NUM
+} Cl1PhyUtModCaseIdT;
+
+typedef struct
+{
+ kal_uint32 OperationType; /* 0: off 1: on */
+ kal_uint32 RfMode; /* 0: RTT 1: EVDO */
+ kal_uint32 PathBmp; /* bit0: main bit1:div bit2:sec */
+ kal_uint32 RxAgcState; /* 0:FAST 1:STEADY 2:ICS 3:FHC */
+ kal_uint32 PwrMode; /* 0:HPM 1:LPM */
+ kal_int32 InitRssidBmQ5[3];
+} Cl1PhyUtParamRxAgcT;
+
+typedef struct
+{
+ kal_uint32 OperationType; /* 0: off 1: on */
+ kal_uint32 RfMode; /* 0: RTT 1: EVDO */
+ kal_uint32 PathBmp; /* bit0: main bit1:div bit2:sec */
+ kal_uint32 RxAgcState; /* 0:FAST 1:STEADY 2:ICS 3:FHC */
+ kal_uint32 PwrMode; /* 0:HPM 1:LPM */
+ kal_int32 InitRssidBmQ5[3];
+ kal_int32 FoeHz;
+
+} Cl1PhyUtParamAfcNcoT;
+
+typedef struct
+{
+ kal_uint32 OperationType; /* 0: off 1: on */
+ kal_uint32 RfMode; /* 0: RTT 1: EVDO */
+ kal_uint32 PathBmp; /* bit0: main bit1:div bit2:sec */
+ kal_uint32 RxAgcState; /* 0:FAST 1:STEADY 2:ICS 3:FHC */
+ kal_uint32 PwrMode; /* 0:HPM 1:LPM */
+ kal_int32 InitRssidBmQ5[3];
+ kal_uint32 NbifBmp;
+ kal_int32 FoeHz[3];
+
+} Cl1PhyUtParamAfcNbifT;
+
+typedef struct
+{
+ kal_uint32 ModeBmp; /* Bit0: 1X; Bit1: EVDO
+ 1: 1X only; 2: DO only; 3: 1X and DO */
+ kal_uint32 CaseBmp[2]; /* [0]: 1X; [1]: DO */
+} Cl1PhyUtParamRxTimerT;
+
+
+typedef struct
+{
+ kal_uint32 ModeBmp; /* Bit0: 1X; Bit1: EVDO
+ 1: 1X only; 2: DO only; 3: 1X and DO */
+ kal_uint32 CaseBmp[2]; /* [0]: 1X; [1]: DO */
+} Cl1PhyUtParamSlpCtrlT;
+
+
+typedef union
+{
+ kal_uint32 Reserved; /* Reserved */
+ Cl1PhyUtParamRxAgcT ParamRxAgc;
+ Cl1PhyUtParamAfcNcoT ParamAfcNco;
+ Cl1PhyUtParamAfcNbifT ParamAfcNbif;
+ Cl1PhyUtParamRxTimerT ParamRxTimer;
+ Cl1PhyUtParamSlpCtrlT ParamSlpCtrl;
+} Cl1PhyUtParamU;
+
+typedef struct
+{
+ Cl1PhyUtModIdT ModId;
+ Cl1PhyUtModCaseIdT CaseId; /* Case ID in module */
+ Cl1PhyUtParamU Param;
+} Cl1PhyUtTrigCmdT;
+#endif
+extern void Cl1TstPhyUtMsgHandler(void *pMsg);
+
+
+#endif /* #ifndef _CL1TSTPHYUTMAIN_H_ */
diff --git a/mcu/interface/l1/cl1/common/cph1xflbrp.h b/mcu/interface/l1/cl1/common/cph1xflbrp.h
new file mode 100644
index 0000000..1b61f0d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xflbrp.h
@@ -0,0 +1,413 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XFLBRP_H_
+#define _CPH1XFLBRP_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+#define XL1_SYNC_CORR_NUM 17
+
+typedef enum
+{
+ RTT_BRP_SYNC = 0,
+ RTT_BRP_PCH,
+ RTT_BRP_FCH,
+ RTT_BRP_ROLL_BACK
+} Cph1xBrpChSel;
+
+
+typedef struct
+{
+/******DBRP RTT SYNC/PCH/FCH Full rate PARAM1*******/
+ kal_uint16 IntlvSize;
+ kal_uint8 IntlvM;
+ kal_uint8 IntlvJM1;
+ kal_uint8 IntlvFbEn;
+}FchSchParam1T;
+
+typedef struct
+{
+/******DBRP RTT SYNC/PCH/FCH Full rate PARAM2*******/
+ kal_uint8 RepeatRate;
+ kal_uint8 PuncCfg;
+ kal_uint16 PuncPattern;
+ kal_uint16 EncodedBits;
+}FchSchParam2T;
+
+typedef struct
+{
+/******DBRP RTT SYNC/PCH/FCH Full rate PARAM3*******/
+ kal_uint16 CodeBlockSize;
+ kal_uint8 CrcSize;
+ kal_uint8 CodeRate;
+ kal_uint8 SetPt;
+}FchSchParam3T;
+
+typedef struct
+{
+ /***********************Full rata*******************/
+
+ FchSchParam1T FchChanFullParam1;
+ FchSchParam2T FchChanFullParam2;
+ FchSchParam3T FchChanFullParam3;
+
+ /*******************Half rata*********************/
+ FchSchParam2T FchChanHalfParam2;
+ FchSchParam3T FchChanHalfParam3;
+
+ /*******************Quarter rata*********************/
+ FchSchParam2T FchChanQuarterParam2;
+ FchSchParam3T FchChanQuarterParam3;
+
+/*******************Eighth rata*********************/
+ FchSchParam2T FchChanEighthParam2;
+ FchSchParam3T FchChanEighthParam3;
+}FchParamsT;
+
+
+typedef struct
+{
+ FchSchParam1T FschChanParam1;
+ FchSchParam2T FschChanParam2;
+ FchSchParam3T FschChanParam3;
+} SchChanParamT;
+
+
+typedef struct
+{
+ FchSchParam1T PchChanParam1;
+ FchSchParam2T PchChanParam2;
+ FchSchParam3T PchChanParam3;
+} PchChanParamT;
+
+typedef struct
+{
+ FchSchParam1T SyncChanParam1;
+ FchSchParam2T SyncChanParam2;
+ FchSchParam3T SyncChanParam3;
+} SyncChanParamT;
+
+/*****************************************************************************
+
+ DMA Vit Parameters
+
+*****************************************************************************/
+
+typedef struct
+{
+ kal_uint8 BitOffset;
+ kal_uint8 SwapEndian;
+ kal_uint8 CrcRemove;
+ kal_uint8 DmaDisable;
+}ChanDMACfgT;
+
+typedef struct
+{
+ kal_uint32 DbrpVitFchDmaFullBase;
+ kal_uint32 DbrpVitFchDmaHalfBase;
+ kal_uint32 DbrpVitFchDmaQuatBase;
+ kal_uint32 DbrpVitFchDmaEighBase;
+ kal_uint32 DbrpVitSchDmaBase;
+ ChanDMACfgT FchFullDmaCfg;
+ ChanDMACfgT SchDmaCfg;
+} DmaCfgT;
+
+typedef struct
+{
+ kal_uint8 CnfgPinSel;
+ kal_uint8 DataPingSel;
+}DbrpDmaCh3ReqT;
+
+typedef struct
+{
+ kal_uint8 Mode;
+ kal_uint8 Cnfg;
+ kal_uint8 Priority;
+ kal_uint8 AccIdx;
+ kal_uint16 BufIdx;
+}DbrpDmaCh3CtrlT;
+
+typedef struct
+{
+ kal_uint16 BaseAddrIdx;
+ kal_uint16 StartSampleIdx;
+}DbrpDmaCh3CtrlCnfgT;
+
+typedef struct
+{
+ kal_uint32 DbrpDmaCh3;
+ DbrpDmaCh3ReqT DbrpDmaCh3Req;
+ DbrpDmaCh3CtrlT DbrpDmaCh3Ctrl;
+ DbrpDmaCh3CtrlCnfgT DbrpDmaCh3CtrlCnfgPing;
+ DbrpDmaCh3CtrlCnfgT DbrpDmaCh3CtrlCnfgPong;
+ kal_uint32 DbrpDmaCh3CtrlCnfg;
+ DbrpDmaCh3CtrlCnfgT DbrpDmaCh3CtrlDataPing;
+ DbrpDmaCh3CtrlCnfgT DbrpDmaCh3CtrlDataPong;
+ kal_uint32 DbrpDmaCh3CtrlData;
+}DmaChannel3T;
+
+//turbo para
+typedef struct
+{
+ kal_uint8 MaxIter;
+ kal_uint8 MinIter;
+}DbrpTurRttCfgT;
+typedef struct
+{
+ kal_uint8 MacOfst;
+ kal_uint8 SwapEndian;
+ kal_uint8 CrcRemove;
+}DbrpTurRttDmaCfgT;
+
+typedef struct
+{
+ DbrpTurRttCfgT DbrpTurRttCfg;
+ kal_uint32 DbrpTurRttDst;
+ DbrpTurRttDmaCfgT DbrpTurRttDmaCfg;
+ kal_uint32 DbrpTurRttTraceCfg;
+}TurboParamesT;
+
+
+
+/*****************************************************************************
+
+ Control Parameters
+
+*****************************************************************************/
+typedef struct
+{
+ kal_uint8 FchDrmDone;
+ kal_uint8 SchDrmDone;
+ kal_uint8 FchDecDone;
+ kal_uint8 SchDecDone;
+ kal_uint8 CorrDone;
+}DbrpRttDoneVecT;
+
+typedef struct
+{
+ kal_uint8 CfgOk;
+ kal_uint8 CfgAssert;
+}DbrpRttCfgOkT;
+
+typedef struct
+{
+ kal_uint32 FchEn;
+ kal_uint32 SchEn;
+ kal_uint32 SchEncoding;
+}DbrpRttChDetT;
+
+typedef struct
+{
+ kal_uint32 ScaleMode;
+ kal_uint32 DereapScalMode;
+}DbrpRttScaleCfgT;
+
+typedef struct
+{
+ kal_uint8 ChSel;
+ kal_uint8 SyncBufIdx;
+ kal_uint8 SyncDrmEn;
+ kal_uint8 SyncCorrEn;
+ kal_uint8 SyncVitEn;
+}DbrpRttFchCfgT;
+
+typedef struct
+{
+ kal_uint16 EtPcgMap;
+ kal_bool EtEn;
+ kal_uint16 EtQuarPcg ;
+ kal_uint16 EtHalfPcg;
+ kal_uint16 EtFullPcg;
+}DbrpRttFchEtParmaT;
+
+
+typedef struct
+{
+ kal_uint32 DbrpRttStart;
+ kal_uint32 DbrpRttDone;
+ DbrpRttDoneVecT DbrpRttDoneVec;
+ DbrpRttCfgOkT DbrpRttCfgOk;
+ DbrpRttChDetT DbrpRttChDet;
+ DbrpRttScaleCfgT DbrpRttScalCfg;
+ DbrpRttFchCfgT DbrpRttFchCfg;
+ DbrpRttFchEtParmaT DbrpRttFchEtParam;
+}DbrpControlParamT;
+
+/*****************************************************************************
+
+ Vit Decode Parameters
+
+*****************************************************************************/
+
+typedef struct
+{
+ kal_bool Full;
+ kal_bool Half;
+ kal_bool Quat;
+ kal_bool Eigh;
+}VitFchCrcStatusT;
+
+
+typedef struct
+{
+ kal_uint32 Full;
+ kal_uint32 Half;
+ kal_uint32 Quat;
+ kal_uint32 Eigh;
+}VitFchSStatusT; /*End state metric(S-Value,S) 21bits,S*/
+
+typedef struct
+{
+ kal_uint32 Full;
+ kal_uint32 Half;
+ kal_uint32 Quat;
+ kal_uint32 Eigh;
+}VitFchYStatusT; /*yamamoto metric(Y) 11bits, YAMA*/
+
+typedef struct
+{
+ kal_uint32 Full;
+ kal_uint32 Half;
+ kal_uint32 Quat;
+ kal_uint32 Eigh;
+}VitFchHStatusT; /*Hypothesis Metric(H) 21bits,E*/
+
+
+typedef struct
+{
+ kal_uint32 Full;
+ kal_uint32 Half;
+ kal_uint32 Quat;
+ kal_uint32 Eigh;
+}VitFchSertatusT; /*SER 11bits,SER*/
+
+typedef struct
+{
+ kal_uint32 Full;
+ kal_uint32 Half;
+ kal_uint32 Quat;
+ kal_uint32 Eigh;
+}VitFchSoftSertatusT; /*Soft SER 11bits, PM*/
+
+
+typedef struct
+{
+ VitFchSStatusT FchS;
+ VitFchYStatusT FchY;
+ VitFchHStatusT FchH;
+ VitFchSertatusT FchSer;
+ VitFchSoftSertatusT FchSoftSer;
+ VitFchCrcStatusT FchCrc;
+ kal_uint32 SchCrc;
+}VitRdaParamT;
+
+
+typedef struct
+{
+ kal_uint32 DbrpVitReset;
+ kal_uint32 DbrpVitLva;
+ kal_uint32 DbrpVitPchConf;
+ kal_uint32 DbrpVitFirstFrm;
+ kal_uint32 DbrpVitSync;
+
+ kal_uint32 DbrpVitFchDmaFullBase;
+ kal_uint32 DbrpVitFchDmaHalfBase;
+ kal_uint32 DbrpVitFchDmaQuatBase;
+ kal_uint32 DbrpVitFchDmaEighBase;
+ kal_uint32 DbrpVitSchDmaBase;
+ ChanDMACfgT FchFullDmaCfg;
+ ChanDMACfgT SchDmaCfg;
+
+ VitRdaParamT DbrpRdaParmes;
+ kal_uint32 DbrpVitStatus ;
+ kal_uint32 DbrpVitDone;
+ kal_uint32 DbrpVitFchFullUsage; //debug used
+}VitChanParamT;
+
+typedef struct
+{
+ kal_uint8 MsgLength;
+ kal_uint8 CorrExtraEnable;
+}
+DbrpRttCorrPatternT;
+
+typedef struct
+{
+ kal_uint8 DbrpRttCorrBufIdx;
+ kal_uint16 DbrpRttCorrEnergy;
+ kal_int16 DbrpRttCorrRslt[XL1_SYNC_CORR_NUM];
+}BbrpRttCorrT;
+
+/*****************************************************************************
+
+ Function declaration
+
+*****************************************************************************/
+extern void Cph1xFlBrpSyncPchParamConfig(PchChanParamT *ads_ptr);
+extern void Cph1xFlBrpFchParamConfig(FchParamsT *ads_ptr);
+extern void Cph1xFlBrpFschParamConfig(SchChanParamT *ads_ptr);
+extern void Cph1xFlBrpCorrVitControlConfig(Cph1xBrpChSel ChSel,kal_uint8 BufIdx,kal_bool VitEn, kal_uint8 VitStartBufIdx,kal_bool CorrEn);
+extern void Cph1xFlBrpTurConfig(TurboParamesT *ads_ptr);
+extern void Cph1xFlBrpVitConfig(VitChanParamT *ads_ptr);
+extern void Cph1xFlBrpInputDmaConfig(DmaChannel3T *ads_ptr);
+extern void Cph1xFlBrpSyncSomRsltRead(BbrpRttCorrT *ads_ptr);
+extern void Cph1xFlBrpSyncCorrExtraEnable(kal_uint16 ExtraLen);
+extern void Cph1xFlBrpFchRdaRead(VitRdaParamT *RdaVitPtr);
+extern kal_uint32 Cph1xFlBrpVitDone();
+extern kal_uint32 Cph1xFlBrpCorrDone();
+extern kal_uint32 Cph1xFlBrpTurDone();
+extern kal_uint32 Cph1xFlBrpDrmDone();
+extern void Cph1xFlBrpDoneClr();
+extern void Cph1xFlBrpCfgDone();
+extern void Cph1xFlBrpFchCrcStateRead(VitFchCrcStatusT *ads_ptr);
+extern kal_uint32 Cph1xFlBrpSchVitCrcStateRead();
+extern kal_uint32 Cph1xFlBrpSchTurCrcStateRead();
+extern void Cph1xFlBrpEnConfig(DbrpRttChDetT *ads_ptr);
+extern void Cph1xFlBrpScaleConfig(DbrpRttScaleCfgT *ads_ptr);
+extern void Cph1xFlBrpEtParaConfig(DbrpRttFchEtParmaT *ads_ptr);
+extern void Cph1xFlBrpChSel(DbrpRttFchCfgT *ads_ptr);
+extern void Cph1xFlBrpFchCrcStateRead(VitFchCrcStatusT *ads_ptr);
+extern void Cph1xFlBrpCodeBlcokSizeCfg(kal_uint32 CodeBlockSize);
+extern void Cph1xFlBrpVitFirstFrmCfg(kal_bool FirstFrm);
+extern kal_uint32 Cph1xFlBrpDumpCh0Enerage();
+extern kal_uint32 Cph1xFlBrpDumpCh1Enerage();
+extern kal_uint32 Cph1xFlBrpDumpCh1TurEnerage();
+extern kal_uint32 Cph1xFlBrpDoneRead();
+extern kal_uint32 Cph1xFlBrpCfgDoneRead();
+extern kal_uint32 Cph1xFlBrpVitState();
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cph1xflbsrpregaccess.h b/mcu/interface/l1/cl1/common/cph1xflbsrpregaccess.h
new file mode 100644
index 0000000..25804e2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xflbsrpregaccess.h
@@ -0,0 +1,76 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPH1XFLBSRPREGACCESS_H_
+#define _CPH1XFLBSRPREGACCESS_H_
+
+
+#ifndef MTK_C2K_COSIM
+#undef HwdWrite32
+#undef HwdRead32
+#undef HwdClearBit32
+#undef HwdSetBit32
+
+#ifdef MTK_PLT_ON_PC
+#define HwdWrite32(Reg, data) Xl1FlBsrpRegWrite((HwdRegT)(Reg), data)
+#define HwdRead32(Reg) Xl1FlBsrpRegRead((HwdRegT)(Reg))
+#define HwdClearBit32(Reg,bit_mask) Xl1FlBsrpRegClearBit((HwdRegT)Reg,bit_mask)
+#define HwdSetBit32(Reg,bit_mask) Xl1FlBsrpRegSetBit((HwdRegT)Reg,bit_mask)
+#else
+#define HwdWrite32(Reg, data) Xl1FlBsrpRegWrite((volatile unsigned long*)(Reg), data)
+#define HwdRead32(Reg) Xl1FlBsrpRegRead((volatile unsigned long*)(Reg))
+#define HwdClearBit32(Reg,bit_mask) Xl1FlBsrpRegClearBit((volatile unsigned long*)Reg,bit_mask)
+#define HwdSetBit32(Reg,bit_mask) Xl1FlBsrpRegSetBit((volatile unsigned long*)Reg,bit_mask)
+#endif
+
+#endif /* #ifndef MTK_C2K_COSIM */
+
+
+#ifdef MTK_PLT_ON_PC
+extern void Xl1FlBsrpRegWrite(HwdRegT reg, kal_uint32 data);
+extern kal_int32 Xl1FlBsrpRegRead(HwdRegT reg);
+extern void Xl1FlBsrpRegClearBit(HwdRegT reg,kal_int32 bit_mask);
+extern void Xl1FlBsrpRegSetBit(HwdRegT reg,kal_int32 bit_mask);
+#else
+extern void Xl1FlBsrpRegWrite(volatile unsigned long* reg, kal_uint32 data);
+extern kal_int32 Xl1FlBsrpRegRead(volatile unsigned long* reg);
+extern void Xl1FlBsrpRegClearBit(volatile unsigned long* reg,kal_int32 bit_mask);
+extern void Xl1FlBsrpRegSetBit(volatile unsigned long* reg,kal_int32 bit_mask);
+#endif
+
+#endif /* #ifndef _CPH1XFLSRPREGACCESS_H_ */
+
+
+
diff --git a/mcu/interface/l1/cl1/common/cph1xflrake.h b/mcu/interface/l1/cl1/common/cph1xflrake.h
new file mode 100644
index 0000000..ff37a35
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xflrake.h
@@ -0,0 +1,463 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XFLRAKE_H_
+#define _CPH1XFLRAKE_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+#define D2BIF_WORK_AROUND_MORE_ANT 1
+
+//#define D2BIF_WORK_AROUND_T2_DISD2BIF 1
+
+
+#define SECTOR_NUM_1X 6
+#define FINGER_NUM_1X 8
+
+#define SPEED_UPPERROUND 0xff
+
+#define DEFAULT_T1_PCG (0)
+#define DEFAULT_T6_PCG (0)
+#define DEFAULT_T7_PCG (15)
+#if defined(__MD93__)||defined(__MD95__)
+#define BIGRAM_BASE_ADDR_L1 0xa9000000
+#endif
+
+#ifdef __MD97__
+#define BIGRAM_BASE_ADDR_L1 0xab000000
+#endif
+/*Rake Bootup*/
+typedef enum
+{
+ BOOT_UP_WCDMA_MODE = 0,
+ BOOT_UP_C2K_MODE
+} CphBootUpMode;
+
+
+/*Rake Generate*/
+typedef enum
+{
+ B2R_MODE_WCDMA,
+ B2R_MODE_C1X,
+ B2R_MODE_CDO,
+ B2R_MODE_SHDR
+} Cph1xB2RifMode;
+
+typedef enum
+{
+ D2B_MODE_WCDMA,
+ D2B_MODE_C1X,
+ D2B_MODE_CDO,
+ D2B_MODE_QLIC
+} Cph1xD2BifMode;
+
+
+/*Rake Generate*/
+typedef enum
+{
+ CPH_NULL_STATE = 0,
+ CPH_SYNC_STATE = 1,
+ CPH_IDLE_STATE = 2,
+ CPH_CONNECTED_STATE = 4
+} Cph1xL1dState;
+
+typedef enum
+{
+ DISABLE_MODE,
+ RTT_MODE,
+ EVDO_MODE,
+ SHDR_STATE
+} CphL1dMode;
+
+typedef enum
+{
+ ANT_MAIN_ONLY,
+ ANT_DIV_ONLY,
+ ANT_DIVERSITY,
+ ANT_SHDR,
+ ANT_DISABLE
+} CphAntMod;
+
+
+typedef enum
+{
+ CH_NULL = 0,
+ CH_PCH = 3,
+ CH_FCH = 3,
+ CH_SCH = 4,
+ CH_SYNC = 5
+} Cph1xCHType;
+
+typedef enum
+{
+ SF4 = 0,
+ SF8,
+ SF16,
+ SF32,
+ SF64,
+ SF128,
+ SF256
+} Cph1xSFType;
+
+
+typedef enum
+{
+ FNG_RELEASED = 0,
+ FNG_ACTIVATED,
+ FNG_OBSERVED
+} Cph1xFngStatus;
+
+typedef struct
+{
+ kal_bool QlicEn;
+ kal_uint32 T7Timing;
+}Cph1xFlRakeQlicCfgT;
+
+
+typedef struct
+{
+ /*For normal init*/
+ kal_uint32 T3Time; /*Uint is 1/8 chip*/
+ kal_uint32 T2Time; /*Uint is 1/8 chip*/
+ kal_uint16 T3Dist; /*Uint is 1/8 chip, last 7 bit not valid*/
+ /*from Rfc state*/
+ CphAntMod AntMode;
+ /*For shdr init*/
+ kal_uint16 PagingOffset;
+ kal_uint32 GsrSlotIndx;
+ kal_uint32 T3GsrAddr;
+
+ /*For all init*/
+ kal_uint8 T7SlotIdx;
+ /*uint is 100kHz*/
+ kal_uint16 DlCarrierFreq;
+ Cph1xL1dState L1dState1x;
+ kal_bool QlicEn;
+ kal_uint16 QlicDelay; /*EChip*/
+ kal_uint32 T7Timing;
+ kal_uint32 LcMask[2];
+ kal_uint32 LcState[2];
+ /*LcState timing*/
+ kal_uint32 LcFrame;
+ kal_uint8 LcPcg;
+ kal_uint8 Pich1xrttRshBit;
+ kal_uint8 FchRshBit;
+ /*Pilot on evdo chip*/
+ kal_uint32 PichOnDoChip;
+} Cph1xFlRakeInitT;
+
+
+
+typedef struct
+{
+ kal_uint8 T6SlotIdx;
+ kal_bool IsShdr;
+} Cph1xFlRakeDeactiveT;
+
+typedef struct
+{
+ kal_bool ChChange;
+ kal_bool ChEn;
+ Cph1xCHType Type;/*CH_TYPE: 1 PCH 2 SYNC 3 FCH */
+ kal_uint8 ForRc;
+ kal_uint8 RevRc;
+ kal_uint32 RshBit;
+ kal_uint16 PnOffset[SECTOR_NUM_1X];
+ kal_uint16 WalshCode[SECTOR_NUM_1X];
+ kal_uint8 QofCode[SECTOR_NUM_1X];
+ kal_uint8 PwrSecSetId[SECTOR_NUM_1X];
+ kal_uint8 Sf;/*0 SF4 1 SF8 ....6 SF 256*/
+ kal_uint16 CfgChangeBit;
+ kal_uint8 ValidBit;
+ kal_uint8 FrameOffset;
+ kal_uint8 Phch0RshBit;
+ kal_uint8 Phch2RshBit;
+} Cph1xFlRakeCh0T;
+
+typedef struct
+{
+ kal_bool ChChange;
+ kal_bool ChEn;
+ kal_uint8 ForRc;
+ kal_uint16 RshBit;
+ kal_uint16 WalshCode[SECTOR_NUM_1X];
+ kal_uint8 QofCode[SECTOR_NUM_1X];
+ kal_uint8 Sf; /*0 SF4 1 SF8 ....6 SF 256*/
+ kal_uint8 CfgChangeBit;
+ kal_uint8 ValidBit;
+ kal_uint8 FrameOffset;
+ kal_uint8 Phch1RshBit;
+} Cph1xFlRakeCh1T;
+
+
+typedef struct
+{
+ Cph1xFlRakeCh0T RakeCh0Cfg;
+ Cph1xFlRakeCh1T RakeCh1Cfg;
+} Cph1xFlRakeChCfgT;
+
+
+
+typedef struct
+{
+ CphAntMod AntMode;
+ kal_uint32 RefTimeEChip;
+ kal_uint32 RefGsrHChip;
+ kal_bool RefGsrSyncReadState;
+ kal_bool RefGsrTimingReadState;
+} Cph1xFlRakeGsrT;
+
+
+typedef struct
+{
+ kal_bool FngEnFlag;
+ kal_uint8 FngIdx;
+
+ kal_uint8 SecId;
+ kal_bool FngReassignFlag;
+ Cph1xFngStatus FngStatus;
+ kal_uint32 FngAddr;
+ kal_uint32 FngSymIdx;
+ kal_uint32 FngInitPower;
+
+ kal_int16 FngAccuDrift;
+ } Cph1xFlRakeFingerCfgT;
+
+typedef struct
+{
+ kal_uint16 PwrTshdA2OH;
+ kal_uint16 PwrTshdO2AH;
+} Cph1xFlRakeTrackerTshdCfgT;
+
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_uint8 FngAccuDrift;
+} Cph1xFlRakeTrackerDriftCfgT;
+
+typedef struct
+{
+ kal_bool RssiStableFlag;
+ kal_uint16 PreviousSpeedResult;
+} Cph1xFlRakeSpestT;
+
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_int8 FngAccuDrift;
+ kal_uint32 FngMicPower;
+ kal_uint8 FngStatus;
+} Cph1xFlRakeTrackerReadT;
+
+
+typedef struct
+{
+ kal_uint8 currSpeed;
+
+} Cph1xFlRakeCurrSpeedT;
+
+
+
+typedef struct
+{
+ kal_bool RxDFlag;
+} Cph1xFlRakeRxdT;
+
+
+
+typedef struct
+{
+ kal_bool OcEn;
+ kal_bool OcSelEn;
+ kal_uint16 OcSelSlotIdx;
+ kal_uint16 OcSelSymIdx;
+ kal_uint16 OcSelLength;
+}Cph1xFlRakeOcCfgT;
+
+
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_bool Enable;
+ kal_int32 FngPos[8]; // finger number
+}Cph1xFlRakeQlicFingerCfgT;
+
+
+typedef struct
+{
+ kal_bool Enable;
+ kal_uint32 ChEnState;
+ kal_uint32 ActionTimeChip;
+ kal_uint16 ValidBitFch;
+ kal_uint16 ValidBitSch;
+}Cph1xFlRakeCfsCfgT;
+
+
+typedef struct
+{
+ kal_bool FpcEnable;
+ kal_uint16 FpcMode;
+ kal_uint16 FwdRc; /*FWD RC:Rc1 1,RC2 2,...RC11 6, RC12 7*/
+ kal_uint16 RpcMode;
+ kal_uint16 RevRc;
+
+ kal_int32 FpcSubChanGain;
+ kal_bool FchSetPtIncl;
+ kal_int32 FchCurrSetPt;
+ kal_bool SchSetPtIncl;
+ kal_int32 SchCurrSetPt;
+
+}Cph1xFlRakePcModeCfgT;
+
+typedef struct
+{
+ kal_bool FchSetPtIncl;
+ kal_int32 FchCurrSetPt;
+ kal_bool SchSetPtIncl;
+ kal_uint32 SchCurrSetPt;
+}Cph1xFlRakePcSetPtCfgT;
+
+
+typedef struct
+{
+ kal_bool FchFpcValid;
+ kal_uint16 FchFpcDecision;
+ kal_int32 FchEbNt; /*PCG level*/
+
+ kal_bool SchFpcValid;
+ kal_uint16 SchFpcDecision;
+ kal_int32 SchEbNt; /*PCG level*/
+}Cph1xFlRakeFpcBitT;
+
+
+typedef struct
+{
+ kal_bool RpcValid;
+ kal_uint16 RpcDecision;
+ kal_uint16 Index;
+}Cph1xFlRakeRpcBitT;
+
+
+typedef struct
+{
+ kal_bool ChChange;
+ kal_uint16 FchAckMask;
+ kal_uint16 RevFchAckMask;
+ kal_uint32 RxSrpAckTsh;
+}Cph1xFlRakeAckCfgT;
+
+
+typedef struct
+{
+ kal_bool FoeReady;
+ kal_int32 FineFoe;
+ kal_uint32 SqPwr;
+
+}Cph1xFlRakeFoeReadT;
+
+typedef struct
+{
+ kal_uint32 IirPilotPwr;
+ kal_uint32 IirNoisePwr;
+ kal_uint32 IirPcbPwr;
+ kal_uint32 IirFschPwr;
+}Cph1xFlRakeSrpAlphaT;
+
+typedef struct
+{
+ kal_uint32 FchDecodeOK;
+ kal_uint32 FchDecodeUpdate;
+ kal_uint32 FschDecodeOK;
+ kal_uint32 FschDecodeUpdate;
+}Cph1xFlRakeSrpEibT;
+
+extern void Cph1xFlRakeInit(Cph1xFlRakeInitT *adsPtr);
+extern void Cph1xFlRakeShdrInit(Cph1xFlRakeInitT *adsPtr);
+extern kal_bool Cph1xFlRakeSleepIndRead();
+extern kal_bool Cph1xFlRakeStatusRead();
+extern void Cph1xFlRakeChannelDisable();
+extern void Cph1xRlRakeDeactive(Cph1xFlRakeDeactiveT *adsPtr);
+extern void Cph1xFlRakeDisableLoad();
+extern void Cph1xFlRakeDisableD2bifB2rif();
+extern void Cph1xFlRakeDisableA1C1(void);
+extern void Cph1xFlRakeCh0Config(Cph1xFlRakeCh0T *adsPtr);
+extern void Cph1xFlRakeCh1Config(Cph1xFlRakeCh1T *adsPtr);
+extern void Cph1xFlRakeCh2Config(Cph1xFlRakeCh0T *adsPtr);
+extern void Cph1xFlRakeGsrRead(Cph1xFlRakeGsrT *adsPtr);
+extern void Cph1xFlRakeT6Config(kal_uint8 T6SlotIdx);
+extern void Cph1xFlRakeT7Config(kal_uint8 T7SlotIdx);
+extern void Cph1xFlRakeFingerConfig(Cph1xFlRakeFingerCfgT *adsPtr);
+extern void Cph1xFlRakeTrackerRead(Cph1xFlRakeTrackerReadT *adsPtr);
+extern void Cph1xFlRakeTrackerInfo();
+extern void Cph1xFlRakeTrackerTshConfig(Cph1xFlRakeTrackerTshdCfgT *adsPtr);
+extern void Cph1xFlRakeTrackerConfig(Cph1xFlRakeTrackerDriftCfgT *adsPtr);
+extern void Cph1xFlRakeOcConfig(Cph1xFlRakeOcCfgT *adsPtr);
+extern void Cph1xFlRakeOCResultConfig(kal_bool OcSelEn);
+extern void Cph1xFlRakeSpestConfig(Cph1xFlRakeSpestT *adsPtr);
+extern void Cph1xFlRakeSpestForceConfig(kal_uint32 SpeedEstFinal);
+extern void Cph1xFlRakeSpestRead(Cph1xFlRakeCurrSpeedT *adsPtr);
+extern void Cph1xFlRakeRxdConfig(kal_bool Enable);
+extern kal_bool Cph1xFlRakeRxdCheck();
+extern void Cph1xFlRakeQlicConfig(kal_bool QlicEn, kal_uint32 T7Timing);
+extern void Cph1xFlRakeQlicFingerConfig(Cph1xFlRakeQlicFingerCfgT *adsPtr);
+extern void Cph1xFlRakeCfsConfig(Cph1xFlRakeCfsCfgT *adsPtr);
+extern void Cph1xFlRakeFpcModeConfig(Cph1xFlRakePcModeCfgT *adsPtr);
+extern void Cph1xFlRakeFpcSetPtConfig(Cph1xFlRakePcModeCfgT *adsPtr);
+extern void Cph1xFlRakeFpcBitRead(Cph1xFlRakeFpcBitT *adsPtr);
+extern kal_int32 Cph1xFlRakeSyncPchEbNtRead();
+extern void Cph1xFlRakeRpcBitRead(Cph1xFlRakeRpcBitT *adsPtr);
+extern void Cph1xFlRakeAckConfig(Cph1xFlRakeAckCfgT *adsPtr);
+extern kal_bool Cph1xFlRakeAckRead();
+extern void Cph1xFlRakeAckClr();
+extern void Cph1xFlRakeLongCodeMaskConfig(kal_uint32 *adsPtr);
+extern void Cph1xFlRakeLongCodeStateConfig(kal_uint32 *adsPtr);
+extern void Cph1xFlRakeLongCodeStateRead(kal_uint32 *adsPtr);
+extern void Cph1xFlRakeAfcRst();
+extern void Cph1xFlRakeAfcRead(Cph1xFlRakeFoeReadT *adsPtr);
+extern kal_uint32 Cph1xFlRakePilotEbNtRead();
+extern void Cph1xFlRakeSrpAlphaCfg(Cph1xFlRakeSrpAlphaT *adsPtr);
+extern void Cph1xFlRakeEibCfg(Cph1xFlRakeSrpEibT *adsPtr);
+extern kal_bool Cph1xFlRakeC1A1EnCheck();
+extern kal_bool Cph1xFlRakeC0A0EnCheck(void);
+extern void Cph1xFlRakeTrkInitCfg();
+extern void Cph1xFlRakeOcInitCfg();
+extern void Cph1xFlRakeTrkConfThCfg(kal_uint32 PwrTshdO2AH);
+extern void Cph1xFlRakeBigramDumpAccessEnable();
+extern kal_uint32 Cph1xFlRakeBigramIqAddress(CphAntMod AntMode);
+extern void Cph1xFlRakeShdrGsrRead(Cph1xFlRakeGsrT *adsPtr);
+#endif
diff --git a/mcu/interface/l1/cl1/common/cph1xrlbrp.h b/mcu/interface/l1/cl1/common/cph1xrlbrp.h
new file mode 100644
index 0000000..d92f737
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xrlbrp.h
@@ -0,0 +1,65 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XRLBRP_H_
+#define _CPH1XRLBRP_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+typedef struct
+{
+ kal_uint16 TxHaMode;
+ kal_uint16 TxIntrlvParm;
+ kal_uint16 FrepL;
+ kal_uint16 FrepLp;
+ kal_uint16 FrepLpml;
+ kal_uint16 FrepM;
+ kal_uint16 FrepAcc0;
+ kal_uint16 ChnlType;
+ kal_uint16 Crc;
+ kal_uint16 Punc;
+ kal_uint16 PuncPat0;
+ kal_uint16 PuncPat1;
+ kal_uint16 InputLen;
+ kal_uint16 TstCtrl;
+ kal_uint32 ChnlAddress;
+ kal_uint16 RTT_Start;
+} Cph1xRlBrpCfgT;
+
+void Cph1xRlBrpInit();
+void Cph1xRlBrpCfg(Cph1xRlBrpCfgT *CphBrpCfgPtr);
+kal_bool Cph1xRlBrpStatGet();
+void Cph1xRlBrpRegLog();
+#endif
diff --git a/mcu/interface/l1/cl1/common/cph1xrlcrp.h b/mcu/interface/l1/cl1/common/cph1xrlcrp.h
new file mode 100644
index 0000000..e297db0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xrlcrp.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XRLCRP_H_
+#define _CPH1XRLCRP_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+typedef enum
+{
+ CPH_RL_CRP_RAT_TYPE_INV = 0x0,
+ CPH_RL_CRP_RAT_TYPE_WCDMA = 0x1,
+ CPH_RL_CRP_RAT_TYPE_TD = 0x2,
+ CPH_RL_CRP_RAT_TYPE_NA = 0x4,
+ CPH_RL_CRP_RAT_TYPE_EVDO = 0x8,
+ CPH_RL_CRP_RAT_TYPE_1xRTT = 0x10,
+ CPH_RL_CRP_RAT_TYPE_MAX
+}CphRlCrpModeT;
+
+void CphRlCrpModeCfg(CphRlCrpModeT Mode);
+void Cph1xRlCrpInit();
+void Cph1xRlCrpStart();
+void Cph1xRlCrpStop(kal_uint16 StopByPcg);
+void Cph1xRlCrpLcInitCfg(kal_uint16 *LcInitPtr);
+void Cph1xRlCrpScInitCfg(kal_uint16 ScInitPcg);
+void Cph1xRlCrpLcMskCfg(kal_uint16 *LcMskPtr);
+kal_uint16 Cph1xRlCrpLcScramGet();
+void Cph1xRlCrpAckCfg(kal_uint16 AckBit);
+void Cph1xRlCrpFpcCfg(kal_uint16 FpcEibBit);
+void Cph1xRlCrpChnCtrlCfg(kal_uint16 TxCtrl, kal_uint16 FchStatus);
+void Cph1xRlCrpChnScaleCfg(kal_uint16 PilotScale, kal_uint16 FchScale, kal_uint16 SchScale, kal_uint16 AckScale);
+void Cph1xRlCrpKsStartCfg();
+kal_bool Cph1xRlCrpKsStatusGet();
+kal_int16 Cph1xRlCrpKsValueGet();
+void Cph1xRlCrpLatchModeCfg(kal_bool HpcgLatchEn);
+void Cph1xRlCrpCrcCheckCfg(kal_uint32 CrcLength);
+kal_uint32 Cph1xRlCrpCrcRead();
+void Cph1xRlCrpIs95Cfg(kal_bool Is95);
+void Cph1xRlCrpRegLog();
+#endif
diff --git a/mcu/interface/l1/cl1/common/cph1xrltmr.h b/mcu/interface/l1/cl1/common/cph1xrltmr.h
new file mode 100644
index 0000000..58c68b1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xrltmr.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XRLTMR_H_
+#define _CPH1XRLTMR_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+#define TX_TMR_WIDTH (0x100000) //20bits
+
+#ifdef __MD93__
+#define RTT_TXRXDELAY_INIT (278) //Same ase RFC_RTT_TRXPATH_DELAY
+#elif defined __MD95__
+#define RTT_TXRXDELAY_INIT (273) //Same ase RFC_RTT_TRXPATH_DELAY
+#else
+/**Used to Other Setting ,for example MD97*/
+#if defined(MT6297)
+#define RTT_TXRXDELAY_INIT (419) //Same as RFC_RTT_TRXPATH_DELAY
+#elif defined(MT6885)|| defined(MT6873)
+#define RTT_TXRXDELAY_INIT (402) //Same as RFC_RTT_TRXPATH_DELAY
+#else
+#define RTT_TXRXDELAY_INIT (402) //Same as RFC_RTT_TRXPATH_DELAY
+#endif
+
+#endif
+
+
+typedef enum
+{
+ TX_TMR_DLY_TYPE_FRAME_OFT = 0,
+ TX_TMR_DLY_TYPE_RTX,
+ TX_TMR_DLY_TYPE_RA,
+ TX_TMR_DLY_TYPE_MAX
+}Cph1xTxTmrDlyTypeT;
+
+typedef enum
+{
+ TX_TMR_WIN_TYPE_TXDFE = 0,
+ TX_TMR_WIN_TYPE_TXDFE_FIFO,
+ TX_TMR_WIN_TYPE_TXDAC,
+ TX_TMR_WIN_TYPE_MAX
+}Cph1xTxTmrWinTypeT;
+
+typedef enum
+{
+ TX_TMR_STB_TYPE_TXBRP = 0,
+ TX_TMR_STB_TYPE_TXCRP,
+ TX_TMR_STB_TYPE_KS,
+ TX_TMR_STB_TYPE_MAX
+}Cph1xTxTmrStbTypeT;
+
+
+void Cph1xTxTmrInit();
+void Cph1xTxTmrDlyCfg(Cph1xTxTmrDlyTypeT Type, kal_uint32 Delay);
+void Cph1xTxTmrWinCfg(Cph1xTxTmrWinTypeT Type, kal_bool IsOn, kal_uint32 WinTime);
+void Cph1xTxTmrStbCfg(Cph1xTxTmrStbTypeT Type, kal_uint32 StbTime);
+void Cph1xTxTmrKsPerTrig(kal_uint32 StbTime);
+void Cph1xTxFrmBdyOftCfg(kal_uint32 FrmBdyOffset);
+kal_uint32 Cph1xTxTmrCntGet();
+void Cph1xTxSysCntImmedRdEn();
+kal_uint32 Cph1xTxSysRaDlyGet();
+kal_uint32 Cph1xTxSysFrmOftGet();
+void Cph1xRlTmrRegLog();
+#endif
diff --git a/mcu/interface/l1/cl1/common/cph1xsch.h b/mcu/interface/l1/cl1/common/cph1xsch.h
new file mode 100644
index 0000000..611ca89
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xsch.h
@@ -0,0 +1,155 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+
+ FILE NAME: Cph1xsch.h
+
+ DESCRIPTION:
+
+ This include file provides searcher constants.
+
+*****************************************************************************/
+#ifndef _CPH1XSCH_H_
+#define _CPH1XSCH_H_
+
+#include "kal_general_types.h"
+
+#if (defined(MTK_C2K_COSIM))||(defined(MTK_C2K_L1_TST))
+#define SR1X_MAX_PAGES 12
+#else
+#define SR1X_MAX_PAGES 11
+#endif
+/* default register assignment, TBD */
+#define DEFAULT_CTL_REG 0
+#define DEFAULT_CORR_REG 0
+#define DEFAULT_NCOH_REG 0
+#define DEFAULT_AUXPILOT_REG 0
+#define DEFAULT_WIN_REG 0
+#define DEFAULT_D1TH_REG 0
+#define DEFAULT_TEST_REG 0
+#define DEFAULT_OFFSET_REG 0
+
+#define DWELL_LEN_MASK 0x3F
+#define DWELL2_CORR_SHIFT 6
+#define DWELL2_CNT_SHIFT 6
+#define SR1X_SINGLE_BUF_SZ 1024
+#define SR1X_DOUBLE_BUF_SZ 2048
+
+/* searcher constant */
+#define FULL_PN_CIR 32767 /* 2^15 - 1 */
+#define FULL_PN_CIR_2X 0 /* 2^16 = 0x10000 = (unit 16) 0 */
+#define SR1X_MAX_HITS 10
+#define DEFAULT_WIN_SIZ 32
+#define SR1X_SEARCHQ_SIZE 32
+#define SR1X_PN_BUF_SIZ 32
+#define SR1X_PN_BUF_SIZ_HALF (SR1X_PN_BUF_SIZ >> 1)
+#define SR1X_CIAQ_WIN_SIZE 1
+#define SR1X_FFT_SIZE 128
+#define SR1X_FFT_BIN_WTH_HZ 600
+
+/* Aflt Constant */
+#define SR1X_AFLT_SPY_PWR_BUF_SZ 55 // 1 + 3*10 + 3*8
+#define SR1X_AFLT_DBG_BUF_SZ (SYS_MAX_AFLT_LIST_PILOTS*9)
+#define SR1X_AFLT_1CHIP_UNIT_IN_TC16 16
+#define SR1X_AFLT_1CHIP_MASK_IN_TC16 (1 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1)
+#define SR1X_AFLT_2CHIP_MASK_IN_TC16 (2 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1)
+#define SR1X_AFLT_3CHIP_MASK_IN_TC16 (3 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1)
+
+/* Different or Candidate Frequency Search */
+#define SR1X_CFS_SRCH_VALID_MSK 0xC000
+#define SR1X_CFS_RSLT_DBG_SZ 15
+
+/** Input buffer test address, i.e. offset relative to input buffer start: valid value is 0~2047. */
+#define INBUF_TST_ADDR 0x0000
+
+typedef enum
+{
+ SCH_INPUT_SEL_C0A0,
+ SCH_INPUT_SEL_C0A1,
+ SCH_INPUT_SEL_C1A0,
+ SCH_INPUT_SEL_C1A1
+}SchInputSelT;
+
+typedef struct
+{
+ SchInputSelT SchInputSel;
+ kal_uint32 SchCtrlRegVal;
+ kal_uint32 SchCorrRegVal;
+ kal_uint32 SchNCohRegVal;
+ kal_uint32 SchAuxPilotRegVal;
+ kal_uint32 SchD1ThreshRegVal;
+ kal_uint32 SchAuxOffRegVal;
+ kal_uint32 SchTestRegVal;
+ kal_uint32 SchTest2RegVal;
+ kal_uint32 SchCtrl2RegVal;
+ kal_uint32 SchStatusRegVal;
+ kal_uint32 SchThresRegVal;
+ kal_uint32 SchInBufTstCtrlRegVal;
+ kal_uint32 SchInBufTstDataRegVal;
+}Cph1xSchHwCfgT;
+
+typedef struct
+{
+ kal_uint32 SchStartPnOffset;
+ kal_uint32 SchWinSize;
+}Cph1xSchWinCfgT;
+
+extern void Cph1xSchHwInit(kal_bool InitAll);
+extern void Cph1xSchHwReset(kal_bool ResetAll);
+extern void Cph1xSchHwCfg(Cph1xSchHwCfgT *AdsPtr);
+extern void Cph1xSchWinCfg(kal_uint32 PnNum, Cph1xSchWinCfgT *AdsPtr);
+extern void Cph1xSchFakeCfg(kal_bool Start);
+extern void Cph1xSchDlyStartEnable(kal_bool Enable);
+extern void Cph1xSchDlyStartTimeSet(kal_uint32 SysTime);
+extern kal_uint8 Cph1xSchObfStateGet(void);
+extern kal_uint8 Cph1xSchDoneStateGet(void);
+extern void Cph1xSchDoneStateClr(void);
+extern void Cph1xSchObfStateClr(void);
+extern kal_uint8 Cph1xSchMemShareBitGet(void);
+extern kal_bool Cph1xSchClockStateGet(void);
+extern void Cph1xSchRsltRead(kal_bool InitialAcq,
+ kal_bool UseSorter,
+ kal_bool TimeDomain,
+ kal_uint8 SchMode,
+ kal_uint16 *Buf1Ptr,
+ kal_uint16 *Buf2Ptr);
+extern void Cph1xSchIQDumpCfg(kal_uint16 StartOffset);
+extern void Cph1xSchIQDump(kal_uint16 *BufPtr, kal_uint16 IQLength);
+extern void Cph1xSchInputBufClr(void);
+extern void Cph1xSchInputBufDump(void);
+extern void Cph1xSchHwStallRegDump(void);
+extern void Cph1xSchRegValDump(void);
+#endif
diff --git a/mcu/interface/l1/cl1/common/cph1xschregaccess.h b/mcu/interface/l1/cl1/common/cph1xschregaccess.h
new file mode 100644
index 0000000..e013f0a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xschregaccess.h
@@ -0,0 +1,61 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XSCHREGACCESS_H_
+#define _CPH1XSCHREGACCESS_H_
+
+
+#ifndef MTK_C2K_COSIM
+#undef HwdWrite32
+#undef HwdRead32
+#ifdef MTK_PLT_ON_PC
+#define HwdWrite32(Reg, data) Xl1SchRegWrite((HwdRegT)(Reg), data)
+#define HwdRead32(Reg) Xl1SchRegRead((HwdRegT)(Reg))
+#else
+#define HwdWrite32(Reg, data) Xl1SchRegWrite((volatile unsigned long*)(Reg), data)
+#define HwdRead32(Reg) Xl1SchRegRead((volatile unsigned long*)(Reg))
+#endif
+#endif /* #ifndef MTK_C2K_COSIM */
+
+
+#ifdef MTK_PLT_ON_PC
+extern void Xl1SchRegWrite(HwdRegT reg, kal_uint32 data);
+extern kal_int32 Xl1SchRegRead(HwdRegT reg);
+#else
+extern void Xl1SchRegWrite(volatile unsigned long* reg, kal_uint32 data);
+extern kal_int32 Xl1SchRegRead(volatile unsigned long* reg);
+#endif
+
+
+#endif /* #ifndef _CPHEVDOFLSRPREGACCESS_H_ */
diff --git a/mcu/interface/l1/cl1/common/cphevdoflbrp.h b/mcu/interface/l1/cl1/common/cphevdoflbrp.h
new file mode 100644
index 0000000..e786168
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdoflbrp.h
@@ -0,0 +1,63 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHEVDOFLBRP_H_
+#define _CPHEVDOFLBRP_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+typedef struct
+{
+ kal_uint8 InterlaceId;/**Output*/
+ kal_uint8 CrcResult;/**Output:For Each interlace ID.*/
+ kal_uint16 EpSize; /**Output:For Each interlace ID.*/
+} CphEvdoFlBrpOutputAdsStruct;
+
+typedef struct
+{
+
+ kal_uint8 InterlaceId; /**Input: param for read.*/
+ kal_uint8 DrcIndex;/**Output*/
+ kal_uint8 CrcType;/**Output:0: CRC LEN=16; 1: CRC LEN=24; for each interlace ID.*/
+ kal_uint8 SlotCount;/**Output:For Each interlace ID.*/
+
+} CphEvdoFlBrpControllerReadAdsStruct;
+
+
+void CphEvdoFlBrpIntClear();
+void CphEvdoFlBrpConfig(kal_uint32 dmaAddress);
+void CphEvdoFlBrpOutput(CphEvdoFlBrpOutputAdsStruct *ads_ptr);
+void CphEvdoFlBrpControllerRead(CphEvdoFlBrpControllerReadAdsStruct *ads_ptr);
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphevdoflbsrpregaccess.h b/mcu/interface/l1/cl1/common/cphevdoflbsrpregaccess.h
new file mode 100644
index 0000000..0e850c7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdoflbsrpregaccess.h
@@ -0,0 +1,90 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPHEVDOFLBSRPREGACCESS_H_
+#define _CPHEVDOFLBSRPREGACCESS_H_
+
+
+#ifndef MTK_C2K_COSIM
+
+#define INCLUDE_DSP_HEADER_ENABLE_INNER_BRP
+#include "CUIF_inner_brp_ALL.h"
+#undef INCLUDE_DSP_HEADER_ENABLE_INNER_BRP
+
+#undef CUIF_READ
+#undef CUIF_WRITE
+
+#if defined(MTK_PLT_ON_PC_IT)
+extern CUIF_C2K_EVDO_REGS CphCuifRegs;
+#define CUIF_READ(reg) Evl1CuifRegRead((kal_uint32*)(&(CphCuifRegs.reg)))
+#define CUIF_WRITE(reg, val) Evl1CuifRegWrite((kal_uint32*)(&(CphCuifRegs.reg)), val)
+#else
+
+#define CUIF_READ(reg) Evl1CuifRegRead((kal_uint32*)(&(CUIF_C2K_EVDO->reg)))
+#define CUIF_WRITE(reg, val) Evl1CuifRegWrite((kal_uint32*)(&(CUIF_C2K_EVDO->reg)), val)
+#endif
+
+
+#undef HwdWrite32
+#undef HwdRead32
+#ifdef MTK_PLT_ON_PC
+#define HwdWrite32(Reg, data) Evl1FlBsrpRegWrite((HwdRegT)(Reg), data)
+#define HwdRead32(Reg) Evl1FlBsrpRegRead((HwdRegT)(Reg))
+#else
+#define HwdWrite32(Reg, data) Evl1FlBsrpRegWrite((volatile unsigned long*)(Reg), data)
+#define HwdRead32(Reg) Evl1FlBsrpRegRead((volatile unsigned long*)(Reg))
+
+#endif
+
+#endif /* #ifndef MTK_C2K_COSIM */
+
+void Evl1CuifRegWrite(kal_uint32* reg, kal_uint32 val);
+kal_uint32 Evl1CuifRegRead(kal_uint32* reg);
+
+#ifdef MTK_PLT_ON_PC
+extern void Evl1FlBsrpRegWrite(HwdRegT reg, kal_uint32 data);
+extern kal_int32 Evl1FlBsrpRegRead(HwdRegT reg);
+
+#else
+extern void Evl1FlBsrpRegWrite(volatile unsigned long* reg, kal_uint32 data);
+extern kal_int32 Evl1FlBsrpRegRead(volatile unsigned long* reg);
+
+#endif
+
+
+#endif /* #ifndef _CPHEVDOFLSRPREGACCESS_H_ */
+
+
+
diff --git a/mcu/interface/l1/cl1/common/cphevdoflsrp.h b/mcu/interface/l1/cl1/common/cphevdoflsrp.h
new file mode 100644
index 0000000..041dd9b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdoflsrp.h
@@ -0,0 +1,670 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHEVDOFLSRP_H_
+#define _CPHEVDOFLSRP_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+#define EVDO_MAX_NUM_PILOTS (6)
+#define EVDO_MAX_NUM_DATA_FINGERS (3)
+#define EVDO_MAX_NUM_MAC_FINGERS (12)
+#define EVDO_MAX_TOTAL_FINGERS (EVDO_MAX_NUM_DATA_FINGERS + EVDO_MAX_NUM_MAC_FINGERS)
+#define EVDO_MAX_NUM_PCG (6)
+#define EVDO_INVALID_SECTORID (0xFF)
+#define EVDO_INVALID_PCGID (0xFF)
+#define EVDO_INVALID_PNOFFSET (0xFFFF)
+#define EVDO_MAX_MACINDEX (127)
+#define EVDO_MAX_SPEED (200)
+#define T3_INIT_ADDR (0)
+#define DRC_REG_SIZE_M 15 /* DRC Offset is from 0 -14 */
+#define RXC_INTERLACE_LENGTH (4)
+#define EVDO_REV_A (0x02)
+
+
+#define BR_DMA_BASIC_ADDRESS (0xAB860000)
+#define BIGRAM_BASE_ADDRESS (0xA9000000)
+#define EVDO_INIT_SPEED (160)
+
+//#define C2K_RAKE_CMIF_REG_BASE 1
+
+/*Rake Generate*/
+typedef enum
+{
+ TRAFFIC_MODE_WCDMA,
+ TRAFFIC_MODE_1XRTT,
+ TRAFFIC_MODE_EVDO,
+ TRAFFIC_MODE_1XRTT_QLIC
+} CphEvl1TrafficMode;
+
+
+/*Rake Bootup*/
+typedef enum
+{
+ BOOT_UP_MODE_WCDMA = 0,
+ BOOT_UP_MODE_C2K
+} CphRakeBootUpMode;
+
+/*Rake State*/
+typedef enum
+{
+ EVL1_SYNC = 1,
+ EVL1_IDLE = 2,
+ EVL1_CONNECTED = 4
+} CphEvl1StateT;
+
+/*Rake Mode*/
+typedef enum
+{
+ RAKE_MODE_DISABLE = 0,
+ RAKE_MODE_1X,
+ RAKE_MODE_DO,
+ RAKE_MODE_SHDR
+} CphRakeMode;
+
+/*PMB CH type*/
+typedef enum
+{
+ PILOT_TRAFFIC_CH = 0,
+ PILOT_MAC_CH = PILOT_TRAFFIC_CH,
+ MAC_CH = 1,
+ RA_CH = MAC_CH,
+ PMB0_CH = 7,
+ PMB1_CH = PMB0_CH,
+ PMB2_CH = PMB0_CH,
+ PMB_FTC_CH = PMB0_CH,
+} CphEvl1ChType;
+
+
+/*Spreading factor*/
+typedef enum
+{
+ EVL1_SF4 = 0,
+ EVL1_SF8,
+ EVL1_SF16,
+ EVL1_SF32,
+ EVL1_SF64,
+ EVL1_SF128,
+ EVL1_SF256
+} CphEvl1SFType;
+
+/*Spreading factor*/
+typedef enum
+{
+ FINGER_NO_CHANGE = 0,
+ FINGER_ASSIGN,
+ FINGER_RELEASE
+} CphEvl1FngAllocAction;
+
+/*Spreading factor*/
+typedef enum
+{
+ FINGER_RELEASED = 0,
+ FINGER_ACTIVATED = 1,
+ FINGER_OBSERVED = 2,
+}Evl1FngStatusT;
+
+
+/* AFC_Mode */
+typedef enum
+{
+ AFC_FAST,
+ AFC_NORMAL
+} CphAfcModeT;
+
+
+typedef enum
+{
+ CONFIG_MU = 0x01,
+ CONFIG_DOF = 0x02,
+ CONFIG_PMB_MODE = 0x04,
+ CONFIG_MACINDEX = 0x08,
+ CONFIG_PD_RESET = 0x10,
+ CONFIG_PD_ENABLE = 0x20
+} CphEvl1FlSrpPdCfgType;
+
+typedef enum
+{
+ PD_MODE_INIT_ACQ,
+ PD_MODE_TRAFFIC,
+ PD_MODE_IDLE
+} CphEvl1FlSrpPdMode;
+
+
+typedef enum
+{
+ DRC_TABLE_INIT = 0x01,
+ DRC_SLMS_INIT = 0x02,
+ DRC_SW_PARA_INIT = 0x04,
+ DRC_REINIT = 0x08
+} CphEvl1FlSrpDrcInitType;
+
+
+typedef enum
+{
+ EVENT_DRC_INIT = 0x01,
+ EVENT_DRC_CFG = 0x02,
+ EVENT_DRC_TABLE_UPDATE =0x04
+} CphEvl1FlSrpDrcEventType;
+
+
+typedef enum
+{
+ CFG_DRC_LEN = 0x01,
+ CFG_DRC_GATING = 0x02,
+ CFG_FIX_TX_RATE = 0x04,
+ CFG_FIX_TX_RATE_DISABLE =0x08,
+ CFG_GLOBAL_BYPASS = 0x10,
+ CFG_ADJ_C2I_LEVEL_LENGTH = 0x20,
+ CFG_GlOBAL_ADJ = 0x40,
+ CFG_PREDICTION = 0x80,
+ CFG_DRC_RANGE = 0x100
+} CphEvl1FlSrpDrcCfgType;
+
+
+typedef struct
+{
+ /** [In]*/
+ CphEvl1StateT Evl1State;
+ /** [In]*/
+ kal_uint32 RxPath;
+ /** [In]*/
+ kal_uint32 Evl1Subtype;
+ /** [In]*/
+ kal_uint32 T3Dist;
+ /** [In]*/
+ kal_uint32 DLCarrierFreq;
+ /** [In]*/
+ kal_uint32 T3Time;
+ /** [In]*/
+ kal_uint32 T2Time;
+ /** [In]*/
+ kal_uint32 CpichOnTime;
+ /** [In] */
+ kal_bool Evl1Enabled;
+}CphEvl1RakeStartT;
+
+
+typedef struct
+{
+ kal_uint16 PilotPN;
+ kal_uint16 PwrEst;
+ kal_uint8 PcgId;
+ kal_uint8 ServCell;
+ kal_uint8 MacId;
+ kal_uint8 MacWalshId;
+ kal_uint8 RABLength;
+ kal_uint8 RABOffset;
+ kal_uint8 RAChannelGain;
+ kal_uint8 Res;
+}RakeSectorInfoT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_bool PmbFtcCfgChange;
+ /** [In]*/
+ kal_uint8 MacCfgChange;
+ /** [In]*/
+ kal_uint8 ServingSecId;
+ /** [In]*/
+ kal_uint16 ServingPN;
+ /** [In]*/
+ kal_uint16 UserMacIdx;
+ /** [In]*/
+ kal_uint16 CcShortPktIdx;
+ /** [In]*/
+ kal_uint8 NumSec;
+ /** [In]*/
+ kal_uint8 SecRenumId[EVDO_MAX_NUM_PILOTS];
+ /** [In]*/
+ RakeSectorInfoT SectorInfo[EVDO_MAX_NUM_PILOTS];
+}CphEvl1RakeChT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint8 FngIdx;
+ /** [In]*/
+ kal_uint8 SecId;
+ /** [In]*/
+ CphEvl1FngAllocAction Action;
+ /** [In]*/
+ Evl1FngStatusT FngStatus;
+ /** [In]*/
+ kal_uint16 FngAddr;
+ /** [In]*/
+ kal_uint16 FngSymIdx;
+ /** [In]*/
+ kal_uint32 FngInitPower;
+ } CphEvl1RakeFngCfgT;
+
+typedef struct
+{
+ /** [Out]*/
+ kal_uint32 RefTimeEchip;
+ /** [Out]*/
+ kal_uint32 RefGsrAddr;
+}CphEvl1FlSrpGsrT;
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_uint16 FngSnr;
+} CphEvl1RakeFngSNRResultT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_bool RssiStableFlag;
+ /** [In]*/
+ kal_uint8 PrevSpeedResult;
+ /** [Out]*/
+ kal_uint8 FinalSpeed;
+} CphEvl1SpestCfgT;
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_int8 FngAccDriftValue;
+}AccDriftT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_int16 A2OPilot;
+ /** [In]*/
+ kal_int16 O2APilot;
+ /** [In]*/
+ kal_int16 A2OMac;
+ /** [In]*/
+ kal_int16 O2AMac;
+ /** [In]*/
+ kal_uint8 NumFngUpd;
+ /** [In]*/
+ AccDriftT AccDrift[EVDO_MAX_TOTAL_FINGERS];
+}CphEvl1TrackerCfgT;
+
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint8 FngIdx;
+ /** [Out]*/
+ kal_uint8 FngStatus;
+ /** [Out]*/
+ kal_int8 FngAccuDrift;
+ /** [Out]*/
+ kal_uint32 FngMicPower;
+} CphEvl1TrackerResultT;
+
+
+typedef struct
+{
+ kal_bool RcpDbgEn; /* 1->RCP subchannel in Debug mode, 0->normal mode */
+ kal_bool RcpDbgVal;
+ kal_bool ArqDbgEn; /* 1->H/LARQ subchannel in Debug mode, 0->normal mode */
+ kal_bool ArqDbgVal;
+}Evl1McdDebugParamT;
+
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint8 DrcLockPeriod;
+ /** [In]*/
+ kal_uint8 DrcLockLen;
+ /** [In]*/
+ kal_uint8 ArqMode;
+ /** [In]*/
+ kal_uint8 ArqType;
+ /** [In]*/
+ kal_uint8 FrabTc;
+ /** [In]*/
+ kal_uint8 QrabTc;
+ /** [In]*/
+ Evl1McdDebugParamT McdDbgData; /* 1->RCP subchannel in Debug mode, 0->normal mode */
+}CphEvl1BsrpMcdInfoT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint8 NextArqtype;
+} CphEvl1McdArqTypeCfgT;
+
+
+typedef struct
+{
+ /** [In]*/
+ kal_bool ParqValid;
+ /** [In]*/
+ kal_uint8 RtcMacSubType;
+ /** [In]*/
+ kal_uint8 NumSec;
+ /** [In]*/
+ kal_uint8 NumPcg;
+ /** [In]*/
+ kal_uint8 SecRenumId[EVDO_MAX_NUM_PILOTS];
+ /** [In]*/
+ kal_uint8 PcgRenumId[EVDO_MAX_NUM_PCG];
+} CphEvl1McdGetMacBitsInputT;
+
+typedef struct
+{
+ /** [Out]*/
+ kal_int16 RAB; /* <13,1,t> for SoftRAB(MAC subtype 0/1), <16,15,t> for RAB(MAC subtype 2/3) */
+ /** [Out]*/
+ kal_uint8 SlotRAB; /* [0], hard limited RAB */
+ /** [Out]*/
+ kal_uint8 SlotQRAB; /* [0], subframe rate sampling */
+ /** [Out]*/
+ kal_int32 SlotFRAB; /* <13,1,t>, subframe rate sampling */
+} CphMacBitsSectorT;
+
+typedef struct
+{
+ /** [Out]*/
+ kal_uint8 DRCLockPcg; /* 0->UnLock, 1->Lock */
+ /** [Out]*/
+ kal_uint8 DRCLockPcgFinal; /* Final value after persistence test, 0->UnLock, 1->Lock */
+ /** [Out]*/
+ kal_uint8 DRCLockCounter; /* for persistence test */
+ /** [Out]*/
+ kal_uint8 HLARQBitPcg; /* 1->ACK, 0->NAK */
+ /** [Out]*/
+ kal_int32 DRCLockMetric; /* DRCLock metric, check sign for decision */
+ /** [Out]*/
+ kal_int32 HLARQMetric; /* [20:0], at subframe rate */
+ /** [Out]*/
+ kal_int32 PARQMetric; /* [20:0], at subframe rate */
+ /** [Out]*/
+ kal_uint32 CIMetric; /* [21:0], C/I metric at subframe rate */
+} CphMacBitsPCGT;
+
+typedef struct
+{
+ /** [Out]*/
+ kal_uint8 RABValid; /* 0/1->NotValid/Valid, Valid occurs every slot T mod RABLengthn = RABOffsetn-1 */
+ /** [Out]*/
+ kal_uint8 DRCLockValid; /* 0->NotVal, 1->Valid, Valid occurs every */
+ /* slot (T-FrameOffset) mod DRCLockPeriod x DRCLockLength */
+ /* = (DRCLockPeriod -1) x DRCLockLength */
+ /* For Rev A. DRCLockPeriod = 4 */
+ /** [Out]*/
+ kal_uint8 HLARQBit; /* H/LARQ Bit combined over the PCGs */
+ /* 1->ACK, 0->NAK */
+ /** [Out]*/
+ kal_uint8 RPCValid; /* 0->NotVal, 1->Valid, Valid occurs every */
+ /** [Out]*/
+ kal_uint8 RPCBit; /* 0->up, 1->down*/
+ /** [Out]*/
+ kal_uint8 QRAB; /* QRAB Hard value combined (logical OR) over all sectors */
+ /** [Out]*/
+ kal_int32 FRAB; /* FRAB for current subframe combined (max among) over all sectors */
+ /** [Out]*/
+ kal_int32 oldFRAB; /* FRAB for previous subframe combined (max among) over all sectors */
+ /** [Out]*/
+ CphMacBitsSectorT Sector[EVDO_MAX_NUM_PILOTS];
+ /** [Out]*/
+ CphMacBitsPCGT Pcg[EVDO_MAX_NUM_PCG];
+}CphEvl1McdGetMacBitsOutputT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_bool muEnable;
+ /** [In]*/
+ kal_uint8 dof;
+ /** [In]*/
+ kal_uint16 pmbCtrlInitTraffic;
+ /** [In]*/
+ kal_uint8 pmbMode;
+ /** [In]*/
+ kal_uint8 macIndex;
+ /** [In]*/
+ kal_uint16 pmbCtrl;
+ /** [In]*/
+ kal_uint16 pmbEnablePmabM;
+}CphEvl1PdCtxT;
+
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint8 initBitmap;
+ /** [In]*/
+ kal_uint16 cfgBitmap; /*indicate the configuration type*/
+ /** [In]*/
+ kal_int32 drcC2IMax;
+ /** [In]*/
+ kal_int32 drcC2IMin;
+ /** [In]*/
+ kal_int32 drcGlobalAdj;
+ /** [In]*/
+ kal_bool globalByPass;
+ /** [In]*/
+ kal_int32 slmsInit[5];
+ /** [In]*/
+ kal_int32 drcThrByPass1;
+ /** [In]*/
+ kal_int32 drcThrByPass2;
+ /** [In]*/
+ kal_int32 drcSlmsMu;
+ /** [In]*/
+ kal_int32 drcIIrPole;
+ /** [In]*/
+ kal_int32 drcErrIIrPole;
+ /** [In]*/
+ kal_uint8 drcLength;
+ /** [In]*/
+ kal_bool drcGating;
+ /** [In]*/
+ kal_int32 drcLvcrossLen;
+ /** [In]*/
+ kal_uint8 fixTxDrc;
+ /** [In]*/
+ kal_uint16 drcMode;
+ /** [In]*/
+ kal_int32 drcCtrl;
+ /** [In]*/
+ kal_uint16 pmbEnablePmabM;
+ /** [In]*/
+ kal_uint32 *pDrcOffset;
+ /** [In]*/
+ kal_int32 *pDrcC2IThr;
+ /** [In]*/
+ kal_uint32 *pDrcThrPut;
+ /** [In]*/
+ kal_uint32 *pDrcThrAwgn;
+ /** [In]*/
+ kal_bool bDrcRangeFlag;
+ /** [In]*/
+ kal_uint32 maxDrcValue;
+ /** [In]*/
+ kal_uint32 minDrcValue;
+}CphEvl1DrcCtxT;
+
+
+typedef struct
+{
+ /** [Out]*/
+ kal_uint8 timeStamp;
+ /** [Out]*/
+ kal_bool reackFlag;
+ /** [Out]*/
+ kal_uint8 supMacindex;
+ /** [Out]*/
+ kal_uint8 preambleMacindex;
+ /** [Out]*/
+ kal_uint8 interlaceId;
+} CphEvl1RxcPacketInfoReadT;
+
+typedef struct
+{
+ /** [Out]*/
+ kal_bool interlaceStatus[RXC_INTERLACE_LENGTH];
+} CphEvl1RxcInterlaceStatusReadT;
+
+
+typedef struct
+{
+ /** [In]*/
+ kal_bool crcResultInterlace;
+ /** [In]*/
+ kal_uint8 interlaceId;
+} CphEvl1RxcPacketCrcResultT;
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint8 CntAcc;
+ /** [In]*/
+ kal_uint32 SNRAcc;
+ /** [In]*/
+ kal_int32 ReFineAcc;
+ /** [In]*/
+ kal_int32 ImFineAcc;
+ /** [In]*/
+ kal_int32 ReCoarseAcc;
+ /** [In]*/
+ kal_int32 ImCoarseAcc;
+} CphEvl1AfcAccMetricT;
+
+
+typedef struct
+{
+ /** [In]*/
+ kal_uint16 PreSnr1; /**Pre SNR 1 from CE, floating point 1/5/10 format*/
+ /** [In]*/
+ kal_uint16 PreSnr2; /**Pre SNR2 RXD from CE, floating point 1/5/10 format*/
+}CphEvl1CePreSnrT;
+
+
+typedef struct
+{
+ kal_bool RESET_EN;
+ kal_bool EQ_MODE_L1_EN;
+ kal_uint32 EQ_MODE;
+ kal_bool MMSE_FLAG_L1_EN;
+ kal_uint32 MMSE_FLAG;
+ kal_bool ITER_NUM_L1_EN;
+ kal_uint32 ITER_NUM;
+ kal_bool ALPHA_FILTER_MODE_L1_EN;
+ kal_uint32 ALPHA_FILTER_MODE;
+ kal_bool DATA_FTM_L1_EN;
+ kal_uint32 DATA_FRAC;
+ kal_uint32 C2I_FRAC;
+ kal_bool PRE_COURSE_L1_EN;
+ kal_uint32 PRE_COURSE;
+ kal_bool CORR_LEN_L1_EN;
+ kal_uint32 CORR_LEN;
+ kal_bool ALPHA_SHIFT_L1_EN;
+ kal_uint32 ALPHA_SHIFT;
+ kal_bool WIN_ADD_BD_L1_EN;
+ kal_uint32 WIN_ADD_BD;
+ kal_bool PD_MATRIX_NOISE_L1_EN;
+ kal_uint32 PD_MATRIX_NOISE;
+}CphEvl1CuifCfgParamT;
+
+void CphEvl1FlSrpRakeCmifReset(void);
+void CphEvl1FlSrpRakeStart(CphEvl1RakeStartT *adsPtr);
+void CphEvl1FlSrpRakeRestore(CphEvl1RakeStartT *adsPtr);
+void CphEvl1FlSrpIdRegDump(kal_uint32 *ads_ptr);
+void CphEvl1FlSrpCgRegDump(kal_uint32 *ads_ptr);
+void CphEvl1FlSrpRakeCphichOn(kal_uint32 CpichOnTime);
+void CphEvl1FlSrpRakeDeactive(kal_uint8 T5SlotIdx);
+void CphEvl1FlSrpRakeEnterDormantDleep(void);
+void CphEvl1FlSrpD2bifOff(void);
+void CphEvl1FlSrpRakeStateCfg(CphEvl1StateT Evl1State);
+void CphEvl1FlSrpRakeSubTypeCfg(kal_uint32 Evl1Subtype);
+void CphEvl1FlSrpRakeT5Cfg(kal_uint8 T5SlotIdx);
+void CphEvl1FlSrpRakeChCfg(CphEvl1StateT Evl1State, CphEvl1RakeChT *adsPtr);
+void CphEvl1FlSrpRakeFngCfg(CphEvl1RakeFngCfgT *adsPtr);
+void CphEvl1FlSrpTargetSectorCfg(kal_bool CellSwEnFlag, kal_uint8 TargetSectorId);
+kal_bool CphEvl1FlSrpCsmEnCheck(void);
+void CphEvl1FlSrpRakeTxFrameOffsetCfg(kal_uint16 TxFrameOffset);
+kal_uint16 CphEvl1FlSrpFngTotalSNRRead(void);
+kal_uint32 CphEvl1FlSrpFngSNRRead(kal_uint8 FngIdx);
+kal_uint32 CphEvl1FlSrpFngRxDSNRRead(kal_uint8 FngIdx);
+void CphEvl1FlSrpTrackerCfg(CphEvl1TrackerCfgT *adsPtr);
+void CphEvl1FlSrpTrackerResultRead(CphEvl1TrackerResultT*adsPtr);
+void CphEvl1FlSrpSpestCfg(CphEvl1SpestCfgT *adsPtr);
+kal_uint32 CphEvl1FlSrpCurrSpeedRead(void);
+void CphEvl1FlSrpRxdCfg(kal_bool RxDEn);
+void CphEvl1FlSrpOCOnCfg(kal_bool OcEnFlag);
+void CphEvl1FlSrpMcdStart(kal_uint32 MacSubType, CphEvl1BsrpMcdInfoT *adsPtr);
+kal_uint8 CphEvl1FlSrpMcdHlArqRead( void );
+void CphEvl1FlSrpMcdArqTypeCfg(kal_uint8 NextArqType);
+void CphEvl1FlSrpMcdDbgCfg(Evl1McdDebugParamT *adsPtr);
+void CphEvl1FlSrpMcdMacBitsRead(CphEvl1McdGetMacBitsInputT *adsPtrIn, CphEvl1McdGetMacBitsOutputT *adsPtrOut);
+void CphEvl1FlSrpUsipCfg(kal_bool UsipEnFlag);
+void CphEvl1FlSrpUsipMacIndexCfg(kal_uint8 SupMacIndex);
+void CphEvl1FlSrpPdEnable(kal_bool enable , void *adsPtr);
+void CphEvl1FlSrpPdConfig(CphEvl1FlSrpPdCfgType cfgType, void *adsPtr);
+void CphEvl1FlSrpDrcInit(CphEvl1FlSrpDrcInitType initType, void *adsPtr);
+void CphEvl1FlSrpDrcConfig(CphEvl1FlSrpDrcCfgType cfgType, void *adsPtr);
+void CphEvl1FlSrpDrcTableUpdate(void *adsPtr);
+kal_int32 CphEvl1FlSrpDrcRegRead(APBADDR32 regAddr);
+void CphEvl1FlSrpDrcRegWrite(APBADDR32 regAddr, kal_int32 regVal);
+void CphEvl1FlSrpRxcInitialTimeConfig(kal_uint32 timeStamp);
+void CphEvl1FlSrpRxcCrcResultConfig(CphEvl1RxcPacketCrcResultT *adsPtr);
+void CphEvl1FlSrpRxcPacketInfoRead(CphEvl1RxcPacketInfoReadT *adsPtr);
+void CphEvl1FlSrpRxcInterlaceStatusRead(CphEvl1RxcInterlaceStatusReadT *adsPtr);
+void CphEvl1FlSrpAfcAccRead(CphEvl1AfcAccMetricT *adsPtr);
+kal_bool CphEvl1FlSrpAfcBusyChk(void);
+void CphEvl1FlSrpAfcRst(void);
+void CphEvl1FlSrpAfcLock(void);
+void CphEvl1FlSrpAfcUnLock(void);
+void CphEvl1FlSrpAfcModeCfg(CphAfcModeT AfcMode);
+void CphEvl1FlSrpPreSNRRead(CphEvl1CePreSnrT *CESnr);
+kal_uint16 CphEvl1FlSrpPostSNRRead(kal_uint8 InterlaceId);
+void CphEvl1FlSrpC2iMuCfg(kal_uint32 IirTime);
+kal_uint16 CphEvl1FlSrpC2iSamplCntGet(kal_uint8 SecId);
+void CphEvl1FlSrpC2iLogRlstGet(kal_uint8 SecId, kal_int16 *C2iLog0y, kal_int16 *C2iLog1y);
+kal_uint8 CphEvl1FlSrpSupMacIndexRead(kal_uint8 InterlaceId);
+kal_uint32 CphEvl1FlSrpFnSlotOffsetRead(void);
+kal_uint8 CphEvl1FlSrpSubTypeRead(void);
+kal_uint16 CphEvl1FlSrpDrcC2iShortRead(void);
+kal_uint16 CphEvl1FlSrpDrcC2iLongRead(void);
+kal_uint8 CphEvl1FlSrpDrcValueRead(void);
+kal_uint8 CphEvl1FlSrpUserMacIndexRead(void);
+extern void CphEvl1FlSrpGsrRead(CphEvl1FlSrpGsrT *adsPtr);
+extern kal_uint32 CphEvl1FlSrpFngEnRead();
+extern kal_uint32* CphEvl1FlSrpCalBigRAMAddr(void);
+extern void CphEvl1FlSrpRxcConfigMinContSpan(kal_uint8 MinContSpan);
+extern void CphEvl1FlSrpCuifCfg(CphEvl1CuifCfgParamT *adsPtr);
+extern void CphEvl1FlSrpTimingAdjCfg(kal_int16 TimeAdjEchip);
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/cphevdorlbrp.h b/mcu/interface/l1/cl1/common/cphevdorlbrp.h
new file mode 100644
index 0000000..d2672e5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdorlbrp.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RLBRP_H_
+#define _CPH_EVDO_RLBRP_H_
+
+
+#include "cl1common.h"
+
+#include "kal_general_types.h"
+#include "cphevdorlcomdef.h"
+
+
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+typedef enum
+{
+ BRP_SWAP_FORMAT4 = 0,
+ BRP_SWAP_FORMAT1 = 1,
+ BRP_SWAP_FORMAT2 = 2,
+ BRP_SWAP_FORMAT3 = 4
+} CphEvdoRlBrpSwapTypT;
+
+
+typedef struct
+{
+ kal_bool HwTrig;
+ CphEvdoComCnhlTypT ChnlTyp;
+ CphEvdoComAccPrtclTypT AccPrtclSbTyp;
+ CphEvdoComTrffcPrtclTypT RtcPrtclSbtyp;
+ CphEvdoRlBrpSwapTypT SwapTyp;
+} CphEvdoRlBrpInitT;
+
+
+typedef struct
+{
+ kal_bool Enable;
+} CphEvdoRlBrpEnT;
+
+
+typedef struct
+{
+ kal_uint16 AccData;
+ kal_uint16 TrffcSbtyp01Data;
+ kal_uint16 TrffcSbtyp2DataAck;
+ kal_uint16 TrffcSbtyp2DataNak;
+
+ kal_uint32 PacketDataAddr;
+ kal_uint32 PacketDataAddrNak;
+
+} CphEvdoRlBrpDataCfgT;
+
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+void CphEvdoRlBrpInit(CphEvdoRlBrpInitT *AdsPtr);
+void CphEvdoRlBrpReset(void);
+void CphEvdoRlBrpEn(CphEvdoRlBrpEnT *AdsPtr);
+void CphEvdoRlBrpSwTrig(void);
+void CphEvdoRlBrpDataCfg(CphEvdoRlBrpDataCfgT *AdsPtr);
+void CphEvdoRlBrpSwInterlaceEn(kal_uint8 Interlace);
+void CphEvdoRlBrpSwInterlaceDisEn(void);
+void CphEvdoRlBrpDegugCrcEn(void);
+void CphEvdoRlBrpDegugCrcRead(kal_uint32 *BrpCrcI,kal_uint32 *BrpCrcQ);
+CphEvdoComCnhlTypT CphEvdoRlBrpChnlTypeGet();
+void CphEvdoRlBrpModeSel();
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphevdorlbsrpregaccess.h b/mcu/interface/l1/cl1/common/cphevdorlbsrpregaccess.h
new file mode 100644
index 0000000..ad124bb
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdorlbsrpregaccess.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPHEVDORLBSRPREGACCESS_H_
+#define _CPHEVDORLBSRPREGACCESS_H_
+
+
+#ifndef MTK_C2K_COSIM
+#undef HwdWrite32
+#undef HwdRead32
+#ifdef MTK_PLT_ON_PC
+#define HwdWrite32(Reg, data) Evl1RlBsrpRegWrite((HwdRegT)(Reg), data)
+#define HwdRead32(Reg) Evl1RlBsrpRegRead((HwdRegT)(Reg))
+#else
+#define HwdWrite32(Reg, data) Evl1RlBsrpRegWrite((volatile unsigned long*)(Reg), data)
+#define HwdRead32(Reg) Evl1RlBsrpRegRead((volatile unsigned long*)(Reg))
+
+#endif
+
+#endif /* #ifndef MTK_C2K_COSIM */
+
+
+#ifdef MTK_PLT_ON_PC
+extern void Evl1RlBsrpRegWrite(HwdRegT reg, kal_uint32 data);
+extern kal_int32 Evl1RlBsrpRegRead(HwdRegT reg);
+
+#else
+extern void Evl1RlBsrpRegWrite(volatile unsigned long* reg, kal_uint32 data);
+extern kal_int32 Evl1RlBsrpRegRead(volatile unsigned long* reg);
+
+#endif
+
+
+#endif /* #ifndef _CPHEVDOFLSRPREGACCESS_H_ */
+
+
+
+
diff --git a/mcu/interface/l1/cl1/common/cphevdorlcomdef.h b/mcu/interface/l1/cl1/common/cphevdorlcomdef.h
new file mode 100644
index 0000000..a7ab5d5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdorlcomdef.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#ifndef _CPH_EVDO_RL_COM_DEF_H_
+#define _CPH_EVDO_RL_COM_DEF_H_
+
+
+typedef enum
+{
+ ACCESS_CHANNEL,
+ TRAFFIC_CHANNEL
+} CphEvdoComCnhlTypT;
+
+typedef enum
+{
+ ACCESS0_PROTOCOL,
+ ACCESS12_PROTOCOL
+} CphEvdoComAccPrtclTypT;
+
+
+typedef enum
+{
+ TRAFFIC01_PROTOCOL,
+ TRAFFIC2_PROTOCOL
+} CphEvdoComTrffcPrtclTypT;
+
+typedef enum
+{
+ ACCESS_SYMBOLE_RATE_0,
+ ACCESS_SYMBOLE_RATE_96,
+ ACCESS_SYMBOLE_RATE_192,
+ ACCESS_SYMBOLE_RATE_384,
+ ACCESS_SYMBOLE_RATE_768,
+ ACCESS_SYMBOLE_RATE_153
+} CphEvdoComAccSymbRateT;
+
+
+typedef enum
+{
+ ACCESS_PAYLOAD_INDEX_0 = 0,
+ ACCESS_PAYLOAD_INDEX_256 = 2,
+ ACCESS_PAYLOAD_INDEX_512 = 3,
+ ACCESS_PAYLOAD_INDEX_1024 = 5,
+ ACCESS_PAYLOAD_INDEX_2048 = 7,
+ ACCESS_PAYLOAD_INDEX_4096 = 9,
+} CphEvdoComAccPldIdxT;
+
+typedef enum
+{
+ TRAFFIC_SUBTUPE01_SYMBOLE_RATE_0,
+ TRAFFIC_SUBTUPE01_SYMBOLE_RATE_96,
+ TRAFFIC_SUBTUPE01_SYMBOLE_RATE_192,
+ TRAFFIC_SUBTUPE01_SYMBOLE_RATE_384,
+ TRAFFIC_SUBTUPE01_SYMBOLE_RATE_768,
+ TRAFFIC_SUBTUPE01_SYMBOLE_RATE_153
+} CphEvdoComTrffcSbtyp01SymbRateT;
+
+
+typedef enum
+{
+ TRAFFIC_SUBTUPE01_PAYLOAD_INDEX_0 = 0,
+ TRAFFIC_SUBTUPE01_PAYLOAD_INDEX_256 = 2,
+ TRAFFIC_SUBTUPE01_PAYLOAD_INDEX_512 = 3,
+ TRAFFIC_SUBTUPE01_PAYLOAD_INDEX_1024 = 5,
+ TRAFFIC_SUBTUPE01_PAYLOAD_INDEX_2048 = 7,
+ TRAFFIC_SUBTUPE01_PAYLOAD_INDEX_4096 = 9,
+}CphEvdoComTrffcSbtyp01PldIdxT;
+
+
+typedef enum
+{
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_0 = 0,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_128 = 1,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_256 = 2,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_512 = 3,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_768 = 4,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_1024 = 5,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_1536 = 6,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_2048 = 7,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_3072 = 8,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_4096 = 9,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_6144 = 10,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_8192 = 11,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_1288 = 12,
+ TRAFFIC_SUBTUPE2_PAYLOAD_INDEX_NUM
+} CphEvdoComTrffcSbtyp2PldIdxT;
+
+typedef enum
+{
+ TRAFFIC_SUBTUPE2_SUBPACKET_INDEX_0 = 0,
+ TRAFFIC_SUBTUPE2_SUBPACKET_INDEX_1 = 1,
+ TRAFFIC_SUBTUPE2_SUBPACKET_INDEX_2 = 2,
+ TRAFFIC_SUBTUPE2_SUBPACKET_INDEX_3 = 3,
+ TRAFFIC_SUBTUPE2_SUBPACKET_NUM
+} CphEvdoComTrffcSbtyp2SbPacketIdxT;
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphevdorlcrp.h b/mcu/interface/l1/cl1/common/cphevdorlcrp.h
new file mode 100644
index 0000000..38540df
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdorlcrp.h
@@ -0,0 +1,238 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#ifndef _CPH_EVDO_RLCRP_H_
+#define _CPH_EVDO_RLCRP_H_
+
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+#include "cphevdorlcomdef.h"
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+typedef struct
+{
+ kal_bool HwDrcDscBoost;
+ kal_bool HwTrig;
+ kal_bool HwHarqCfg;
+ kal_bool SwDrcValueCfg;
+ kal_bool SwDrcChangeCtrl;
+ kal_bool InvIq;
+} CphEvdoRlCrpInitT;
+
+
+typedef struct
+{
+ kal_bool Reset;
+} CphEvdoRlCrpResetT;
+
+
+typedef struct
+{
+ CphEvdoComAccPrtclTypT ProtocolSubtyp;
+ kal_uint16 PrmblPltScale;
+} CphEvdoRlCrpAccPrmblCfgT;
+
+
+typedef struct
+{
+ kal_uint16 PltScale;
+ kal_uint16 PrmblPltScale;
+ kal_uint16 DataScale0;
+ kal_uint16 RriData;
+ kal_uint16 DataScaleKsAck;
+} CphEvdoRlCrpAccCpslCfgT;
+
+typedef struct
+{
+ CphEvdoComTrffcPrtclTypT ProtocolSubtyp;
+ kal_uint16 PltScale;
+ kal_uint16 AuxPltMinPyld;
+ kal_uint16 DrcLen;
+ kal_uint16 DrcGating;
+ kal_uint16 DrcScale;
+ kal_uint16 DrcScaleBoost;
+ kal_uint16 DrcBoostLen;
+ kal_uint16 DscScale;
+ kal_uint16 DscScaleBoost;
+ kal_uint16 DscBoostLen;
+ kal_uint32 AckSupScale;
+ kal_uint32 AckMupScale;
+} CphEvdoRlCrpTrffcParamCfgT;
+
+
+typedef struct
+{
+ kal_uint16 DrcLen;
+ kal_uint16 DrcScale;
+ kal_uint16 AckSupScale;
+ kal_uint16 AckMupScale;
+ kal_uint16 DscScale;
+} CphEvdoRlCrpTrffcSemiStaticCfgT;
+
+
+typedef struct
+{
+ kal_uint16 AuxPltScaleAck;
+ kal_uint16 AuxPltScaleNak;
+ kal_uint16 RriScaleAck;
+ kal_uint16 RriScaleNak;
+ kal_uint16 DataScaleKsAck;
+ kal_uint16 DataScaleKsNak;
+ kal_uint16 DataScale0Ack;
+ kal_uint16 DataScale0Nak;
+ kal_uint16 DataScale1Ack;
+ kal_uint16 DataScale1Nak;
+ kal_uint16 DataScale2Ack;
+ kal_uint16 DataScale2Nak;
+ kal_uint16 DataScale3Ack;
+ kal_uint16 DataScale3Nak;
+ kal_uint16 RriData1;
+ kal_uint16 RriData2Ack;
+ kal_uint16 RriData2Nak;
+ CphEvdoComTrffcSbtyp2PldIdxT PldIdx;
+ CphEvdoComTrffcSbtyp2SbPacketIdxT SbPacketIdx;
+} CphEvdoRlCrpTrffcDataCfgT;
+
+
+typedef struct
+{
+ kal_uint16 SlotOffset;
+ kal_uint32 LongPnMaskH;
+ kal_uint32 LongPnMaskL;
+}CphEvdoRlCrpPnCodeCfgT;
+
+typedef struct
+{
+ kal_uint16 CurSlot;
+ kal_uint16 DrcCover;
+} CphEvdoRlCrpDrcCoverCfgT;
+
+typedef struct
+{
+ kal_uint16 CurSlot;
+ kal_uint16 DscData;
+} CphEvdoRlCrpDscDataCfgT;
+
+
+typedef enum
+{
+ SINGLE_USER,
+ MULITIPLE_USER
+} CphEvdoRlCrpAckUserTypT;
+
+
+typedef struct
+{
+ kal_bool Enable;
+ CphEvdoRlCrpAckUserTypT AckUserType;
+ kal_uint8 Ackbit;
+} CphEvdoRlCrpAckChnlCfgT;
+
+
+
+typedef struct
+{
+ kal_bool Enable;
+} CphEvdoRlCrpEnCfgT;
+
+typedef struct
+{
+ kal_bool Freeze;
+} CphEvdoRlCrpFreezeCfgT;
+
+
+typedef struct
+{
+ kal_bool KsTrig;
+} CphEvdoRlCrpTstKsTrigT;
+
+typedef struct
+{
+ kal_bool TimerTrig;
+} CphEvdoRlCrpTstTimerTrigT;
+
+typedef struct
+{
+ kal_uint16 DrcValue;
+} CphEvdoRlCrpTstDrcValueCfgT;
+
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+
+void CphEvdoRlCrpInit(CphEvdoRlCrpInitT *AdsPtr);
+void CphEvdoRlCrpReset(CphEvdoRlCrpResetT *AdsPtr);
+void CphEvdoRlCrpAccPrmblCfg(CphEvdoRlCrpAccPrmblCfgT *AdsPtr);
+void CphEvdoRlCrpAccCpslCfg(CphEvdoRlCrpAccCpslCfgT *AdsPtr);
+void CphEvdoRlCrpTrffcStaticCfg(CphEvdoRlCrpTrffcParamCfgT *AdsPtr);
+void CphEvdoRlCrpTrffcSemiStaticCfg(CphEvdoRlCrpTrffcSemiStaticCfgT *AdsPtr);
+void CphEvdoRlCrpTrffcDataCfg(CphEvdoRlCrpTrffcDataCfgT *AdsPtr);
+void CphEvdoRlCrpPnCodeCfg(CphEvdoRlCrpPnCodeCfgT *AdsPtr);
+void CphEvdoRlCrpDrcCoverCfg(CphEvdoRlCrpDrcCoverCfgT *AdsPtr);
+void CphEvdoRlCrpDscDataCfg(CphEvdoRlCrpDscDataCfgT *AdsPtr);
+void CphEvdoRlCrpFreezeCfg(CphEvdoRlCrpFreezeCfgT *AdsPtr);
+void CphEvdoRlCrpAckChnlCfg(CphEvdoRlCrpAckChnlCfgT *AdsPtr);
+void CphEvdoRlCrpDisAckChnl(void);
+void CphEvdoRlCrpWriteSupAckScale(kal_uint32 SupAckScale);
+void CphEvdoRlCrpWriteMupAckScale(kal_uint32 MupAckScale);
+void CphEvdoRlCrpTstEnableCfg(CphEvdoRlCrpEnCfgT *AdsPtr);
+void CphEvdoRlCrpTstKsTrig(CphEvdoRlCrpTstKsTrigT *AdsPtr);
+void CphEvdoRlCrpTstTimerTrig(CphEvdoRlCrpTstTimerTrigT *AdsPtr);
+void CphEvdoRlCrpTstDrcValueCfg(CphEvdoRlCrpTstDrcValueCfgT *AdsPtr);
+void CphEvdoInitializeChannelScale();
+void CphEvdoDrcRateValueForTest(kal_uint32 DRCValue);
+void CphEvdoRriDataAckSymbolRate(kal_uint32 RriDataAck );
+kal_int16 CphEvdoRlCrpAckValueGet();
+kal_uint32 CphEvdoDrcValueDebug();
+kal_uint32 CphEvdoRlAckDebug();
+kal_uint32 CphEvdoRlKs0Debug();
+kal_uint32 CphEvdoRlKs1Debug();
+kal_uint32 CphEvdoCrpFsmDebug();
+kal_uint32 CphEvdoRlCrpDscDataRead();
+void CphEvdoRlCrpCrcCheckCfg(kal_uint32 CrcLength);
+void CphEvdoRlCrpModeSel();
+//void CphEvdoRlCrpAllRegisterDump(); /* only for Txcrp debug */
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphevdorltmr.h b/mcu/interface/l1/cl1/common/cphevdorltmr.h
new file mode 100644
index 0000000..2ca48ba
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdorltmr.h
@@ -0,0 +1,93 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHEVDORLTMR_H_
+#define _CPHEVDORLTMR_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+/**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/
+#ifdef __MD93__
+#define DO_TXRXDELAY (278) //Same as RFC_DO_TRXPATH_DELAY
+#elif defined __MD95__
+#define DO_TXRXDELAY (273) //Same as RFC_DO_TRXPATH_DELAY
+#else
+/**Used to Other Setting ,for example MD97*/
+#if defined(MT6297)
+#define DO_TXRXDELAY (419) //Same as RFC_DO_TRXPATH_DELAY
+#elif defined(MT6885)|| defined(MT6873)
+#define DO_TXRXDELAY (402) //Same as RFC_DO_TRXPATH_DELAY
+#else
+#define DO_TXRXDELAY (402) //Same as RFC_DO_TRXPATH_DELAY
+#endif
+
+#endif
+
+typedef enum
+{
+ TX_TMR_DO_WIN_TYPE_CRP,
+ TX_TMR_DO_WIN_TYPE_TXDFE_FIFO,
+ TX_TMR_DO_WIN_TYPE_TXDFE,
+ TX_TMR_DO_WIN_TYPE_TXDAC,
+ TX_TMR_DO_WIN_TYPE_MAX
+}CphEvdoTxTmrWinTypeT;
+
+typedef enum
+{
+ TX_TMR_DO_STRB_TYPE_TXBRP = 0,
+ TX_TMR_DO_STRB_TYPE_TXCRP,
+ TX_TMR_DO_STRB_TYPE_KS,
+ TX_TMR_DO_STRB_TYPE_MAX
+}CphEvdoTxTmrStrbTypeT;
+
+typedef enum
+{
+ TX_TMR_DO_STRB_TRIG_TYPE_DIS = 0,
+ TX_TMR_DO_STRB_TRIG_TYPE_SINGLE = 1,
+ TX_TMR_DO_STRB_TRIG_TYPE_SLOT_OR_FRAME = 2,
+ TX_TMR_DO_STRB_TRIG_TYPE_SUBFRAME = 3,
+ TX_TMR_DO_STRB_TRIG_TYPE_MAX
+}CphEvdoTxTmrStrbTrigTypeT;
+
+
+void CphEvdoTxTmrInit();
+void CphEvdoTxTmrFrameOffset(kal_uint32 FrameOffset);
+void CphEvdoTxTmrWinCfg(CphEvdoTxTmrWinTypeT Type, kal_bool IsOn, kal_uint32 WinTime);
+void CphEvdoTxTmrStrbCfg(CphEvdoTxTmrStrbTypeT StbType, CphEvdoTxTmrStrbTrigTypeT TrigType, kal_uint32 StbTime);
+kal_int32 CphEvdoGetTxTmr();
+kal_int32 CphEvdoTxRxDelay();
+void CphEvdoSetTxRxDelay(kal_uint32 TxRxDelay);
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphevdosch.h b/mcu/interface/l1/cl1/common/cphevdosch.h
new file mode 100644
index 0000000..098388c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdosch.h
@@ -0,0 +1,340 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHEVDOSCH_H_
+#define _CPHEVDOSCH_H_
+
+//#include "cl1common.h"
+#include "kal_general_types.h"
+
+#define SCH_MAX_PILOTS 56
+#define SCH_KEPT_PILOTS 20
+#define SYS_MAX_ACTIVE_LIST_PILOTS 6 /* max number of pilot pn's in acitve list */
+#define SYS_MAX_CANDIDATE_LIST_PILOTS 10 /* max number of pilot pn's in candidate list */
+#define SYS_MAX_NEIGHBOR_LIST_PILOTS 56 /* max number of pilot pn's in neighbor list */
+#define SYS_MAX_REMAINING_LIST_PILOTS 5 /* max number of pilots in remaining set */
+
+
+#define SCH_MAX_PER_PILOT_PATHS 16
+#define SCH_VERIF_NUM_PILOTS_FOUR 4
+#define SCH_VERIF_NUM_PILOTS_ONE 1
+#define SCH_ALWAYS_SRCH 1
+#define SCH_NOT_ALWAYS_SRCH 0
+#define SCH_MAX_USABLE_PATHS 42
+#define SCH_MAX_PER_PILOT_USABLE_PATHS 7
+
+#define SCH_USABLE_PATH_SPY_UPDATE_CNT 10
+
+#define SCH_KEPT_PILOTS 20
+#define SCH_PILOT_ENABLE 1
+#define SCH_PILOT_DISABLE 0
+#define SCH_PILOT_KEEP 1
+#define SCH_PILOT_DONT_KEEP 0
+#define SCH_PPM_SLOT_Q6 15625
+/* #define SCH_STAT_TO_ECIO_Q29 23981*/
+#define SCH_STAT_TO_ECIO_Q29 (31655*2) /*temp fix for pilot fluctuation, match shift 1 change */
+
+#define SCH_MINUS8DBQ16 10387
+#define SCH_MINUS11DBQ16 5206
+#define SCH_MINUS12DBQ16 4135
+#define SCH_MINUS14DBQ16 2609
+#define SCH_MINUS14p5DBQ16 2325
+#define SCH_MINUS15DBQ16 2072
+#define SCH_MINUS18DBQ16 1038
+#define SCH_MINUS21DBQ16 520
+#define SCH_MAX_NUM_FINGERS 6
+#define SCH_MIN_OFFSET_DIST_TC2 2
+#define SCH_HALF_CHIP_TC2 1
+#define SCH_ONE_CHIP_TC2 2
+
+#define SCH_FINGER_ALLOC_CNT 3
+
+/*Sch HW programming for SRDO_INBUF_CTL:BUFFCAPT: Period in half-slots before next buffer capture NOTE: the CAPLEN<= BUFFCAPT period
+define ONLINE search mode values */
+#define SCH_HW_PROG_ONL_INBUF_CTL_CAPT_PERIOD 7 /* Capture at (M+1) half slots intervals, i.e., 6.668ms */
+
+/*Sch HW programming for SRDO_INBUF_CTL:BUFFCAPINT: Num of buffers captured before INTR is triggered
+define ONLINE search mode values */
+#define SCH_HW_PROG_ONL_INBUF_CTL_CAPTURES_PER_INTR 8 /* Interrupt to CP every N*(M+1) half slots, 53.3ms */
+
+
+/*Sch HW programming for SRDO_INBUF_CTL:BUFFCAPT: Period in half-slots before next buffer capture NOTE: the CAPLEN<= BUFFCAPT period
+define DFS search mode values */
+#define SCH_HW_PROG_DFS_INBUF_CTL_CAPT_PERIOD 3 /* Capture at (M+1) half slots intervals, i.e., 3.334ms */
+
+/*Sch HW programming for SRDO_INBUF_CTL:BUFFCAPINT: Num of buffers captured before INTR is triggered
+define DFS search mode values */
+#define SCH_HW_PROG_DFS_INBUF_CTL_CAPTURES_PER_INTR 2 /* Interrupt to CP every N*(M+1) half slots, 6.668ms */
+
+/* Sch HW programming for SRDO_INBUF_CTL:ANTENNA_INIT_EN :-
+ Enable changing the source antenna (main OR diversity, based on the value in
+ SRDO_INBUF_CTL:ANTENNA_INIT ), in Antenna-toggle search mode
+ (SRDO_INBUF_CTL:ANT_MODE = 0x2/ 0x3)
+ NOTE: IMD requires last buffer to be captured as MAIN hence based on the
+ number of buffers captured, change the starting source accordingly
+*/
+#define SCH_HW_INBUF_CTL_ANTENNA_INIT_EN_USED 1
+#define SCH_HW_INBUF_CTL_ANTENNA_INIT_EN_NOTUSED 0
+#define SCH_HW_INBUF_CTL_ANTENNA_INIT_NOTUSED SCH_HW_PROG_INBUF_ANT_MODE_MAIN //Don't care value for SRDO_INBUF_CTL:ANTENNA_INIT field
+
+#define RMC_SCH_LOGIQ_MAX_BUFFER_LENGTH 0x8C0 /*1024+96chip 2x*/
+
+/* Sch HW programming for SRDO_INBUF_CTL:ANT_MODE :-
+Define type to indicate input source antenna */
+typedef enum
+{
+ SCH_HW_PROG_INBUF_ANT_MODE_MAIN = 0,
+ SCH_HW_PROG_INBUF_ANT_MODE_DIV = 1,
+ SCH_HW_PROG_INBUF_ANT_MODE_ALTERNATE_PER_CAPT = 2, /* Alternate antenna after each capture NOTE: Multiple captures before search HW interrupt is triggered. Also each cpature can be multiple half-slots long */
+ SCH_HW_PROG_INBUF_ANT_MODE_ALTERNATE_PER_HFSLOT = 3, /* Alternate antenna after each half slot*/
+}SchHwProgInBufAntModeT;
+
+typedef enum
+{
+ HW_RESET,
+ HW_PAUSE,
+ INIT_ACQ_PN_SRCH,
+ INIT_ACQ_ONLINE_PN_SRCH,
+ INIT_ACQ_VERIF_SRCH,
+ MINI_ACQ,
+ FAST_SEARCH,
+ ONLINE,
+ OFFSET_ADJ,
+ FAST_FULL_SEARCH,
+ SCH_MODE_UNUSED_1,
+ SCH_MODE_UNUSED_2,
+ DFS,
+ MEAS_6MS_SRCH,
+ MEAS_ONLINE_SCAN
+} SchModeT;
+
+typedef struct
+{
+ kal_uint16 PilotPN; /* PilotPN 0 to 511 */
+ kal_int16 StartOffset; /* Start offset to search, Tc/2 (-1024,...,+1023.5 chips) */
+} SchCfgPnListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Active list */
+ kal_uint16 WinSize; /* Window Size */
+ SchCfgPnListT PnListQ[SYS_MAX_ACTIVE_LIST_PILOTS];
+} SchCfgActListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Candidate list */
+ kal_uint16 WinSize; /* Window Size */
+ SchCfgPnListT PnListQ[SYS_MAX_CANDIDATE_LIST_PILOTS];
+} SchCfgCandListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Neighbor list */
+ kal_uint16 WinSize[SYS_MAX_NEIGHBOR_LIST_PILOTS]; /* Window information */
+ SchCfgPnListT PnListQ[SYS_MAX_NEIGHBOR_LIST_PILOTS];
+} SchCfgNeighListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Remaining list */
+ kal_uint16 WinSize; /* Window Size */
+ SchCfgPnListT PnListQ[SYS_MAX_REMAINING_LIST_PILOTS];
+} SchCfgRemListT;
+
+
+typedef struct
+{
+ kal_int16 ListNum; /* total search list number (A+C+N+R) */
+ SchCfgActListT Active;
+ SchCfgCandListT Candidate;
+ SchCfgNeighListT Neighbor;
+ SchCfgRemListT Remaining;
+} SchListT;
+
+typedef struct
+{
+ kal_uint16 WinSize; /* Window Size */
+ kal_int16 WinOffset; /* Window Offset */
+} WinT;
+
+typedef struct
+{
+ kal_uint16 PilotPN; /* PilotPN 0 to 511 */
+ kal_int16 Offset; /* Tc/2 resolution */
+} AcqListQT;
+
+typedef struct
+{
+ kal_int16 ListNum;
+ AcqListQT PnListQ[SCH_VERIF_NUM_PILOTS_FOUR];
+} SchAcqListT;
+
+typedef struct
+{
+ SchModeT SchMode;
+ kal_uint16 SchInitAcqNumHalfSlotBufCap;
+ kal_uint8 Antenna;
+ kal_bool antenna_init_en;
+ kal_uint32 antenna_init; //Not Valid as antenna_init_en is FALSE
+ kal_bool Div_only;
+ kal_uint16 SchInitAcqWinSizeTc;
+ kal_uint16 SchInitAcqWinOffsetTc;
+ kal_uint16 SchMiniAcqWinSizeIndex;
+ //intkal_bool bHwdPwrSavingDoPwrUp;//no this mode for 93
+ kal_bool SchStartDlyEn;
+ kal_uint32 SchStartDlyCnt;
+ SchListT SchList;
+ SchAcqListT SchAcqSrch;
+} CphEvdoSchModeConfigStruct;
+
+typedef struct
+{
+ kal_uint16 Metric;
+ kal_uint16 PilotPN;
+ kal_int16 Offset; /* Offset in Tc/2 (-1024,...,+1023.5 chips) */
+} SchSortQT;
+
+typedef struct
+{
+ kal_uint16 Count;
+ SchSortQT SortQ[SCH_MAX_PILOTS];
+} SchSortT;
+
+typedef struct
+{
+ kal_uint16 Stat; /* Stat for path */
+ kal_int16 StatOffset; /* Stat Offset in Tc/2 (-1024,...,+1023.5 chips) */
+ kal_uint8 PathValid; /* Indicates if path is valid (passes thresh) */
+ kal_uint8 NumAvg; /* Number of times offset was found */
+ kal_uint8 Ant; /* Source antenna */
+} SchPathQT;
+
+typedef struct
+{
+ kal_uint16 PilotPN; /* PilotPN 0 to 511 */
+ kal_int16 Offset; /* strongest offset found, Tc/2 (-1024,...,+1023.5 chips) */
+ kal_int16 StartOffset; /* Start offset to search, Tc/2 (-1024,...,+1023.5 chips) */
+ kal_uint16 MaxStat; /* Maximum statistic in the path buffer */
+ kal_uint16 PwrEst; /* Sum of usable path power */
+#ifdef MTK_PLT_ON_PC
+ kal_int16 Strength_db; /* pilot strength in db */
+#endif
+ kal_uint8 NumWinSearch; /* Number of times the pilot was searched */
+ kal_uint8 PilotFound; /* Indicates if the H/W found the pilot */
+ SchPathQT PathQ[SCH_MAX_PER_PILOT_PATHS];
+} ListQT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Active list */
+ kal_uint16 WinSize; /* Window Size */
+ kal_uint8 MACIndex[SYS_MAX_ACTIVE_LIST_PILOTS]; /* MAC Index */
+ kal_int8 PcgId[SYS_MAX_ACTIVE_LIST_PILOTS];
+ kal_uint8 RABLength[SYS_MAX_ACTIVE_LIST_PILOTS];
+ kal_uint8 RABOffset[SYS_MAX_ACTIVE_LIST_PILOTS];
+ kal_uint8 RAChannelGain[SYS_MAX_ACTIVE_LIST_PILOTS];
+ kal_uint8 DRCCover[SYS_MAX_ACTIVE_LIST_PILOTS];
+ kal_uint8 DSC[SYS_MAX_ACTIVE_LIST_PILOTS]; /* oxff means NULL */
+ ListQT ListQ[SYS_MAX_ACTIVE_LIST_PILOTS];
+} ActListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Candidate list */
+ kal_uint16 WinSize; /* Window Size */
+ ListQT ListQ[SYS_MAX_CANDIDATE_LIST_PILOTS];
+} CandListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Neighbor list */
+ WinT Win[SYS_MAX_NEIGHBOR_LIST_PILOTS]; /* Window information */
+ ListQT ListQ[SYS_MAX_NEIGHBOR_LIST_PILOTS];
+} NeighListT;
+
+typedef struct
+{
+ kal_int8 NumPilots; /* Number of Pilots in the Remaining list */
+ kal_uint16 WinSize; /* Window Size */
+ ListQT ListQ[SYS_MAX_REMAINING_LIST_PILOTS];
+} RemListT;
+
+typedef struct
+{
+ kal_int16 PilotSeq;
+ kal_uint8 ConnSetupFlag;
+ kal_uint8 TcaFlag;
+ kal_int16 ListNum; /* total search list number (A+C+N+R) */
+ ActListT Active;
+ CandListT Candidate;
+ NeighListT Neighbor;
+ RemListT Remaining;
+} RmcSchStatusT;
+
+typedef struct
+{
+ SchModeT SchMode;
+ SchSortQT *pSortQ; /**For store INIT_PN_SRCH result: SCH_KEPT_PILOTS.*/
+ RmcSchStatusT *pSchStatus; /**For store other search result.*/
+} CphEvdoSchResultReadStruct;
+
+typedef struct
+{
+ kal_int8 ImdAdcI; /* IMD ADC I samples */
+ kal_int8 ImdAdcQ; /* IMD ADC Q samples */
+} RmcSchLogIQComplexSampleT;
+
+
+typedef struct
+{
+ kal_int8 tbd;
+}CphEvdoSchTestIqDumpAdsStruct;
+
+void CphEvdoSchInit();
+void CphEvdoPauseConfig(kal_uint8 PauseBit);
+void CphEvdoSchModeConfig(CphEvdoSchModeConfigStruct *ads_ptr);
+void CphEvdoSchResultRead(CphEvdoSchResultReadStruct *ads_ptr);
+void CphEvdoSchLogIqRead(RmcSchLogIQComplexSampleT *ads_ptr);
+#if 0 /**Just used for debug.*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+kal_bool CphEvdoSchReadSchDone(void);
+#ifdef MTK_PLT_ON_PC_IT
+void CphEvdoSchWriteSchDone(kal_bool SchDone);
+#endif
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/cphevdoschregaccess.h b/mcu/interface/l1/cl1/common/cphevdoschregaccess.h
new file mode 100644
index 0000000..dd92ebf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphevdoschregaccess.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPHEVDOSCHREGACCESS_H_
+#define _CPHEVDOSCHREGACCESS_H_
+
+
+#ifndef MTK_C2K_COSIM
+#undef HwdWrite32
+#undef HwdRead32
+#ifdef MTK_PLT_ON_PC
+#define HwdWrite32(Reg, data) Evl1SchRegWrite((HwdRegT)(Reg), data)
+#define HwdRead32(Reg) Evl1SchRegRead((HwdRegT)(Reg))
+#else
+#define HwdWrite32(Reg, data) Evl1SchRegWrite((volatile unsigned long*)(Reg), data)
+#define HwdRead32(Reg) Evl1SchRegRead((volatile unsigned long*)(Reg))
+
+#endif
+
+#endif /* #ifndef MTK_C2K_COSIM */
+
+
+#ifdef MTK_PLT_ON_PC
+extern void Evl1SchRegWrite(HwdRegT reg, kal_uint32 data);
+extern kal_int32 Evl1SchRegRead(HwdRegT reg);
+
+#else
+extern void Evl1SchRegWrite(volatile unsigned long* reg, kal_uint32 data);
+extern kal_int32 Evl1SchRegRead(volatile unsigned long* reg);
+
+#endif
+
+
+#endif /* #ifndef _CPHEVDOFLSRPREGACCESS_H_ */
+
+
+
+
diff --git a/mcu/interface/l1/cl1/common/cphheaddocinc.h b/mcu/interface/l1/cl1/common/cphheaddocinc.h
new file mode 100644
index 0000000..c224ccf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphheaddocinc.h
@@ -0,0 +1,80 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_HEAD_DOC_INC_H_
+#define _CPH_HEAD_DOC_INC_H_
+
+/*HW Register Head Doc*/
+#include "cph1xrxbrp.h"
+#include "cph1xrxbrpcorrser.h"
+#include "cph1xrxbrpdma.h"
+#include "cph1xrxbrpwctdma.h"
+#include "cph1xrxeventgen.h" //OK for 95
+#include "cph1xrxslp.h"
+#include "cph1xschreg.h" //OK for 95
+#include "cph1xtxbrp.h"
+#include "cph1xtxcrp.h"
+#include "cph1xtxtmr.h"
+#include "cphb2rif.h"
+#include "cphd2bif.h"
+#include "cphcstopreg.h"
+#include "cphevdoschreg.h"
+#include "cphc2kl1aocfg.h"
+#include "cphc2krxbrpdvit.h"
+#include "cphc2krxbrptur.h"
+#include "cphc2krxdfe.h"
+#include "cphc2krxdfefcimm.h"
+#include "cphevdorxbrp.h"
+#include "cphmrsg.h"
+#include "cphevdorxeventgen.h"
+#include "cphevdorxslp.h"
+#include "cphevdotxbrp.h"
+#include "cphevdotxcrp.h"
+#include "cphevdotxtimerreg.h"
+#include "cphrtttxtimerreg.h"
+#include "cphrxdfeatimer.h"
+#include "cphrxdfefccaltc.h"
+#include "cphrxdfesysconfig.h"
+#include "cphrxmmeventgen.h"
+#include "cphsystemtimer.h"
+#include "cphtxcrpcommon.h"
+#include "cphtxdfebb.h"
+#if defined(__MD93__)||defined(__MD95__)
+#include "cphtxsysglbconfigreg0.h"
+#include "cphtxsysglbconfigreg1.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphdfesysglbconfigreg0.h"
+#include "cphdfesysglbconfigreg1.h"
+#endif
+#endif //#ifndef _CPH_HEAD_DOC_INC_H_
diff --git a/mcu/interface/l1/cl1/common/cphmdsysmdm.h b/mcu/interface/l1/cl1/common/cphmdsysmdm.h
new file mode 100644
index 0000000..f6360b1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphmdsysmdm.h
@@ -0,0 +1,160 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDSYS_MDM_H_
+#define _CPH_MDSYS_MDM_H_
+
+#include "kal_general_types.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDSYS_MDM_REG_BASE (0xA0490000)
+
+#define MDSYS_MDM_end (MDSYS_MDM_REG_BASE + 0xC0 + 8*4)
+
+
+
+#define MDM_TM_ENDSIM ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x14))
+#define MDM_TM_ERRCNT ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x18))
+#define MDM_TM_DBGINFO ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x1C))
+#define MDM_TM_ENDFAIL ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x28))
+#define MDM_TM_ENDSUCC ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x2C))
+#define MDM_TM_ALLFMT32B ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x34))
+#define MDM_TM_HEXFMT32B ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x38))
+#define MDM_TM_DECFMT32B ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x3C))
+#define MDM_TM_BINFMT32B ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x40))
+#define MDM_TM_MEMDUMPSTR ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x50))
+#define MDM_TM_MEMDUMPSTOP ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x54))
+#define MDM_TM_MEMGOLDENSTR ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x58))
+#define MDM_TM_MEMGOLDENSTOP ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x5C))
+#define MDM_TM_MEMREVISESTR ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x60))
+#define MDM_TM_MEMREVISESTOP ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x64))
+#define MDM_TM_RUNTIME_USEC ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x6C))
+#define MDM_TM_STR_CLEAR ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x90))
+#define MDM_TM_STR_DISPLAY ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x94))
+#define MDM_TM_STR(n) ((APBADDR32)(MDSYS_MDM_REG_BASE + 0x98 + (n)*4)) //n is from 0 to 7
+#define MDM_TM_DAT(n) ((APBADDR32)(MDSYS_MDM_REG_BASE + 0xC0 + (n)*4)) //n is from 0 to 7
+
+
+#define MDM_TM_ENDSIM_MDM_TM_ENDSIM_LSB (0)
+#define MDM_TM_ENDSIM_MDM_TM_ENDSIM_WIDTH (32)
+#define MDM_TM_ENDSIM_MDM_TM_ENDSIM_MASK (0xFFFFFFFF)
+
+#define MDM_TM_ERRCNT_MDM_TM_ERRCNT_LSB (0)
+#define MDM_TM_ERRCNT_MDM_TM_ERRCNT_WIDTH (32)
+#define MDM_TM_ERRCNT_MDM_TM_ERRCNT_MASK (0xFFFFFFFF)
+
+#define MDM_TM_DBGINFO_MDM_TM_DBGINFO_LSB (0)
+#define MDM_TM_DBGINFO_MDM_TM_DBGINFO_WIDTH (32)
+#define MDM_TM_DBGINFO_MDM_TM_DBGINFO_MASK (0xFFFFFFFF)
+
+#define MDM_TM_ENDFAIL_MDM_TM_ENDFAIL_LSB (0)
+#define MDM_TM_ENDFAIL_MDM_TM_ENDFAIL_WIDTH (32)
+#define MDM_TM_ENDFAIL_MDM_TM_ENDFAIL_MASK (0xFFFFFFFF)
+
+#define MDM_TM_ENDSUCC_MDM_TM_ENDSUCC_LSB (0)
+#define MDM_TM_ENDSUCC_MDM_TM_ENDSUCC_WIDTH (32)
+#define MDM_TM_ENDSUCC_MDM_TM_ENDSUCC_MASK (0xFFFFFFFF)
+
+#define MDM_TM_ALLFMT32B_MDM_TM_ALLFMT32B_LSB (0)
+#define MDM_TM_ALLFMT32B_MDM_TM_ALLFMT32B_WIDTH (32)
+#define MDM_TM_ALLFMT32B_MDM_TM_ALLFMT32B_MASK (0xFFFFFFFF)
+
+#define MDM_TM_HEXFMT32B_MDM_TM_HEXFMT32B_LSB (0)
+#define MDM_TM_HEXFMT32B_MDM_TM_HEXFMT32B_WIDTH (32)
+#define MDM_TM_HEXFMT32B_MDM_TM_HEXFMT32B_MASK (0xFFFFFFFF)
+
+#define MDM_TM_DECFMT32B_MDM_TM_DECFMT32B_LSB (0)
+#define MDM_TM_DECFMT32B_MDM_TM_DECFMT32B_WIDTH (32)
+#define MDM_TM_DECFMT32B_MDM_TM_DECFMT32B_MASK (0xFFFFFFFF)
+
+#define MDM_TM_BINFMT32B_MDM_TM_BINFMT32B_LSB (0)
+#define MDM_TM_BINFMT32B_MDM_TM_BINFMT32B_WIDTH (32)
+#define MDM_TM_BINFMT32B_MDM_TM_BINFMT32B_MASK (0xFFFFFFFF)
+
+#define MDM_TM_MEMDUMPSTR_MDM_TM_MEMDUMPSTR_LSB (0)
+#define MDM_TM_MEMDUMPSTR_MDM_TM_MEMDUMPSTR_WIDTH (32)
+#define MDM_TM_MEMDUMPSTR_MDM_TM_MEMDUMPSTR_MASK (0xFFFFFFFF)
+
+#define MDM_TM_MEMDUMPSTOP_MDM_TM_MEMDUMPSTOP_LSB (0)
+#define MDM_TM_MEMDUMPSTOP_MDM_TM_MEMDUMPSTOP_WIDTH (32)
+#define MDM_TM_MEMDUMPSTOP_MDM_TM_MEMDUMPSTOP_MASK (0xFFFFFFFF)
+
+#define MDM_TM_MEMGOLDENSTR_MDM_TM_MEMGOLDENSTR_LSB (0)
+#define MDM_TM_MEMGOLDENSTR_MDM_TM_MEMGOLDENSTR_WIDTH (32)
+#define MDM_TM_MEMGOLDENSTR_MDM_TM_MEMGOLDENSTR_MASK (0xFFFFFFFF)
+
+#define MDM_TM_MEMGOLDENSTOP_MDM_TM_MEMGOLDENSTOP_LSB (0)
+#define MDM_TM_MEMGOLDENSTOP_MDM_TM_MEMGOLDENSTOP_WIDTH (32)
+#define MDM_TM_MEMGOLDENSTOP_MDM_TM_MEMGOLDENSTOP_MASK (0xFFFFFFFF)
+
+#define MDM_TM_MEMREVISESTR_MDM_TM_MEMREVISESTR_LSB (0)
+#define MDM_TM_MEMREVISESTR_MDM_TM_MEMREVISESTR_WIDTH (32)
+#define MDM_TM_MEMREVISESTR_MDM_TM_MEMREVISESTR_MASK (0xFFFFFFFF)
+
+#define MDM_TM_MEMREVISESTOP_MDM_TM_MEMREVISESTOP_LSB (0)
+#define MDM_TM_MEMREVISESTOP_MDM_TM_MEMREVISESTOP_WIDTH (32)
+#define MDM_TM_MEMREVISESTOP_MDM_TM_MEMREVISESTOP_MASK (0xFFFFFFFF)
+
+#define MDM_TM_RUNTIME_USEC_MDM_TM_RUNTIME_USEC_LSB (0)
+#define MDM_TM_RUNTIME_USEC_MDM_TM_RUNTIME_USEC_WIDTH (32)
+#define MDM_TM_RUNTIME_USEC_MDM_TM_RUNTIME_USEC_MASK (0xFFFFFFFF)
+
+#define MDM_TM_STR_CLEAR_MDM_TM_STR_CLEAR_LSB (0)
+#define MDM_TM_STR_CLEAR_MDM_TM_STR_CLEAR_WIDTH (4)
+#define MDM_TM_STR_CLEAR_MDM_TM_STR_CLEAR_MASK (0x0000000F)
+
+#define MDM_TM_STR_DISPLAY_MDM_TM_STR_DISPLAY_LSB (0)
+#define MDM_TM_STR_DISPLAY_MDM_TM_STR_DISPLAY_WIDTH (4)
+#define MDM_TM_STR_DISPLAY_MDM_TM_STR_DISPLAY_MASK (0x0000000F)
+
+#define MDM_TM_STR_MDM_TM_STR_LSB (0)
+#define MDM_TM_STR_MDM_TM_STR_WIDTH (8)
+#define MDM_TM_STR_MDM_TM_STR_MASK (0x000000FF)
+
+#define MDM_TM_DAT_MDM_TM_DAT_LSB (0)
+#define MDM_TM_DAT_MDM_TM_DAT_WIDTH (32)
+#define MDM_TM_DAT_MDM_TM_DAT_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_MDSYS_MDM_H_
diff --git a/mcu/interface/l1/cl1/common/cphrldfebb.h b/mcu/interface/l1/cl1/common/cphrldfebb.h
new file mode 100644
index 0000000..aad1ebe
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphrldfebb.h
@@ -0,0 +1,51 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHRLDFEBB_H_
+#define _CPHRLDFEBB_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+
+void CphRlDfeInit();
+void CphRlDfeNcoCfg(kal_int32 Nco);
+void Cph1xRlDfeIs95Cfg(kal_bool Is95);
+void Cph1xRlDfeCrcCheckCfg(void);
+kal_uint32 Cph1xRlDfeBbCrcRead(void);
+kal_uint32 Cph1xRlDfeRfCrcRead(void);
+void CphRlDfeRegLog();
+void CphRlDfeBbSineCfg(kal_uint32 CfgData);
+void CphTstEvdoTxDfeWinCfg(SysAirInterfaceT Interface,kal_bool IsOn);
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphrlsysglb.h b/mcu/interface/l1/cl1/common/cphrlsysglb.h
new file mode 100644
index 0000000..27988a5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphrlsysglb.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHRLSYSGLB_H_
+#define _CPHRLSYSGLB_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+void Cph1xRlBrpRst();
+void Cph1xRlCrpRst();
+void CphEvdoRlBrpRst();
+void CphEvdoRlCrpRst();
+void CphRlSysTxBrpDivCfg(SysAirInterfaceT Interface, kal_bool MmTx);
+void CphRlSysTxCrpDivCfg(SysAirInterfaceT Interface, kal_bool MmTx);
+void CphRlSysTxDfeBbCkEn();
+void CphRlSysTxDfeBbCkDis();
+void CphRlSysTxCrpCkEn();
+void CphRlSysTxCrpCkDis();
+void CphRlSysTxBrpCkEn();
+void CphRlSysTxBrpCkDis();
+void CphRlSysTxDfeRfCkEn();
+void Cph1xRlSysGlbRegLog();
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphrxdfe.h b/mcu/interface/l1/cl1/common/cphrxdfe.h
new file mode 100644
index 0000000..e0300b0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphrxdfe.h
@@ -0,0 +1,69 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHRXDFE_H_
+#define _CPHRXDFE_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+
+typedef enum
+{
+ MRSG_MODE_EVDO_SCH,
+ MRSG_MODE_EVDO_INNER,
+ MRSG_MODE_1X_SCH,
+ MRSG_MODE_1X_INNER
+
+} CphC2kMrsgModeEnum;
+
+extern void CphRxdfeClockOn(void);
+
+extern void CphRxdfeTstPatternCpy(const void *addr,
+ kal_uint32 len /* the data length of test pattern, 128 bytes multiples and not larger than 16 MBytes */);
+
+extern void CphRxdfeOn(CphC2kMrsgModeEnum mrsgMode,
+ kal_uint32 len, /* the data length of test pattern, 128 bytes multiples and not larger than 16 MBytes */
+ kal_uint32 offset /* the 80ms system timer at which test pattern start */);
+
+extern void CphRxdfeOnDataAddr(CphC2kMrsgModeEnum mrsgMode,
+ kal_uint32 len, /* the data length of test pattern, 128 bytes multiples and not larger than 16 MBytes */
+ kal_uint32 offset, /* the 80ms system timer at which test pattern start */
+ kal_uint32 DataAddr /*Data adress*/);
+extern void CphRxdfeMrsgWinOn(CphC2kMrsgModeEnum mrsgMode,
+ kal_uint32 offset /* the 80ms system timer at which test pattern start */);
+
+extern void CphRxdfeMrsgWinOff(CphC2kMrsgModeEnum mrsgMode,
+ kal_uint32 offset /* the 80ms system timer at which test pattern end */);
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphsystemtimer.h b/mcu/interface/l1/cl1/common/cphsystemtimer.h
new file mode 100644
index 0000000..2e0762f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphsystemtimer.h
@@ -0,0 +1,1278 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHSYSTEMTIMER_H_
+#define _CPHSYSTEMTIMER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if (defined(__MD93__)||defined(__MD95__))
+#define ST_RX_TIMER_REG_BASE (0xA60C0000)/*RX TIMER REG BASE 93&95*/
+#elif defined(__MD97__) || defined(__MD97P__)
+#define ST_RX_TIMER_REG_BASE (0xA80C0000)/*RX TIMER REG BASE 97*/
+#endif
+
+#define ST_ADV_RET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000000))
+#define ST_SYNC_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000004))
+#define ST_SYNC_SYSCNT_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000008))
+#define ST_SYNC_SUPFRM_CNT_L_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000000C))
+#define ST_SYNC_SUPFRM_CNT_H_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000010))
+#define ST_SYNC_TIME_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000014))
+#define ST_SUPFRM_CNT_L_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000018))
+#define ST_SUPFRM_CNT_H_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000001C))
+#define ST_SUPFRM_CNT_INI_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000020))
+#define ST_FRM_TYPE(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000024))
+#define ST_CPINT_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000028))
+#define ST_CPINT_MASK(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000002C))
+#define ST_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000030))
+#define ST_CPINT_SRC(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000034))
+#define ST_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000038))
+#define ST_HALF_CPINT_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000003C))
+#define ST_HALF_CPINT_MASK(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000040))
+#define ST_HALF_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000044))
+#define ST_HALF_CPINT_SRC(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000048))
+#define ST_HALF_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000004C))
+#define ST_CFG_CPINT_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000050))
+#define ST_CFG_CPINT_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000054))
+#define ST_CFG_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000058))
+#define ST_CFG_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000005C))
+#ifdef __MD93__
+#define ST_SUBFR_STATUS(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000060))
+#endif
+#define ST_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000064))
+#define ST_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000068))
+#define ST_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000006C))
+#define ST_FRC_TIMING_SYNC_MODE(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000070))
+#define ST_FRC_TIMING_SYNC_CMP(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000074))
+#define ST_FRC_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000078))
+#define ST_FRC_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000007C))
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000080))
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000084))
+#define ST_MU_SFO(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000088))
+#define ST_MU_ACC_INI_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000008C))
+#define ST_MU_ACC_INI_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000090))
+#define ST_MU_ACC_SET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000094))
+#define ST_RAKE_CTL_TIME3(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000098))
+#define ST_GSR_CTL_TIME2(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000009C))
+#define ST_GSR_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A0))
+#define ST_GSR_SYNC_TAG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A4))
+#ifdef __MD93__
+#define ST_1XDO_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A8))
+#define ST_1XDO_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000AC))
+#else
+#define ST_1XDO_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C0))
+#define ST_1XDO_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C4))
+#define ST_1XDO_TIMING_SYNC_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C8))
+#define ST_1XDO_TIMING_SYNC_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000CC))
+#endif
+#define ST_1XDOMRG_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B0))
+#define ST_1XDOMRG_INI_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B4))
+#define ST_1XDOMRG_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B8))
+#define ST_GPS_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000BC))
+#if defined(__MD97__) || defined(__MD97P__)
+#define ST_1XDO_US_SYNC_IMM_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000200))
+#define ST_1XDO_US_SYNC_IMM_UCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000204))
+#define ST_1XDO_US_SYNC_IMM_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000208))
+#define ST_1XDO_US_SYNC_SCH_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000210))
+#define ST_1XDO_US_SYNC_SCH_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000020c))
+#define ST_1XDO_US_SYNC_SCH_UCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000214))
+#endif
+
+
+#define ST_ADV_RET_MODE_LSB (0)
+#define ST_ADV_RET_MODE_WIDTH (2)
+#define ST_ADV_RET_MODE_MASK (0x00000003)
+#define ST_ADV_RET_MODE_ADV (0x00000001)
+#define ST_ADV_RET_MODE_RET (0x00000002)
+
+#define ST_ADV_RET_ADJ_TC8_LSB (2)
+#define ST_ADV_RET_ADJ_TC8_WIDTH (9)
+#define ST_ADV_RET_ADJ_TC8_MASK (0x000007FC)
+
+
+#define ST_SYNC_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST_SYNC_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_SYNC_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_SYSCNT_INI_SYSTEM_TIME_CNT_LSB (0)
+#define ST_SYSCNT_INI_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_SYSCNT_INI_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+
+#define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_LSB (0)
+#define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_WIDTH (32)
+#define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_LSB (0)
+#define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_WIDTH (4)
+#define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_SYNC_TIME_EN_EN_LSB (0)
+#define ST_SYNC_TIME_EN_EN_WIDTH (1)
+#define ST_SYNC_TIME_EN_EN_MASK (0x00000001)
+#define ST_SYNC_TIME_EN_EN_BIT (0x00000001)
+
+#define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_WIDTH (32)
+#define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_WIDTH (4)
+#define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_LSB (0)
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_WIDTH (1)
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_MASK (0x00000001)
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_BIT (0x00000001)
+
+#define ST_FRM_TYPE_FRM_TYPE_LSB (0)
+#define ST_FRM_TYPE_FRM_TYPE_WIDTH (1)
+#define ST_FRM_TYPE_FRM_TYPE_MASK (0x00000001)
+#define ST_FRM_TYPE_FRM_TYPE_26MS (0x00000000)
+#define ST_FRM_TYPE_FRM_TYPE_20MS (0x00000001)
+
+#define ST_CPINT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST_CPINT_OFFSET_CHIP_OFFSET_WIDTH (18)
+#define ST_CPINT_OFFSET_CHIP_OFFSET_MASK (0x000FFFFC)
+
+#define ST_CPINT_MASK_MSK15_LSB (15)
+#define ST_CPINT_MASK_MSK15_WIDTH (1)
+#define ST_CPINT_MASK_MSK15_MASK (0x00008000)
+#define ST_CPINT_MASK_MSK15_BIT (0x00008000)
+
+#define ST_CPINT_MASK_MSK14_LSB (14)
+#define ST_CPINT_MASK_MSK14_WIDTH (1)
+#define ST_CPINT_MASK_MSK14_MASK (0x00004000)
+#define ST_CPINT_MASK_MSK14_BIT (0x00004000)
+
+#define ST_CPINT_MASK_MSK13_LSB (13)
+#define ST_CPINT_MASK_MSK13_WIDTH (1)
+#define ST_CPINT_MASK_MSK13_MASK (0x00002000)
+#define ST_CPINT_MASK_MSK13_BIT (0x00002000)
+
+#define ST_CPINT_MASK_MSK12_LSB (12)
+#define ST_CPINT_MASK_MSK12_WIDTH (1)
+#define ST_CPINT_MASK_MSK12_MASK (0x00001000)
+#define ST_CPINT_MASK_MSK12_BIT (0x00001000)
+
+#define ST_CPINT_MASK_MSK11_LSB (11)
+#define ST_CPINT_MASK_MSK11_WIDTH (1)
+#define ST_CPINT_MASK_MSK11_MASK (0x00000800)
+#define ST_CPINT_MASK_MSK11_BIT (0x00000800)
+
+#define ST_CPINT_MASK_MSK10_LSB (10)
+#define ST_CPINT_MASK_MSK10_WIDTH (1)
+#define ST_CPINT_MASK_MSK10_MASK (0x00000400)
+#define ST_CPINT_MASK_MSK10_BIT (0x00000400)
+
+#define ST_CPINT_MASK_MSK9_LSB (9)
+#define ST_CPINT_MASK_MSK9_WIDTH (1)
+#define ST_CPINT_MASK_MSK9_MASK (0x00000200)
+#define ST_CPINT_MASK_MSK9_BIT (0x00000200)
+
+#define ST_CPINT_MASK_MSK8_LSB (8)
+#define ST_CPINT_MASK_MSK8_WIDTH (1)
+#define ST_CPINT_MASK_MSK8_MASK (0x00000100)
+#define ST_CPINT_MASK_MSK8_BIT (0x00000100)
+
+#define ST_CPINT_MASK_MSK7_LSB (7)
+#define ST_CPINT_MASK_MSK7_WIDTH (1)
+#define ST_CPINT_MASK_MSK7_MASK (0x00000080)
+#define ST_CPINT_MASK_MSK7_BIT (0x00000080)
+
+#define ST_CPINT_MASK_MSK6_LSB (6)
+#define ST_CPINT_MASK_MSK6_WIDTH (1)
+#define ST_CPINT_MASK_MSK6_MASK (0x00000040)
+#define ST_CPINT_MASK_MSK6_BIT (0x00000040)
+
+#define ST_CPINT_MASK_MSK5_LSB (5)
+#define ST_CPINT_MASK_MSK5_WIDTH (1)
+#define ST_CPINT_MASK_MSK5_MASK (0x00000020)
+#define ST_CPINT_MASK_MSK5_BIT (0x00000020)
+
+#define ST_CPINT_MASK_MSK4_LSB (4)
+#define ST_CPINT_MASK_MSK4_WIDTH (1)
+#define ST_CPINT_MASK_MSK4_MASK (0x00000010)
+#define ST_CPINT_MASK_MSK4_BIT (0x00000010)
+
+#define ST_CPINT_MASK_MSK3_LSB (3)
+#define ST_CPINT_MASK_MSK3_WIDTH (1)
+#define ST_CPINT_MASK_MSK3_MASK (0x00000008)
+#define ST_CPINT_MASK_MSK3_BIT (0x00000008)
+
+#define ST_CPINT_MASK_MSK2_LSB (2)
+#define ST_CPINT_MASK_MSK2_WIDTH (1)
+#define ST_CPINT_MASK_MSK2_MASK (0x00000004)
+#define ST_CPINT_MASK_MSK2_BIT (0x00000004)
+
+#define ST_CPINT_MASK_MSK1_LSB (1)
+#define ST_CPINT_MASK_MSK1_WIDTH (1)
+#define ST_CPINT_MASK_MSK1_MASK (0x00000002)
+#define ST_CPINT_MASK_MSK1_BIT (0x00000002)
+
+#define ST_CPINT_MASK_MSK0_LSB (0)
+#define ST_CPINT_MASK_MSK0_WIDTH (1)
+#define ST_CPINT_MASK_MSK0_MASK (0x00000001)
+#define ST_CPINT_MASK_MSK0_BIT (0x00000001)
+
+#define ST_CPINT_CLR_CLR15_LSB (15)
+#define ST_CPINT_CLR_CLR15_WIDTH (1)
+#define ST_CPINT_CLR_CLR15_MASK (0x00008000)
+#define ST_CPINT_CLR_CLR15_BIT (0x00008000)
+
+#define ST_CPINT_CLR_CLR14_LSB (14)
+#define ST_CPINT_CLR_CLR14_WIDTH (1)
+#define ST_CPINT_CLR_CLR14_MASK (0x00004000)
+#define ST_CPINT_CLR_CLR14_BIT (0x00004000)
+
+#define ST_CPINT_CLR_CLR13_LSB (13)
+#define ST_CPINT_CLR_CLR13_WIDTH (1)
+#define ST_CPINT_CLR_CLR13_MASK (0x00002000)
+#define ST_CPINT_CLR_CLR13_BIT (0x00002000)
+
+#define ST_CPINT_CLR_CLR12_LSB (12)
+#define ST_CPINT_CLR_CLR12_WIDTH (1)
+#define ST_CPINT_CLR_CLR12_MASK (0x00001000)
+#define ST_CPINT_CLR_CLR12_BIT (0x00001000)
+
+#define ST_CPINT_CLR_CLR11_LSB (11)
+#define ST_CPINT_CLR_CLR11_WIDTH (1)
+#define ST_CPINT_CLR_CLR11_MASK (0x00000800)
+#define ST_CPINT_CLR_CLR11_BIT (0x00000800)
+
+#define ST_CPINT_CLR_CLR10_LSB (10)
+#define ST_CPINT_CLR_CLR10_WIDTH (1)
+#define ST_CPINT_CLR_CLR10_MASK (0x00000400)
+#define ST_CPINT_CLR_CLR10_BIT (0x00000400)
+
+#define ST_CPINT_CLR_CLR9_LSB (9)
+#define ST_CPINT_CLR_CLR9_WIDTH (1)
+#define ST_CPINT_CLR_CLR9_MASK (0x00000200)
+#define ST_CPINT_CLR_CLR9_BIT (0x00000200)
+
+#define ST_CPINT_CLR_CLR8_LSB (8)
+#define ST_CPINT_CLR_CLR8_WIDTH (1)
+#define ST_CPINT_CLR_CLR8_MASK (0x00000100)
+#define ST_CPINT_CLR_CLR8_BIT (0x00000100)
+
+#define ST_CPINT_CLR_CLR7_LSB (7)
+#define ST_CPINT_CLR_CLR7_WIDTH (1)
+#define ST_CPINT_CLR_CLR7_MASK (0x00000080)
+#define ST_CPINT_CLR_CLR7_BIT (0x00000080)
+
+#define ST_CPINT_CLR_CLR6_LSB (6)
+#define ST_CPINT_CLR_CLR6_WIDTH (1)
+#define ST_CPINT_CLR_CLR6_MASK (0x00000040)
+#define ST_CPINT_CLR_CLR6_BIT (0x00000040)
+
+#define ST_CPINT_CLR_CLR5_LSB (5)
+#define ST_CPINT_CLR_CLR5_WIDTH (1)
+#define ST_CPINT_CLR_CLR5_MASK (0x00000020)
+#define ST_CPINT_CLR_CLR5_BIT (0x00000020)
+
+#define ST_CPINT_CLR_CLR4_LSB (4)
+#define ST_CPINT_CLR_CLR4_WIDTH (1)
+#define ST_CPINT_CLR_CLR4_MASK (0x00000010)
+#define ST_CPINT_CLR_CLR4_BIT (0x00000010)
+
+#define ST_CPINT_CLR_CLR3_LSB (3)
+#define ST_CPINT_CLR_CLR3_WIDTH (1)
+#define ST_CPINT_CLR_CLR3_MASK (0x00000008)
+#define ST_CPINT_CLR_CLR3_BIT (0x00000008)
+
+#define ST_CPINT_CLR_CLR2_LSB (2)
+#define ST_CPINT_CLR_CLR2_WIDTH (1)
+#define ST_CPINT_CLR_CLR2_MASK (0x00000004)
+#define ST_CPINT_CLR_CLR2_BIT (0x00000004)
+
+#define ST_CPINT_CLR_CLR1_LSB (1)
+#define ST_CPINT_CLR_CLR1_WIDTH (1)
+#define ST_CPINT_CLR_CLR1_MASK (0x00000002)
+#define ST_CPINT_CLR_CLR1_BIT (0x00000002)
+
+#define ST_CPINT_CLR_CLR0_LSB (0)
+#define ST_CPINT_CLR_CLR0_WIDTH (1)
+#define ST_CPINT_CLR_CLR0_MASK (0x00000001)
+#define ST_CPINT_CLR_CLR0_BIT (0x00000001)
+
+#define ST_CPINT_SRC_SRC15_LSB (15)
+#define ST_CPINT_SRC_SRC15_WIDTH (1)
+#define ST_CPINT_SRC_SRC15_MASK (0x00008000)
+#define ST_CPINT_SRC_SRC15_BIT (0x00008000)
+
+#define ST_CPINT_SRC_SRC14_LSB (14)
+#define ST_CPINT_SRC_SRC14_WIDTH (1)
+#define ST_CPINT_SRC_SRC14_MASK (0x00004000)
+#define ST_CPINT_SRC_SRC14_BIT (0x00004000)
+
+#define ST_CPINT_SRC_SRC13_LSB (13)
+#define ST_CPINT_SRC_SRC13_WIDTH (1)
+#define ST_CPINT_SRC_SRC13_MASK (0x00002000)
+#define ST_CPINT_SRC_SRC13_BIT (0x00002000)
+
+#define ST_CPINT_SRC_SRC12_LSB (12)
+#define ST_CPINT_SRC_SRC12_WIDTH (1)
+#define ST_CPINT_SRC_SRC12_MASK (0x00001000)
+#define ST_CPINT_SRC_SRC12_BIT (0x00001000)
+
+#define ST_CPINT_SRC_SRC11_LSB (11)
+#define ST_CPINT_SRC_SRC11_WIDTH (1)
+#define ST_CPINT_SRC_SRC11_MASK (0x00000800)
+#define ST_CPINT_SRC_SRC11_BIT (0x00000800)
+
+#define ST_CPINT_SRC_SRC10_LSB (10)
+#define ST_CPINT_SRC_SRC10_WIDTH (1)
+#define ST_CPINT_SRC_SRC10_MASK (0x00000400)
+#define ST_CPINT_SRC_SRC10_BIT (0x00000400)
+
+#define ST_CPINT_SRC_SRC9_LSB (9)
+#define ST_CPINT_SRC_SRC9_WIDTH (1)
+#define ST_CPINT_SRC_SRC9_MASK (0x00000200)
+#define ST_CPINT_SRC_SRC9_BIT (0x00000200)
+
+#define ST_CPINT_SRC_SRC8_LSB (8)
+#define ST_CPINT_SRC_SRC8_WIDTH (1)
+#define ST_CPINT_SRC_SRC8_MASK (0x00000100)
+#define ST_CPINT_SRC_SRC8_BIT (0x00000100)
+
+#define ST_CPINT_SRC_SRC7_LSB (7)
+#define ST_CPINT_SRC_SRC7_WIDTH (1)
+#define ST_CPINT_SRC_SRC7_MASK (0x00000080)
+#define ST_CPINT_SRC_SRC7_BIT (0x00000080)
+
+#define ST_CPINT_SRC_SRC6_LSB (6)
+#define ST_CPINT_SRC_SRC6_WIDTH (1)
+#define ST_CPINT_SRC_SRC6_MASK (0x00000040)
+#define ST_CPINT_SRC_SRC6_BIT (0x00000040)
+
+#define ST_CPINT_SRC_SRC5_LSB (5)
+#define ST_CPINT_SRC_SRC5_WIDTH (1)
+#define ST_CPINT_SRC_SRC5_MASK (0x00000020)
+#define ST_CPINT_SRC_SRC5_BIT (0x00000020)
+
+#define ST_CPINT_SRC_SRC4_LSB (4)
+#define ST_CPINT_SRC_SRC4_WIDTH (1)
+#define ST_CPINT_SRC_SRC4_MASK (0x00000010)
+#define ST_CPINT_SRC_SRC4_BIT (0x00000010)
+
+#define ST_CPINT_SRC_SRC3_LSB (3)
+#define ST_CPINT_SRC_SRC3_WIDTH (1)
+#define ST_CPINT_SRC_SRC3_MASK (0x00000008)
+#define ST_CPINT_SRC_SRC3_BIT (0x00000008)
+
+#define ST_CPINT_SRC_SRC2_LSB (2)
+#define ST_CPINT_SRC_SRC2_WIDTH (1)
+#define ST_CPINT_SRC_SRC2_MASK (0x00000004)
+#define ST_CPINT_SRC_SRC2_BIT (0x00000004)
+
+#define ST_CPINT_SRC_SRC1_LSB (1)
+#define ST_CPINT_SRC_SRC1_WIDTH (1)
+#define ST_CPINT_SRC_SRC1_MASK (0x00000002)
+#define ST_CPINT_SRC_SRC1_BIT (0x00000002)
+
+#define ST_CPINT_SRC_SRC0_LSB (0)
+#define ST_CPINT_SRC_SRC0_WIDTH (1)
+#define ST_CPINT_SRC_SRC0_MASK (0x00000001)
+#define ST_CPINT_SRC_SRC0_BIT (0x00000001)
+
+#define ST_CPINT_ISR_ISR15_LSB (15)
+#define ST_CPINT_ISR_ISR15_WIDTH (1)
+#define ST_CPINT_ISR_ISR15_MASK (0x00008000)
+#define ST_CPINT_ISR_ISR15_BIT (0x00008000)
+
+#define ST_CPINT_ISR_ISR14_LSB (14)
+#define ST_CPINT_ISR_ISR14_WIDTH (1)
+#define ST_CPINT_ISR_ISR14_MASK (0x00004000)
+#define ST_CPINT_ISR_ISR14_BIT (0x00004000)
+
+#define ST_CPINT_ISR_ISR13_LSB (13)
+#define ST_CPINT_ISR_ISR13_WIDTH (1)
+#define ST_CPINT_ISR_ISR13_MASK (0x00002000)
+#define ST_CPINT_ISR_ISR13_BIT (0x00002000)
+
+#define ST_CPINT_ISR_ISR12_LSB (12)
+#define ST_CPINT_ISR_ISR12_WIDTH (1)
+#define ST_CPINT_ISR_ISR12_MASK (0x00001000)
+#define ST_CPINT_ISR_ISR12_BIT (0x00001000)
+
+#define ST_CPINT_ISR_ISR11_LSB (11)
+#define ST_CPINT_ISR_ISR11_WIDTH (1)
+#define ST_CPINT_ISR_ISR11_MASK (0x00000800)
+#define ST_CPINT_ISR_ISR11_BIT (0x00000800)
+
+#define ST_CPINT_ISR_ISR10_LSB (10)
+#define ST_CPINT_ISR_ISR10_WIDTH (1)
+#define ST_CPINT_ISR_ISR10_MASK (0x00000400)
+#define ST_CPINT_ISR_ISR10_BIT (0x00000400)
+
+#define ST_CPINT_ISR_ISR9_LSB (9)
+#define ST_CPINT_ISR_ISR9_WIDTH (1)
+#define ST_CPINT_ISR_ISR9_MASK (0x00000200)
+#define ST_CPINT_ISR_ISR9_BIT (0x00000200)
+
+#define ST_CPINT_ISR_ISR8_LSB (8)
+#define ST_CPINT_ISR_ISR8_WIDTH (1)
+#define ST_CPINT_ISR_ISR8_MASK (0x00000100)
+#define ST_CPINT_ISR_ISR8_BIT (0x00000100)
+
+#define ST_CPINT_ISR_ISR7_LSB (7)
+#define ST_CPINT_ISR_ISR7_WIDTH (1)
+#define ST_CPINT_ISR_ISR7_MASK (0x00000080)
+#define ST_CPINT_ISR_ISR7_BIT (0x00000080)
+
+#define ST_CPINT_ISR_ISR6_LSB (6)
+#define ST_CPINT_ISR_ISR6_WIDTH (1)
+#define ST_CPINT_ISR_ISR6_MASK (0x00000040)
+#define ST_CPINT_ISR_ISR6_BIT (0x00000040)
+
+#define ST_CPINT_ISR_ISR5_LSB (5)
+#define ST_CPINT_ISR_ISR5_WIDTH (1)
+#define ST_CPINT_ISR_ISR5_MASK (0x00000020)
+#define ST_CPINT_ISR_ISR5_BIT (0x00000020)
+
+#define ST_CPINT_ISR_ISR4_LSB (4)
+#define ST_CPINT_ISR_ISR4_WIDTH (1)
+#define ST_CPINT_ISR_ISR4_MASK (0x00000010)
+#define ST_CPINT_ISR_ISR4_BIT (0x00000010)
+
+#define ST_CPINT_ISR_ISR3_LSB (3)
+#define ST_CPINT_ISR_ISR3_WIDTH (1)
+#define ST_CPINT_ISR_ISR3_MASK (0x00000008)
+#define ST_CPINT_ISR_ISR3_BIT (0x00000008)
+
+#define ST_CPINT_ISR_ISR2_LSB (2)
+#define ST_CPINT_ISR_ISR2_WIDTH (1)
+#define ST_CPINT_ISR_ISR2_MASK (0x00000004)
+#define ST_CPINT_ISR_ISR2_BIT (0x00000004)
+
+#define ST_CPINT_ISR_ISR1_LSB (1)
+#define ST_CPINT_ISR_ISR1_WIDTH (1)
+#define ST_CPINT_ISR_ISR1_MASK (0x00000002)
+#define ST_CPINT_ISR_ISR1_BIT (0x00000002)
+
+#define ST_CPINT_ISR_ISR0_LSB (0)
+#define ST_CPINT_ISR_ISR0_WIDTH (1)
+#define ST_CPINT_ISR_ISR0_MASK (0x00000001)
+#define ST_CPINT_ISR_ISR0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_WIDTH (11)
+#define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_MASK (0x00001FFC)
+
+#define ST_HALF_CPINT_MASK_MSK31_LSB (31)
+#define ST_HALF_CPINT_MASK_MSK31_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK31_MASK (0x80000000)
+#define ST_HALF_CPINT_MASK_MSK31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_MASK_MSK30_LSB (30)
+#define ST_HALF_CPINT_MASK_MSK30_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK30_MASK (0x40000000)
+#define ST_HALF_CPINT_MASK_MSK30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_MASK_MSK29_LSB (29)
+#define ST_HALF_CPINT_MASK_MSK29_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK29_MASK (0x20000000)
+#define ST_HALF_CPINT_MASK_MSK29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_MASK_MSK28_LSB (28)
+#define ST_HALF_CPINT_MASK_MSK28_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK28_MASK (0x10000000)
+#define ST_HALF_CPINT_MASK_MSK28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_MASK_MSK27_LSB (27)
+#define ST_HALF_CPINT_MASK_MSK27_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK27_MASK (0x08000000)
+#define ST_HALF_CPINT_MASK_MSK27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_MASK_MSK26_LSB (26)
+#define ST_HALF_CPINT_MASK_MSK26_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK26_MASK (0x04000000)
+#define ST_HALF_CPINT_MASK_MSK26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_MASK_MSK25_LSB (25)
+#define ST_HALF_CPINT_MASK_MSK25_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK25_MASK (0x02000000)
+#define ST_HALF_CPINT_MASK_MSK25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_MASK_MSK24_LSB (24)
+#define ST_HALF_CPINT_MASK_MSK24_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK24_MASK (0x01000000)
+#define ST_HALF_CPINT_MASK_MSK24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_MASK_MSK23_LSB (23)
+#define ST_HALF_CPINT_MASK_MSK23_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK23_MASK (0x00800000)
+#define ST_HALF_CPINT_MASK_MSK23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_MASK_MSK22_LSB (22)
+#define ST_HALF_CPINT_MASK_MSK22_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK22_MASK (0x00400000)
+#define ST_HALF_CPINT_MASK_MSK22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_MASK_MSK21_LSB (21)
+#define ST_HALF_CPINT_MASK_MSK21_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK21_MASK (0x00200000)
+#define ST_HALF_CPINT_MASK_MSK21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_MASK_MSK20_LSB (20)
+#define ST_HALF_CPINT_MASK_MSK20_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK20_MASK (0x00100000)
+#define ST_HALF_CPINT_MASK_MSK20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_MASK_MSK19_LSB (19)
+#define ST_HALF_CPINT_MASK_MSK19_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK19_MASK (0x00080000)
+#define ST_HALF_CPINT_MASK_MSK19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_MASK_MSK18_LSB (18)
+#define ST_HALF_CPINT_MASK_MSK18_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK18_MASK (0x00040000)
+#define ST_HALF_CPINT_MASK_MSK18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_MASK_MSK17_LSB (17)
+#define ST_HALF_CPINT_MASK_MSK17_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK17_MASK (0x00020000)
+#define ST_HALF_CPINT_MASK_MSK17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_MASK_MSK16_LSB (16)
+#define ST_HALF_CPINT_MASK_MSK16_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK16_MASK (0x00010000)
+#define ST_HALF_CPINT_MASK_MSK16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_MASK_MSK15_LSB (15)
+#define ST_HALF_CPINT_MASK_MSK15_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK15_MASK (0x00008000)
+#define ST_HALF_CPINT_MASK_MSK15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_MASK_MSK14_LSB (14)
+#define ST_HALF_CPINT_MASK_MSK14_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK14_MASK (0x00004000)
+#define ST_HALF_CPINT_MASK_MSK14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_MASK_MSK13_LSB (13)
+#define ST_HALF_CPINT_MASK_MSK13_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK13_MASK (0x00002000)
+#define ST_HALF_CPINT_MASK_MSK13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_MASK_MSK12_LSB (12)
+#define ST_HALF_CPINT_MASK_MSK12_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK12_MASK (0x00001000)
+#define ST_HALF_CPINT_MASK_MSK12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_MASK_MSK11_LSB (11)
+#define ST_HALF_CPINT_MASK_MSK11_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK11_MASK (0x00000800)
+#define ST_HALF_CPINT_MASK_MSK11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_MASK_MSK10_LSB (10)
+#define ST_HALF_CPINT_MASK_MSK10_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK10_MASK (0x00000400)
+#define ST_HALF_CPINT_MASK_MSK10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_MASK_MSK9_LSB (9)
+#define ST_HALF_CPINT_MASK_MSK9_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK9_MASK (0x00000200)
+#define ST_HALF_CPINT_MASK_MSK9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_MASK_MSK8_LSB (8)
+#define ST_HALF_CPINT_MASK_MSK8_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK8_MASK (0x00000100)
+#define ST_HALF_CPINT_MASK_MSK8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_MASK_MSK7_LSB (7)
+#define ST_HALF_CPINT_MASK_MSK7_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK7_MASK (0x00000080)
+#define ST_HALF_CPINT_MASK_MSK7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_MASK_MSK6_LSB (6)
+#define ST_HALF_CPINT_MASK_MSK6_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK6_MASK (0x00000040)
+#define ST_HALF_CPINT_MASK_MSK6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_MASK_MSK5_LSB (5)
+#define ST_HALF_CPINT_MASK_MSK5_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK5_MASK (0x00000020)
+#define ST_HALF_CPINT_MASK_MSK5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_MASK_MSK4_LSB (4)
+#define ST_HALF_CPINT_MASK_MSK4_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK4_MASK (0x00000010)
+#define ST_HALF_CPINT_MASK_MSK4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_MASK_MSK3_LSB (3)
+#define ST_HALF_CPINT_MASK_MSK3_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK3_MASK (0x00000008)
+#define ST_HALF_CPINT_MASK_MSK3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_MASK_MSK2_LSB (2)
+#define ST_HALF_CPINT_MASK_MSK2_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK2_MASK (0x00000004)
+#define ST_HALF_CPINT_MASK_MSK2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_MASK_MSK1_LSB (1)
+#define ST_HALF_CPINT_MASK_MSK1_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK1_MASK (0x00000002)
+#define ST_HALF_CPINT_MASK_MSK1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_MASK_MSK0_LSB (0)
+#define ST_HALF_CPINT_MASK_MSK0_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK0_MASK (0x00000001)
+#define ST_HALF_CPINT_MASK_MSK0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_CLR_CLR31_LSB (31)
+#define ST_HALF_CPINT_CLR_CLR31_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR31_MASK (0x80000000)
+#define ST_HALF_CPINT_CLR_CLR31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_CLR_CLR30_LSB (30)
+#define ST_HALF_CPINT_CLR_CLR30_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR30_MASK (0x40000000)
+#define ST_HALF_CPINT_CLR_CLR30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_CLR_CLR29_LSB (29)
+#define ST_HALF_CPINT_CLR_CLR29_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR29_MASK (0x20000000)
+#define ST_HALF_CPINT_CLR_CLR29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_CLR_CLR28_LSB (28)
+#define ST_HALF_CPINT_CLR_CLR28_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR28_MASK (0x10000000)
+#define ST_HALF_CPINT_CLR_CLR28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_CLR_CLR27_LSB (27)
+#define ST_HALF_CPINT_CLR_CLR27_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR27_MASK (0x08000000)
+#define ST_HALF_CPINT_CLR_CLR27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_CLR_CLR26_LSB (26)
+#define ST_HALF_CPINT_CLR_CLR26_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR26_MASK (0x04000000)
+#define ST_HALF_CPINT_CLR_CLR26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_CLR_CLR25_LSB (25)
+#define ST_HALF_CPINT_CLR_CLR25_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR25_MASK (0x02000000)
+#define ST_HALF_CPINT_CLR_CLR25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_CLR_CLR24_LSB (24)
+#define ST_HALF_CPINT_CLR_CLR24_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR24_MASK (0x01000000)
+#define ST_HALF_CPINT_CLR_CLR24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_CLR_CLR23_LSB (23)
+#define ST_HALF_CPINT_CLR_CLR23_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR23_MASK (0x00800000)
+#define ST_HALF_CPINT_CLR_CLR23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_CLR_CLR22_LSB (22)
+#define ST_HALF_CPINT_CLR_CLR22_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR22_MASK (0x00400000)
+#define ST_HALF_CPINT_CLR_CLR22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_CLR_CLR21_LSB (21)
+#define ST_HALF_CPINT_CLR_CLR21_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR21_MASK (0x00200000)
+#define ST_HALF_CPINT_CLR_CLR21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_CLR_CLR20_LSB (20)
+#define ST_HALF_CPINT_CLR_CLR20_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR20_MASK (0x00100000)
+#define ST_HALF_CPINT_CLR_CLR20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_CLR_CLR19_LSB (19)
+#define ST_HALF_CPINT_CLR_CLR19_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR19_MASK (0x00080000)
+#define ST_HALF_CPINT_CLR_CLR19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_CLR_CLR18_LSB (18)
+#define ST_HALF_CPINT_CLR_CLR18_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR18_MASK (0x00040000)
+#define ST_HALF_CPINT_CLR_CLR18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_CLR_CLR17_LSB (17)
+#define ST_HALF_CPINT_CLR_CLR17_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR17_MASK (0x00020000)
+#define ST_HALF_CPINT_CLR_CLR17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_CLR_CLR16_LSB (16)
+#define ST_HALF_CPINT_CLR_CLR16_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR16_MASK (0x00010000)
+#define ST_HALF_CPINT_CLR_CLR16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_CLR_CLR15_LSB (15)
+#define ST_HALF_CPINT_CLR_CLR15_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR15_MASK (0x00008000)
+#define ST_HALF_CPINT_CLR_CLR15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_CLR_CLR14_LSB (14)
+#define ST_HALF_CPINT_CLR_CLR14_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR14_MASK (0x00004000)
+#define ST_HALF_CPINT_CLR_CLR14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_CLR_CLR13_LSB (13)
+#define ST_HALF_CPINT_CLR_CLR13_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR13_MASK (0x00002000)
+#define ST_HALF_CPINT_CLR_CLR13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_CLR_CLR12_LSB (12)
+#define ST_HALF_CPINT_CLR_CLR12_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR12_MASK (0x00001000)
+#define ST_HALF_CPINT_CLR_CLR12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_CLR_CLR11_LSB (11)
+#define ST_HALF_CPINT_CLR_CLR11_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR11_MASK (0x00000800)
+#define ST_HALF_CPINT_CLR_CLR11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_CLR_CLR10_LSB (10)
+#define ST_HALF_CPINT_CLR_CLR10_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR10_MASK (0x00000400)
+#define ST_HALF_CPINT_CLR_CLR10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_CLR_CLR9_LSB (9)
+#define ST_HALF_CPINT_CLR_CLR9_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR9_MASK (0x00000200)
+#define ST_HALF_CPINT_CLR_CLR9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_CLR_CLR8_LSB (8)
+#define ST_HALF_CPINT_CLR_CLR8_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR8_MASK (0x00000100)
+#define ST_HALF_CPINT_CLR_CLR8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_CLR_CLR7_LSB (7)
+#define ST_HALF_CPINT_CLR_CLR7_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR7_MASK (0x00000080)
+#define ST_HALF_CPINT_CLR_CLR7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_CLR_CLR6_LSB (6)
+#define ST_HALF_CPINT_CLR_CLR6_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR6_MASK (0x00000040)
+#define ST_HALF_CPINT_CLR_CLR6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_CLR_CLR5_LSB (5)
+#define ST_HALF_CPINT_CLR_CLR5_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR5_MASK (0x00000020)
+#define ST_HALF_CPINT_CLR_CLR5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_CLR_CLR4_LSB (4)
+#define ST_HALF_CPINT_CLR_CLR4_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR4_MASK (0x00000010)
+#define ST_HALF_CPINT_CLR_CLR4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_CLR_CLR3_LSB (3)
+#define ST_HALF_CPINT_CLR_CLR3_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR3_MASK (0x00000008)
+#define ST_HALF_CPINT_CLR_CLR3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_CLR_CLR2_LSB (2)
+#define ST_HALF_CPINT_CLR_CLR2_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR2_MASK (0x00000004)
+#define ST_HALF_CPINT_CLR_CLR2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_CLR_CLR1_LSB (1)
+#define ST_HALF_CPINT_CLR_CLR1_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR1_MASK (0x00000002)
+#define ST_HALF_CPINT_CLR_CLR1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_CLR_CLR0_LSB (0)
+#define ST_HALF_CPINT_CLR_CLR0_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR0_MASK (0x00000001)
+#define ST_HALF_CPINT_CLR_CLR0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_SRC_SRC31_LSB (31)
+#define ST_HALF_CPINT_SRC_SRC31_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC31_MASK (0x80000000)
+#define ST_HALF_CPINT_SRC_SRC31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_SRC_SRC30_LSB (30)
+#define ST_HALF_CPINT_SRC_SRC30_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC30_MASK (0x40000000)
+#define ST_HALF_CPINT_SRC_SRC30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_SRC_SRC29_LSB (29)
+#define ST_HALF_CPINT_SRC_SRC29_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC29_MASK (0x20000000)
+#define ST_HALF_CPINT_SRC_SRC29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_SRC_SRC28_LSB (28)
+#define ST_HALF_CPINT_SRC_SRC28_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC28_MASK (0x10000000)
+#define ST_HALF_CPINT_SRC_SRC28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_SRC_SRC27_LSB (27)
+#define ST_HALF_CPINT_SRC_SRC27_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC27_MASK (0x08000000)
+#define ST_HALF_CPINT_SRC_SRC27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_SRC_SRC26_LSB (26)
+#define ST_HALF_CPINT_SRC_SRC26_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC26_MASK (0x04000000)
+#define ST_HALF_CPINT_SRC_SRC26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_SRC_SRC25_LSB (25)
+#define ST_HALF_CPINT_SRC_SRC25_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC25_MASK (0x02000000)
+#define ST_HALF_CPINT_SRC_SRC25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_SRC_SRC24_LSB (24)
+#define ST_HALF_CPINT_SRC_SRC24_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC24_MASK (0x01000000)
+#define ST_HALF_CPINT_SRC_SRC24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_SRC_SRC23_LSB (23)
+#define ST_HALF_CPINT_SRC_SRC23_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC23_MASK (0x00800000)
+#define ST_HALF_CPINT_SRC_SRC23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_SRC_SRC22_LSB (22)
+#define ST_HALF_CPINT_SRC_SRC22_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC22_MASK (0x00400000)
+#define ST_HALF_CPINT_SRC_SRC22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_SRC_SRC21_LSB (21)
+#define ST_HALF_CPINT_SRC_SRC21_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC21_MASK (0x00200000)
+#define ST_HALF_CPINT_SRC_SRC21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_SRC_SRC20_LSB (20)
+#define ST_HALF_CPINT_SRC_SRC20_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC20_MASK (0x00100000)
+#define ST_HALF_CPINT_SRC_SRC20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_SRC_SRC19_LSB (19)
+#define ST_HALF_CPINT_SRC_SRC19_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC19_MASK (0x00080000)
+#define ST_HALF_CPINT_SRC_SRC19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_SRC_SRC18_LSB (18)
+#define ST_HALF_CPINT_SRC_SRC18_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC18_MASK (0x00040000)
+#define ST_HALF_CPINT_SRC_SRC18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_SRC_SRC17_LSB (17)
+#define ST_HALF_CPINT_SRC_SRC17_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC17_MASK (0x00020000)
+#define ST_HALF_CPINT_SRC_SRC17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_SRC_SRC16_LSB (16)
+#define ST_HALF_CPINT_SRC_SRC16_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC16_MASK (0x00010000)
+#define ST_HALF_CPINT_SRC_SRC16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_SRC_SRC15_LSB (15)
+#define ST_HALF_CPINT_SRC_SRC15_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC15_MASK (0x00008000)
+#define ST_HALF_CPINT_SRC_SRC15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_SRC_SRC14_LSB (14)
+#define ST_HALF_CPINT_SRC_SRC14_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC14_MASK (0x00004000)
+#define ST_HALF_CPINT_SRC_SRC14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_SRC_SRC13_LSB (13)
+#define ST_HALF_CPINT_SRC_SRC13_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC13_MASK (0x00002000)
+#define ST_HALF_CPINT_SRC_SRC13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_SRC_SRC12_LSB (12)
+#define ST_HALF_CPINT_SRC_SRC12_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC12_MASK (0x00001000)
+#define ST_HALF_CPINT_SRC_SRC12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_SRC_SRC11_LSB (11)
+#define ST_HALF_CPINT_SRC_SRC11_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC11_MASK (0x00000800)
+#define ST_HALF_CPINT_SRC_SRC11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_SRC_SRC10_LSB (10)
+#define ST_HALF_CPINT_SRC_SRC10_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC10_MASK (0x00000400)
+#define ST_HALF_CPINT_SRC_SRC10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_SRC_SRC9_LSB (9)
+#define ST_HALF_CPINT_SRC_SRC9_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC9_MASK (0x00000200)
+#define ST_HALF_CPINT_SRC_SRC9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_SRC_SRC8_LSB (8)
+#define ST_HALF_CPINT_SRC_SRC8_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC8_MASK (0x00000100)
+#define ST_HALF_CPINT_SRC_SRC8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_SRC_SRC7_LSB (7)
+#define ST_HALF_CPINT_SRC_SRC7_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC7_MASK (0x00000080)
+#define ST_HALF_CPINT_SRC_SRC7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_SRC_SRC6_LSB (6)
+#define ST_HALF_CPINT_SRC_SRC6_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC6_MASK (0x00000040)
+#define ST_HALF_CPINT_SRC_SRC6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_SRC_SRC5_LSB (5)
+#define ST_HALF_CPINT_SRC_SRC5_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC5_MASK (0x00000020)
+#define ST_HALF_CPINT_SRC_SRC5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_SRC_SRC4_LSB (4)
+#define ST_HALF_CPINT_SRC_SRC4_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC4_MASK (0x00000010)
+#define ST_HALF_CPINT_SRC_SRC4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_SRC_SRC3_LSB (3)
+#define ST_HALF_CPINT_SRC_SRC3_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC3_MASK (0x00000008)
+#define ST_HALF_CPINT_SRC_SRC3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_SRC_SRC2_LSB (2)
+#define ST_HALF_CPINT_SRC_SRC2_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC2_MASK (0x00000004)
+#define ST_HALF_CPINT_SRC_SRC2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_SRC_SRC1_LSB (1)
+#define ST_HALF_CPINT_SRC_SRC1_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC1_MASK (0x00000002)
+#define ST_HALF_CPINT_SRC_SRC1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_SRC_SRC0_LSB (0)
+#define ST_HALF_CPINT_SRC_SRC0_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC0_MASK (0x00000001)
+#define ST_HALF_CPINT_SRC_SRC0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_ISR_ISR31_LSB (31)
+#define ST_HALF_CPINT_ISR_ISR31_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR31_MASK (0x80000000)
+#define ST_HALF_CPINT_ISR_ISR31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_ISR_ISR30_LSB (30)
+#define ST_HALF_CPINT_ISR_ISR30_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR30_MASK (0x40000000)
+#define ST_HALF_CPINT_ISR_ISR30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_ISR_ISR29_LSB (29)
+#define ST_HALF_CPINT_ISR_ISR29_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR29_MASK (0x20000000)
+#define ST_HALF_CPINT_ISR_ISR29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_ISR_ISR28_LSB (28)
+#define ST_HALF_CPINT_ISR_ISR28_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR28_MASK (0x10000000)
+#define ST_HALF_CPINT_ISR_ISR28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_ISR_ISR27_LSB (27)
+#define ST_HALF_CPINT_ISR_ISR27_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR27_MASK (0x08000000)
+#define ST_HALF_CPINT_ISR_ISR27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_ISR_ISR26_LSB (26)
+#define ST_HALF_CPINT_ISR_ISR26_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR26_MASK (0x04000000)
+#define ST_HALF_CPINT_ISR_ISR26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_ISR_ISR25_LSB (25)
+#define ST_HALF_CPINT_ISR_ISR25_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR25_MASK (0x02000000)
+#define ST_HALF_CPINT_ISR_ISR25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_ISR_ISR24_LSB (24)
+#define ST_HALF_CPINT_ISR_ISR24_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR24_MASK (0x01000000)
+#define ST_HALF_CPINT_ISR_ISR24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_ISR_ISR23_LSB (23)
+#define ST_HALF_CPINT_ISR_ISR23_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR23_MASK (0x00800000)
+#define ST_HALF_CPINT_ISR_ISR23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_ISR_ISR22_LSB (22)
+#define ST_HALF_CPINT_ISR_ISR22_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR22_MASK (0x00400000)
+#define ST_HALF_CPINT_ISR_ISR22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_ISR_ISR21_LSB (21)
+#define ST_HALF_CPINT_ISR_ISR21_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR21_MASK (0x00200000)
+#define ST_HALF_CPINT_ISR_ISR21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_ISR_ISR20_LSB (20)
+#define ST_HALF_CPINT_ISR_ISR20_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR20_MASK (0x00100000)
+#define ST_HALF_CPINT_ISR_ISR20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_ISR_ISR19_LSB (19)
+#define ST_HALF_CPINT_ISR_ISR19_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR19_MASK (0x00080000)
+#define ST_HALF_CPINT_ISR_ISR19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_ISR_ISR18_LSB (18)
+#define ST_HALF_CPINT_ISR_ISR18_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR18_MASK (0x00040000)
+#define ST_HALF_CPINT_ISR_ISR18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_ISR_ISR17_LSB (17)
+#define ST_HALF_CPINT_ISR_ISR17_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR17_MASK (0x00020000)
+#define ST_HALF_CPINT_ISR_ISR17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_ISR_ISR16_LSB (16)
+#define ST_HALF_CPINT_ISR_ISR16_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR16_MASK (0x00010000)
+#define ST_HALF_CPINT_ISR_ISR16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_ISR_ISR15_LSB (15)
+#define ST_HALF_CPINT_ISR_ISR15_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR15_MASK (0x00008000)
+#define ST_HALF_CPINT_ISR_ISR15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_ISR_ISR14_LSB (14)
+#define ST_HALF_CPINT_ISR_ISR14_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR14_MASK (0x00004000)
+#define ST_HALF_CPINT_ISR_ISR14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_ISR_ISR13_LSB (13)
+#define ST_HALF_CPINT_ISR_ISR13_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR13_MASK (0x00002000)
+#define ST_HALF_CPINT_ISR_ISR13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_ISR_ISR12_LSB (12)
+#define ST_HALF_CPINT_ISR_ISR12_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR12_MASK (0x00001000)
+#define ST_HALF_CPINT_ISR_ISR12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_ISR_ISR11_LSB (11)
+#define ST_HALF_CPINT_ISR_ISR11_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR11_MASK (0x00000800)
+#define ST_HALF_CPINT_ISR_ISR11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_ISR_ISR10_LSB (10)
+#define ST_HALF_CPINT_ISR_ISR10_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR10_MASK (0x00000400)
+#define ST_HALF_CPINT_ISR_ISR10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_ISR_ISR9_LSB (9)
+#define ST_HALF_CPINT_ISR_ISR9_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR9_MASK (0x00000200)
+#define ST_HALF_CPINT_ISR_ISR9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_ISR_ISR8_LSB (8)
+#define ST_HALF_CPINT_ISR_ISR8_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR8_MASK (0x00000100)
+#define ST_HALF_CPINT_ISR_ISR8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_ISR_ISR7_LSB (7)
+#define ST_HALF_CPINT_ISR_ISR7_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR7_MASK (0x00000080)
+#define ST_HALF_CPINT_ISR_ISR7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_ISR_ISR6_LSB (6)
+#define ST_HALF_CPINT_ISR_ISR6_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR6_MASK (0x00000040)
+#define ST_HALF_CPINT_ISR_ISR6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_ISR_ISR5_LSB (5)
+#define ST_HALF_CPINT_ISR_ISR5_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR5_MASK (0x00000020)
+#define ST_HALF_CPINT_ISR_ISR5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_ISR_ISR4_LSB (4)
+#define ST_HALF_CPINT_ISR_ISR4_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR4_MASK (0x00000010)
+#define ST_HALF_CPINT_ISR_ISR4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_ISR_ISR3_LSB (3)
+#define ST_HALF_CPINT_ISR_ISR3_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR3_MASK (0x00000008)
+#define ST_HALF_CPINT_ISR_ISR3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_ISR_ISR2_LSB (2)
+#define ST_HALF_CPINT_ISR_ISR2_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR2_MASK (0x00000004)
+#define ST_HALF_CPINT_ISR_ISR2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_ISR_ISR1_LSB (1)
+#define ST_HALF_CPINT_ISR_ISR1_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR1_MASK (0x00000002)
+#define ST_HALF_CPINT_ISR_ISR1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_ISR_ISR0_LSB (0)
+#define ST_HALF_CPINT_ISR_ISR0_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR0_MASK (0x00000001)
+#define ST_HALF_CPINT_ISR_ISR0_BIT (0x00000001)
+
+#define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_CFG_CPINT_EN_EN_LSB (0)
+#define ST_CFG_CPINT_EN_EN_WIDTH (1)
+#define ST_CFG_CPINT_EN_EN_MASK (0x00000001)
+#define ST_CFG_CPINT_EN_EN_BIT (0x00000001)
+
+#define ST_CFG_CPINT_ISR_ISR_LSB (0)
+#define ST_CFG_CPINT_ISR_ISR_WIDTH (1)
+#define ST_CFG_CPINT_ISR_ISR_MASK (0x00000001)
+#define ST_CFG_CPINT_ISR_ISR_BIT (0x00000001)
+
+#define ST_CFG_CPINT_CLR_CLR_LSB (0)
+#define ST_CFG_CPINT_CLR_CLR_WIDTH (1)
+#define ST_CFG_CPINT_CLR_CLR_MASK (0x00000001)
+#define ST_CFG_CPINT_CLR_CLR_BIT (0x00000001)
+
+#define ST_SUBFR_STATUS_SUBFR_STATUS_LSB (0)
+#define ST_SUBFR_STATUS_SUBFR_STATUS_WIDTH (6)
+#define ST_SUBFR_STATUS_SUBFR_STATUS_MASK (0x0000003F)
+
+#define ST_SYSCNT_SYSTEM_TIME_CNT_LSB (0)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_MAX (0x000BFFFF)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_ROUND (0x000C0000)
+
+#define ST_SUPFRM_CNT_L_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_L_SUPFRM_CNT_WIDTH (32)
+#define ST_SUPFRM_CNT_L_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_SUPFRM_CNT_H_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_H_SUPFRM_CNT_WIDTH (4)
+#define ST_SUPFRM_CNT_H_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_FRC_TIMING_SYNC_MODE_MODE_LSB (0)
+#define ST_FRC_TIMING_SYNC_MODE_MODE_WIDTH (1)
+#define ST_FRC_TIMING_SYNC_MODE_MODE_MASK (0x00000001)
+#define ST_FRC_TIMING_SYNC_MODE_MODE_BIT (0x00000001)
+
+#define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_LSB (2)
+#define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_LSB (0)
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_WIDTH (1)
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_MASK (0x00000001)
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_BIT (0x00000001)
+
+#define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_LSB (0)
+#define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_LSB (0)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_WIDTH (32)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_LSB (0)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_WIDTH (4)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_MU_SFO_EN_LSB (31)
+#define ST_MU_SFO_EN_WIDTH (1)
+#define ST_MU_SFO_EN_MASK (0x80000000)
+#define ST_MU_SFO_EN_BIT (0x80000000)
+
+#define ST_MU_SFO_AFC_PPB_LSB (0)
+#define ST_MU_SFO_AFC_PPB_WIDTH (16)
+#define ST_MU_SFO_AFC_PPB_MASK (0x0000FFFF)
+
+#define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_LSB (0)
+#define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_WIDTH (32)
+#define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_MASK (0xFFFFFFFF)
+
+#define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_LSB (0)
+#define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_WIDTH (8)
+#define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_MASK (0x000000FF)
+
+#define ST_MU_ACC_SET_EN_LSB (31)
+#define ST_MU_ACC_SET_EN_WIDTH (1)
+#define ST_MU_ACC_SET_EN_MASK (0x80000000)
+#define ST_MU_ACC_SET_EN_BIT (0x80000000)
+
+#define ST_MU_ACC_SET_SYSTEM_TIME_CNT_LSB (2)
+#define ST_MU_ACC_SET_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_MU_ACC_SET_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_RAKE_CTL_TIME3_EN_LSB (31)
+#define ST_RAKE_CTL_TIME3_EN_WIDTH (1)
+#define ST_RAKE_CTL_TIME3_EN_MASK (0x80000000)
+#define ST_RAKE_CTL_TIME3_EN_BIT (0x80000000)
+
+#define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_LSB (7)
+#define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_WIDTH (13)
+#define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_MASK (0x000FFF80)
+
+#define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_LSB (2)
+#define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_GSR_SYNC_TRIG_TRIG_LSB (31)
+#define ST_GSR_SYNC_TRIG_TRIG_WIDTH (1)
+#define ST_GSR_SYNC_TRIG_TRIG_MASK (0x80000000)
+#define ST_GSR_SYNC_TRIG_TRIG_BIT (0x80000000)
+
+#define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_LSB (2)
+#define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_WIDTH (18)
+#define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_MASK (0x000FFFFC)
+
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_LSB (0)
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_WIDTH (1)
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_MASK (0x00000001)
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_BIT (0x00000001)
+
+#define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_LSB (0)
+#define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+
+#define ST_1XDOMRG_EN_EN_LSB (0)
+#define ST_1XDOMRG_EN_EN_WIDTH (1)
+#define ST_1XDOMRG_EN_EN_MASK (0x00000001)
+#define ST_1XDOMRG_EN_EN_BIT (0x00000001)
+
+#define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_LSB (3)
+#define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_WIDTH (17)
+#define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFF8)
+
+#define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_LSB (3)
+#define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_WIDTH (17)
+#define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_MASK (0x000FFFF8)
+
+#define ST_GPS_EN_GPS_EN_LSB (0)
+#define ST_GPS_EN_GPS_EN_WIDTH (1)
+#define ST_GPS_EN_GPS_EN_MASK (0x00000001)
+#define ST_GPS_EN_GPS_EN_BIT (0x00000001)
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/cphsystime.h b/mcu/interface/l1/cl1/common/cphsystime.h
new file mode 100644
index 0000000..0f2cf27
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphsystime.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHSYSTIME_H_
+#define _CPHSYSTIME_H_
+
+#include "cl1common.h"
+#include "cphsystemtimer.h"
+#include "kal_general_types.h"
+#include "sysdefs.h"
+#include "sysapi.h"
+
+#define CphSysStIntClr(Airinterface, Mask) HwdWrite32(ST_CPINT_CLR(Airinterface), Mask)
+#define CphSysStHalfIntClr(Airinterface, Mask) HwdWrite32(ST_HALF_CPINT_CLR(Airinterface), Mask)
+
+
+
+/* System Timer Common Part*/
+extern void CphSysTimeInit(void);
+extern void CphSysTimeAdvRet (SysAirInterfaceT Airinterface, kal_uint16 Echips, kal_bool Advance);
+extern void CphSysTimeSyncTime (SysAirInterfaceT Airinterface, kal_uint32 SyncEchip, kal_uint32 EchipIni, kal_uint8 SupfrmIniH, kal_uint32 SupfrmIniL);
+extern void CphSysTimeSetSupfrmCnt (SysAirInterfaceT Airinterface, kal_uint8 SupfrmIniH, kal_uint32 SupfrmIniL);
+extern void CphSysSetFrameSize (SysAirInterfaceT Airinterface, SysFrameSizeT FrameSize);
+extern void CphSysStIntDisable (SysAirInterfaceT Airinterface, kal_uint16 Mask);
+extern void CphSysStIntEnable (SysAirInterfaceT Airinterface, kal_uint16 Mask);
+extern void CphSysStHalfIntDisable (SysAirInterfaceT Airinterface, kal_uint32 Mask);
+extern void CphSysStHalfIntEnable (SysAirInterfaceT Airinterface, kal_uint32 Mask);
+extern void CphSysSetStIntOffset (SysAirInterfaceT Airinterface, kal_uint32 ChipOffset2x);
+extern kal_uint32 CphSysGetStIntOffset (SysAirInterfaceT Airinterface);
+extern void CphSysSetStHalfIntOffset (SysAirInterfaceT Airinterface, kal_uint32 ChipOffset2x);
+extern kal_uint32 CphSysGetStHalfIntOffset (SysAirInterfaceT Airinterface);
+extern void CphSysTimeSetSfo (SysAirInterfaceT Airinterface, kal_int16 AfcPpb);
+extern kal_int16 CphSysTimeGetSfo (SysAirInterfaceT Airinterface);
+extern kal_uint32 CphSysTimeEchipCnt(SysAirInterfaceT Airinterface);
+extern kal_uint64 CphSysTimeSupfrmCnt(SysAirInterfaceT Airinterface);
+extern kal_uint16 CphSysTimeSymbNum(SysAirInterfaceT Airinterface);
+extern kal_int32 CphSysTime1xDiffToDo(void);
+#if defined __MD95__
+extern kal_int64 CphSysTime1xTotalDiffToDo(void);
+#endif
+extern kal_int32 CphSysTimeTxDiffToRx(SysAirInterfaceT Airinterface);
+extern void CphSysTimeWait(SysAirInterfaceT Airinterface, kal_uint32 EchipWait);
+extern kal_int32 CphSysTimeTxDiffToRxInWin(SysAirInterfaceT Airinterface);
+extern void CphSysTimeTxTimerAdj(SysAirInterfaceT Airinterface, kal_int32 Adj32x);
+extern void CphSysTimeTxSyncToRx(SysAirInterfaceT Airinterface);
+
+#if defined(MTK_C2K_COSIM)
+extern void Sys1xPcgLisr(void);
+extern void SysDoSlotLisr(void);
+extern kal_uint64 CphSysTimeInSlotGet(SysAirInterfaceT Airinterface);
+#endif
+
+extern kal_uint32 CphReadSyncTime(SysAirInterfaceT Airinterface);
+
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/do_fmpapi.h b/mcu/interface/l1/cl1/common/do_fmpapi.h
new file mode 100644
index 0000000..0deb0dc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/do_fmpapi.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*************************************************************
+*
+* This Software is the property of VIA Telecom, Inc. and may only be used pursuant to a license from VIA Telecom, Inc.
+*
+* Any unauthorized use inconsistent with the terms of such license is strictly prohibited.
+*
+* Copyright (c) 2006-2010 VIA Telecom, Inc. All rights reserved.
+*
+*************************************************************/
+/*****************************************************************************
+*
+* FILE NAME : do_fmpapi.h
+*
+* DESCRIPTION : API definition for FMP (Finger Management Processing) component.
+*
+* HISTORY :
+*****************************************************************************/
+#ifndef _DO_FMPAPI_H_
+#define _DO_FMPAPI_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "do_rmcapi.h"
+
+
+/*----------------------------------------------------------------------------
+ Global Defines and Macros
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Message IDs, for #define RMC_CMD_MAILBOX, EXE_MAILBOX_1_ID
+----------------------------------------------------------------------------*/
+/*
+The Message Ids are moved to do_rmcapi.h, to maintain one enumeration list for
+the RMC task.
+*/
+
+/*----------------------------------------------------------------------------
+ Message Formats structure
+----------------------------------------------------------------------------*/
+/* typedef PACKED struct */
+
+
+
+
+
+
+
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/hsc_module_trace.h b/mcu/interface/l1/cl1/common/hsc_module_trace.h
new file mode 100644
index 0000000..ec2d2c6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hsc_module_trace.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(MTK_DEV_93M_PREIT) && defined(MTK_PLT_ON_PC_IT)
+
+#ifndef _HSC_MODULE_TRACE_H_
+#define _HSC_MODULE_TRACE_H_
+
+/*****************************************************************************
+
+ FILE NAME: hsc_module_trace.h
+
+ DESCRIPTION:
+
+ This file contains the definition of hsc task trace in NWSIM for 93m temp use.
+
+*****************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#define MonPrintf(...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_CHSC, ##__VA_ARGS__)
+
+
+#define CL1TRACE_HSC_CMD MonPrintf
+
+/** HSC Related Trace definitions.*/
+static char *Hsc_Msg_String[]={
+
+"HscProcCmdMsg: MsgId 0x%x",
+"HscProcMpaMsg: MsgId 0x%x"
+
+};
+
+#define Hsc_Msg_String(index) Hsc_Msg_String[index]
+#endif
+
+#endif /* defined(MTK_DEV_93M_PREIT) && defined(MTK_PLT_ON_PC_IT) */
+
+
diff --git a/mcu/interface/l1/cl1/common/hsc_msg_struct.h b/mcu/interface/l1/cl1/common/hsc_msg_struct.h
new file mode 100644
index 0000000..389b400
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hsc_msg_struct.h
@@ -0,0 +1,391 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* FILE NAME :hsc_msg_struct.h
+*
+* DESCRIPTION :This module defines the Layer 1 ILM messgae struct for HSC
+*
+*
+* HISTORY :
+* 1.File Create by atlas.xu, 2016,2,5
+*
+*****************************************************************************/
+
+#ifndef _HSC_MSG_STRUCT_H
+#define _HSC_MSG_STRUCT_H
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "kal_public_defs.h"
+#include "hscapi.h"
+#include "hscapiex.h"
+#include "do_mpaapi.h"
+#include "cl1tskll1aapi.h"
+#include "cl1fhrtbaif.h"
+#include "hscdefs.h"
+#include "do_clcapi.h"
+#include "l1dapi.h"
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscClcOosaSleepCmdMsgT msg;
+} hsc_clc_oosa_sleep_cmd_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscClcOosaSleepCmdMsgT msg;
+} hsc_clc_oosa_cont_cmd_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscClcOosaSleepCmdMsgT msg;
+} l1d_oosa_cont_msg_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscInfiniteSleepReqMsgT msg;
+} hsc_infinite_sleep_req_msg_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aIdpSignalProtectStatusIndT msg;
+} hsc_clc_ll1a_idp_signal_protect_status_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscCssSuspendResumeCmdMsgT msg;
+} hsc_css_suspend_resume_cmd_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+} hsc_ssm_deque_signal_cmd_msg_struct;
+
+/* LL1A_PSW_SIGNAL_PROTECT_STATUS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aPswSignalProtectStatusIndT msg;
+} ll1a_psw_signal_protect_status_ind_struct;
+
+#if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1)
+/* HSC_SIB8_TIMING_SYNC_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscSib8TimingSyncReqMsgT msg;
+} hsc_sib8_timing_sync_req_struct;
+
+/* HSC_SIB8_TIMING_SYNC_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscSib8TimingSyncCnfMsgT msg;
+} hsc_sib8_timing_sync_cnf_struct;
+#endif
+/* MSG_ID_HSC_SLEEPOVER_INT_COMP_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscSleepOverCompMsgT msg;
+} hsc_sleepover_int_comp_msg_struct;
+
+/* MSG_ID_HSC_SET_SHDR_SVDO_OP_MODE_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscSetShdrSvdoOpModeT msg;
+} hsc_set_shdr_svdo_op_mode_msg_struct;
+
+#ifdef MTK_DEV_C2K_IRAT
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscClcSib8InfoCfgMsgT msg;
+} hsc_clc_sib8_info_cfg_msg_struct;
+#endif
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscC2kRecoverTimingCnfMsgT msg;
+} hsc_recover_timing_cnf_struct;
+
+
+/* HSC_CLc_CAL_START_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscClkCalStartMsgT msg;
+} hsc_clc_cal_start_msg_struct;
+
+
+/* MSG_ID_HSC_CLK_CAL_START_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscClkCalStartMsgT msg;
+} hsc_clk_cal_start_msg_struct;
+
+/* HSC_IDP_SLEEP_CMD_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscIdpSleepCmdMsgT msg;
+} hsc_idp_sleep_cmd_msg_struct;
+
+/* MPA_RF_ANTENNA_ASSIGN_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MpaRspMsgT msg;
+} hsc_mpa_rf_antenna_assign_msg_struct;
+
+/* L1D_MPA_RF_PREEMPT_REQ_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MpaReqMsgT msg;
+} l1d_mpa_rf_preempt_req_msg_struct;
+
+
+/* MPA_RF_ANTENNA_RELEASE_REQ_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MpaReqMsgT msg;
+} mpa_rf_antenna_release_req_msg_struct;
+
+/* MPA_RF_ANTENNA_REQUEST_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MpaReqMsgT msg;
+} mpa_rf_antenna_request_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MpaRspMsgT msg;
+} mpa_rf_release_ind_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MpaRspMsgT msg;
+} mpa_rf_antenna_request_cancel_msg_struct;
+
+/* LL1A_CLC_LTE_SCAN_C2K_ACTIVE_PARAMS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aClcLteScanC2kActiveParamsIndT msg;
+} ll1a_clc_lte_scan_c2k_active_params_ind_struct;
+
+/* LL1A_L1D_MODE_STATUS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aL1dModeStatusIndMsgT msg;
+} ll1a_l1d_mode_status_ind_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aEvStandbyMeasDoneIndMsgT msg;
+} ll1a_evstandby_meas_done_ind_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aEvStandbyMeasReqMsgT msg;
+} ll1a_evstandby_measure_req_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aIdpSignalProtectStatusIndT msg;
+} ll1a_idp_signal_protect_status_struct;
+
+/* MSG_ID_HSC_IDP_ENABLE_DO_SLOTTED_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscIdpSPageParmsMsgT msg;
+} hsc_idp_enable_do_slotted_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscRmcMiniAcqErrMsgT msg;
+} hsc_rmc_miniacq_result_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aRmcModeStatusIndMsgT msg;
+} ll1a_rmc_mode_status_ind_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aRmcRatStatusIndMsgT msg;
+} ll1a_rmc_rat_status_ind_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Ll1aRmcActiveMeasInfoIndMsgT msg;
+} ll1a_rmc_active_measure_info_ind_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ IdpHscResyncDeniedMsgT msg;
+} hsc_do_resync_denied_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ IdpHscWakeupIndMsgT msg;
+} hsc_wake_ind_msg_struct;
+
+
+#if defined (MTK_DEV_C2K_IRAT)
+/*MSG_ID_HSC_C2K_SIM_INDEX_INFO_MSG*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscC2kSimIndexInfoMsgT msg;
+}hsc_c2k_sim_index_info_msg_struct;
+
+/* MSG_ID_HSC_C2K_MMO_GAP_INFO_MSG*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscC2kMmoGapPatternIndMsgT msg;
+}hsc_c2k_mmo_gap_info_msg_struct;
+#endif
+
+/* HSC_IDP_WAKE_CMD_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscIdpWakeCmdMsgT msg;
+} hsc_idp_wake_cmd_msg_struct;
+
+
+#if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1)
+/* HSC_1X_PRIORITY_BOOST_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ Hsc1xPriorityBoostMsgT msg;
+}hsc_1x_priority_boost_msg_struct;
+#endif
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 rxDiversityCtrl;
+}hsc_rx_div_ctrl_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ L1dOosaReqMsgT msg;
+}l1d_oosa_req_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscFrcSyncInfoReptMsgT msg;
+} hsc_frc_sync_info_rept_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscDoPriorityBoostMsgT msg;
+} hsc_Do_priority_boost_msg_struct;
+
+typedef struct
+{
+ HscSysAirInterfaceT ResyncOwner;
+ HscSysAirInterfaceT UpdateOwner;
+ HscResyncT Resync;
+} HscSpResyncRecordMsgT;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscSpResyncRecordMsgT msg;
+} hsc_sp_resync_record_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 index;
+#if defined(__UE_SIMULATOR__)
+ kal_char string[256];
+ #else
+ kal_char string[128];
+#endif
+} c2k_sleep_ctrl_msg_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscTimeProfileMsgT msg;
+} hsc_time_profile_msg_struct;
+
+/* MSG_ID_HSC_CSS_PSEUDO_SET_RAT_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ HscCssPseudoSetRatIndT msg;
+} hsc_css_pseudo_set_rat_ind_struct;
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/hscapi.h b/mcu/interface/l1/cl1/common/hscapi.h
new file mode 100644
index 0000000..c6cda78
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hscapi.h
@@ -0,0 +1,533 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*************************************************************
+*
+* This Software is the property of VIA Telecom, Inc. and may only be used pursuant to a license from VIA Telecom, Inc.
+*
+* Any unauthorized use inconsistent with the terms of such license is strictly prohibited.
+*
+* Copyright (c) 2002-2010 VIA Telecom, Inc. All rights reserved.
+*
+*************************************************************/
+#ifndef _HSCAPI_H_
+#define _HSCAPI_H_
+/*****************************************************************************
+*
+* FILE NAME : hscapi.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Include Files
+----------------------------------------------------------------------------*/
+#include "sysapi.h"
+#include "pswapi.h"
+
+
+/*----------------------------------------------------------------------------
+* Message IDs for signals and commands sent to HSC
+*----------------------------------------------------------------------------*/
+#include "hscmsg.h"
+
+/*----------------------------------------------------------------------------
+* Definitions
+*----------------------------------------------------------------------------*/
+#define HSC_NUM_APPS (SYS_MODE_EVDO+1)
+/* The maximum mini-acq error, in tc8, where the 32K calibration will be applied.
+ If the mini-acq error is greater than or equal to this threshold,
+ the error will not be used for adjusting 32k clock calibration. */
+#define SP_MINI_ACQ_TC8_CAL_ADJUST_MAX (8*5) /* Threshold for mini-acq error for SCI=0 */
+
+
+#define HSC_FM_FREQUENCY 208000000 /*208MHz*/
+#define HSC_FM_DURATION 1 /*1s*/
+#define HSC_32K_CNTS_PER_SEC 32768 /*HWD_CLK_FREQ_32KHZ TBD*/
+
+#define CL1_IF_EVDO_RC_REQ_TXOFF_DELAY (7) /* 7ms, about 1.666*(3+1), for L3 use, 1 slot more than RC Tx off slot is for marge */
+#define CL1_IF_1XRTT_RC_REQ_TXOFF_DELAY (5) /* 5ms, about 1.250*(3+1), for L3 use, 1 slot more than RC Tx off slot is for marge */
+
+
+/* MPA Release reasons, to be shared with SYS */
+typedef enum
+{
+ HSC_SSM_MPA_REL_PREEMPT,
+ HSC_SSM_MPA_REL_SLEEP,
+ HSC_SSM_MPA_REL_RESET,
+ HSC_SSM_PREP_MAX
+} HscSsmMpaReasonT;
+
+/* 32k Clk Cal Settle Speeds */
+typedef enum
+{
+ SETTLE_NORMAL,
+ SETTLE_FAST,
+ SETTLE_MAX
+} HscClkCalSpeedT;
+
+typedef enum
+{
+ CONFID_HIGH,
+ CONFID_MED,
+ CONFID_MIN,
+ CONFID_MAX
+} HscClkCalThreshT;
+
+typedef enum
+{
+ SIM2_GSM_SUSPEND,
+ SIM2_GSM_RESUME,
+ SIM1_1xRTT_SUSPEND,
+ SIM1_1xRTT_RESUME,
+ SIM1_1xRTT_CANCEL,
+ SIM1_LTE_RESUME
+} HscCssSupendResumeT;
+
+typedef enum
+{
+ UNKNOWN_STATE = 0,
+ WAITING_STATE,
+ OFFERED_STATE,
+ INVALID_STATE
+} HscSib8TimingStateT;
+
+typedef enum
+{
+ HSC_CSS_RAT_FLIGHT,
+ HSC_CSS_RAT_STANDBY,
+ HSC_CSS_RAT_ACTIVE
+}HscCssRatTypeT;
+
+typedef enum
+{
+ FH,
+ PCG,
+ SLOT,
+ FH_INPCGSLOT,
+ FH_inPCGIRQ,
+ FH_inSLOTIRQ
+} TimeProfileModeT;
+
+typedef SysAirInterfaceT HscSysAirInterfaceT;
+
+/*----------------------------------------------------------------------------
+ Message Formats structure
+----------------------------------------------------------------------------*/
+/* MSG_ID_HSC_CLK_CAL_START_MSG, HSC_ETS_CLK_CAL_START_MSG */
+typedef struct
+{
+ HscSysAirInterfaceT Owner; /* SYS_MODE_1xRTT or SYS_MODE_EVDO */
+} HscClkCalStartMsgT;
+
+
+/* HSC_IDP_SLEEP_CMD_MSG */
+typedef struct
+{
+ FrameRecT PchWakeSystemTimeFrame;
+ kal_uint8 SyncCapsuleOffset;
+} HscIdpSleepCmdMsgT;
+
+
+/* MSG_ID_HSC_IDP_ENABLE_DO_SLOTTED_MSG */
+typedef struct
+{
+ kal_uint16 PageSlot; /* assigned slot to monitor */
+ kal_uint16 SlotCycleIndex; /* selected slot cycle index */
+} HscIdpSPageParmsMsgT;
+
+
+/* MSG_ID_HSC_RMC_ACTIVATE_RSP_MSG */
+typedef struct
+{
+ kal_int16 PilotPN;
+ kal_int16 RxTxOffsetTc2;
+ kal_int16 MiniAcqErrTc2;
+ kal_uint16 PwrEst;
+} HscRmcMiniAcqErrMsgT;
+
+#ifdef MTK_DEV_C2K_IRAT
+/* HSC_CLC_SIB8_INFO_CFG_MSG */
+typedef struct
+{
+ kal_bool is_update; /* 0 = Clear, 1 = Update*/
+ sys_time_info_c2k_struct sib8_sys_time_info;
+} HscClcSib8InfoCfgMsgT;
+
+/* HSC_SIB8_TIMING_SYNC_REQ */
+typedef struct
+{
+ SysAirInterfaceT Mode; /* 0 = 1xRTT, 1 = EvDO*/
+} HscSib8TimingSyncReqMsgT;
+
+/* HSC_SIB8_TIMING_SYNC_CNF */
+typedef struct
+{
+ SysAirInterfaceT Mode; /* 0 = 1xRTT, 1 = EvDO*/
+ kal_bool result; /* Indicate the time sync info in this message is valid or invalid. */
+} HscSib8TimingSyncCnfMsgT;
+#endif
+
+/* MSG_ID_HSC_CLC_OOSA_SLEEP_CMD_MSG */
+typedef struct
+{
+ kal_uint32 SleepDuration; /* Sleep duration in 1/10 seconds */
+} HscClcOosaSleepCmdMsgT;
+
+typedef struct
+{
+ HscSysAirInterfaceT Mode; /* 0 = 1xRTT, 1 = EvDO*/
+ kal_bool IsFlightMode; /* TRUE - Fligh mode; FALSE - other mode */
+} HscInfiniteSleepReqMsgT;
+
+
+/* MSG_ID_HSC_CSS_SUSPEND_RESUME_CMD_MSG */
+typedef struct
+{
+ HscCssSupendResumeT CssCmdType;
+ HscCssRatTypeT RatType;
+} HscCssSuspendResumeCmdMsgT;
+
+/* LL1A_CLC_LTE_SCAN_C2K_ACTIVE_PARAMS_IND */
+typedef struct
+{
+ kal_uint16 LTE_scan_active_duration_1xRTT; /* unit in milisecond, value range [1..10000], 0xFFFF means invalid (feature off) */
+ kal_uint16 LTE_scan_active_duration_DO; /* unit in milisecond, value range [1..1000], 0xFFFF means invalid (feature off) */
+} Ll1aClcLteScanC2kActiveParamsIndT;
+
+/* LL1A_IDP_SIGNAL_PROTECT_STATUS_IND */
+typedef struct
+{
+ kal_bool bSignalProtectStatus;/* KAL_TRUE,means signal interation is started and need be protected; */
+ /* KAL_FALSE,means signal interation is ended and protection can be canceled. */
+} Ll1aIdpSignalProtectStatusIndT;
+
+/* LL1A_PSW_SIGNAL_PROTECT_STATUS_IND */
+typedef struct
+{
+ kal_bool bSignalProtectStatus;/* KAL_TRUE,means signal interation is started and need be protected; */
+ /* KAL_FALSE,means signal interation is ended and protection can be canceled. */
+} Ll1aPswSignalProtectStatusIndT;
+
+/* HSC_ETS_CAL_SETTLE_TIME_SET_MSG */
+typedef struct
+{
+ kal_uint8 SettleTime[SETTLE_MAX][CONFID_MAX];
+ kal_uint16 FastSettlePeriodInSeconds;
+} HscClkCalParmsT;
+
+/* MSG_ID_HSC_ALTERNATE_AFC_MSG */
+typedef struct
+{
+ kal_uint8 Enable;
+} HscAlternateAfcMsgT;
+
+/* HSC_IDP_WAKE_CMD_MSG */
+typedef struct
+{
+ kal_uint8 Req;
+} HscIdpWakeCmdMsgT;
+
+typedef struct
+{
+ TimeProfileModeT Mode;
+ kal_uint8 startidx;
+ kal_uint8 endidx;
+} HscTimeProfileMsgT;
+
+typedef struct
+{
+ kal_uint8 Owner;
+} HscSleepOverCompMsgT;
+
+/* MSG_ID_HSC_SET_SHDR_SVDO_OP_MODE_MSG */
+typedef struct
+{
+ kal_uint8 ShdrEnabled;
+ kal_uint8 SvdoEnabled;
+} HscSetShdrSvdoOpModeT;
+
+#if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1)
+
+typedef struct
+{
+ kal_bool C2kInSim2;
+} HscC2kSimIndexInfoMsgT;
+
+typedef struct
+{
+ kal_uint32 MmoGapStartTime;
+ kal_int32 GapLength;
+} HscC2kMmoGapPatternIndMsgT;
+
+/* HSC_1X_PRIORITY_BOOST_MSG
+ * This message is sent by PSW, to modify 1X priority for preemption */
+typedef struct
+{
+ kal_bool control; /* True: raise priority, False: decrease priority */
+} Hsc1xPriorityBoostMsgT;
+
+typedef struct
+{
+ kal_bool control; /* True: raise priority, False: decrease priority */
+} HscDoPriorityBoostMsgT;
+
+#endif
+
+
+typedef struct
+{
+ SysAirInterfaceT Mode; /* 0 = 1xRTT, 1 = EvDO*/
+} HscFrcSyncInfoReptMsgT;
+
+/* MSG_ID_HSC_CSS_PSEUDO_SET_RAT_IND */
+typedef struct
+{
+ HscCssRatTypeT RatType;
+ kal_bool IsC2kOnSim2;
+} HscCssPseudoSetRatIndT;
+
+
+/*----------------------------------------------------------------------------
+* Hsc global
+*----------------------------------------------------------------------------*/
+extern kal_bool HscClkCalFastSettleEnabled;
+/*----------------------------------------------------------------------------
+* Hsc global APIs
+*----------------------------------------------------------------------------*/
+/*****************************************************************************
+
+ FUNCTION NAME: HscSsmFrameCntEst
+
+ DESCRIPTION: Estimates frame count during slotted paging
+
+ PARAMETERS:
+
+ RETURNED VALUES: FrameRecT
+
+*****************************************************************************/
+extern FrameRecT HscSsmFrameCntEst(HscSysAirInterfaceT Owner);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscSysDoPchBackoffTotalFrames
+
+ DESCRIPTION:
+
+ PARAMETERS:
+
+ RETURNED VALUES: Returns Total Backoff Time in DO Frames
+ (including RF backoff, Calibration, and MiniAcqErr Adjust)
+
+*****************************************************************************/
+extern kal_uint8 HscSysDoPchBackoffTotalFrames(HscSysAirInterfaceT Owner, kal_int32 backoff);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscClkCalSettleTimeGet
+
+ DESCRIPTION: Returns the 32KHz calibration settling time
+
+ PARAMETERS: SettleSpeed = SETTLE_NORMAL or SETTLE_FAST;
+ ThresholdZone = CONFID_HIGH, CONFID_MED, or CONFID_MIN;
+
+ RETURNED VALUES: 32KHz Calibration settling time
+
+*****************************************************************************/
+extern kal_uint8 HscClkCalSettleTimeGet(kal_uint8 SettleSpeed, kal_uint8 ThresholdZone);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscClkCalFastSettle
+
+ DESCRIPTION: Send HSC Transmitter State for 32k clock calibration
+
+ PARAMETERS: None
+
+ RETURNS: None
+
+*****************************************************************************/
+extern void HscClkCalFastSettle(kal_bool TxOn);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscSetAfcStatus
+
+ DESCRIPTION: Validates Afc for the given interface.
+
+ PARAMETERS: HscSysAirInterfaceT Interface
+ SysCdmaBandT Band
+ kal_bool Valid
+
+ RETURNS: None
+
+*****************************************************************************/
+extern void HscSetAfcStatus(SysAirInterfaceT Interface, SysCdmaBandT Band, kal_bool Valid);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscSsmSpecial1xPreemption
+
+ DESCRIPTION: Enables 1x PS to force high priorty for 1X antenna request
+
+ PARAMETERS: KAL_TRUE/KAL_FALSE
+
+ RETURNED VALUES: None
+
+*****************************************************************************/
+extern void HscSsmSpecial1xPreemption(kal_bool Control);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscSsmSpecialDoProtectPreemption
+
+ DESCRIPTION: Used to raise Do's priority and protect DO from being HSC preempt by 1xRTT
+
+ PARAMETERS: Control - Enable Do special protect from HSC preemption or not
+
+ RETURNED VALUES: None
+
+*****************************************************************************/
+extern void HscSsmSpecialDoProtectPreemption(kal_bool Control);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscSsmDoRxAgcSettleLong
+
+ DESCRIPTION:
+
+ PARAMETERS:
+
+ RETURNED VALUES: 1/KAL_TRUE : Long RxAgc Fast Settle Time
+ : 0/KAL_FALSE: Short RxAgc Fast Settle Time
+
+*****************************************************************************/
+extern kal_bool HscSsmDoRxAgcSettleLong(void);
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscShdrEnabled
+
+ DESCRIPTION:
+
+ PARAMETERS:
+
+ RETURNED VALUES: 1/KAL_TRUE : SHDR is enabled
+ : 0/KAL_FALSE: SHDR is not enabled
+
+*****************************************************************************/
+extern kal_bool HscShdrEnabled(void);
+
+
+/*****************************************************************************
+
+ FUNCTION NAME: HscCurrentWakeupInShdr
+
+ DESCRIPTION: Returns the current (dynamic) state
+
+ PARAMETERS: None
+
+ RETURNED VALUES: 1/KAL_TRUE : SHDR is enabled
+ : 0/KAL_FALSE: SHDR is not enabled
+
+*****************************************************************************/
+extern kal_uint8 HscL1dSPageWakeStatus(void);
+extern void HscSpDisable(HscSysAirInterfaceT Owner);
+extern kal_uint16 HscSpHistory(HscSysAirInterfaceT Owner);
+extern kal_uint16 HscL1dSPageGetNumOfFrames4Wakeup(void);
+extern kal_bool HscSsmDoInSuspendQueue(void);
+#ifdef MTK_CBP
+extern void HscSsmRmcAntennaRelease(kal_uint8 RfPaths, kal_bool releaseFlag);
+extern void HscSsmResyncCancel(HscSysAirInterfaceT Owner);
+extern kal_bool HscSsmInWakeQueue(HscSysAirInterfaceT Owner);
+extern void HscSsmReset(HscSysAirInterfaceT Owner);
+extern kal_uint8 HscSpEnabled(HscSysAirInterfaceT Owner);
+#endif
+
+#if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1)
+extern kal_bool HscSsmIs1xAvailableforAutoGap( void );
+extern kal_bool HscSsmCloseToResync(void);
+extern kal_bool HscSsmResyncTimeQuery(HscSysAirInterfaceT Owner, kal_uint32 *Frc);
+extern kal_bool HscSsmResyncShdrGet(HscSysAirInterfaceT Owner);
+extern void HscSsmEvstandbyTimeCopyProhibit(kal_bool Prohibit);
+extern void HscOosaStateUpdateEvStandby();
+extern void HscOosaStateUpdate();
+extern void HscOosaSendWakeInd();
+extern void HscLl1aGapOfferReq(kal_bool Enable);
+extern kal_bool HscSsmDoPchPrioBoostTrigQuery(void);
+#endif
+
+
+extern void HscSsmResumeWakeCmdMsg(void);
+extern kal_bool MpaCheckSecondPathSupport(void);
+
+#ifdef SYS_OPTION_TX_TAS_ENABLE
+/* used for TAS only */
+extern kal_bool HscSsmCheckDoPreemptForTas(void);
+extern kal_bool HscSsmCheckShdrModeForTas(void);
+#endif
+
+/*****************************************************************************
+ * removed!
+*****************************************************************************/
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
+/**Log information: \main\Trophy\Trophy_ylxiao_href22033\1 2013-03-18 14:15:26 GMT ylxiao
+** HREF#22033, merge 4.6.0**/
+/**Log information: \main\Trophy\1 2013-03-19 05:19:47 GMT hzhang
+** HREF#22033 to merge 0.4.6 code from SD.**/
+/**Log information: \main\Trophy\Trophy_jluo_href22084\1 2013-04-03 04:13:29 GMT jluo
+** HREF#22084:HANDROID#1723**/
+/**Log information: \main\Trophy\2 2013-04-03 06:37:55 GMT czhang
+** HREF#22084**/
+/**Log information: \main\Trophy\Trophy_yanliu_handroid2028\1 2013-08-30 07:03:10 GMT yanliu
+** HANDROID#2028: check in SD's MT slotted optimization**/
+/**Log information: \main\Trophy\3 2013-08-30 07:05:25 GMT yanliu
+** HANDROID#2028 merged: check in SD's MT slotted optimization**/
+/**Log information: \main\Trophy\Trophy_xding_href22331\1 2013-12-10 07:17:45 GMT xding
+** HREF#22331, ºÏ²¢MMCÏà¹Ø¹¦Äܵ½Trophy baselineÉÏ**/
+/**Log information: \main\Trophy\4 2013-12-10 08:33:12 GMT jzwang
+** href#22331:Merge MMC latest implementation from Qilian branch.**/
+
diff --git a/mcu/interface/l1/cl1/common/hscapiex.h b/mcu/interface/l1/cl1/common/hscapiex.h
new file mode 100644
index 0000000..af8fcc8
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hscapiex.h
@@ -0,0 +1,218 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _HSCAPIEX_H_
+#define _HSCAPIEX_H_
+/*****************************************************************************
+*
+* FILE NAME : hscapi.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Include Files
+----------------------------------------------------------------------------*/
+#include "sysapi.h"
+#include "systyp.h"
+#include "cl1fhrtbadefs.h"
+#include "hsctypdefs.h"
+
+#include "hscapi.h"
+
+
+/*----------------------------------------------------------------------------
+ typedef
+----------------------------------------------------------------------------*/
+#ifndef MTK_PLT_ON_PC
+//#define MTK_DEV_93M_SIB8_TIMING_BYPASS_ENABLE
+#endif
+#define HSC_SIB8_TIMING_VALID_TIMER (6000) /* valid Timer, 6000ms */
+#define HSC_SIB8_TIMING_INVALID_TIMER (6000) /* valid Timer, 6000ms */
+
+#define SP_BACKOFF_ACTIVATE_DSP_US (266) /* 266us, TBD */
+#define SP_BACKOFF_ACTIVATE_DSP_9M (SYS_CONVERT_FRC_TO_9M(SP_BACKOFF_ACTIVATE_DSP_US, 0))
+
+
+/*----------------------------------------------------------------------------
+ MPA event structure
+----------------------------------------------------------------------------*/
+
+/* for 6293 */
+/* HSC_MPA_REQ event structure */
+typedef struct
+{
+ /* 1xRTT or EvDO */
+ SysAirInterfaceT Owner;
+
+ /* RF to request.
+ Bitmap definition, refer to
+ MPA_MDM_PATH_MAIN
+ MPA_MDM_PATH_DIV
+ MPA_MDM_PATH_TX */
+ MpaAntTypeBmpT Req;
+} HscMpaReqEventT;
+
+/* HSC_MPA_RELEASE event sturcture */
+typedef struct
+{
+ /* The reason to release RF.
+ Bitmpa definition, refer to
+ HSC_SSM_MPA_REL_PREEMPT - release RF for being preempted
+ HSC_SSM_MPA_REL_SLEEP - release RF for going to sleep
+ HSC_SSM_MPA_REL_RESET - release RF for reseted */
+ HscSsmMpaReasonT Reason;
+
+ /* 1xRTT or EvDO */
+ SysAirInterfaceT Owner;
+
+
+ /* RF to be released.
+ Bitmap definition, refer to
+ MPA_MDM_PATH_MAIN
+ MPA_MDM_PATH_DIV
+ MPA_MDM_PATH_TX */
+ MpaAntTypeBmpT Req;
+
+}HscMpaReleaseEventT;
+
+
+/* HSC_RF_ASSIGN_IND event sturcture */
+typedef struct
+{
+
+ /* 0 - MPA_RF_DENIED, 1- MPA_RF_GRANT, 2 - MPA_RF_PENDING */
+ MpaRfAssignStatusT RfGrant;
+
+ /* requested RF by CL1.
+ Bitmap definition, refer to
+ MPA_MDM_PATH_MAIN
+ MPA_MDM_PATH_DIV
+ MPA_MDM_PATH_TX */
+ MpaAntTypeBmpT Req;
+
+ /* assigned RF path by MPA.
+ RF path definition, refer to
+ MPA_RF_PATH_RX_1
+ MPA_RF_PATH_RX_2
+ MPA_RF_PATH_RX_3
+ MPA_RF_PATH_TX_1
+ MPA_RF_PATH_TX_2 */
+ MpaRfPathBmpT RfAntenna;
+
+}HscRfAssignIndEventT;
+
+
+/* HSC_RXACTIVATE_IND event sturcture */
+typedef struct
+{
+ /* assigned RF path by MPA.
+ RF path definition, refer to
+ MPA_RF_PATH_RX_1
+ MPA_RF_PATH_RX_2
+ MPA_RF_PATH_RX_3
+ MPA_RF_PATH_TX_1
+ MPA_RF_PATH_TX_2 */
+ MpaRfPathBmpT RfAntenna;
+
+ /** Rtba channel Sys RcStart time and Rc end time, 80ms SuperFrame and 1/8 chipoffset */
+ RtbaRcTimingTypeT SysRcStartTime;
+ SysSFrameTimeT SysEndTime; /* CL1 doesn't need use the fake flage for end time*/
+}HscRxActivateIndEventT;
+
+
+/* EVT_ID_RMC_MPA_FULL_PREEMPT_IND and EVT_ID_RMC_MPA_DIV_PREEMPT_IND event sturcture */
+typedef struct
+{ /* {0xFFFFFFFFFFFFFFFFUL, 0xFFFFFFFFUL} is invalid time, RMC should bypass it. */
+ SysSFrameTimeT DoLastRFStopTime;
+}HscPreemptEventT;
+
+
+/* HSC SLEEPOVER COMP EVNET event structure */
+typedef struct
+{
+ SysAirInterfaceT Owner; /* 1xRTT or EVDO */
+} HscSleepOverCompEventT;
+
+
+/*----------------------------------------------------------------------------
+* Clock Calibration Definitions
+*----------------------------------------------------------------------------*/
+typedef struct
+{
+ kal_uint32 ScCnt;
+ kal_uint32 FcFreq;
+ kal_uint32 FcCnt;
+} HscFmResultT;
+
+/*----------------------------------------------------------------------------
+* HSC SIB8 Timing Sync
+*----------------------------------------------------------------------------*/
+typedef struct
+{
+ HscSib8TimingStateT State; /* sib8 timing state, UNKNOWN, WAITING, OFFERED , INVALID */
+ HscClcSib8InfoCfgMsgT Sib8InfoCfgMsg; /* store Sib8 timing configuration */
+ kal_bool IsTimingSyncReqProcessing[HSC_NUM_APPS]; /* Set pending flag for 1x or do when 1x PS or EVDO L1 request sib8 timing, clear this flag respectively when 1x or do timing recover finished */
+ kal_bool IsSib8InfoCfgMsgPending; /* sib8 timing configuration msg comes, set this pending flag when HSC is processing timing sync req from 1x PS or DO L1*/
+ ll1_cl1_sib8_timing_sync_cnf_struct Sib8TimingSyncResultFromLL1; /* store the sib8 timing result from MD1 */
+} HscSib8TimingT;
+
+typedef struct
+{
+ kal_uint64 CurrC2kSystemTime; /* Uint: CDMA chip, based on 1.2288MHz*/
+ kal_uint32 CurrFrc; /* current Frc , unit: 1us */
+} HscC2kRecoverTimingReqEvtT;
+
+typedef struct
+{
+ SysAirInterfaceT mode; /* 1x or do*/
+ kal_bool result;
+} HscC2kRecoverTimingCnfMsgT;
+
+/*----------------------------------------------------------------------------
+* Functions
+*----------------------------------------------------------------------------*/
+extern void HscRecoverTimingBySib8Timing(SysAirInterfaceT mode, HscC2kRecoverTimingReqEvtT *pCurrTime);
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/hscdefs.h b/mcu/interface/l1/cl1/common/hscdefs.h
new file mode 100644
index 0000000..fad2ec0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hscdefs.h
@@ -0,0 +1,505 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSKTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _HSCDEFS_H_
+#define _HSCDEFS_H_
+/*****************************************************************************
+*
+* FILE NAME : hscdefs.h
+*
+* DESCRIPTION : This file contains general constants and definitions used by
+* the L1D unit
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "do_mpaapi.h"
+#include "hscapi.h"
+#include "hscapiex.h"
+#include "systyp.h"
+
+/*----------------------------------------------------------------------------
+ Hardware Macros
+----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------
+ MPA definitions
+----------------------------------------------------------------------------*/
+typedef struct
+{
+ MpaAntennaInfoT MpaRfAntenna[MPA_RF_NUM_PATHS]; /*HWD_RF_MPA_MAX_PATH_NUM */
+ kal_uint8 AllStatus;
+ kal_uint8 Status[MPA_RF_NUM_APPS];
+ kal_uint8 RfPriv[MPA_RF_NUM_APPS];
+} HscMpaT;
+
+typedef enum
+{
+ HSC_OP_MODE_LEGACY_HYBRID_BN = 0,
+ HSC_OP_MODE_SHDR_WITH_DIV_BN,
+ HSC_OP_MODE_SHDR_2_MAINS_BN,
+ HSC_OP_MODE_SVDO_2_RX_BN,
+ HSC_OP_MODE_SVDO_3_RX_BN
+}HscMpaOpModeT;
+
+#define HSC_OP_MODE_LEGACY_HYBRID (1<<HSC_OP_MODE_LEGACY_HYBRID_BN)
+#define HSC_OP_MODE_SHDR_WITH_DIV (1<<HSC_OP_MODE_SHDR_WITH_DIV_BN)
+#define HSC_OP_MODE_SHDR_2_MAINS (1<<HSC_OP_MODE_SHDR_2_MAINS_BN)
+#define HSC_OP_MODE_SVDO_2_RX (1<<HSC_OP_MODE_SVDO_2_RX_BN)
+#define HSC_OP_MODE_SVDO_3_RX (1<<HSC_OP_MODE_SVDO_3_RX_BN)
+#define HSC_OP_MODE_SHDR (HSC_OP_MODE_SHDR_WITH_DIV | HSC_OP_MODE_SHDR_2_MAINS)
+#define HSC_OP_MODE_SVDO (HSC_OP_MODE_SVDO_2_RX | HSC_OP_MODE_SVDO_3_RX)
+#define HSC_OP_MODE_SHDR_OR_SVDO (HSC_OP_MODE_SHDR | HSC_OP_MODE_SVDO)
+
+extern kal_uint8 hscMpaOpMode;
+extern kal_uint8 hscMpaOpModeHwdConfig;
+
+/*----------------------------------------------------------------------------
+ Clk Calibration definitions
+----------------------------------------------------------------------------*/
+#define SP_CNT_32K_UPPER_8_MASK 0x00FF /* Upper mask 8bits:[23-16] of 32kHz counter [23:0] */
+#define SP_CNT_9MHZ_UPPER_4_MASK 0x000F /* Upper mask 4bits:[19-16] of 9MHz counter [19:0] */
+#define SP_CNT_9MHZ_UPPER_2_MASK 0x0003 /* bits [17-16] of 9MHz counter [19:0] */
+#define HSC_CLK_CAL_DO_PILOT_HIGH_CONFID 16462 /* -6dB in Q16 */
+#define HSC_CLK_CAL_DO_PILOT_MED_CONFID 8231 /* -9dB in Q16 */
+#define HSC_CLK_CAL_DO_PILOT_MIN_CONFID 4135 /* -12dB in Q16 */
+#define HSC_CLK_CAL_SETTLE_TIME_16X 16 /* settle time in units of slot cycle length */
+#define HSC_CLK_CAL_SETTLE_TIME_8X 8 /* settle time in units of slot cycle length */
+#define HSC_CLK_CAL_SETTLE_TIME_4X 4 /* settle time in units of slot cycle length */
+#define HSC_CLK_CAL_SETTLE_TIME_2X 2 /* settle time in units of slot cycle length */
+#define HSC_CLK_CAL_SETTLE_TIME_1X 1 /* settle time in units of slot cycle length */
+#define HSC_CLK_CAL_FAST_SETTLE_PERIOD 120 /* fast settle period in units of seconds */
+#define HSC_MINI_ACQ_ERR_TC8_THRESH (45*8) /* Threshold set at 45 chips */
+
+
+
+/*------------------------------------------------------------------------------
+ Spage Backoff Time Definitions (CBP7.0 Slotted Operation Section 2.4, Jing Su)
+-------------------------------------------------------------------------------*/
+#define HSC_SP_SLOTTED_WAKE_SCHE_SLOT_CNT 1
+#define HSC_SP_RX_AGC_SETTLE_SHORT_SLOT_CNT 2
+#define HSC_SP_RX_AGC_SETTLE_LONG_SLOT_CNT 4
+#define HSC_SP_MINI_ACQ_DATA_CAP_SLOT_CNT 3
+#define HSC_SP_MINI_ACQ_POST_PROC_SLOT_CNT 2
+#define HSC_SP_FING_ALLOC_SLOT_CNT 7
+
+/*----------------------------------------------------------------------------
+ DO TxFreeze Backoff Time Definitions
+----------------------------------------------------------------------------*/
+#define HSC_STOPDO_GUARD_FRMS 10 /* 10 guard frames whether in 1X or DO */
+
+/*----------------------------------------------------------------------------
+ HscSsm Definitions
+----------------------------------------------------------------------------*/
+#define HSC_32K_STEP_FRAC_SHIFT (18)
+
+#define HSC_9M_CNTS_PER_2048_80MS 0x60000000UL /* 9MHz count in max duration of Slotted cycle (9.8304MHz * 2048 * 80 ms) */
+#define HSC_26MS_FRM_CNTS_PER_2048_80MS 0x1800 /* 26ms Frame cnt in max duration of Slotted cycle (2048 * 3) */
+#define HSC_26MS_FRM_CNTS_MOD_MAX_SLOTPERIOD HSC_26MS_FRM_CNTS_PER_2048_80MS
+#define HSC_26MS_FRM_CNTS_MOD_MAX_32BITS 0xFFFFF000UL /* 0xFFFFF000 = 0x100000000/0x1800 */
+
+#define HSC_SSM_RESYNC_CAL_BACKOFF_SP_CLK_CNT (FRC_FREQ * 80 / 1000) /* Clk Cal Collision buffer 80ms */
+#define HSC_SSM_RESYNC_COLLISION_US (FRC_FREQ * 150 / 1000) /* Resync Collision buffer 150ms */
+#define HSC_SSM_DUAL_RESYNC_COLLISION_US (FRC_FREQ * 40 / 1000) /* Resync Collision buffer 40ms */
+#define HSC_SSM_RESYNC_SHDR_HYBRID_TIMER (150000) /* 150ms ahead, Resync decision to wake up in SHDR or hybrid */
+#define HSC_SSM_RESYNC_1X_SCAN_BACKOFF_US (2*FRC_FREQ) /* Resync Collision buffer 2s */
+#define HSC_SSM_RESYNC_DO_SCAN_BACKOFF_US (0*FRC_FREQ) /* Resync Collision buffer 0s */
+#define HSC_SSM_REF_TIME_SV_PERIOD (40) /* DO ref time supervision period: 40s */
+#define HSC_DO_SLT_BLOCK_LENGTH (106667) /* 64 slots */
+#define HSC_DO_WAKE_BLOCK_LENGTH (53333) /* 32 slots */
+
+#define HSC_SSM_STATUS_DO_BN 0
+#define HSC_SSM_STATUS_RESYNC_CMPLT_BN 1 /* completed hw Resync */
+#define HSC_SSM_STATUS_RESYNC_DENIED_BN 2 /* Slotted wakeup was denied */
+#define HSC_SSM_STATUS_SUSPENDED_BN 3 /* preempted and suspended */
+#define HSC_SSM_STATUS_WAKE_PENDING_BN 4 /* Wake Cmd was received */
+#define HSC_SSM_STATUS_WAKE_SCHEDULED_BN 5 /* Resync has been scheduled for the wake command */
+#define HSC_SSM_STATUS_MPA_NORM_REQ_PENDING_BN 6 /* waiting for RF Norm Req results */
+#define HSC_SSM_STATUS_MPA_NORM_REQ_IMMED_BN 7 /* Immediate RF request (1^MpaReqMsg.QueueRequest) */
+#define HSC_SSM_STATUS_TX_AVAILABLE_BN 10 /* Tx available Ind */
+#define HSC_SSM_STATUS_MPA_MEAS_REQ_BN 11 /* Antenna request is for Meas */
+#define HSC_SSM_STATUS_WAKE_PROCESSED_BN 12 /* Wake cmd is processed */
+#define HSC_SSM_STATUS_SLOTTED_BN 13 /* Slotted mode */
+
+#define HSC_SSM_STATUS_DO (1<<HSC_SSM_STATUS_DO_BN) /*0x0001*/
+#define HSC_SSM_STATUS_RESYNC_CMPLT (1<<HSC_SSM_STATUS_RESYNC_CMPLT_BN) /*0x0002*/
+#define HSC_SSM_STATUS_RESYNC_DENIED (1<<HSC_SSM_STATUS_RESYNC_DENIED_BN) /*0x0004*/
+#define HSC_SSM_STATUS_SUSPENDED (1<<HSC_SSM_STATUS_SUSPENDED_BN) /*0x0008*/
+#define HSC_SSM_STATUS_WAKE_PENDING (1<<HSC_SSM_STATUS_WAKE_PENDING_BN) /*0x0010*/
+#define HSC_SSM_STATUS_WAKE_SCHEDULED (1<<HSC_SSM_STATUS_WAKE_SCHEDULED_BN) /*0x0020*/
+#define HSC_SSM_STATUS_MPA_NORM_REQ_PENDING (1<<HSC_SSM_STATUS_MPA_NORM_REQ_PENDING_BN) /*0x0040*/
+#define HSC_SSM_STATUS_MPA_NORM_REQ_IMMED (1<<HSC_SSM_STATUS_MPA_NORM_REQ_IMMED_BN) /*0x0080*/
+#define HSC_SSM_STATUS_TX_AVAIL_IND_PEND (1<<HSC_SSM_STATUS_TX_AVAILABLE_BN) /*0x0400*/
+#define HSC_SSM_STATUS_MPA_MEAS_REQ (1<<HSC_SSM_STATUS_MPA_MEAS_REQ_BN) /*0x0800*/
+#define HSC_SSM_STATUS_WAKE_PROCESSED (1<<HSC_SSM_STATUS_WAKE_PROCESSED_BN) /*0x1000*/
+#define HSC_SSM_STATUS_SLOTTED (1<<HSC_SSM_STATUS_SLOTTED_BN)
+
+#define HSC_SSM_STATUS_RESYNC_RESET ( HSC_SSM_STATUS_RESYNC_CMPLT | \
+ HSC_SSM_STATUS_RESYNC_DENIED | \
+ HSC_SSM_STATUS_SUSPENDED )
+
+typedef enum
+{
+ HSC_SSM_ACTIVE_1xRTT,
+ HSC_SSM_ACTIVE_EVDO,
+ HSC_SSM_RESYNC,
+ HSC_SSM_WAIT_1,
+ HSC_SSM_WAIT_2,
+ HSC_SSM_SUSPENDED,
+ HSC_SSM_NUM_WAKE
+} WakeTypeT;
+
+typedef enum
+{
+ HSC_FM_NONE,
+ HSC_FM_ONGOING,
+ HSC_FM_DONE
+} HscFmStatusT;
+
+typedef struct
+{
+ HscFmStatusT FmStatus;
+ HscFmResultT FmResult;
+ kal_int32 MiniAcqCorrectionTc8;
+ kal_int32 OnlineAdj;
+ kal_int32 CalValue;
+ kal_uint16 MiniAcqPwrEst;
+ kal_int32 MiniAcqCalValue;
+ kal_uint8 CalScale[HSC_NUM_APPS]; /* CalScale = ResyncDenyCnt+1 */
+ kal_uint8 ResyncDenyCnt[HSC_NUM_APPS];
+ kal_uint32 SleepTimes;
+} HscClkCalT; /* This is the clk cal structure for DO, see SPageCal in l1d for 1X */
+
+
+typedef struct
+{
+ kal_uint32 RxPllSettle; /* Slotted Paging RF Rx Pll settle in symbols.*/
+ kal_uint32 RxAgcSettle; /* This is updated in frame handler */
+ kal_uint32 RxAgcSettleShort; /* Short Slotted Paging RxAgc settle in symbols.*/
+ kal_uint32 RxAgcSettleLong; /* Long Slotted Paging RxAgc settle in symbols.*/
+ kal_uint32 MiniAcq; /* Buffer Capture, search, and finger allocation delay in ms */
+ kal_uint32 MiscAdj; /* Time between Resync Lisr to Resync Hisr */
+} HscSpBackoffT;
+
+typedef struct
+{
+ FrameRecT WakeFrame;
+ kal_uint32 FRC_Resync;
+} HscDoStopTxT;
+
+typedef struct
+{ /* WARNING! THis structure is reset to 0 before every Resync Time calc */
+ kal_bool Valid;
+ FrameRecT PchWakeSystemTimeFrame;
+ kal_uint32 Total9MHzDuration;
+ kal_int32 TotalCalValue;
+ kal_int32 Backoff9MHz;
+ SysSFrameTimeT Sframe_PrevResync;
+ SysSFrameTimeT Sframe_Resync;
+ kal_uint32 FRC_Resync;
+ kal_uint32 FRC_Rtb; /* in FRC, for resync polling in frame tick */
+} HscResyncT;
+
+
+typedef struct
+{
+ HscSysAirInterfaceT Owner;
+ kal_uint16 Status;
+ kal_uint8 RfReq;
+ HscResyncT Resync;
+ kal_bool (*InTraffic)(void);
+ kal_uint8 ActiveQnum;
+ kal_bool WakeSchedulePend;
+ kal_uint8 WakeScheLen; /* In frame */
+ kal_bool ModemWakePend;
+ kal_bool HscShdrWakeup;
+ kal_bool TimeCopyProhibit;
+} HscAppT;
+
+typedef struct
+{
+ HscAppT *Ptr;
+ void (*DeQueueP) (kal_uint8);
+} HscQueueT;
+
+typedef struct
+{
+ kal_bool Special1xPreemption;
+ kal_uint8 Priority;
+ HscSysAirInterfaceT ResyncOwner;
+ HscQueueT WakeQueue[HSC_SSM_NUM_WAKE];
+ HscAppT App[HSC_NUM_APPS];
+ HscSpBackoffT Backoff;
+ kal_uint32 ScanBackoff[HSC_NUM_APPS];
+ HscDoStopTxT DoStopTx;
+ kal_uint32 ResyncCollisionBuffer; /* In FRC unit */
+ kal_bool ShdrModeCheckingFlag;
+ kal_uint32 ShdrModeCheckingTime;
+} HscSsmStatusT;
+
+/* Deep Sleep Request in HSC */
+typedef struct
+{
+ kal_uint32 VetoFlag[HSC_NUM_APPS];
+} HscSsmDeepSleepT;
+
+
+/* Deep Sleep Request in HSC */
+typedef struct
+{
+ FrameRecT PchWakeSystemTimeFrame; /* in frame */
+ kal_uint32 Backoff9MHz; /* in echip */
+ kal_uint32 AgcSettle; /* in echip */
+ SysSFrameTimeT SframeResync; /* in supframe+echip */
+ kal_uint32 FrcResync; /* in FRC */
+ kal_uint32 FrcRtb; /* in FRC, for resync polling in frame tick */
+} HscSsmDoSleepCmdT;
+
+typedef struct
+{
+ FrameRecT PchWakeSystemTimeFrame; /* in frame */
+ kal_uint32 Backoff9MHz; /* in echip */
+ SysSFrameTimeT SframeResync; /* in supframe+echip */
+ kal_uint32 FrcResync; /* in FRC */
+ kal_uint32 FrcRtb; /* in FRC, for resync polling in frame tick */
+} HscSsm1xSleepCmdT;
+
+
+/*----------------------------------------------------------------------------
+ SPage definitions
+----------------------------------------------------------------------------*/
+#define SP_STATUS_SP_ENABLED_BN 0
+#define SP_STATUS_CAL_DONE_BN 1
+#define SP_STATUS_SRCH_DONE_BN 2
+#define SP_STATUS_SLEEP_CMD_RECVD_BN 3
+#define SP_STATUS_SLEEP_CMD_PEND_BN 4
+#define SP_STATUS_STOP_ACK_RECVD_BN 5
+#define SP_STATUS_RESYNC_CMPLT_BN 6 /* send RESYNC_IND, WAKE_IND, or THAW_IND if not set */
+#define SP_STATUS_MINI_ACQ_CMPLT_BN 7 /* rf is current, a RxActivate request was sent */
+#define SP_STATUS_MINI_ACQ_REQ_BN 8 /* Mini Acq is required upon resuming from preemption */
+#define SP_STATUS_SP_DISABLE_PEND_BN 9 /* Pending Slotted Disable */
+#define SP_STATUS_SUSPENDED_BN 10
+#define SP_STATUS_SLEEP_CMD_DISCARD_BN 11
+#define SP_STATUS_RESYNC_DENIED_BN 12
+
+#define SP_STATUS_SP_ENABLED (1<<SP_STATUS_SP_ENABLED_BN) /*0x0001*/
+#define SP_STATUS_CAL_DONE (1<<SP_STATUS_CAL_DONE_BN) /*0x0002*/
+#define SP_STATUS_SRCH_DONE (1<<SP_STATUS_SRCH_DONE_BN) /*0x0004*/
+#define SP_STATUS_SLEEP_CMD_RECVD (1<<SP_STATUS_SLEEP_CMD_RECVD_BN) /*0x0008*/
+#define SP_STATUS_SLEEP_CMD_PEND (1<<SP_STATUS_SLEEP_CMD_PEND_BN) /*0x0010*/
+#define SP_STATUS_STOP_ACK_RECVD (1<<SP_STATUS_STOP_ACK_RECVD_BN) /*0x0020*/
+#define SP_STATUS_RESYNC_CMPLT (1<<SP_STATUS_RESYNC_CMPLT_BN) /*0x0040*/
+#define SP_STATUS_MINI_ACQ_CMPLT (1<<SP_STATUS_MINI_ACQ_CMPLT_BN) /*0x0080*/
+#define SP_STATUS_MINI_ACQ_REQ (1<<SP_STATUS_MINI_ACQ_REQ_BN) /*0x0100*/
+#define SP_STATUS_SP_DISABLE_PEND (1<<SP_STATUS_SP_DISABLE_PEND_BN) /*0x0200*/
+#define SP_STATUS_SUSPENDED (1<<SP_STATUS_SUSPENDED_BN) /*0x0400*/
+#define SP_STATUS_SLEEP_CMD_DISCARD (1<<SP_STATUS_SLEEP_CMD_DISCARD_BN) /*0x0800*/
+#define SP_STATUS_RESYNC_DENIED (1<<SP_STATUS_RESYNC_DENIED_BN) /*0x1000*/
+
+#define SP_ENABLING_TRIGGERS (SP_STATUS_SP_ENABLED | SP_STATUS_CAL_DONE) /*0x0003*/
+
+#define SP_EVENT_TRIGGERS (SP_STATUS_SRCH_DONE | \
+ SP_STATUS_SLEEP_CMD_RECVD | \
+ SP_STATUS_SLEEP_CMD_PEND | \
+ SP_STATUS_STOP_ACK_RECVD | \
+ SP_STATUS_RESYNC_CMPLT )
+#define SP_SLEEP_RESET (SP_STATUS_SRCH_DONE | \
+ SP_STATUS_SLEEP_CMD_RECVD | \
+ SP_STATUS_SLEEP_CMD_PEND | \
+ SP_STATUS_STOP_ACK_RECVD | \
+ SP_STATUS_MINI_ACQ_CMPLT | \
+ SP_STATUS_MINI_ACQ_REQ | \
+ SP_STATUS_RESYNC_CMPLT )
+#define SP_SUSPEND_RESET (SP_STATUS_SRCH_DONE | \
+ SP_STATUS_SLEEP_CMD_RECVD | \
+ SP_STATUS_SLEEP_CMD_PEND | \
+ SP_STATUS_STOP_ACK_RECVD | \
+ SP_STATUS_MINI_ACQ_CMPLT )
+#define SP_ACTIVATE_RESET (SP_STATUS_SRCH_DONE | \
+ SP_STATUS_SLEEP_CMD_RECVD | \
+ SP_STATUS_STOP_ACK_RECVD | \
+ SP_STATUS_MINI_ACQ_REQ )
+
+
+typedef struct
+{
+ kal_uint8 Enabled;
+ kal_uint8 State;
+ kal_uint32 History;
+ kal_uint8 SlotCycleIdx[2];
+ kal_uint8 CalSettleTime;
+ kal_uint8 ImmediateMode;
+} HscSpStatusT;
+
+typedef struct
+{
+ kal_uint16 History;
+ kal_uint8 ImmediateMode;
+} L1dSPageStatusT;
+
+typedef enum
+{
+ SP_STATE_NONSLOTTED = 0, /* slotted page mode is disabled */
+ SP_STATE_PCH_MONITOR,
+ SP_STATE_WAIT_FOR_STOP_ACK,
+ SP_STATE_SPAGE_SLEEP,
+ SP_STATE_MAX
+} SpStateT;
+
+typedef struct
+{
+ kal_uint8 RepeatOk;
+ void (*FuncP)(void);
+ kal_uint16 Triggers;
+ kal_uint8 Next;
+} SpDoStateTblEntryT;
+
+typedef struct
+{
+ SpDoStateTblEntryT State[SP_STATE_MAX];
+} HscSpDoStateTblT;
+
+
+typedef struct
+{
+ HscSysAirInterfaceT ResyncOwner;
+ HscResyncT Resync[HSC_NUM_APPS];
+} HscSpResyncRecordT;
+
+
+/*----------------------------------------------------------------------------
+ HSC OOSA definitions
+----------------------------------------------------------------------------*/
+typedef enum
+{
+ OOSA_STATE_INIT = 0, /* slotted page mode is disabled */
+ OOSA_STATE_IN_SLEEP,
+ OOSA_STATE_ENTERING_SLEEP,
+ OOSA_STATE_WAKE_BEFORE_SLEEP /* OOSA wake cmd assert before OOSA sleep flow finished */
+} OosaStateT;
+
+#define HSC_OOSA_TYPE_NORMAL (1<<0)
+#define HSC_OOSA_TYPE_RAVAS_SUSPEND (1<<1)
+#define HSC_OOSA_TYPE_INFINITE_SLEEP (1<<2)
+#define HSC_OOSA_TYPE_FLIGHT_MODE (1<<3)
+#define MAX_OOSA_SLEEP_DURATION_1XRTT (1800) /*unit:0.1s, 180 s for 1xRTT */
+#define MAX_OOSA_SLEEP_DURATION_EVDO (6000) /*unit:0.1s, 600 s for 1xRTT */
+
+/* Convert the OOSA sleep duration(unit 0.1 second) to FRC( Unit 1 us),
+the MAX SLEEP DURATION: 600s for EVDO, 180 s for 1xRTT */
+#define M_0P1SEC_TO_FRC(a) ((kal_uint64)a*100000L)
+
+typedef struct
+{
+ kal_uint8 OosaSleepType;
+ OosaStateT OosaState;
+ kal_uint32 StartTime; /* In FRC */
+ kal_uint32 WakeTime; /* In FRC */
+ kal_uint32 SleepDuration; /* In 0.1s */
+ kal_bool WakeupFlag;
+ kal_uint8 OosaWakeupType;
+} HscOosaT;
+
+
+typedef struct
+{
+ HscSysAirInterfaceT Owner;
+} HscOosaSleepEvtT;
+
+
+
+
+#if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1)
+/*----------------------------------------------------------------------------
+ HSC GAP servive definitions
+----------------------------------------------------------------------------*/
+typedef struct
+{
+ kal_bool SltWakePend; /* DO slotted wake pending for GAP stopping */
+ kal_bool OosaWakePend; /* OOSA wake pending for GAP stopping */
+ kal_bool ContOosaPend; /* CONT OOSA sleep pending */
+ kal_uint32 GapEndFrame; /* Frame number of GAP end when DO slotted sleep */
+ kal_uint32 ContSleepDuration; /* in 100ms */
+ kal_bool GapGate; /* KAL_TRUE: means can't offer gap to MD1 */
+} HscGapT;
+#endif
+
+
+/*----------------------------------------------------------------------------
+ HSC General definitions
+----------------------------------------------------------------------------*/
+typedef enum
+{
+ HSC_OOSA_TIMER_1X_ID,
+ HSC_OOSA_TIMER_DO_ID,
+ HSC_CLK_CAL_FAST_SETTLE_TIMER_ID,
+ HSC_SHDR_MODE_TIMER_ID,
+ HSC_NUM_TIMERS
+} HscTimerIds;
+
+typedef enum
+{
+ HSC_T_MPA_ANT_AVAILABLE,
+ HSC_T_MPA_ANT_ASSIGNED
+}HscAntStatusT;
+
+
+#if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1)
+/* GAP servive */
+extern HscGapT HscGap;
+#endif
+
+
+
+/*****************************************************************************
+* $Log: hscdefs.h $
+*****************************************************************************/
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+/**Log information: \main\Trophy\Trophy_ylxiao_href22033\1 2013-03-18 14:14:24 GMT ylxiao
+** HREF#22033, merge 4.6.0**/
+/**Log information: \main\Trophy\1 2013-03-19 05:18:41 GMT hzhang
+** HREF#22033 to merge 0.4.6 code from SD.**/
+/**Log information: \main\Trophy\Trophy_jluo_href22084\1 2013-04-03 04:11:28 GMT jluo
+** HREF#22084:HANDROID#1723**/
+/**Log information: \main\Trophy\2 2013-04-03 06:24:59 GMT czhang
+** HREF#22084**/
+
diff --git a/mcu/interface/l1/cl1/common/hscmsg.h b/mcu/interface/l1/cl1/common/hscmsg.h
new file mode 100644
index 0000000..faab192
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hscmsg.h
@@ -0,0 +1,118 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*************************************************************
+*
+* This Software is the property of VIA Telecom, Inc. and may only be used pursuant to a license from VIA Telecom, Inc.
+*
+* Any unauthorized use inconsistent with the terms of such license is strictly prohibited.
+*
+* Copyright (c) 1998-2011 VIA Telecom, Inc. All rights reserved.
+*
+*************************************************************/
+/*****************************************************************************
+
+ FILE NAME: hscmsg.h
+
+ DESCRIPTION:
+
+ This file contains the defenitions of all the HSC msg id's.
+
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Message IDs for signals and commands sent to HSC
+*----------------------------------------------------------------------------*/
+
+#include "hsc_msgid.h"
+
+#ifndef MSG_ID_MISMATCH_DETECT
+#undef MSGID_SET
+#undef MSGID_NEXT
+
+
+// regular msg id's enum
+#define MSGID_SET(name, val) name = val
+#define MSGID_NEXT(name) name
+
+#define HSC_SPDO_MSG_IDS typedef enum
+#define HSC_SPDO__MSG_IDS_NAME HscSpDoMsgIdT
+#define HSC_SP1X_MSG_IDS typedef enum
+#define HSC_SP1X__MSG_IDS_NAME HscSp1xMsgIdT
+#define HSC_CMD_MSG_IDS typedef enum
+#define HSC_CMD__MSG_IDS_NAME HscCmdMsgIdT
+
+
+extern const kal_uint32 HscSpDoValidMsgIdList[];
+extern kal_uint32 HscSpDoValidMsgIdListSizeOf(void);
+extern const kal_uint32 HscSp1xValidMsgIdList[];
+extern kal_uint32 HscSp1xValidMsgIdListSizeOf(void);
+extern const kal_uint32 HscCmdValidMsgIdList[];
+extern kal_uint32 HscCmdValidMsgIdListSizeOf(void);
+
+
+#else
+
+
+#ifdef HWD_MSG_ID_MISMATCH_DETECT
+#define HSC_SPDOValidMsgIdList HwdHscSpDoValidMsgIdList
+#define HSC_SP1XValidMsgIdList HwdHscSp1xValidMsgIdList
+#define HSC_CMDValidMsgIdList HwdHscCmdValidMsgIdList
+#else
+#define HSC_SPDOValidMsgIdList HscSpDoValidMsgIdList
+#define HSC_SP1XValidMsgIdList HscSp1xValidMsgIdList
+#define HSC_CMDValidMsgIdList HscCmdValidMsgIdList
+#endif
+
+
+#undef HSC_SPDO_MSG_IDS
+#undef HSC_SPDO__MSG_IDS_NAME
+#undef HSC_SP1X_MSG_IDS
+#undef HSC_SP1X__MSG_IDS_NAME
+#undef HSC_CMD_MSG_IDS
+#undef HSC_CMD__MSG_IDS_NAME
+
+
+
+#define HSC_SPDO_MSG_IDS const kal_uint32 HSC_SPDOValidMsgIdList[] =
+#define HSC_SPDO__MSG_IDS_NAME
+#define HSC_SP1X_MSG_IDS const kal_uint32 HSC_SP1XValidMsgIdList[] =
+#define HSC_SP1X__MSG_IDS_NAME
+#define HSC_CMD_MSG_IDS const kal_uint32 HSC_CMDValidMsgIdList []=
+#define HSC_CMD__MSG_IDS_NAME
+
+
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/hsctypdefs.h b/mcu/interface/l1/cl1/common/hsctypdefs.h
new file mode 100644
index 0000000..4948bdf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/hsctypdefs.h
@@ -0,0 +1,76 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _HSCTYPEDEFS_H_
+#define _HSCTYPEDEFS_H_
+/*****************************************************************************
+*
+* FILE NAME : hsctypdefs.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Include Files
+----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ typedef
+----------------------------------------------------------------------------*/
+typedef kal_uint8 MpaRfPathBmpT;
+
+typedef kal_uint8 MpaAntTypeBmpT;
+
+typedef enum
+{
+ MPA_RF_DENIED = 0,
+ MPA_RF_GRANT,
+ MPA_RF_PENDING,
+ MPA_RF_STATUS_NUM
+} MpaRfAssignStatusT;
+
+
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/nvram_cl1def.h b/mcu/interface/l1/cl1/common/nvram_cl1def.h
new file mode 100644
index 0000000..21a4ae9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/nvram_cl1def.h
@@ -0,0 +1,104 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * nvram_cl1def.h
+ *
+ * Project:
+ * --------
+ * 93
+ *
+ * Description:
+ * ------------
+ * C2K interface declaration provided to NVRAM.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#ifndef _NVRAM_CL1DEF_H_
+#define _NVRAM_CL1DEF_H_
+
+#include "cl1_rf_public.h"
+
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##aFFIX##_##nAME##_ITEM,
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1CAL_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1CAL_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##nAME##_##aFFIX##_ITEM,
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) NVRAM_EF_CL1_##nAME##_##aFFIX##_ITEM,
+
+typedef enum {
+ #include "cl1_nvram_id.h"
+ CL1D_RF_NVRAM_ITEM_MAX_NUM
+} NVRAM_CL1_LID_IDX_E;
+
+
+typedef void* CL1D_RF_CUST_DATA_SET_INFO_T;
+
+
+extern const CL1D_RF_CUST_DATA_SET_INFO_T c1ld_rf_cust_data_drdi_set_ptr[][CL1D_RF_NVRAM_ITEM_MAX_NUM];
+
+#endif /* _NVRAM_CL1DEF_H_ */
+
+
diff --git a/mcu/interface/l1/cl1/common/reg_access.h b/mcu/interface/l1/cl1/common/reg_access.h
new file mode 100644
index 0000000..0aab1da
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/reg_access.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef REG_ACCESS_H
+#define REG_ACCESS_H
+
+#define REG_READ(val) (kal_uint8)((HwdRead32(val)))
+#define REG_WRITE(reg, val) HwdWrite32(reg, val)
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/stub_msg_struct.h b/mcu/interface/l1/cl1/common/stub_msg_struct.h
new file mode 100644
index 0000000..6a0e7bf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/stub_msg_struct.h
@@ -0,0 +1,330 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2017
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* FILE NAME :stub_msg_struct.h
+*
+* DESCRIPTION :This module defines the Layer 1 ILM messgae struct for L1 STUB module
+*
+*
+* HISTORY :
+* 1.File Create by Hairong.Wang, 2017,02,20
+*
+*****************************************************************************/
+
+#ifndef _STUB_MSG_STRUCT_H
+#define _STUB_MSG_STRUCT_H
+
+#ifdef MTK_DEV_C2K_SRLTE_BASE
+/**********************************************STUB Interface Related*********************************/
+/* The rat status enmu. */
+typedef enum
+{
+ CBS_LL1STUB_RAT_FLIGHT,
+ CBS_LL1STUB_RAT_STANDBY,
+ CBS_LL1STUB_RAT_ACTIVE
+}CbsLl1stubRatStatusE;
+
+/* The mode status enmu. */
+typedef enum
+{
+ CBS_LL1STUB_NULL_MODE,
+ CBS_LL1STUB_IDLE_MODE,
+ CBS_LL1STUB_CONNECT_MODE
+}CbsLl1stubModeStatusE;
+
+/* The RAT enmu. */
+typedef enum
+{
+ INVALID_RAT,
+ STUB_LTE,
+ STUB_GSM,
+ STUB_TDS
+
+}RatE;
+
+/* RAT_MODE_T */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ RatE Rat; /* LTE/GSM */
+ CbsLl1stubRatStatusE RatStatus; /* Flight/Standby/Active. */
+ CbsLl1stubModeStatusE ModeStatus; /* NULL/IDLE/CONNECTED. */
+}cbs_rat_mode_status_ind_struct,
+el1_rat_mode_status_ind_struct;
+
+
+/* The Operation enmu. */
+typedef enum
+{
+ MD1_STUB_INVALID_OP,
+ MD1_STUB_OP_ADD,
+ MD1_STUB_OP_DELETE,
+ MD1_STUB_OP_CHANGE
+}StubOperationE;
+
+
+/* The ChannelType enmu. */
+typedef enum
+{
+ /* C2K channel types define*/
+ StubCTimerNone = 0, /*00*/
+ StubCTimerXL1IcsPilot, /*01*/
+ StubCTimerXL1IcsSync, /*02*/
+ StubCTimerXL1NsltPchOvhd, /*03*/
+ StubCTimerXL1NsltInterMeas, /*04*/
+ StubCTimerXL1AfltMeas, /*05*/
+ StubCTimerXL1SltCci, /*06*/
+ StubCTimerXL1SltQpch_1, /*07*/
+ StubCTimerXL1SltQpch_2, /*08*/
+ StubCTimerXL1SltPch, /*09*/
+ StubCTimerXL1SltPchLostDet, /*10*/
+ StubCTimerXL1SltnterMeas, /*11*/
+ StubCTimerXL1ConnectPsRx, /*12*/
+ StubCTimerXL1ConnectInterMeas, /*13*/
+ StubCTimerXL1ConnectAfltMeas, /*14*/
+ StubCTimerEvL1IcsPilot, /*15*/
+ StubCTimerEvL1IcsSync, /*16*/
+ StubCTimerEvL1NsltCC, /*17*/
+ StubCTimerEvL1SltPch, /*18*/
+ StubCTimerEvL1InterMeas, /*19*/
+ StubCTimerEvL1ConnectRx, /*20*/
+ StubCTimerEvL1ConnectInterMeas, /*21*/
+ StubCTimerEvStdbyMeas, /*22*/
+ StubCTimerEvStdbySync, /*23*/
+ StubCTimerEvStdbyCgi, /*24*/
+ StubCTimerEnd, /*25*/
+ /* LTE channel types define */
+ Stub4GTimerMacDrxsch, /*26*/
+ Stub4GTimerRach, /*27*/
+ Stub4GTimerIntraFreqCsMeas, /*28*/
+ Stub4GTimerInterFreqCsMeas, /*29*/
+ Stub4GTimerInterFreqGapCsMeas, /*30*/
+ Stub4GTimerDlSync, /*31*/
+ Stub4GTimerNbrBcchHigh, /*32*/
+ Stub4GTimerNbrBcchCsHigh, /*33*/
+ Stub4GTimerPaging, /*34*/
+ Stub4GTimerPagingDump, /*35*/
+ Stub4GTimerServBcch, /*36*/
+ Stub4GTimerSrvBcch, /*37*/
+ Stub4GTimerSrvBcchCs, /*38*/
+ Stub4GTimerNbrBcchMiddle, /*39*/
+ Stub4GTimerNbrBcchCsMiddle, /*40*/
+ Stub4GTimerNbrBcchLow, /*41*/
+ Stub4GTimerNbrBcchCsLow, /*42*/
+ Stub4GTimerCsr, /*43*/
+
+ /* GSM channel types define */
+ Stub2GTimerBcch, /*44*/
+ Stub2GTimerNBcch, /*45*/
+ Stub2GTimerPdtch, /*46*/
+ Stub2GTimerPacch, /*47*/
+ Stub2GTimerPtcch, /*48*/
+ Stub2GTimerServingSB, /*49*/
+ Stub2GTimerPollingResp, /*50*/
+ Stub2GTimerSingleDl, /*51*/
+ Stub2GTimerPollResp, /*52*/
+ Stub2GTimerPch, /*53*/
+ Stub2GTimerSB, /*54*/
+ Stub2GTimerFCBSearch, /*55*/
+ Stub2GTimerFullScan, /*56*/
+ Stub2GTimerSingleUlTwoPhase, /*57*/
+ Stub2GTimerAgch, /*58*/
+ Stub2GTimerCbch, /*59*/
+ Stub2GTimerPtcchUp, /*60*/
+ Stub2GTimerPtcchDown, /*61*/
+ Stub2GTimerFcchT, /*62*/
+ Stub2GTimerSchT, /*63*/
+ Stub2GTimerIM, /*64*/
+ Stub2GTimerPdch, /*65*/
+ StubTdsTimerBchHigh, /*66*/
+ StubTdsTimerBchMed, /*67*/
+ StubTdsTimerBchLow, /*68*/
+ StubTdsTimerPich, /*69*/
+ StubTdsTimerPch3G, /*70*/
+ StubTdsTimerRxtx, /*71*/
+ StubTdsTimerMeas, /*72*/
+ StubTdsTimerSCS, /*73*/
+ StubTdsTimerRa, /*74*/
+
+ StubTotalTimerNum /*75*/
+}ChannelTypeE;
+
+#define C2K_CHANNEL_START StubCTimerNone
+#define C2K_CHANNEL_END StubCTimerEnd
+#define LTE_CHANNEL_START Stub4GTimerMacDrxsch
+#define LTE_CHANNEL_END Stub4GTimerCsr
+#define GSM_CHANNEL_START Stub2GTimerBcch
+#define GSM_CHANNEL_END Stub2GTimerPdch
+#define TDS_CHANNEL_START StubTdsTimerBchHigh
+#define TDS_CHANNEL_END StubTdsTimerRa
+
+
+/* SCRIPT_CHANNEL_INFO_T */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ RatE Rat; /* LTE/GSM */
+ StubOperationE Operation; /* add/delete/change. */
+ ChannelTypeE ChannelType; /* LTE/GSM channel type */
+ kal_uint32 ChannelOffset; /* channel offset base on FRCtime(0),unit:us */
+ kal_uint32 ChannelLength; /* channel length, unit:us */
+ kal_uint32 Period; /* channel period. for PCH channel, period means DRXCycle;"0"means for continuous receive channel; 0xFFFFFFFF for unperiodic channel;uint:us */
+}cbs_channel_config_ind_struct;
+
+/* CHANNEL_INFO_T */
+typedef struct
+{
+ kal_bool valid; /* indicate the channel is valid or not */
+ kal_uint32 Offset; /* channel offset base on FRCtime(0),unit:us */
+ kal_uint32 Length; /* channel length, unit:us */
+ kal_uint32 Period; /* channel period. for PCH channel, period means DRXCycle;"0"means for continuous receive channel; 0xFFFFFFFF for unperiodic channel;uint:us */
+}CBS_CHANNEL_DATA_T;
+
+/* CBS LTE/GSM STATE enum */
+typedef enum
+{
+ FLIGHT,
+ LTE_SUSPEND,
+ LTE_STANDBY,
+ LTE_IDLE,
+ LTE_PS,
+ GSM_IDLE,
+ GSM_V_IDLE,
+ GSM_PS,
+ TDS_IDLE,
+ TDS_PS,
+ TDS_STANDBY,
+ TDS_V_IDLE
+
+}CbsRtbModeStateE;
+
+/* CbsRatStatusT */
+typedef struct
+{
+ CbsRtbModeStateE LteState; /* indicate LTE state */
+ CbsRtbModeStateE GsmState; /* indicate GSM state */
+ CbsRtbModeStateE TdsState; /* indicate TDS state */
+}CBS_RTB_MODE_STATE_T;
+
+
+/* Ll1stubCbsChannelNotifyT */
+typedef struct
+{
+ ChannelTypeE ChannelType; /* LTE's inter_freq number */
+ StubOperationE Operation; /* add/delete/change. */
+
+}LL1STUB_CBS_CHANNEL_NOTIFY_T;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ LL1STUB_CBS_CHANNEL_NOTIFY_T msg;
+}ll1stub_cbs_channel_notify_ind_struct;
+
+/* EL1_ACTIVE_MEASURE_INFO_T */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 FreqNum; /* only for LTE channel type */
+}el1_active_measure_info_ind_struct;
+
+typedef enum
+{
+ NULL_MEAS,
+ MEAS_ON,
+ MEAS_OFF,
+ CARRIER_SERACH_ON,
+ CARRIER_SERACH_OFF,
+ BCCH_ON,
+ BCCH_OFF
+}MeasPurposeE;
+
+/* EL1_STANDBY_MEASURE_REQ_T */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ MeasPurposeE MeasPurpose;
+}el1_standby_measure_req_struct;
+
+/* EL1_AUTO_GAP_AVAILABLE_IND_T */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool available;
+}el1_auto_gap_available_ind_struct;
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint16 LTE_scan_active_duration_1xRTT; /* unit in milisecond, value range [1..10000], 0xFFFF means invalid (feature off) */
+ kal_uint16 LTE_scan_active_duration_DO; /* unit in milisecond, value range [1..1000], 0xFFFF means invalid (feature off) */
+ kal_bool IsStopGapAdv; /* to indicate special case that need stop LTE MMO standby measure in gap range */
+ kal_bool IsDoSigProtectInGap; /* to indicate special case that need send Do protect signal start in gap range */
+ kal_bool IsRttSigProtectInGap; /* to indicate special case that need send RTT protect signal start in gap range */
+}
+ll1a_script_lte_scan_c2k_active_params_ind_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_bool IsProtect; /* to indicate ps signal need protect or not */
+}
+ll1a_script_ps_mmo_signal_protect_ind_struct;
+
+typedef enum
+{
+ STUB_RSVAS_SUSPEND,
+ STUB_RSVAS_RESUME
+} ScriptRsvasSupendResumeT;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ ScriptRsvasSupendResumeT RsvasCmdType; /* to indicate rsvas cmd type to ll1stub */
+}
+ll1stub_script_rsvas_suspend_resume_ind_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+}rsvas_cl1_ll1_resume_ind_struct, rsvas_cl1_ll1_suspend_ind_struct; /* for send msg to LL1A */
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+}el1_stop_gap_ind_struct;
+
+
+#endif
+#endif
diff --git a/mcu/interface/l1/cl1/common/sys32kless.h b/mcu/interface/l1/cl1/common/sys32kless.h
new file mode 100644
index 0000000..c120a63
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/sys32kless.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#ifndef _SYS32KLESS_H_
+#define _SYS32KLESS_H_
+/*****************************************************************************
+*
+* FILE NAME : sys32kless.h
+*
+* DESCRIPTION : Defines local interface for 32K-less.
+*
+* HISTORY :
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#include "sysapi.h"
+
+
+
+/*----------------------------------------------------------------------------
+ Global Defines and Macros
+----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+extern kal_bool SysIs32klessMode(void);
+#if defined(MT6763) && !defined(L1_SIM)
+extern kal_bool Sys32klessSleepAllowed(void);
+#endif
+extern void Sys32klessSetLpmKreslt(SysAirInterfaceT Adjuster, kal_int32 K_result, kal_int32 TimeDrift);
+extern void Sys32klessUpdateLpmParam(SysAirInterfaceT Adjuster, kal_bool ForceUpdate);
+extern void Sys32klessUpdateFpmParam(SysAirInterfaceT Adjuster, kal_int32 AfcFreqOffset);
+extern void Sys32klessPNUpdate(SysAirInterfaceT Adjuster, kal_uint16 PilotPN);
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
+
+
+
+
diff --git a/mcu/interface/l1/cl1/common/syscommon.h b/mcu/interface/l1/cl1/common/syscommon.h
new file mode 100644
index 0000000..ad8a1d2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/syscommon.h
@@ -0,0 +1,156 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*************************************************************
+*
+* This Software is the property of VIA Telecom, Inc. and may only be used pursuant to a license from VIA Telecom, Inc.
+*
+* Any unauthorized use inconsistent with the terms of such license is strictly prohibited.
+*
+* Copyright (c) 2006-2010 VIA Telecom, Inc. All rights reserved.
+*
+*************************************************************/
+#ifndef _SYSCOMMON_H_
+#define _SYSCOMMON_H_
+
+/*****************************************************************************
+*
+* FILE NAME : syscommon.h
+*
+* DESCRIPTION : Common functions for DO & 1X
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Include Files
+----------------------------------------------------------------------------*/
+#include "sysapi.h"
+
+/*----------------------------------------------------------------------------
+ Global Defines And Macros
+----------------------------------------------------------------------------*/
+
+/* Turn these RMC debug ifdefs OFF */
+/*
+#define RMC_SCH_INPUT_BUFFER_CAPTURE_ENABLE
+#define RMC_MAC_FINGER_WORKAROUND
+#define RMC_MBP_UNIT_TEST
+#define RMC_MBP_UNIT_TEST_RPC
+#define RMC_MAC_PROC_RESET
+#define IRAT_MULTIMODE_TEST
+*/
+
+#define RMC_EQUALIZER
+#define RMC_EQ_RAKE_AUTO_COMBINE
+
+/* Turn these RMC debug ifdefs ON */
+#define RMC_MBP_UNIT_TEST_RPC
+#define RMC_MAC_PN_LOAD_ISSUE
+#define RMC_MBP_RENUM_FIX
+
+#define CCM_ACM_DSA_TEST
+
+#define FCP_FWD_ACK_DEBUG
+#define FCP_PACKET_PERF_STAT
+#define AFC_IMPROVE
+
+/* #define RCP_RTM_REVA_WORK_AROUND */
+/* #define FCP_FTM_DRC_BY_PASS */
+/* #define FCP_FTM_DRC_TEST */
+
+#define FCP_FTM_DRC_MIPS_BY_PASS
+
+
+#define RCP_PACKET_PERF_STAT
+
+#define RTM_TXTIME_PROFILE
+/*
+#define RTM_DUAL_FCS_BUFFER
+*/
+
+/*#define FWD_CHAN_MON_TEST */
+
+/*----------------------------------------------------------------------------
+Global Typedefs
+----------------------------------------------------------------------------*/
+/* OOSA_WAKEUP_TYPE */
+typedef enum
+{
+ OOSA_NORMAL_WAKEUP,
+ OOSA_EARLY_WAKEUP,
+ OOSA_WAKEUP_MAX
+} OosaWakeupTypeT;
+
+typedef enum
+{
+ CONV_LOG10_10,
+ CONV_LOG10_20,
+ CONV_LOG2
+} LogScaleConvTypeT;
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+/* RandNum Generator */
+extern void SysRandomNumberInit(void);
+extern kal_uint32 SysRandomNumber( kal_uint32 range );
+
+/* Misc Operations */
+extern kal_uint32 SysGetWrappedResult( kal_uint32 val, kal_int32 offset, kal_uint32 wrapLen );
+extern kal_uint32 SysGetWrappedResult2( kal_uint32 val, kal_int32 offset, kal_uint32 wrapLen );
+extern FrameRecT SysGetFrameTimeAdded( FrameRecT time, kal_int32 offset );
+extern SysTimeFullT SysGetSlotTimeAdded( SysTimeFullT time, kal_int32 offset );
+extern FrameRecT SysConvertSysTime1XtoDO( FrameRecT Time1X );
+
+/* Gain to Linear Conversion functions */
+extern kal_uint32 SysDb2LinearConv(kal_int16 GainDb);
+
+/* Linear to Gain Conversion functions */
+extern kal_int16 SysLinear2DbmConv(kal_uint32 LinearGain);
+extern kal_int16 SysLinear2DbConv(kal_uint32 LinearGain);
+
+extern void Sha1Hash(const void *data, kal_uint32 len, kal_uint8 *dst);
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/sysfrc.h b/mcu/interface/l1/cl1/common/sysfrc.h
new file mode 100644
index 0000000..13fbd2c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/sysfrc.h
@@ -0,0 +1,127 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#ifndef _SYSFRC_H_
+#define _SYSFRC_H_
+/*****************************************************************************
+*
+* FILE NAME : sysfrc.h
+*
+* DESCRIPTION : Defines local interface for FRC.
+*
+* HISTORY :
+*
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "systyp.h"
+#include "valapi.h"
+
+
+
+/*----------------------------------------------------------------------------
+ Global Defines and Macros
+----------------------------------------------------------------------------*/
+
+/* Val * 9.8304 * (1 + AfcPpb/1000000000) */
+#define SYS_CONVERT_FRC_TO_9M(Val, AfcPpb) ((((kal_int64)(Val)) * 6144 + ((((kal_int64)(Val)) * (AfcPpb) * 3) >> 19)) / 625)
+
+/* Val / (1 + AfcPpb/1000000000) / 9.8304 = Val * (1 - AfcPpb/1000000000) / 9.8304 */
+#define SYS_CONVERT_9M_TO_FRC(Val, AfcPpb) ((kal_uint32)((((kal_int64)(Val)) * 625 - ((((kal_int64)(Val)) * (AfcPpb) * 625) >> 30)) / 6144))
+
+#define MAX_FRC_CNT (0x100000000UL)
+#define C2K_FRC_WRAP (0xFFFFFFFF)
+#define FRC_FREQ (1000000L) /* 1 MHz */
+
+#if defined(__FPGA__) && defined(__MTK_TARGET__)
+/* In FPGA vefication platform, Rx Timer clock frequency has downscale 100\50,
+ but FRC clock remains 1MHz. Therefore, need to correct FRC value by /(100 or 50) */
+#if defined(__MD93__)||defined(__MD95__)
+#define FRC_DOWNSCALE_FACTOR (100)
+#endif
+#if defined(__MD97__) || defined(__MD97P__)
+#define FRC_DOWNSCALE_FACTOR (160)
+#endif
+#else
+#define FRC_DOWNSCALE_FACTOR (1)
+#endif
+
+/* Diff of two comapred FRC number cannot be bigger than 2^31: 2147.5s */
+#define MAX_FRC_DIFF (0x80000000)
+
+/** To check earlrFRC is earlier than lateFRC */
+#define FRC_COMPARE(early, late) \
+ (((early < late) && ((late - early) < MAX_FRC_DIFF)) || \
+ ((early > late) && ((early - late) > MAX_FRC_DIFF)))
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+extern void SysFrcStartTimeSync(SysAirInterfaceT Interface);
+extern void SysFrcStopTimeSync(SysAirInterfaceT Interface);
+extern void SysFrcReset(SysAirInterfaceT Interface);
+extern void SysFrcSetSnapshot(SysAirInterfaceT Interface, SysSFrameTimeT *SysTime, kal_uint32 Frc);
+extern kal_bool SysFrcConvertToSt(SysAirInterfaceT Interface, kal_uint32 Frc, SysSFrameTimeT *SysTime);
+extern void SysFrcConvertToStForce(SysAirInterfaceT Interface, kal_uint32 Frc, SysSFrameTimeT *SysTime,kal_bool NeedTrace);
+extern kal_bool SysStConvertToFrc(SysAirInterfaceT Interface, SysSFrameTimeT *SysTime, kal_uint32 *Frc);
+extern kal_bool SysFrcSyncIsValid(SysAirInterfaceT Interface);
+extern kal_bool SysFrcGetNextFrameBoundary(SysAirInterfaceT Interface, kal_bool Check20msBoundary, kal_uint32 CheckTime, kal_uint32 *FrcFrameBoundary, kal_bool UseFrameOffset);
+extern kal_uint32 SysFrcCntGet(void);
+extern kal_uint32 SysFrcCntGetNoDS(void);
+extern kal_uint8 SysFrcHighCntGet(void);
+extern kal_bool SysFrcReadSnapshotImm(SysAirInterfaceT Interface, SysSFrameTimeT* SFrameTime, kal_uint32* Frc);
+extern void SysFrcReptSyncInfo(SysAirInterfaceT Interface);
+extern void SysFrcReadSnapshotImmDvt(SysAirInterfaceT Interface, SysSFrameTimeT* SFrameTime, kal_uint32* Frc);
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
diff --git a/mcu/interface/l1/cl1/common/sysswi.h b/mcu/interface/l1/cl1/common/sysswi.h
new file mode 100644
index 0000000..4045821
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/sysswi.h
@@ -0,0 +1,76 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* FILE NAME : sysswi.h
+*
+* DESCRIPTION : Defines local interface for SWI control.
+*
+* HISTORY :
+*
+*
+*****************************************************************************/
+
+#ifndef _SYSSWI_H_
+#define _SYSSWI_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Defines and Macros
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+extern void SysFrFhSwiLisr(void);
+extern void SysDoCrpSwiLisr(void);
+extern void SysBackupSwiLisr(void) ;
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/tlsapi.h b/mcu/interface/l1/cl1/common/tlsapi.h
new file mode 100644
index 0000000..95c2d92
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/tlsapi.h
@@ -0,0 +1,161 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*************************************************************
+*
+* This Software is the property of VIA Telecom, Inc. and may only be used pursuant to a license from VIA Telecom, Inc.
+*
+* Any unauthorized use inconsistent with the terms of such license is strictly prohibited.
+*
+* Copyright (c) 2002-2010 VIA Telecom, Inc. All rights reserved.
+*
+*************************************************************/
+/*****************************************************************************
+*
+* FILE NAME : tlsapi.h
+*
+* DESCRIPTION : API definition for TLS task.
+*
+* HISTORY :
+*****************************************************************************/
+#ifndef _TLSAPI_H_
+#define _TLSAPI_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "do_msgdefs.h"
+#include "syscommon.h"
+/*----------------------------------------------------------------------------
+ Global Defines and Macros
+----------------------------------------------------------------------------*/
+#define TLS_PRIORITY_STRING_LEN 256
+#define TLS_MAX_SPY_LEN 164
+
+/*----------------------------------------------------------------------------
+ Mailbox IDs
+----------------------------------------------------------------------------*/
+#define TLS_MAILBOX_CMD EXE_MAILBOX_1_ID
+
+/*----------------------------------------------------------------------------
+ Command Message IDs, for TLS task, for TLS_MAILBOX_CMD, EXE_MAILBOX_1_ID
+ The messages IDs for components shall also be put in here.
+----------------------------------------------------------------------------*/
+typedef enum /*_Message_ID_define*/
+{
+ TLS_TEST_ANON_MSG = TLS_CMD_MSGID_START,
+ TLS_TRANSPORT_CONNECT_RSP_MSG,
+ TLS_HANDSHAKE_MSG,
+ TLS_TIMER_EXPIRED_MSG,
+ TLS_HANDSHAKE_FINISH_MSG,
+ TLS_RECORD_RECV_MSG,
+ TLS_BYE_MSG,
+ TLS_TEST_X509_MSG,
+ TLS_TEST_OPENPGP_MSG,
+
+ TLS_VAL_CONN_REQ,
+ TLS_VAL_SEND_REQ,
+ TLS_VAL_CLOSE_REQ,
+
+
+ TLS_CMD_MSGID_LAST
+} TlsMsgIdT;
+
+typedef enum /*_Trace_ID_define*/
+{
+ TLS_TRACE_PEER_CLOSED_TLS_CONNECTION,
+ TLS_TRACE_RECV_RECORD_ERROR,
+ TLS_TRACE_HANDSHAKE_ERROR,
+ TLS_TRACE_HANDSHAKE_IN_PROGRESS,
+ TLS_TRACE_HANDSHAKE_COMPLETE,
+
+ TLS_TRACE_LAST
+} TlsGeneralTraceIdT;
+
+typedef PACKED_PREFIX struct
+{
+ kal_uint8 Priorities[TLS_PRIORITY_STRING_LEN];
+} PACKED_POSTFIX TlsTestMsgT;
+
+typedef struct {
+ void *session;
+} TlsByeMsgT;
+
+typedef struct {
+ void *session;
+} TlsHandshakeMsgT;
+
+typedef struct {
+ void *session;
+} TlsHandshakeFinishMsgT;
+
+typedef struct {
+ void *session;
+} TlsRecordRecvMsgT;
+
+typedef PACKED_PREFIX struct{
+ kal_uint16 TimerID;
+} PACKED_POSTFIX TlsTimerExpiredMsgT;
+
+
+
+/* The UE shall only support Alternative Client Authentication based security. */
+typedef struct {
+ kal_uint32 addressType; /* 0: IPV4, 1: IPv6, 2: both */
+ kal_uint32 address[5]; /* [0]: IPV4 address, [1]-[4] IPV6 address */
+ kal_uint16 locadPort;
+ kal_uint16 remotePort;
+ kal_uint16 certType;
+ kal_uint16 certLength;
+ kal_uint8 certBuf[1];
+}TlsOpenReqMsgT;
+
+
+typedef struct {
+ kal_uint32 len; /* length of data to be sent */
+ kal_uint8 * buf; /* buffer of data */
+}TlsSendMsgT;
+
+typedef struct
+{
+ kal_uint16 len;
+ kal_uint8 *buf;
+}ValTlsSendRspT;
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_dat_public.h b/mcu/interface/l1/cl1/rfd/cl1_rf_dat_public.h
new file mode 100644
index 0000000..78414a8
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_dat_public.h
@@ -0,0 +1,85 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_tas_public.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * Header file containing typedefs and definitions pertaining
+ * to C2K RF driver external interface.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+#ifndef CL1_RF_DAT_PUBLIC_H
+#define CL1_RF_DAT_PUBLIC_H
+
+/*DAT compile option */
+#if defined (__DYNAMIC_ANTENNA_TUNING__)||defined (L1_SIM)
+ #if defined(__MD93__)
+ #define IS_C2K_DAT_RFD_CTRL_EN (1)
+ #define IS_C2K_UDAT_SUPPORT (0)
+ #elif defined(__MD95__)
+ #define IS_C2K_DAT_RFD_CTRL_EN (0)
+ #define IS_C2K_UDAT_SUPPORT (1)
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #define IS_C2K_DAT_RFD_CTRL_EN (0)
+ #define IS_C2K_UDAT_SUPPORT (0)
+ #endif
+#else
+ #define IS_C2K_DAT_RFD_CTRL_EN (0)
+ #define IS_C2K_UDAT_SUPPORT (0)
+#endif
+
+#endif
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_elna_public.h b/mcu/interface/l1/cl1/rfd/cl1_rf_elna_public.h
new file mode 100644
index 0000000..325ab5e
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_elna_public.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_elna_public.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * Header file containing typedefs and definitions pertaining
+ * to C2K RF driver external interface.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+#ifndef CL1_RF_ELNA_PUBLIC_H
+#define CL1_RF_ELNA_PUBLIC_H
+
+#include "cl1d_rf_common_defs.h"
+extern kal_uint32 elna_hwd_mask;
+extern kal_uint32 tpc_hwd_en;
+
+/*ELNA pin control switch */
+#define C2K_ELNA_PIN_NONE (-1)
+#define ELNA_RF_BAND_MAX_NUM (5)
+typedef enum{
+ C2K_ELNA1,
+ C2K_ELNA2,
+ C2K_ELNA3,
+ C2K_ELNA4,
+ C2K_ELNA5,
+ C2K_ELNA6,
+ C2K_ELNA7,
+ C2K_ELNA8,
+ C2K_ELNA9,
+ C2K_ELNA10,
+ C2K_ELNA_MAX_NUM,
+ C2K_ELNA_NONE=C2K_ELNA_MAX_NUM
+}C2K_ELNA_TYPE_E;
+typedef struct{
+ kal_uint8 pnum_pin0; /*the 1st BPI pin num for ELNA crl *//*C2K_ELNA_PIN_NONE means not used */
+ kal_uint8 pnum_pin1; /*the 2nd BPI pin num for ELNA ctr *//*C2K_ELNA_PIN_NONE means not used */
+ kal_uint32 pdata_on_pin0;
+ kal_uint32 pdata_on_pin1;
+ kal_uint32 pdata_bypass_pin0;
+ kal_uint32 pdata_bypass_pin1;
+}C2K_ELNA_BPI_DATA_T;
+typedef struct{
+ /*ELNA Mapping for RF BNAD */
+ kal_uint8 elnaMapping_RX[ELNA_RF_BAND_MAX_NUM];
+ kal_uint8 elnaMapping_RXD[ELNA_RF_BAND_MAX_NUM];
+}CL1D_RF_CUST_ELNA_CFG_T;
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public.h b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public.h
new file mode 100644
index 0000000..0059b0a
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined (__MD93__)
+#include "cl1_rf_poc_public_md93.h"
+#elif defined (__MD95__)
+#include "cl1_rf_poc_public_md95.h"
+#elif defined (__MD97__) || defined (__MD97P__)
+#include "cl1_rf_poc_public_md97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md93.h b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md93.h
new file mode 100644
index 0000000..98deb5d
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md93.h
@@ -0,0 +1,1049 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2017
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+*
+* FILE NAME :cl1_rf_poc_public.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#if defined (__C2K_RAT__) || defined(__CL1_TASK_ENABLE__)
+#ifndef _CL1D_RF_POC_PUBLIC_H_
+#define _CL1D_RF_POC_PUBLIC_H_
+
+#include "cl1d_rf_cid.h"
+//#include "mml1_rxdfe_api.h"
+
+/* TX DFE related */
+#if defined(__MD95__)
+#define TX_DC_COMP_FC_MODE_NUM (1)
+#elif defined(__MD93__)
+#define TX_DC_COMP_FC_MODE_NUM (2)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define TX_DC_COMP_FC_MODE_NUM (1)
+#endif
+
+#if IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define TX_PGA_BIAS_SET_NUM 3
+#endif
+
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define TX_DC_COMP_PGA_SLICE_SET_NUM 4
+#else
+#define TX_DC_COMP_PGA_SLICE_SET_NUM 8
+#endif
+
+#if defined(__MD95__)
+#define TX_IQ_COMP_FC_MODE_NUM (1)
+#elif defined(__MD93__)
+#define TX_IQ_COMP_FC_MODE_NUM (2)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define TX_IQ_COMP_FC_MODE_NUM (1)
+#endif
+
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define TX_IQ_COMP_PGA_SLICE_SET_NUM 4
+#else
+#define TX_IQ_COMP_PGA_SLICE_SET_NUM 8
+#endif
+
+/* RX DFE related */
+#define RX_PATH_MAX_NUM (3)
+#define RX_POWER_MODE_MAX_NUM (2)
+
+#if defined(__MD95__)
+#define RX_FD_FILT_TAPS_MAX_NUM 7 /*> maximum numbers of compensation filter taps */
+#elif defined(__MD93__)
+#define RX_FD_FILT_TAPS_MAX_NUM 7 /*> maximum numbers of compensation filter taps */
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define RX_FD_FILT_TAPS_MAX_NUM 5 /*> maximum numbers of compensation filter taps */
+#endif
+
+#define CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS (3)
+#define CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS (7)
+
+#define CL1D_RF_RXDFE_DC_TIA_GAIN_LPM_STEPS CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS
+#define CL1D_RF_RXDFE_DC_PGA_GAIN_LPM_STEPS CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS
+
+/* TXK DFE related */
+#if defined(__MD95__)
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (13)
+#elif defined(__MD93__)
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (11)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (13)
+#endif
+#if defined(__MD95__)
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (1)
+#elif defined(__MD93__)
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (2)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (1)
+#endif
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define CL1D_RF_TXK_DETDFE_GAIN_STEPS (5)
+#else
+#define CL1D_RF_TXK_DETDFE_GAIN_STEPS (15)
+#endif
+/* RX DEV related */
+#define CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX (19) // CL1D_RF_DEV_RXAGC_TABLE_MAX_INDEX
+#define MMRFC_C2K_POC_TX_PGA_SLICE_NUM (7) // MMRFC_C2K_TX_PGA_SLICE_NUM
+
+#if IS_CL1D_RF_MT6177L
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (21) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (17) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_MT6177M
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (30) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (0) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_TRINITYE1
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (14) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (13) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITYLE2
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (27) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (0) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_TRINITY2L
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (27) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (0) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_COLUMBUSE1
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (14) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (13) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#endif
+#define CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE (CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE + CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE)//CL1D_RF_DEV_TX_PGA_TABLE_SIZE
+
+#define CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE (15) //CL1D_RF_DEV_TXDET_AGC_TABLE_SIZE
+#define CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS (2) //CL1D_RF_DEV_DET_FE_GAIN_STEPS
+
+
+#define CL1D_RF_IF_MAX_NUM (7)
+#define CL1D_RF_DET_PGA_GAIN_STEPS (5)
+
+#if IS_CL1D_RF_MT6177L
+#define CL1D_TX_LPF_NOMINAL_VALUE 172//for 77L
+#elif IS_CL1D_RF_MT6177M
+#define CL1D_TX_LPF_NOMINAL_VALUE 26//for 77M
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define CL1D_TX_LPF_NOMINAL_VALUE 172//Stub for TrinityE1. Will delete later.
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define CL1D_TX_LPF_NOMINAL_VALUE 172
+#endif
+
+#if IS_CL1D_RF_MT6177L
+#define CL1D_TX_RCF_NOMINAL_VALUE 16
+#elif IS_CL1D_RF_MT6177M
+#define CL1D_TX_RCF_NOMINAL_VALUE 17
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define CL1D_TX_RCF_NOMINAL_VALUE 16//Stub for TrinityE1. Will delete later.
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define CL1D_TX_RCF_NOMINAL_VALUE 16
+#endif
+
+#define CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX (14)
+
+typedef enum
+{
+ CL1D_RF_DEV_TIA0,
+ CL1D_RF_DEV_TIA1,
+ CL1D_RF_DEV_TIA_NUM
+}CL1D_RF_DEV_TIA_E;
+
+typedef struct
+{
+ kal_int16 i_part;
+ kal_int16 q_part;
+} CL1D_RF_TXDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXDFE_DC_COMP_T comp_tab[TX_DC_COMP_FC_MODE_NUM][TX_DC_COMP_PGA_SLICE_SET_NUM];
+} CL1D_RF_TXDFE_DC_COMP_TAB_T;
+
+typedef struct
+{
+ kal_int16 gain;
+ kal_int16 phase;
+} CL1D_RF_TXDFE_IQ_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXDFE_IQ_COMP_T comp_tab[TX_IQ_COMP_FC_MODE_NUM][TX_IQ_COMP_PGA_SLICE_SET_NUM];
+} CL1D_RF_TXDFE_IQ_COMP_TAB_T;
+
+#if defined(__MD93__)
+typedef struct{
+ kal_int32 gain_est_hw; /*> S-3.10, epsilon */
+ kal_int32 phase_est_hw;/*> S-4.10, -theta/2, in radians */
+ kal_int16 freq_dep_filt[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+#elif defined(__MD95__)
+typedef struct{
+ // kal_int32 gain_est_hw; /*> S-3.10, epsilon */
+ kal_int8 phase_est_hw;/*> S-4.10, -theta/2, in radians */
+ kal_int16 freq_dep_filt[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+#elif (defined(__MD97__) || defined(__MD97P__))
+typedef struct{
+ kal_int32 rx_fiiq_phase;/*> S-4.10, -theta/2, in radians */
+ kal_int16 rx_fdiq_coef[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+#endif
+
+typedef struct{
+ CL1D_RF_RXDFE_IRR_COMP_T hpm;
+ CL1D_RF_RXDFE_IRR_COMP_T lpm;
+} CL1D_RF_RXDFE_IRR_COMP_PER_PATH_T;
+
+
+typedef struct{
+ CL1D_RF_RXDFE_IRR_COMP_PER_PATH_T rx[RX_PATH_MAX_NUM];
+} CL1D_RF_RXDFE_IRR_COMP_PER_BAND_T;
+
+
+
+
+
+
+#if defined(__MD95__)
+typedef struct
+{
+ kal_uint8 cr_sel; ///< 0: C4R8, 1: C5R7, 2: C6R6, 3: NA
+ kal_uint8 tap_sel; ///< 0: 9 taps, 1: 14 taps
+ kal_uint32 filter_taps[CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX]; ///< s8
+}CL1D_RF_RXDFE_RFEQ_COMP_T;
+
+typedef struct{
+
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_hpm;
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_lpm;
+}CL1D_RXDFE_RFEQ_COMP_BW_T;
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+typedef struct
+{
+ kal_uint32 coef[CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX];
+ kal_uint32 power_saving_mode;
+ kal_uint32 ct_sel; ///< 0: C4R8, 1: C5R7, 2: C6R6, 3: NA
+}CL1D_RF_RXDFE_RFEQ_COMP_T;
+
+typedef struct{
+
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_hpm;
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_lpm;
+}CL1D_RXDFE_RFEQ_COMP_BW_T;
+#endif
+
+
+
+
+typedef struct
+{
+ kal_int16 dc_i; /*> RF DC:S5.0,resolution = 9mV. DFE DC: S0.14, fixed point value at Rx ADC, Rx ADC full swing is +/-1.62v */
+ kal_int16 dc_q; /*> RF DC:S5.0,resolution = 9mV. DFE DC: S0.14, fixed point value at Rx ADC, Rx ADC full swing is +/-1.62v */
+} CL1D_RF_RXDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DC_COMP_T hpm[CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS][CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS];
+ CL1D_RF_RXDFE_DC_COMP_T lpm[CL1D_RF_RXDFE_DC_TIA_GAIN_LPM_STEPS][CL1D_RF_RXDFE_DC_PGA_GAIN_LPM_STEPS];
+} CL1D_RF_RXDFE_DC_COMP_PER_PATH_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DC_COMP_PER_PATH_T rx[RX_PATH_MAX_NUM];
+} CL1D_RF_RXDFE_DC_COMP_PER_BAND_T;
+
+
+/* TRANSCEIVER PART */
+/** POC processing result structure definition*/
+#if IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+typedef struct
+{
+ kal_uint32 i_idx_opt; /*> optimum gate bias on I channel */
+ kal_uint32 q_idx_opt; /*> optimum gate bias on Q channel */
+}RX_IIP2_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int16 tx_abb_csel2;
+ kal_int16 tx_abb_csel1;
+ kal_int16 tx_abb_rsel;
+ //RCF use default value
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_2a;
+ kal_int16 tx_rcf_csel_1a;
+ kal_int16 tx_rcf_rsel;
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int32 tx_coarsedc_i;
+ kal_int32 tx_coarsedc_q;
+}TX_coarse_DC_RESULT_T;
+
+typedef struct
+{
+ kal_uint8 tx_pga_ctune;
+ kal_uint8 tx_mod_ctune;
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[RX_PATH_MAX_NUM];//main/div/sec
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_T rx_iip2_cal_result[RX_PATH_MAX_NUM];//main/div/sec
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX ABB RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;//R use default value
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+ //kal_int16 tx_pga_phase_step;
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result[CL1D_RF_DET_PGA_GAIN_STEPS];
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_txlb_cal_result[CL1D_RF_DET_PGA_GAIN_STEPS];
+
+/* DET spare */
+ //DET_SPARES_T det_spares;
+
+/* MRX PGA&TZA Ctune */
+ kal_uint8 mrx_pga_ctune;//use default value
+ kal_uint8 mrx_tza_ctune;//use default value
+
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+
+#elif IS_CL1D_RF_TRINITYL
+typedef struct
+{
+ kal_uint32 i_idx_opt; /*> optimum gate bias on I channel */
+ kal_uint32 q_idx_opt; /*> optimum gate bias on Q channel */
+}RX_IIP2_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int16 tx_abb_csel2;
+ kal_int16 tx_abb_csel1;
+ kal_int16 tx_abb_rsel;
+ //RCF use default value
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_2a;
+ kal_int16 tx_rcf_csel_1a;
+ kal_int16 tx_rcf_rsel;
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int32 tx_coarsedc_i;
+ kal_int32 tx_coarsedc_q;
+}TX_coarse_DC_RESULT_T;
+
+typedef struct
+{
+ kal_uint8 tx_pga_ctune;
+ kal_uint8 tx_mod_ctune;
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[RX_PATH_MAX_NUM];//main/div/sec
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_T rx_iip2_cal_result[RX_PATH_MAX_NUM];//main/div/sec
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX ABB RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;//R use default value
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+ //kal_int16 tx_pga_phase_step;
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result[CL1D_RF_DET_PGA_GAIN_STEPS];
+
+/* DET spare */
+ //DET_SPARES_T det_spares;
+
+/* MRX PGA&TZA Ctune */
+ kal_uint8 mrx_pga_ctune;//use default value
+ kal_uint8 mrx_tza_ctune;//use default value
+
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+typedef struct
+{
+ kal_uint32 i_idx_opt; /*> optimum gate bias on I channel */
+ kal_uint32 q_idx_opt; /*> optimum gate bias on Q channel */
+}RX_IIP2_CAL_RESULT_CW_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint16 tx_abb_csel;
+ kal_uint16 tx_abb_rsel;
+ //RCF use default value
+ kal_uint16 tx_rcf_csel;
+ kal_uint16 tx_rcf_csel_1b;
+ kal_uint16 tx_rcf_csel_2a;
+ kal_uint16 tx_rcf_rsel;
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int32 tx_coarsedc_i;
+ kal_int32 tx_coarsedc_q;
+}TX_coarse_DC_RESULT_T;
+
+typedef struct
+{
+ kal_uint8 tx_pga_ctune;
+ kal_uint8 tx_mod_ctune;
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoci_sign; /* MRX coarse DC offset I channel sign */
+ kal_uint32 mrx_cdcoci_mag; /* MRX coarse DC offset I channel magnitude */
+ kal_uint32 mrx_cdcocq_sign; /* MRX coarse DC offset Q channel sign */
+ kal_uint32 mrx_cdcocq_mag; /* MRX coarse DC offset Q channel magnitude */
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[3];//Edwin TBD
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_CW_T rx_iip2_cal_result[2];//Edwin TBD
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX ABB RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;//R use default value
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+ kal_int16 tx_pga_phase_step;//Edwin TBD, removed in Gen95
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result[4];//Edwin TBD
+
+/* DET spare */
+ DET_SPARES_T det_spares;//Edwin TBD, not sure if needed or not
+
+/* MRX PGA&TZA Ctune */
+ kal_uint8 mrx_pga_ctune;//use default value
+ kal_uint8 mrx_tza_ctune;//use default value
+
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+
+#else
+typedef struct
+{
+ kal_uint32 rxd_iip2_cw349; /* RX1 IIP2 Cal */
+ kal_uint32 rx_iip2_cw473; /* RX1 IIP2 Cal */
+ kal_uint32 rx_iip2_cw482; /* RX2 IIP2 Cal */
+ kal_uint32 rxd_iip2_cw350;
+}RX_IIP2_CAL_RESULT_CW_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_rc_lpf_cw787; /* TX RC Cal */
+ kal_uint32 tx_rc_rcf_cw793; /* TX RC Cal */
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_bal_cap_cw795; /* TX PGA Cap Tuning */
+ kal_uint32 tx_bal_cap_cw796; /* TX PGA Cap Tuning */
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_cdcoc_cw807; /* DET coarse DCOC */
+ kal_uint32 tx_cdcoc_cw808; /* DET coarse DCOC */
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[3];
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_CW_T rx_iip2_cal_result;
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX LO Cal, config in RF */
+ TX_LO_CAL_RESULT_T tx_lo_cal_result;
+
+/* TX RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;
+
+/* TX IQDC, config in TXDFE */
+// CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T tx_iq_dc_cal_result[MMRFC_C2K_POC_TX_PGA_SLICE_NUM+1];
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX PGA Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+/* TX PGA phase step */
+ kal_int16 tx_pga_phase_step;
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result;
+
+/* DET spare */
+ DET_SPARES_T det_spares;
+
+/* DET DNL, config in RF */
+ kal_int16 det_dnl_cal_result[CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE];
+
+/* DET IQ imbalance with Tx path forward signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T det_iq_fwd[CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS];
+
+/* DET fine DC with Tx path forward signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T det_dc_fwd[CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE];
+
+/* DET IQ imbalance with Tx path reverse signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T det_iq_rev[CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS];
+
+/* DET fine DC with Tx path reverse signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T det_dc_rev[CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE];
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+#endif
+
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_COMP_T coef[CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+}CL1D_RF_TXK_DETDFE_EQLPF_CFG_T;
+
+#if defined(__MD95__)
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+#elif defined(__MD93__)
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain[CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+#elif (defined(__MD97__) || defined(__MD97P__))
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+#endif
+
+typedef struct
+{
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int32 dnl;
+ kal_int32 freq_dep_phase_est; ///< Valid for 2-point meas. for error handling
+}CL1D_RF_TXK_DETDFE_IQ_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_IQ_COMP_T per_fe_gain[CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_IQ_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_int32 dc_est_i; /*> S0.11, fixed point value at Det ADC, Det ADC full swing is +/-0.6v */
+ kal_int32 dc_est_q; /*> S0.11, fixed point value at Det ADC, Det ADC full swing is +/-0.6v */
+}CL1D_RF_TXK_DETDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_DC_COMP_T per_det_gain[CL1D_RF_TXK_DETDFE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T;
+
+#if IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+typedef struct
+{
+ kal_int32 pga_bias[TX_PGA_BIAS_SET_NUM];
+}CL1D_RF_POC_DEV_TX_PGA_BIAS_RESULT_T;
+#endif
+
+typedef struct{
+
+ /* NVRAM version number */
+#if defined(__MD95__)
+ kal_uint32 verno;
+#endif
+
+ /* RXDFE */
+ CL1D_RF_RXDFE_IRR_COMP_PER_BAND_T irr_comp;
+#if defined(__MD95__)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#elif defined(__MD93__)
+ CL1D_RF_RXDFE_DC_COMP_PER_BAND_T dc_comp;
+#endif
+
+ /* TXDFE */
+ CL1D_RF_TXDFE_IQ_COMP_TAB_T tx_iq_comp;
+ CL1D_RF_TXDFE_DC_COMP_TAB_T tx_dc_comp;
+#if defined(__MD95__)
+ CL1D_RF_TXDFE_DC_COMP_TAB_T tx_coarse_dc_comp;
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+ CL1D_RF_TXDFE_DC_COMP_TAB_T tx_coarse_dc_comp;
+#endif
+
+ /* TXKDFE */
+ CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T txk_eqlpf_fwd_comp;
+ CL1D_RF_TXK_DETDFE_IQ_COMP_PER_BAND_T txk_iq_fwd_comp;
+#if IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_TRINITY2L
+ CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T txk_dc_fwd_comp_txlb;
+#endif
+ CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T txk_dc_fwd_comp;
+
+ /* Transceiver */
+ CL1D_RF_POC_DEV_FINAL_RESULT_T poc_dev_fin;
+
+ /* PGA_BIAS */
+#if IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+ CL1D_RF_POC_DEV_TX_PGA_BIAS_RESULT_T tx_pga_bias_comp;
+#endif
+} CL1D_RF_POC_FINAL_T;
+
+#endif /* _CL1D_RF_POC_PUBLIC_H_ */
+#endif
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md95.h b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md95.h
new file mode 100644
index 0000000..dbc010e
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md95.h
@@ -0,0 +1,1051 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2017
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+*
+* FILE NAME :cl1_rf_poc_public.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#if defined (__C2K_RAT__) || defined(__CL1_TASK_ENABLE__)
+#ifndef _CL1D_RF_POC_PUBLIC_H_
+#define _CL1D_RF_POC_PUBLIC_H_
+
+#include "cl1d_rf_cid.h"
+//#include "mml1_rxdfe_api.h"
+
+/* TX DFE related */
+#if defined(__MD95__)
+#define TX_DC_COMP_FC_MODE_NUM (1)
+#elif defined(__MD93__)
+#define TX_DC_COMP_FC_MODE_NUM (2)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define TX_DC_COMP_FC_MODE_NUM (1)
+#endif
+
+#if IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define TX_PGA_BIAS_SET_NUM 3
+#endif
+
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define TX_DC_COMP_PGA_SLICE_SET_NUM 4
+#else
+#define TX_DC_COMP_PGA_SLICE_SET_NUM 8
+#endif
+
+#if defined(__MD95__)
+#define TX_IQ_COMP_FC_MODE_NUM (1)
+#elif defined(__MD93__)
+#define TX_IQ_COMP_FC_MODE_NUM (2)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define TX_IQ_COMP_FC_MODE_NUM (1)
+#endif
+
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define TX_IQ_COMP_PGA_SLICE_SET_NUM 4
+#else
+#define TX_IQ_COMP_PGA_SLICE_SET_NUM 8
+#endif
+
+/* RX DFE related */
+#define RX_PATH_MAX_NUM (3)
+#define RX_POWER_MODE_MAX_NUM (2)
+
+#if defined(__MD95__)
+#define RX_FD_FILT_TAPS_MAX_NUM 7 /*> maximum numbers of compensation filter taps */
+#elif defined(__MD93__)
+#define RX_FD_FILT_TAPS_MAX_NUM 7 /*> maximum numbers of compensation filter taps */
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define RX_FD_FILT_TAPS_MAX_NUM 5 /*> maximum numbers of compensation filter taps */
+#endif
+
+#define CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS (3)
+#define CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS (7)
+
+#define CL1D_RF_RXDFE_DC_TIA_GAIN_LPM_STEPS CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS
+#define CL1D_RF_RXDFE_DC_PGA_GAIN_LPM_STEPS CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS
+
+/* TXK DFE related */
+#if defined(__MD95__)
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (13)
+#elif defined(__MD93__)
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (11)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (13)
+#endif
+#if defined(__MD95__)
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (1)
+#elif defined(__MD93__)
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (2)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (1)
+#endif
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define CL1D_RF_TXK_DETDFE_GAIN_STEPS (5)
+#else
+#define CL1D_RF_TXK_DETDFE_GAIN_STEPS (15)
+#endif
+/* RX DEV related */
+#define CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX (19) // CL1D_RF_DEV_RXAGC_TABLE_MAX_INDEX
+#define MMRFC_C2K_POC_TX_PGA_SLICE_NUM (7) // MMRFC_C2K_TX_PGA_SLICE_NUM
+
+#if IS_CL1D_RF_MT6177L
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (21) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (17) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_MT6177M
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (30) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (0) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_TRINITYE1
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (14) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (13) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITYLE2
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (27) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (0) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_TRINITY2L
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (27) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (0) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#elif IS_CL1D_RF_COLUMBUSE1
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (14) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (13) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#endif
+#define CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE (CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE + CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE)//CL1D_RF_DEV_TX_PGA_TABLE_SIZE
+
+#define CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE (15) //CL1D_RF_DEV_TXDET_AGC_TABLE_SIZE
+#define CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS (2) //CL1D_RF_DEV_DET_FE_GAIN_STEPS
+
+
+#define CL1D_RF_IF_MAX_NUM (7)
+#define CL1D_RF_DET_PGA_GAIN_STEPS (5)
+
+#if IS_CL1D_RF_MT6177L
+#define CL1D_TX_LPF_NOMINAL_VALUE 172//for 77L
+#elif IS_CL1D_RF_MT6177M
+#define CL1D_TX_LPF_NOMINAL_VALUE 26//for 77M
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define CL1D_TX_LPF_NOMINAL_VALUE 172//Stub for TrinityE1. Will delete later.
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define CL1D_TX_LPF_NOMINAL_VALUE 172
+#endif
+
+#if IS_CL1D_RF_MT6177L
+#define CL1D_TX_RCF_NOMINAL_VALUE 16
+#elif IS_CL1D_RF_MT6177M
+#define CL1D_TX_RCF_NOMINAL_VALUE 17
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define CL1D_TX_RCF_NOMINAL_VALUE 16//Stub for TrinityE1. Will delete later.
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define CL1D_TX_RCF_NOMINAL_VALUE 16
+#endif
+
+#define CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX (14)
+
+typedef enum
+{
+ CL1D_RF_DEV_TIA0,
+ CL1D_RF_DEV_TIA1,
+ CL1D_RF_DEV_TIA_NUM
+}CL1D_RF_DEV_TIA_E;
+
+typedef struct
+{
+ kal_int16 i_part;
+ kal_int16 q_part;
+} CL1D_RF_TXDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXDFE_DC_COMP_T comp_tab[TX_DC_COMP_FC_MODE_NUM][TX_DC_COMP_PGA_SLICE_SET_NUM];
+} CL1D_RF_TXDFE_DC_COMP_TAB_T;
+
+typedef struct
+{
+ kal_int16 gain;
+ kal_int16 phase;
+} CL1D_RF_TXDFE_IQ_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXDFE_IQ_COMP_T comp_tab[TX_IQ_COMP_FC_MODE_NUM][TX_IQ_COMP_PGA_SLICE_SET_NUM];
+} CL1D_RF_TXDFE_IQ_COMP_TAB_T;
+
+#if defined(__MD93__)
+typedef struct{
+ kal_int32 gain_est_hw; /*> S-3.10, epsilon */
+ kal_int32 phase_est_hw;/*> S-4.10, -theta/2, in radians */
+ kal_int16 freq_dep_filt[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+#elif defined(__MD95__)
+typedef struct{
+ // kal_int32 gain_est_hw; /*> S-3.10, epsilon */
+ kal_int8 phase_est_hw;/*> S-4.10, -theta/2, in radians */
+ kal_int16 freq_dep_filt[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+#elif (defined(__MD97__) || defined(__MD97P__))
+typedef struct{
+ kal_int32 rx_fiiq_phase;/*> S-4.10, -theta/2, in radians */
+ kal_int16 rx_fdiq_coef[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+#endif
+
+typedef struct{
+ CL1D_RF_RXDFE_IRR_COMP_T hpm;
+ CL1D_RF_RXDFE_IRR_COMP_T lpm;
+} CL1D_RF_RXDFE_IRR_COMP_PER_PATH_T;
+
+
+typedef struct{
+ CL1D_RF_RXDFE_IRR_COMP_PER_PATH_T rx[RX_PATH_MAX_NUM];
+} CL1D_RF_RXDFE_IRR_COMP_PER_BAND_T;
+
+
+
+
+
+
+#if defined(__MD95__)
+typedef struct
+{
+ kal_uint8 cr_sel; ///< 0: C4R8, 1: C5R7, 2: C6R6, 3: NA
+ kal_uint8 tap_sel; ///< 0: 9 taps, 1: 14 taps
+ kal_uint32 filter_taps[CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX]; ///< s8
+}CL1D_RF_RXDFE_RFEQ_COMP_T;
+
+typedef struct{
+
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_hpm;
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_lpm;
+}CL1D_RXDFE_RFEQ_COMP_BW_T;
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+typedef struct
+{
+ kal_uint32 coef[CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX];
+ kal_uint32 power_saving_mode;
+ kal_uint32 ct_sel; ///< 0: C4R8, 1: C5R7, 2: C6R6, 3: NA
+}CL1D_RF_RXDFE_RFEQ_COMP_T;
+
+typedef struct{
+
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_hpm;
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_lpm;
+}CL1D_RXDFE_RFEQ_COMP_BW_T;
+#endif
+
+
+
+
+typedef struct
+{
+ kal_int16 dc_i; /*> RF DC:S5.0,resolution = 9mV. DFE DC: S0.14, fixed point value at Rx ADC, Rx ADC full swing is +/-1.62v */
+ kal_int16 dc_q; /*> RF DC:S5.0,resolution = 9mV. DFE DC: S0.14, fixed point value at Rx ADC, Rx ADC full swing is +/-1.62v */
+} CL1D_RF_RXDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DC_COMP_T hpm[CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS][CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS];
+ CL1D_RF_RXDFE_DC_COMP_T lpm[CL1D_RF_RXDFE_DC_TIA_GAIN_LPM_STEPS][CL1D_RF_RXDFE_DC_PGA_GAIN_LPM_STEPS];
+} CL1D_RF_RXDFE_DC_COMP_PER_PATH_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DC_COMP_PER_PATH_T rx[RX_PATH_MAX_NUM];
+} CL1D_RF_RXDFE_DC_COMP_PER_BAND_T;
+
+
+/* TRANSCEIVER PART */
+/** POC processing result structure definition*/
+#if IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+typedef struct
+{
+ kal_uint32 i_idx_opt; /*> optimum gate bias on I channel */
+ kal_uint32 q_idx_opt; /*> optimum gate bias on Q channel */
+}RX_IIP2_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int16 tx_abb_csel2;
+ kal_int16 tx_abb_csel1;
+ kal_int16 tx_abb_rsel;
+ //RCF use default value
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_2a;
+ kal_int16 tx_rcf_csel_1a;
+ kal_int16 tx_rcf_rsel;
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int32 tx_coarsedc_i;
+ kal_int32 tx_coarsedc_q;
+}TX_coarse_DC_RESULT_T;
+
+typedef struct
+{
+ kal_uint8 tx_pga_ctune;
+ kal_uint8 tx_mod_ctune;
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[RX_PATH_MAX_NUM];//main/div/sec
+#if IS_CL1D_RXDC_GXE_SUPPORT
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc_GXE[RX_PATH_MAX_NUM];
+#endif
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_T rx_iip2_cal_result[RX_PATH_MAX_NUM];//main/div/sec
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX ABB RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;//R use default value
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+ //kal_int16 tx_pga_phase_step;
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result[CL1D_RF_DET_PGA_GAIN_STEPS];
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_txlb_cal_result[CL1D_RF_DET_PGA_GAIN_STEPS];
+
+/* DET spare */
+ //DET_SPARES_T det_spares;
+
+/* MRX PGA&TZA Ctune */
+ kal_uint8 mrx_pga_ctune;//use default value
+ kal_uint8 mrx_tza_ctune;//use default value
+
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+
+#elif IS_CL1D_RF_TRINITYL
+typedef struct
+{
+ kal_uint32 i_idx_opt; /*> optimum gate bias on I channel */
+ kal_uint32 q_idx_opt; /*> optimum gate bias on Q channel */
+}RX_IIP2_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int16 tx_abb_csel2;
+ kal_int16 tx_abb_csel1;
+ kal_int16 tx_abb_rsel;
+ //RCF use default value
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_2a;
+ kal_int16 tx_rcf_csel_1a;
+ kal_int16 tx_rcf_rsel;
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int32 tx_coarsedc_i;
+ kal_int32 tx_coarsedc_q;
+}TX_coarse_DC_RESULT_T;
+
+typedef struct
+{
+ kal_uint8 tx_pga_ctune;
+ kal_uint8 tx_mod_ctune;
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[RX_PATH_MAX_NUM];//main/div/sec
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_T rx_iip2_cal_result[RX_PATH_MAX_NUM];//main/div/sec
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX ABB RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;//R use default value
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+ //kal_int16 tx_pga_phase_step;
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result[CL1D_RF_DET_PGA_GAIN_STEPS];
+
+/* DET spare */
+ //DET_SPARES_T det_spares;
+
+/* MRX PGA&TZA Ctune */
+ kal_uint8 mrx_pga_ctune;//use default value
+ kal_uint8 mrx_tza_ctune;//use default value
+
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+typedef struct
+{
+ kal_uint32 i_idx_opt; /*> optimum gate bias on I channel */
+ kal_uint32 q_idx_opt; /*> optimum gate bias on Q channel */
+}RX_IIP2_CAL_RESULT_CW_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint16 tx_abb_csel;
+ kal_uint16 tx_abb_rsel;
+ //RCF use default value
+ kal_uint16 tx_rcf_csel;
+ kal_uint16 tx_rcf_csel_1b;
+ kal_uint16 tx_rcf_csel_2a;
+ kal_uint16 tx_rcf_rsel;
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_int32 tx_coarsedc_i;
+ kal_int32 tx_coarsedc_q;
+}TX_coarse_DC_RESULT_T;
+
+typedef struct
+{
+ kal_uint8 tx_pga_ctune;
+ kal_uint8 tx_mod_ctune;
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoci_sign; /* MRX coarse DC offset I channel sign */
+ kal_uint32 mrx_cdcoci_mag; /* MRX coarse DC offset I channel magnitude */
+ kal_uint32 mrx_cdcocq_sign; /* MRX coarse DC offset Q channel sign */
+ kal_uint32 mrx_cdcocq_mag; /* MRX coarse DC offset Q channel magnitude */
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[3];//Edwin TBD
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_CW_T rx_iip2_cal_result[2];//Edwin TBD
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX ABB RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;//R use default value
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+ kal_int16 tx_pga_phase_step;//Edwin TBD, removed in Gen95
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result[4];//Edwin TBD
+
+/* DET spare */
+ DET_SPARES_T det_spares;//Edwin TBD, not sure if needed or not
+
+/* MRX PGA&TZA Ctune */
+ kal_uint8 mrx_pga_ctune;//use default value
+ kal_uint8 mrx_tza_ctune;//use default value
+
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+
+#else
+typedef struct
+{
+ kal_uint32 rxd_iip2_cw349; /* RX1 IIP2 Cal */
+ kal_uint32 rx_iip2_cw473; /* RX1 IIP2 Cal */
+ kal_uint32 rx_iip2_cw482; /* RX2 IIP2 Cal */
+ kal_uint32 rxd_iip2_cw350;
+}RX_IIP2_CAL_RESULT_CW_T;
+
+typedef struct
+{
+ kal_uint32 tx_lo_cw714; /* TX LO Cal */
+}TX_LO_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_rc_lpf_cw787; /* TX RC Cal */
+ kal_uint32 tx_rc_rcf_cw793; /* TX RC Cal */
+}TX_RC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_bal_cap_cw795; /* TX PGA Cap Tuning */
+ kal_uint32 tx_bal_cap_cw796; /* TX PGA Cap Tuning */
+}TX_CAP_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_cdcoc_cw807; /* DET coarse DCOC */
+ kal_uint32 tx_cdcoc_cw808; /* DET coarse DCOC */
+}DET_CDCOC_CAL_RESULT_T;
+
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10 */
+ kal_int16 phase_est; /*> S-4.10 */
+}DET_IQ_CAL_RESULT_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11 */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}DET_DC_CAL_RESULT_T;
+
+typedef struct
+{
+ kal_uint32 tx_det_cw817; /* Bit19-Bit12 Ncsel */
+}DET_SPARES_T;
+
+/** RXDC Table context */
+typedef struct
+{
+ kal_uint16 rxDcocI; /** S5.0,resolution = 9mV */
+ kal_uint16 rxDcocQ; /** S5.0,resolution = 9mV */
+}CL1D_RF_DEV_POC_RF_RX_DCOC_T; //CL1D_RF_DEV_RF_RX_DCOC_T
+
+typedef struct
+{
+ /** The estimate DC offset, TxPath:S0.14, Tx DAC full swing is +/-1.05v. DetPath:S0.11, det ADC full swing is +/-0.6v, 13MHz clock */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+ /** The estimate phase error, TxPath:S-4.10, -theta/2, in radians. DetPath:S-4.10, -theta/2, in radians */
+ kal_int16 phase_est;
+ /** The estimate gain error, TxPath:S-4.10, epsilon/2. DetPath:S-3.10, epsilon */
+ kal_int16 gain_est;
+}CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T; //CL1D_RF_DEV_IQ_DC_CALIB_PARM_T
+
+typedef struct
+{
+ kal_int16 pga_gain; /** TX_PGA relative gain with G0, 1/32dB unit */
+}CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T;
+
+/** TX and DET path IQ imbalance and DC POC result structure */
+typedef struct{
+ kal_int16 gain_est; /*> S-3.10, epsilon */
+ kal_int16 phase_est; /*> S-4.10, -theta/2, in radians */
+}CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T;
+
+typedef struct
+{
+ /** The estimate DC offset in S0.11, det ADC full swing is +/-0.6v, the clock is 13MHz */
+ kal_int16 dco_est_i;
+ kal_int16 dco_est_q;
+}CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct
+{
+/* RX IRR, config in RXDFE */
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_hpm[RX_PATH_MAX_NUM];
+ //CL1D_RF_DEV_DFE_RX_IRR_T rx_irr_lpm[RX_PATH_MAX_NUM];
+
+/* RX DC of DFE*/
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_hpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+ //CL1D_RF_DEV_DFE_RX_DC_T dfe_rx_dc_lpm[RX_PATH_MAX_NUM][CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX];
+
+/* RX DC of RF*/
+ CL1D_RF_DEV_DC_TBL_T rf_rx_dc[3];
+
+/* RX IIP2, config in RF */
+ RX_IIP2_CAL_RESULT_CW_T rx_iip2_cal_result;
+}RX_POC_TABLE_T;
+
+typedef struct
+{
+/* TX LO Cal, config in RF */
+ TX_LO_CAL_RESULT_T tx_lo_cal_result;
+
+/* TX RC, config in RF */
+ TX_RC_CAL_RESULT_T tx_rc_cal_result;
+
+/* TX IQDC, config in TXDFE */
+// CL1D_RF_DEV_POC_IQ_DC_CALIB_PARM_T tx_iq_dc_cal_result[MMRFC_C2K_POC_TX_PGA_SLICE_NUM+1];
+
+/* TX DNL */
+ CL1D_RF_DEV_POC_RF_TX_AGC_TABLE_T tx_dnl_cal_result[CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE];
+
+/* TX PGA Cap Tuning, config in RF */
+ TX_CAP_CAL_RESULT_T tx_cap_cal_result;
+
+/* TX PGA phase step */
+ kal_int16 tx_pga_phase_step;
+
+}TX_POC_TABLE_T;
+
+typedef struct
+{
+/* DET coarse DCOC, config in RF */
+ DET_CDCOC_CAL_RESULT_T det_cdcoc_cal_result;
+
+/* DET spare */
+ DET_SPARES_T det_spares;
+
+/* DET DNL, config in RF */
+ kal_int16 det_dnl_cal_result[CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE];
+
+/* DET IQ imbalance with Tx path forward signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T det_iq_fwd[CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS];
+
+/* DET fine DC with Tx path forward signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T det_dc_fwd[CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE];
+
+/* DET IQ imbalance with Tx path reverse signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_IQ_CAL_PARM_T det_iq_rev[CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS];
+
+/* DET fine DC with Tx path reverse signal, config in TXDFE */
+ CL1D_RF_DEV_POC_DET_DC_CAL_PARM_T det_dc_rev[CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE];
+}DET_POC_TABLE_T;
+
+typedef struct
+{
+ RX_POC_TABLE_T rx_poc_table;
+ TX_POC_TABLE_T tx_poc_table;
+ DET_POC_TABLE_T det_poc_table;
+}CL1D_RF_POC_DEV_FINAL_RESULT_T;
+#endif
+
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_COMP_T coef[CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+}CL1D_RF_TXK_DETDFE_EQLPF_CFG_T;
+
+#if defined(__MD95__)
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+#elif defined(__MD93__)
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain[CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+#elif (defined(__MD97__) || defined(__MD97P__))
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+#endif
+
+typedef struct
+{
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int32 dnl;
+ kal_int32 freq_dep_phase_est; ///< Valid for 2-point meas. for error handling
+}CL1D_RF_TXK_DETDFE_IQ_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_IQ_COMP_T per_fe_gain[CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_IQ_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_int32 dc_est_i; /*> S0.11, fixed point value at Det ADC, Det ADC full swing is +/-0.6v */
+ kal_int32 dc_est_q; /*> S0.11, fixed point value at Det ADC, Det ADC full swing is +/-0.6v */
+}CL1D_RF_TXK_DETDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_DC_COMP_T per_det_gain[CL1D_RF_TXK_DETDFE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T;
+
+#if IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+typedef struct
+{
+ kal_int32 pga_bias[TX_PGA_BIAS_SET_NUM];
+}CL1D_RF_POC_DEV_TX_PGA_BIAS_RESULT_T;
+#endif
+
+typedef struct{
+
+ /* NVRAM version number */
+#if defined(__MD95__)
+ kal_uint32 verno;
+#endif
+
+ /* RXDFE */
+ CL1D_RF_RXDFE_IRR_COMP_PER_BAND_T irr_comp;
+#if defined(__MD95__)
+#elif (defined(__MD97__) || defined(__MD97P__))
+#elif defined(__MD93__)
+ CL1D_RF_RXDFE_DC_COMP_PER_BAND_T dc_comp;
+#endif
+
+ /* TXDFE */
+ CL1D_RF_TXDFE_IQ_COMP_TAB_T tx_iq_comp;
+ CL1D_RF_TXDFE_DC_COMP_TAB_T tx_dc_comp;
+#if defined(__MD95__)
+ CL1D_RF_TXDFE_DC_COMP_TAB_T tx_coarse_dc_comp;
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+ CL1D_RF_TXDFE_DC_COMP_TAB_T tx_coarse_dc_comp;
+#endif
+
+ /* TXKDFE */
+ CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T txk_eqlpf_fwd_comp;
+ CL1D_RF_TXK_DETDFE_IQ_COMP_PER_BAND_T txk_iq_fwd_comp;
+#if IS_CL1D_RF_TRINITYLE2 || IS_CL1D_RF_TRINITY2L
+ CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T txk_dc_fwd_comp_txlb;
+#endif
+ CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T txk_dc_fwd_comp;
+
+ /* Transceiver */
+ CL1D_RF_POC_DEV_FINAL_RESULT_T poc_dev_fin;
+
+ /* PGA_BIAS */
+#if IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+ CL1D_RF_POC_DEV_TX_PGA_BIAS_RESULT_T tx_pga_bias_comp;
+#endif
+} CL1D_RF_POC_FINAL_T;
+
+#endif /* _CL1D_RF_POC_PUBLIC_H_ */
+#endif
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md97.h b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md97.h
new file mode 100644
index 0000000..63d7faf
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_poc_public_md97.h
@@ -0,0 +1,1016 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2017
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+*
+* FILE NAME :cl1_rf_poc_public.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#if defined (__C2K_RAT__) || defined(__CL1_TASK_ENABLE__)
+#ifndef _CL1D_RF_POC_PUBLIC_H_
+#define _CL1D_RF_POC_PUBLIC_H_
+
+#include "cl1d_rf_cid.h"
+#include "cl1d_rf_common_defs.h"
+//#include "mml1_rf_cal_interface.h"
+//#include "mml1_rf_cal_rf_interface_columbus.h"
+//#include "mml1_cdf_sku_mgr.h"
+
+/* TX DFE related */
+#define TX_DC_COMP_FC_MODE_NUM (1)
+#define TX_DC_COMP_PGA_SLICE_SET_NUM (4)
+#define TX_IQ_COMP_FC_MODE_NUM (1)
+#define TX_IQ_COMP_PGA_SLICE_SET_NUM (4)
+
+/* RX DFE related */
+#define RX_PATH_MAX_NUM (3)
+#define RX_POWER_MODE_MAX_NUM (2)
+#define RX_FD_FILT_TAPS_MAX_NUM (5) /*> maximum numbers of compensation filter taps */
+
+#define CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS (2)
+#define CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS (7)
+
+#define CL1D_RF_RXDFE_DC_TIA_GAIN_LPM_STEPS (1)
+#define CL1D_RF_RXDFE_DC_PGA_GAIN_LPM_STEPS (6)
+
+#define CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX (14)
+
+/* TXK DFE related */
+#define CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM (13)
+#define CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS (1)
+#define CL1D_RF_TXK_DETDFE_GAIN_STEPS (5)
+
+/* RX DEV related */
+#define CL1D_RF_DEV_POC_RXAGC_TABLE_MAX_INDEX (19) // CL1D_RF_DEV_RXAGC_TABLE_MAX_INDEX
+#define MMRFC_C2K_POC_TX_PGA_SLICE_NUM (7) // MMRFC_C2K_TX_PGA_SLICE_NUM
+#define CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE (14) //CL1D_RF_DEV_TX_PGA_A_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE (13) //CL1D_RF_DEV_TX_PGA_B_TABLE_SIZE
+#define CL1D_RF_DEV_POC_TX_PGA_TABLE_SIZE (CL1D_RF_DEV_POC_TX_PGA_A_TABLE_SIZE + CL1D_RF_DEV_POC_TX_PGA_B_TABLE_SIZE)//CL1D_RF_DEV_TX_PGA_TABLE_SIZE
+
+#define CL1D_RF_DEV_POC_TXDET_AGC_TABLE_SIZE (15) //CL1D_RF_DEV_TXDET_AGC_TABLE_SIZE
+#define CL1D_RF_DEV_POC_DET_FE_GAIN_STEPS (2) //CL1D_RF_DEV_DET_FE_GAIN_STEPS
+
+#define CL1D_RF_IF_MAX_NUM (7)
+#define CL1D_RF_IF_HPM_MAX_NUM (7)
+#define CL1D_RF_IF_LPM_MAX_NUM (6)
+
+#define CL1D_RF_DET_PGA_GAIN_STEPS (5)
+
+#define CL1D_TX_LPF_NOMINAL_VALUE (172)
+#define CL1D_TX_RCF_NOMINAL_VALUE (16)
+
+typedef enum
+{
+ CL1D_RF_DEV_TIA0,
+ CL1D_RF_DEV_TIA_NUM
+}CL1D_RF_DEV_TIA_E;
+#if 1
+typedef struct
+{
+ kal_int16 i_part;
+ kal_int16 q_part;
+} CL1D_RF_TXDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXDFE_DC_COMP_T comp_tab[TX_DC_COMP_FC_MODE_NUM][TX_DC_COMP_PGA_SLICE_SET_NUM];
+} CL1D_RF_TXDFE_DC_COMP_TAB_T;
+
+typedef struct
+{
+ kal_int16 gain;
+ kal_int16 phase;
+} CL1D_RF_TXDFE_IQ_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXDFE_IQ_COMP_T comp_tab[TX_IQ_COMP_FC_MODE_NUM][TX_IQ_COMP_PGA_SLICE_SET_NUM];
+} CL1D_RF_TXDFE_IQ_COMP_TAB_T;
+
+typedef struct{
+ kal_int32 rx_fiiq_phase;/*> S-4.10, -theta/2, in radians */
+ kal_int16 rx_fdiq_coef[RX_FD_FILT_TAPS_MAX_NUM]; /*> Valid for 2-point meas. */
+} CL1D_RF_RXDFE_IRR_COMP_T;
+
+typedef struct{
+ CL1D_RF_RXDFE_IRR_COMP_T hpm;
+ CL1D_RF_RXDFE_IRR_COMP_T lpm;
+} CL1D_RF_RXDFE_IRR_COMP_PER_PATH_T;
+
+typedef struct{
+ CL1D_RF_RXDFE_IRR_COMP_PER_PATH_T rx[RX_PATH_MAX_NUM];
+} CL1D_RF_RXDFE_IRR_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_uint32 coef[CL1D_RF_RXDFE_RFEQ_TAPS_NUM_MAX];
+ kal_uint32 power_saving_mode;
+ kal_uint32 ct_sel; ///< 0: C4R8, 1: C5R7, 2: C6R6, 3: NA
+}CL1D_RF_RXDFE_RFEQ_COMP_T;
+
+typedef struct {
+ kal_uint32 dc; /*RF DC offset in S5.0*/ /*digital DC offset in S0.14*/
+}CL1D_RF_DEV_DC_T;
+
+typedef struct {
+ CL1D_RF_DEV_DC_T DC_DATA_I_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_I_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_HPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+ CL1D_RF_DEV_DC_T DC_DATA_Q_LPM[CL1D_RF_DEV_TIA_NUM][CL1D_RF_IF_MAX_NUM];
+} CL1D_RF_DEV_DC_TBL_T;
+
+typedef struct{
+
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_hpm;
+ CL1D_RF_RXDFE_RFEQ_COMP_T rfeq_lpm;
+}CL1D_RXDFE_RFEQ_COMP_BW_T;
+
+typedef struct
+{
+ kal_int16 dc_i; /*> RF DC:S5.0,resolution = 9mV. DFE DC: S0.14, fixed point value at Rx ADC, Rx ADC full swing is +/-1.62v */
+ kal_int16 dc_q; /*> RF DC:S5.0,resolution = 9mV. DFE DC: S0.14, fixed point value at Rx ADC, Rx ADC full swing is +/-1.62v */
+} CL1D_RF_RXDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DC_COMP_T hpm[CL1D_RF_RXDFE_DC_TIA_GAIN_HPM_STEPS][CL1D_RF_RXDFE_DC_PGA_GAIN_HPM_STEPS];
+ CL1D_RF_RXDFE_DC_COMP_T lpm[CL1D_RF_RXDFE_DC_TIA_GAIN_LPM_STEPS][CL1D_RF_RXDFE_DC_PGA_GAIN_LPM_STEPS];
+} CL1D_RF_RXDFE_DC_COMP_PER_PATH_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DC_COMP_PER_PATH_T rx[RX_PATH_MAX_NUM];
+} CL1D_RF_RXDFE_DC_COMP_PER_BAND_T;
+#endif
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif IS_CL1D_RF_TRINITYL
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#if 1
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_COMP_T coef[CL1D_RF_TXK_DETDFE_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+}CL1D_RF_TXK_DETDFE_EQLPF_CFG_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_EQLPF_CFG_T per_fe_gain;
+}CL1D_RF_TXK_DETDFE_EQLPF_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int32 dnl;
+ kal_int32 freq_dep_phase_est; ///< Valid for 2-point meas. for error handling
+}CL1D_RF_TXK_DETDFE_IQ_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_IQ_COMP_T per_fe_gain[CL1D_RF_TXK_DETDFE_FE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_IQ_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_int32 dc_est_i; /*> S0.11, fixed point value at Det ADC, Det ADC full swing is +/-0.6v */
+ kal_int32 dc_est_q; /*> S0.11, fixed point value at Det ADC, Det ADC full swing is +/-0.6v */
+}CL1D_RF_TXK_DETDFE_DC_COMP_T;
+
+typedef struct
+{
+ CL1D_RF_TXK_DETDFE_DC_COMP_T per_det_gain[CL1D_RF_TXK_DETDFE_GAIN_STEPS];
+}CL1D_RF_TXK_DETDFE_DC_COMP_PER_BAND_T;
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#endif /* _CL1D_RF_POC_PUBLIC_H_ */
+#endif
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_public.h b/mcu/interface/l1/cl1/rfd/cl1_rf_public.h
new file mode 100644
index 0000000..1ed94cc
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_public.h
@@ -0,0 +1,1776 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1_rf_public.h
+ *
+ * Project:
+ * --------
+ * 93
+ *
+ * Description:
+ * ------------
+ * RF public defines and types
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#ifndef _CL1_RF_PUBLIC_H_
+#define _CL1_RF_PUBLIC_H_
+
+#include "c2k_defs.h"
+#include "cl1d_rf_common_defs.h"
+#include "cl1_rf_tas_public.h"
+#include "cl1_rf_elna_public.h"
+#include "cl1_rf_poc_public.h"
+#include "mml1_rf_public.h"
+#include "cl1_rf_dat_public.h"
+#include "mml1_fe_public.h"
+#include "cl1_rf_tas_public.h"
+
+#define C2K_USID_NULL 0x0000
+#define C2K_USID_REG_W 0x0001
+#define C2K_USID_REG_W_EXT 0x0002
+
+#define C2K_REG_0_W 0x0001
+#define C2K_REG_W 0x0002
+#define C2K_REG_W_EXT_1ST 0x0003
+#define C2K_REG_W_EXT_BYTE 0x0004
+#define C2K_REG_W_EXT_END 0x0005
+#define C2K_REG_W_EXT_ONLY_ONEBYTE 0x0006
+#define C2K_REG_W_INVALID 0x0008
+
+/* port select */
+#define C2K_MIPI_PORT0 0x0000
+#define C2K_MIPI_PORT1 0x0001
+#define C2K_MIPI_PORT2 0x0002
+#define C2K_MIPI_PORT3 0x0003
+#define C2K_MIPI_PORT4 0x0004
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define C2K_MIPI_PORT_MAX (C2K_MIPI_PORT4+1)
+
+/* event type */
+#define C2K_MIPI_TRX_ON 0x0001
+#define C2K_MIPI_TRX_OFF 0x0002
+#define C2K_MIPI_TPC_SET 0x0003
+#define C2K_MIPI_TX_GATE_ON 0x0004
+#define C2K_MIPI_TX_GATE_OFF 0x0005
+#define C2K_MIPI_RX_DIV_ON 0x0006
+#define C2K_MIPI_RX_DIV_OFF 0x0007
+#define C2K_MIPI_ETM_TX_ON 0x0008
+#define C2K_MIPI_ETM_TX_OFF 0x0009
+#define C2K_MIPI_ETM_TPC_SET 0x000A
+#define C2K_MIPI_ELNA_ON 0x000B
+#define C2K_MIPI_ELNA_BYPASS 0x000C
+#define C2K_MIPI_ELNA_OFF 0x000D
+#define C2K_MIPI_EVENT_NULL 0x1000
+
+/* element type */
+#define C2K_MIPI_NULL 0x0000
+#define C2K_MIPI_ASM 0x0001
+#define C2K_MIPI_ANT 0x0002
+#define C2K_MIPI_PA 0x0003
+#define C2K_MIPI_PA_SEC 0x0004
+#define C2K_MIPI_TAS 0x0005
+#define C2K_MIPI_TUNER 0x0006
+#define C2K_MIPI_ETM 0x0007
+#define C2K_MIPI_ETM_SEC 0x0008
+/*ELNA MIPI element type */
+#define C2K_MIPI_ELNA 0x0009
+#define C2K_MIPI_DAT 0x000A
+#define C2K_MIPI_END_PATTERN 0xFFFF
+
+/* TPC PA SECTION DATA PATTERN */
+#define C2K_MIPI_PA_SECTION_DATA0 0x0
+#define C2K_MIPI_PA_SECTION_DATA1 0x1
+#define C2K_MIPI_PA_SECTION_DATA2 0x2
+#define C2K_MIPI_PA_SECTION_DATA3 0x3
+#define C2K_MIPI_PA_SECTION_DATA4 0x4
+
+/* Dummy PA USID and register address */
+#define C2K_MIPI_PA_SECTION_USID 0x0
+#define C2K_MIPI_PA_SECTION_ADDRESS 0x0
+
+/* TPC ETM SECTION DATA PATTERN */
+#define C2K_MIPI_ETM_SECTION_DATA0 0x0
+#define C2K_MIPI_ETM_SECTION_DATA1 0x1
+#define C2K_MIPI_ETM_SECTION_DATA2 0x2
+#define C2K_MIPI_ETM_SECTION_DATA3 0x3
+#define C2K_MIPI_ETM_SECTION_DATA4 0x4
+
+/* Dummy ETM USID and register address */
+#define C2K_MIPI_ETM_SECTION_USID 0x0
+#define C2K_MIPI_ETM_SECTION_ADDRESS 0x0
+
+
+#define C2K_MIPI_SUBBAND_NUM 5
+
+#define M_US(x) x
+
+
+/*************** RF Cust Data Dimentions ***************/
+#define RF_CUST_SUPPORT_BAND_MAX_NUM 5
+#define MIPI_TPC_OCT_NUM 8
+#define RF_ELNA_MAX_NUM 10
+
+/*Temp: 8 */
+#define CL1D_RF_NUM_TEMP_CALIBR 8
+#define CL1D_RF_NUM_TEMP_CALIBR_D (2*CL1D_RF_NUM_TEMP_CALIBR-1)
+/* Freq: 16 */
+#define CL1D_RF_NUM_FREQ_CALIBR 16
+/*Pa Gain:8 */
+#define CL1D_RF_NUM_TX_PA_GAIN_CALIBR 8
+
+#define TX_POWER_OFFSET_TABLE_ITEM_NUM 16
+
+/*SAR and SWTP table num - start */
+#if defined(__MD93__) || defined(__MD95__)
+#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
+#define SAR_TX_POWER_OFFSET_TABLE_NUM 9
+#elif defined(__TX_POWER_OFFSET_SUPPORT__)
+#define SAR_TX_POWER_OFFSET_TABLE_NUM 1
+#else
+#define SAR_TX_POWER_OFFSET_TABLE_NUM 9
+#endif
+#endif
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define SAR_TX_POWER_OFFSET_TABLE_NUM 20
+#define SWTP_TX_POWER_OFFSET_TABLE_NUM 1
+#endif
+/*SAR and SWTP table num - end */
+
+#define CL1D_RF_NUM_RAMP_LEVEL 16
+#define SAR_FREQ_CALIBR_NUM 16
+
+/*************** RF Cust Data Dimentions ***************/
+#define CL1D_RF_SUB_CLASS_ALL_SUPPORTED 0xffff0000
+#define CL1D_RF_SUB_CLASS_NONE_SUPPORTED 0x00000000
+
+/***************** RF cust params *******************/
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_COLUMBUSE1//temp for Gen97 warning
+#define PMHB1 (0)
+#define PMHB2 (1)
+#define PMHB3 (2)
+#define PMHB4 (3)
+#define PMHB5 (4)
+#define PMHB6 (5)
+#define PMHB7 (6)
+#define PMHB8 (7)
+#define PMHB9 (8)
+#define PMHB10 (9)
+#define PUHBLAA1 (10)
+#define PUHBLAA2 (11)
+#define PLB1 (12)
+#define PLB2 (13)
+#define PLB3 (14)
+#define PLB4 (15)
+#define PLB5 (16)
+#define PLB6 (17)
+#define DMHB1 PMHB1
+#define DMHB2 PMHB2
+#define DMHB3 PMHB3
+#define DMHB4 PMHB4
+#define DMHB5 PMHB5
+#define DMHB6 PMHB6
+#define DMHB7 PMHB7
+#define DMHB8 PMHB8
+#define DMHB9 PMHB9
+#define DMHB10 PMHB10
+#define DUHBLAA1 PUHBLAA1
+#define DUHBLAA2 PUHBLAA2
+#define DLB1 PLB1
+#define DLB2 PLB2
+#define DLB3 PLB3
+#define DLB4 PLB4
+#define PRXMAX PLB6
+#define DRXMAX DLB4
+
+#define TX0_OFF (0)
+#define TX0_LB1 (1)
+#define TX0_LM1 (2)
+#define TX0_LM2 (3)
+#define TX0_MB1 (4)
+#define TX0_HB1 (5)
+#define TX0_HB2 (6)
+#define TX0_ULB (7)
+#define TX0_LOAD (8)
+#define TX1_OFF (9)
+#define TX1_LB1 (10)
+#define TX1_LM1 (11)
+#define TX1_LM2 (12)
+#define TX1_MB1 (13)
+#define TX1_HB1 (14)
+#define TX1_HB2 (15)
+#define TX1_ULB (16)
+#define TX1_LOAD (17)
+#define TX2_OFF (18)
+#define TX2_LB1 (19)
+#define TX2_LM1 (20)
+#define TX2_LM2 (21)
+#define TX2_MB1 (22)
+#define TX2_HB1 (23)
+#define TX2_HB2 (24)
+#define TX2_ULB (25)
+#define TX2_LOAD (26)
+#define TXMAX_RF0 TX0_LOAD
+#define TXMAX_RF1 TX0_LOAD
+#define TXMAX_RF2 TX0_LOAD
+#define TXMAX_PORT_NUM (TX0_LOAD + 1)
+
+#elif IS_CL1D_RF_TRINITYL || IS_CL1D_RF_TRINITY2L || IS_CL1D_RF_TRINITYLE2
+#define PMHB1 (0)
+#define PMHB2 (1)
+#define PMHB3 (2)
+#define PMHB4 (3)
+#define PMHB5 (4)
+#define PMHB6 (5)
+#define PMHB7 (6)
+#define PMHB8 (7)
+#define PLB1 (12)
+#define PLB2 (13)
+#define PLB3 (14)
+#define PLB4 (15)
+#define PLB5 (16)
+#define PLAAUHB1 (10)
+#define PLAAUHB2 (11)
+#define DMHB1 PMHB1
+#define DMHB2 PMHB2
+#define DMHB3 PMHB3
+#define DMHB4 PMHB4
+#define DMHB5 PMHB5
+#define DMHB6 PMHB6
+#define DMHB7 PMHB7
+#define DMHB8 PMHB8
+#define DLB1 PLB1
+#define DLB2 PLB2
+#define DLB3 PLB3
+#define DLB4 PLB4
+#define DLB5 PLB5
+#define DLAAUHB1 PLAAUHB1
+#define DLAAUHB2 PLAAUHB2
+#define PRXMAX_TRINITYL 15
+#define DRXMAX_TRINITYL 15
+
+#define PRXMAX PRXMAX_TRINITYL
+#define DRXMAX DRXMAX_TRINITYL
+
+#define TX0_OFF (0)
+#define TX0_LB1 (1)
+#define TX0_LB2 (9)
+#define TX0_MB1 (4)
+#define TX0_MB2 (10)
+#define TX0_HB1 (5)
+#define TX0_HB_UHB1 (11)
+#define TX0_HB_UHB2 (12)
+#define TX0_LOAD (12) //max tx port num defined in mmrf
+#define TXMAX_PORT_NUM (TX0_LOAD + 1)
+
+#define TX1_OFF (TXMAX_PORT_NUM+TX0_OFF)
+#define TX1_LB1 (TXMAX_PORT_NUM+TX0_LB1)
+#define TX1_MB1 (TXMAX_PORT_NUM+TX0_MB1)
+#define TX1_MB2 (TXMAX_PORT_NUM+TX0_MB2)
+#define TX1_HB_UHB1 (TXMAX_PORT_NUM+TX0_HB_UHB1)
+#define TX1_HB_UHB2 (TXMAX_PORT_NUM+TX0_HB_UHB2)
+
+#define TX1_LOAD (TXMAX_PORT_NUM+TX0_LOAD)
+#define TXMAX_RF0 TX0_LOAD
+#define TXMAX_RF1 TX0_LOAD
+#define TXMAX_RF2 TX0_LOAD
+
+
+#else
+#define PRX1 (0)
+#define PRX2 (1)
+#define PRX3 (2)
+#define PRX4 (3)
+#define PRX5 (4)
+#define PRX6 (5)
+#define PRX7 (6)
+#define PRX8 (7)
+#define PRX9 (8)
+#define PRX10 (9)
+#define PRX11 (10)
+#define PRX12 (11)
+#define PRX13 (12)
+#define PRX14 (13)
+#define PRX15 (14)
+#define PRX16 (15)
+#define PRX17 (16)
+#define PRX18 (17)
+#define PRX19 (18)
+#define PRX20 (19)
+#define PRX21 (20)
+#define PRX22 (21)
+#define DRX1 PRX1
+#define DRX2 PRX2
+#define DRX3 PRX3
+#define DRX4 PRX4
+#define DRX5 PRX5
+#define DRX6 PRX6
+#define DRX7 PRX7
+#define DRX8 PRX8
+#define DRX9 PRX9
+#define DRX10 PRX10
+#define DRX11 PRX11
+#define DRX12 PRX12
+#define DRX13 PRX13
+#define DRX14 PRX14
+#define DRX15 PRX15
+#define DRX16 PRX16
+#define DRX17 PRX17
+#define DRX18 PRX18
+#define DRX19 PRX19
+#define DRX20 PRX20
+#define DRX21 PRX21
+#define DRX22 PRX22
+#define PRXMAX_RF1 PRX11
+#define PRXMAX_RF2 PRX22
+#define DRXMAX_RF1 DRX11
+#define DRXMAX_RF2 DRX22
+#define PRXMAX PRX22
+#define DRXMAX DRX22
+
+#define TX0_UHB (0)
+#define TX0_HB1 (1)
+#define TX0_HB2 (2)
+#define TX0_MB1 (3)
+#define TX0_MB2 (4)
+#define TX0_MB3 (5)
+#define TX0_LB1 (6)
+#define TX0_LB2 (7)
+#define TX0_LB3 (8)
+#define TX0_LB4 (9)
+#define TX1_UHB (10)
+#define TX1_HB (11)
+#define TX1_MB (12)
+#define TX1_LB1 (13)
+#define TX1_LB2 (14)
+#define TXO1 TX0_HB1
+#define TXO2 TX0_MB1
+#define TXO3 TX0_MB2
+#define TXO4 TX0_LB1
+#define TXO5 TX0_LB2
+#define TXMAX_RF1 TX0_LB4
+#define TXMAX_RF2 TX1_LB2
+#endif
+
+#define C2K_TX_DET_IO_DET0 (0)
+#define C2K_TX_DET_IO_DET1 (1)
+
+
+#define NONE_USED_BAND (0xff)
+
+#define NONE_USED_PRX PRXMAX
+#define NONE_USED_DRX DRXMAX
+#define TX_IO_NULL TXMAX_RF1
+#define C2K_TX_DET_IO_NULL C2K_TX_DET_IO_DET0
+
+/*** TAS 2.0 ***/
+#define C2K_TAS_MAX_CAT_A_ROUTE_NUM (4)
+#define C2K_TAS_MAX_CAT_B_ROUTE_NUM (4)
+#define C2K_TAS_MAX_CAT_C_ROUTE_NUM (4)
+#define C2K_TAS_MAX_FE_ROUTE_NUM (5)
+#define C2K_TAS_MAX_STATE_NUM (8)
+#define C2K_TUNER_FE_MAX (8)
+
+
+typedef enum
+{
+ CL1D_RF_TX_POWER_BACK_OFF_HIGH_TEMP,
+ CL1D_RF_TX_POWER_BACK_OFF_LOW_TEMP,
+ CL1D_RF_TX_POWER_BACK_OFF_TEMP_NUM
+}CL1D_RF_TX_POWER_BAK_OFF_TEMP_E;
+
+/** C2K PA control type enumeration */
+typedef enum
+{
+ CL1D_RF_PA_BPI_TYPE=0,
+ CL1D_RF_PA_MIPI_TYPE,
+ CL1D_RF_PA_TYPE_NUM
+}CL1D_RF_PA_TYPE_E;
+
+/** C2K RAT type enumeration */
+typedef enum
+{
+ CL1D_RF_RAT_1XRTT = 0,
+ CL1D_RF_RAT_EVDO = 1,
+ CL1D_RF_RAT_NUM = 2,
+ CL1D_RF_RAT_NULL = CL1D_RF_RAT_NUM,
+} CL1D_RF_RAT_TYPE_E;
+
+typedef enum
+{
+ C2K_DC2DC =0,
+ C2K_PMIC =VPA_SOURCE_HW_PMIC,
+ C2K_BATT,
+ C2K_ETM,
+ C2K_HPUE =VPA_SOURCE_HW_EXT_VPA
+} CL1D_RF_PA_VDD_SRC_E;
+
+typedef enum
+{
+ _IDX = 1,
+ BAND_A_IDX = 1,
+ BAND_B_IDX = 2,
+ BAND_C_IDX = 3,
+ BAND_D_IDX = 4,
+ BAND_E_IDX = 5,
+ MAX_BAND_NUM = 5,
+
+ Route0_IDX = 1,
+ Route1_IDX = 2,
+ Route2_IDX = 3,
+ Route3_IDX = 4,
+ MAX_Route_NUM = 4,
+
+ DAT_CAT_A_Route0_IDX = 1,
+ DAT_CAT_A_Route1_IDX = 2,
+ DAT_CAT_A_Route2_IDX = 3,
+ DAT_CAT_A_Route3_IDX = 4,
+ DAT_CAT_A_Route4_IDX = 5,
+ DAT_CAT_A_Route5_IDX = 6,
+ DAT_CAT_A_Route6_IDX = 7,
+ DAT_CAT_A_Route7_IDX = 8,
+ DAT_CAT_A_Route8_IDX = 9,
+ DAT_CAT_A_Route9_IDX = 10,
+ MAX_DAT_CAT_A_Route_NUM = 10,
+
+ DAT_CAT_B_Route0_IDX = 1,
+ DAT_CAT_B_Route1_IDX = 2,
+ DAT_CAT_B_Route2_IDX = 3,
+ DAT_CAT_B_Route3_IDX = 4,
+ DAT_CAT_B_Route4_IDX = 5,
+ DAT_CAT_B_Route5_IDX = 6,
+ DAT_CAT_B_Route6_IDX = 7,
+ DAT_CAT_B_Route7_IDX = 8,
+ DAT_CAT_B_Route8_IDX = 9,
+ DAT_CAT_B_Route9_IDX = 10,
+ DAT_CAT_B_Route10_IDX = 11,
+ DAT_CAT_B_Route11_IDX = 12,
+ DAT_CAT_B_Route12_IDX = 13,
+ DAT_CAT_B_Route13_IDX = 14,
+ DAT_CAT_B_Route14_IDX = 15,
+ DAT_CAT_B_Route15_IDX = 16,
+ DAT_CAT_B_Route16_IDX = 17,
+ DAT_CAT_B_Route17_IDX = 18,
+ DAT_CAT_B_Route18_IDX = 19,
+ DAT_CAT_B_Route19_IDX = 20,
+ DAT_CAT_B_Route20_IDX = 21,
+ DAT_CAT_B_Route21_IDX = 22,
+ DAT_CAT_B_Route22_IDX = 23,
+ DAT_CAT_B_Route23_IDX = 24,
+ DAT_CAT_B_Route24_IDX = 25,
+ DAT_CAT_B_Route25_IDX = 26,
+ DAT_CAT_B_Route26_IDX = 27,
+ DAT_CAT_B_Route27_IDX = 28,
+ DAT_CAT_B_Route28_IDX = 29,
+ DAT_CAT_B_Route29_IDX = 30,
+ DAT_CAT_B_Route30_IDX = 31,
+ DAT_CAT_B_Route31_IDX = 32,
+ DAT_CAT_B_Route32_IDX = 33,
+ DAT_CAT_B_Route33_IDX = 34,
+ DAT_CAT_B_Route34_IDX = 35,
+ DAT_CAT_B_Route35_IDX = 36,
+ DAT_CAT_B_Route36_IDX = 37,
+ DAT_CAT_B_Route37_IDX = 38,
+ DAT_CAT_B_Route38_IDX = 39,
+ DAT_CAT_B_Route39_IDX = 40,
+ MAX_DAT_CAT_B_Route_NUM = 40,
+
+ ELNA1_IDX = 1,
+ ELNA2_IDX = 2,
+ ELNA3_IDX = 3,
+ ELNA4_IDX = 4,
+ ELNA5_IDX = 5,
+ ELNA6_IDX = 6,
+ ELNA7_IDX = 7,
+ ELNA8_IDX = 8,
+ ELNA9_IDX = 9,
+ ELNA10_IDX = 10,
+ MAX_ELNA_NUM = 10
+} CL1D_RF_NV_ITEM_INDEX_T;
+
+/*ELNA mode */
+typedef enum{
+ C2K_ELNA_ALWAYS_ON,
+ C2K_ELNA_ALWAYS_ON_2ND_SAW,
+ C2K_ELNA_BYPASS,
+ C2K_ELNA_BYPASS_2ND_SAW,
+ C2K_ELNA_OFF,
+ C2K_ELNA_MODE_NUM_MAX,
+ C2k_ELNA_ILLEGAL
+}MIPI_ELNA_CATEGORY_E;
+#if (defined __MD95__)
+typedef enum{
+ CL1D_ELNA_NONE,
+ CL1D_18dB_BYPASS_LOW_TX_ISO,
+ CL1D_18dB_BYPASS_HIGH_TX_ISO,
+ CL1D_18dB_BYPASS_LOW_TX_ISO_R_MATCHING,
+ CL1D_13P5dB_BYPASS_LOW_TX_ISO,
+ CL1D_13P5dB_BYPASS_HIGH_TX_ISO,
+ CL1D_13P5dB_BYPASS_LOW_TX_ISO_R_MATCHING,
+ CL1D_13P5dB_ALWAYS_ON_LOW_TX_ISO,
+ CL1D_13P5dB_ALWAYS_ON_HIGH_TX_ISO,
+ CL1D_ELNA_MODE_NUM,
+ CL1D_ELNA_MODE_ILLEGAL=CL1D_ELNA_MODE_NUM
+}CL1D_ELNA_MODE_E;
+#else
+typedef enum{
+ CL1D_ELNA_NONE,
+ CL1D_ELNA_ALWAYS_ON,
+ CL1D_ELNA_RUNTIME_CHANGE,
+ CL1D_ELNA_MODE_NUM,
+ CL1D_ELNA_MODE_ILLEGAL=CL1D_ELNA_MODE_NUM
+}CL1D_ELNA_MODE_E;
+#endif
+typedef enum{
+ C2K_ELNA_ON_INTER,
+ C2K_ELNA_BYPASS_INTER,
+ C2K_ELNA_OFF_INTER,
+ C2K_ELNA_EVENT_TYPE_MAX_NUM
+}MIPI_ELNA_EVENT_TYPE_E;
+
+
+
+typedef struct
+{
+ kal_bool is_supported;
+ SysCdmaBandT band_class;
+ kal_uint32 sub_class;
+} CL1D_RF_CUST_BAND_SUPPORT_T;
+ typedef struct
+{
+ kal_int16 pa_setting_time;
+} CL1D_RF_CUST_PA_TIMING_T;
+#if defined(__MD93__) || defined(__MD95__)
+ typedef struct
+ {
+ /* Band Class Supported */
+ CL1D_RF_CUST_BAND_SUPPORT_T band_support[RF_CUST_SUPPORT_BAND_MAX_NUM];/*5bands: A,B,C,D,E */
+ /* PA control timing */
+ CL1D_RF_CUST_PA_TIMING_T pa_timing;
+ /* PA VDD selection*/
+ CL1D_RF_PA_VDD_SRC_E pa_vdd_src_sel[RF_CUST_SUPPORT_BAND_MAX_NUM];
+
+ /* RX LNA port selection */
+ kal_uint8 rx_lna_port_sel[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ /* RX Diversity LNA port selection */
+ kal_uint8 rxd_lna_port_sel[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ /* TX LNA port selection */
+ kal_uint8 tx_lna_port_sel[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ /* DET LNA port selection */
+ kal_uint8 det_lna_port_sel[RF_CUST_SUPPORT_BAND_MAX_NUM];
+
+ /* RX Diversity enable */
+ kal_bool rx_diversity_enable[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ /* RX Diversity enable for test */
+ kal_bool rx_diversity_only_test_enable[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ /* PA control by mipi or bpi */
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ CL1D_RF_PA_TYPE_E pa_control_sel[RF_CUST_SUPPORT_BAND_MAX_NUM];
+#endif
+ } CL1D_RF_CUST_PARAM_T;
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+typedef struct
+{
+ /* Band Class Supported */
+ CL1D_RF_CUST_BAND_SUPPORT_T band_support[RF_CUST_SUPPORT_BAND_MAX_NUM];/*5bands: A,B,C,D,E */
+ /* RX Diversity enable */
+ kal_bool rx_diversity_enable[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ /* RX Diversity enable for test */
+ kal_bool rx_diversity_only_test_enable[RF_CUST_SUPPORT_BAND_MAX_NUM];
+} CL1D_RF_CUST_PARAM_T;
+#endif
+
+/***************** BPI *******************/
+typedef struct{
+ /*BPI Data*/
+ kal_uint32 pdata_pr1;
+ kal_uint32 pdata_pr2;
+ kal_uint32 pdata_pr2b;
+ kal_uint32 pdata_pr3;
+ kal_uint32 pdata_pr3a;
+
+ kal_uint32 pdata_pt1;
+ kal_uint32 pdata_pt2;
+ kal_uint32 pdata_pt2b;
+ kal_uint32 pdata_pt3;
+ kal_uint32 pdata_pt3a;
+
+ kal_uint32 pdata_rxd_pr1;
+ kal_uint32 pdata_rxd_pr2;
+ kal_uint32 pdata_rxd_pr2b;
+ kal_uint32 pdata_rxd_pr3;
+ kal_uint32 pdata_rxd_pr3a;
+
+ kal_uint32 pdata_ptg1;
+ kal_uint32 pdata_ptg2;
+ kal_uint32 pdata_ptg2b;
+ kal_uint32 pdata_ptg3;
+ kal_uint32 pdata_ptg3a;
+
+}CL1D_RF_CUST_BPI_DATA_CFG_T;
+typedef struct{
+ /*RX */
+ kal_int16 tc_pr1;
+ kal_int16 tc_pr2;
+ kal_int16 tc_pr2b;
+ kal_int16 tc_pr3;
+ kal_int16 tc_pr3a;
+
+ /*RXD */
+ kal_int16 tc_rxd_pr1;
+ kal_int16 tc_rxd_pr2;
+ kal_int16 tc_rxd_pr2b;
+ kal_int16 tc_rxd_pr3;
+ kal_int16 tc_rxd_pr3a;
+
+ /*TX */
+ kal_int16 tc_pt1;
+ kal_int16 tc_pt2;
+ kal_int16 tc_pt2b;
+ kal_int16 tc_pt3;
+ kal_int16 tc_pt3a;
+
+ /*TX GATE */
+ kal_int16 tc_ptg1;
+ kal_int16 tc_ptg2;
+ kal_int16 tc_ptg2b;
+ kal_int16 tc_ptg3;
+ kal_int16 tc_ptg3a;
+
+}CL1D_RF_CUST_BPI_TIMING_CFG_T;
+
+typedef struct
+{
+ CL1D_RF_CUST_BPI_DATA_CFG_T bpi_data;
+ CL1D_RF_CUST_BPI_TIMING_CFG_T bpi_timing;
+}CL1D_RF_CUST_BPI_CFG_T;
+
+
+
+/***************** TAS *******************/
+#define C2K_MIPI_TAS_EVENT_NUM (10)
+#define C2K_MIPI_TAS_DATA_NUM (20)
+#define C2K_MIPI_TAS_ROUTE_NUM (4)
+#define C2K_MIPI_TUNER_EVENT_NUM (8+1)
+#define C2K_MIPI_TUNER_DATA_NUM (8+1)
+#define C2K_MIPI_TUNER_ROUTE_NUM (8)
+/*DAT*/
+#define C2K_DAT_FE_NULL (255)
+#define C2K_DAT_MIPI_TABLE_NULL (255)
+#define C2K_DAT_MAX_CAT_A_ROUTE_NUM 10
+#define C2K_DAT_MAX_CAT_B_ROUTE_NUM 40
+#define C2K_DAT_NO_SPLIT_BAND (0xFF)
+#define C2K_DAT_MAX_STATE_NUM (8)
+#define C2K_DAT_MAX_CAT_NUM (2)
+#define C2K_MIPI_DAT_EVENT_NUM (8)
+#define C2K_MIPI_DAT_DATA_NUM (20)
+#define C2K_ANT_TUNER_SPLIT_PART_MAX (5)
+
+/*match to TAS big switch *///0,1,2,3
+/*ST*/
+typedef enum
+{
+ TAS2_IDX_STATE0 = 0,
+ TAS2_IDX_STATE1,
+ TAS2_IDX_STATE2,
+ TAS2_IDX_STATE3,
+ TAS2_IDX_STATE4,
+ TAS2_IDX_STATE5,
+ TAS2_IDX_STATE6,
+ TAS2_IDX_STATE7,
+#ifndef __MD93__
+ TAS2_IDX_STATE8,
+ TAS2_IDX_STATE9,
+ TAS2_IDX_STATE10,
+ TAS2_IDX_STATE11,
+ TAS2_IDX_STATE12,
+ TAS2_IDX_STATE13,
+ TAS2_IDX_STATE14,
+ TAS2_IDX_STATE15,
+ TAS2_IDX_STATE16,
+ TAS2_IDX_STATE17,
+ TAS2_IDX_STATE18,
+ TAS2_IDX_STATE19,
+ TAS2_IDX_STATE20,
+ TAS2_IDX_STATE21,
+ TAS2_IDX_STATE22,
+ TAS2_IDX_STATE23,
+#endif
+ TAS2_IDX_FORCE,
+ TAS2_IDX_DEFAULT,
+ TAS2_IDX_DEFAULT_ON_TEST_SIM,
+ TAS2_IDX_DEFAULT_ON_REAL_SIM,
+ TAS2_TBL_IDX_MAX
+} CL1D_RF_TAS_YABL_INIT_IDX_T;
+
+
+typedef struct
+{
+ kal_int32 tasBMMask;
+ kal_int32 tasBMData;
+ kal_int32 initTblIndex;
+ kal_bool tasSwitchEn;
+} CL1D_RF_TAS_TABL_T;
+typedef enum
+{
+ TAS_BY_RAT_REAL_SIM_ENBLE = 0,
+ TAS_BY_RAT_TEST_SIM_ENBLE = 1,
+ TAS_FORCE_ENBLE = 0,
+ TAS_BY_BAND_REAL_SIM_ENBLE,
+ TAS_BY_BAND_TEST_SIM_ENBLE,
+ TAS_TEST_MODE_ENBLE,
+ TAS_IS_TESTSIM,
+ TAS_BY_RAT_ALL_SWITCH_MAX = 4
+}CL1D_RF_TAS_MAP_T;
+/*SP*/
+
+typedef enum{
+ C2K_TAS_CAT_A,
+ C2K_TAS_CAT_B,
+ C2K_TAS_CAT_C,
+ C2K_TAS_CAT_NUM
+}CL1D_RF_CUST_TAS_CAT_E ;
+
+typedef enum{
+ C2K_TAS_ROUTE_0,
+ C2K_TAS_ROUTE_1,
+ C2K_TAS_ROUTE_2,
+ C2K_TAS_ROUTE_3,
+ C2K_TAS_ROUTE_NUM
+}CL1D_RF_CUST_TAS_ROUTE_E;
+
+typedef enum {
+ ANT_NULL = 0, /* NO TAS control */
+ ANT_1,
+ ANT_2,
+ ANT_3,
+ ANT_4,
+ ANT_5,
+ ANT_6,
+ ANT_7,
+
+ ANT_MAX_NUM,
+
+ ANT_INVALID_NUM = ANT_MAX_NUM
+}CL1D_RF_CUST_TAS_ANT_INDEX_E;
+
+typedef enum
+{
+ C2K_TAS_FE_ROUTE0,
+ C2K_TAS_FE_ROUTE1,
+ C2K_TAS_FE_ROUTE2,
+ C2K_TAS_FE_ROUTE3,
+ C2K_TAS_FE_ROUTE4,
+ C2K_TAS_FE_NULL = C2K_TAS_FE_ROUTE4
+}C2K_CUSTOM_TAS_FE_ROUTE_IDX_E;
+
+typedef enum
+{
+ C2K_TAS_DISBLE,
+ C2K_TAS_DISABLE = C2K_TAS_DISBLE,
+ C2K_TAS_ENABLE
+}C2K_CUSTOM_TAS_SWITCH_E;
+
+typedef enum
+{
+ C2K_ANT_LAYOUT_GROUP_INDEX0,
+ C2K_ANT_LAYOUT_GROUP_INDEX1,
+ C2K_ANT_LAYOUT_GROUP_INDEX2,
+ C2K_ANT_LAYOUT_GROUP_INDEX3,
+ C2K_ANT_LAYOUT_GROUP_INDEX4,
+ C2K_ANT_LAYOUT_GROUP_INDEX5,
+ C2K_ANT_LAYOUT_GROUP_INDEX6,
+ C2K_ANT_LAYOUT_GROUP_INDEX7,
+ C2K_ANT_LAYOUT_GROUP_INDEX8,
+ C2K_ANT_LAYOUT_GROUP_INDEX9,
+ C2K_ANT_LAYOUT_GROUP_INDEX_MAX,
+ C2K_ANT_LAYOUT_GROUP_INDEX_NULL = 0xFF
+}C2K_CUSTOM_TAS_LAYOUT_GROUP_E;
+
+/*DAT structure */
+typedef enum
+{
+ C2K_DAT_CAT_A_CONFIG_IDX0,
+ C2K_DAT_CAT_A_CONFIG_IDX1,
+ C2K_DAT_CAT_A_CONFIG_IDX2,
+ C2K_DAT_CAT_A_CONFIG_IDX3,
+ C2K_DAT_CAT_A_CONFIG_IDX4,
+ C2K_DAT_CAT_A_CONFIG_IDX5,
+ C2K_DAT_CAT_A_CONFIG_IDX6,
+ C2K_DAT_CAT_A_CONFIG_IDX7,
+ C2K_DAT_CAT_A_CONFIG_IDX8,
+ C2K_DAT_CAT_A_CONFIG_IDX9,
+ C2K_DAT_CAT_A_NULL = C2K_DAT_FE_NULL,
+}C2K_CUSTOM_DAT_CAT_A_IDX_E;
+
+typedef enum
+{
+ C2K_DAT_CAT_B_CONFIG_IDX0,
+ C2K_DAT_CAT_B_CONFIG_IDX1,
+ C2K_DAT_CAT_B_CONFIG_IDX2,
+ C2K_DAT_CAT_B_CONFIG_IDX3,
+ C2K_DAT_CAT_B_CONFIG_IDX4,
+ C2K_DAT_CAT_B_CONFIG_IDX5,
+ C2K_DAT_CAT_B_CONFIG_IDX6,
+ C2K_DAT_CAT_B_CONFIG_IDX7,
+ C2K_DAT_CAT_B_CONFIG_IDX8,
+ C2K_DAT_CAT_B_CONFIG_IDX9,
+ C2K_DAT_CAT_B_CONFIG_IDX10,
+ C2K_DAT_CAT_B_CONFIG_IDX11,
+ C2K_DAT_CAT_B_CONFIG_IDX12,
+ C2K_DAT_CAT_B_CONFIG_IDX13,
+ C2K_DAT_CAT_B_CONFIG_IDX14,
+ C2K_DAT_CAT_B_CONFIG_IDX15,
+ C2K_DAT_CAT_B_CONFIG_IDX16,
+ C2K_DAT_CAT_B_CONFIG_IDX17,
+ C2K_DAT_CAT_B_CONFIG_IDX18,
+ C2K_DAT_CAT_B_CONFIG_IDX19,
+ C2K_DAT_CAT_B_CONFIG_IDX20,
+ C2K_DAT_CAT_B_CONFIG_IDX21,
+ C2K_DAT_CAT_B_CONFIG_IDX22,
+ C2K_DAT_CAT_B_CONFIG_IDX23,
+ C2K_DAT_CAT_B_CONFIG_IDX24,
+ C2K_DAT_CAT_B_CONFIG_IDX25,
+ C2K_DAT_CAT_B_CONFIG_IDX26,
+ C2K_DAT_CAT_B_CONFIG_IDX27,
+ C2K_DAT_CAT_B_CONFIG_IDX28,
+ C2K_DAT_CAT_B_CONFIG_IDX29,
+ C2K_DAT_CAT_B_CONFIG_IDX30,
+ C2K_DAT_CAT_B_CONFIG_IDX31,
+ C2K_DAT_CAT_B_CONFIG_IDX32,
+ C2K_DAT_CAT_B_CONFIG_IDX33,
+ C2K_DAT_CAT_B_CONFIG_IDX34,
+ C2K_DAT_CAT_B_CONFIG_IDX35,
+ C2K_DAT_CAT_B_CONFIG_IDX36,
+ C2K_DAT_CAT_B_CONFIG_IDX37,
+ C2K_DAT_CAT_B_CONFIG_IDX38,
+ C2K_DAT_CAT_B_CONFIG_IDX39,
+ C2K_DAT_CAT_B_NULL = C2K_DAT_FE_NULL,
+}C2K_CUSTOM_DAT_CAT_B_IDX_E;
+
+typedef enum
+{
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX0,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX1,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX2,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX3,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX4,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX5,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX6,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX7,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX8,
+ C2K_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX9,
+ C2K_DAT_CAT_A_MIPI_TABLE_NULL = C2K_DAT_MIPI_TABLE_NULL,
+}C2K_CUSTOM_DAT_CAT_A_MIPI_TBL_IDX_E;
+
+
+typedef enum
+{
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX0,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX1,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX2,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX3,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX4,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX5,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX6,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX7,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX8,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX9,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX10,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX11,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX12,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX13,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX14,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX15,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX16,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX17,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX18,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX19,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX20,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX21,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX22,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX23,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX24,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX25,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX26,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX27,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX28,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX29,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX30,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX31,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX32,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX33,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX34,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX35,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX36,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX37,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX38,
+ C2K_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX39,
+ C2K_DAT_CAT_B_MIPI_TABLE_NULL = C2K_DAT_MIPI_TABLE_NULL,
+}C2K_CUSTOM_DAT_CAT_B_MIPI_TBL_IDX_E;
+
+typedef enum
+{
+ C2K_DAT_DISABLE,
+ C2K_DAT_ENABLE
+}C2K_CUSTOM_DAT_SWITCH_E;
+
+typedef enum
+{
+ C2K_DAT_STATE0,
+ C2K_DAT_STATE1,
+ C2K_DAT_STATE2,
+ C2K_DAT_STATE3,
+ C2K_DAT_STATE4,
+ C2K_DAT_STATE5,
+ C2K_DAT_STATE6,
+ C2K_DAT_STATE7,
+ C2K_DAT_STATE_NULL,
+}C2K_CUSTOM_DAT_STATE_E;
+
+typedef struct
+{
+ kal_uint32 cat_a_route_num;
+ kal_uint32 cat_b_route_num;
+}C2K_CUSTOM_DAT_FE_ROUTE_MAP_T;
+
+
+typedef struct
+{
+ C2K_CUSTOM_DAT_FE_ROUTE_MAP_T dat_fe_setting[C2K_DAT_MAX_STATE_NUM];
+}C2K_CUSTOM_DAT_ROUTE_SETTING_T;
+
+typedef struct
+{
+ C2K_CUSTOM_DAT_SWITCH_E feature_enable;
+ C2K_CUSTOM_DAT_ROUTE_SETTING_T c2k_dat_fe_route_db[RF_CUST_SUPPORT_BAND_MAX_NUM];
+}CL1D_RF_DAT_FE_ROUTE_DATABASE_T;
+typedef CL1D_RF_DAT_FE_ROUTE_DATABASE_T C2K_CUSTOM_DAT_FE_ROUTE_DATABASE_T;
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ C2K_CUSTOM_DAT_CAT_A_MIPI_TBL_IDX_E dat_mipi_table_index;
+}C2K_CUSTOM_DAT_CAT_A_FE_SETTING_T;
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ C2K_CUSTOM_DAT_CAT_B_MIPI_TBL_IDX_E dat_mipi_table_index;
+}C2K_CUSTOM_DAT_CAT_B_FE_SETTING_T;
+
+typedef struct
+{
+ C2K_CUSTOM_DAT_CAT_A_FE_SETTING_T dat_cat_a_fe_route[C2K_DAT_MAX_CAT_A_ROUTE_NUM];
+}C2K_CUSTOM_DAT_FE_CAT_A_T;
+typedef C2K_CUSTOM_DAT_FE_CAT_A_T CL1D_RF_DAT_FE_CAT_A_T;
+
+typedef struct
+{
+ C2K_CUSTOM_DAT_CAT_B_FE_SETTING_T dat_cat_b_fe_route[C2K_DAT_MAX_CAT_B_ROUTE_NUM];
+}C2K_CUSTOM_DAT_FE_CAT_B_T;
+typedef C2K_CUSTOM_DAT_FE_CAT_B_T CL1D_RF_DAT_FE_CAT_B_T;
+
+
+typedef struct
+{
+ kal_uint8 dat_ant_switch_index;
+ kal_uint8 dat_tuner_index;
+}C2K_CUSTOM_DAT_ANT_TUNER_INDEX_T;
+
+typedef struct
+{
+ C2K_CUSTOM_DAT_ANT_TUNER_INDEX_T dat_route_index[C2K_DAT_MAX_STATE_NUM];
+}C2K_CUSTOM_DAT_ROUTE_INDEX_T;
+
+typedef struct
+{
+ kal_uint8 split_number;
+ kal_uint16 sub_freq[C2K_ANT_TUNER_SPLIT_PART_MAX];
+ C2K_CUSTOM_DAT_ROUTE_INDEX_T dat_split_part_route_index[C2K_ANT_TUNER_SPLIT_PART_MAX];
+}C2K_CUSTOM_DAT_SPLIT_PART_STATE_INDEX_T;
+
+typedef struct
+{
+ C2K_CUSTOM_DAT_SWITCH_E feature_enable;
+ C2K_CUSTOM_DAT_SPLIT_PART_STATE_INDEX_T c2k_dat_fe_route_db[RF_CUST_SUPPORT_BAND_MAX_NUM];
+}CL1D_RF_DAT_ANT_TUNER_ROUTE_DATABASE_T;
+
+typedef CL1D_RF_DAT_ANT_TUNER_ROUTE_DATABASE_T C2K_CUSTOM_DAT_ANT_TUNER_ROUTE_DATABASE_T;
+
+
+/*TAS TST config structure */
+typedef enum{
+ C2K_TAS_TST_DISABLE,
+ C2K_TAS_TST_ENABLE
+}C2K_CUSTOM_TAS_TST_SWITCH_E;
+
+typedef struct{
+ C2K_CUSTOM_TAS_TST_SWITCH_E tas_tst_enable; //enable query state info
+ SysCdmaBandT tas_tst_band_support[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ C2K_CUSTOM_TAS_SWITCH_E tas_tst_state_support[RF_CUST_SUPPORT_BAND_MAX_NUM][C2K_TAS_MAX_STATE_NUM];
+}CL1D_RF_TAS_TST_CONFIG_T;
+
+typedef struct
+{
+ C2K_CUSTOM_TAS_SWITCH_E tas_enable;
+ MMRFD_CUSTOM_TAS_STATE_E tas_state;
+}C2K_CUSTOM_TAS_FEATURE_OPTION_T;
+
+#ifndef __MD93__
+typedef struct
+{
+ kal_uint16 subband_freq;
+ C2K_CUSTOM_ANT_TUNER_CONFIG_SETTING_INDEX_E tuner_control_split_setting;
+}C2K_CUSTOM_ANT_TUNER_SPLIT_CONFIGURE_T;
+
+typedef struct
+{
+ kal_uint8 ant_tuner_split_num;
+ C2K_CUSTOM_ANT_TUNER_SPLIT_CONFIGURE_T tuner_control_setting[C2K_RF_UTAS_MAX_SPLIT_BAND_NUM];
+}C2K_CUSTOM_ANT_TUNER_CONFIGURE_T;
+
+typedef struct
+{
+ C2K_CUSTOM_TAS_FEATURE_OPTION_T real_sim_tas_feature;
+ C2K_CUSTOM_TAS_FEATURE_OPTION_T test_sim_tas_feature;
+ C2K_CUSTOM_TAS_STATE_E ant_tas_calibration_state_setting;
+ C2K_CUSTOM_TAS_LAYOUT_GROUP_E ant_utas_group_setting_index;
+ C2K_CUSTOM_ANT_TUNER_CONFIGURE_T ant_tuner_control_setting;
+ kal_int8 rscp_bias[C2K_RF_UTAS_MAX_ANT_NUM];
+}C2K_CUSTOM_ANT_FEATURE_CONFIGURE_BY_BAND_T;
+
+typedef struct
+{
+ C2K_CUSTOM_ANT_FEATURE_CONFIGURE_BY_BAND_T ant_tuner_fe_route_database[RF_CUST_SUPPORT_BAND_MAX_NUM];
+}CL1D_RF_ANT_FE_ROUTE_DATABASE_T;
+
+typedef CL1D_RF_ANT_FE_ROUTE_DATABASE_T C2K_CUSTOM_ANT_FE_ROUTE_DATABASE_T;
+
+typedef struct
+{
+ kal_int32 STx_SO_HYSTERESIS_DURATION;
+ kal_int32 STx_SO_A_THRESHOLD_INDICATING_NO_POWER_HEADROOM;
+ kal_int32 STx_SO_TXP_GAIN_THRESHOLD;
+ kal_int32 STx_SO_PHR_GAIN_THRESHOLD;
+ kal_int32 STx_SO_PRESWITCHING_STATE_DURATION;
+ kal_int32 STx_SO_INCREASED_TXP_THRESHOLD_IN_PRESWITCHING_STATE;
+ kal_int32 STx_SO_THRESHOLD_FOR_SUM_OF_TXP_AND_SIGPOWER_IN_PRESWITCHING_STATE;
+}C2K_CUSTOM_UTAS_STx_SO_PARAMETER_T;
+typedef struct
+{
+ kal_int32 PTXP_DB_LOWER_BOUND_PARAM;
+ kal_int32 PTXP_DB_UPPER_BOUND_PARAM;
+ kal_int32 PTXP_DB_INCREASED_AMOUNT_BARRIER_PARAM;
+ kal_int32 PTXP_DB_DECREASED_AMOUNT_BARRIER_PARAM;
+ kal_int32 HR_DB_LOWER_BOUND_PARAM;
+ kal_int32 HR_DB_UPPER_BOUND_PARAM;
+ kal_int32 HR_DB_INCREASED_AMOUNT_BARRIER_PARAM;
+ kal_int32 HR_DB_DECREASED_AMOUNT_BARRIER_PARAM;
+ kal_int32 HR_DB_TIME_DURATION_TO_RELAX_BARRIER_PARAM;
+}C2K_CUSTOM_UTAS_DB_PARAMETER_T;
+typedef struct
+{
+ kal_int32 BTx_SO_HYSTERESIS_DURATION;
+ kal_int32 BTx_SO_MEAS_SIGPOWER_NUMBER;
+ kal_int32 BTx_SO_SIGPOWER_CB_THRESHOLD;
+ kal_int32 BTx_SO_A_THRESHOLD_INDICATING_NO_POWER_HEADROOM;
+ kal_int32 BTx_SO_SIGPOWER_THRESHOLD_FOR_STARTING_TIMER;
+ kal_int32 BTx_SO_INITIAL_DURATION;
+ kal_int32 BTx_SO_UPPER_BOUND;
+ kal_int32 BTx_SO_INCREASED_AMOUNT_DELTA_FOR_FAIL_PRE_SWITCHING;
+ kal_int32 BTx_SO_PRESWITCHING_STATE_DURATION;
+ kal_int32 BTx_SO_INCREASED_TXP_THRESHOLD_IN_PRE_SWITCHIN_STATE;
+ kal_int32 BTx_SO_THRESHOLD_FOR_SUM_OF_TXP_AND_SIGPOWER_IN_PRESWITCHING_STATE;
+}C2K_CUSTOM_UTAS_BTx_SO_PARAMETER_T;
+typedef struct
+{
+ kal_int32 BRX_HYSTERESIS_DURATION;
+ kal_int32 BRX_LOW_QUALITY_THRESHOLD;
+ kal_int32 BRX_SIGPOWER_CB_THRESHOLD;
+ kal_int32 BRX_LOW_SNR_THRESHOLD;
+ kal_int32 BRX_SIGPOWER_THRESHOLD_FOR_STARTING_TIMER;
+ kal_int32 BRX_INITIAL_DURATION;
+ kal_int32 BRX_UPPER_BOUND;
+ kal_int32 BRX_INCREASED_AMOUNT_DELTA_FOR_FAIL_PRESWITCHING;
+ kal_int32 BRX_PRESWITCHING_STATE_DURATION;
+ kal_int32 BRX_SIGPOWER_CB_THRESHOLD_IN_PRESWITCHING_state;
+}C2K_CUSTOM_UTAS_BRX_PARAMETER_T;
+typedef struct
+{
+ kal_int32 HTP_HYSTERESIS_DURATION;
+ kal_int32 HTP_A_THRESHOLD_INDICATIONG_NO_POWER_HEADROOM;
+}C2K_CUSTOM_UTAS_HTP_PARAMETER_T;
+typedef struct
+{
+ C2K_CUSTOM_UTAS_STx_SO_PARAMETER_T UTAS_STx_SO_PARAMETER;
+ C2K_CUSTOM_UTAS_DB_PARAMETER_T UTAS_DB_PARAMETER;
+ C2K_CUSTOM_UTAS_BTx_SO_PARAMETER_T UTAS_BTx_SO_PARAMETER;
+ C2K_CUSTOM_UTAS_BRX_PARAMETER_T UTAS_BRX_PARAMETER;
+ C2K_CUSTOM_UTAS_HTP_PARAMETER_T UTAS_HTP_PARAMETER;
+}C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T;
+typedef C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T CL1D_RF_UTAS_ALGORITHM_PARAMETER_T;
+#endif
+
+#if (defined(__MD97__) || defined(__MD97P__))
+typedef struct{
+ kal_int8 rscp_bias[C2K_RF_UTAS_MAX_ANT_NUM];
+}CL1D_RF_TAS_RSCP_BIAS_T;
+typedef CL1D_RF_TAS_RSCP_BIAS_T C2K_CUSTOM_TAS_RSCP_BIAS_T;
+
+typedef struct{
+ C2K_CUSTOM_DAT_SWITCH_E dat_enable;
+ C2K_CUSTOM_TAS_FEATURE_OPTION_T force_mode_tas_feature;
+ C2K_CUSTOM_TAS_SWITCH_E tas_enable_on_real_sim;
+ C2K_CUSTOM_TAS_SWITCH_E tas_enable_on_test_sim;
+ MMRFD_CUSTOM_TAS_STATE_E tas_init_ant_state;
+ MMRFD_CUSTOM_TAS_STATE_E ant_tas_calibration_state_setting[RF_CUST_SUPPORT_BAND_MAX_NUM];
+ C2K_CUSTOM_TAS_RSCP_BIAS_T rscp_bias_by_band[RF_CUST_SUPPORT_BAND_MAX_NUM];
+}CL1D_RF_TAS_FEATURE_T;
+typedef CL1D_RF_TAS_FEATURE_T C2K_CUSTOM_TAS_FEATURE_T;
+#else
+typedef struct{
+#ifdef __MD93__
+ C2K_CUSTOM_TAS_VER_E tas_version;
+#endif
+ C2K_CUSTOM_TAS_FEATURE_OPTION_T force_mode_tas_feature;
+ C2K_CUSTOM_TAS_STATE_E tas_init_ant_state;
+ C2K_CUSTOM_TAS_SWITCH_E tas_enable_on_real_sim;
+ C2K_CUSTOM_TAS_SWITCH_E tas_enable_on_test_sim;
+}CL1D_RF_TAS_FEATURE_BY_RAT_T;
+typedef CL1D_RF_TAS_FEATURE_BY_RAT_T C2K_CUSTOM_TAS_FEATURE_BY_RAT_T;
+#endif
+
+typedef struct
+{
+ C2K_CUSTOM_TAS_FEATURE_OPTION_T real_sim_tas_feature;
+ C2K_CUSTOM_TAS_FEATURE_OPTION_T test_sim_tas_feature;
+}C2K_CUSTOM_TAS_FEATURE_ENABLE_T;
+
+typedef struct
+{
+ kal_uint32 cat_a_route_num;
+ kal_uint32 cat_b_route_num;
+ kal_uint32 cat_c_route_num;
+}C2K_CUSTOM_TAS_FE_ROUTE_MAP_T;
+typedef struct
+{
+ kal_uint32 tas_state_num;
+ C2K_CUSTOM_TAS_FEATURE_ENABLE_T tas_feature_enable;
+ C2K_CUSTOM_TAS_FE_ROUTE_MAP_T tas_fe_setting[C2K_TAS_MAX_STATE_NUM];
+}C2K_CUSTOM_SB_TAS_SETTING_T;
+typedef struct
+{
+ C2K_CUSTOM_SB_TAS_SETTING_T c2k_tas_fe_route_db[C2K_TAS_MAX_FE_ROUTE_NUM];/*By route(By RF_Band) */
+}CL1D_RF_TAS_FE_ROUTE_DATABASE_T;
+typedef CL1D_RF_TAS_FE_ROUTE_DATABASE_T C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T;
+
+typedef enum
+{
+ C2K_TAS_MIPI_TABLE_ROUTE0,
+ C2K_TAS_MIPI_TABLE_ROUTE1,
+ C2K_TAS_MIPI_TABLE_ROUTE2,
+ C2K_TAS_MIPI_TABLE_ROUTE3,
+ C2K_TAS_MIPI_TABLE_NULL
+}C2K_CUSTOM_TAS_MIPI_TBL_IDX_E;
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ C2K_CUSTOM_TAS_MIPI_TBL_IDX_E tas_mipi_table_index;
+}C2K_CUSTOM_TAS_FE_SETTING_T;
+typedef struct
+{
+ C2K_CUSTOM_TAS_FE_SETTING_T tas_cat_a_fe_route[C2K_TAS_MAX_CAT_A_ROUTE_NUM];
+}CL1D_RF_TAS_FE_CAT_A_T;
+typedef const CL1D_RF_TAS_FE_CAT_A_T C2K_CUSTOM_TAS_FE_CAT_A_T;
+
+typedef struct
+{
+ C2K_CUSTOM_TAS_FE_SETTING_T tas_cat_b_fe_route[C2K_TAS_MAX_CAT_B_ROUTE_NUM];
+}CL1D_RF_TAS_FE_CAT_B_T;
+typedef const CL1D_RF_TAS_FE_CAT_B_T C2K_CUSTOM_TAS_FE_CAT_B_T;
+
+typedef struct
+{
+ C2K_CUSTOM_TAS_FE_SETTING_T tas_cat_c_fe_route[C2K_TAS_MAX_CAT_C_ROUTE_NUM];
+}CL1D_RF_TAS_FE_CAT_C_T;
+typedef const CL1D_RF_TAS_FE_CAT_C_T C2K_CUSTOM_TAS_FE_CAT_C_T;
+
+typedef struct
+{
+ kal_int8 main_route_num;
+ kal_int8 div_route_num;
+}HwdRfTunerIndexT;
+typedef struct
+{
+ HwdRfTunerIndexT TunerInitSetting;
+ HwdRfTunerIndexT TunerWithTasSetting[C2K_TAS_MAX_STATE_NUM];
+}HwdRfTunerSetting;
+typedef struct
+{
+ HwdRfTunerSetting tuner_fe_route[RF_CUST_SUPPORT_BAND_MAX_NUM];
+}CL1D_RF_TUNER_FE_ROUTE_TABLE;
+typedef const CL1D_RF_TUNER_FE_ROUTE_TABLE C2K_CUSTOM_TUNER_FE_ROUTE_TABLE;
+
+typedef enum
+{
+ C2K_TUNER_FE_ROUTE0,
+ C2K_TUNER_FE_ROUTE1,
+ C2K_TUNER_FE_ROUTE2,
+ C2K_TUNER_FE_ROUTE3,
+ C2K_TUNER_FE_ROUTE4,
+ C2K_TUNER_FE_ROUTE5,
+ C2K_TUNER_FE_ROUTE6,
+ C2K_TUNER_FE_ROUTE7,
+ C2K_TUNER_FE_NULL ,
+}C2K_CUSTOM_TUER_FE_ROUTE_IDX_E;
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ C2K_CUSTOM_TUER_FE_ROUTE_IDX_E tas_mipi_table_index;
+}C2K_CUSTOM_TUNER_FE_SETTING_T;
+typedef struct
+{
+ C2K_CUSTOM_TUNER_FE_SETTING_T tuner_band_route[C2K_TUNER_FE_MAX];
+}CL1D_RF_TUNER_BAND_T;
+typedef const CL1D_RF_TUNER_BAND_T C2K_CUSTOM_TUNER_BAND_T;
+typedef struct{
+ C2K_CUSTOM_TAS_FE_CAT_A_T * tas_cat_a_ptr;
+ C2K_CUSTOM_TAS_FE_CAT_B_T * tas_cat_b_ptr;
+ C2K_CUSTOM_TAS_FE_CAT_C_T * tas_cat_c_ptr;
+}CL1D_RF_TAS_DATA_BASE_T;
+
+typedef struct{
+ C2K_CUSTOM_TUNER_BAND_T * tuner_data_base_by_band[RF_CUST_SUPPORT_BAND_MAX_NUM];
+}CL1D_RF_TUNER_DATA_BASE_T;
+
+typedef struct
+{
+ kal_bool mipi_enable;
+ kal_uint32 mipi_tool_version;
+}CL1D_RF_MIPI_PARAM_T;
+/*mipi event(RX/TX/TPC Event)*/
+typedef struct
+{
+ kal_uint16 mipi_data_st;/*MIPI data start index*/
+ kal_uint16 mipi_data_sp;/*MIPI data stop index*/
+}CL1D_RF_MIPI_DATA_STSP;
+//final
+typedef struct
+{
+ kal_uint16 mipi_elm_type;/*MIPI element:ASM,PA,Tuner,etc. */
+ CL1D_RF_MIPI_DATA_STSP mipi_data_stsp;
+ kal_uint16 mipi_evt_type;/*MIPI event type: RX/TX on/off */
+ kal_uint32 mipi_evt_offset;/*MIPI event offset,in unit of chips */
+}CL1D_RF_MIPI_EVENT_TABLE_T;//ju he 1
+
+/*mipi RX/TX Data */
+typedef struct
+{
+ kal_uint16 addr;
+ kal_uint32 data;
+}CL1D_MIPI_ADDR_DATA_EXPAND_TABLE_T;
+typedef struct
+{
+ kal_uint16 mipi_subband_freq;
+ CL1D_MIPI_ADDR_DATA_EXPAND_TABLE_T mipi_data;
+}CL1D_MIPI_DATA_EXPAND_TABLE_T;
+/*MIPI_SUBBAND */
+typedef enum
+{
+ mipi_subband_0=0,
+ mipi_subband_1,
+ mipi_subband_2,
+ mipi_subband_3,
+ mipi_subband_4,
+ mipi_subband_num_max
+}MIPI_SUBBAND_E;
+
+typedef struct
+{
+ kal_uint16 mipi_elm_type;
+ kal_uint16 mipi_port_sel;
+ kal_uint16 mipi_data_seq;/*mipi data write format */
+ kal_uint16 mipi_usid;
+ CL1D_MIPI_DATA_EXPAND_TABLE_T mipi_subband_data[mipi_subband_num_max];
+}CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T;//ju he 2
+
+/*mipi TPC Data */
+
+typedef struct
+{
+ kal_uint16 mipi_elm_type;
+ kal_uint16 mipi_port_sel;
+ kal_uint16 mipi_data_seq;/*mipi data write format */
+ kal_uint16 mipi_usid;
+ kal_uint16 addr;
+ kal_uint32 data;
+}CL1D_RF_MIPI_DATA_TABLE_T;
+
+typedef struct
+{
+ kal_uint16 addr;
+ kal_uint16 data;
+}CL1D_RF_MIPI_ADDR_DATA_TABLE_T;
+typedef struct
+{
+ CL1D_RF_MIPI_ADDR_DATA_TABLE_T mipi_event_data[5];///TODO: the max num of data is 5 !
+}CL1D_MIPI_TPC_SUBBAND_OCT_TABLE_T;
+
+typedef struct
+{
+ kal_uint16 mipi_subband_freq;
+ kal_uint16 mipi_usid;
+ CL1D_MIPI_TPC_SUBBAND_OCT_TABLE_T mipi_pa_oct_table[MIPI_TPC_OCT_NUM];///TODO: typedef an enum !!!
+}CL1D_RF_TPC_SECTION_TABLE_T;//ju he 3
+
+typedef const CL1D_RF_MIPI_EVENT_TABLE_T C2K_MIPI_EVENT_TABLE_T;
+typedef const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T C2K_MIPI_DATA_SUBBAND_TABLE_T;
+typedef const CL1D_RF_MIPI_DATA_TABLE_T C2K_MIPI_DATA_TABLE_T;
+typedef const CL1D_RF_TPC_SECTION_TABLE_T C2K_MIPI_TPC_SECTION_TABLE_T;
+
+/* MIPI Aggregation structure*/
+typedef struct
+{
+ /*Event tables*/
+ CL1D_RF_MIPI_EVENT_TABLE_T *RX_EVENT_ptr;
+ CL1D_RF_MIPI_EVENT_TABLE_T *TX_EVENT_ptr;
+ CL1D_RF_MIPI_EVENT_TABLE_T *TPC_EVENT_ptr;
+ /*ETM event tables */
+ CL1D_RF_MIPI_EVENT_TABLE_T *ETM_TX_EVENT_ptr;
+ CL1D_RF_MIPI_EVENT_TABLE_T *ETM_TPC_EVENT_ptr;
+
+ /*Data tables*/
+ CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T *RX_DATA_ptr;
+ CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T *TX_DATA_ptr;
+ CL1D_RF_MIPI_DATA_TABLE_T *TPC_DATA_ptr;
+ /*ETM data tables */
+ CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T *ETM_TX_DATA_ptr;
+ CL1D_RF_MIPI_DATA_TABLE_T *ETM_TPC_DATA_ptr;
+
+ /*TPC section tables*/
+ CL1D_RF_TPC_SECTION_TABLE_T *TPC_SECTION_DATA_1XRTT_ptr[mipi_subband_num_max];
+ CL1D_RF_TPC_SECTION_TABLE_T *TPC_SECTION_DATA_EVDO_ptr[mipi_subband_num_max];
+ CL1D_RF_TPC_SECTION_TABLE_T *TPC_SECTION_DPD_DATA_1XRTT_ptr[mipi_subband_num_max];
+ CL1D_RF_TPC_SECTION_TABLE_T *TPC_SECTION_DPD_DATA_EVDO_ptr[mipi_subband_num_max];
+ /*ETM section tables */
+ CL1D_RF_TPC_SECTION_TABLE_T *ETM_TPC_SECTION_DATA_1XRTT_ptr[mipi_subband_num_max];
+ CL1D_RF_TPC_SECTION_TABLE_T *ETM_TPC_SECTION_DATA_EVDO_ptr[mipi_subband_num_max];
+}CL1D_RF_CUST_MIPI_INPUT_T;
+/* ELNA MIPI Aggregation structure */
+typedef struct{
+ CL1D_RF_MIPI_EVENT_TABLE_T *ELNA_EVENT_ptr;
+ CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T *ELNA_DATA_ptr;
+}CL1D_RF_CUST_ELNA_MIPI_INPUT_T;
+
+/*MIPI event&data Aggregation structure */
+typedef struct{
+ CL1D_RF_MIPI_EVENT_TABLE_T *MIPI_EVENT_ptr;
+ CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T *MIPI_DATA_ptr;
+}CL1D_RF_CUST_MIPI_INPUT_AGGREATION_T;
+
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"//Just for obtain MIPI_DAT_EVENT_MAX_NUM && MIPI_DAT_DATA_MAX_NUM
+
+typedef struct{
+ CL1D_RF_MIPI_EVENT_TABLE_T DatMipiEventBuffer[C2K_DAT_MAX_CAT_NUM*MIPI_DAT_EVENT_MAX_NUM];
+ CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T DatMipiDataBuffer[C2K_DAT_MAX_CAT_NUM*MIPI_DAT_DATA_MAX_NUM];
+}CL1D_RF_CUST_MIPI_BUFFER_T;
+
+
+/***************** Calibration *******************/
+/*temperature and frequency compensation parameter */
+typedef struct{
+ kal_int16 TemFreqComp[CL1D_RF_NUM_TEMP_CALIBR][CL1D_RF_NUM_FREQ_CALIBR];/*TEMP:8; FREQ:15 */
+}CL1D_RF_TEMP_FREQ_COMP_DATA_T;
+/*RX Path Loss Data */
+typedef struct{
+ kal_int8 TemCelsius[CL1D_RF_NUM_TEMP_CALIBR];/*TEMP:8 */
+ kal_uint16 ChanNum[CL1D_RF_NUM_FREQ_CALIBR];/*FREQ:15 */
+ CL1D_RF_TEMP_FREQ_COMP_DATA_T RxPathLossFreqComp[CL1D_RF_LNA_MODE_NUM];/*LNA:8 */
+}CL1D_RF_RX_PATH_LOSS_COMP_T;
+typedef const CL1D_RF_RX_PATH_LOSS_COMP_T C2K_RF_RX_PATH_LOSS_COMP_T;
+typedef struct {
+ kal_uint16 init_dac;
+ kal_int16 slope;
+ kal_uint16 cap_id;
+ kal_uint16 Reserved;
+}CL1D_RF_AFC_DATA_T;
+typedef const CL1D_RF_AFC_DATA_T C2K_RF_AFC_DATA_T;
+
+/*PA Context Data */
+typedef struct{
+ /** The reference power, in 1/32 dBm. */
+ kal_int16 refPwr;
+ /** The reference power output PA without feq/temp compensation, in 1/32 dBm. */
+ kal_int16 paGain;
+ /** The PA mode info.*/
+ kal_uint16 paMode;
+ /** The PA control RFGPOs level */
+ ///TODO: Below 3 parameter not used
+ kal_uint16 paVm0;
+ kal_uint16 paVm1;
+ /** PA BUCK supply voltage level, unit is mv*/
+ kal_uint16 paVdd;
+}CL1D_RF_PA_CONTEXT_T;
+typedef struct{
+ kal_int16 HighSwitchThresh;/* Tx power for L2M or M2H, unit is 1/32dBm (Q5)*/
+ kal_int16 LowSwitchThresh;/* Tx power for H2M or M2L, unit is 1/32dBm (Q5)*/
+}CL1D_RF_TX_PA_HYST_DATA_T;
+typedef struct{
+ kal_int16 TH_OP_A2D;
+ kal_int16 TH_OP_D2A;///TODO: new feature for 93
+}CL1D_RF_APT_DPD_SWITCH_THD_T;
+typedef struct
+{
+ kal_int32 PaCalSectionNum;
+ CL1D_RF_PA_CONTEXT_T TxPwrPaContext[CL1D_RF_NUM_TX_PA_GAIN_CALIBR];/*PA Gain:8 */
+ CL1D_RF_TX_PA_HYST_DATA_T TxHyst[CL1D_RF_PA_MODE_NUM-1];/*Hyst Region */
+ kal_int16 paPhaseJumpComp[CL1D_RF_PA_MODE_NUM];/*PA mode:3 */
+ kal_int16 reserve;
+}CL1D_RF_TX_APT_PA_CONTEXT_T;
+typedef const CL1D_RF_TX_APT_PA_CONTEXT_T C2K_RF_TX_APT_PA_CONTEXT_T;
+typedef struct{
+ kal_uint8 PaCalSectionNum;
+ CL1D_RF_PA_CONTEXT_T TxPwrPaContext[CL1D_RF_NUM_TX_PA_GAIN_CALIBR];/*PA Gain:8 */
+ CL1D_RF_TX_PA_HYST_DATA_T TxHyst[CL1D_RF_PA_MODE_NUM-1];/*Hyst Region */
+ kal_int16 paPhaseJumpComp[CL1D_RF_PA_MODE_NUM];/*PA mode:3 */
+ CL1D_RF_APT_DPD_SWITCH_THD_T AptDpdSwitchThd;
+}CL1D_RF_TX_DPD_PA_CONTEXT_T;
+typedef const CL1D_RF_TX_DPD_PA_CONTEXT_T C2K_RF_TX_DPD_PA_CONTEXT_T;
+
+/*APT PA Gain Data */
+typedef struct{
+ kal_int8 TemCelsius[CL1D_RF_NUM_TEMP_CALIBR];/*TEMP:8 */
+ kal_uint16 ChanNum[CL1D_RF_NUM_FREQ_CALIBR];/*FREQ:16 */
+ CL1D_RF_TEMP_FREQ_COMP_DATA_T TxPwrPaGainComp[CL1D_RF_NUM_TX_PA_GAIN_CALIBR];/*PA Gain:8 */
+}CL1D_RF_TX_APT_PA_GAIN_COMP_T;
+typedef const CL1D_RF_TX_APT_PA_GAIN_COMP_T C2K_RF_TX_APT_PA_GAIN_COMP_T;
+
+/*DPD Common parameters */
+typedef struct{
+ kal_int16 FdB[CL1D_RF_NUM_TX_PA_GAIN_CALIBR];
+ kal_int16 PtarThTmp[CL1D_RF_NUM_TX_PA_GAIN_CALIBR];
+}CL1D_RF_TX_DPD_COMM_DATA_T;
+
+/*DPD custom parameters*/
+typedef struct
+{
+ /*DPD Normal Mode enable Flag*/
+ CL1D_DPD_ENABLE_E dpd_normal_enable;
+
+ /* The delta term add to tab_PA_Vcc_idx_th, value from custom file */
+ kal_int16 d_tar_th_dpd;
+
+} CL1D_RF_DPD_COMMON_CTRL_T;
+
+/************PCFE SA fine tune Parameters Start*******/
+
+typedef struct
+{
+ kal_uint32 reserved0;
+}CL1D_RF_PCFE_CUSTOM_PARA_T;
+
+typedef struct
+{
+ kal_int16 dpd_apt_temperature_th_by_rfic[2]; // for 2 RFIC
+}CL1D_RF_DPD_OTFC_CUSTOM_PARA_T;
+
+typedef struct
+{
+ CL1D_RF_DPD_OTFC_CUSTOM_PARA_T dpd_otfc_custom;
+ CL1D_RF_PCFE_CUSTOM_PARA_T pcfe_custom;
+
+}CL1D_RF_PCFE_DPD_OTFC_CUSTOM_PARA_T;
+
+
+
+/*DPD PA Gain Data */
+#define CL1D_RF_NUM_RAMP_CALIBR 16
+typedef struct{
+ kal_int8 TemCelsius[CL1D_RF_NUM_TEMP_CALIBR];/*TEMP:8 */
+ kal_uint16 ChanNum[CL1D_RF_NUM_FREQ_CALIBR];/*FREQ:16 */
+ CL1D_RF_TEMP_FREQ_COMP_DATA_T TxPwrPaGainComp[CL1D_RF_NUM_TX_PA_GAIN_CALIBR];/*PA Gain:8 */
+ CL1D_RF_TX_DPD_COMM_DATA_T TxDpdComm[CL1D_RF_NUM_FREQ_CALIBR];
+ kal_int16 DpdTr[CL1D_RF_NUM_FREQ_CALIBR];
+}CL1D_RF_TX_DPD_PA_GAIN_COMP_T;
+typedef const CL1D_RF_TX_DPD_PA_GAIN_COMP_T C2K_RF_TX_DPD_PA_GAIN_COMP_T;
+
+/* AM LUT data parameter */
+typedef struct{
+ kal_uint8 AmLut[CL1D_RF_NUM_TX_PA_GAIN_CALIBR][CL1D_RF_NUM_RAMP_LEVEL];/*PA :8; RAMP:16 */
+}CL1D_RF_AM_LUT_DATA_T;
+
+/* PM LUT data parameter */
+typedef struct{
+ kal_int8 PmLut[CL1D_RF_NUM_TX_PA_GAIN_CALIBR][CL1D_RF_NUM_RAMP_LEVEL];/*PA :8; RAMP:16 */
+}CL1D_RF_PM_LUT_DATA_T;
+
+/*DPD AM/PM Data */
+typedef struct{
+ CL1D_RF_AM_LUT_DATA_T AmLut[CL1D_RF_NUM_FREQ_CALIBR];/* FREQ :16 */
+ CL1D_RF_PM_LUT_DATA_T PmLut[CL1D_RF_NUM_FREQ_CALIBR];/* FREQ :16 */
+}CL1D_RF_TX_DPD_AM_PM_LUT_DATA_T;
+typedef const CL1D_RF_TX_DPD_AM_PM_LUT_DATA_T C2K_RF_TX_DPD_AM_PM_LUT_DATA_T;
+
+/*DPD AM/PM Data For One Freq*/
+typedef struct{
+ CL1D_RF_AM_LUT_DATA_T AmLut;/* FREQ :16 */
+ CL1D_RF_PM_LUT_DATA_T PmLut;/* FREQ :16 */
+}CL1D_RF_TX_DPD_AM_PM_CAL_LUT_DATA_T;
+typedef const CL1D_RF_TX_DPD_AM_PM_CAL_LUT_DATA_T C2K_RF_TX_DPD_AM_PM_CAL_LUT_DATA_T;
+
+
+/*DET Couper Loss Data */
+typedef struct{
+ kal_int16 CouplerGain[CL1D_RF_PA_MODE_NUM];/*PA mode:3 */
+}CL1D_RF_DET_COUPLE_LOSS_T;
+typedef const CL1D_RF_DET_COUPLE_LOSS_T C2K_RF_DET_COUPLE_LOSS_T;
+
+/*DET Compensation Data */
+typedef struct{
+ kal_int8 TemCelsius[CL1D_RF_NUM_TEMP_CALIBR];/*TEMP:8 */
+ kal_uint16 ChanNum[CL1D_RF_NUM_FREQ_CALIBR];/*FREQ:15 */
+ CL1D_RF_TEMP_FREQ_COMP_DATA_T TxPdetCouplerGainComp[CL1D_RF_PA_MODE_NUM];/*PA mode:3 */
+}CL1D_RF_DET_COUPLE_LOSS_COMP_T;
+typedef const CL1D_RF_DET_COUPLE_LOSS_COMP_T C2K_RF_DET_COUPLE_LOSS_COMP_T;
+typedef struct
+{
+ kal_int32 group_delay;
+}CL1D_RF_AGPS_GROUP_DELAY_T;
+typedef const CL1D_RF_AGPS_GROUP_DELAY_T C2K_RF_AGPS_GROUP_DELAY_T;
+
+typedef struct
+{
+ kal_int16 temp;
+ kal_int16 back_off;
+}CL1D_RF_TX_POWER_BACK_OFF_ITEM_T;
+
+typedef struct
+{
+ CL1D_RF_TX_POWER_BACK_OFF_ITEM_T tbl[CL1D_RF_TX_POWER_BACK_OFF_TEMP_NUM];
+}CL1D_RF_TX_POWER_BACK_OFF_T;
+typedef const CL1D_RF_TX_POWER_BACK_OFF_T C2K_RF_TX_POWER_BACK_OFF_T;
+
+/*SAR and SWTP data structure */
+#if defined(__MD93__)
+typedef enum{
+ C2K_SAR_LANT_1 = 0,
+ C2K_SAR_UANT,
+ C2K_SAR_LANT_2,
+ C2K_SAR_TX_ANT_NUM,
+ C2K_SAR_TX_ANT_NULL =C2K_SAR_TX_ANT_NUM
+}CL1D_RF_SAR_TX_ANT_E; //Gen93 ANT num is 3
+#endif
+#if defined(__MD95__)
+typedef enum{
+ C2K_SAR_ANT0,
+ C2K_SAR_ANT1,
+ C2K_SAR_ANT2,
+ C2K_SAR_ANT3,
+ C2K_SAR_ANT4,
+ C2K_SAR_TX_ANT_NUM,
+ C2K_SAR_TX_ANT_NULL = C2K_SAR_TX_ANT_NUM
+}CL1D_RF_SAR_TX_ANT_E; //Gen95 ANT num is 5
+#endif
+#if defined(__MD97__) || defined(__MD97P__)
+typedef enum{
+ C2K_SAR_ANT0 = 0,
+ C2K_SAR_ANT1,
+ C2K_SAR_ANT2,
+ C2K_SAR_ANT3,
+ C2K_SAR_ANT4,
+ C2K_SAR_ANT5,
+ C2K_SAR_ANT6,
+ C2K_SAR_ANT7,
+ C2K_SAR_ANT8,
+ C2K_SAR_ANT9,
+ C2K_SAR_ANT10,
+ C2K_SAR_ANT11,
+ C2K_SAR_TX_ANT_NUM,
+ C2K_SAR_TX_ANT_NULL = C2K_SAR_TX_ANT_NUM
+}CL1D_RF_SAR_TX_ANT_E; //Gen97 ANT num is 12
+#endif
+/*Gen93 and Gen95 SAR & SWTP structure */
+#if defined(__MD93__) || defined(__MD95__)
+typedef struct{
+ kal_uint16 sar_chan_num; /* Unit: sar channel number */
+ kal_int16 sar_power_offset[C2K_SAR_TX_ANT_NUM][CL1D_RF_RAT_NUM]; /* SAR TX power offset, in unit of 1/32 */
+}CL1D_RF_SAR_TX_POWER_OFFSET_TBL_ITEM_T;
+typedef struct{
+ CL1D_RF_SAR_TX_POWER_OFFSET_TBL_ITEM_T sar_tbl_item[SAR_FREQ_CALIBR_NUM];
+}CL1D_RF_SAR_TX_POWER_OFFSET_TBL_T;
+typedef struct{
+ CL1D_RF_SAR_TX_POWER_OFFSET_TBL_T sar_tbl[SAR_TX_POWER_OFFSET_TABLE_NUM];
+}CL1D_RF_SAR_TX_POWER_OFFSET_T;
+typedef const CL1D_RF_SAR_TX_POWER_OFFSET_T C2K_RF_SAR_TX_POWER_OFFSET_T; //Gen93 and Gen95 SAR and SWTP co-structure
+#endif
+
+/*Gen97 SAR & SWTP structure */
+#if defined(__MD97__) || defined(__MD97P__)
+//SAR structure
+typedef struct
+{
+ kal_int16 sar_power_offset[C2K_SAR_TX_ANT_NUM][CL1D_RF_RAT_NUM]; /* SAR TX power offset, in unit of 1/32 */
+}CL1D_RF_SAR_TX_POWER_OFFSET_TBL_ITEM_T;
+
+typedef struct
+{
+ CL1D_RF_SAR_TX_POWER_OFFSET_TBL_ITEM_T sar_tbl_item;
+}CL1D_RF_SAR_TX_POWER_OFFSET_TBL_T;
+
+typedef struct
+{
+ CL1D_RF_SAR_TX_POWER_OFFSET_TBL_T sar_tbl[SAR_TX_POWER_OFFSET_TABLE_NUM];
+}CL1D_RF_SAR_TX_POWER_OFFSET_T;
+typedef const CL1D_RF_SAR_TX_POWER_OFFSET_T C2K_RF_SAR_TX_POWER_OFFSET_T; //Gen97 SAR and SWTP use independent structure.
+
+typedef struct
+{
+ CL1D_RF_SAR_TX_POWER_OFFSET_T* sar_type_byBand[RF_Band_NUM_MAX];
+}CL1D_RF_SAR_TYPE_T;
+
+typedef struct
+{
+ kal_int32 operator_sar_type;//for debug. common_sar choose type accroding to operator_sar_type(mmrf API)
+ kal_int16 common_sar_tx_power_offset[SAR_TX_POWER_OFFSET_TABLE_NUM][C2K_SAR_TX_ANT_NUM];
+}CL1D_RF_COMMON_SAR_INIT_T;
+
+//SWTP structure
+typedef struct
+{
+ kal_uint16 swtp_chan_num; /* Unit: sar channel number */
+ kal_int16 swtp_power_offset[C2K_SAR_TX_ANT_NUM][CL1D_RF_RAT_NUM]; /* SAR TX power offset, in unit of 1/32 */
+}CL1D_RF_SWTP_TX_POWER_OFFSET_TBL_ITEM_T;
+
+typedef struct
+{
+ CL1D_RF_SWTP_TX_POWER_OFFSET_TBL_ITEM_T swtp_tbl_item[SAR_FREQ_CALIBR_NUM];
+}CL1D_RF_SWTP_TX_POWER_OFFSET_TBL_T;
+
+typedef struct
+{
+ CL1D_RF_SWTP_TX_POWER_OFFSET_TBL_T swtp_tbl[SWTP_TX_POWER_OFFSET_TABLE_NUM];
+}CL1D_RF_SWTP_TX_POWER_OFFSET_T;
+typedef const CL1D_RF_SWTP_TX_POWER_OFFSET_T C2K_RF_SWTP_TX_POWER_OFFSET_T; //Gen97 SAR and SWTP use independent structure.
+#endif
+
+
+#if defined(__C2K_RF_HOPPING_SUPPORT__)
+#define IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT 1
+#define IS_C2K_RF_HOPPING_DEBUG_ENABLE 0
+#else
+#define IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT 0
+#define IS_C2K_RF_HOPPING_DEBUG_ENABLE 0
+#endif
+
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+#define C2K_RF_FREQ_INVALID (65535)
+#define C2K_RF_FREQ_SMALL_GROUP_NUM (8)
+#define C2K_RF_FREQ_TABLE_NUM (8)
+typedef enum
+{
+ C2K_RF_INTERFERE_CHECK_DISABLE,
+ C2K_RF_INTERFERE_CHECK_ENABLE
+}C2K_RF_INTERFERE_CHECK_E;
+
+typedef struct{
+ kal_uint16 c2k_rf_freq_start;
+ kal_uint16 c2k_rf_freq_end;
+}CL1D_RF_HOPPING_TBL_ITEM_T;
+
+typedef struct{
+ CL1D_RF_HOPPING_TBL_ITEM_T c2k_rf_tbl_item [C2K_RF_FREQ_SMALL_GROUP_NUM]; // 8 small group for G_A/B
+}CL1D_RF_HOPPING_TBL_ITEM_GROUP_T;
+
+typedef struct{
+ CL1D_RF_HOPPING_TBL_ITEM_GROUP_T c2k_rf_group_a;
+ CL1D_RF_HOPPING_TBL_ITEM_GROUP_T c2k_rf_group_b;
+}CL1D_RF_HOPPING_TBL_T;
+
+typedef struct{
+ C2K_RF_INTERFERE_CHECK_E c2k_rf_hopping_table_en[C2K_RF_FREQ_TABLE_NUM];
+ CL1D_RF_HOPPING_TBL_T c2k_rf_hopping_table[C2K_RF_FREQ_TABLE_NUM];
+}CL1D_RF_HOPPING_DATA_BASE_T;
+
+typedef const CL1D_RF_HOPPING_DATA_BASE_T C2K_CUSTOM_HOPPING_DATA_BASE_T;
+#endif
+#endif /* _CL1_RF_PUBLIC_H_ */
+
diff --git a/mcu/interface/l1/cl1/rfd/cl1_rf_tas_public.h b/mcu/interface/l1/cl1/rfd/cl1_rf_tas_public.h
new file mode 100644
index 0000000..712eaa1
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1_rf_tas_public.h
@@ -0,0 +1,253 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_tas_public.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * Header file containing typedefs and definitions pertaining
+ * to C2K RF driver external interface.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+#ifndef CL1D_RF_TAS_PUBLIC_H
+#define CL1D_RF_TAS_PUBLIC_H
+#ifdef SYS_OPTION_TX_TAS_ENABLE
+ #if defined(__MD93__)
+ #define _C2K_TAS_SUPPORT_ (1)
+ #define _C2K_UTAS_SUPPORT_ (0)
+ #define _C2K_UTAS_SUPPORT_97 (0)
+ #elif (defined(__MD95__))
+ #define _C2K_TAS_SUPPORT_ (0)
+ #define _C2K_UTAS_SUPPORT_ (1)
+ #define _C2K_UTAS_SUPPORT_97 (0)
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #define _C2K_TAS_SUPPORT_ (0)
+ #define _C2K_UTAS_SUPPORT_ (0)
+ #define _C2K_UTAS_SUPPORT_97 (1)
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#else
+ #define _C2K_TAS_SUPPORT_ (0)
+ #define _C2K_UTAS_SUPPORT_ (0)
+ #define _C2K_UTAS_SUPPORT_97 (0)
+#endif
+
+#define C2K_RF_UTAS_RF_PATH_NUM 2
+#define C2K_RF_UTAS_MAX_SPLIT_BAND_NUM 5
+#define C2K_RF_UTAS_MAX_ANT_NUM 8
+
+#define C2K_ANT_INVALID_PATTERN 0xFF
+#ifdef L1_SIM
+ #if defined(__MD93__)
+ #undef _C2K_TAS_SUPPORT_
+ #define _C2K_TAS_SUPPORT_ (1)
+ #elif defined(__MD95__)
+ #undef _C2K_UTAS_SUPPORT_
+ #define _C2K_UTAS_SUPPORT_ (1)
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #undef _C2K_UTAS_SUPPORT_97
+ #define _C2K_UTAS_SUPPORT_97 (1)
+#endif
+#endif
+
+#define _C2K_TUNER_OLD_ (0)
+
+#define C2K_TAS_BPI_PIN_NULL (-1)
+#define M_ABS(vALUE) (vALUE>=0? vALUE:(-vALUE))
+
+#define C2K_TAS_BPI_PIN_GEN(pIN1eN, pIN2eN, pIN3eN, sETiDX) \
+ ((C2K_TAS_BPI_PIN1_##sETiDX == C2K_TAS_BPI_PIN_NULL ? 0 : ((pIN1eN) << M_ABS(C2K_TAS_BPI_PIN1_##sETiDX))) \
+ |(C2K_TAS_BPI_PIN2_##sETiDX == C2K_TAS_BPI_PIN_NULL ? 0 : ((pIN2eN) << M_ABS(C2K_TAS_BPI_PIN2_##sETiDX))) \
+ |(C2K_TAS_BPI_PIN3_##sETiDX == C2K_TAS_BPI_PIN_NULL ? 0 : ((pIN3eN) << M_ABS(C2K_TAS_BPI_PIN3_##sETiDX))))
+
+typedef enum
+{
+ C2K_TAS_STATE0=0,
+ C2K_TAS_STATE1,
+ C2K_TAS_STATE2,
+ C2K_TAS_STATE3,
+ C2K_TAS_STATE4,
+ C2K_TAS_STATE5,
+ C2K_TAS_STATE6,
+ C2K_TAS_STATE7,
+ #ifndef __MD93__
+ C2K_TAS_STATE8,
+ C2K_TAS_STATE9,
+ C2K_TAS_STATE10,
+ C2K_TAS_STATE11,
+ C2K_TAS_STATE12,
+ C2K_TAS_STATE13,
+ C2K_TAS_STATE14,
+ C2K_TAS_STATE15,
+ C2k_TAS_STATE16,
+ C2K_TAS_STATE17,
+ C2K_TAS_STATE18,
+ C2K_TAS_STATE19,
+ C2K_TAS_STATE20,
+ C2K_TAS_STATE21,
+ C2K_TAS_STATE22,
+ C2K_TAS_STATE23,
+ C2K_TAS_STATE24,
+ C2K_TAS_STATE25,
+ C2K_TAS_STATE26,
+ C2K_TAS_STATE27,
+ C2K_TAS_STATE28,
+ C2K_TAS_STATE29,
+ C2k_TAS_STATE30,
+ C2K_TAS_STATE31,
+ C2K_TAS_STATE32,
+ C2K_TAS_STATE33,
+ C2K_TAS_STATE34,
+ C2K_TAS_STATE35,
+ C2K_TAS_STATE36,
+ C2K_TAS_STATE37,
+ C2K_TAS_STATE38,
+ C2K_TAS_STATE39,
+ C2K_TAS_STATE40,
+ C2K_TAS_STATE41,
+ C2K_TAS_STATE42,
+ C2K_TAS_STATE43,
+ C2K_TAS_STATE44,
+ C2K_TAS_STATE45,
+ C2K_TAS_STATE46,
+ C2K_TAS_STATE47,
+ C2k_TAS_STATE48,
+ C2K_TAS_STATE49,
+ C2K_TAS_STATE50,
+ C2K_TAS_STATE51,
+ C2K_TAS_STATE52,
+ C2K_TAS_STATE53,
+ C2K_TAS_STATE54,
+ C2K_TAS_STATE55,
+ C2k_TAS_STATE56,
+ C2K_TAS_STATE57,
+ C2K_TAS_STATE58,
+ C2K_TAS_STATE59,
+ C2K_TAS_STATE60,
+ C2K_TAS_STATE61,
+ C2K_TAS_STATE62,
+ C2K_TAS_STATE63,
+ #endif
+ C2K_TAS_STATE_MAX,
+ C2K_TAS_STATE_NULL = C2K_ANT_INVALID_PATTERN
+}C2K_CUSTOM_TAS_STATE_E;
+
+typedef enum{
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX0,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX1,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX2,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX3,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX4,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX5,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX6,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX7,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX8,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX9,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX10,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX11,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX12,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX13,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX14,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX15,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX16,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX17,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX18,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX19,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX20,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX21,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX22,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX23,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX24,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX25,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX26,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX27,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX28,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX29,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX30,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX31,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX32,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX33,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX34,
+ C2K_ANT_TUNER_CONTROL_SETTING_INDEX_MAX,
+ C2K_ANT_TUNER_CONTROL_SETTING_NULL = C2K_ANT_INVALID_PATTERN
+}C2K_CUSTOM_ANT_TUNER_CONFIG_SETTING_INDEX_E;
+
+typedef enum
+{
+ C2K_ANT_FE_SWITCH_INDEX,
+ C2K_ANT_FE_TUNER_INDEX,
+ C2K_ANT_FE_CAT_NUM
+}C2K_ANT_FE_CATEGORY_E;
+
+typedef enum{
+ C2K_TAS_VER_1_0 = 0,
+ C2K_TAS_VER_1_5 = 1,
+ C2K_TAS_VER_2_0 = 2,
+ C2K_MAX_TAS_VER_NUM
+}C2K_CUSTOM_TAS_VER_E;
+
+typedef enum{
+ CL1D_NORMAL_MODE = 0,
+ CL1D_META_MODE = 1,
+ CL1D_BOOT_MODE_CAT_NUM
+}C2K_BOOT_MODE_TYPE_E;
+
+typedef struct{
+ kal_bool AT_TAS_SWITCH_Flag;
+}CL1D_RF_TAS_AT_CMD_T;
+
+#endif
diff --git a/mcu/interface/l1/cl1/rfd/cl1d_mmrf_share_data.h b/mcu/interface/l1/cl1/rfd/cl1d_mmrf_share_data.h
new file mode 100644
index 0000000..36b8bbc
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1d_mmrf_share_data.h
@@ -0,0 +1,73 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1D_MMRF_SHARE_DATA_H_
+#define _CL1D_MMRF_SHARE_DATA_H_
+
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*** TAS ***/
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*ELNA*/
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*TX POWER*/
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*TAS TST */
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DECLARE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#include "cl1_nvram_id.h"
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/rfd/cl1d_rf_cid.h b/mcu/interface/l1/cl1/rfd/cl1d_rf_cid.h
new file mode 100644
index 0000000..36a57ce
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1d_rf_cid.h
@@ -0,0 +1,131 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_cid.h
+ *
+ * Project:
+ * --------
+ * 93m
+ *
+ * Description:
+ * ------------
+ * This file contains c2k RF related compile option id.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================*/
+
+
+#ifndef __CL1D_RF_CID_H__
+#define __CL1D_RF_CID_H__
+
+/************************************************************************************
+* Include
+************************************************************************************/
+/*.................................................................*/
+/*............Chip ID definition.............................*/
+/*.................................................................*/
+
+#define CL1D_RF_ID_MT6177M 0x00000001
+#define CL1D_RF_ID_MT6179 0x00000002
+#define CL1D_RF_ID_MT6177L 0x00000004
+#define CL1D_RF_ID_TRINITY_E1 0x00000008
+#define CL1D_RF_ID_MT6185M 0x00000010
+#define CL1D_RF_ID_MT6186 0x00000020
+#define CL1D_RF_ID_MT6186M 0x00000040
+#define CL1D_RF_ID_MT6190T 0x00000080
+#define CL1D_RF_ID_COLUMBUSE2 0x00000100
+#define CL1D_RF_ID_MT6190M 0x00000200
+
+#ifndef CL1D_RF_ID
+ #if defined(MT6177M_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6177M
+ #elif defined(MT6177L_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6177L
+ #elif defined(TRINITYE1_C2K_RF)// || defined(MT6190T_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_TRINITY_E1
+ #elif defined(TRINITYL_C2K_RF) || defined(MT6185M_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6185M
+ #elif defined(MT6186_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6186
+ #elif defined(MT6186M_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6186M
+ #elif defined(MT6190T_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6190T
+ #elif defined(COLUMBUSE2_C2K_RF) || defined(MT6190_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_COLUMBUSE2
+ #elif defined(MT6190M_C2K_RF)
+#define CL1D_RF_ID CL1D_RF_ID_MT6190M
+ #else
+#error "No Valid RF Chip was defined"
+ #endif
+#else
+#error "Unexpected RF Chip was defined"
+#endif
+
+#define IS_CL1D_RF_MT6177M (CL1D_RF_ID == CL1D_RF_ID_MT6177M)
+#define IS_CL1D_RF_MT6177L (CL1D_RF_ID == CL1D_RF_ID_MT6177L)
+#define IS_CL1D_RF_TRINITYE1 (CL1D_RF_ID == CL1D_RF_ID_TRINITY_E1)
+#define IS_CL1D_RF_TRINITYL (CL1D_RF_ID == CL1D_RF_ID_MT6185M)
+#define IS_CL1D_RF_TRINITYLE2 (CL1D_RF_ID == CL1D_RF_ID_MT6186)
+#define IS_CL1D_RF_TRINITY2L (CL1D_RF_ID == CL1D_RF_ID_MT6186M)
+#define IS_CL1D_RF_COLUMBUSE1 (CL1D_RF_ID == CL1D_RF_ID_MT6190T)
+#define IS_CL1D_RF_COLUMBUSE2 (CL1D_RF_ID == CL1D_RF_ID_COLUMBUSE2)
+#define IS_CL1D_RF_MT6190M (CL1D_RF_ID == CL1D_RF_ID_MT6190M) //COLUMBUSL OPTION
+#define IS_C2K_DRDI_SUPPORT defined(__RF_DRDI_CAPABILITY_SUPPORT__)
+
+/*RXDC GxE Dimension (For Lafite(and later) + Trinty-L E2 & Trinity-2L, updated 20180913)*/
+#if defined(__MD95__)
+
+#if defined(MT3967)||defined(MT6295M)
+#define IS_CL1D_RXDC_GXE_SUPPORT (0)
+#else
+#if IS_CL1D_RF_TRINITYE1 || IS_CL1D_RF_TRINITYL
+#define IS_CL1D_RXDC_GXE_SUPPORT (0)
+#else
+#define IS_CL1D_RXDC_GXE_SUPPORT (1)
+#endif
+#endif/*MT3967 or MT6295M*/
+
+#endif/*__MD95__*/
+
+
+#endif /* __CL1D_RF_CID_H__ */
diff --git a/mcu/interface/l1/cl1/rfd/cl1d_rf_common_defs.h b/mcu/interface/l1/cl1/rfd/cl1d_rf_common_defs.h
new file mode 100644
index 0000000..7f10e81
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1d_rf_common_defs.h
@@ -0,0 +1,338 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_common_defs.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * This file containing common definition for RF driver interface.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#ifndef _CL1D_RF_COMMON_DEFS_H_
+#define _CL1D_RF_COMMON_DEFS_H_
+
+#include "kal_general_types.h"
+/*----------------------------------------------------------------------------
+ Global Defines And Macros
+----------------------------------------------------------------------------*/
+#ifndef TRUE
+#define TRUE (1)
+#endif
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+
+#ifndef NULL
+#define NULL ((void* )0)
+#endif
+
+/** PA mode enumeration */
+typedef enum
+{
+ CL1D_RF_PA_MODE_HIGH = 0,
+ CL1D_RF_PA_MODE_MID = 1,
+ CL1D_RF_PA_MODE_LOW = 2,
+ CL1D_RF_PA_MODE_NUM = 3,
+}CL1D_RF_PA_MODE_E;
+
+
+/** LNA mode enumeration */
+typedef enum
+{
+ CL1D_RF_LNA_MODE0 = 0, /**> LNA highest mode*/
+ CL1D_RF_LNA_MODE1 = 1,
+ CL1D_RF_LNA_MODE2 = 2,
+ CL1D_RF_LNA_MODE3 = 3,
+ CL1D_RF_LNA_MODE4 = 4,
+ CL1D_RF_LNA_MODE5 = 5,
+ CL1D_RF_LNA_MODE6 = 6,
+ CL1D_RF_LNA_MODE7 = 7,
+ CL1D_RF_LNA_MODE_NUM = 8,
+}CL1D_RF_LNA_MODE_E;
+
+/** PGA index enumeration */
+typedef enum
+{
+ CL1D_RF_PGA_INDEX0 = 0, /**> PGA highest index*/
+ CL1D_RF_PGA_INDEX1 = 1,
+ CL1D_RF_PGA_INDEX2 = 2,
+ CL1D_RF_PGA_INDEX3 = 3,
+ CL1D_RF_PGA_INDEX4 = 4,
+ CL1D_RF_PGA_INDEX5 = 5,
+ CL1D_RF_PGA_INDEX6 = 6, /** only for Tier1 mode*/
+ CL1D_RF_PGA_INDEX7 = 7, /** only for Tier1 mode*/
+ CL1D_RF_PGA_INDEX_NUM = 8,
+}CL1D_RF_PGA_INDEX_E;
+
+/* --------------- ELT LOGGING ------------------*/
+/* For RXDFE logging */
+typedef enum
+{
+ RF_TST_RXDFE_FC_TQ = 0,
+ RF_TST_RXDFE_FC_IMM,
+ RF_TST_RXDFE_FC_ACT,
+ RF_TST_RXDFE_FC_WBUF,
+ RF_TST_RXDFE_FC_CALTC,
+
+ RF_TST_RXDFE_STIME,
+ RF_TST_RXDFE_ATIME,
+
+ RF_TST_RXDFE_FC_NUM
+} CL1_RF_TST_RXDFE_RG_TYPE_E;
+
+typedef enum
+{
+ RF_TST_TXDFE_DBG_REG = 0,
+ RF_TST_TXDFE_COMP_DC_FI,
+ RF_TST_TXDFE_COMP_ASYMM,
+ RF_TST_TXDFE_COMP_FDAD,
+ RF_TST_TXDFE_AM_PM_LUT,
+ RF_TST_TXDFE_TPC_COMN,
+
+ RF_TST_TXDFE_STIME,
+
+ RF_TST_TXDFE_FC_NUM
+} CL1_RF_TST_TXDFE_RG_TYPE_E;
+
+typedef enum
+{
+ RF_TST_TXKDFE_DBG_REG = 0,
+ RF_TST_TXKDFE_REF_DBG,
+ RF_TST_TXKDFE_DET_DBG,
+
+ RF_TST_TXKDFE_FC_NUM
+} CL1_RF_TST_TXKDFE_RG_TYPE_E;
+/* --------------- ELT LOGGING ------------------*/
+
+
+/** C2K RF frequency band type enumeration */
+typedef enum
+{
+ CL1D_RF_FREQ_LOW_BAND = 0,
+ CL1D_RF_FREQ_HIGH_BAND = 1,
+ CL1D_RF_FREQ_BAND_NUM = 2
+}CL1D_RF_FREQ_BAND_E;
+
+typedef enum
+{
+ RF_Band_A=0,
+ RF_Band_B,
+ RF_Band_C,
+ RF_Band_D,
+ RF_Band_E,
+ RF_Band_NUM_MAX,
+ RF_Band_ERR
+}CL1D_RF_BAND_E;
+
+typedef enum
+{
+///TODO: need to be confirmed !
+ RF_RAT_1XRTT=0,
+ RF_RAT_EVDO,
+ RF_RAT_NUM,
+ RF_RAT_INVALID
+}CL1D_RF_RAT_E;
+
+/* define Cdma Band type */
+typedef enum
+{
+ CL1D_RF_BAND_CLASS_0 = 0, /* 800 MHz cellular band */
+ CL1D_RF_BAND_CLASS_1, /* 1.8 to 2.0 GHz band */
+ CL1D_RF_BAND_CLASS_2, /* 872 to 960 MHz TACS band */
+ CL1D_RF_BAND_CLASS_3, /* 832 to 925 MHz JTACS band */
+ CL1D_RF_BAND_CLASS_4, /* 1.75 to 1.87 GHz Korean PCS */
+ CL1D_RF_BAND_CLASS_5, /* 450 MHz NMT band */
+ CL1D_RF_BAND_CLASS_6, /* 2 GHz IMT-2000 band */
+ CL1D_RF_BAND_CLASS_7, /* 700 MHz band */
+ CL1D_RF_BAND_CLASS_8, /* 1800 MHz band */
+ CL1D_RF_BAND_CLASS_9, /* 900 MHz band */
+ CL1D_RF_BAND_CLASS_10, /* Secondary 800 MHz NMT band */
+ CL1D_RF_BAND_CLASS_11, /* 400 MHz European PARM band */
+ CL1D_RF_BAND_CLASS_12, /* 800 MHz PAMR band */
+ CL1D_RF_BAND_CLASS_13, /* 2.5 GHz IMT-2000 */
+ CL1D_RF_BAND_CLASS_14, /* US PCS 1.9 GHz band */
+ CL1D_RF_BAND_CLASS_15, /* AWS band */
+ CL1D_RF_BAND_CLASS_16, /* US 2.5 GHz band */
+ CL1D_RF_BAND_CLASS_17, /* US 2.5GHz Forward Link Only Band */
+ CL1D_RF_BAND_CLASS_18, /* 700 MHz Public Safety Band */
+ CL1D_RF_BAND_CLASS_19, /* Lower 700 MHz Band */
+ CL1D_RF_BAND_CLASS_20, /* L-Band */
+ CL1D_RF_BAND_CLASS_MAX,
+ CL1D_RF_BAND_CLASS_NOT_USED = CL1D_RF_BAND_CLASS_MAX,
+ CL1D_RF_BAND_CLASS_UNSUPPORTED /* MUST be DIFFERENT than CL1D_RF_BAND_CLASS_MAX / CL1D_RF_BAND_CLASS_NOT_USED */
+} CL1D_RF_BAND_CLASS_TYPE_E;
+
+#define CL1D_RF_SUB_CLASS_MAX 16
+
+#define CL1D_RF_SUB_CLASS_0_SUPPORTED 0x80000000
+#define CL1D_RF_SUB_CLASS_1_SUPPORTED (1<<30)
+#define CL1D_RF_SUB_CLASS_2_SUPPORTED (1<<29)
+#define CL1D_RF_SUB_CLASS_3_SUPPORTED (1<<28)
+#define CL1D_RF_SUB_CLASS_4_SUPPORTED (1<<27)
+#define CL1D_RF_SUB_CLASS_5_SUPPORTED (1<<26)
+#define CL1D_RF_SUB_CLASS_6_SUPPORTED (1<<25)
+#define CL1D_RF_SUB_CLASS_7_SUPPORTED (1<<24)
+#define CL1D_RF_SUB_CLASS_8_SUPPORTED (1<<23)
+#define CL1D_RF_SUB_CLASS_9_SUPPORTED (1<<22)
+#define CL1D_RF_SUB_CLASS_10_SUPPORTED (1<<21)
+#define CL1D_RF_SUB_CLASS_11_SUPPORTED (1<<20)
+#define CL1D_RF_SUB_CLASS_12_SUPPORTED (1<<19)
+#define CL1D_RF_SUB_CLASS_13_SUPPORTED (1<<18)
+#define CL1D_RF_SUB_CLASS_14_SUPPORTED (1<<17)
+#define CL1D_RF_SUB_CLASS_15_SUPPORTED (1<<16)
+
+#define CL1D_RF_SUB_CLASS_0_UNSUPPORTED (0<<31)
+#define CL1D_RF_SUB_CLASS_1_UNSUPPORTED (0<<30)
+#define CL1D_RF_SUB_CLASS_2_UNSUPPORTED (0<<29)
+#define CL1D_RF_SUB_CLASS_3_UNSUPPORTED (0<<28)
+#define CL1D_RF_SUB_CLASS_4_UNSUPPORTED (0<<27)
+#define CL1D_RF_SUB_CLASS_5_UNSUPPORTED (0<<26)
+#define CL1D_RF_SUB_CLASS_6_UNSUPPORTED (0<<25)
+#define CL1D_RF_SUB_CLASS_7_UNSUPPORTED (0<<24)
+#define CL1D_RF_SUB_CLASS_8_UNSUPPORTED (0<<23)
+#define CL1D_RF_SUB_CLASS_9_UNSUPPORTED (0<<22)
+#define CL1D_RF_SUB_CLASS_10_UNSUPPORTED (0<<21)
+#define CL1D_RF_SUB_CLASS_11_UNSUPPORTED (0<<20)
+#define CL1D_RF_SUB_CLASS_12_UNSUPPORTED (0<<19)
+#define CL1D_RF_SUB_CLASS_13_UNSUPPORTED (0<<18)
+#define CL1D_RF_SUB_CLASS_14_UNSUPPORTED (0<<17)
+#define CL1D_RF_SUB_CLASS_15_UNSUPPORTED (0<<16)
+
+#define CL1D_RF_SUB_CLASS_ALL_SUPPORTED 0xffff0000
+#define CL1D_RF_SUB_CLASS_NONE_SUPPORTED 0x00000000
+
+#ifndef BIT0
+#define BIT0 0x01
+#define BIT1 0x02
+#define BIT2 0x04
+#define BIT3 0x08
+#define BIT4 0x10
+#define BIT5 0x20
+#define BIT6 0x40
+#define BIT7 0x80
+#define BIT8 0x100
+#define BIT9 0x200
+#define BIT10 0x400
+#define BIT11 0x800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+#define BIT16 0x10000UL
+#define BIT17 0x20000UL
+#define BIT18 0x40000UL
+#define BIT19 0x80000UL
+#define BIT20 0x100000UL
+#define BIT21 0x200000UL
+#define BIT22 0x400000UL
+#define BIT23 0x800000UL
+#define BIT24 0x1000000UL
+#define BIT25 0x2000000UL
+#define BIT26 0x4000000UL
+#define BIT27 0x8000000UL
+#define BIT28 0x10000000UL
+#define BIT29 0x20000000UL
+#define BIT30 0x40000000UL
+#define BIT31 0x80000000UL
+#endif
+
+/* Handy macros */
+#ifndef MAX
+#define MAX(x,y) (( (x) > (y) ) ? (x) : (y))
+#endif
+
+#ifndef MIN
+#define MIN(x,y) (( (x) < (y) ) ? (x) : (y))
+#endif
+
+#ifndef M_Q9
+#define M_Q9(vALUE) ((kal_int32)((vALUE) * (1 << 9)))
+#endif
+
+#ifndef M_Q9ToQ0
+#define M_Q9ToQ0(vALUE) ((vALUE) >> 9)
+#endif
+
+/** uS and nS to C2K chips: 1 c2k chip = 1/1.228 uS */
+#ifndef M_UsToChips
+#define M_UsToChips(uS) (((uS) * 1228 + 1000 - 1) / 1000)
+#endif
+
+#ifndef M_NsToChips
+#define M_NsToChips(nS) (((nS) * 1228 * 1000 + 1000 * 1000 - 1) / 1000 * 1000)
+#endif
+
+#ifndef M_ChipsToUs
+#define M_ChipsToUs(cHIPS) (((cHIPS) * 1000 + 1228 - 1) / 1228)
+#endif
+
+#ifndef M_UsToChips8x
+#define M_UsToChips8x(uS) (((uS) * 1228)*8 / 1000)
+#endif
+
+
+/* Internal options */
+#ifndef L1_SIM
+#define __CL1_RF_IT_ON_TARGET__ 1
+#else
+#undef __CL1_RF_IT_ON_TARGET__
+#endif
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/rfd/cl1d_rf_public.h b/mcu/interface/l1/cl1/rfd/cl1d_rf_public.h
new file mode 100644
index 0000000..3988d1b
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1d_rf_public.h
@@ -0,0 +1,1976 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_public.h
+ *
+ * Project:
+ * --------
+ * C2K
+ *
+ * Description:
+ * ------------
+ * Header file containing typedefs and definitions pertaining
+ * to C2K RF driver external interface.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#ifndef _CL1D_RF_PUBLIC_H_
+#define _CL1D_RF_PUBLIC_H_
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+
+#include "sysdefs.h"
+#include "kal_general_types.h"
+#include "cl1_rf_poc_public.h"
+#include "cl1d_rf_common_defs.h"
+#include "cl1_rf_tas_public.h"
+#include "cl1_rf_elna_public.h"
+#include "cl1_rf_public.h"
+
+/*----------------------------------------------------------------------------
+ Global Defines And Macros
+----------------------------------------------------------------------------*/
+#define CL1D_RF_SUB_CLASS_MAX 16
+
+#define CL1D_RF_SUB_CLASS_0_SUPPORTED 0x80000000
+#define CL1D_RF_SUB_CLASS_1_SUPPORTED (1<<30)
+#define CL1D_RF_SUB_CLASS_2_SUPPORTED (1<<29)
+#define CL1D_RF_SUB_CLASS_3_SUPPORTED (1<<28)
+#define CL1D_RF_SUB_CLASS_4_SUPPORTED (1<<27)
+#define CL1D_RF_SUB_CLASS_5_SUPPORTED (1<<26)
+#define CL1D_RF_SUB_CLASS_6_SUPPORTED (1<<25)
+#define CL1D_RF_SUB_CLASS_7_SUPPORTED (1<<24)
+#define CL1D_RF_SUB_CLASS_8_SUPPORTED (1<<23)
+#define CL1D_RF_SUB_CLASS_9_SUPPORTED (1<<22)
+#define CL1D_RF_SUB_CLASS_10_SUPPORTED (1<<21)
+#define CL1D_RF_SUB_CLASS_11_SUPPORTED (1<<20)
+#define CL1D_RF_SUB_CLASS_12_SUPPORTED (1<<19)
+#define CL1D_RF_SUB_CLASS_13_SUPPORTED (1<<18)
+#define CL1D_RF_SUB_CLASS_14_SUPPORTED (1<<17)
+#define CL1D_RF_SUB_CLASS_15_SUPPORTED (1<<16)
+
+#define CL1D_RF_SUB_CLASS_0_UNSUPPORTED (0<<31)
+#define CL1D_RF_SUB_CLASS_1_UNSUPPORTED (0<<30)
+#define CL1D_RF_SUB_CLASS_2_UNSUPPORTED (0<<29)
+#define CL1D_RF_SUB_CLASS_3_UNSUPPORTED (0<<28)
+#define CL1D_RF_SUB_CLASS_4_UNSUPPORTED (0<<27)
+#define CL1D_RF_SUB_CLASS_5_UNSUPPORTED (0<<26)
+#define CL1D_RF_SUB_CLASS_6_UNSUPPORTED (0<<25)
+#define CL1D_RF_SUB_CLASS_7_UNSUPPORTED (0<<24)
+#define CL1D_RF_SUB_CLASS_8_UNSUPPORTED (0<<23)
+#define CL1D_RF_SUB_CLASS_9_UNSUPPORTED (0<<22)
+#define CL1D_RF_SUB_CLASS_10_UNSUPPORTED (0<<21)
+#define CL1D_RF_SUB_CLASS_11_UNSUPPORTED (0<<20)
+#define CL1D_RF_SUB_CLASS_12_UNSUPPORTED (0<<19)
+#define CL1D_RF_SUB_CLASS_13_UNSUPPORTED (0<<18)
+#define CL1D_RF_SUB_CLASS_14_UNSUPPORTED (0<<17)
+#define CL1D_RF_SUB_CLASS_15_UNSUPPORTED (0<<16)
+
+#define CL1D_RF_SUB_CLASS_ALL_SUPPORTED 0xffff0000
+#define CL1D_RF_SUB_CLASS_NONE_SUPPORTED 0x00000000
+
+
+#define CL1D_RF_RXDFE_NBIF_NUM (3)
+
+/** RFD NV operation */
+#define CL1D_RF_NV_LOCAL (1 << 0)
+#define CL1D_RF_NV_NVRAM (1 << 1)
+#define CL1D_RF_NV_INIT (1 << 2)
+/* Return status */
+#define CL1D_RF_NV_SUCCESS (0)
+#define CL1D_RF_NV_FAIL (-1)
+
+#define CL1D_RF_NUM_RAMP_LEVEL 16
+#define CL1D_RXDFE_DUMP_ENA 1
+
+/** C2K test mode enumeration */
+typedef enum
+{
+ CL1D_RF_RX_TEST_MODE = 0,
+ CL1D_RF_TX_TEST_MODE = 1,
+ CL1D_RF_META_MODE = 2,
+}CL1D_RF_TEST_MODE_E;
+
+
+/** C2K temperature enumeration */
+typedef enum
+{
+ CL1D_RF_TMP_STOP = 0,
+ CL1D_RF_TMP_START = 1,
+ CL1D_RF_TMP_IMM = 2,
+ CL1D_RF_TMP_MODE_NUM
+}CL1D_RF_TMP_MODE_E;
+
+
+/** RF Path type enumeration */
+typedef enum
+{
+ CL1D_RF_MAIN_RX = 0,
+ CL1D_RF_DIV_RX ,
+ CL1D_RF_SEC_RX ,
+ CL1D_RF_MAX_NUM_OF_RX ,
+ CL1D_RF_TX = CL1D_RF_MAX_NUM_OF_RX,
+ CL1D_RF_MAX_NUM_OF_TXRX,
+ CL1D_RF_MAX_NUM_OF_TX =CL1D_RF_MAX_NUM_OF_TXRX-CL1D_RF_MAX_NUM_OF_RX,
+}CL1D_RF_PATH_E;
+
+/** RF power mode enumeration */
+typedef enum
+{
+ CL1D_RF_HPM = 0,
+ CL1D_RF_LPM = 1,
+ CL1D_RF_MAX_NUM_OF_PM = 2,
+}CL1D_RF_PWR_MODE_E;
+
+/** RxAGC gain history record index enumeration */
+typedef enum
+{
+ CL1D_RF_RXAGC_HISTORY_REC_IDX0 = 0,
+ CL1D_RF_RXAGC_HISTORY_REC_IDX1,
+ CL1D_RF_RXAGC_HISTORY_REC_IDX2,
+ CL1D_RF_RXAGC_HISTORY_REC_IDX3,
+ CL1D_RF_RXAGC_HISTORY_REC_IDX4,
+ CL1D_RF_RXAGC_HISTORY_REC_NUM,
+ CL1D_RF_RXAGC_HISTORY_REC_IDX_INVALID = 0xFF,
+}CL1D_RF_RXAGC_HISTORY_REC_IDX_E;
+
+#ifdef MTK_DEV_TEMP_C2K_OTFC
+/** Tx DPD OTFC history record index enumeration */
+typedef enum
+{
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX0 = 0,
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX1,
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX2,
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX3,
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX4,
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_NUM,
+ CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX_INVALID = 0xFF,
+}CL1D_RF_TX_DPD_OTFC_HISTORY_REC_IDX_E;
+#endif
+
+/** C2K TX AGC test mode type enumeration */
+typedef enum
+{
+ CL1D_RF_TPC_TEST_MODE_FIXPWR = 0,
+ CL1D_RF_TPC_TEST_MODE_MANUAL = 1,
+ CL1D_RF_TPC_TEST_MODE_FDB = 2
+}CL1D_RF_TPC_TEST_MODE_E;
+
+/** C2K RX AGC test mode type enumeration */
+typedef enum
+{
+ CL1D_RF_AGC_TEST_MODE_FIXGAIN = 0,
+ CL1D_RF_AGC_TEST_MODE_MANUAL = 1
+}CL1D_RF_AGC_TEST_MODE_E;
+
+/** C2K RX AGC FSM type enumeration */
+typedef enum
+{
+ CL1D_RF_AGC_FSM_FAST = 0,
+ CL1D_RF_AGC_FSM_STEADY = 1,
+ CL1D_RF_AGC_FSM_ICS = 2,
+ CL1D_RF_AGC_FSM_CAL = 3,
+ CL1D_RF_AGC_FSM_FIX_GAIN = 4,
+ CL1D_RF_AGC_FSM_NUM = 5
+}CL1D_RF_AGC_FSM_E;
+
+/** C2K NBIF rounding mode enumeration */
+typedef enum
+{
+ CL1D_RF_RXDFE_NBIF_ROUND_MODE_6 = 0, /* shift 6, round 3 */
+ CL1D_RF_RXDFE_NBIF_ROUND_MODE_7 = 1, /* shift 7, round 4 */
+ CL1D_RF_RXDFE_NBIF_ROUND_MODE_8 = 2, /* shift 8, round 5 */
+ CL1D_RF_RXDFE_NBIF_ROUND_MODE_9 = 3, /* shift 9, round 6 */
+ CL1D_RF_RXDFE_NBIF_ROUND_MODE_10 = 4 /* shift 10, round 7 */
+
+}CL1D_RF_RXDFE_NBIF_ROUND_MODE_E;
+
+/** C2K RXDFE Path enumeration */
+#if defined(__MD95__)
+typedef enum
+{
+ RF_RXDFE_MAIN_ON,
+ RF_RXDFE_MAIN_OFF,
+ RF_RXDFE_DIV_ON,
+ RF_RXDFE_DIV_OFF,
+ RF_RXDFE_MAIN_PART_ON,
+ RF_RXDFE_MAIN_PART_OFF,
+ RF_RXDFE_DIV_PART_ON,
+ RF_RXDFE_DIV_PART_OFF,
+ RF_RXDFE_MAIN_DIV_ON,
+ RF_RXDFE_MAIN_DIV_OFF,
+ RF_RXDFE_SEC_ON,
+ RF_RXDFE_SEC_OFF,
+ RF_RXDFE_MS_MAIN_DIV_ON,
+ RF_RXDFE_MS_SEC_ON,
+
+ RF_RXDFE_MAIN = RF_RXDFE_MAIN_ON,
+ RF_RXDFE_DIV = RF_RXDFE_DIV_ON,
+ RF_RXDFE_SEC = RF_RXDFE_SEC_ON,
+}CL1D_RF_RXDFE_SENARIO_E;
+#elif defined(__MD93__)
+typedef enum
+{
+ RF_RXDFE_MAIN_ON,
+ RF_RXDFE_MAIN_OFF,
+ RF_RXDFE_DIV_ON,
+ RF_RXDFE_DIV_OFF,
+ RF_RXDFE_MAIN_PART_ON,
+ RF_RXDFE_MAIN_PART_OFF,
+ RF_RXDFE_DIV_PART_ON,
+ RF_RXDFE_DIV_PART_OFF,
+ RF_RXDFE_MAIN_DIV_ON,
+ RF_RXDFE_MAIN_DIV_OFF,
+ RF_RXDFE_SEC_ON,
+ RF_RXDFE_SEC_OFF,
+
+ RF_RXDFE_MAIN = RF_RXDFE_MAIN_ON,
+ RF_RXDFE_DIV = RF_RXDFE_DIV_ON,
+ RF_RXDFE_SEC = RF_RXDFE_SEC_ON,
+}CL1D_RF_RXDFE_SENARIO_E;
+#elif (defined(__MD97__) || defined(__MD97P__))
+typedef enum
+{
+ RF_RXDFE_MAIN_ON,
+ RF_RXDFE_MAIN_OFF,
+ RF_RXDFE_DIV_ON,
+ RF_RXDFE_DIV_OFF,
+ RF_RXDFE_MAIN_PART_ON,
+ RF_RXDFE_MAIN_PART_OFF,
+ RF_RXDFE_DIV_PART_ON,
+ RF_RXDFE_DIV_PART_OFF,
+ RF_RXDFE_MAIN_DIV_ON,
+ RF_RXDFE_MAIN_DIV_OFF,
+ RF_RXDFE_SEC_ON,
+ RF_RXDFE_SEC_OFF,
+ RF_RXDFE_MS_MAIN_DIV_ON,
+ RF_RXDFE_MS_SEC_ON,
+
+ RF_RXDFE_MAIN = RF_RXDFE_MAIN_ON,
+ RF_RXDFE_DIV = RF_RXDFE_DIV_ON,
+ RF_RXDFE_SEC = RF_RXDFE_SEC_ON,
+}CL1D_RF_RXDFE_SENARIO_E;
+
+#endif
+
+/** C2K TXDFE Path enumeration */
+typedef enum
+{
+ RF_TXDFE_ON,
+ RF_TXDFE_OFF,
+ RF_TXDFE_GATE_ON,
+ RF_TXDFE_GATE_OFF,
+}CL1D_RF_TXDFE_SENARIO_E;
+
+/** C2K RXDFE Test out IQ data dump point*/
+typedef enum
+{
+ CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_SRRC,
+ CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_DAGC,
+ CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_SRC,
+ CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_CS,
+ CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_NUM
+
+}CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_E;
+
+/** C2K TX ON/OFF RF/TPC CTRL enumeration */
+typedef enum
+{
+ CL1D_RF_TX_ON_RF_TPC_CTRL_RF_ON_TPC_INIT = 0,
+ CL1D_RF_TX_ON_RF_TPC_CTRL_RF_ON_TPC_GATE_ON = 1,
+} CL1D_RF_TX_ON_RF_TPC_CTRL_E;
+
+typedef enum
+{
+ CL1D_RF_TX_OFF_RF_TPC_CTRL_RF_OFF_TPC_OFF = 0,
+ CL1D_RF_TX_OFF_RF_TPC_CTRL_RF_OFF_TPC_GATE_OFF = 1,
+ CL1D_RF_TX_OFF_RF_TPC_CTRL_TPC_OFF = 2,
+} CL1D_RF_TX_OFF_RF_TPC_CTRL_E;
+
+typedef enum {
+ RXDFE_FC_CFG_NBIF,
+ RXDFE_FC_CFG_NCO,
+ RXDFE_FC_CFG_RFC,
+ RXDFE_FC_CFG_NCO_CAL,
+ RXDFE_FC_CFG_DC_CAL,
+ RXDFE_FC_CFG_IRR_CAL,
+ RXDFE_FC_CFG_NUM
+}CL1D_RF_RXDFE_FC_CFG_TYPE_E;
+
+typedef enum
+{
+ C_TX_DDL_CHECK = 0x43000000,
+ C_TX_PM_DL_START,
+ C_TX_S_U_TIME_SYNC,
+ C_TX_CTRL_TIME_SYNC,
+
+ C_TX_DMA_CHECK = 0x43000010,
+ C_TX_GDMA_CHECK,
+
+ C_TX_PATHON_CHECK = 0x43000020,
+ C_TX_PATHOFF_CHECK,
+
+ C_TX_CFG_TIME_WARNNING = 0x43000030,
+
+ C_TX_CFG_RAT_CHECK = 0x43000040,
+ C_TX_CFG_CMD_CHECK,
+ C_TX_CFG_BUF_CHECK ,
+ C_TX_CFG_GATE_CHECK ,
+
+ C_TX_CFG_BACKOFF_CHECK = 0x43000050,
+
+ C_TX_CFG_D_TQ_CHECK = 0x43000060,
+ C_TX_CFG_D_GC_CHECK,
+
+ C_TX_CFG_A_TQ_CHECK = 0x43000070,
+ C_TX_CFG_A_GC_CHECK,
+}C2K_TPC_BANNER_TRACE_ID_E;
+
+#if CL1D_RXDFE_DUMP_ENA
+typedef enum
+{
+ RXDFE_DUMP_A_MIXED_IF_OUTPUT = 0 , //0
+ RXDFE_DUMP_A_CIC_S1 , //1
+ RXDFE_DUMP_A_DCOC_OUTPUT , //2
+ RXDFE_DUMP_A_PRE_NCO_FIR_NR , //3
+ RXDFE_DUMP_A_PRE_NCO_FIR_WTC , //4
+ RXDFE_DUMP_A_PATH_DEC_OUTPUT , //5
+ RXDFE_DUMP_A_RFEQ_OUTPUT , //6
+ RXDFE_DUMP_A_FDPM_OUTPUT , //7
+ RXDFE_DUMP_A_IQC_OUTPUT , //8
+ RXDFE_DUMP_A_NBIF_OUTPUT , //9
+ RXDFE_DUMP_A_PATH_OUTPUT , //10
+ RXDFE_DUMP_A_L_START_OUTPUT , //11
+ RXDFE_DUMP_A_NCO_OUTPUT = RXDFE_DUMP_A_L_START_OUTPUT,
+ RXDFE_DUMP_A_L_PostNCO_OUTPUT , //12,
+ RXDFE_DUMP_A_SRRC_PNAAF_OUTPUT , //13,
+ RXDFE_DUMP_A_LWC_DAGC_OUTPUT , //14,
+ RXDFE_DUMP_A_PRE_2X_HB , //15,
+ RXDFE_DUMP_A_SRC_OUTPUT , //16,
+ RXDFE_DUMP_A_FC_OUT , //17,
+ RXDFE_DUMP_D_FC_IN , //18,
+ RXDFE_DUMP_D_PRE_2X_HB , //19,
+ RXDFE_DUMP_D_DDSSRC , //20,
+ RXDFE_DUMP_D_DSRC , //21,
+ RXDFE_DUMP_D_LAYER_OUT , //22,
+ RXDFE_DUMP_D_CS_NCO , //23,
+ RXDFE_DUMP_D_CS_FIR , //24,
+ RXDFE_DUMP_D_CS_DAGC , //25,
+ RXDFE_DUMP_D_CS_OUTPUT , //26,
+ RXDFE_DUMP_D_PBCH_OUT , //27,
+ RXDFE_DUMP_D_SSS_OUT , //28,
+ RXDFE_DUMP_NODE_NUM , //29,
+ RXDFE_DUMP_D_START = RXDFE_DUMP_D_FC_IN -6,
+}CL1D_RF_RXDFE_DUMP_NODE_E;
+
+typedef enum
+{
+ RXDFE_TTG_CIC,
+ RXDFE_TTG_RFEQ,
+ RXDFE_TTG_P = RXDFE_TTG_RFEQ,
+ RXDFE_TTG_HB,
+ RXDFE_TTG_SRC,
+ RXDFE_TTG_NUM
+}CL1D_RF_RXDFE_TTG_IN_E;
+typedef enum
+{
+ TXDFE_FDAD_OUTPUT, //TBD BY WATSON
+}CL1D_RF_TXDFE_DUMP_NODE_E;
+#endif
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+/* This structure describes the support for a particular bandclass.
+ The Subclass element is a bitmap field with each bit indicating support
+ for a particular subclass. The Supported element indicates in general
+ support for a specific band class
+*/
+typedef struct CL1D_RF_SUPPORTED_BAND_INFO_tag
+{
+ kal_uint32 subclass;
+ kal_uint16 supported;
+} CL1D_RF_SUPPORTED_BAND_INFO_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Get_Platform_Info() function. */
+typedef struct CL1D_RF_GET_PLATFORM_INFO_tag
+{
+ /** [out] - RF chip ID */
+ kal_uint16 rf_chip_id;
+ /** [out] - total suported band class number */
+ kal_uint16 support_bc_num;
+ /** [out] - suported band class info */
+ CL1D_RF_SUPPORTED_BAND_INFO_T support_bc_info[SYS_BAND_CLASS_MAX];
+ /** [out] - diversity supported status,1: support, 0:not support */
+ kal_uint16 diversity_en[SYS_BAND_CLASS_MAX];
+ /** [out] - diversity only test feature supported status,1: support, 0:not support */
+ kal_uint16 diversity_only_test_en[SYS_BAND_CLASS_MAX];
+ /** [out] - RX path number */
+ kal_uint16 rx_path_num;
+ /** [out] - RX synthesizer number */
+ kal_uint16 rx_synth_num;
+ /** [out] - TX path number */
+ kal_uint16 tx_path_num;
+ /** [out] - TX synthesizer number */
+ kal_uint16 tx_synth_num;
+ /** [out] - high power mode LNA number */
+ kal_uint16 hpm_lna_num;
+ /** [out] - low power mode LNA number */
+ kal_uint16 lpm_lna_num;
+ /** [out] - the HRT of RXON in us unit*/
+ kal_uint16 rxon_hrt;
+ /** [out] - the HRT of RXOFF in us unit */
+ kal_uint16 rxoff_hrt;
+ /** [out] - the HRT of TXON in us unit */
+ kal_uint16 txon_hrt;
+ /** [out] - the HRT of TXOFF in us unit */
+ kal_uint16 txoff_hrt;
+ /** [out] - the AGPS Group Delay in ns unit */
+ kal_int32 agps_group_delay[SYS_BAND_CLASS_MAX];
+ /** [out] - dpd enable status,1: enable, 0:disable */
+ kal_uint16 dpd_en[SYS_BAND_CLASS_MAX];
+
+} CL1D_RF_GET_PLATFORM_INFO_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Synth_Offset_Update() function. */
+typedef struct CL1D_RF_AFC_SYNTH_OFFSET_UPDATE_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value of tuning RF PLL frequency, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - CL1D_RF_PATH_E enum type of RF path */
+ kal_uint8 path_type;
+ /** [in] - total frequency offset error in Hz */
+ kal_int32 foe_hz;
+} CL1D_RF_AFC_SYNTH_OFFSET_UPDATE_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Init_Foe_Ppb_Query() function. */
+typedef struct CL1D_RF_AFC_INIT_FOE_PPB_QUERY_tag
+{
+ /** [out] - total frequency offset error in ppb*/
+ kal_int32 foe_ppb;
+} CL1D_RF_AFC_INIT_FOE_PPB_QUERY_T;
+
+/** s-curve structure. */
+#ifndef __MD93__
+typedef struct CL1D_RF_AFC_S_CURVE_tag
+{
+ kal_int32 c0Fac;
+ kal_int32 c1Fac;
+ kal_int32 c2Fac;
+ kal_int32 c3Fac;
+} CL1D_RF_AFC_S_CURVE_T;
+#else
+typedef struct CL1D_RF_AFC_S_CURVE_tag
+{
+ float c0Fac;
+ float c1Fac;
+ float c2Fac;
+ float c3Fac;
+} CL1D_RF_AFC_S_CURVE_T;
+#endif
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_S_Curve_Param_Query() function. */
+typedef struct CL1D_RF_AFC_S_CURVE_PARAM_QUERY_tag
+{
+ /** [out] - Pointer of s-curve structure*/
+ CL1D_RF_AFC_S_CURVE_T s_curve;
+} CL1D_RF_AFC_S_CURVE_PARAM_QUERY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Foe_Ppb_To_Dac() function. */
+typedef struct CL1D_RF_AFC_FOE_PPB_TO_DAC_tag
+{
+ /** [in] - total frequency offset error in ppb*/
+ kal_int32 foe_ppb;
+ /** [out] - AFC DAC value*/
+ kal_uint32 afc_dac;
+} CL1D_RF_AFC_FOE_PPB_TO_DAC_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Dac_To_Foe_Ppb() function. */
+typedef struct CL1D_RF_AFC_DAC_TO_FOE_PPB_tag
+{
+ /** [in] - AFC DAC value*/
+ kal_uint32 afc_dac;
+ /** [out] - total frequency offset error in ppb*/
+ kal_int32 foe_ppb;
+} CL1D_RF_AFC_DAC_TO_FOE_PPB_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Rx_Channel_To_Frequency() function. */
+typedef struct CL1D_RF_AFC_RX_CHANNEL_TO_FREQUENCY_tag
+{
+ /** [in] - 3GPP2 band class*/
+ kal_uint8 band_class;
+ /** [in] - channel number*/
+ kal_uint16 channel;
+ /** [out] - frequency in KHz unit*/
+ kal_int32 freq_khz;
+} CL1D_RF_AFC_RX_CHANNEL_TO_FREQUENCY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Tx_Channel_To_Frequency() function. */
+typedef struct CL1D_RF_AFC_TX_CHANNEL_TO_FREQUENCY_tag
+{
+ /** [in] - 3GPP2 band class*/
+ kal_uint8 band_class;
+ /** [in] - channel number*/
+ kal_uint16 channel;
+ /** [out] - frequency in KHz unit*/
+ kal_int32 freq_khz;
+} CL1D_RF_AFC_TX_CHANNEL_TO_FREQUENCY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Cap_Id_Update() function. */
+typedef struct CL1D_RF_AFC_CAP_ID_UPDATE_tag
+{
+ /** [in] - cap ID*/
+ kal_uint8 cap_id;
+} CL1D_RF_AFC_CAP_ID_UPDATE_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AFC_Dac_Update() function. */
+typedef struct CL1D_RF_AFC_DAC_UPDATE_tag
+{
+ /** [in] - AFC DAC value*/
+ kal_uint16 afc_dac;
+} CL1D_RF_AFC_DAC_UPDATE_T;
+
+
+/** Ads structure to provide parameters to the CL1D_RF_Temperature_Query() function. */
+typedef struct CL1D_RF_TEMPERATURE_QUERY_tag
+{
+ /** [in] - 0: From RF for RF temperature compensation
+ 1: From PMIC for AFC temperature compensation
+ */
+ kal_uint8 temp_type;
+ /** [out] - Temperature value in Celsius*/
+ kal_int16 temperature;
+} CL1D_RF_TEMPERATURE_QUERY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Tx_Path_On() function. */
+typedef struct CL1D_RF_TX_PATH_ON_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [in] - time of on air TX on with HRT in RX stimer, unit: echip, range: 0~0xBFFFF*/
+ kal_uint32 rx_stime;
+ /** [in] - time of on air TX boundary in TX stimer, unit: echip, range: 0~0xBFFFF*/
+ kal_uint32 tx_stime;
+ /** [in] - 3GPP2 band class*/
+ kal_uint8 band_class;
+ /** [in] - channek number*/
+ kal_uint16 channel;
+ /** [in] - total frequency offset error in Hz*/
+ kal_int32 foe_hz;
+ /** [in] - power reference used for open loop estimation in 1/64dBm@S9.6 unit*/
+ kal_int16 pwr_ref;
+ /** [in] - RSSI value with filter in 1/64dBm@S7.6 unit*/
+ kal_int16 rssi_wi_filter;
+ /** [in] - open loop correct gain with S0.16 unit*/
+ kal_int32 ol_corr_gain;
+ /** [in] - open loop max slew with S2.6 unit*/
+ kal_int32 ol_max_slew;
+ /** [in] - RPC combine threshold with U5.0, only for 1XRTT*/
+ kal_uint16 rpc_comb_thr;
+ /** [in] - TXAGC SW mode control, 1: sw mode; 0: normal mode. bit[7:0] rpc_bit_src_sel; bit[15:8] ks_value_src_sel; bit[23:16] rpc_sym_pos_sel*/
+ kal_uint32 txagc_sw_mode_ctrl;
+ /** [in] - diversity only enable info, 0: not div only mode; 1:div only mode*/
+ kal_uint32 div_only_en;
+ /** [in] - tx on control, 0: normal on, RF/FEM on+TXAGC on+TXUPC on; 1: gate on, RF/FEM on+TXUPC on, only for 1XRTT*/
+ kal_uint32 tx_on_ctrl;
+#ifdef MTK_DEV_TEMP_C2K_OTFC
+ /** [in] - DPD OTFC l1 condition check, 0: l1 not fullfil OTFC, 1: l1 fullfil OTFC */
+ kal_bool dpd_otfc_l1_en;
+ /** [in] - save Tx index in history recode. 0xFF means NOT save in history record */
+ kal_uint8 cell_index;
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+ MMRFD_CUSTOM_TAS_STATE_E ant_state;
+#endif
+}CL1D_RF_TX_PATH_ON_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Tx_Path_Off() function. */
+typedef struct CL1D_RF_TX_PATH_OFF_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [in] - time of TX off on air boundry without HRT in RX stimer, unit: echip, range: 0~0xBFFFF*/
+ kal_uint32 rx_stime;
+ /** [in] - time of TX off on air boundry without HRT in TX stimer, unit: echip, range: 0~0xBFFFF*/
+ kal_uint32 tx_stime;
+ /** [in] - tx off control, 0: normal off, RF/FEM/DFE off+TXAGC off+TXUPC off; 1: gate off, RF/FEM/DFE off+TXUPC off, only for 1XRTT*/
+ kal_uint32 tx_off_ctrl;
+#ifdef MTK_DEV_TEMP_C2K_OTFC
+ /** [in] - save Tx index in history recode. 0xFF means NOT save in history record */
+ kal_uint8 cell_index;
+#endif
+}CL1D_RF_TX_PATH_OFF_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Tx_Path_Gate_On() function. */
+typedef struct CL1D_RF_TX_PATH_GATE_ON_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - tx on air boundary in RX stimer, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - tx on air boundary in TX stimer, range is 0~0xBFFFF */
+ kal_int32 tx_stime;
+} CL1D_RF_TX_PATH_GATE_ON_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Tx_Path_Gate_Off() function. */
+typedef struct CL1D_RF_TX_PATH_GATE_OFF_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - tx on air boundary in RX stimer, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - tx on air boundary in TX stimer, range is 0~0xBFFFF */
+ kal_int32 tx_stime;
+} CL1D_RF_TX_PATH_GATE_OFF_T;
+
+/** This structure is used to dynamic configure TXAGC/TPC HW in 1XRTT mode. */
+typedef struct CL1D_RF_TPC_CFG_1XRTT_tag
+{
+ /** [in] - for non-RC8 case, indicate TPC whether needs to configure TQ in PCG, it's reserve to use*/
+ kal_bool tq_en;
+ /** [in] - hale PCG power control status, TRUE: valid(only for RC8); FALSE: invalid*/
+ kal_bool hpcg_pctrl_en;
+ /** [in] - whether needs to update close loop accumulation*/
+ kal_bool pcg_vld;
+ /** [in] - close loop step up size in 1/64dB, S2.6 unit*/
+ kal_int16 cl_step_up;
+ /** [in] - close loop step down size in 1/64dB, S2.6 unit*/
+ kal_int16 cl_step_down;
+ /** [in] - close loop adjustment limited 1/64dB, S8.6 unit*/
+ kal_int16 cl_adj_max;
+ /** [in] - close loop adjustment limited 1/64dB, S8.6 unit*/
+ kal_int16 cl_adj_min;
+ /** [in] - maximum transmit power adjustment in 1/64dB, S5.6 unit, set 0 if not use it*/
+ kal_int16 max_pwr_adj;
+ /** [in] - RPC bit in SW mode with U2.0 unit*/
+ kal_int16 rpc_bit_sw;
+ /** [in] - KS value in SW mode with S6.6 unit*/
+ kal_int16 ks_value_sw;
+ /** [in] - RPC symbol position in SW mode with U5.0 unit*/
+ kal_int16 rpc_sym_pos_sw;
+}CL1D_RF_TPC_CFG_1XRTT_T;
+
+/** This structure is used to dynamic configure TXAGC/TPC HW in EVDO mode. */
+typedef struct CL1D_RF_TPC_CFG_EVDO_tag
+{
+ /** [in] - close loop valid status, TRUE: valid, caculate target power ol+cl+ks; FLASE: invalid, ol+ks, at on air TX slot boundray*/
+ kal_bool cl_valid;
+ /** [in] - close loop step up size in 1/64dB, S2.6 unit*/
+ kal_int16 cl_step_up;
+ /** [in] - close loop step down size in 1/64dB, S2.6 unit*/
+ kal_int16 cl_step_down;
+ /** [in] - close loop adjustment limited 1/64dB, S8.6 unit*/
+ kal_int16 cl_adj_max;
+ /** [in] - close loop adjustment limited 1/64dB, S8.6 unit*/
+ kal_int16 cl_adj_min;
+ /** [in] - maximum transmit power adjustment in 1/64dB, S5.6 unit, set 0 if not use it*/
+ kal_int16 max_pwr_adj;
+ /** [in] - RPC bit in SW mode with U2.0 unit*/
+ kal_int16 rpc_bit_sw;
+ /** [in] - KS value in SW mode with S6.6 unit*/
+ kal_int16 ks_value_sw;
+}CL1D_RF_TPC_CFG_EVDO_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TPC_Cfg() function. */
+typedef struct CL1D_RF_TPC_CFG_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [in] - time of on air TX boundary in TX stimer, the configuration will be applied to HW after this time, unit: echip, range: 0~0xBFFFF*/
+ kal_uint32 tx_stime;
+#if (defined(__MD97__) || defined(__MD97P__))
+ /** [in] - RX stime value of boundary,range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+#endif
+ /** [in] - structure pointer of CL1D_RF_TPC_CFG_1XRTT_T or CL1D_RF_TPC_CFG_EVDO_T*/
+ kal_uint32 *tpc_cfg_ptr;
+}CL1D_RF_TPC_CFG_T;
+
+/** This structure is used to configure TPC HW in SW mode, the PA/CPL table is come from RFNVRAM. */
+typedef struct CL1D_RF_TPC_CFG_TST_FIX_POWER_tag
+{
+ /** [in] - tx timer value on air, range: 0~0xBFFFF*/
+ kal_uint32 tx_stime;
+#if (defined(__MD97__) || defined(__MD97P__))
+ /** [in] - RX stime value of boundary,range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+#endif
+ /** [in] - tx power on air in 1/32 dBm S6.5 unit*/
+ kal_int32 target_power;
+ /** [in] - TRUE: ILPC enable; FALSE: ILPC disable*/
+ kal_bool ilpc_en;
+ /** [in] - PA power control mode, 0: APT; 1: DPD; 2: ET; 3: Auto*/
+ kal_uint16 pa_ctrl_mode;
+}CL1D_RF_TPC_CFG_TST_FIX_POWER_T;
+
+/** This structure is used to configure TPC HW in SW mode, the PA/CPL table is come from manual configure info. */
+typedef struct CL1D_RF_TPC_CFG_TST_MANUAL_POWER_tag
+{
+ /** [in] - tx timer value on air, range: 0~0xBFFFF*/
+ kal_uint32 tx_stime;
+#if (defined(__MD97__) || defined(__MD97P__))
+ /** [in] - RX stime value of boundary,range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+#endif
+ /** [in] - tx power on air in 1/32 dBm S6.5 unit*/
+ kal_int32 target_power;
+ /** [in] - coupler loss from antenna to RFDET port in 1/64dB unit*/
+ kal_int32 cpl_gain;
+ /** [in] - TRUE: ILPC enable; FALSE: ILPC disable*/
+ kal_bool ilpc_en;
+ /** [in] - PA power control mode, 0: APT; 1: DPD; 2: ET; 3: Auto*/
+ kal_uint16 pa_ctrl_mode;
+ /** [in] - PA context table index*/
+ kal_uint16 pa_tbl_idx;
+ /** [in] - reference tx power at antenna in 1/64dBm unit*/
+ kal_int32 ref_target_power;
+ /** [in] - algorithm reference tx power output PA in 1/64dBm unit*/
+ kal_int32 pa_gain;
+ /** [in] - PA power mode, H/M/L mode, CL1D_RF_PA_MODE_E enum*/
+ kal_uint16 pa_mode;
+ /** [in] - PA bias voltage in mV unit*/
+ kal_uint16 pa_vdd;
+ /** [in] - PA mode control with BPI*/
+ kal_uint16 pa_vm0;
+ /** [in] - PA mode control with BPI*/
+ kal_uint16 pa_vm1;
+ /** [in] - AM value in DPD mode(TBD)*/
+ kal_int16 dpd_am;
+ /** [in] - PM value in DPD mode(TBD)*/
+ kal_int16 dpd_pm;
+}CL1D_RF_TPC_CFG_TST_MANUAL_POWER_T;
+
+/** This structure is used to configure TPC FdB parameters. */
+typedef struct CL1D_RF_TPC_CFG_TST_FDB_tag
+{
+ /** [in] - FDB index unit is 1/32*/
+ kal_int16 fdb_idx;
+ /** [in] - FDB unit is 1/32*/
+ kal_int16 fdb;
+}CL1D_RF_TPC_CFG_TST_FDB_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TPC_Cfg_Test() function. */
+typedef struct CL1D_RF_TPC_CFG_TEST_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [in] - enum type of CL1D_RF_TPC_TEST_MODE_E, 0: fix power mode; 1: manual power mode; 2: FDB mode*/
+ kal_uint8 test_mode;
+ /** [in] - structure pointer of test_mode*/
+ kal_uint32* cfg_ptr;
+}CL1D_RF_TPC_CFG_TEST_T;
+
+/** This structure is used to store TPC HW information in 1XRTT mode. */
+typedef struct CL1D_RF_TPC_INFO_1XRTT_tag
+{
+ /** [out] - PCG number(reverse to use)*/
+ kal_uint16 pcg_num;
+ /** [out] - close loop adjust accumulation with 1/64dB S8.6 unit*/
+ kal_int16 cl_accum_pre;
+ /** [out] - RSSI value with filter in TXAGC HW with 1/64dB S7.6 unit*/
+ kal_int16 ol_rx_pwr_filter_pre;
+ /** [out] - current max limit tx power with temperature back off and SWTP back off in HW with 1/64dB S5.6 unit*/
+ kal_int16 pwr_max;
+ /** [out] - tx power calculated by TPC HW*/
+ kal_int16 target_pwr;
+ /** [out] - KS in HW with 1/64dB S6.6 unit*/
+ kal_int16 ks;
+ /** [out] - RPC bit position*/
+ kal_int16 rpc_sym_pos;
+ /** [out] - TXUPC trigger*/
+ kal_int16 tx_upc_trig;
+ /** [out] - RPC bit*/
+ kal_int16 rpc_bit;
+}CL1D_RF_TPC_INFO_1XRTT_T;
+
+/** This structure is used to store TPC HW information in EVDO mode. */
+typedef struct CL1D_RF_TPC_INFO_EVDO_tag
+{
+ /** [out] - slot number*/
+ kal_uint16 slot_num;
+ /** [out] - close loop adjust accumulation with 1/64dB S8.6 unit*/
+ kal_int16 cl_accum_pre;
+ /** [out] - RSSI value with filter in TXAGC HW with 1/64dB S7.6 unit*/
+ kal_int16 ol_rx_pwr_filter_pre;
+ /** [out] - current max limit x power with temperature back off and SWTP back off in HW with 1/64dB S5.6 unit*/
+ kal_int16 pwr_max;
+ /** [out] - tx power calculated by TPC HW*/
+ kal_int16 target_pwr;
+ /** [out] - (calculate target power-pwr_max) in HW with 1/64dB S5.6 unit*/
+ kal_int16 max_limit_thd_clip;
+ /** [out] - KS in HW with 1/64dB S6.6 unit*/
+ kal_int16 ks;
+ /** [out] - RPC bit*/
+ kal_int16 rpc_bit;
+ /** [out] - power reference used for open loop estimation with 1/64dB S9.6 unit*/
+ kal_int16 pwr_ref;
+}CL1D_RF_TPC_INFO_EVDO_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TPC_Info_Query() function. */
+typedef struct CL1D_RF_TPC_INFO_QUERY_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [out] - structure pointer of CL1D_RF_TPC_TPC_INFO_1XRTT_T or CL1D_RF_TPC_TPC_INFO_EVDO_T(dimension is two half-slot)*/
+ kal_uint32 *tpc_info;
+}CL1D_RF_TPC_INFO_QUERY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TPC_Antenna_Power_Query() function. */
+typedef struct CL1D_RF_TPC_ANTENNA_POWER_QUERY_tag
+{
+ /** [out] - current tx power at antenna in 1/32dBm unit*/
+ kal_int16 ant_power;
+}CL1D_RF_TPC_ANTENNA_POWER_QUERY_T;
+
+#if (defined(__MD97__) || defined(__MD97P__))
+/** Ads structure to provide parameters to the CL1D_RF_TPC_Algo_Result_Query() function. */
+typedef struct CL1D_RF_TPC_ALGO_RESULT_QUERY_tag
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [out] - current op mode, U2.0, HW return, 0: ET; 1: DPD; 2: APT */
+ kal_uint8 op_mode;
+ /** [out] - PGA gain index, U5.0*/
+ kal_uint8 pga_idx;
+ /** [out] - PA gain index, U5.0*/
+ kal_uint8 pa_idx;
+ /** [out] - DET gain index, U4.0*/
+ kal_uint8 det_idx;
+ /** [out] - PGA A/B table mode, U1.0*/
+ kal_uint8 pga_mode;
+ /** [out] - desired tx gain, S7.5*/
+ kal_int16 gtx_db;
+ /** [out] - target power, S7.5*/
+ kal_int16 gtar_db;
+ /** [out] - PA gain, S6.5*/
+ kal_int16 pa_db;
+ /** [out] - PGA gain, S7.5*/
+ kal_int16 pga_db;
+ /** [out] - digital gain, S6.5*/
+ kal_int16 bb_db;
+ /** [out] - det path FE+PGA gain, S6.5*/
+ kal_int16 det_rf_db;
+ /** [out] - couplerloss gain of DET path, S6.5*/
+ kal_int16 cpl_gain;
+ /** [out] - back off gain, S6.5*/
+ kal_int16 bkf_gain;
+ /** [out] - ILPC compensation value for tx PGA gain adjustment, S4.5*/
+ kal_int16 meas_rf;
+ /** [out] - DDPC det var from TPC HW, S24.0*/
+ kal_int32 ddpc_det;
+ /** [out] - PA output power be mesured, S6.5*/
+ kal_int16 ppa_dbm;
+ /** [out] - RX rssi for TXAGC, S7.6*/
+ kal_int16 ol_rx_pwr_filter;
+}CL1D_RF_TPC_ALGO_RESULT_QUERY_T;
+#endif
+
+/** This structure is used to configure RXDFE NCO. */
+typedef struct CL1D_RF_RXDFE_NCO_CFG_tag
+{
+ /** [in] - RXDFE foe, unit is hz */
+ kal_int32 foe;
+} CL1D_RF_RXDFE_NCO_CFG_T;
+
+/** This structure is used to configure RXDFE NBIF. */
+typedef struct CL1D_RF_RXDFE_NBIF_CFG_tag
+{
+ /** [in] - the valid bit map info of three NBIFs, 3b'xxx */
+ kal_uint8 nbif_bmp;
+ /** [in] - position of NBIF for I path */
+ kal_int32 nbif_ai[CL1D_RF_RXDFE_NBIF_NUM];
+ /** [in] - position of NBIF for Q path */
+ kal_int32 nbif_aq[CL1D_RF_RXDFE_NBIF_NUM];
+ /** [in] - rounding mode of NBIF */
+ kal_uint32 nbif_p[CL1D_RF_RXDFE_NBIF_NUM];
+} CL1D_RF_RXDFE_NBIF_CFG_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Rx_Path_On() function. */
+typedef struct CL1D_RF_RX_PATH_ON_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value that align to HRT of RXON, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - 3GPP2 band class */
+ kal_uint8 band_class;
+ /** [in] - Channel number */
+ kal_uint16 channel;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - total frequency offset error in Hz */
+ kal_int32 foe_hz;
+ /** [in] - initial RSSI in 1/32 dBm*/
+ kal_int32 init_rssi[CL1D_RF_MAX_NUM_OF_RX];
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+ /** [in] - The slot/PCG number to keep FAST state before STEADY state*/
+ kal_uint8 fast_num;
+ /** [in] - ICS/FAST/STEADY, ICS state only for EVDO*/
+ kal_uint8 agc_fsm;
+ /** [in] - use to get the backup gain setting from cell table by rx path,0xFF means NOT resume from history record */
+ kal_uint16 cell_index[CL1D_RF_MAX_NUM_OF_RX];
+
+#if (defined(__MD97__) || defined(__MD97P__))
+ MMRFD_CUSTOM_TAS_STATE_E ant_state;
+#endif
+} CL1D_RF_RX_PATH_ON_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_Rx_Path_On() function. */
+typedef struct CL1D_RF_RX_PATH_OFF_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value that align to HRT of RXON, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - save AGC index in history recode. 0xFF means NOT save in history record */
+ kal_uint16 cell_index[CL1D_RF_MAX_NUM_OF_RX];
+} CL1D_RF_RX_PATH_OFF_T;
+
+/** This structure is used to dynamic update AGC FSM and power mode in EVDO mode. */
+typedef struct CL1D_RF_AGC_CFG_EVDO_tag
+{
+ /** [in] - Indicate whether FSM is valid */
+ kal_bool agc_fsm_vld;
+ /** [in] - ICS/FAST/STEADY, ICS state only for EVDO */
+ kal_uint8 agc_fsm;
+ /** [in] - Indicate whether power mode is valid */
+ kal_bool power_mode_vld;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+} CL1D_RF_AGC_CFG_EVDO_T;
+
+/** This structure is used to dynamic update AGC FSM and power mode in EVDO mode. */
+typedef struct CL1D_RF_AGC_CFG_1XRTT_tag
+{
+ /** [in] - Indicate whether power mode is valid */
+ kal_bool power_mode_vld;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+} CL1D_RF_AGC_CFG_1XRTT_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AGC_Cfg() function. */
+typedef struct CL1D_RF_AGC_CFG_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - Structure pointer of CL1D_RF_AGC_CFG_EVDO_T/CL1D_RF_AGC_CFG_1XRTT_T */
+ kal_uint32* agc_cfg_ptr;
+} CL1D_RF_AGC_CFG_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AGC_Rssi_Query() function. */
+typedef struct CL1D_RF_AGC_RSSI_QUERY_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [out] - RSSI result of 3 Rx path.
+ normal mode: include temperature comp and low power comp, it's a average of current SLOT/PCG
+ test/meta mode: include temperature comp without lower comp, it's a average of testing period
+ */
+ kal_int16 rssi[CL1D_RF_MAX_NUM_OF_RX];
+} CL1D_RF_AGC_RSSI_QUERY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_PAHT_SNR_Query() function. */
+typedef struct CL1D_RF_PATH_SNR_QUERY_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [out] - SNR result of 3 Rx path.
+ normal mode: include temperature comp and low power comp, it's a average of current SLOT/PCG
+ test/meta mode: include temperature comp without lower comp, it's a average of testing period
+ */
+ kal_int16 snr[CL1D_RF_MAX_NUM_OF_RX];
+} CL1D_RF_PATH_SNR_QUERY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_PATH_EC_IO_Query() function. */
+typedef struct CL1D_RF_PATH_EC_IO_QUERY_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [out] - RSSI result of 3 Rx path.
+ normal mode: include temperature comp and low power comp, it's a average of current SLOT/PCG
+ test/meta mode: include temperature comp without lower comp, it's a average of testing period
+ */
+ kal_int16 ecio[CL1D_RF_MAX_NUM_OF_RX];
+} CL1D_RF_PATH_EC_IO_QUERY_T;
+
+
+/** This structure is used to configure AGCDC HW in FIX GAIN mode. */
+typedef struct CL1D_RF_AGC_CFG_TST_FIX_GAIN_tag
+{
+ /** [in] - ICS/FAST/STEADY/FHC */
+ kal_uint8 agc_fsm;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+ /** [in] - LNA index of CL1D_RF_LNA_MODE_E*/
+ kal_uint8 lna_idx;
+ /** [in] - Rx timer value, range is 0~0xBFFFF, indicate when to begin RSSI average,
+ 0xFFFFFFFF means no time limitation
+ */
+ kal_uint32 rssi_avg_start_time;
+
+ /** [in] - Rx timer value, range is 0~0xBFFFF, indicate when to end RSSI average,
+ 0xFFFFFFFF means no time limitation
+ */
+ kal_uint32 rssi_avg_end_time;
+
+} CL1D_RF_AGC_CFG_TST_FIX_GAIN_T;
+
+/** This structure is used to configure AGCDC HW in MANUAL mode. */
+typedef struct CL1D_RF_AGC_CFG_TST_MANUAL_tag
+{
+ /** [in] - ICS/FAST/STEADY/FHC */
+ kal_uint8 agc_fsm;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E */
+ kal_uint8 power_mode;
+ /** [in] - LNA index of CL1D_RF_LNA_MODE_E */
+ kal_uint8 lna_idx;
+ /** [in] - PGA index of CL1D_RF_PGA_INDEX_E */
+ kal_uint8 pga_idx;
+ /** [in] - digital gain in DB2 format, S5.5 */
+ kal_int32 dig_gain;
+ /** [in] - indicate which parameters to be fixed
+ bit0: rf gain
+ bit1: rf DC
+ bit2: digital gain
+ bit3: digital DC
+ */
+ kal_uint8 agcdc_fix_bmp;
+} CL1D_RF_AGC_CFG_TST_MANUAL_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AGC_Cfg_Test() function. */
+typedef struct CL1D_RF_AGC_CFG_TEST_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - 0: AGC fix gain mode 1: ¡ */
+ kal_uint8 test_mode;
+ /** [in] - Structure pointer of CL1D_RF_AGC_CFG_TST_FIX_GAIN_T/CL1D_RF_AGC_CFG_TST_MANUAL_T */
+ kal_uint32* cfg_ptr;
+} CL1D_RF_AGC_CFG_TEST_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_AGC_Backup_Info_Query() function. */
+typedef struct CL1D_RF_AGC_BACKUP_INFO_QUERY_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - use to get the backup gain setting from cell table by rx path*/
+ kal_uint16 cell_index[CL1D_RF_MAX_NUM_OF_RX];
+
+ /** [out] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode[CL1D_RF_MAX_NUM_OF_RX];
+} CL1D_RF_AGC_BACKUP_INFO_QUERY_T;
+
+#if (defined(__MD97__) || defined(__MD97P__))
+/** Ads structure to provide parameters to the CL1D_RF_AGC_Algo_Result_Query() function. */
+typedef struct CL1D_RF_AGC_ALGO_RESULT_QUERY_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [out] - PGA index of CL1D_RF_PGA_INDEX_E */
+ kal_uint8 pga_idx;
+ /** [out] - LNA index of CL1D_RF_LNA_MODE_E */
+ kal_uint8 lna_idx;
+ /** [out] - ELNA index of CL1D_RF_ELNA_MODE_E */
+ kal_uint8 elna_idx;
+ /** [out] - MLNA index of CL1D_RF_MLNA_MODE_E */
+ kal_uint8 mlna_idx;
+ /** [out] - digital gain in Q5 format */
+ kal_int32 dig_gain;
+ /** [out] - RF gain in Q5 format */
+ kal_int32 rf_gain;
+ /** [out] - pathloss in Q5 format */
+ kal_int32 pathloss;
+ /** [out] - calculated wide-band power in Q5 format */
+ kal_int32 wb_power;
+ /** [out] - calculated in-band power in Q5 format */
+ kal_int32 ib_power;
+ /** [out] - calculated rssi in Q5 format */
+ kal_int32 rssi;
+ /** [out] - estimated residual DC in I path */
+ kal_int32 dc_est_re_i;
+ /** [out] - estimated residual DC in Q path */
+ kal_int32 dc_est_re_q;
+ /** [out] - RF DC in I path */
+ kal_int32 rf_dc_i;
+ /** [out] - RF DC in Q path */
+ kal_int32 rf_dc_q;
+ /** [out] - digital DC in I path */
+ kal_int32 dig_dc_i;
+ /** [out] - digital DC in Q path */
+ kal_int32 dig_dc_q;
+}CL1D_RF_AGC_ALGO_RESULT_QUERY_T;
+#endif
+
+#ifndef __MD93__
+typedef struct
+{
+ kal_uint8 lna_mode_number;
+ kal_int16 power_calibration_value[CL1D_RF_LNA_MODE_NUM];
+}CL1D_LNA_CALIBRATION_POWER_T;
+
+typedef struct
+{
+ CL1D_LNA_CALIBRATION_POWER_T high_power_point;
+ CL1D_LNA_CALIBRATION_POWER_T low_power_point;
+}CL1D_RF_LNA_CALIBRATION_POWER_T;
+
+typedef struct
+{
+ kal_int16 min;
+ kal_int16 max;
+}CL1D_RF_MIN_MAX_T;
+
+typedef struct
+{
+ CL1D_RF_MIN_MAX_T high_power_calibration_range[CL1D_RF_LNA_MODE_NUM];
+ CL1D_RF_MIN_MAX_T lower_power_calibration_range[CL1D_RF_LNA_MODE_NUM];
+}CL1D_RF_LNA_CAL_RANGE_POWER_T;
+
+typedef struct
+{
+ CL1D_RF_LNA_CALIBRATION_POWER_T cl1d_rf_calib_power_point[CL1D_RF_MAX_NUM_OF_RX];
+ CL1D_RF_LNA_CAL_RANGE_POWER_T cl1d_rf_calib_power_range[CL1D_RF_MAX_NUM_OF_RX];
+}CL1D_RF_RX_LNA_CALIBRATION_POWER_AND_RANGE_T;
+
+extern CL1D_RF_RX_LNA_CALIBRATION_POWER_AND_RANGE_T *CL1D_RF_GET_LNA_CAL_POWER_POINTS_AND_POWER_RANGE(kal_uint8 band_class_num,kal_uint8 *band_class);
+
+#endif
+
+/** Ads structure to provide parameters to the CL1D_RF_RXDFE_IQC_Update() function. */
+typedef struct CL1D_RF_RXDFE_IQC_UPDATE_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value of update IQ compensation, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { bit2:second Rx, bit1:diversity Rx, bit0:main Rx} */
+ kal_uint8 path_bmp;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+} CL1D_RF_RXDFE_IQC_UPDATE_T;
+
+
+/** Ads structure to provide parameters to the CL1D_RF_RXDFE_Nbif_Update() function. */
+typedef struct CL1D_RF_RXDFE_NCO_UPDATE_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value of set NCO, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { bit2:second Rx, bit1:diversity Rx, bit0:main Rx} */
+ kal_uint8 path_bmp;
+ /** [in] - RXDFE NCO configuration*/
+ CL1D_RF_RXDFE_NCO_CFG_T nco_cfg;
+} CL1D_RF_RXDFE_NCO_UPDATE_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_RXDFE_Nbif_Update() function. */
+typedef struct CL1D_RF_RXDFE_NBIF_UPDATE_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - RXDFE NBIF configuration*/
+ CL1D_RF_RXDFE_NBIF_CFG_T nbif_cfg;
+} CL1D_RF_RXDFE_NBIF_UPDATE_T;
+
+typedef union{
+ CL1D_RF_RXDFE_NBIF_UPDATE_T nbif_data;
+ CL1D_RF_RXDFE_NCO_UPDATE_T nco_data;
+ CL1D_RF_RXDFE_IQC_UPDATE_T iqc_data;
+}CL1D_RF_RXDFE_DYN_CFG_DATA_U;
+/** Ads structure to provide parameters to the CL1D_RF_RXDFE_Sort_Done() function. */
+typedef struct CL1D_RF_RXDFE_SORT_DONE_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+
+} CL1D_RF_RXDFE_SORT_DONE_T;
+
+#if defined(__MD93__)
+typedef struct CL1D_RF_RXDFE_PATH_CFG_tag
+{
+ CL1D_RF_RAT_TYPE_E rat;
+ CL1D_RF_RXDFE_SENARIO_E scenario;
+ kal_uint32 stime; /* in unit of chips */
+ CL1D_RF_BAND_CLASS_TYPE_E band;
+}CL1D_RF_RXDFE_PATH_CFG_T;
+#elif defined(__MD95__)
+typedef struct CL1D_RF_RXDFE_PATH_CFG_tag
+{
+ CL1D_RF_RAT_TYPE_E rat;
+ CL1D_RF_RXDFE_SENARIO_E scenario;
+ kal_uint32 stime; /* in unit of chips */
+ CL1D_RF_BAND_CLASS_TYPE_E band;
+}CL1D_RF_RXDFE_PATH_CFG_T;
+#elif (defined(__MD97__) || defined(__MD97P__))
+typedef struct CL1D_RF_RXDFE_PATH_CFG_tag
+{
+ CL1D_RF_RAT_TYPE_E rat;
+ CL1D_RF_RXDFE_SENARIO_E scenario;
+ kal_uint32 stime; /* in unit of chips */
+ CL1D_RF_BAND_CLASS_TYPE_E band;
+ //kal_uint8 rcc_idx_use;
+}CL1D_RF_RXDFE_PATH_CFG_T;
+#endif
+
+
+typedef struct {
+ CL1D_RF_RAT_TYPE_E rat;
+ CL1D_RF_TXDFE_SENARIO_E scenario;
+ kal_uint32 rx_stime; /* in unit of chips */
+ kal_uint32 tx_stime; /* in unit of chips */
+ CL1D_RF_BAND_CLASS_TYPE_E band_class;
+ kal_uint32 freq_khz;
+ CL1D_RF_FREQ_BAND_E freq_band_type;
+}CL1D_RF_TXDFE_CFG_T;
+
+
+/** This structure is used to configure RXDFE NCO. */
+typedef struct CL1D_RF_TXDFE_NCO_CFG_tag
+{
+ /** [in] - RXDFE NCO phase, unit is ? */
+ kal_int32 foe;
+} CL1D_RF_TXDFE_NCO_CFG_T;
+
+/** Ads structure to provide parameters to the cl1d_rf_txdfe_nco_update_config() function. */
+typedef struct CL1D_RF_TXDFE_NCO_UPDATE_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Tx timer value of set NCO, range is 0~0xBFFFF */
+ kal_uint32 tx_stime;
+ /** [in] - { bit2:second Rx, bit1:diversity Rx, bit0:main Rx} */
+ kal_uint8 path_bmp;
+ /** [in] - RXDFE NCO configuration*/
+ CL1D_RF_TXDFE_NCO_CFG_T nco_cfg;
+} CL1D_RF_TXDFE_NCO_UPDATE_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TXDFE_RF_TTG_Cfg() function. */
+typedef struct CL1D_RF_TXDFE_RF_TTG_CFG_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - TRUE: turn on TXDFE_WIN and TTG
+ FALSE: turn off TXDFE_WIN and TTG
+ */
+ kal_bool ttg_en;
+ /** [in] - Sine tone frequency in Hz */
+ kal_uint32 ttg_freq;
+
+ kal_uint8 band_class;
+} CL1D_RF_TXDFE_RF_TTG_CFG_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TXDFE_BB_TTG_Cfg() function. */
+typedef struct {
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - TRUE: turn on TXDFE_WIN and TTG
+ FALSE: turn off TXDFE_WIN and TTG
+ */
+ kal_bool ttg_en;
+ /** [in] - Sine tone frequency in Hz */
+ kal_uint32 ttg_freq;
+
+ kal_uint32 ttg_gain;
+}CL1D_RF_TXDFE_BB_TTG_CFG_T;
+
+
+/** Ads structure to provide parameters to the CL1D_RF_Test_Mode_Request() function. */
+typedef struct CL1D_RF_TEST_MODE_REQUEST_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - TRUE: test mode enable
+ FALSE: test mode disablein */
+ kal_bool test_mode_en;
+
+ /** [in] - bit0: RX test mode
+ bit1: TX test mode
+ bit2: META mode
+ Note: just one bit can be set/clear every time
+ */
+ kal_uint8 test_mode_bmp;
+
+} CL1D_RF_TEST_MODE_REQUEST_T;
+
+typedef struct CL1D_RF_NV_tag
+{
+ kal_uint32 nvram_lid;
+ kal_uint8* data_buf;
+ kal_uint32 oper_bmp;
+ kal_uint16 nvram_rec_idx;
+} CL1D_RF_NV_T;
+
+typedef struct CL1D_RF_NV_RE_INIT_tag
+{
+ kal_uint32 oper_bmp;
+} CL1D_RF_NV_RE_INIT_T;
+
+/** This structure is used to store UPC HW information in EVDO and 1xRTT mode. */
+typedef struct CL1D_RF_UPC_INFO_tag
+{
+ /** [in] - PA index */
+ kal_uint8 pa_idx;
+
+ /** [out] - PGA gain */
+ kal_int16 pga_gain;
+
+ /** [out] - DET path PGA gain */
+ kal_int16 det_gain;
+
+ /** [out] - BB gain */
+ kal_int16 bb_gain;
+
+} CL1D_RF_UPC_INFO_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_UPC_Info_Query() function. */
+typedef struct CL1D_RF_UPC_INFO_QUERY_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [out] - Structure pointer of CL1D_RF_UPC_INFO_T
+ */
+ CL1D_RF_UPC_INFO_T* upc_info;
+} CL1D_RF_UPC_INFO_QUERY_T;
+
+/** Ads structure to provide parameters to the CL1D_RF_TPC_Gain_Info_Query() function. */
+typedef struct CL1D_RF_TPC_GAIN_INFO_QUERY_tag
+{
+ /** [in] - PA index */
+ kal_uint8 pa_idx;
+
+ /** [out] - PA gain */
+ kal_int16 pa_gain;
+
+ /** [in] - PGA index */
+ kal_uint8 pga_idx;
+
+ /** [out] - PGA gain */
+ kal_int16 pga_gain;
+
+ /** [in] - DET PA index */
+ kal_uint8 det_pga_idx;
+
+ /** [out] - DET PA gain */
+ kal_int16 det_pga_gain;
+
+ /** [in] - CPL PA index */
+ kal_uint8 cpl_idx;
+
+ /** [out] - CPL PA gain */
+ kal_int16 cpl_gain;
+
+ /** [in] - BB PA index */
+ kal_uint8 bb_idx;
+
+ /** [out] - BB PA gain */
+ kal_int16 bb_gain;
+
+} CL1D_RF_TPC_GAIN_INFO_QUERY_T;
+
+
+/** This structure is used to get PA LUT table */
+typedef struct CL1D_RF_CUST_GET_PA_LUT_TBL_CONTEX_tag
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+
+ /** [in] - PA index */
+ kal_uint8 pa_idx;
+
+ /** [out] - PA mode */
+ kal_uint8 pa_mode;
+
+ /** [out] - target power */
+ kal_int16 prf;
+
+ /** [out] - PA gain (include compensation) */
+ kal_int16 pa_gain;
+
+ /** [out] - Coupler loss (include compensation) */
+ kal_int16 coupler_loss;
+
+ /** [out] - VM0 */
+ kal_uint8 vm0;
+
+ /** [out] - VM1 */
+ kal_uint8 vm1;
+
+ /** [out] - VDD */
+ kal_uint16 vdd;
+
+ /** [out] - PA comp**/
+ kal_int16 pa_gain_comp;
+
+} CL1D_RF_CUST_GET_PA_LUT_TBL_CONTEX_T;
+
+/** This structure is used to get custom item info */
+typedef struct CL1D_RF_CUST_GET_CUST_ITEM_INFO_tag
+{
+ /** [in] - LID */
+ kal_uint32 item_lid;
+
+ /** [in] - rec_idx */
+ kal_uint32 rec_idx;
+
+ /** [out] - LID item address */
+ kal_uint32* item_addr;
+
+} CL1D_RF_CUST_GET_CUST_ITEM_INFO_T;
+
+/** This structure is used to copy data from SHM to NVRAM */
+typedef struct CL1D_RF_COPY_DATA_FROM_SHM_TO_NVRAM_tag
+{
+ /** [in] - LID */
+ kal_uint32 item_lid;
+
+ /** [in] - rec_idx */
+ kal_uint32 rec_idx;
+
+} CL1D_RF_COPY_DATA_FROM_SHM_TO_NVRAM_T;
+
+#if defined(__MD95__)
+typedef struct
+{
+ kal_uint8 rat_type;
+}CL1D_RF_RXDFE_IQ_DUMP_T;
+#elif (defined(__MD97__) || defined(__MD97P__))
+#if CL1D_RXDFE_DUMP_ENA
+typedef struct
+{
+ kal_bool ttg_en;
+ CL1D_RF_PATH_E rf_path;
+ CL1D_RF_RAT_TYPE_E rat_type;
+ CL1D_RF_RXDFE_TTG_IN_E node;
+ kal_uint32 scale;
+}CL1D_RF_RXDFE_TTG_Input_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_DUMP_NODE_E dump_node;
+ CL1D_RF_PATH_E rf_path;
+ CL1D_RF_RAT_TYPE_E rat_type;
+ kal_uint32 dump_size;
+}CL1D_RF_RXDFE_IQ_DUMP_Input_T;
+
+typedef struct
+{
+ kal_int32 dump_idx;
+ kal_int32 dump_size;
+ kal_uint32 * data_addr;
+}CL1D_RF_RXTXDFE_IQ_DUMP_QURY_T;
+typedef struct
+{
+ kal_int32 buffer_size;
+ kal_int32 buffer_num;
+}CL1D_RF_RXDFE_IQ_DUMP_Output_T;
+
+typedef struct
+{
+ CL1D_RF_RXDFE_IQ_DUMP_Input_T input;
+ CL1D_RF_RXDFE_IQ_DUMP_Output_T output;
+}CL1D_RF_RXDFE_IQ_DUMP_T;
+#endif
+#endif
+#if CL1D_RXDFE_DUMP_ENA
+typedef enum {
+ TXK_REF,
+ TXDFE_RF,
+ TXDFE_BB,
+ TXDFE_ET,
+ TXK_DET,
+}CL1D_RF_TXDFE_IQ_DUMP_SEL_CFG_E;
+
+typedef enum {
+ BB_INPUT,
+ BB_FIRAD_INPUT,
+ BB_SRC_INPUT,
+ BB_CIC1X_INPUT,
+ BB_CIC2X_INPUT,
+ BB_NCO_INPUT,
+ BB_NCO_OUTPUT,
+ RF_BB_GAIN = 0,
+ RF_DPD_COMP,
+ RF_GAIN_BKF,
+ RF_GA_COMP,
+ RF_AD_COMP,
+ RF_MAIN_PHASE_R_DELAY,
+ RF_MAIN_DC,
+ RF_MAIN_FI,
+ RF_MAIN_FD,
+}CL1D_RF_TXDFE_IQ_DUMP_NODE_CFG_E;
+
+typedef enum{
+ RF_DET_FIFO,
+ RF_DET_CIC,
+ RF_DET_OUT,
+ RF_REF_SCALE =0 ,
+ RF_REF_I_DELAY,
+ RF_REF_F_DELAY,
+ RF_REF_DCM,
+}CL1D_RF_TXKDFE_IQ_DUMP_NODE_CFG_E;
+
+typedef struct {
+ /** [in] - BB or RF or MRX**/
+ CL1D_RF_TXDFE_IQ_DUMP_SEL_CFG_E dump_sel;
+ /** [in] - For TXDFE_BB:0:bb input; 1:firad input; 2:src input; 3:cic1x input; 4:cic2x input; 5:nco input; 6:nco ouput
+ For TXDFE_RF:0:gain_bb; 1:dpd comp; 2:gain bkf; 3:ga comp; 4:ad comp; 5:main phase r delay; 6:main dc; 7:main fi; 8:main fd**/
+ CL1D_RF_TXDFE_IQ_DUMP_NODE_CFG_E node_sel;
+ CL1D_RF_RAT_TYPE_E rat_type;
+ kal_uint32 dump_size;
+}CL1D_RF_TXDFE_IQ_DUMP_INPUT_T;
+
+
+typedef struct
+{
+ kal_int32 buffer_size;
+ kal_int32 buffer_num;
+}CL1D_RF_TXDFE_IQ_DUMP_OUTPUT_T;
+
+
+
+typedef struct {
+ /** [in] - 0:TXK_REF; 1:TXDFE_BB; 2:TXDFE_RF; 3:TXDFE_ET; 4:TXK_DET**/
+ CL1D_RF_TXDFE_IQ_DUMP_SEL_CFG_E dump_sel;
+ /** [in] - For TXK DET: 0:det afifo out; 1:det cic out; 2:det out;
+ For TXK REF: 0:ref scale out; 1:ref i delay out; 2:ref f delay out; 3:ref dcm out**/
+ CL1D_RF_TXKDFE_IQ_DUMP_NODE_CFG_E node_sel;
+ kal_uint32 dump_size;
+}CL1D_RF_TXKDFE_IQ_DUMP_INPUT_T;
+
+typedef struct
+{
+ kal_int32 buffer_size;
+ kal_int32 buffer_num;
+}CL1D_RF_TXKDFE_IQ_DUMP_OUTPUT_T;
+#endif
+
+
+
+typedef struct{
+ kal_uint32 addr_start;
+ kal_uint32 size;
+}CL1D_RF_MIPI_READ_T;
+
+typedef struct{
+ kal_uint32 addr;
+ kal_uint32 data;
+}CL1D_RF_MIPI_WRITE_T;
+
+#if defined(__MD97__)
+typedef struct{
+ CL1D_RF_TX_APT_PA_CONTEXT_T pa_context;
+ CL1D_RF_TX_APT_PA_GAIN_COMP_T pa_compensation_data;
+}CL1D_RF_TX_LEAKAGE_PA_FK_RESULT_T;
+#endif
+
+#if (defined(__MD97__) || defined(__MD97P__))
+
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+/** Ads structure to provide parameters to the CL1D_RF_HOPPING_FREQ_Query() function. */
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type; // 0 for 1xrtt; 1 for evdo
+ /** [in] - 3GPP2 band class */
+ kal_uint8 band_class;
+ /** [in] - Channel number */
+ kal_uint16 channel;
+ /** [in] - Freq Group type */
+ kal_uint8 freq_group_type; // 0 for group_a; 1 for group_b
+ /** [in] - Freq Table index */
+ kal_uint8 freq_table_index; //0~7 for table0~table7
+} CL1D_RF_HOPPING_QUERY_T;
+
+typedef struct
+{
+ /** [out] - Indicate the total num of device table */
+ kal_uint8 table_num;
+ /** [out] - Indicate the table enable mask */
+ kal_uint32 table_en_mask; //bit 0~7 for table0~7
+}CL1D_RF_TABLE_INFO_QUERY_T;
+
+typedef enum
+{
+ C2K_RF_HOPPING_GROUP_A = 0,
+ C2K_RF_HOPPING_GROUP_B = 1,
+ C2K_RF_HOPPING_GROUP_NULL
+}CL1D_RF_HOPPING_GROUP_E;
+#endif
+
+#endif
+
+/** Ads structure to provide parameters to the CL1D_RF_RFPD_Info_Query() function. */
+typedef struct CL1D_RF_RFPD_INFO_QUERY_tag
+{
+ /** [out] - target power, S7.5*/
+ kal_int16 target_power;
+ /** [out] - PA output power be mesured, S6.5*/
+ kal_int16 ddpc;
+ /** [out] - DDPC det var from TPC HW, S24.0*/
+ kal_int32 ddpc_det;
+ /** [out] - RX rssi for TXAGC, S7.6*/
+ kal_int16 rssi_filter;
+ /** [out] - fetch the PLL state */
+ kal_bool pll;
+ /** [out] - fetch the VCC */
+ kal_uint8 vcc;
+ /** [out] - fetch the temperature */
+ kal_int16 temperature;
+ /** [out] - power is abnormal or not*/
+ kal_bool power_abnormal;
+}CL1D_RF_RFPD_INFO_QUERY_T;
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+extern kal_uint8 rat2mmrfMode[CL1D_RF_RAT_NUM];
+#define M_RAT_TO_MMRF_MODE(rat) (rat2mmrfMode[rat])
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+/**RFD common interface*/
+extern void CL1D_RF_Get_Platform_Info(CL1D_RF_GET_PLATFORM_INFO_T* adsPtr);
+#if _C2K_UTAS_SUPPORT_
+extern C2K_CUSTOM_TAS_STATE_E CL1D_RF_UTAS_GetCurrentState(SysCdmaBandT band,CL1D_RF_RAT_E l1_rat);
+extern kal_bool CL1D_RF_UTAS_IsEnable(SysCdmaBandT band);
+extern C2K_CUSTOM_TAS_LAYOUT_GROUP_E CL1D_RF_UTAS_Get_Hw_Group(SysCdmaBandT band);
+extern C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T *CL1D_RF_GET_UTAS_ALGORITHM_PARAMETER(void);
+extern kal_int8 CL1D_RF_Quary_UTAS_Ant_Rscp_Bias(kal_uint8 ant_index,kal_uint8 c2k_band);
+#endif
+extern void CL1D_RF_Sw_Init(void);
+extern void CL1D_RF_HW_TX_Init(void);
+extern void CL1D_RF_HW_TX_End(void);
+extern void CL1D_RF_HW_RX_Init(void);
+extern void CL1D_RF_HW_RX_End(void);
+extern void CL1D_RF_Init(void);
+
+/**RFD AFC interface*/
+extern void CL1D_RF_AFC_Synth_Offset_Update(CL1D_RF_AFC_SYNTH_OFFSET_UPDATE_T* adsPtr);
+extern void CL1D_RF_AFC_Init_Foe_Ppb_Query(CL1D_RF_AFC_INIT_FOE_PPB_QUERY_T* adsPtr);
+extern void CL1D_RF_AFC_S_Curve_Param_Query(CL1D_RF_AFC_S_CURVE_PARAM_QUERY_T* adsPtr);
+extern void CL1D_RF_AFC_Foe_Ppb_To_Dac(CL1D_RF_AFC_FOE_PPB_TO_DAC_T* adsPtr);
+extern void CL1D_RF_AFC_Dac_To_Foe_Ppb(CL1D_RF_AFC_DAC_TO_FOE_PPB_T* adsPtr);
+extern void CL1D_RF_AFC_Rx_Channel_To_Frequency(CL1D_RF_AFC_RX_CHANNEL_TO_FREQUENCY_T* adsPtr);
+extern void CL1D_RF_AFC_Tx_Channel_To_Frequency(CL1D_RF_AFC_TX_CHANNEL_TO_FREQUENCY_T* adsPtr);
+extern void CL1D_RF_AFC_Cap_Id_Update(CL1D_RF_AFC_CAP_ID_UPDATE_T* adsPtr);
+extern void CL1D_RF_AFC_Dac_Update(CL1D_RF_AFC_DAC_UPDATE_T* adsPtr);
+
+/**RFD power saving interface*/
+extern void CL1D_RF_Power_On(void);
+extern void CL1D_RF_Power_Off(void);
+
+/**RFD temperature feature interface*/
+extern void CL1D_RF_Temperature_Query(CL1D_RF_TEMPERATURE_QUERY_T* adsPtr);
+extern void CL1D_RF_Temperature_Meas(kal_uint8 rat, CL1D_RF_TMP_MODE_E tmp_mode);
+
+/**RFD TX path control interface*/
+extern void CL1D_RF_Tx_Path_On(CL1D_RF_TX_PATH_ON_T* adsPtr);
+extern void CL1D_RF_Tx_Path_Off(CL1D_RF_TX_PATH_OFF_T* adsPtr);
+extern void CL1D_RF_Tx_Path_Gate_On(CL1D_RF_TX_PATH_GATE_ON_T* adsPtr);
+extern void CL1D_RF_Tx_Path_Gate_Off(CL1D_RF_TX_PATH_GATE_OFF_T* adsPtr);
+
+/**RFD TPC control interface*/
+extern void CL1D_RF_TPC_Init(void);
+extern void CL1D_RF_TPC_Cfg(CL1D_RF_TPC_CFG_T* adsPtr);
+extern void CL1D_RF_TPC_Info_Query(CL1D_RF_TPC_INFO_QUERY_T* adsPtr);
+extern void CL1D_RF_TPC_Cfg_Test(CL1D_RF_TPC_CFG_TEST_T* adsPtr);
+extern void CL1D_RF_TPC_Antenna_Power_Query(CL1D_RF_TPC_ANTENNA_POWER_QUERY_T* adsPtr);
+extern void CL1D_RF_TPC_Gain_Info_Query(CL1D_RF_TPC_GAIN_INFO_QUERY_T* adsPtr);
+extern void CL1D_RF_UPC_Info_Query(CL1D_RF_UPC_INFO_QUERY_T* adsPtr);
+extern kal_bool CL1D_RF_CUST_Fdb_Read_Done_Query(void);
+#if (defined(__MD97__) || defined(__MD97P__))
+extern void CL1D_RF_TPC_Algo_Result_Query(CL1D_RF_TPC_ALGO_RESULT_QUERY_T* adsPtr);
+#endif
+
+/**RFD RX path control interface*/
+extern void CL1D_RF_Rx_Path_On(CL1D_RF_RX_PATH_ON_T* adsPtr);
+extern void CL1D_RF_Rx_Path_Off(CL1D_RF_RX_PATH_OFF_T* adsPtr);
+
+/**RFD POC update interface*/
+extern void CL1D_RF_DEV_AGC_POC_update(void);
+extern void CL1D_RF_DEV_TPC_POC_update(void);
+
+/**RFD AGC control interface*/
+extern void CL1D_RF_AGC_Cfg(CL1D_RF_AGC_CFG_T* adsPtr);
+extern void CL1D_RF_AGC_Rssi_Query(CL1D_RF_AGC_RSSI_QUERY_T* adsPtr);
+extern void CL1D_RF_AGC_Cfg_Test(CL1D_RF_AGC_CFG_TEST_T* adsPtr);
+extern void CL1D_RF_AGC_Backup_Info_Query(CL1D_RF_AGC_BACKUP_INFO_QUERY_T* adsPtr);
+#if (defined(__MD97__) || defined(__MD97P__))
+extern void CL1D_RF_AGC_Algo_Result_Query(CL1D_RF_AGC_ALGO_RESULT_QUERY_T* adsPtr);
+#endif
+
+/**RFD DFE control interface*/
+extern void CL1D_RF_RXDFE_Iqc_Update(CL1D_RF_RXDFE_IQC_UPDATE_T* adsPtr);
+extern void CL1D_RF_RXDFE_Nco_Update(CL1D_RF_RXDFE_NCO_UPDATE_T* adsPtr);
+extern void CL1D_RF_RXDFE_Nbif_Update(CL1D_RF_RXDFE_NBIF_UPDATE_T* adsPtr);
+extern void CL1D_RF_RXDFE_Nbif_Update_Test(CL1D_RF_RXDFE_NBIF_UPDATE_T* adsPtr);
+extern void CL1D_RF_RXDFE_Sort_Done(CL1D_RF_RXDFE_SORT_DONE_T* adsPtr);
+extern void CL1D_RF_TXDFE_RF_TTG_Cfg(CL1D_RF_TXDFE_RF_TTG_CFG_T* adsPtr);
+extern void CL1D_RF_TXDFE_BB_TTG_Cfg(CL1D_RF_TXDFE_BB_TTG_CFG_T* adsPtr);
+extern void CL1D_RF_TXDFE_TTG_BB_Config(const CL1D_RF_TXDFE_BB_TTG_CFG_T *config_ptr);
+extern void CL1D_RF_RXDFE_Test_Out(void);
+extern void CL1D_RF_RXDFE_Test_Out_Cfg(CL1D_RF_RXDFE_TEST_OUT_IQ_DATA_DUMP_E dump_point);
+/**RFD test control interface*/
+extern void CL1D_RF_Test_Mode_Request(CL1D_RF_TEST_MODE_REQUEST_T* adsPtr);
+
+/**RFD NV interface */
+extern kal_int32 CL1D_RF_NV_Get(CL1D_RF_NV_T* nv_get_p);
+extern kal_int32 CL1D_RF_NV_Set(CL1D_RF_NV_T* nv_set_p);
+extern kal_int32 CL1d_RF_NV_Re_Init(CL1D_RF_NV_RE_INIT_T* re_init_p);
+
+/**RFD Band conversion interface */
+extern kal_uint8 CL1D_RF_CUST_C2k_Band_To_Rf_Band(kal_uint8 c2k_band);
+
+/** RFD TAS interface **/
+extern C2K_CUSTOM_TAS_STATE_E CL1D_RF_Tas_GetCurrentState(SysCdmaBandT band, CL1D_RF_RAT_E l1_rat);
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if _C2K_UTAS_SUPPORT_
+extern void CL1D_RF_Cust_TAS_Init(void);
+extern void CL1D_RF_META_InitCalibrationState(boot_mode_type current_mode);
+#endif
+extern C2K_CUSTOM_TAS_VER_E CL1D_RF_Tas_GetVersion(void);
+extern kal_bool CL1D_RF_Tas2_IsEnable(CL1D_RF_BAND_E rf_band);
+extern void CL1D_RF_Tas_Update_State(SysCdmaBandT band,
+ C2K_CUSTOM_TAS_STATE_E state,
+ CL1D_RF_RAT_E l1_rat);
+extern void CL1D_RF_Tas_Update_ATcmd_Info(CL1D_RF_TAS_AT_CMD_T* tasAtCmdInfoPtr);
+extern void CL1D_RF_Tas_Update_SIM_Status(kal_bool tstSIMstatus);
+/*TAS NVRAM API*/
+/*Api-1 */
+extern C2K_CUSTOM_TAS_STATE_E TasForceStateInfo(SysCdmaBandT band);
+/*Api-2 */
+extern void CL1D_TAS_ENABLE_SETTING(kal_bool nvram_write);
+/*Api-3 */
+extern void FORCE_TAS_STATE_TO_NVRAM(
+ C2K_CUSTOM_TAS_STATE_E TasState,
+ kal_bool nvram_write);
+/*Api-4 */
+extern void FORCE_TAS_STATE_BY_BAND(
+ C2K_CUSTOM_TAS_STATE_E TasState,
+ SysCdmaBandT band);
+/*Api-5 */
+extern C2K_CUSTOM_TAS_STATE_E RESTORE_TAS_STATE_BY_BAND(SysCdmaBandT band);
+
+/*Api-6 */
+#if (!defined(__MD97__) && !defined(__MD97P__))
+extern C2K_CUSTOM_TAS_FEATURE_BY_RAT_T* TasByRatInfoQuery(void);
+#endif
+
+/**Turn On Pa**/
+extern void CL1D_RF_Vpa_Enable(kal_bool vpa_en,SysCdmaBandT band);
+
+/**Send/Read BSI/MIPI/BPI CW**/
+void CL1D_RF_IMM_SEND_BSI(kal_uint16 bsiid, kal_uint32 bsiaddr, kal_uint32 bsidata);
+void CL1D_RF_IMM_READ_BSI(kal_uint16 bsiid, kal_uint32 bsiaddr, kal_uint32* bsidata);
+void CL1D_RF_IMM_SEND_MIPI(kal_uint16 mipiport, kal_uint32 mipiusid, kal_uint32 mipiaddr, kal_uint32 mipidata);
+void CL1D_RF_IMM_READ_MIPI(kal_uint16 mipiport, kal_uint32 mipiusid, kal_uint32 mipiaddr, kal_uint32* mipidata);
+void CL1D_RF_IMM_SEND_BPI(CL1D_RF_RAT_TYPE_E rat_mode, kal_uint32 bpidata);
+void CL1D_RF_IMM_READ_BPI(CL1D_RF_RAT_TYPE_E rat_mode, kal_uint32* bpidata);
+
+/**RFD Trace**/
+void CL1D_RF_Log_Tick(CL1D_RF_RAT_TYPE_E rat);
+void CL1D_RF_Dump_Bsi_Bpi_Mipi_Cw_Logger(void);
+
+/**RF conflict checking interface**/
+void CL1D_RF_Bpi_Conflict_Check(CL1D_RF_RAT_TYPE_E rat);
+
+#if CL1D_RXDFE_DUMP_ENA
+#define CL1TST_RX_TX_IQ_DUMP_NUM 12800
+
+#if defined(__MD95__)
+extern void CL1D_RF_RXDFE_IQ_DUMP_CAS(CL1D_RF_RXDFE_IQ_DUMP_T* dump_param);
+#elif (defined(__MD97__) || defined(__MD97P__))
+#if CL1D_RXDFE_DUMP_ENA
+extern kal_int32 cl1d_rf_rxtxdfe_dump_size ;
+extern kal_int32 cl1d_rf_rxtxdfe_buffer_num;
+#endif
+extern void CL1D_RF_RXDFE_IQ_Dump_Cfg(CL1D_RF_RXDFE_IQ_DUMP_Input_T * dump_param,CL1D_RF_RXDFE_IQ_DUMP_Output_T* dump_output);
+extern void CL1D_RF_RXTXDFE_IQ_Dump_Query(CL1D_RF_RXTXDFE_IQ_DUMP_QURY_T * dump_param);
+extern void CL1D_RF_RXDFE_TTG_Config(CL1D_RF_RXDFE_TTG_Input_T* adsPtr);
+#endif
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+/**RF control tick**/
+extern void CL1D_RF_Ctrl_Tick(CL1D_RF_RAT_TYPE_E rat);
+extern void CL1D_RF_TXDFE_Nco_Update(const CL1D_RF_TXDFE_NCO_UPDATE_T *config_ptr);
+#endif
+#if (defined(__MD97__) || defined(__MD97P__))
+extern void CL1D_RF_TXDFE_CG_CTRL(kal_bool en);
+#endif
+
+extern void CL1D_RF_TXDFE_IQ_Dump_Cfg(CL1D_RF_TXDFE_IQ_DUMP_INPUT_T* config_ptr, CL1D_RF_TXDFE_IQ_DUMP_OUTPUT_T *dump_output );
+extern void CL1D_RF_TXDFE_IQ_Dump_Cfg_Tmp(CL1D_RF_TXDFE_IQ_DUMP_INPUT_T* config_ptr, CL1D_RF_TXDFE_IQ_DUMP_OUTPUT_T *dump_output );
+
+extern void CL1D_RF_TXKDFE_IQ_Dump_Cfg(CL1D_RF_TXKDFE_IQ_DUMP_INPUT_T* config_ptr, CL1D_RF_TXKDFE_IQ_DUMP_OUTPUT_T *dump_output );
+
+#if defined(__MD97__)
+extern void CL1D_RF_PA_FK_Result_Query(kal_uint8 c2k_band_class, CL1D_RF_TX_LEAKAGE_PA_FK_RESULT_T *p_pa_fk_result);
+#endif
+
+#if _C2K_UTAS_SUPPORT_97
+extern MMRFD_CUSTOM_TAS_STATE_E CL1D_RF_TAS_Get_Init_State(C2K_BOOT_MODE_TYPE_E current_mode, CL1D_RF_BAND_E band_idx);
+extern void CL1D_RF_TAS_Update_SIM_Status(kal_bool tstSIMstatus);
+extern kal_bool CL1D_RF_TAS_Is_Enable(SysCdmaBandT c2k_band);
+extern C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T* CL1D_RF_TAS_Get_Alogrithm_Parameter(void);
+extern MMRFD_ANT_HW_LAYOUT_GROUP_IDX_E CL1D_RF_TAS_Get_Hw_Group(SysCdmaBandT band);
+extern void CL1D_RF_TAS_Enable_Setting(kal_bool nvram_write);
+extern MMRFD_CUSTOM_TAS_STATE_E CL1D_RF_TAS_Force_State_Info(SysCdmaBandT band);
+extern void CL1D_RF_TAS_Force_State_To_NV(MMRFD_CUSTOM_TAS_STATE_E TasState, kal_bool nvram_write);
+extern void CL1D_RF_TAS_Force_State_By_Band(MMRFD_CUSTOM_TAS_STATE_E TasState, SysCdmaBandT band);
+extern MMRFD_CUSTOM_TAS_STATE_E CL1D_RF_TAS_Restore_State_By_Band(SysCdmaBandT band);
+extern C2K_CUSTOM_TAS_FEATURE_T* CL1D_RF_TAS_Get_ByRat_Info(void);
+extern void CL1D_RF_TAS_Update_ATcmd_Info(CL1D_RF_TAS_AT_CMD_T* tasAtCmdInfoPtr);
+extern C2K_CUSTOM_TAS_VER_E CL1D_RF_TAS_Get_Version(void);
+extern kal_int8 CL1D_RF_TAS_Query_ANT_RSCP_Bias(kal_uint8 ant_index, kal_uint8 c2k_band);
+extern MMRFD_ANT_INDEX_TYPE_E CL1D_RF_TAS_Query_Current_TX_ANT_IDX(void);
+extern MMRFD_ANT_FE_SWITCH_NW_GROUP_E CL1D_RF_ANT_Get_FE_Swtich_NW_Group(CL1D_RF_BAND_E rf_band);
+#endif
+
+#if (defined(__MD97__) || defined(__MD97P__))
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+extern kal_bool CL1D_RF_HOPPING_FREQ_Query(CL1D_RF_HOPPING_QUERY_T* adsPtr);
+extern void CL1D_RF_HOPPING_FREQ_TABLE_INFO_Query(CL1D_RF_TABLE_INFO_QUERY_T* adsPtr);
+#endif
+#endif
+
+extern void CL1D_RF_RFPD_Info_Query(CL1D_RF_RFPD_INFO_QUERY_T* adsPtr);
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+
diff --git a/mcu/interface/l1/cl1/rfd/cl1d_rf_tst_elt_msg_struct.h b/mcu/interface/l1/cl1/rfd/cl1d_rf_tst_elt_msg_struct.h
new file mode 100644
index 0000000..d50e082
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1d_rf_tst_elt_msg_struct.h
@@ -0,0 +1,64 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+*
+* FILE NAME :elt_msg_struct.h
+*
+* DESCRIPTION :
+*
+*
+* HISTORY :
+* See Log at end of file
+*
+*****************************************************************************/
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#ifndef _CL1D_RF_TST_ELT_MSG_STRUCT_H_
+#define _CL1D_RF_TST_ELT_MSG_STRUCT_H_
+
+
+#include "cl1d_rf_tst_msg.h"
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ CL1D_RF_TST_CASE_MSG_T msg;
+}elt_cl1d_rf_tst_case_msg_struct;
+
+#endif /* _CL1D_RF_TST_ELT_MSG_STRUCT_H_ */
diff --git a/mcu/interface/l1/cl1/rfd/cl1d_rf_tst_msg.h b/mcu/interface/l1/cl1/rfd/cl1d_rf_tst_msg.h
new file mode 100644
index 0000000..fd01d98
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/cl1d_rf_tst_msg.h
@@ -0,0 +1,718 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+//#if defined(__CL1_TASK_ENABLE__)
+#include "cl1d_rf_public.h"
+//#endif
+
+#ifndef _CL1D_RF_TST_MSG_H_
+#define _CL1D_RF_TST_MSG_H_
+
+
+typedef enum
+{
+ RTT_RX_MAIN_ON_OFF = 0,
+ RTT_RX_DIV_ON_OFF,
+ RTT_RX_DIV_PARTIAL_ON_OFF,
+ RTT_RX_MAIN_DIV_ON_OFF,
+ RTT_RX_DFS,
+ RTT_TX_ON_OFF,
+ RTT_TX_TXGATE_ON_OFF,
+ RTT_TX_TPC,
+ RTT_TRX_ON_OFF,
+ RTT_HYBRID_MODE,
+ RTT_AGC_ICS,
+ RTT_AGC_FAST,
+ RTT_AGC_STEADY,
+ RTT_AGC_FHC,
+ RTT_AGC_FAST_STEADY,
+ RTT_AGC_POWER_MODE,
+ DO_RX_MAIN_ON_OFF,
+ DO_RX_DIV_ON_OFF,
+ DO_RX_DIV_PARTIAL_ON_OFF,
+ DO_RX_DFS_ACT,
+ DO_RX_DFS_IDLE,
+ DO_RX_MAIN_DIV_SEC_FHC,
+ DO_RX_AGC_FSM,
+ DO_RX_AGC_PWM,
+ DO_TX_ON_OFF,
+ DO_TX_TPC,
+ DO_TRX_ON_OFF,
+ DO_SHDR,
+ DO_HYBRID_MODE,
+ DO_AGC_ICS,
+ DO_AGC_FAST,
+ DO_AGC_STEADY,
+ DO_AGC_FHC,
+ DO_AGC_FAST_STEADY,
+ DO_AGC_POWER_MODE,
+ RTT_RX_ICS_ON,
+ RTT_RX_ICS_OFF,
+ RTT_RX_MAIN_ON,
+ RTT_RX_MAIN_OFF,
+ RTT_RX_MAIN_DIV_ON,
+ RTT_RX_MAIN_DIV_OFF,
+ RTT_TX_ON,
+ RTT_TX_OFF,
+ DO_RX_MAIN_ON,
+ DO_RX_MAIN_OFF,
+ DO_RX_FHC_ON,
+ DO_RX_FHC_OFF,
+ DO_RX_MAIN_DIV_ON,
+ DO_RX_MAIN_DIV_OFF,
+ DO_TX_ON,
+ DO_TX_OFF,
+ RX_RESULT_QUERY,
+ TXDFE_RESULT_QUERY,
+ DO_IMM_BSI_SEND,
+ DO_IMM_BSI_READ,
+ DO_IMM_MIPI_SEND,
+ DO_IMM_MIPI_READ,
+ DO_RX_AFC,
+ RTT_TPC_UPDATE_TST,
+ DO_TPC_UPDATE_TST,
+ RTT_TEST_MODE,
+ DO_TEST_MODE,
+ RTT_AGC_CFG,
+ DO_AGC_CFG,
+ RTT_AGC_CFG_TST,
+ DO_AGC_CFG_TST,
+ DFE_RX_PATH,
+ DFE_RX_DYN,
+ DFE_TX_ON,
+ DFE_TX_OFF,
+ DFE_TX_ON_CHECK,
+ DFE_TX_OFF_CHECK,
+ TPC_UPDATE_OL,
+ TPC_UPDATE_CL,
+ TXDFE_TTG_CONFIG,
+ TXDFE_DUMP_CONFIG,
+ TXKDFE_DUMP_CONFIG,
+ RXDFE_TTG_CONFIG,
+ RXDFE_DUMP_CONFIG,
+ MIPI_READ_REG,
+ MIPI_WRITE_REG,
+ TPC_PM_DOWNLOAD,
+ RTT_TPC_ON,
+ DO_TPC_ON,
+ RTT_TPC_UPDATE_TST_LOOP,
+ DO_TPC_UPDATE_TST_LOOP,
+ RTT_TPC_GATE_LOOP,
+ SYS_FRAME_TYPE_SET,
+ DFE_RX_WIN_ON,
+ DFE_RX_WIN_OFF,
+ DFE_RX_COMP,
+ DFE_SET_IQ_SWAP,
+// DFE_RX_PATH_TST,
+ DFE_RX_DYN_TST,
+ DFE_RX_FULL_SCH,
+ DFE_RX_NBIF_CHECK_TST,
+ DFE_RX_NCO_CHECK_TST,
+ DFE_RX_RFC_CHECK_TST,
+ DFE_RX_WIN_ONOFF_TST,
+ TX_RESULT_QUERY,
+ TX_DO_TPC_CFG_TEST,
+ TX_DO_TPC_CFG,
+ TX_RTT_TPC_CFG_TEST,
+ TX_RTT_TPC_CFG,
+ TX_TEMP_COMP_TEST,
+ RF_TST_CASE_NUM
+} CL1D_RF_TST_CASE_IDX_E;
+
+typedef enum
+{
+ AGC_ALGO_RESULT_CHECK,
+ AGC_FAST_STEADY_SWITCH_CHECK,
+ AGC_POWER_MODE_SWITCH_CHECK,
+ AGC_GAIN_DC_BACKUP_CHECK,
+ AGC_IQ_SWAP_CHECK,
+ AGC_FIX_GAIN_DC_CHECK,
+ RF_TST_RX_CASE_CHECK_ITEM_NUM
+}CL1D_RF_TST_RX_CASE_CHECK_ITEM_E;
+
+typedef enum
+{
+ CL1D_RF_TST_REQ_SUCCESS,
+ CL1D_RF_TST_REQ_FAILURE,
+ CL1D_RF_TST_REQ_NOT_SUPPORT,
+ CL1D_RF_TST_REQ_INVALID = 0x7FFFFFFF
+}CL1D_RF_TST_REQ_STATUS_E;
+
+typedef enum
+{
+ CL1D_RF_TST_SYS_FRAME_SIZE_20MS = 0,
+ CL1D_RF_TST_SYS_FRAME_SIZE_26MS = 1
+}CL1D_RF_TST_SYS_FRAME_SIZE_E;
+
+typedef struct
+{
+ kal_uint32 dummy;
+} CL1D_RF_TST_CASE_NULL_T;
+
+typedef enum
+{ /* following number are according to HWPOR port select */
+ CL1D_MML1_RF_RFIC1 = 0x0000,
+ CL1D_MML1_RF_RFIC2 = 0x0001,
+ CL1D_MML1_RF_PMIC = 0x0002,
+ CL1D_MML1_RF_MIPI0 = 0x0003,
+ CL1D_MML1_RF_MIPI1 = 0x0004,
+ CL1D_MML1_RF_MIPI2 = 0x0005,
+ CL1D_MML1_RF_MIPI3 = 0x0006,
+ CL1D_MML1_RF_MIPI4 = 0x0007,
+#if IS_MML1_CHIP_MT6292_AND_LATTER_VERSION
+ CL1D_MML1_RF_MIPI5 = 0x0008,
+ CL1D_MML1_RF_MIPI6 = 0x0009,
+ CL1D_MML1_RF_MIPI7 = 0x000A,
+#endif
+ CL1D_MML1_RF_PORT_CNT,
+ CL1D_MML1_RF_PORT_ENDMARK,
+}CL1D_MML1_RF_BSIMM_PORT_T;
+
+typedef enum
+{
+ CL1D_MML1_MIPI_RW = 0x0000,
+ CL1D_MML1_MIPI_EXTRW_1BYTE = 0x0001,
+ CL1D_MML1_MIPI_EXTRW_2BYTE = 0x0002,
+ CL1D_MML1_MIPI_EXTRW_3BYTE = 0x0003,
+ CL1D_MML1_MIPI_EXTRW_4BYTE = 0x0004,
+ CL1D_MML1_MIPI_SUPPORT_RW_CNT,
+}CL1D_MML1_MIPI_REG_RW_T;
+
+typedef struct
+{
+ CL1D_MML1_RF_BSIMM_PORT_T port;
+ kal_uint32 bsidata;
+} BSI_SEND_T;
+
+typedef struct
+{
+ CL1D_MML1_RF_BSIMM_PORT_T port;
+ kal_uint32 bsiaddr;
+} BSI_READ_T;
+
+typedef struct
+{
+ CL1D_MML1_RF_BSIMM_PORT_T port;
+ CL1D_MML1_MIPI_REG_RW_T rw_type;
+ kal_uint32 bsidata1;
+ kal_uint32 bsidata2;
+} MIPI_SEND_T;
+
+typedef struct
+{
+ CL1D_MML1_RF_BSIMM_PORT_T port;
+ CL1D_MML1_MIPI_REG_RW_T rw_type;
+ kal_uint32 bsiaddr;
+} MIPI_READ_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - Indicate whether FSM is valid */
+ kal_bool agc_fsm_vld;
+ /** [in] - ICS/FAST/STEADY, ICS state only for EVDO */
+ kal_uint8 agc_fsm;
+ /** [in] - Indicate whether power mode is valid */
+ kal_bool power_mode_vld;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+}CL1D_RF_TST_AGC_CFG_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Rx timer value, range is 0~0xBFFFF */
+ kal_uint32 rx_stime;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - 0: AGC fix gain mode 1: AGC manual mode */
+ kal_uint8 test_mode;
+ /** [in] - ICS/FAST/STEADY/FHC */
+ kal_uint8 agc_fsm;
+ /** [in] - power mode of CL1D_RF_PWR_MODE_E*/
+ kal_uint8 power_mode;
+ /** [in] - LNA index of CL1D_RF_LNA_MODE_E*/
+ kal_uint8 lna_idx;
+ /** [in] - Rx timer value, range is 0~0xBFFFF, indicate when to begin RSSI average,
+ 0xFFFFFFFF means no time limitation
+ */
+ kal_uint32 rssi_avg_start_time;
+
+ /** [in] - Rx timer value, range is 0~0xBFFFF, indicate when to end RSSI average,
+ 0xFFFFFFFF means no time limitation
+ */
+ kal_uint32 rssi_avg_end_time;
+#ifdef __MD97__
+ /** [in] - PGA index of CL1D_RF_PGA_INDEX_E */
+ kal_uint8 pga_idx;
+ /** [in] - digital gain in DB2 format, S5.5 */
+ kal_int32 dig_gain;
+ /** [in] - indicate which parameters to be fixed
+ bit0: rf gain
+ bit1: rf DC
+ bit2: digital gain
+ bit3: digital DC
+ */
+ kal_uint8 agcdc_fix_bmp;
+#endif
+} CL1D_RF_TST_AGC_CFG_TEST_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - Set system frame type */
+ CL1D_RF_TST_SYS_FRAME_SIZE_E sys_frame_size;
+}CL1D_RF_TST_SYS_FRAME_TYPE_SET_T;
+
+typedef struct
+{
+ /** [out] - Indicate Rx case check item */
+ CL1D_RF_TST_RX_CASE_CHECK_ITEM_E check_item;
+ /** [out] - Return case status */
+ CL1D_RF_TST_REQ_STATUS_E status;
+ /** [out] - PGA index of CL1D_RF_PGA_INDEX_E */
+ kal_uint8 pga_idx;
+ /** [out] - LNA index of CL1D_RF_LNA_MODE_E */
+ kal_uint8 lna_idx;
+ /** [out] - MLNA index of CL1D_RF_MLNA_MODE_E */
+ kal_uint8 mlna_idx;
+ /** [out] - digital gain in Q5 format */
+ kal_int32 dig_gain;
+ /** [out] - pathloss in Q5 format */
+ kal_int32 pathloss;
+ /** [out] - calculated rssi in Q5 format */
+ kal_int32 rssi;
+ /** [out] - estimated residual DC in I path */
+ kal_int32 dc_est_re_i;
+ /** [out] - estimated residual DC in Q path */
+ kal_int32 dc_est_re_q;
+ /** [out] - RF DC in I path */
+ kal_int32 rf_dc_i;
+ /** [out] - RF DC in Q path */
+ kal_int32 rf_dc_q;
+ /** [out] - digital DC in I path */
+ kal_int32 dig_dc_i;
+ /** [out] - digital DC in Q path */
+ kal_int32 dig_dc_q;
+}CL1D_RF_TST_RX_RESULT_CHECK_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - { second Rx, diversity Rx, main Rx}
+ bit0: main Rx
+ bit1: diversity Rx
+ bit2: second Rx
+ */
+ kal_uint8 path_bmp;
+ /** [in] - Indicate Rx case check item */
+ CL1D_RF_TST_RX_CASE_CHECK_ITEM_E check_item;
+}CL1D_RF_TST_RX_RESULT_QUERY_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+}CL1D_RF_TST_TPC_PM_DL_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ kal_uint8 rat_type;
+ /** [in] - 0: TPC fix power mode,1: TPC manual power mode */
+ kal_uint8 test_mode;
+ /** [in] - Tx timer value on air, range is 0~0xBFFFF */
+ kal_uint32 tx_stime;
+ /** [in] - Tx power on air in 1/64dBm unit */
+ kal_int32 target_power;
+ /** [in] - TRUE: ILPC enable,FALSE: ILPC disable */
+ kal_bool ilpc_en;
+ /** [in] - PA power control mode,0:APT mode, 1: DPD mode, 2: ET mode, 3: Auto mode */
+ kal_uint16 pa_ctrl_mode;
+ /** [in] - TRUE: DPD enable,FALSE: DPD disable */
+ kal_bool dpd_en;
+}CL1D_RF_TST_TPC_CFG_TEST_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ CL1D_RF_RAT_TYPE_E rat_type;
+ /** [in] - Tx timer value on air, range is 0~0xBFFFF */
+ kal_uint32 tx_stime;
+ /** [in] - Tx power on air in 1/64dBm unit */
+ kal_int32 target_power;
+}CL1D_RF_TST_TPC_CFG_OL_T;
+
+typedef struct
+{
+ /** [in] - Indicate the RAT type of EVDO/1XRTT */
+ CL1D_RF_RAT_TYPE_E rat_type;
+ /** [in] - Tx timer value on air, range is 0~0xBFFFF */
+ kal_uint32 tx_stime;
+ /** [in] - set rpc bit 0: decrease 1: increase */
+ kal_uint8 rpc_bit;
+ /** [in] - set rssi init value before TPC CL iteration */
+ kal_int16 rssi_init;
+ /** [in] - set TPC CL iteration times */
+ kal_int16 iter_times;
+}CL1D_RF_TST_TPC_CFG_CL_T;
+
+typedef struct
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+ /** [in] - indicate whether CL is valid */
+ kal_bool is_close_loop;
+ /** [in] - time of on air TX boundary in TX stimer, the configuration will be applied to HW after this time, unit: echip, range: 0~0xBFFFF*/
+ kal_uint32 tx_stime;
+ /** [in] - close loop step up size in 1/64dB, S2.6 unit*/
+ kal_int16 cl_step_up;
+ /** [in] - close loop step down size in 1/64dB, S2.6 unit*/
+ kal_int16 cl_step_down;
+ /** [in] - close loop adjustment limited 1/64dB, S8.6 unit*/
+ kal_int16 cl_adj_max;
+ /** [in] - close loop adjustment limited 1/64dB, S8.6 unit*/
+ kal_int16 cl_adj_min;
+ /** [in] - maximum transmit power adjustment in 1/64dB, S5.6 unit, set 0 if not use it*/
+ kal_int16 max_pwr_adj;
+ /** [in] - sim rssi value from RXAGC */
+ kal_int16 rssi_val;
+ /** [in] - RPC bit in SW mode with U2.0 unit*/
+ kal_int16 rpc_bit_sw;
+ /** [in] - KS value in SW mode with S6.6 unit*/
+ kal_int16 ks_value_sw;
+ /** [in] - RPC symbol position in SW mode with U5.0 unit*/
+ kal_int16 rpc_sym_pos_sw;
+ /** [in] - set TPC CL iteration times */
+ kal_int16 iter_times;
+}CL1D_RF_TST_TPC_CFG_T;
+
+typedef struct
+{
+ /** [out] - current op mode, U2.0, HW return, 0: ET; 1: DPD; 2: APT */
+ kal_uint8 op_mode;
+ /** [out] - PGA gain index, U5.0*/
+ kal_uint8 pga_idx;
+ /** [out] - PA gain index, U5.0*/
+ kal_uint8 pa_idx;
+ /** [out] - DET gain index, U4.0*/
+ kal_uint8 det_idx;
+ /** [out] - PGA A/B table mode, U1.0*/
+ kal_uint8 pga_mode;
+ /** [out] - desired tx gain, S7.5*/
+ kal_int32 gtx_db;
+ /** [out] - target power, S7.5*/
+ kal_int32 gtar_db;
+ /** [out] - PA gain, S6.5*/
+ kal_int32 pa_db;
+ /** [out] - PGA gain, S7.5*/
+ kal_int32 pga_db;
+ /** [out] - digital gain, S6.5*/
+ kal_int32 bb_db;
+ /** [out] - det path FE+PGA gain, S6.5*/
+ kal_int32 det_rf_db;
+ /** [out] - couplerloss gain of DET path, S6.5*/
+ kal_int32 cpl_gain;
+ /** [out] - back off gain, S6.5*/
+ kal_int32 bkf_gain;
+ /** [out] - ILPC compensation value for tx PGA gain adjustment, S4.5*/
+ kal_int32 meas_rf;
+ /** [out] - PA output power be mesured, S6.5*/
+ kal_int32 ppa_dbm;
+}CL1D_RF_TST_TX_RESULT_CHECK_T;
+
+typedef struct
+{
+ /** [in] - indicate the RAT type of EVDO/1XRTT, 0: 1XRTT; 1: EVDO */
+ kal_uint8 rat_type;
+}CL1D_RF_TST_TX_RESULT_QUERY_T;
+
+typedef struct{
+CL1D_RF_RXDFE_NBIF_UPDATE_T nbif_data;
+CL1D_RF_RXDFE_NCO_UPDATE_T nco_data;
+CL1D_RF_RXDFE_IQC_UPDATE_T iqc_data;
+}CL1D_RF_RXDFE_DYN_CFG_DATA_T;
+
+typedef struct {
+CL1D_RF_RXDFE_FC_CFG_TYPE_E cfg_type;
+CL1D_RF_RXDFE_DYN_CFG_DATA_U cfg_data;
+}CL1D_RF_TST_DFE_RX_DYN_TEST_T;
+
+
+typedef struct {
+CL1D_RF_RXDFE_FC_CFG_TYPE_E cfg_type;
+CL1D_RF_RXDFE_DYN_CFG_DATA_T cfg_data;
+}CL1D_RF_TST_DFE_RX_DYN_TEST_BORG_T;
+
+typedef struct {
+ CL1D_RF_RAT_TYPE_E rat;
+ CL1D_RF_RXDFE_SENARIO_E scenario;
+ kal_uint32 stime; /* in unit of chips */
+ CL1D_RF_BAND_CLASS_TYPE_E band;
+ CL1D_RF_RXDFE_DYN_CFG_DATA_T dyn_data;
+}CL1D_RF_TST_DFE_RX_PATH_TEST_T;
+
+typedef struct{
+kal_uint32 win_onoff_num;
+kal_uint32 p;
+}CL1D_RF_TST_DFE_RX_WIN_ONOFF_TEST_T;
+typedef enum{
+DFE_RX_FULL_SCH_CASE0,
+DFE_RX_FULL_SCH_CASE1,
+DFE_RX_FULL_SCH_CASE2,
+DFE_RX_FULL_SCH_CASE3,
+DFE_RX_FULL_SCH_CASE4,
+DFE_RX_FULL_SCH_CASE_NUM,
+}cl1d_rf_tst_dfe_rx_full_sch_e;
+typedef struct {
+cl1d_rf_tst_dfe_rx_full_sch_e case_id;
+CL1D_RF_RX_PATH_ON_T path_on;
+}CL1D_RF_TST_DFE_RX_FULL_SCH_T;
+
+
+#if defined (__MD97__) || defined (__MD97P__)
+typedef enum
+{
+ RXDFE_WIN_ON,
+ RXDFE_WIN_OFF,
+ RXDFE_IQ_SWAP,
+ RXDFE_COMP,
+ RXDFE_CASE_NUM,
+ RXDFE_CASE_INVALID = 0xFF
+}CL1D_RF_RXDFE_CASE_E;
+
+typedef struct
+{
+ //P
+ kal_uint32 iq_swap_en;
+ kal_uint32 sw_dcoc_comp_en;
+ kal_uint32 p_nbif_en;
+ kal_uint32 p_rfeq_en;
+ kal_uint32 p_fdpm_en;
+ kal_uint32 p_iqc_en;
+ kal_uint32 p_cplx_rfeq_en;
+ //L
+ kal_uint32 sw_dagc_en;
+ kal_uint32 sw_nco_lna_comp_en;
+ kal_uint32 res_phase_step_en;
+ kal_uint32 l_nco_en;
+ kal_uint32 l_nco_mbsfn_en;
+}CL1D_RF_RXDFE_REG_CTRL;
+
+typedef struct
+{
+ MMRF_COMMON_BAND_IDX_E band;
+ kal_uint32 utime;
+ //kal_uint32 adc_idx[MMRFC_C2K_ANT_NUM];
+ //MML1_CDF_DEVICE_DRIVER_RF_SX_IDX_E sx_idx;
+}CL1D_RF_TST_DFE_WIN_ON_TEST_T;
+
+typedef struct
+{
+ kal_uint32 utime;
+}CL1D_RF_TST_DFE_WIN_OFF_TEST_T;
+
+
+typedef struct
+{
+ kal_bool for_c2k;
+ //kal_uint32 p_path_idx[MMRFC_C2K_ANT_NUM];
+}CL1D_RF_TST_DFE_IQ_SWAP_TEST_T;
+
+typedef struct
+{
+ //kal_bool is_hpm;
+ kal_uint32 utime;
+ //C2K_RXDFE_RXK_COMP_IRR_T* irr[MMRFC_C2K_ANT_NUM];
+ //C2K_RXDFE_RXK_COMP_DC_T* dc[MMRFC_C2K_ANT_NUM];
+}CL1D_RF_TST_DFE_RXK_COMP_TEST_T;
+#endif
+
+typedef struct {
+ CL1D_RF_RAT_TYPE_E rat;
+ CL1D_RF_TXDFE_SENARIO_E scenario;
+ kal_uint32 stime; /* in unit of chips */
+ CL1D_RF_BAND_CLASS_TYPE_E band_class;
+}CL1D_RF_TST_TXDFE_CFG_TEST_T;
+
+typedef union
+{
+ CL1D_RF_TST_CASE_NULL_T case_data_null;
+ CL1D_RF_RX_PATH_ON_T rx_on;
+ CL1D_RF_RX_PATH_OFF_T rx_off;
+ CL1D_RF_TX_PATH_ON_T tx_on;
+ CL1D_RF_TX_PATH_OFF_T tx_off;
+ BSI_SEND_T bsi_send;
+ BSI_READ_T bsi_read;
+ MIPI_SEND_T mipi_send;
+ MIPI_READ_T mipi_read;
+ CL1D_RF_TEST_MODE_REQUEST_T test_mode;
+ CL1D_RF_TST_SYS_FRAME_TYPE_SET_T sys_frame_type_set;
+ CL1D_RF_AFC_SYNTH_OFFSET_UPDATE_T afc;
+ CL1D_RF_TST_AGC_CFG_T agc_cfg;
+ CL1D_RF_TST_AGC_CFG_TEST_T agc_cfg_tst;
+ CL1D_RF_TST_RX_RESULT_QUERY_T rx_result_query;
+ CL1D_RF_TST_DFE_RX_PATH_TEST_T rx_dfe_path;
+ CL1D_RF_TST_DFE_RX_DYN_TEST_T rx_dfe_dyn;
+ CL1D_RF_TST_TPC_CFG_OL_T tpc_ol_cfg;
+ CL1D_RF_TST_TPC_CFG_CL_T tpc_cl_cfg;
+ CL1D_RF_TST_TPC_PM_DL_T tpc_pm_dl;
+ CL1D_RF_TST_TPC_CFG_TEST_T tpc_cfg_tst;
+ CL1D_RF_TST_TPC_CFG_T tpc_cfg;
+ CL1D_RF_TST_TX_RESULT_QUERY_T tx_result_query;
+#if (defined(__MD97__) || defined(__MD97P__))
+ CL1D_RF_TXDFE_BB_TTG_CFG_T ttg_cfg;
+ CL1D_RF_TXDFE_IQ_DUMP_INPUT_T txdfe_dump_cfg;
+ CL1D_RF_TXKDFE_IQ_DUMP_INPUT_T txkdfe_dump_cfg;
+ CL1D_RF_RXDFE_TTG_Input_T rxdfe_ttg;
+ CL1D_RF_RXDFE_IQ_DUMP_Input_T rxdfe_dump;
+ CL1D_RF_MIPI_READ_T mipi_read_reg;
+ CL1D_RF_MIPI_WRITE_T mipi_write_reg;
+ CL1D_RF_TST_DFE_WIN_ON_TEST_T dfe_rx_win_on;
+ CL1D_RF_TST_DFE_WIN_OFF_TEST_T dfe_rx_win_off;
+ CL1D_RF_TST_DFE_IQ_SWAP_TEST_T dfe_rx_iq_swap;
+ CL1D_RF_TST_DFE_RXK_COMP_TEST_T dfe_rx_rxk_comp;
+ CL1D_RF_TST_DFE_RX_DYN_TEST_BORG_T rx_dfe_dyn_borg;
+ CL1D_RF_TST_DFE_RX_FULL_SCH_T rx_dfe_full_sch;
+ CL1D_RF_TST_DFE_RX_WIN_ONOFF_TEST_T rx_dfe_win_onoff;
+#endif
+} CL1D_RF_TST_CASE_DATA_T;
+
+typedef struct
+{
+ CL1D_RF_TST_CASE_IDX_E case_idx;
+ kal_uint16 case_iter_times;
+ CL1D_RF_TST_CASE_DATA_T case_data;
+} CL1D_RF_TST_CASE_MSG_T;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ CL1D_RF_TST_CASE_MSG_T msg;
+} CL1D_RF_TST_CASE_MSG_ELT_T;
+
+typedef struct
+{
+ CL1D_RF_TST_REQ_STATUS_E status;
+} CL1D_RF_TST_CASE_RSP_MSG_T;
+
+typedef struct
+{
+ CL1D_RF_TST_CASE_IDX_E case_idx;
+ CL1D_RF_RX_PATH_ON_T rx_path_on;
+ CL1D_RF_RX_PATH_OFF_T rx_path_off;
+ CL1D_RF_TST_AGC_CFG_T agc_cfg;
+ CL1D_RF_TST_AGC_CFG_TEST_T agc_cfg_tst;
+ CL1D_RF_TST_RX_RESULT_QUERY_T rx_result_query;
+ CL1D_RF_TST_SYS_FRAME_TYPE_SET_T sys_frame_type_set;
+ CL1D_RF_TST_DFE_RX_PATH_TEST_T rx_dfe_path;
+ CL1D_RF_TST_DFE_RX_DYN_TEST_T rx_dfe_dyn;
+ CL1D_RF_TST_DFE_WIN_ON_TEST_T dfe_rx_win_on;
+ CL1D_RF_TST_DFE_WIN_OFF_TEST_T dfe_rx_win_off;
+ CL1D_RF_TST_DFE_IQ_SWAP_TEST_T dfe_rx_iq_swap;
+ CL1D_RF_TST_DFE_RXK_COMP_TEST_T dfe_rx_rxk_comp;
+ CL1D_RF_TST_DFE_RX_DYN_TEST_BORG_T rx_dfe_dyn_borg;
+ CL1D_RF_TST_DFE_RX_FULL_SCH_T rx_dfe_full_sch;
+ CL1D_RF_TST_DFE_RX_WIN_ONOFF_TEST_T rx_dfe_win_onoff;
+}CL1D_RF_TST_RX_CASE_MSG_T;
+
+typedef struct
+{
+ CL1D_RF_TST_CASE_IDX_E case_idx;
+}CL1D_RF_TST_TXDFE_CASE_MSG_T;
+
+typedef struct
+{
+ CL1D_RF_TST_RX_RESULT_CHECK_T rx_result_check[CL1D_RF_MAX_NUM_OF_RX];
+}CL1D_RF_TST_RX_RESULT_CHECK_MSG_T;
+
+typedef struct
+{
+ /** [out] - TXDFE related window enable status */
+ kal_bool win_on;
+ /** [out] - TXDFE AD comp */
+ kal_bool ad_comp;
+ /** [out] - TXDFE GA comp */
+ kal_bool ga_comp;
+ /** [out] - TXDFE DC comp */
+ kal_bool dc_comp;
+ /** [out] - TXKDFE DC comp */
+ kal_bool k_dc_comp;
+ /** [out] - TXKDFE FI comp */
+ kal_bool k_fi_comp;
+ /** [out] - TXKDFE FD comp */
+ kal_bool k_fd_comp;
+ /** [out] - TXDFE related window disable status */
+ kal_bool win_off;
+}CL1D_RF_TST_TXDFE_RESULT_CHECK_T;
+
+typedef struct
+{
+ CL1D_RF_TST_TXDFE_RESULT_CHECK_T txdfe_result_check;
+}CL1D_RF_TST_TXDFE_RESULT_CHECK_MSG_T;
+
+typedef struct
+{
+ CL1D_RF_TST_CASE_IDX_E case_idx;
+ CL1D_RF_TST_TPC_PM_DL_T tpc_pm_dl;
+ CL1D_RF_TEST_MODE_REQUEST_T tx_test_mode;
+ CL1D_RF_TX_PATH_ON_T tx_path_on;
+ CL1D_RF_TX_PATH_OFF_T tx_path_off;
+ CL1D_RF_TST_TPC_CFG_TEST_T tpc_cfg_tst;
+ CL1D_RF_TST_TPC_CFG_T tpc_cfg;
+ CL1D_RF_TST_TX_RESULT_QUERY_T tx_result_query;
+}CL1D_RF_TST_TX_CASE_MSG_T;
+
+typedef struct
+{
+ CL1D_RF_TST_TX_RESULT_CHECK_T tx_result_check;
+}CL1D_RF_TST_TX_RESULT_CHECK_MSG_T;
+#endif /* _CL1D_RF_TST_MSG_H_ */
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_data_defs.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_data_defs.h
new file mode 100644
index 0000000..1958ac1
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_data_defs.h
@@ -0,0 +1,924 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#ifndef _CL1_DATA_DEFS_H_
+#define _CL1_DATA_DEFS_H_
+
+#define RF_CUST_CUSTOM_DATA_BC_SUPPORT(sETiDX) \
+{\
+ {CL1_CAT_(BAND_A_SUPPORTED_, sETiDX), CL1_CAT_(CUST_BAND_A_, sETiDX), CL1D_RF_SUB_CLASS_ALL_SUPPORTED},\
+ {CL1_CAT_(BAND_B_SUPPORTED_, sETiDX), CL1_CAT_(CUST_BAND_B_, sETiDX), CL1D_RF_SUB_CLASS_ALL_SUPPORTED},\
+ {CL1_CAT_(BAND_C_SUPPORTED_, sETiDX), CL1_CAT_(CUST_BAND_C_, sETiDX), CL1D_RF_SUB_CLASS_ALL_SUPPORTED},\
+ {CL1_CAT_(BAND_D_SUPPORTED_, sETiDX), CL1_CAT_(CUST_BAND_D_, sETiDX), CL1D_RF_SUB_CLASS_ALL_SUPPORTED},\
+ {CL1_CAT_(BAND_E_SUPPORTED_, sETiDX), CL1_CAT_(CUST_BAND_E_, sETiDX), CL1D_RF_SUB_CLASS_ALL_SUPPORTED},\
+}
+
+#define RF_CUST_CUSTOM_DATA_PA_TIMING_AND_SOURCE(sETiDX)\
+{\
+ M_US2ECHIP(CL1_CAT_(DC2DC_OFFSET_, sETiDX)),\
+},\
+{\
+ CL1_CAT_(PA_VDD_SOURCE_SEL_BAND_A_, sETiDX),\
+ CL1_CAT_(PA_VDD_SOURCE_SEL_BAND_B_, sETiDX),\
+ CL1_CAT_(PA_VDD_SOURCE_SEL_BAND_C_, sETiDX),\
+ CL1_CAT_(PA_VDD_SOURCE_SEL_BAND_D_, sETiDX),\
+ CL1_CAT_(PA_VDD_SOURCE_SEL_BAND_E_, sETiDX),\
+}
+#ifdef __MD95__
+#define RF_CUST_CUSTOM_DATA_PA_CONTROL_TYPE(sETiDX)\
+{\
+ CL1_CAT_(PA_CONTROL_SEL_BAND_A_, sETiDX),\
+ CL1_CAT_(PA_CONTROL_SEL_BAND_B_, sETiDX),\
+ CL1_CAT_(PA_CONTROL_SEL_BAND_C_, sETiDX),\
+ CL1_CAT_(PA_CONTROL_SEL_BAND_D_, sETiDX),\
+ CL1_CAT_(PA_CONTROL_SEL_BAND_E_, sETiDX)\
+}
+#endif
+#define RF_CUST_CUSTOM_DATA_RF_PORTS(sETiDX)\
+/* RX LNA port selection */\
+{\
+ CL1_CAT_(BAND_A_RX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_B_RX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_C_RX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_D_RX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_E_RX_IO_SEL_, sETiDX),\
+},\
+/* RX Diverisity LNA port selection */\
+{\
+ CL1_CAT_(BAND_A_RXD_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_B_RXD_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_C_RXD_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_D_RXD_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_E_RXD_IO_SEL_, sETiDX),\
+},\
+/* TX path selection */\
+{\
+ CL1_CAT_(BAND_A_TX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_B_TX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_C_TX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_D_TX_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_E_TX_IO_SEL_, sETiDX),\
+},\
+/* TX detect path selection */\
+{\
+ CL1_CAT_(BAND_A_TX_DET_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_B_TX_DET_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_C_TX_DET_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_D_TX_DET_IO_SEL_, sETiDX),\
+ CL1_CAT_(BAND_E_TX_DET_IO_SEL_, sETiDX),\
+}
+
+#define RF_CUST_CUSTOM_DATA_EN_ELNA(sETiDX)\
+{\
+ CL1_CAT_(RX_BAND_A_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RX_BAND_B_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RX_BAND_C_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RX_BAND_D_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RX_BAND_E_ELNA_ENABLE_, sETiDX),\
+},\
+{\
+ CL1_CAT_(RXD_BAND_A_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RXD_BAND_B_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RXD_BAND_C_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RXD_BAND_D_ELNA_ENABLE_, sETiDX),\
+ CL1_CAT_(RXD_BAND_E_ELNA_ENABLE_, sETiDX),\
+}
+
+#define RF_CUST_CUSTOM_DATA_ENS(sETiDX)\
+{\
+ /* Rx diversity enable */\
+ CL1_CAT_(RX_DIVERSITY_ENABLE_BAND_A_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ENABLE_BAND_B_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ENABLE_BAND_C_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ENABLE_BAND_D_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ENABLE_BAND_E_, sETiDX),\
+},\
+/* Rx diversity test enable. The diversity path will be always on if this is TRUE. Used by HSC */\
+{\
+ CL1_CAT_(RX_DIVERSITY_ONLY_TEST_ENABLE_BAND_A_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ONLY_TEST_ENABLE_BAND_B_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ONLY_TEST_ENABLE_BAND_C_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ONLY_TEST_ENABLE_BAND_D_, sETiDX),\
+ CL1_CAT_(RX_DIVERSITY_ONLY_TEST_ENABLE_BAND_E_, sETiDX),\
+}
+
+/* The default table of RF custom parameters */
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+#define RF_CUST_HOPPING_TBL_EN(sETiDX) \
+{\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE0_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE1_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE2_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE3_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE4_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE5_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE6_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_INTERFERENCE_FREQ_TABLE7_ENABLE_, sETiDX),\
+}
+
+#define RF_CUST_HOPPING_TBL_GROUP(gROUPiDX, tABLEiDX, sETiDX) \
+{\
+ {\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 0_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 1_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 2_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 3_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 4_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 5_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 6_), sETiDX),\
+ CL1_CAT_(CL1_CAT_(CL1_CAT_(CL1_CAT_(C2K_INTERFERENCE_FREQ_, tABLEiDX), gROUPiDX), 7_), sETiDX),\
+ }\
+}
+
+#define RF_CUST_HOPPING_TBL(tABLEiDX, sETiDX) \
+{\
+ RF_CUST_HOPPING_TBL_GROUP(_A, tABLEiDX, sETiDX),\
+ RF_CUST_HOPPING_TBL_GROUP(_B, tABLEiDX, sETiDX),\
+}
+
+#define RF_CUST_HOPPING_TBL_DATA_BASE(sETiDX) \
+{\
+ RF_CUST_HOPPING_TBL(TABLE0, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE1, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE2, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE3, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE4, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE5, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE6, sETiDX),\
+ RF_CUST_HOPPING_TBL(TABLE7, sETiDX),\
+}
+#define RF_CUST_HOPPING_DATA(sETiDX) \
+const CL1D_RF_HOPPING_DATA_BASE_T CL1_CAT_(CL1D_RF_CUST_RF_HOPPING__, sETiDX) =\
+{\
+ RF_CUST_HOPPING_TBL_EN(sETiDX),\
+ RF_CUST_HOPPING_TBL_DATA_BASE(sETiDX)\
+}
+
+
+#endif
+
+#ifdef __MD95__
+#define RF_CUST_CUSTOM_DATA(sETiDX) \
+const CL1D_RF_CUST_PARAM_T CL1_CAT_(CL1D_RF_CUST_PARAM__, sETiDX) =\
+{\
+ RF_CUST_CUSTOM_DATA_BC_SUPPORT(sETiDX),\
+ RF_CUST_CUSTOM_DATA_PA_TIMING_AND_SOURCE(sETiDX),\
+ RF_CUST_CUSTOM_DATA_RF_PORTS(sETiDX),\
+ RF_CUST_CUSTOM_DATA_ENS(sETiDX),\
+ RF_CUST_CUSTOM_DATA_PA_CONTROL_TYPE(sETiDX)\
+}
+#elif (__MD97__ || __MD97P__)
+#define RF_CUST_CUSTOM_DATA(sETiDX) \
+const CL1D_RF_CUST_PARAM_T CL1_CAT_(CL1D_RF_CUST_PARAM__, sETiDX) =\
+{\
+ RF_CUST_CUSTOM_DATA_BC_SUPPORT(sETiDX),\
+ RF_CUST_CUSTOM_DATA_ENS(sETiDX)\
+}
+#elif __MD93__
+#define RF_CUST_CUSTOM_DATA(sETiDX) \
+const CL1D_RF_CUST_PARAM_T CL1_CAT_(CL1D_RF_CUST_PARAM__, sETiDX) =\
+{\
+ RF_CUST_CUSTOM_DATA_BC_SUPPORT(sETiDX),\
+ RF_CUST_CUSTOM_DATA_PA_TIMING_AND_SOURCE(sETiDX),\
+ RF_CUST_CUSTOM_DATA_RF_PORTS(sETiDX),\
+ RF_CUST_CUSTOM_DATA_ENS(sETiDX)\
+}
+#endif
+#define RF_CUST_CUSTOM_DATA_BPI_TIMING(sETiDX) \
+{\
+ /*RX */\
+ -M_US2ECHIP(CL1_CAT_(TC_PR1_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_PR2_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_PR2B_, sETiDX)),\
+ M_US2ECHIP(CL1_CAT_(TC_PR3_, sETiDX)),\
+ M_US2ECHIP(TC_PR3A),\
+\
+ /*RXD */\
+ -M_US2ECHIP(CL1_CAT_(TC_RXD_PR1_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_RXD_PR2_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_RXD_PR2B_, sETiDX)),\
+ M_US2ECHIP(CL1_CAT_(TC_RXD_PR3_, sETiDX)),\
+ M_US2ECHIP(TC_RXD_PR3A),\
+\
+ /*TX */\
+ -M_US2ECHIP(CL1_CAT_(TC_PT1_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_PT2_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_PT2B_, sETiDX)),\
+ M_US2ECHIP(CL1_CAT_(TC_PT3_, sETiDX)),\
+ M_US2ECHIP(TC_PT3A),\
+\
+ /*TX GATE */\
+ -M_US2ECHIP(CL1_CAT_(TC_PTG1_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_PTG2_, sETiDX)),\
+ -M_US2ECHIP(CL1_CAT_(TC_PTG2B_, sETiDX)),\
+ M_US2ECHIP(CL1_CAT_(TC_PTG3_, sETiDX)),\
+ M_US2ECHIP(TC_PTG3A),\
+}
+
+/* BPI data segment default values */
+#define RF_CUST_BPI_DATA(bAND, sETiDX) \
+{\
+ CL1_CAT_(PDATA_##bAND##_PR1_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PR2_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PR2B_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PR3_, sETiDX),\
+ PDATA_##bAND##_PR3A,\
+ CL1_CAT_(PDATA_##bAND##_PT1_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PT2_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PT2B_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PT3_, sETiDX),\
+ PDATA_##bAND##_PT3A,\
+ CL1_CAT_(PDATA2_##bAND##_PR1_, sETiDX),\
+ CL1_CAT_(PDATA2_##bAND##_PR2_, sETiDX),\
+ CL1_CAT_(PDATA2_##bAND##_PR2B_, sETiDX),\
+ CL1_CAT_(PDATA2_##bAND##_PR3_, sETiDX),\
+ PDATA2_##bAND##_PR3A,\
+\
+ /* TX gate data */\
+ CL1_CAT_(PDATA_##bAND##_PTG1_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PTG2_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PTG2B_, sETiDX),\
+ CL1_CAT_(PDATA_##bAND##_PTG3_, sETiDX),\
+ PDATA_##bAND##_PTG3A,\
+}
+
+#define RF_CUST_BPI_CFG(bAND, sETiDX) \
+const CL1D_RF_CUST_BPI_CFG_T CL1_CAT_(CL1_CAT_(CL1D_RF_CUST_BPI_CFG_, bAND##_), sETiDX) =\
+{\
+ RF_CUST_BPI_DATA(bAND, sETiDX),\
+ RF_CUST_CUSTOM_DATA_BPI_TIMING(sETiDX),\
+}
+
+/*ELNA */
+#define RF_CUST_ELNA_CATEGORY(eLNAiNDEX,sETiDX) CL1_CAT_(C2K_##eLNAiNDEX##_CATEGORY_, sETiDX)
+#define RF_CUST_ELNA_MAPPING_RF_BAND(bAND,sETiDX) CL1_CAT_(C2K_##bAND##_ELNA_, sETiDX)
+#define RF_CUST_ELNA_CFG(sETiDX) \
+const CL1D_RF_CUST_ELNA_CFG_T CL1D_RF_CUST_ELNA_CFG__##sETiDX =\
+{\
+ /*ELNA Category */\
+ {\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_A_RX,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_B_RX,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_C_RX,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_D_RX,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_E_RX,sETiDX)\
+ },\
+ {\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_A_RXD,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_B_RXD,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_C_RXD,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_D_RXD,sETiDX),\
+ RF_CUST_ELNA_MAPPING_RF_BAND(BAND_E_RXD,sETiDX)\
+ }\
+}
+/* TAS TST configuration */
+#define RF_CUST_TAS_TST_STATE_INFO(bANDiDX,sETiDX) {\
+ C2K_TAS_TST_##bANDiDX##_STATE0_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE1_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE2_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE3_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE4_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE5_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE6_##sETiDX,\
+ C2K_TAS_TST_##bANDiDX##_STATE7_##sETiDX,\
+}
+
+#define RF_CUST_TAS_TST_CONFIG(sETiDX) \
+const CL1D_RF_TAS_TST_CONFIG_T CL1D_RF_TAS_TST_CONFIG__##sETiDX =\
+{\
+ C2K_TAS_TST_CONFIG_ENABLE_##sETiDX,\
+ {\
+ C2K_TAS_TST_BAND_A_##sETiDX,\
+ C2K_TAS_TST_BAND_B_##sETiDX,\
+ C2K_TAS_TST_BAND_C_##sETiDX,\
+ C2K_TAS_TST_BAND_D_##sETiDX,\
+ C2K_TAS_TST_BAND_E_##sETiDX\
+ },\
+ {\
+ RF_CUST_TAS_TST_STATE_INFO(BAND_A,sETiDX),\
+ RF_CUST_TAS_TST_STATE_INFO(BAND_B,sETiDX),\
+ RF_CUST_TAS_TST_STATE_INFO(BAND_C,sETiDX),\
+ RF_CUST_TAS_TST_STATE_INFO(BAND_D,sETiDX),\
+ RF_CUST_TAS_TST_STATE_INFO(BAND_E,sETiDX)\
+ }\
+}
+
+/* TAS default configurations */
+/*** C2K_CUSTOM_TAS_FEATURE_BY_RAT_T ***/
+#if defined(__MD97__) || defined(__MD97P__)
+#define C2K_ANT_CONFIGURE(b,sETiDX,s) C2K_ANT_##s##_CONFIGURE(b,sETiDX)
+#define C2K_ANT_SPLIT_CONFIGURE(b,sETiDX)\
+{\
+ { C2K_ANT_##b##_REAL_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_REAL_SIM_INIT_SETTING_##sETiDX },\
+ { C2K_ANT_##b##_TEST_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_TEST_SIM_INIT_SETTING_##sETiDX },\
+ C2K_ANT_##b##_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_##b##_LAYOUT_GROUP_##sETiDX,\
+ {\
+ C2K_ANT_##b##_SPLIT_NUM_##sETiDX,\
+ {\
+ {\
+ C2K_ANT_##b##_SPLIT_PART1_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART1_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART2_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART2_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART3_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART3_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART4_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART4_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART5_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART5_TUNER_CONFIG_##sETiDX\
+ }\
+ }\
+ },\
+ {\
+ C2K_##b##_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT7_RSCP_BIAS_##sETiDX\
+ }\
+}
+
+#define C2K_ANT_SINGLE_CONFIGURE(b,sETiDX)\
+{\
+ { C2K_ANT_##b##_REAL_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_REAL_SIM_INIT_SETTING_##sETiDX },\
+ { C2K_ANT_##b##_TEST_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_TEST_SIM_INIT_SETTING_##sETiDX },\
+ C2K_ANT_##b##_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_##b##_LAYOUT_GROUP_##sETiDX,\
+ {\
+ 0,\
+ {\
+ {0, C2K_ANT_##b##_TUNER_CONFIG_##sETiDX},\
+ {0, 0},\
+ {0, 0},\
+ {0, 0},\
+ {0, 0}\
+ }\
+ },\
+ {\
+ C2K_##b##_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT7_RSCP_BIAS_##sETiDX\
+ }\
+}
+
+#define RF_CUST_TAS_BY_RAT_DATA(sETiDX) \
+const C2K_CUSTOM_TAS_FEATURE_T CL1D_RF_CUST_TAS_FEATURE__##sETiDX =\
+{\
+ C2K_DAT_FEATURE_ENABLE_##sETiDX,\
+ {\
+ C2K_TAS_FORCE_ENABLE_##sETiDX,\
+ C2K_TAS_FORCE_INIT_SETTING_##sETiDX,\
+ },\
+ C2K_TAS_ENABLE_ON_REAL_SIM_##sETiDX,\
+ C2K_TAS_ENABLE_ON_TEST_SIM_##sETiDX,\
+ C2K_TAS_INIT_SETTING_##sETiDX,\
+ {\
+ C2K_ANT_BAND_A_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_BAND_B_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_BAND_C_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_BAND_D_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_BAND_E_CALIBRATION_INIT_SETTING_##sETiDX,\
+ },\
+ {\
+ {\
+ {\
+ C2K_BAND_A_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_A_TAS_ANT7_RSCP_BIAS_##sETiDX,\
+ }\
+ },\
+ {\
+ {\
+ C2K_BAND_B_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_B_TAS_ANT7_RSCP_BIAS_##sETiDX,\
+ }\
+ },\
+ {\
+ {\
+ C2K_BAND_C_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_C_TAS_ANT7_RSCP_BIAS_##sETiDX,\
+ }\
+ },\
+ {\
+ {\
+ C2K_BAND_D_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_D_TAS_ANT7_RSCP_BIAS_##sETiDX,\
+ }\
+ },\
+ {\
+ {\
+ C2K_BAND_E_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_BAND_E_TAS_ANT7_RSCP_BIAS_##sETiDX,\
+ }\
+ },\
+ },\
+}
+
+#define RF_CUST_UTAS_ALGORITHM_PARAMETER(sETiDX)\
+const C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T CL1D_RF_CUST_UTAS_ALGORITHM_PARAMETER__##sETiDX =\
+{\
+ {\
+ C2K_UTAS_STx_SO_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_STx_SO_A_THRESHOLD_INDICATING_NO_POWER_HEADROOM_##sETiDX,\
+ C2K_UTAS_STx_SO_TXP_GAIN_THRESHOLD_##sETiDX,\
+ C2K_UTAS_STx_SO_PHR_GAIN_THRESHOLD_##sETiDX,\
+ C2K_UTAS_STx_SO_PRESWITCHING_STATE_DURATION_##sETiDX,\
+ C2K_UTAS_STx_SO_INCREASED_TXP_THRESHOLD_IN_PRESWITCHING_STATE_##sETiDX,\
+ C2K_UTAS_STx_SO_THRESHOLD_FOR_SUM_OF_TXP_AND_SIGPOWER_IN_PRESWITCHING_STATE_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_PTXP_DB_LOWER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_PTXP_DB_UPPER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_PTXP_DB_INCREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_PTXP_DB_DECREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_LOWER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_UPPER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_INCREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_DECREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_TIME_DURATION_TO_RELAX_BARRIER_PARAM_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_BTx_SO_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_BTx_SO_MEAS_SIGPOWER_NUMBER_##sETiDX,\
+ C2K_UTAS_BTx_SO_SIGPOWER_CB_THRESHOLD_##sETiDX,\
+ C2K_UTAS_BTx_SO_A_THRESHOLD_INDICATING_NO_POWER_HEADROOM_##sETiDX,\
+ C2K_UTAS_BTx_SO_SIGPOWER_THRESHOLD_FOR_STARTING_TIMER_##sETiDX,\
+ C2K_UTAS_BTx_SO_INITIAL_DURATION_##sETiDX,\
+ C2K_UTAS_BTx_SO_UPPER_BOUND_##sETiDX,\
+ C2K_UTAS_BTx_SO_INCREASED_AMOUNT_DELTA_FOR_FAIL_PRE_SWITCHING_##sETiDX,\
+ C2K_UTAS_BTx_SO_PRESWITCHING_STATE_DURATION_##sETiDX,\
+ C2K_UTAS_BTx_SO_INCREASED_TXP_THRESHOLD_IN_PRE_SWITCHIN_STATE_##sETiDX,\
+ C2K_UTAS_BTx_SO_THRESHOLD_FOR_SUM_OF_TXP_AND_SIGPOWER_IN_PRESWITCHING_STAT_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_BRX_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_BRX_LOW_QUALITY_THRESHOLD_##sETiDX,\
+ C2K_UTAS_BRX_SIGPOWER_CB_THRESHOLD_##sETiDX,\
+ C2K_UTAS_BRX_LOW_SNR_THRESHOLD_##sETiDX ,\
+ C2K_UTAS_BRX_SIGPOWER_THRESHOLD_FOR_STARTING_TIMER_##sETiDX ,\
+ C2K_UTAS_BRX_INITIAL_DURATION_##sETiDX,\
+ C2K_UTAS_BRX_UPPER_BOUND_##sETiDX,\
+ C2K_UTAS_BRX_INCREASED_AMOUNT_DELTA_FOR_FAIL_PRESWITCHING_##sETiDX,\
+ C2K_UTAS_BRX_PRESWITCHING_STATE_DURATION_##sETiDX,\
+ C2K_UTAS_BRX_SIGPOWER_CB_THRESHOLD_IN_PRESWITCHING_state_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_HTP_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_HTP_A_THRESHOLD_INDICATIONG_NO_POWER_HEADROOM_##sETiDX\
+ }\
+}
+#elif __MD95__
+#define C2K_ANT_CONFIGURE(b,sETiDX,s) C2K_ANT_##s##_CONFIGURE(b,sETiDX)
+#define C2K_ANT_SPLIT_CONFIGURE(b,sETiDX)\
+{\
+ { C2K_ANT_##b##_REAL_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_REAL_SIM_INIT_SETTING_##sETiDX },\
+ { C2K_ANT_##b##_TEST_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_TEST_SIM_INIT_SETTING_##sETiDX },\
+ C2K_ANT_##b##_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_##b##_LAYOUT_GROUP_##sETiDX,\
+ {\
+ C2K_ANT_##b##_SPLIT_NUM_##sETiDX,\
+ {\
+ {\
+ C2K_ANT_##b##_SPLIT_PART1_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART1_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART2_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART2_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART3_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART3_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART4_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART4_TUNER_CONFIG_##sETiDX\
+ },\
+ {\
+ C2K_ANT_##b##_SPLIT_PART5_DL_END_##sETiDX,\
+ C2K_ANT_##b##_SPLIT_PART5_TUNER_CONFIG_##sETiDX\
+ }\
+ }\
+ },\
+ {\
+ C2K_##b##_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT7_RSCP_BIAS_##sETiDX\
+ }\
+}
+
+#define C2K_ANT_SINGLE_CONFIGURE(b,sETiDX)\
+{\
+ { C2K_ANT_##b##_REAL_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_REAL_SIM_INIT_SETTING_##sETiDX },\
+ { C2K_ANT_##b##_TEST_SIM_TAS_ENABLE_##sETiDX, C2K_ANT_##b##_TEST_SIM_INIT_SETTING_##sETiDX },\
+ C2K_ANT_##b##_CALIBRATION_INIT_SETTING_##sETiDX,\
+ C2K_ANT_##b##_LAYOUT_GROUP_##sETiDX,\
+ {\
+ 0,\
+ {\
+ {0, C2K_ANT_##b##_TUNER_CONFIG_##sETiDX},\
+ {0, 0},\
+ {0, 0},\
+ {0, 0},\
+ {0, 0}\
+ }\
+ },\
+ {\
+ C2K_##b##_TAS_ANT0_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT1_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT2_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT3_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT4_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT5_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT6_RSCP_BIAS_##sETiDX,\
+ C2K_##b##_TAS_ANT7_RSCP_BIAS_##sETiDX\
+ }\
+}
+
+#define RF_CUST_TAS_BY_RAT_DATA(sETiDX) \
+C2K_CUSTOM_TAS_FEATURE_BY_RAT_T CL1D_RF_CUST_TAS_FEATURE__##sETiDX =\
+{\
+ {C2K_TAS_FORCE_ENABLE_##sETiDX,C2K_TAS_FORCE_INIT_SETTING_##sETiDX},\
+ C2K_TAS_INIT_SETTING_##sETiDX,\
+ C2K_TAS_ENABLE_ON_REAL_SIM_##sETiDX,\
+ C2K_TAS_ENABLE_ON_TEST_SIM_##sETiDX,\
+}
+#define RF_CUST_UTAS_ALGORITHM_PARAMETER(sETiDX)\
+C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T CL1D_RF_CUST_UTAS_ALGORITHM_PARAMETER__##sETiDX =\
+{\
+ {\
+ C2K_UTAS_STx_SO_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_STx_SO_A_THRESHOLD_INDICATING_NO_POWER_HEADROOM_##sETiDX,\
+ C2K_UTAS_STx_SO_TXP_GAIN_THRESHOLD_##sETiDX,\
+ C2K_UTAS_STx_SO_PHR_GAIN_THRESHOLD_##sETiDX,\
+ C2K_UTAS_STx_SO_PRESWITCHING_STATE_DURATION_##sETiDX,\
+ C2K_UTAS_STx_SO_INCREASED_TXP_THRESHOLD_IN_PRESWITCHING_STATE_##sETiDX,\
+ C2K_UTAS_STx_SO_THRESHOLD_FOR_SUM_OF_TXP_AND_SIGPOWER_IN_PRESWITCHING_STATE_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_PTXP_DB_LOWER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_PTXP_DB_UPPER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_PTXP_DB_INCREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_PTXP_DB_DECREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_LOWER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_UPPER_BOUND_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_INCREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_DECREASED_AMOUNT_BARRIER_PARAM_##sETiDX,\
+ C2K_UTAS_HR_DB_TIME_DURATION_TO_RELAX_BARRIER_PARAM_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_BTx_SO_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_BTx_SO_MEAS_SIGPOWER_NUMBER_##sETiDX,\
+ C2K_UTAS_BTx_SO_SIGPOWER_CB_THRESHOLD_##sETiDX,\
+ C2K_UTAS_BTx_SO_A_THRESHOLD_INDICATING_NO_POWER_HEADROOM_##sETiDX,\
+ C2K_UTAS_BTx_SO_SIGPOWER_THRESHOLD_FOR_STARTING_TIMER_##sETiDX,\
+ C2K_UTAS_BTx_SO_INITIAL_DURATION_##sETiDX,\
+ C2K_UTAS_BTx_SO_UPPER_BOUND_##sETiDX,\
+ C2K_UTAS_BTx_SO_INCREASED_AMOUNT_DELTA_FOR_FAIL_PRE_SWITCHING_##sETiDX,\
+ C2K_UTAS_BTx_SO_PRESWITCHING_STATE_DURATION_##sETiDX,\
+ C2K_UTAS_BTx_SO_INCREASED_TXP_THRESHOLD_IN_PRE_SWITCHIN_STATE_##sETiDX,\
+ C2K_UTAS_BTx_SO_THRESHOLD_FOR_SUM_OF_TXP_AND_SIGPOWER_IN_PRESWITCHING_STAT_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_BRX_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_BRX_LOW_QUALITY_THRESHOLD_##sETiDX,\
+ C2K_UTAS_BRX_SIGPOWER_CB_THRESHOLD_##sETiDX,\
+ C2K_UTAS_BRX_LOW_SNR_THRESHOLD_##sETiDX ,\
+ C2K_UTAS_BRX_SIGPOWER_THRESHOLD_FOR_STARTING_TIMER_##sETiDX ,\
+ C2K_UTAS_BRX_INITIAL_DURATION_##sETiDX,\
+ C2K_UTAS_BRX_UPPER_BOUND_##sETiDX,\
+ C2K_UTAS_BRX_INCREASED_AMOUNT_DELTA_FOR_FAIL_PRESWITCHING_##sETiDX,\
+ C2K_UTAS_BRX_PRESWITCHING_STATE_DURATION_##sETiDX,\
+ C2K_UTAS_BRX_SIGPOWER_CB_THRESHOLD_IN_PRESWITCHING_state_##sETiDX\
+ },\
+ {\
+ C2K_UTAS_HTP_HYSTERESIS_DURATION_##sETiDX,\
+ C2K_UTAS_HTP_A_THRESHOLD_INDICATIONG_NO_POWER_HEADROOM_##sETiDX\
+ }\
+}
+
+#elif __MD93__
+#define RF_CUST_TAS_BY_RAT_DATA(sETiDX) \
+C2K_CUSTOM_TAS_FEATURE_BY_RAT_T CL1D_RF_CUST_TAS_FEATURE__##sETiDX =\
+{\
+ C2K_TAS_VERSION_##sETiDX,\
+ {C2K_TAS_FORCE_ENABLE_##sETiDX,C2K_TAS_FORCE_INIT_SETTING_##sETiDX},\
+ C2K_TAS_INIT_SETTING_##sETiDX,\
+ C2K_TAS_ENABLE_ON_REAL_SIM_##sETiDX,\
+ C2K_TAS_ENABLE_ON_TEST_SIM_##sETiDX,\
+}
+/*** C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T ***/
+#define C2K_SB_FE_TAS_SETTING(b,s) \
+{\
+ b##_TAS_STATE_NUM_##s,\
+ {\
+ { b##_TAS_REAL_SIM_BY_ROUTE_TAS_ENABLE_##s, b##_TAS_REAL_SIM_BY_ROUTE_INIT_SETTING_##s },\
+ { b##_TAS_TEST_SIM_BY_ROUTE_TAS_ENABLE_##s, b##_TAS_TEST_SIM_BY_ROUTE_INIT_SETTING_##s },\
+ },\
+ {\
+ { b##_TAS_STATE0_CAT_A_ROUTE_##s, b##_TAS_STATE0_CAT_B_ROUTE_##s, b##_TAS_STATE0_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE1_CAT_A_ROUTE_##s, b##_TAS_STATE1_CAT_B_ROUTE_##s, b##_TAS_STATE1_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE2_CAT_A_ROUTE_##s, b##_TAS_STATE2_CAT_B_ROUTE_##s, b##_TAS_STATE2_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE3_CAT_A_ROUTE_##s, b##_TAS_STATE3_CAT_B_ROUTE_##s, b##_TAS_STATE3_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE4_CAT_A_ROUTE_##s, b##_TAS_STATE4_CAT_B_ROUTE_##s, b##_TAS_STATE4_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE5_CAT_A_ROUTE_##s, b##_TAS_STATE5_CAT_B_ROUTE_##s, b##_TAS_STATE5_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE6_CAT_A_ROUTE_##s, b##_TAS_STATE6_CAT_B_ROUTE_##s, b##_TAS_STATE6_CAT_C_ROUTE_##s },\
+ { b##_TAS_STATE7_CAT_A_ROUTE_##s, b##_TAS_STATE7_CAT_B_ROUTE_##s, b##_TAS_STATE7_CAT_C_ROUTE_##s },\
+ },\
+}
+
+#define C2K_SB_TAS_CONFIGURE(sETiDX) \
+C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T CL1D_RF_CUST_TAS_FE_ROUTE_DATABASE__##sETiDX =\
+{\
+ {\
+ C2K_SB_FE_TAS_SETTING( C2K_Band_A , sETiDX ),\
+ C2K_SB_FE_TAS_SETTING( C2K_Band_B , sETiDX ),\
+ C2K_SB_FE_TAS_SETTING( C2K_Band_C , sETiDX ),\
+ C2K_SB_FE_TAS_SETTING( C2K_Band_D , sETiDX ),\
+ C2K_SB_FE_TAS_SETTING( C2K_Band_E , sETiDX ),\
+ }\
+}
+/*** C2K_TUNER_FE_ROUTE_TABLE ***/
+#define C2K_CUSTOM_TUNER_SETTING(b,s)\
+{\
+ {b##_TUNER_INITIAL_MAIN_ROUTE_##s,b##_TUNER_INITIAL_DIV_ROUTE_##s},\
+ {\
+ {b##_TAS_STATE0_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE0_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE1_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE1_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE2_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE2_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE3_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE3_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE4_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE4_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE5_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE5_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE6_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE6_TUNER_DIV_ROUTE_##s},\
+ {b##_TAS_STATE7_TUNER_MAIN_ROUTE_##s,b##_TAS_STATE7_TUNER_DIV_ROUTE_##s},\
+ }\
+}
+
+#define C2K_CUSTOM_TUNER_CONFIGURE(sETiDX)\
+C2K_CUSTOM_TUNER_FE_ROUTE_TABLE CL1D_RF_CUST_TUNER_FE_ROUTE_TABLE__##sETiDX=\
+{\
+ {\
+ C2K_CUSTOM_TUNER_SETTING(C2K_Band_A,sETiDX),\
+ C2K_CUSTOM_TUNER_SETTING(C2K_Band_B,sETiDX),\
+ C2K_CUSTOM_TUNER_SETTING(C2K_Band_C,sETiDX),\
+ C2K_CUSTOM_TUNER_SETTING(C2K_Band_D,sETiDX),\
+ C2K_CUSTOM_TUNER_SETTING(C2K_Band_E,sETiDX),\
+ }\
+}
+#endif
+
+#ifdef __MD93__
+/*DAT */
+#define C2K_SB_DAT_CONFIGURE(b,s)\
+{\
+ {\
+ {b##_DAT_STATE0_CAT_A_CONFIG_##s, b##_DAT_STATE0_CAT_B_CONFIG_##s}, \
+ {b##_DAT_STATE1_CAT_A_CONFIG_##s, b##_DAT_STATE1_CAT_B_CONFIG_##s} , \
+ {b##_DAT_STATE2_CAT_A_CONFIG_##s, b##_DAT_STATE2_CAT_B_CONFIG_##s} , \
+ {b##_DAT_STATE3_CAT_A_CONFIG_##s, b##_DAT_STATE3_CAT_B_CONFIG_##s} , \
+ {b##_DAT_STATE4_CAT_A_CONFIG_##s, b##_DAT_STATE4_CAT_B_CONFIG_##s} , \
+ {b##_DAT_STATE5_CAT_A_CONFIG_##s, b##_DAT_STATE5_CAT_B_CONFIG_##s} , \
+ {b##_DAT_STATE6_CAT_A_CONFIG_##s, b##_DAT_STATE6_CAT_B_CONFIG_##s} , \
+ {b##_DAT_STATE7_CAT_A_CONFIG_##s, b##_DAT_STATE7_CAT_B_CONFIG_##s} , \
+ }\
+}
+#define C2K_DAT_FE_ROUTE_DATABASE(sETiDX)\
+const CL1D_RF_DAT_FE_ROUTE_DATABASE_T CL1D_RF_DAT_FE_ROUTE_DATABASE__##sETiDX = \
+{\
+ C2K_DAT_FEATURE_ENABLE_##sETiDX,\
+ {\
+ C2K_SB_DAT_CONFIGURE( C2K_BAND_A , sETiDX ) ,\
+ C2K_SB_DAT_CONFIGURE( C2K_BAND_B , sETiDX ) ,\
+ C2K_SB_DAT_CONFIGURE( C2K_BAND_C , sETiDX ) ,\
+ C2K_SB_DAT_CONFIGURE( C2K_BAND_D , sETiDX ) ,\
+ C2K_SB_DAT_CONFIGURE( C2K_BAND_E , sETiDX ) ,\
+ }\
+}
+#else
+#define C2K_DAT_STATE_ROUTE_CONFIGURE(b,p,s)\
+{\
+ {\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE0_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE0_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE1_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE1_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE2_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE2_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE3_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE3_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE4_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE4_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE5_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE5_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE6_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE6_TUNER_CONFIG_##s\
+ },\
+ {\
+ C2K_##b##_DAT_SPLIT_##p##_STATE7_SWITCH_CONFIG_##s,\
+ C2K_##b##_DAT_SPLIT_##p##_STATE7_TUNER_CONFIG_##s\
+ }\
+ }\
+}
+
+
+#define C2K_DAT_SB_ANT_TUNER_ROUTE_CONFIGURE(b,s)\
+{\
+ C2K_##b##_DAT_SPLIT_NUM_##s,\
+ {\
+ C2K_##b##_DAT_SPLIT_PART1_DL_END_##s,\
+ C2K_##b##_DAT_SPLIT_PART2_DL_END_##s,\
+ C2K_##b##_DAT_SPLIT_PART3_DL_END_##s,\
+ C2K_##b##_DAT_SPLIT_PART4_DL_END_##s,\
+ C2K_##b##_DAT_SPLIT_PART5_DL_END_##s\
+ },\
+ {\
+ C2K_DAT_STATE_ROUTE_CONFIGURE(b,PART1,s),\
+ C2K_DAT_STATE_ROUTE_CONFIGURE(b,PART2,s),\
+ C2K_DAT_STATE_ROUTE_CONFIGURE(b,PART3,s),\
+ C2K_DAT_STATE_ROUTE_CONFIGURE(b,PART4,s),\
+ C2K_DAT_STATE_ROUTE_CONFIGURE(b,PART5,s)\
+ }\
+}
+
+#define C2K_RF_DAT_ANT_TUNER_ROUTE_DATABASE(sETiDX)\
+const CL1D_RF_DAT_ANT_TUNER_ROUTE_DATABASE_T CL1D_RF_CUST_DAT_ANT_TUNER_ROUTE_DATABASE__##sETiDX =\
+{\
+ C2K_DAT_FEATURE_ENABLE_##sETiDX,\
+ {\
+ C2K_DAT_SB_ANT_TUNER_ROUTE_CONFIGURE( BAND_A , sETiDX) ,\
+ C2K_DAT_SB_ANT_TUNER_ROUTE_CONFIGURE( BAND_B , sETiDX) ,\
+ C2K_DAT_SB_ANT_TUNER_ROUTE_CONFIGURE( BAND_C , sETiDX) ,\
+ C2K_DAT_SB_ANT_TUNER_ROUTE_CONFIGURE( BAND_D , sETiDX) ,\
+ C2K_DAT_SB_ANT_TUNER_ROUTE_CONFIGURE( BAND_E , sETiDX)\
+ }\
+};
+
+#endif
+
+/* Finished */
+#ifndef __MD93__
+#define HWD_TAS_BPI_CUSTOM_DATA_DECLARE(sETiDX) \
+extern C2K_CUSTOM_TAS_FEATURE_BY_RAT_T CL1D_RF_CUST_TAS_FEATURE__##sETiDX;\
+extern C2K_CUSTOM_ANT_FE_ROUTE_DATABASE_T C2K_ANT_FE_ROUTE_DATABASE__##sETiDX;\
+extern C2K_CUSTOM_UTAS_ALGORITHM_PARAMETER_T CL1D_RF_CUST_UTAS_ALGORITHM_PARAMETER__##sETiDX;\
+extern const CL1D_RF_DAT_ANT_TUNER_ROUTE_DATABASE_T CL1D_RF_CUST_DAT_ANT_TUNER_ROUTE_DATABASE__##sETiDX
+#else
+#define HWD_TAS_BPI_CUSTOM_DATA_DECLARE(sETiDX) \
+extern C2K_CUSTOM_TAS_FEATURE_BY_RAT_T CL1D_RF_CUST_TAS_FEATURE__##sETiDX;\
+extern C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T CL1D_RF_CUST_TAS_FE_ROUTE_DATABASE__##sETiDX;\
+extern C2K_CUSTOM_TUNER_FE_ROUTE_TABLE CL1D_RF_CUST_TUNER_FE_ROUTE_TABLE__##sETiDX;\
+extern C2K_CUSTOM_TAS_FE_CAT_A_T CL1D_RF_CUST_TAS_FE_CAT_A__##sETiDX;\
+extern C2K_CUSTOM_TAS_FE_CAT_B_T CL1D_RF_CUST_TAS_FE_CAT_B__##sETiDX;\
+extern C2K_CUSTOM_TAS_FE_CAT_C_T CL1D_RF_CUST_TAS_FE_CAT_C__##sETiDX;\
+extern C2K_CUSTOM_TUNER_BAND_T CL1D_RF_CUST_TUNER_BAND_A_##sETiDX;\
+extern C2K_CUSTOM_TUNER_BAND_T CL1D_RF_CUST_TUNER_BAND_B_##sETiDX;\
+extern C2K_CUSTOM_TUNER_BAND_T CL1D_RF_CUST_TUNER_BAND_C_##sETiDX;\
+extern C2K_CUSTOM_TUNER_BAND_T CL1D_RF_CUST_TUNER_BAND_D_##sETiDX;\
+extern C2K_CUSTOM_TUNER_BAND_T CL1D_RF_CUST_TUNER_BAND_E_##sETiDX
+
+#define HWD_TAS_MIPI_CUSTOM_DATA_DECLARE(sETiDX)\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_EVENT_BAND_A_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_EVENT_BAND_B_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_EVENT_BAND_C_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_EVENT_BAND_D_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_EVENT_BAND_E_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_DATA_BAND_A_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_DATA_BAND_B_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_DATA_BAND_C_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_DATA_BAND_D_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TUNER_ROUTE_DATA_BAND_E_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_A_Route0_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_A_Route1_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_A_Route2_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_A_Route3_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_A_Route0_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_A_Route1_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_A_Route2_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_A_Route3_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_B_Route0_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_B_Route1_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_B_Route2_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_B_Route3_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_B_Route0_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_B_Route1_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_B_Route2_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_B_Route3_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_C_Route0_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_C_Route1_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_C_Route2_##sETiDX[];\
+extern const CL1D_RF_MIPI_EVENT_TABLE_T CL1D_RF_CUST_TAS_EVENT_CAT_C_Route3_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_C_Route0_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_C_Route1_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_C_Route2_##sETiDX[];\
+extern const CL1D_RF_MIPI_DATA_SUBBAND_TABLE_T CL1D_RF_CUST_TAS_DATA_CAT_C_Route3_##sETiDX[]
+#endif
+
+#define RF_CUST_MIPI_PARAM(sETiDX) \
+const CL1D_RF_MIPI_PARAM_T CL1_CAT_(C2K__MIPI_PARAM_, sETiDX)[] =\
+{\
+ {\
+ CL1_CAT_(IS_MIPI_FRONT_END_ENABLE_, sETiDX),\
+ CL1_CAT_(C2K_MIPI_TOOL_VER_, sETiDX),\
+ },\
+}
+
+#endif /* _CL1_DATA_DEFS_H_ */
+
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi.c b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi.c
new file mode 100644
index 0000000..6039d83
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi.c
@@ -0,0 +1,272 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+
+#include "kal_general_types.h"
+#include "cl1d_rf_public.h"
+#include "cl1_rf_common.h"
+#include "nvram_enums.h"
+#include "cl1_rf_public.h"
+#include "cl1_nvram_def.h"
+#include "nvram_cl1def.h"
+#include "cl1_data_defs.h"
+#include "cl1_drdi.h"
+
+#include "mml1_custom_drdi.h" /* open drdi in mml1 */
+#include "mml1_drdi.h"
+#include "mml1_custom_drdi.h" /* use MML1 total set nums */
+#include "c2k_custom_drdi.h"
+#include "c2k_custom_drdi.c"
+
+#include "mml1_fe_public.h" /* use MML1_ELNA index */
+#include "mml1_rf_public.h" /* use PA source contol */
+#define DRDI_DEF_INCLUDE_FILE
+#define DRDI_DEF_VAR_DEFINE
+#include "cl1_drdi_defs.h"
+
+const CL1D_RF_CUST_DATA_SET_INFO_T* set_info_ptr;
+
+#define DRDI_DEF_SET_PTR_ARRAY
+const CL1D_RF_CUST_DATA_SET_INFO_T c1ld_rf_cust_data_drdi_set_ptr[C2K_TOTAL_REAL_SET_NUMS+1][CL1D_RF_NVRAM_ITEM_MAX_NUM] =
+{
+ /* +1 means including SetDefault */
+ #include "cl1_drdi_defs.h"
+};
+
+#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__) && (defined(__MD97__) || defined(__MD97P__))
+//2019_0125 OPPO SAR Extend
+#define SAR(band,value) &CL1D_RF_SAR_TX_POWER_OFFSET_##band##_Type##value
+#define SAR_TYPE(value) {{SAR(BAND_A,value), SAR(BAND_B,value), SAR(BAND_C,value), SAR(BAND_D,value), SAR(BAND_E,value)}}
+
+CL1D_RF_SAR_TYPE_T cl1d_rf_common_sar_data_base[MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM] =
+{
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 0
+ SAR_TYPE(0)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 1
+ ,SAR_TYPE(1)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 2
+ ,SAR_TYPE(2)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 3
+ ,SAR_TYPE(3)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 4
+ ,SAR_TYPE(4)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 5
+ ,SAR_TYPE(5)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 6
+ ,SAR_TYPE(6)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 7
+ ,SAR_TYPE(7)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 8
+ ,SAR_TYPE(8)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 9
+ ,SAR_TYPE(9)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 10
+ ,SAR_TYPE(10)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 11
+ ,SAR_TYPE(11)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 12
+ ,SAR_TYPE(12)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 13
+ ,SAR_TYPE(13)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 14
+ ,SAR_TYPE(14)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 15
+ ,SAR_TYPE(15)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 16
+ ,SAR_TYPE(16)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 17
+ ,SAR_TYPE(17)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 18
+ ,SAR_TYPE(18)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 19
+ ,SAR_TYPE(19)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 20
+ ,SAR_TYPE(20)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 21
+ ,SAR_TYPE(21)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 22
+ ,SAR_TYPE(22)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 23
+ ,SAR_TYPE(23)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 24
+ ,SAR_TYPE(24)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 25
+ ,SAR_TYPE(25)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 26
+ ,SAR_TYPE(26)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 27
+ ,SAR_TYPE(27)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 28
+ ,SAR_TYPE(28)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 29
+ ,SAR_TYPE(29)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 30
+ ,SAR_TYPE(30)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 31
+ ,SAR_TYPE(31)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 32
+ ,SAR_TYPE(32)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 33
+ ,SAR_TYPE(33)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 34
+ ,SAR_TYPE(34)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 35
+ ,SAR_TYPE(35)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 36
+ ,SAR_TYPE(36)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 37
+ ,SAR_TYPE(37)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 38
+ ,SAR_TYPE(38)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 39
+ ,SAR_TYPE(39)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 40
+ ,SAR_TYPE(40)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 41
+ ,SAR_TYPE(41)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 42
+ ,SAR_TYPE(42)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 43
+ ,SAR_TYPE(43)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 44
+ ,SAR_TYPE(44)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 45
+ ,SAR_TYPE(45)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 46
+ ,SAR_TYPE(46)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 47
+ ,SAR_TYPE(47)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 48
+ ,SAR_TYPE(48)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 49
+ ,SAR_TYPE(49)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 50
+ ,SAR_TYPE(50)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 51
+ ,SAR_TYPE(51)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 52
+ ,SAR_TYPE(52)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 53
+ ,SAR_TYPE(53)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 54
+ ,SAR_TYPE(54)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 55
+ ,SAR_TYPE(55)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 56
+ ,SAR_TYPE(56)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 57
+ ,SAR_TYPE(57)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 58
+ ,SAR_TYPE(58)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 59
+ ,SAR_TYPE(59)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 60
+ ,SAR_TYPE(60)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 61
+ ,SAR_TYPE(61)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 62
+ ,SAR_TYPE(62)
+ #endif
+ #if MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM > 63
+ ,SAR_TYPE(63)
+ #endif
+};
+
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi.h
new file mode 100644
index 0000000..3253c82
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi.h
@@ -0,0 +1,143 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1_DRDI_H_
+#define _CL1_DRDI_H_
+
+#define CL1_STR_(tOKEN) CL1_STR_2(tOKEN)
+#define CL1_STR_2(tOKEN) CL1_STR_1(tOKEN)
+#define CL1_STR_1(tOKEN) CL1_STR_0(tOKEN)
+#define CL1_STR_0(tOKEN) #tOKEN
+
+#define CL1_CAT_(t1, t2) CL1_CAT_2(t1, t2)
+#define CL1_CAT_2(t1, t2) CL1_CAT_1(t1, t2)
+#define CL1_CAT_1(t1, t2) CL1_CAT_0(t1, t2)
+#define CL1_CAT_0(t1, t2) t1##t2
+
+#define NVRAM_SET_IDX(sETiDX) sETiDX
+#define NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX) CL1D_RF_##nAME##_##aFFIX##_
+#define NVRAM_ITEM_MIPI_DEFAULT_PRE(nAME, aFFIX) C2K_##aFFIX##_##nAME##_
+
+#define NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_MIPI_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+#define NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, sETiDX) CL1_CAT_(NVRAM_ITEM_RF_CUST_DEFAULT_PRE(nAME, aFFIX), NVRAM_SET_IDX(sETiDX))
+
+
+
+#define CL1D_RF_CUST_PARAM_DEFINE(sETiDX) RF_CUST_CUSTOM_DATA(sETiDX)
+#define CL1D_RF_CUST_BPI_CFG_DEFINE(bAND, sETiDX) RF_CUST_BPI_CFG(bAND, sETiDX)
+#define CL1D_RF_MIPI_PARAM_DEFINE(sETiDX) RF_CUST_MIPI_PARAM(sETiDX)
+/*** TAS ***/
+/*C2K_CUSTOM_TAS_FEATURE_BY_RAT_T*///Control tas.
+#define CL1D_RF_TAS_BY_RAT_DATA_DEFINE(sETiDX) RF_CUST_TAS_BY_RAT_DATA(sETiDX)
+/*C2K_CUSTOM_TAS_FE_ROUTE_DATABASE_T*///Query tas bpi/mipi detail setting by rf_band and state.
+#define CL1D_RF_TAS_CONFIGURE_DEFINE(sETiDX) C2K_SB_TAS_CONFIGURE(sETiDX)
+/*C2K_TUNER_FE_ROUTE_TABLE*/// Query tunner bpi/mipi detail setting.
+#define CL1D_RF_TAS_TUNNER_CONFIGURE_DEFINE(sETiDX) C2K_CUSTOM_TUNER_CONFIGURE(sETiDX)
+/*C2K_UTAS_ALGORITHM_PARAMETER*/
+#define CL1D_RF_UTAS_ALGORITHM_PARAMETER_DEFINE(sETiDX) RF_CUST_UTAS_ALGORITHM_PARAMETER(sETiDX)
+/*** TAS TST ***/
+#define CL1D_RF_TAS_TST_CONFIG_DEFINE(sETiDX) RF_CUST_TAS_TST_CONFIG(sETiDX)
+/*ELNA*/
+#define CL1D_RF_ELNA_CONFIG_DEFINE(sETiDX) RF_CUST_ELNA_CFG(sETiDX)
+
+/*DAT*/
+#define CL1D_RF_DAT_FE_ROUTE_DATABASE_DEFINE(sETiDX) C2K_DAT_FE_ROUTE_DATABASE(sETiDX)
+#define CL1D_RF_UDAT_ANT_TUNER_ROUTE_DATABASE_DEFINE(sETiDX) C2K_RF_DAT_ANT_TUNER_ROUTE_DATABASE(sETiDX)
+
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+#define CL1D_RF_CUST_RF_HOPPING_DEFINE(sETiDX) RF_CUST_HOPPING_DATA(sETiDX)
+#endif
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+#endif /* _CL1_DRDI_H_ */
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi_defs.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi_defs.h
new file mode 100644
index 0000000..c97f3a1
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_drdi_defs.h
@@ -0,0 +1,927 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD97__) || defined(__MD97P__)
+#ifdef DRDI_DEF_INCLUDE_FILE/*SetDefault always exist */
+ #include "DRDI/Set0/c2k_custom_rf.h"
+ #include "c2k_custom_cal_data.c"
+ #include "DRDI/Set0/c2k_custom_rf.c"
+
+ /*DPD custom file*/
+ #include "DRDI/Set0/c2k_custom_rf_dpd.h"
+ #include "DRDI/Set0/c2k_custom_rf_dpd.c"
+
+ /*TAS custom file*/
+ #include "DRDI/Set0/c2k_custom_rf_tas.h"
+ #include "DRDI/Set0/c2k_custom_rf_tas.c"
+
+ /*DAT custom file*/
+ #include "DRDI/Set0/c2k_custom_rf_dat.h"
+ #include "DRDI/Set0/c2k_custom_rf_dat.c"
+
+ /*OPPO common SAR*/
+ #include "c2k_custom_rf_SAR_extend.c"
+#endif /* DRDI_DEF_INCLUDE_FILE */
+
+#ifdef DRDI_DEF_VAR_DECLARE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_ELNA_ARRAY
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, Set0)[];
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0)[];
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_ELNA_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0)[];
+/*TX POWER */
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, Set0);
+/*TAS TST */
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, Set0);
+#include "cl1_nvram_id.h"
+#endif /* DRDI_DEF_VAR_DECLARE */
+
+#ifdef DRDI_DEF_VAR_DEFINE
+ CL1D_RF_CUST_PARAM_DEFINE(Set0);
+ CL1D_RF_TAS_BY_RAT_DATA_DEFINE(Set0);
+ CL1D_RF_UTAS_ALGORITHM_PARAMETER_DEFINE(Set0);
+
+#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+ CL1D_RF_CUST_RF_HOPPING_DEFINE(Set0);
+#endif
+
+#endif /* DRDI_DEF_VAR_DEFINE */
+
+#ifdef DRDI_DEF_SET_PTR_ARRAY
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_ELNA_ARRAY
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, Default),
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default),
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_ELNA_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, Set0),
+{
+ #include "cl1_nvram_id.h"
+},
+#endif /* DRDI_DEF_SET_PTR_ARRAY */
+#ifdef DRDI_DEF_VAR_DECLARE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern CL1D_RF_##tYPE NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"
+#endif
+#ifdef DRDI_DEF_VAR_DEFINE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ CL1D_RF_##tYPE NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"
+#endif
+
+#endif
+
+#if defined(__MD95__)
+#ifdef DRDI_DEF_INCLUDE_FILE/*SetDefault always exist */
+ #include "DRDI/Set0/c2k_custom_rf.h"
+ #include "DRDI/Set0/c2k_custom_rf.c"
+ #include "DRDI/Set0/c2k_custom_mipi.h"
+ #include "DRDI/Set0/c2k_custom_mipi.c"
+ #include "DRDI/Set0/c2k_custom_etm.h"
+ #include "DRDI/Set0/c2k_custom_etm.c"
+ /*TAS custom file*/
+ #if (_C2K_UTAS_SUPPORT_) || (__MD95__)
+ #include "DRDI/Set0/c2k_custom_rf_ant.h"
+ #include "DRDI/Set0/c2k_custom_rf_ant.c"
+ /*remove __MD97__ when GEN 97 custom file ready */
+ #elif (_C2K_TAS_SUPPORT_) || (__MD97__) || (__MD97P__)
+ #ifdef L1_SIM
+ #include "DRDI/Set0/c2k_custom_rf_ant.h"
+ #include "DRDI/Set0/c2k_custom_rf_ant.c"
+ #else
+ #include "DRDI/Set0/c2k_custom_rf_tas.h"
+ #include "DRDI/Set0/c2k_custom_rf_tas.c"
+ #include "DRDI/Set0/c2k_custom_rf_tuner.h"
+ #include "DRDI/Set0/c2k_custom_rf_tuner.c"
+ #endif
+ #endif
+ #include "DRDI/Set0/c2k_custom_rf_tas_tst.h"
+
+ #if (IS_C2K_DAT_RFD_CTRL_EN)||(IS_C2K_UDAT_SUPPORT)
+ /*DAT custom file*/
+ #include "DRDI/Set0/c2k_custom_rf_dat.h"
+ #include "DRDI/Set0/c2k_custom_rf_dat.c"
+ #endif
+ /*DPD custom file*/
+ #include "DRDI/Set0/c2k_custom_rf_dpd.h"
+ #include "DRDI/Set0/c2k_custom_rf_dpd.c"
+#endif /* DRDI_DEF_INCLUDE_FILE */
+
+#ifdef DRDI_DEF_VAR_DECLARE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_ELNA_ARRAY
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, Set0)[];
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0)[];
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0);
+#define NVRAM_ITEM_ELNA_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0)[];
+/*TX POWER */
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, Set0);
+/*TAS TST */
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, Set0);
+#include "cl1_nvram_id.h"
+#endif /* DRDI_DEF_VAR_DECLARE */
+
+#ifdef DRDI_DEF_VAR_DEFINE
+ CL1D_RF_CUST_PARAM_DEFINE(Set0);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_A, Set0);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_B, Set0);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_C, Set0);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_D, Set0);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_E, Set0);
+ CL1D_RF_MIPI_PARAM_DEFINE(Set0);
+ /***TAS macro var define***/
+
+ CL1D_RF_TAS_BY_RAT_DATA_DEFINE(Set0);
+#ifdef __MD95__
+ CL1D_RF_UTAS_ALGORITHM_PARAMETER_DEFINE(Set0);
+#endif
+#if defined(__MD93__)
+ CL1D_RF_TAS_CONFIGURE_DEFINE(Set0);
+ CL1D_RF_TAS_TUNNER_CONFIGURE_DEFINE(Set0);
+ /*TAS TST macro define */
+#endif
+ CL1D_RF_TAS_TST_CONFIG_DEFINE(Set0);
+
+ /*ELNA*/
+ CL1D_RF_ELNA_CONFIG_DEFINE(Set0);
+ #if IS_C2K_DAT_RFD_CTRL_EN
+ /*DAT*/
+ CL1D_RF_DAT_FE_ROUTE_DATABASE_DEFINE(Set0);
+ #endif
+ #if IS_C2K_UDAT_SUPPORT
+ CL1D_RF_UDAT_ANT_TUNER_ROUTE_DATABASE_DEFINE(Set0);
+ #endif
+#endif /* DRDI_DEF_VAR_DEFINE */
+
+#ifdef DRDI_DEF_SET_PTR_ARRAY
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_ELNA_ARRAY
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default),
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_ELNA_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, Set0),
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, Set0),
+{
+ #include "cl1_nvram_id.h"
+},
+#endif /* DRDI_DEF_SET_PTR_ARRAY */
+#ifdef DRDI_DEF_VAR_DECLARE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern CL1D_RF_##tYPE NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"
+#endif
+#ifdef DRDI_DEF_VAR_DEFINE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ CL1D_RF_##tYPE NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"
+#endif
+
+#endif
+
+#if defined(__MD93__)
+#ifdef DRDI_DEF_INCLUDE_FILE/*SetDefault always exist */
+ #include "c2k_custom_rf.h"
+ #include "c2k_custom_rf.c"
+ #include "c2k_custom_mipi.h"
+ #include "c2k_custom_mipi.c"
+ #include "c2k_custom_etm.h"
+ #include "c2k_custom_etm.c"
+ /*TAS custom file*/
+ #include "c2k_custom_rf_tas.h"
+ #include "c2k_custom_rf_tas_tst.h"
+ #include "c2k_custom_rf_tas.c"
+ #include "c2k_custom_rf_tuner.h"
+ #include "c2k_custom_rf_tuner.c"
+ /*ELNA custom file*/
+ #include "c2k_custom_elna.h"
+ #include "c2k_custom_elna.c"
+ #if (IS_C2K_DAT_RFD_CTRL_EN)||(IS_C2K_UDAT_SUPPORT)
+ /*DAT custom file*/
+ #include "c2k_custom_rf_dat.h"
+ #include "c2k_custom_rf_dat.c"
+ #endif
+ /*DPD custom file*/
+ #include "c2k_custom_rf_dpd.h"
+ #include "c2k_custom_rf_dpd.c"
+#endif /* DRDI_DEF_INCLUDE_FILE */
+
+#ifdef DRDI_DEF_VAR_DECLARE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, SetDefault);
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, SetDefault)[];
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, SetDefault);
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, SetDefault);
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, SetDefault)[];
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, SetDefault);
+/*TX POWER */
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, SetDefault);
+/*TAS TST */
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, SetDefault);
+#include "cl1_nvram_id.h"
+#endif /* DRDI_DEF_VAR_DECLARE */
+
+#ifdef DRDI_DEF_VAR_DEFINE
+ CL1D_RF_CUST_PARAM_DEFINE(SetDefault);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_A, SetDefault);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_B, SetDefault);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_C, SetDefault);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_D, SetDefault);
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_E, SetDefault);
+ CL1D_RF_MIPI_PARAM_DEFINE(SetDefault);
+ /***TAS macro var define***/
+
+ CL1D_RF_TAS_BY_RAT_DATA_DEFINE(SetDefault);
+ CL1D_RF_TAS_CONFIGURE_DEFINE(SetDefault);
+ CL1D_RF_TAS_TUNNER_CONFIGURE_DEFINE(SetDefault);
+ /*TAS TST macro define */
+ CL1D_RF_TAS_TST_CONFIG_DEFINE(SetDefault);
+ /*ELNA*/
+ CL1D_RF_ELNA_CONFIG_DEFINE(SetDefault);
+ #if IS_C2K_DAT_RFD_CTRL_EN
+ /*DAT*/
+ CL1D_RF_DAT_FE_ROUTE_DATABASE_DEFINE(SetDefault);
+ #endif
+#endif /* DRDI_DEF_VAR_DEFINE */
+
+#ifdef DRDI_DEF_SET_PTR_ARRAY
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default),
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, SetDefault),
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, SetDefault),
+{
+ #include "cl1_nvram_id.h"
+},
+#endif /* DRDI_DEF_SET_PTR_ARRAY */
+
+#ifdef DRDI_DEF_VAR_DECLARE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern CL1D_RF_##tYPE NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"
+#endif
+#ifdef DRDI_DEF_VAR_DEFINE
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ CL1D_RF_##tYPE NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default);
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+#include "cl1_nvram_id.h"
+#endif
+
+#endif
+
+#if IS_C2K_DRDI_ENABLE
+//#error "I can see here"
+#if defined(__MD93__)
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 0
+#include "cl1_nvram_file_id.h"
+#endif
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 1
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 2
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 3
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 4
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 5
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 6
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 7
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 8
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 9
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 10
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 11
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 12
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 13
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 14
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 15
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 16
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 17
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 18
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 19
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 20
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 21
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 22
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 23
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 24
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 25
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 26
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 27
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 28
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 29
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 30
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 31
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 32
+#include "cl1_nvram_file_id.h"
+#if defined(__MD93__)
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 33
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 34
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 35
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 36
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 37
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 38
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 39
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 40
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 41
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 42
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 43
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 44
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 45
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 46
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 47
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 48
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 49
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 50
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 51
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 52
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 53
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 54
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 55
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 56
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 57
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 58
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 59
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 60
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 61
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 62
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 63
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 64
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 65
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 66
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 67
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 68
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 69
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 70
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 71
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 72
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 73
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 74
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 75
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 76
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 77
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 78
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 79
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 80
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 81
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 82
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 83
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 84
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 85
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 86
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 87
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 88
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 89
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 90
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 91
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 92
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 93
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 94
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 95
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 96
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 97
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 98
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 99
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 100
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 101
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 102
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 103
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 104
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 105
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 106
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 107
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 108
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 109
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 110
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 111
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 112
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 113
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 114
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 115
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 116
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 117
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 118
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 119
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 120
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 121
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 122
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 123
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 124
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 125
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 126
+#include "cl1_nvram_file_id.h"
+#undef DRDI_CUR_SET_IDX
+#define DRDI_CUR_SET_IDX 127
+#include "cl1_nvram_file_id.h"
+#endif /* IS_C2K_DRDI_ENABLE */
+#endif
+
+#undef DRDI_DEF_INCLUDE_FILE
+#undef DRDI_DEF_VAR_DECLARE
+#undef DRDI_DEF_VAR_DEFINE
+#undef DRDI_DEF_SET_PTR_ARRAY
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_nvram_file_id.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_nvram_file_id.h
new file mode 100644
index 0000000..8a8b5a0
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_nvram_file_id.h
@@ -0,0 +1,260 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__) || defined(__MD95__)
+#if C2K_TOTAL_REAL_SET_NUMS > DRDI_CUR_SET_IDX
+ #ifdef DRDI_DEF_INCLUDE_FILE
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf.c)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_mipi.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_mipi.c)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_etm.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_etm.c)
+#ifndef __MD93__
+ #if (_C2K_UTAS_SUPPORT_) || (__MD95__) || (__MD97__) || (__MD97P__)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_ant.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_ant.c)
+ #endif
+#else
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tas.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tas.c)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tuner.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tuner.c)
+
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_elna.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_elna.c)
+#endif
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tas_tst.h)
+ #if (IS_C2K_DAT_RFD_CTRL_EN)||(IS_C2K_UDAT_SUPPORT)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dat.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dat.c)
+ #endif
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dpd.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dpd.c)
+#endif
+
+ #ifdef DRDI_DEF_VAR_DECLARE
+ #undef NVRAM_ITEM_RF_CUST
+ #undef NVRAM_ITEM_MIPI
+ #undef NVRAM_ITEM_RF_CAL
+ #undef NVRAM_ITEM_RF_POC
+ #undef NVRAM_ITEM_RF_TAS_VAR
+ #undef NVRAM_ITEM_RF_TAS_ARRAY
+ #undef NVRAM_ITEM_ELNA_VAR
+ #undef NVRAM_ITEM_TX_POWER_VAR
+ #undef NVRAM_ITEM_RF_TAS_TST
+ #define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX))[];
+ #define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern CL1D_RF_##tYPE NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const C2K_CUSTOM_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX))[];
+ #define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+ #define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #include "cl1_nvram_id.h"
+ #endif /* DRDI_DEF_VAR_DECLARE */
+
+ #ifdef DRDI_DEF_VAR_DEFINE
+ CL1D_RF_CUST_PARAM_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_A, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_B, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_C, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_D, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_CUST_BPI_CFG_DEFINE(BAND_E, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_MIPI_PARAM_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+
+ CL1D_RF_TAS_BY_RAT_DATA_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+#ifndef __MD93__
+ CL1D_RF_UTAS_ALGORITHM_PARAMETER_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+#endif
+#if defined(__MD93__)
+ CL1D_RF_TAS_CONFIGURE_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_TAS_TUNNER_CONFIGURE_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+#endif
+ /*TAS TST macro define */
+ CL1D_RF_TAS_TST_CONFIG_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ /*ELNA*/
+ CL1D_RF_ELNA_CONFIG_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #if IS_C2K_DAT_RFD_CTRL_EN
+ /*DAT*/
+ CL1D_RF_DAT_FE_ROUTE_DATABASE_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #endif
+ #if IS_C2K_UDAT_SUPPORT
+ CL1D_RF_UDAT_ANT_TUNER_ROUTE_DATABASE_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #endif
+ /* Other values are all defined in custom files */
+ #endif /* DRDI_DEF_VAR_DEFINE */
+
+ #ifdef DRDI_DEF_SET_PTR_ARRAY
+ #undef NVRAM_ITEM_RF_CUST
+ #undef NVRAM_ITEM_MIPI
+ #undef NVRAM_ITEM_RF_CAL
+ #undef NVRAM_ITEM_RF_POC
+ #undef NVRAM_ITEM_RF_TAS_VAR
+ #undef NVRAM_ITEM_RF_TAS_ARRAY
+ #undef NVRAM_ITEM_ELNA_VAR
+ #undef NVRAM_ITEM_TX_POWER_VAR
+ #undef NVRAM_ITEM_RF_TAS_TST
+ #define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default),
+ #define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ {
+ #include "cl1_nvram_id.h"
+ },
+ #endif /* DRDI_DEF_SET_PTR_ARRAY */
+#endif
+#endif
+
+#if (defined(__MD97__) || defined(__MD97P__))
+
+#if C2K_TOTAL_REAL_SET_NUMS > DRDI_CUR_SET_IDX
+ #ifdef DRDI_DEF_INCLUDE_FILE
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf.c)
+
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dpd.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dpd.c)
+
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tas.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_tas.c)
+
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dat.h)
+ #include CL1_STR_(CL1_CAT_(DRDI/Set, DRDI_CUR_SET_IDX)/c2k_custom_rf_dat.c)
+#endif
+
+ #ifdef DRDI_DEF_VAR_DECLARE
+ #undef NVRAM_ITEM_RF_CUST
+ #undef NVRAM_ITEM_MIPI
+ #undef NVRAM_ITEM_RF_CAL
+ #undef NVRAM_ITEM_RF_POC
+ #undef NVRAM_ITEM_RF_TAS_VAR
+ #undef NVRAM_ITEM_RF_TAS_ARRAY
+ #undef NVRAM_ITEM_ELNA_VAR
+ #undef NVRAM_ITEM_TX_POWER_VAR
+ #undef NVRAM_ITEM_RF_TAS_TST
+ #define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX))[];
+ #define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern CL1D_RF_##tYPE NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, Default);
+ #define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const C2K_CUSTOM_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX))[];
+ #define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC)
+ #define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ extern const CL1D_RF_##tYPE NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #include "cl1_nvram_id.h"
+ #endif /* DRDI_DEF_VAR_DECLARE */
+
+ #ifdef DRDI_DEF_VAR_DEFINE
+ CL1D_RF_CUST_PARAM_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_TAS_BY_RAT_DATA_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ CL1D_RF_UTAS_ALGORITHM_PARAMETER_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+
+ #if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+ CL1D_RF_CUST_RF_HOPPING_DEFINE(CL1_CAT_(Set, DRDI_CUR_SET_IDX));
+ #endif
+
+ /* Other values are all defined in custom files */
+ #endif /* DRDI_DEF_VAR_DEFINE */
+
+ #ifdef DRDI_DEF_SET_PTR_ARRAY
+ #undef NVRAM_ITEM_RF_CUST
+ #undef NVRAM_ITEM_MIPI
+ #undef NVRAM_ITEM_RF_CAL
+ #undef NVRAM_ITEM_RF_POC
+ #undef NVRAM_ITEM_RF_TAS_VAR
+ #undef NVRAM_ITEM_RF_TAS_ARRAY
+ #undef NVRAM_ITEM_ELNA_VAR
+ #undef NVRAM_ITEM_TX_POWER_VAR
+ #undef NVRAM_ITEM_RF_TAS_TST
+ #define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CUST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_MIPI_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_CAL_DEFAULT(nAME, aFFIX, Default),
+ #define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)NVRAM_ITEM_RF_TAS_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_POC_DEFAULT(nAME, aFFIX, Default),
+ #define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_ELNA_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TX_POWER_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ #define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ (void*)&NVRAM_ITEM_RF_TAS_TST_DEFAULT(nAME, aFFIX, CL1_CAT_(Set, DRDI_CUR_SET_IDX)),
+ {
+ #include "cl1_nvram_id.h"
+ },
+ #endif /* DRDI_DEF_SET_PTR_ARRAY */
+#endif
+
+#endif
+
+
+
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_rf_common.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_rf_common.h
new file mode 100644
index 0000000..4c88232
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1_rf_common.h
@@ -0,0 +1,1120 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1_RF_COMMON_H_
+#define _CL1_RF_COMMON_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+
+/*******************************************************************************
+** Common setting for all RF
+*******************************************************************************/
+/* This part serves as default value of undefined macro constants in c2k_custom_rf.h */
+/* Aim to accommodate to those difference between RF chips */
+
+/* --- Add the definition of l1core ---*/
+#ifndef M_US2CHIP
+#define M_US2ECHIP(uS) (((uS) * 12288 * 8 + 5000) / 10000)
+#endif
+
+
+/* --- RF supported band default value ---*/
+#ifndef CUST_BAND_A
+#define CUST_BAND_A SYS_BAND_CLASS_NOT_USED
+#define BAND_A_SUPPORTED KAL_FALSE
+#endif
+#ifndef CUST_BAND_B
+#define CUST_BAND_B SYS_BAND_CLASS_NOT_USED
+#define BAND_B_SUPPORTED KAL_FALSE
+#endif
+#ifndef CUST_BAND_C
+#define CUST_BAND_C SYS_BAND_CLASS_NOT_USED
+#define BAND_C_SUPPORTED KAL_FALSE
+#endif
+#ifndef CUST_BAND_D
+#define CUST_BAND_D SYS_BAND_CLASS_NOT_USED
+#define BAND_D_SUPPORTED KAL_FALSE
+#endif
+#ifndef CUST_BAND_E
+#define CUST_BAND_E SYS_BAND_CLASS_NOT_USED
+#define BAND_E_SUPPORTED KAL_FALSE
+#endif
+
+
+/* --- RF Window BPI mask default value --- */
+#ifndef PMASK_BAND_A_PR1
+ #define PMASK_BAND_A_PR1 0
+ #define PMASK_BAND_A_PR2 0
+ #define PMASK_BAND_A_PR3 0
+ #define PMASK_BAND_A_PT1 0
+ #define PMASK_BAND_A_PT2 0
+ #define PMASK_BAND_A_PT3 0
+#endif
+#ifndef PMASK_BAND_B_PR1
+ #define PMASK_BAND_B_PR1 0
+ #define PMASK_BAND_B_PR2 0
+ #define PMASK_BAND_B_PR3 0
+ #define PMASK_BAND_B_PT1 0
+ #define PMASK_BAND_B_PT2 0
+ #define PMASK_BAND_B_PT3 0
+#endif
+#ifndef PMASK_BAND_C_PR1
+ #define PMASK_BAND_C_PR1 0
+ #define PMASK_BAND_C_PR2 0
+ #define PMASK_BAND_C_PR3 0
+ #define PMASK_BAND_C_PT1 0
+ #define PMASK_BAND_C_PT2 0
+ #define PMASK_BAND_C_PT3 0
+#endif
+#ifndef PMASK_BAND_D_PR1
+ #define PMASK_BAND_D_PR1 0
+ #define PMASK_BAND_D_PR2 0
+ #define PMASK_BAND_D_PR3 0
+ #define PMASK_BAND_D_PT1 0
+ #define PMASK_BAND_D_PT2 0
+ #define PMASK_BAND_D_PT3 0
+#endif
+#ifndef PMASK_BAND_E_PR1
+ #define PMASK_BAND_E_PR1 0
+ #define PMASK_BAND_E_PR2 0
+ #define PMASK_BAND_E_PR3 0
+ #define PMASK_BAND_E_PT1 0
+ #define PMASK_BAND_E_PT2 0
+ #define PMASK_BAND_E_PT3 0
+#endif
+
+#ifndef PMASK_BAND_A_PR2B
+ #define PMASK_BAND_A_PR2B 0
+#endif
+#ifndef PMASK_BAND_A_PR3A
+ #define PMASK_BAND_A_PR3A 0
+#endif
+#ifndef PMASK_BAND_A_PT2B
+ #define PMASK_BAND_A_PT2B 0
+#endif
+#ifndef PMASK_BAND_A_PT3A
+ #define PMASK_BAND_A_PT3A 0
+#endif
+
+#ifndef PMASK_BAND_B_PR2B
+ #define PMASK_BAND_B_PR2B 0
+#endif
+#ifndef PMASK_BAND_B_PR3A
+ #define PMASK_BAND_B_PR3A 0
+#endif
+#ifndef PMASK_BAND_B_PT2B
+ #define PMASK_BAND_B_PT2B 0
+#endif
+#ifndef PMASK_BAND_B_PT3A
+ #define PMASK_BAND_B_PT3A 0
+#endif
+
+#ifndef PMASK_BAND_C_PR2B
+ #define PMASK_BAND_C_PR2B 0
+#endif
+#ifndef PMASK_BAND_C_PR3A
+ #define PMASK_BAND_C_PR3A 0
+#endif
+#ifndef PMASK_BAND_C_PT2B
+ #define PMASK_BAND_C_PT2B 0
+#endif
+#ifndef PMASK_BAND_C_PT3A
+ #define PMASK_BAND_C_PT3A 0
+#endif
+#ifndef PMASK_BAND_D_PR2B
+ #define PMASK_BAND_D_PR2B 0
+#endif
+#ifndef PMASK_BAND_D_PR3A
+ #define PMASK_BAND_D_PR3A 0
+#endif
+#ifndef PMASK_BAND_D_PT2B
+ #define PMASK_BAND_D_PT2B 0
+#endif
+#ifndef PMASK_BAND_D_PT3A
+ #define PMASK_BAND_D_PT3A 0
+#endif
+#ifndef PMASK_BAND_E_PR2B
+ #define PMASK_BAND_E_PR2B 0
+#endif
+#ifndef PMASK_BAND_E_PR3A
+ #define PMASK_BAND_E_PR3A 0
+#endif
+#ifndef PMASK_BAND_E_PT2B
+ #define PMASK_BAND_E_PT2B 0
+#endif
+#ifndef PMASK_BAND_E_PT3A
+ #define PMASK_BAND_E_PT3A 0
+#endif
+
+//Add for RXD
+#ifndef PMASK2_BAND_A_PR1
+ #define PMASK2_BAND_A_PR1 0
+ #define PMASK2_BAND_A_PR2 0
+ #define PMASK2_BAND_A_PR3 0
+#endif
+#ifndef PMASK2_BAND_B_PR1
+ #define PMASK2_BAND_B_PR1 0
+ #define PMASK2_BAND_B_PR2 0
+ #define PMASK2_BAND_B_PR3 0
+#endif
+#ifndef PMASK2_BAND_C_PR1
+ #define PMASK2_BAND_C_PR1 0
+ #define PMASK2_BAND_C_PR2 0
+ #define PMASK2_BAND_C_PR3 0
+#endif
+#ifndef PMASK2_BAND_D_PR1
+ #define PMASK2_BAND_D_PR1 0
+ #define PMASK2_BAND_D_PR2 0
+ #define PMASK2_BAND_D_PR3 0
+#endif
+#ifndef PMASK2_BAND_E_PR1
+ #define PMASK2_BAND_E_PR1 0
+ #define PMASK2_BAND_E_PR2 0
+ #define PMASK2_BAND_E_PR3 0
+#endif
+
+#ifndef PMASK2_BAND_A_PR2B
+ #define PMASK2_BAND_A_PR2B 0
+#endif
+#ifndef PMASK2_BAND_A_PR3A
+ #define PMASK2_BAND_A_PR3A 0
+#endif
+#ifndef PMASK2_BAND_B_PR2B
+ #define PMASK2_BAND_B_PR2B 0
+#endif
+#ifndef PMASK2_BAND_B_PR3A
+ #define PMASK2_BAND_B_PR3A 0
+#endif
+#ifndef PMASK2_BAND_C_PR2B
+ #define PMASK2_BAND_C_PR2B 0
+#endif
+#ifndef PMASK2_BAND_C_PR3A
+ #define PMASK2_BAND_C_PR3A 0
+#endif
+#ifndef PMASK2_BAND_D_PR2B
+ #define PMASK2_BAND_D_PR2B 0
+#endif
+#ifndef PMASK2_BAND_D_PR3A
+ #define PMASK2_BAND_D_PR3A 0
+#endif
+#ifndef PMASK2_BAND_E_PR2B
+ #define PMASK2_BAND_E_PR2B 0
+#endif
+#ifndef PMASK2_BAND_E_PR3A
+ #define PMASK2_BAND_E_PR3A 0
+#endif
+
+
+/* --- BPI data default value --- */
+#ifndef PDATA_BAND_A_PR1
+ #define PDATA_BAND_A_PR1 0
+ #define PDATA_BAND_A_PR2 0
+ #define PDATA_BAND_A_PR3 0
+ #define PDATA_BAND_A_PT1 0
+ #define PDATA_BAND_A_PT2 0
+ #define PDATA_BAND_A_PT3 0
+#endif
+#ifndef PDATA_BAND_B_PR1
+ #define PDATA_BAND_B_PR1 0
+ #define PDATA_BAND_B_PR2 0
+ #define PDATA_BAND_B_PR3 0
+ #define PDATA_BAND_B_PT1 0
+ #define PDATA_BAND_B_PT2 0
+ #define PDATA_BAND_B_PT3 0
+#endif
+#ifndef PDATA_BAND_C_PR1
+ #define PDATA_BAND_C_PR1 0
+ #define PDATA_BAND_C_PR2 0
+ #define PDATA_BAND_C_PR3 0
+ #define PDATA_BAND_C_PT1 0
+ #define PDATA_BAND_C_PT2 0
+ #define PDATA_BAND_C_PT3 0
+#endif
+#ifndef PDATA_BAND_D_PR1
+ #define PDATA_BAND_D_PR1 0
+ #define PDATA_BAND_D_PR2 0
+ #define PDATA_BAND_D_PR3 0
+ #define PDATA_BAND_D_PT1 0
+ #define PDATA_BAND_D_PT2 0
+ #define PDATA_BAND_D_PT3 0
+#endif
+#ifndef PDATA_BAND_E_PR1
+ #define PDATA_BAND_E_PR1 0
+ #define PDATA_BAND_E_PR2 0
+ #define PDATA_BAND_E_PR3 0
+ #define PDATA_BAND_E_PT1 0
+ #define PDATA_BAND_E_PT2 0
+ #define PDATA_BAND_E_PT3 0
+#endif
+
+#ifndef PDATA_BAND_A_PR2B
+ #define PDATA_BAND_A_PR2B 0
+#endif
+#ifndef PDATA_BAND_A_PR3A
+ #define PDATA_BAND_A_PR3A 0
+#endif
+#ifndef PDATA_BAND_A_PT2B
+ #define PDATA_BAND_A_PT2B 0
+#endif
+#ifndef PDATA_BAND_A_PT3A
+ #define PDATA_BAND_A_PT3A 0
+#endif
+
+#ifndef PDATA_BAND_B_PR2B
+ #define PDATA_BAND_B_PR2B 0
+#endif
+#ifndef PDATA_BAND_B_PR3A
+ #define PDATA_BAND_B_PR3A 0
+#endif
+#ifndef PDATA_BAND_B_PT2B
+ #define PDATA_BAND_B_PT2B 0
+#endif
+#ifndef PDATA_BAND_B_PT3A
+ #define PDATA_BAND_B_PT3A 0
+#endif
+
+#ifndef PDATA_BAND_C_PR2B
+ #define PDATA_BAND_C_PR2B 0
+#endif
+#ifndef PDATA_BAND_C_PR3A
+ #define PDATA_BAND_C_PR3A 0
+#endif
+#ifndef PDATA_BAND_C_PT2B
+ #define PDATA_BAND_C_PT2B 0
+#endif
+#ifndef PDATA_BAND_C_PT3A
+ #define PDATA_BAND_C_PT3A 0
+#endif
+
+#ifndef PDATA_BAND_D_PR2B
+ #define PDATA_BAND_D_PR2B 0
+#endif
+#ifndef PDATA_BAND_D_PR3A
+ #define PDATA_BAND_D_PR3A 0
+#endif
+#ifndef PDATA_BAND_D_PT2B
+ #define PDATA_BAND_D_PT2B 0
+#endif
+#ifndef PDATA_BAND_D_PT3A
+ #define PDATA_BAND_D_PT3A 0
+#endif
+
+#ifndef PDATA_BAND_E_PR2B
+ #define PDATA_BAND_E_PR2B 0
+#endif
+#ifndef PDATA_BAND_E_PR3A
+ #define PDATA_BAND_E_PR3A 0
+#endif
+#ifndef PDATA_BAND_E_PT2B
+ #define PDATA_BAND_E_PT2B 0
+#endif
+#ifndef PDATA_BAND_E_PT3A
+ #define PDATA_BAND_E_PT3A 0
+#endif
+
+//Add for RXD
+#ifndef PDATA2_BAND_A_PR1
+ #define PDATA2_BAND_A_PR1 0
+ #define PDATA2_BAND_A_PR2 0
+ #define PDATA2_BAND_A_PR3 0
+#endif
+#ifndef PDATA2_BAND_B_PR1
+ #define PDATA2_BAND_B_PR1 0
+ #define PDATA2_BAND_B_PR2 0
+ #define PDATA2_BAND_B_PR3 0
+#endif
+#ifndef PDATA2_BAND_C_PR1
+ #define PDATA2_BAND_C_PR1 0
+ #define PDATA2_BAND_C_PR2 0
+ #define PDATA2_BAND_C_PR3 0
+#endif
+#ifndef PDATA2_BAND_D_PR1
+ #define PDATA2_BAND_D_PR1 0
+ #define PDATA2_BAND_D_PR2 0
+ #define PDATA2_BAND_D_PR3 0
+#endif
+#ifndef PDATA2_BAND_E_PR1
+ #define PDATA2_BAND_E_PR1 0
+ #define PDATA2_BAND_E_PR2 0
+ #define PDATA2_BAND_E_PR3 0
+#endif
+
+#ifndef PDATA2_BAND_A_PR2B
+ #define PDATA2_BAND_A_PR2B 0
+#endif
+#ifndef PDATA2_BAND_A_PR3A
+ #define PDATA2_BAND_A_PR3A 0
+#endif
+#ifndef PDATA2_BAND_B_PR2B
+ #define PDATA2_BAND_B_PR2B 0
+#endif
+#ifndef PDATA2_BAND_B_PR3A
+ #define PDATA2_BAND_B_PR3A 0
+#endif
+#ifndef PDATA2_BAND_C_PR2B
+ #define PDATA2_BAND_C_PR2B 0
+#endif
+#ifndef PDATA2_BAND_C_PR3A
+ #define PDATA2_BAND_C_PR3A 0
+#endif
+#ifndef PDATA2_BAND_D_PR2B
+ #define PDATA2_BAND_D_PR2B 0
+#endif
+#ifndef PDATA2_BAND_D_PR3A
+ #define PDATA2_BAND_D_PR3A 0
+#endif
+#ifndef PDATA2_BAND_E_PR2B
+ #define PDATA2_BAND_E_PR2B 0
+#endif
+#ifndef PDATA2_BAND_E_PR3A
+ #define PDATA2_BAND_E_PR3A 0
+#endif
+
+
+/* TX GATE default value */
+#ifndef PMASK_BAND_A_PRG1
+ #define PMASK_BAND_A_PRG1 0
+ #define PMASK_BAND_A_PRG2 0
+ #define PMASK_BAND_A_PRG3 0
+#endif
+#ifndef PMASK_BAND_A_PTG1
+ #define PMASK_BAND_A_PTG1 0
+ #define PMASK_BAND_A_PTG2 0
+ #define PMASK_BAND_A_PTG3 0
+#endif
+#ifndef PMASK_BAND_B_PRG1
+ #define PMASK_BAND_B_PRG1 0
+ #define PMASK_BAND_B_PRG2 0
+ #define PMASK_BAND_B_PRG3 0
+#endif
+#ifndef PMASK_BAND_B_PTG1
+#define PMASK_BAND_B_PTG1 0
+#define PMASK_BAND_B_PTG2 0
+#define PMASK_BAND_B_PTG3 0
+#endif
+#ifndef PMASK_BAND_C_PRG1
+ #define PMASK_BAND_C_PRG1 0
+ #define PMASK_BAND_C_PRG2 0
+ #define PMASK_BAND_C_PRG3 0
+#endif
+#ifndef PMASK_BAND_C_PTG1
+#define PMASK_BAND_C_PTG1 0
+#define PMASK_BAND_C_PTG2 0
+#define PMASK_BAND_C_PTG3 0
+#endif
+#ifndef PMASK_BAND_D_PRG1
+ #define PMASK_BAND_D_PRG1 0
+ #define PMASK_BAND_D_PRG2 0
+ #define PMASK_BAND_D_PRG3 0
+#endif
+#ifndef PMASK_BAND_D_PTG1
+#define PMASK_BAND_D_PTG1 0
+#define PMASK_BAND_D_PTG2 0
+#define PMASK_BAND_D_PTG3 0
+#endif
+#ifndef PMASK_BAND_E_PRG1
+ #define PMASK_BAND_E_PRG1 0
+ #define PMASK_BAND_E_PRG2 0
+ #define PMASK_BAND_E_PRG3 0
+#endif
+#ifndef PMASK_BAND_E_PTG1
+#define PMASK_BAND_E_PTG1 0
+#define PMASK_BAND_E_PTG2 0
+#define PMASK_BAND_E_PTG3 0
+#endif
+
+#ifndef PMASK_BAND_A_PRG2B
+ #define PMASK_BAND_A_PRG2B 0
+#endif
+#ifndef PMASK_BAND_A_PRG3A
+ #define PMASK_BAND_A_PRG3A 0
+#endif
+#ifndef PMASK_BAND_A_PTG2B
+ #define PMASK_BAND_A_PTG2B 0
+#endif
+#ifndef PMASK_BAND_A_PTG3A
+ #define PMASK_BAND_A_PTG3A 0
+#endif
+
+#ifndef PMASK_BAND_B_PRG2B
+ #define PMASK_BAND_B_PRG2B 0
+#endif
+#ifndef PMASK_BAND_B_PRG3A
+ #define PMASK_BAND_B_PRG3A 0
+#endif
+#ifndef PMASK_BAND_B_PTG2B
+ #define PMASK_BAND_B_PTG2B 0
+#endif
+#ifndef PMASK_BAND_B_PTG3A
+ #define PMASK_BAND_B_PTG3A 0
+#endif
+
+#ifndef PMASK_BAND_C_PRG2B
+ #define PMASK_BAND_C_PRG2B 0
+#endif
+#ifndef PMASK_BAND_C_PRG3A
+ #define PMASK_BAND_C_PRG3A 0
+#endif
+#ifndef PMASK_BAND_C_PTG2B
+ #define PMASK_BAND_C_PTG2B 0
+#endif
+#ifndef PMASK_BAND_C_PTG3A
+ #define PMASK_BAND_C_PTG3A 0
+#endif
+
+#ifndef PMASK_BAND_D_PRG2B
+ #define PMASK_BAND_D_PRG2B 0
+#endif
+#ifndef PMASK_BAND_D_PRG3A
+ #define PMASK_BAND_D_PRG3A 0
+#endif
+#ifndef PMASK_BAND_D_PTG2B
+ #define PMASK_BAND_D_PTG2B 0
+#endif
+#ifndef PMASK_BAND_D_PTG3A
+ #define PMASK_BAND_D_PTG3A 0
+#endif
+
+#ifndef PMASK_BAND_E_PRG2B
+ #define PMASK_BAND_E_PRG2B 0
+#endif
+#ifndef PMASK_BAND_E_PRG3A
+ #define PMASK_BAND_E_PRG3A 0
+#endif
+#ifndef PMASK_BAND_E_PTG2B
+ #define PMASK_BAND_E_PTG2B 0
+#endif
+#ifndef PMASK_BAND_E_PTG3A
+ #define PMASK_BAND_E_PTG3A 0
+#endif
+
+
+//Add for RXD
+#ifndef PMASK2_BAND_A_PRG1
+ #define PMASK2_BAND_A_PRG1 0
+ #define PMASK2_BAND_A_PRG2 0
+ #define PMASK2_BAND_A_PRG3 0
+#endif
+#ifndef PMASK2_BAND_B_PRG1
+ #define PMASK2_BAND_B_PRG1 0
+ #define PMASK2_BAND_B_PRG2 0
+ #define PMASK2_BAND_B_PRG3 0
+#endif
+#ifndef PMASK2_BAND_C_PRG1
+ #define PMASK2_BAND_C_PRG1 0
+ #define PMASK2_BAND_C_PRG2 0
+ #define PMASK2_BAND_C_PRG3 0
+#endif
+#ifndef PMASK2_BAND_D_PRG1
+ #define PMASK2_BAND_D_PRG1 0
+ #define PMASK2_BAND_D_PRG2 0
+ #define PMASK2_BAND_D_PRG3 0
+#endif
+#ifndef PMASK2_BAND_E_PRG1
+ #define PMASK2_BAND_E_PRG1 0
+ #define PMASK2_BAND_E_PRG2 0
+ #define PMASK2_BAND_E_PRG3 0
+#endif
+
+#ifndef PMASK2_BAND_A_PRG2B
+ #define PMASK2_BAND_A_PRG2B 0
+#endif
+#ifndef PMASK2_BAND_A_PRG3A
+ #define PMASK2_BAND_A_PRG3A 0
+#endif
+#ifndef PMASK2_BAND_B_PRG2B
+ #define PMASK2_BAND_B_PRG2B 0
+#endif
+#ifndef PMASK2_BAND_B_PRG3A
+ #define PMASK2_BAND_B_PRG3A 0
+#endif
+#ifndef PMASK2_BAND_C_PRG2B
+ #define PMASK2_BAND_C_PRG2B 0
+#endif
+#ifndef PMASK2_BAND_C_PRG3A
+ #define PMASK2_BAND_C_PRG3A 0
+#endif
+#ifndef PMASK2_BAND_D_PRG2B
+ #define PMASK2_BAND_D_PRG2B 0
+#endif
+#ifndef PMASK2_BAND_D_PRG3A
+ #define PMASK2_BAND_D_PRG3A 0
+#endif
+#ifndef PMASK2_BAND_E_PRG2B
+ #define PMASK2_BAND_E_PRG2B 0
+#endif
+#ifndef PMASK2_BAND_E_PRG3A
+ #define PMASK2_BAND_E_PRG3A 0
+#endif
+
+
+/* --- BPI data default value --- */
+#ifndef PDATA_BAND_A_PRG1
+ #define PDATA_BAND_A_PRG1 0
+ #define PDATA_BAND_A_PRG2 0
+ #define PDATA_BAND_A_PRG3 0
+#endif
+#ifndef PDATA_BAND_A_PTG1
+ #define PDATA_BAND_A_PTG1 0
+ #define PDATA_BAND_A_PTG2 0
+ #define PDATA_BAND_A_PTG3 0
+#endif
+#ifndef PDATA_BAND_B_PRG1
+ #define PDATA_BAND_B_PRG1 0
+ #define PDATA_BAND_B_PRG2 0
+ #define PDATA_BAND_B_PRG3 0
+#endif
+#ifndef PDATA_BAND_B_PTG1
+ #define PDATA_BAND_B_PTG1 0
+ #define PDATA_BAND_B_PTG2 0
+ #define PDATA_BAND_B_PTG3 0
+#endif
+#ifndef PDATA_BAND_C_PRG1
+ #define PDATA_BAND_C_PRG1 0
+ #define PDATA_BAND_C_PRG2 0
+ #define PDATA_BAND_C_PRG3 0
+#endif
+#ifndef PDATA_BAND_C_PTG1
+ #define PDATA_BAND_C_PTG1 0
+ #define PDATA_BAND_C_PTG2 0
+ #define PDATA_BAND_C_PTG3 0
+#endif
+#ifndef PDATA_BAND_D_PRG1
+ #define PDATA_BAND_D_PRG1 0
+ #define PDATA_BAND_D_PRG2 0
+ #define PDATA_BAND_D_PRG3 0
+#endif
+#ifndef PDATA_BAND_D_PTG1
+ #define PDATA_BAND_D_PTG1 0
+ #define PDATA_BAND_D_PTG2 0
+ #define PDATA_BAND_D_PTG3 0
+#endif
+#ifndef PDATA_BAND_E_PRG1
+ #define PDATA_BAND_E_PRG1 0
+ #define PDATA_BAND_E_PRG2 0
+ #define PDATA_BAND_E_PRG3 0
+#endif
+#ifndef PDATA_BAND_E_PTG1
+ #define PDATA_BAND_E_PTG1 0
+ #define PDATA_BAND_E_PTG2 0
+ #define PDATA_BAND_E_PTG3 0
+#endif
+#ifndef PDATA_BAND_A_PRG2B
+ #define PDATA_BAND_A_PRG2B 0
+#endif
+#ifndef PDATA_BAND_A_PRG3A
+ #define PDATA_BAND_A_PRG3A 0
+#endif
+#ifndef PDATA_BAND_A_PTG2B
+ #define PDATA_BAND_A_PTG2B 0
+#endif
+#ifndef PDATA_BAND_A_PTG3A
+ #define PDATA_BAND_A_PTG3A 0
+#endif
+
+#ifndef PDATA_BAND_B_PRG2B
+ #define PDATA_BAND_B_PRG2B 0
+#endif
+#ifndef PDATA_BAND_B_PRG3A
+ #define PDATA_BAND_B_PRG3A 0
+#endif
+#ifndef PDATA_BAND_B_PTG2B
+ #define PDATA_BAND_B_PTG2B 0
+#endif
+#ifndef PDATA_BAND_B_PTG3A
+ #define PDATA_BAND_B_PTG3A 0
+#endif
+
+#ifndef PDATA_BAND_C_PRG2B
+ #define PDATA_BAND_C_PRG2B 0
+#endif
+#ifndef PDATA_BAND_C_PRG3A
+ #define PDATA_BAND_C_PRG3A 0
+#endif
+#ifndef PDATA_BAND_C_PTG2B
+ #define PDATA_BAND_C_PTG2B 0
+#endif
+#ifndef PDATA_BAND_C_PTG3A
+ #define PDATA_BAND_C_PTG3A 0
+#endif
+
+#ifndef PDATA_BAND_D_PRG2B
+ #define PDATA_BAND_D_PRG2B 0
+#endif
+#ifndef PDATA_BAND_D_PRG3A
+ #define PDATA_BAND_D_PRG3A 0
+#endif
+#ifndef PDATA_BAND_D_PTG2B
+ #define PDATA_BAND_D_PTG2B 0
+#endif
+#ifndef PDATA_BAND_D_PTG3A
+ #define PDATA_BAND_D_PTG3A 0
+#endif
+
+#ifndef PDATA_BAND_E_PRG2B
+ #define PDATA_BAND_E_PRG2B 0
+#endif
+#ifndef PDATA_BAND_E_PRG3A
+ #define PDATA_BAND_E_PRG3A 0
+#endif
+#ifndef PDATA_BAND_E_PTG2B
+ #define PDATA_BAND_E_PTG2B 0
+#endif
+#ifndef PDATA_BAND_E_PTG3A
+ #define PDATA_BAND_E_PTG3A 0
+#endif
+
+//Add for RXD
+#ifndef PDATA2_BAND_A_PRG1
+ #define PDATA2_BAND_A_PRG1 0
+ #define PDATA2_BAND_A_PRG2 0
+ #define PDATA2_BAND_A_PRG3 0
+#endif
+#ifndef PDATA2_BAND_B_PRG1
+ #define PDATA2_BAND_B_PRG1 0
+ #define PDATA2_BAND_B_PRG2 0
+ #define PDATA2_BAND_B_PRG3 0
+#endif
+#ifndef PDATA2_BAND_C_PRG1
+ #define PDATA2_BAND_C_PRG1 0
+ #define PDATA2_BAND_C_PRG2 0
+ #define PDATA2_BAND_C_PRG3 0
+#endif
+#ifndef PDATA2_BAND_D_PRG1
+ #define PDATA2_BAND_D_PRG1 0
+ #define PDATA2_BAND_D_PRG2 0
+ #define PDATA2_BAND_D_PRG3 0
+#endif
+#ifndef PDATA2_BAND_E_PRG1
+ #define PDATA2_BAND_E_PRG1 0
+ #define PDATA2_BAND_E_PRG2 0
+ #define PDATA2_BAND_E_PRG3 0
+#endif
+
+#ifndef PDATA2_BAND_A_PRG2B
+ #define PDATA2_BAND_A_PRG2B 0
+#endif
+#ifndef PDATA2_BAND_A_PRG3A
+ #define PDATA2_BAND_A_PRG3A 0
+#endif
+#ifndef PDATA2_BAND_B_PRG2B
+ #define PDATA2_BAND_B_PRG2B 0
+#endif
+#ifndef PDATA2_BAND_B_PRG3A
+ #define PDATA2_BAND_B_PRG3A 0
+#endif
+#ifndef PDATA2_BAND_C_PRG2B
+ #define PDATA2_BAND_C_PRG2B 0
+#endif
+#ifndef PDATA2_BAND_C_PRG3A
+ #define PDATA2_BAND_C_PRG3A 0
+#endif
+#ifndef PDATA2_BAND_D_PRG2B
+ #define PDATA2_BAND_D_PRG2B 0
+#endif
+#ifndef PDATA2_BAND_D_PRG3A
+ #define PDATA2_BAND_D_PRG3A 0
+#endif
+#ifndef PDATA2_BAND_E_PRG2B
+ #define PDATA2_BAND_E_PRG2B 0
+#endif
+#ifndef PDATA2_BAND_E_PRG3A
+ #define PDATA2_BAND_E_PRG3A 0
+#endif
+
+/* ELNA */
+#ifndef PMASK_BAND_A_PR3A_ELNA
+#define PMASK_BAND_A_PR3A_ELNA 0
+#endif
+#ifndef PMASK_BAND_B_PR3A_ELNA
+#define PMASK_BAND_B_PR3A_ELNA 0
+#endif
+#ifndef PMASK_BAND_C_PR3A_ELNA
+#define PMASK_BAND_C_PR3A_ELNA 0
+#endif
+#ifndef PMASK_BAND_D_PR3A_ELNA
+#define PMASK_BAND_D_PR3A_ELNA 0
+#endif
+#ifndef PMASK_BAND_E_PR3A_ELNA
+#define PMASK_BAND_E_PR3A_ELNA 0
+#endif
+
+#ifndef PDATA_BAND_A_PR3A_ELNA
+#define PDATA_BAND_A_PR3A_ELNA 0
+#endif
+#ifndef PDATA_BAND_B_PR3A_ELNA
+#define PDATA_BAND_B_PR3A_ELNA 0
+#endif
+#ifndef PDATA_BAND_C_PR3A_ELNA
+#define PDATA_BAND_C_PR3A_ELNA 0
+#endif
+#ifndef PDATA_BAND_D_PR3A_ELNA
+#define PDATA_BAND_D_PR3A_ELNA 0
+#endif
+#ifndef PDATA_BAND_E_PR3A_ELNA
+#define PDATA_BAND_E_PR3A_ELNA 0
+#endif
+
+#ifndef PMASK2_BAND_A_PR3A_ELNA
+#define PMASK2_BAND_A_PR3A_ELNA 0
+#endif
+#ifndef PMASK2_BAND_B_PR3A_ELNA
+#define PMASK2_BAND_B_PR3A_ELNA 0
+#endif
+#ifndef PMASK2_BAND_C_PR3A_ELNA
+#define PMASK2_BAND_C_PR3A_ELNA 0
+#endif
+#ifndef PMASK2_BAND_D_PR3A_ELNA
+#define PMASK2_BAND_D_PR3A_ELNA 0
+#endif
+#ifndef PMASK2_BAND_E_PR3A_ELNA
+#define PMASK2_BAND_E_PR3A_ELNA 0
+#endif
+
+#ifndef PDATA2_BAND_A_PR3A_ELNA
+#define PDATA2_BAND_A_PR3A_ELNA 0
+#endif
+#ifndef PDATA2_BAND_B_PR3A_ELNA
+#define PDATA2_BAND_B_PR3A_ELNA 0
+#endif
+#ifndef PDATA2_BAND_C_PR3A_ELNA
+#define PDATA2_BAND_C_PR3A_ELNA 0
+#endif
+#ifndef PDATA2_BAND_D_PR3A_ELNA
+#define PDATA2_BAND_D_PR3A_ELNA 0
+#endif
+#ifndef PDATA2_BAND_E_PR3A_ELNA
+#define PDATA2_BAND_E_PR3A_ELNA 0
+#endif
+
+
+/* TX Power Control defautl values */
+#ifndef PMASK_PRPC1
+ #define PMASK_PRPC1 0
+ #define PMASK_PRPC2 0
+ #define PMASK_PRPC3 0
+#endif
+#ifndef PMASK_PTPC1
+ #define PMASK_PTPC1 0
+ #define PMASK_PTPC2 0
+#endif
+#ifndef PMASK_PTPC3
+ #define PMASK_PTPC3 0
+#endif
+#ifndef PMASK_PRPC2B
+ #define PMASK_PRPC2B 0
+#endif
+#ifndef PMASK_PRPC3A
+ #define PMASK_PRPC3A 0
+#endif
+#ifndef PMASK_PTPC2B
+ #define PMASK_PTPC2B 0
+#endif
+#ifndef PMASK_PTPC3A
+ #define PMASK_PTPC3A 0
+#endif
+
+//Add for RXD
+#ifndef PMASK2_PRPC1
+ #define PMASK2_PRPC1 0
+ #define PMASK2_PRPC2 0
+ #define PMASK2_PRPC3 0
+#endif
+#ifndef PMASK2_PRPC2B
+ #define PMASK2_PRPC2B 0
+#endif
+#ifndef PMASK2_PRPC3A
+ #define PMASK2_PRPC3A 0
+#endif
+
+/* --- BPI data default value --- */
+#ifndef PDATA_PRPC1
+ #define PDATA_PRPC1 0
+ #define PDATA_PRPC2 0
+ #define PDATA_PRPC3 0
+#endif
+#ifndef PDATA_PTPC1
+ #define PDATA_PTPC1 0
+ #define PDATA_PTPC2 0
+#endif
+#ifndef PDATA_PTPC3
+#define PDATA_PTPC3 0
+#endif
+#ifndef PDATA_PRPC2B
+ #define PDATA_PRPC2B 0
+#endif
+#ifndef PDATA_PRPC3A
+ #define PDATA_PRPC3A 0
+#endif
+#ifndef PDATA_PTPC2B
+ #define PDATA_PTPC2B 0
+#endif
+#ifndef PDATA_PTPC3A
+ #define PDATA_PTPC3A 0
+#endif
+
+//Add for RXD
+#ifndef PDATA2_PRPC1
+ #define PDATA2_PRPC1 0
+ #define PDATA2_PRPC2 0
+ #define PDATA2_PRPC3 0
+#endif
+#ifndef PDATA2_PRPC2B
+ #define PDATA2_PRPC2B 0
+#endif
+#ifndef PDATA2_PRPC3A
+ #define PDATA2_PRPC3A 0
+#endif
+
+
+/* BPI timing */
+#ifndef TC_PR1
+ #define TC_PR1 0
+ #define TC_PR2 0
+ #define TC_PR3 0
+#endif
+#ifndef TC_RXD_PR1
+ #define TC_RXD_PR1 0
+ #define TC_RXD_PR2 0
+ #define TC_RXD_PR3 0
+#endif
+#ifndef TC_PT1
+ #define TC_PT1 0
+ #define TC_PT2 0
+ #define TC_PT3 0
+#endif
+#ifndef TC_PRG1
+ #define TC_PRG1 0
+ #define TC_PRG2 0
+ #define TC_PRG3 0
+#endif
+#ifndef TC_RXD_PRG1
+ #define TC_RXD_PRG1 0
+ #define TC_RXD_PRG2 0
+ #define TC_RXD_PRG3 0
+#endif
+#ifndef TC_PTG1
+ #define TC_PTG1 0
+ #define TC_PTG2 0
+ #define TC_PTG3 0
+#endif
+#ifndef TC_PRPC1
+ #define TC_PRPC1 0
+ #define TC_PRPC2 0
+ #define TC_PRPC3 0
+#endif
+#ifndef TC_RXD_PRPC1
+ #define TC_RXD_PRPC1 0
+ #define TC_RXD_PRPC2 0
+ #define TC_RXD_PRPC3 0
+#endif
+#ifndef TC_PTPC1
+ #define TC_PTPC1 0
+ #define TC_PTPC2 0
+#endif
+#ifndef TC_PTPC3
+ #define TC_PTPC3 0
+#endif
+
+#ifndef TC_PR2B
+ #define TC_PR2B 0
+#endif
+#ifndef TC_PR3A
+ #define TC_PR3A 0
+#endif
+#ifndef TC_RXD_PR2B
+ #define TC_RXD_PR2B 0
+#endif
+#ifndef TC_RXD_PR3A
+ #define TC_RXD_PR3A 0
+#endif
+#ifndef TC_PT2B
+ #define TC_PT2B 0
+#endif
+#ifndef TC_PT3A
+ #define TC_PT3A 0
+#endif
+
+#ifndef TC_PRG2B
+ #define TC_PRG2B 0
+#endif
+#ifndef TC_PRG3A
+ #define TC_PRG3A 0
+#endif
+#ifndef TC_RXD_PRG2B
+ #define TC_RXD_PRG2B 0
+#endif
+#ifndef TC_RXD_PRG3A
+ #define TC_RXD_PRG3A 0
+#endif
+#ifndef TC_PTG2B
+ #define TC_PT2B 0
+#endif
+#ifndef TC_PTG3A
+ #define TC_PTG3A 0
+#endif
+#ifndef TC_PR3A_ELNA
+ #define TC_PR3A_ELNA 0
+#endif
+
+#ifndef BAND_A_RX_IO_SEL
+ #define BAND_A_RX_IO_SEL NONE_USED_PRX
+#endif
+#ifndef BAND_B_RX_IO_SEL
+ #define BAND_B_RX_IO_SEL NONE_USED_PRX
+#endif
+#ifndef BAND_C_RX_IO_SEL
+ #define BAND_C_RX_IO_SEL NONE_USED_PRX
+#endif
+#ifndef BAND_D_RX_IO_SEL
+ #define BAND_D_RX_IO_SEL NONE_USED_PRX
+#endif
+#ifndef BAND_E_RX_IO_SEL
+ #define BAND_E_RX_IO_SEL NONE_USED_PRX
+#endif
+
+#ifndef BAND_A_RXD_IO_SEL
+ #define BAND_A_RXD_IO_SEL NONE_USED_DRX
+#endif
+#ifndef BAND_B_RXD_IO_SEL
+ #define BAND_B_RXD_IO_SEL NONE_USED_DRX
+#endif
+#ifndef BAND_C_RXD_IO_SEL
+ #define BAND_C_RXD_IO_SEL NONE_USED_DRX
+#endif
+#ifndef BAND_D_RXD_IO_SEL
+ #define BAND_D_RXD_IO_SEL NONE_USED_DRX
+#endif
+#ifndef BAND_E_RXD_IO_SEL
+ #define BAND_E_RXD_IO_SEL NONE_USED_DRX
+#endif
+
+#ifndef BAND_A_TX_IO_SEL
+ #define BAND_A_TX_IO_SEL TX_IO_NULL
+#endif
+#ifndef BAND_B_TX_IO_SEL
+ #define BAND_B_TX_IO_SEL TX_IO_NULL
+#endif
+#ifndef BAND_C_TX_IO_SEL
+ #define BAND_C_TX_IO_SEL TX_IO_NULL
+#endif
+#ifndef BAND_D_TX_IO_SEL
+ #define BAND_D_TX_IO_SEL TX_IO_NULL
+#endif
+#ifndef BAND_E_TX_IO_SEL
+ #define BAND_E_TX_IO_SEL TX_IO_NULL
+#endif
+
+#ifndef PDATA_BAND_A_TAS1
+ #define PDATA_BAND_A_TAS1 0
+ #define PDATA_BAND_A_TAS2 0
+ #define PDATA_BAND_A_TAS3 0
+ #define PDATA_BAND_A_TAS4 0
+ #define PDATA_BAND_A_TAS5 0
+ #define PDATA_BAND_A_TAS6 0
+ #define PDATA_BAND_A_TAS7 0
+#endif
+
+#ifndef PDATA_BAND_B_TAS1
+ #define PDATA_BAND_B_TAS1 0
+ #define PDATA_BAND_B_TAS2 0
+ #define PDATA_BAND_B_TAS3 0
+ #define PDATA_BAND_B_TAS4 0
+ #define PDATA_BAND_B_TAS5 0
+ #define PDATA_BAND_B_TAS6 0
+ #define PDATA_BAND_B_TAS7 0
+#endif
+
+#ifndef PDATA_BAND_C_TAS1
+ #define PDATA_BAND_C_TAS1 0
+ #define PDATA_BAND_C_TAS2 0
+ #define PDATA_BAND_C_TAS3 0
+ #define PDATA_BAND_C_TAS4 0
+ #define PDATA_BAND_C_TAS5 0
+ #define PDATA_BAND_C_TAS6 0
+ #define PDATA_BAND_C_TAS7 0
+#endif
+
+#ifndef PDATA_BAND_D_TAS1
+ #define PDATA_BAND_D_TAS1 0
+ #define PDATA_BAND_D_TAS2 0
+ #define PDATA_BAND_D_TAS3 0
+ #define PDATA_BAND_D_TAS4 0
+ #define PDATA_BAND_D_TAS5 0
+ #define PDATA_BAND_D_TAS6 0
+ #define PDATA_BAND_D_TAS7 0
+#endif
+
+#ifndef PDATA_BAND_E_TAS1
+ #define PDATA_BAND_E_TAS1 0
+ #define PDATA_BAND_E_TAS2 0
+ #define PDATA_BAND_E_TAS3 0
+ #define PDATA_BAND_E_TAS4 0
+ #define PDATA_BAND_E_TAS5 0
+ #define PDATA_BAND_E_TAS6 0
+ #define PDATA_BAND_E_TAS7 0
+#endif
+
+/* Enables */
+#ifndef RX_DIVERSITY_ENABLE
+ #define RX_DIVERSITY_ENABLE KAL_FALSE
+#endif
+
+#ifndef RX_DIVERSITY_ONLY_TEST
+ #define RX_DIVERSITY_ONLY_TEST KAL_FALSE
+#endif
+
+#ifndef PA_VDD_DC2DC_ENABLE
+ #define PA_VDD_DC2DC_ENABLE KAL_FALSE
+#endif
+
+#ifndef PA_VDD_PMU_ENABLE
+ #define PA_VDD_PMU_ENABLE KAL_FALSE
+#endif
+
+#ifndef PA_VDD_BATT_ENABLE
+ #define PA_VDD_BATT_ENABLE KAL_FALSE
+#endif
+
+#ifndef TEMPERATURE_MEAS_EN
+ #define TEMPERATURE_MEAS_EN KAL_FALSE
+#endif
+
+
+
+#endif /* _CL1_RF_COMMON_H_ */
+
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_dummy.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_dummy.h
new file mode 100644
index 0000000..9160027
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_dummy.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1D_DUMMY_H_
+#define _CL1D_DUMMY_H_
+
+
+
+#endif /* _CL1_DRDI_H_ */
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_mmrf_share_data.c b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_mmrf_share_data.c
new file mode 100644
index 0000000..306c4ec
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_mmrf_share_data.c
@@ -0,0 +1,74 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#include "kal_general_types.h"
+#include "cl1d_rf_common_defs.h"
+#include "cl1_rf_public.h"
+#include "mmrf_kal.h"
+
+#undef NVRAM_ITEM_RF_CUST
+#undef NVRAM_ITEM_MIPI
+#undef NVRAM_ITEM_RF_CAL
+#undef NVRAM_ITEM_RF_POC
+#undef NVRAM_ITEM_RF_TAS_VAR
+#undef NVRAM_ITEM_RF_TAS_ARRAY
+#undef NVRAM_ITEM_ELNA_VAR
+#undef NVRAM_ITEM_TX_POWER_VAR
+#undef NVRAM_ITEM_RF_TAS_TST
+#define NVRAM_ITEM_RF_CUST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_MIPI(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_RF_CAL(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_RF_POC(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*** TAS ***/
+#define NVRAM_ITEM_RF_TAS_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#define NVRAM_ITEM_RF_TAS_ARRAY(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*ELNA*/
+#define NVRAM_ITEM_ELNA_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*TX POWER*/
+#define NVRAM_ITEM_TX_POWER_VAR(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+/*TAS TST */
+#define NVRAM_ITEM_RF_TAS_TST(nAME, aFFIX, rECnUM, tYPE, tYPEnUM, fUNC) \
+ MMRF_CUSTOM_DEFINE_SHARED_ARRAY(CL1D_RF_##tYPE, CL1D_RF_##nAME##_##aFFIX##_SHM, (tYPEnUM))
+#include "cl1_nvram_id.h"
+
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_error_check.c b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_error_check.c
new file mode 100644
index 0000000..a8da92d
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_error_check.c
@@ -0,0 +1,1248 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_error_check.c
+ *
+ * Project:
+ * --------
+ * MT6177l
+ *
+ * Description:
+ * ------------
+ * Error check assert function
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *----------------------------------------------------------------------------
+ *
+ *
+ *
+ *
+ *
+ *----------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file cl1d_rf_error_check.c
+ * @author Make.Wu (MTK11049)
+ * @date 2016.09.6
+ * @brief Error check function
+ * @details
+ ******************************************************************************/
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "cl1d_rf_error_check.h"
+//#include "mml1_rf_interface.h"
+
+/*******************************************************************************
+ * Global Functions declaration (interface)
+ ******************************************************************************/
+//[NOTE] Please add the new check from the end of this file!!!
+// => In order to keep the assert line number unchanged
+/*===============================================================================*/
+void CL1D_ErrorCheck_Dev_config_rf_scenario(kal_uint16 rf_scen)
+{
+ kal_bool Rf_Scenario = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Rf_Scenario,rf_scen, 0, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Rf_Scenario);
+ MODEM_WARNING_MESSAGE(Rf_Scenario, "Dev_config_rf_scenario");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_afc_config(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Path,path, 0, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Path);
+ MODEM_WARNING_MESSAGE(Path, "Dev_afc_config");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_get_bsi_save(kal_uint16 dev_path, kal_uint16 is_valid)
+{
+ kal_bool get_bsi = KAL_FALSE;
+ EXT_ASSERT(get_bsi,dev_path,is_valid,0);
+}
+
+void CL1D_ErrorCheck_Dev_set_bsi_save(kal_uint16 dev_path, void* bsi_get)
+{
+ kal_bool get_bsi = KAL_FALSE;
+ EXT_ASSERT(get_bsi,dev_path,(kal_uint32)bsi_get,0);
+}
+
+void CL1D_ErrorCheck_Dev_get_bsi_port(kal_uint16 rf)
+{
+ kal_bool Rf = KAL_FALSE;
+ EXT_ASSERT(Rf,rf,0,0);
+}
+
+void CL1D_ErrorCheck_Dev_rf_cust_get_prx_rf(kal_uint16 rf_band,void* bsi_get)
+{
+ kal_bool prx_rf = KAL_FALSE;
+ EXT_ASSERT(prx_rf,rf_band,(kal_uint32)bsi_get,0);
+}
+
+void CL1D_ErrorCheck_Dev_rf_cust_get_drx_rf(kal_uint16 rf_band,void* bsi_get)
+{
+ kal_bool drx_rf = KAL_FALSE;
+ EXT_ASSERT(drx_rf,rf_band,(kal_uint32)bsi_get,0);
+}
+
+void CL1D_ErrorCheck_Dev_rf_get_tx_rf_bsi_idx(kal_uint16 CL1D_RF_DEV_PllBand,void* bsi_get)
+{
+ kal_bool bsi_idx = KAL_FALSE;
+ EXT_ASSERT(bsi_idx,CL1D_RF_DEV_PllBand,(kal_uint32)bsi_get,0);
+}
+
+void CL1D_ErrorCheck_Dev_set_dev_ctrl(kal_uint16 path,void* bsi_get)
+{
+ kal_bool dev_ctrl = KAL_FALSE;
+ EXT_ASSERT(dev_ctrl,path,(kal_uint32)bsi_get,0);
+}
+
+void CL1D_ErrorCheck_Dev_c2k_bsi_switch_to_mml1_bsi(kal_uint16 bsi)
+{
+ kal_bool bsi_switch = KAL_FALSE;
+ EXT_ASSERT(bsi_switch,bsi,0,0);
+}
+
+void CL1D_ErrorCheck_Dev_get_rx1_warmup_code_word(kal_uint16 band_class, kal_uint16 band)
+{
+ kal_bool Path = KAL_FALSE;
+ EXT_ASSERT(Path, band_class, band,0);
+}
+
+void CL1D_ErrorCheck_Dev_get_rx2_warmup_code_word(kal_uint16 band_class, kal_uint16 band)
+{
+ kal_bool Path = KAL_FALSE;
+ EXT_ASSERT(Path, band_class, band,0);
+}
+
+void CL1D_ErrorCheck_Dev_get_prx_port(kal_uint16 prxPort)
+{
+ kal_bool RxPort = KAL_FALSE;
+ EXT_ASSERT(RxPort, prxPort, 0, 0);
+}
+
+void CL1D_ErrorCheck_Dev_get_drx_port(kal_uint16 drxPort)
+{
+ kal_bool RxPort = KAL_FALSE;
+ EXT_ASSERT(RxPort, drxPort, 0, 0);
+}
+#if defined(__MD93__)||defined(__MD95__)
+void CL1D_ErrorCheck_Dev_build_rx_warmup_script(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+ EXT_ASSERT(Path, path,0,0);
+}
+
+void CL1D_ErrorCheck_Dev_build_rx_burst_script(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+ EXT_ASSERT(Path, path,0,0);
+}
+#endif
+void CL1D_ErrorCheck_Dev_build_rx_patial_on_script(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Path,path, 0,0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Path);
+ MODEM_WARNING_MESSAGE(Path, "Dev_build_rx_patial_on_script");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_build_rx_patial_off_script(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Path,path, 0,0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Path);
+ MODEM_WARNING_MESSAGE(Path, "Dev_build_rx_patial_off_script");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_build_rx_sleep_script(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+ EXT_ASSERT(Path,path, 0,0);
+}
+
+void CL1D_ErrorCheck_Dev_rx_on_rx_path(kal_uint16 path)
+{
+ kal_bool Path = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Path,path, 0,0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Path);
+ MODEM_WARNING_MESSAGE(Path, "Dev_rx_on_rx_path");
+#endif
+
+}
+
+void CL1D_ErrorCheck_Dev_rx_on_path_band(kal_uint16 rx_path,kal_uint16 band_class,kal_uint16 rf_band)
+{
+ kal_bool Path = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Path,rx_path, band_class, rf_band);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Path);
+ MODEM_WARNING_MESSAGE(Path, "Dev_rx_on_path_band");
+#endif
+
+
+
+}
+
+void CL1D_ErrorCheck_Dev_rx_on_mode_rf_config(kal_uint16 mode)
+{
+ kal_bool Mode = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Mode,mode, 0, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Mode);
+ MODEM_WARNING_MESSAGE(Mode, "Dev_rx_on_mode_rf_config");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_rx_off_path_mode(kal_uint16 rx_path, kal_uint16 mode)
+{
+ kal_bool Path = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Path,rx_path, mode, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Path);
+ MODEM_WARNING_MESSAGE(Path, "Dev_rx_off_path_mode");
+#endif
+
+}
+
+void CL1D_ErrorCheck_Dev_tx_on_band_mode(kal_uint16 cdma_band, kal_uint16 band,kal_uint16 rat_type)
+{
+ kal_bool Band = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Band,cdma_band, band, rat_type);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Band);
+ MODEM_WARNING_MESSAGE(Band, "Dev_tx_on_band_mode");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_get_tx_warmup_code_word(kal_uint16 band_class, kal_uint16 band)
+{
+ kal_bool Path = KAL_FALSE;
+ EXT_ASSERT(Path, band_class, band,0);
+}
+
+void CL1D_ErrorCheck_Dev_get_tx_port(kal_uint16 txPort)
+{
+ kal_bool TxPort = KAL_FALSE;
+ EXT_ASSERT(TxPort, txPort, 0,0);
+}
+
+void CL1D_ErrorCheck_Dev_gate_on(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Rat,rat_type, 0, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Rat);
+ MODEM_WARNING_MESSAGE(Rat, "Dev_gate_on");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_tx_off(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Rat,rat_type, 0, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Rat);
+ MODEM_WARNING_MESSAGE(Rat, "Dev_tx_off");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_gate_off(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Rat,rat_type, 0, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Rat);
+ MODEM_WARNING_MESSAGE(Rat, "Dev_gate_off");
+#endif
+}
+
+void CL1D_ErrorCheck_Dev_get_rx_dc_tbl(kal_uint8 rx_path,kal_uint8 rf_band)
+{
+ kal_bool Dc = KAL_FALSE;
+#if defined(__MD93__)||defined(__MD95__)
+ EXT_ASSERT(Dc,rx_path, rf_band, 0);
+#elif defined(__MD97__) || defined(__MD97P__)
+ DEBUG_ASSERT(Dc);
+ MODEM_WARNING_MESSAGE(Dc, "Dev_get_rx_dc_tbl");
+#endif
+}
+
+#if defined(__MD93__) || defined(__MD95__)
+void CL1D_ErrorCheck_Dev_pll_srx(kal_uint16 band_class)
+{
+ kal_bool Pll = KAL_FALSE;
+ EXT_ASSERT(Pll,band_class, 0, 0);
+}
+
+void CL1D_ErrorCheck_Dev_pll_stx(kal_uint16 band_class)
+{
+ kal_bool Pll = KAL_FALSE;
+ EXT_ASSERT(Pll,band_class, 0, 0);
+}
+#endif
+#if defined(__PMIC_VS1_LOW_POWER_CTRL_SUPPORT__)
+void CL1D_ErrorCheck_Dev_vs1(kal_uint16 path_type, kal_uint16 path_on)
+{
+ kal_bool Vs1 = KAL_FALSE;
+ EXT_ASSERT(Vs1,path_type, path_type, 0);
+}
+#endif
+
+void CL1D_ErrorCheck_RxDfe_path_rat(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+ EXT_ASSERT(Rat,rat_type ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_path_scen(kal_uint16 scen)
+{
+ kal_bool Scen = KAL_FALSE;
+ EXT_ASSERT(Scen,scen ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_fc_rat(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+ EXT_ASSERT(Rat,rat_type ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_fc_write_rat(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+ EXT_ASSERT(Rat,rat_type ,0 ,0);
+}
+
+
+void CL1D_ErrorCheck_RxDfe_tq_type(kal_uint16 tq_type)
+{
+ kal_bool Tq = KAL_FALSE;
+ EXT_ASSERT(Tq,tq_type ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_fc_type(kal_uint16 fc_type)
+{
+ kal_bool Fc = KAL_FALSE;
+ EXT_ASSERT(Fc,fc_type ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_fc_tq_type(kal_uint16 tq_type)
+{
+ kal_bool Tq = KAL_FALSE;
+ EXT_ASSERT(Tq,tq_type ,0 ,0);
+}
+
+
+void CL1D_ErrorCheck_TxDfe_path_scen(kal_uint16 scen)
+{
+ kal_bool Scen = KAL_FALSE;
+ EXT_ASSERT(Scen,scen ,0 ,0);
+}
+
+void CL1D_ErrorCheck_TxDfe_evt_scen(kal_uint16 scen)
+{
+ kal_bool Scen = KAL_FALSE;
+ EXT_ASSERT(Scen,scen ,0 ,0);
+}
+
+void CL1D_ErrorCheck_TxDfe_evt_rat(kal_uint16 rat_type)
+{
+ kal_bool Rat = KAL_FALSE;
+ EXT_ASSERT(Rat,rat_type ,0 ,0);
+}
+
+void CL1D_ErrorCheck_TxDfe_ttg_scen(kal_uint16 scen)
+{
+ kal_bool Scen = KAL_FALSE;
+ EXT_ASSERT(Scen,scen ,0 ,0);
+}
+
+void CL1D_ErrorCheck_TxDfe_ttg_rat(kal_uint16 rat)
+{
+ kal_bool Rat = KAL_FALSE;
+ EXT_ASSERT(Rat,rat ,0 ,0);
+
+}
+
+
+void CL1D_ErrorCheck_TxDfe_ttg_phi(kal_uint16 phi)
+{
+ kal_bool Phi = KAL_FALSE;
+ EXT_ASSERT(Phi,phi ,0 ,0);
+
+}
+
+void CL1D_ErrorCheck_CUST_param_illegal_sysBandClass(kal_uint8 bandClass){
+ kal_bool BandClass=KAL_FALSE;
+ EXT_ASSERT(BandClass,bandClass,0,0);
+}
+
+#if defined(__MD93__) || defined(__MD95__)
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_rx(kal_uint16 rxDataEnd){
+ kal_bool RxDataEnd=KAL_FALSE;
+ EXT_ASSERT(RxDataEnd,rxDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_event_type_rx(kal_uint16 rxEventType){
+ kal_bool RxEventType=KAL_FALSE;
+ EXT_ASSERT(RxEventType,rxEventType,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_tx(kal_uint16 txDataEnd){
+ kal_bool TxDataEnd=KAL_FALSE;
+ EXT_ASSERT(TxDataEnd,txDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_event_type_tx(kal_uint16 txEventType){
+ kal_bool TxEventType=KAL_FALSE;
+ EXT_ASSERT(TxEventType,txEventType,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index(kal_uint8 txRxBufferIndex){
+ kal_bool TxRxBufferIndex=KAL_FALSE;
+ EXT_ASSERT(TxRxBufferIndex,txRxBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq(kal_uint16 mipiDataSeq){
+ kal_bool MipiDataSeq=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeq,mipiDataSeq,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_tpc1xrtt(kal_uint16 tpcDataEnd){
+ kal_bool TpcDataEnd=KAL_FALSE;
+ EXT_ASSERT(TpcDataEnd,tpcDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_tpc1xrtt(kal_uint8 tpcBufferIndex){
+ kal_bool TpcBufferIndex=KAL_FALSE;
+ EXT_ASSERT(TpcBufferIndex,tpcBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_tpc1xrtt(kal_uint16 mipiDataSeqTpc){
+ kal_bool MipiDataSeqTpc=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeqTpc,mipiDataSeqTpc,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_tpcEvdo(kal_uint16 tpcDataEnd){
+ kal_bool TpcDataEnd=KAL_FALSE;
+ EXT_ASSERT(TpcDataEnd,tpcDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_tpcEvdo(kal_uint8 tpcBufferIndex){
+ kal_bool TpcBufferIndex=KAL_FALSE;
+ EXT_ASSERT(TpcBufferIndex,tpcBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_tpcEvdo(kal_uint16 mipiDataSeqTpc){
+ kal_bool MipiDataSeqTpc=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeqTpc,mipiDataSeqTpc,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_etm(kal_uint16 etmDataEnd){
+ kal_bool EtmDataEnd=KAL_FALSE;
+ EXT_ASSERT(EtmDataEnd,etmDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etmTxOn(kal_uint8 etmBufferIndex){
+ kal_bool EtmBufferIndex=KAL_FALSE;
+ EXT_ASSERT(EtmBufferIndex,etmBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etmTxOn(kal_uint16 mipiDataSeq){
+ kal_bool MipiDataSeq=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeq,mipiDataSeq,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etmTxOff(kal_uint8 etmBufferIndex){
+ kal_bool EtmBufferIndex=KAL_FALSE;
+ EXT_ASSERT(EtmBufferIndex,etmBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etmTxOff(kal_uint16 mipiDataSeq){
+ kal_bool MipiDataSeq=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeq,mipiDataSeq,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_event_type_etm(kal_uint16 etmEventType){
+ kal_bool EtmEventType=KAL_FALSE;
+ EXT_ASSERT(EtmEventType,etmEventType,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_etm_tpc1xrtt(kal_uint16 tpcDataEnd){
+ kal_bool TpcDataEnd=KAL_FALSE;
+ EXT_ASSERT(TpcDataEnd,tpcDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etm_tpc1xrtt(kal_uint8 etmBufferIndex){
+ kal_bool EtmBufferIndex=KAL_FALSE;
+ EXT_ASSERT(EtmBufferIndex,etmBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etm_tpc1xrtt(kal_uint16 mipiDataSeq){
+ kal_bool MipiDataSeq=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeq,mipiDataSeq,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_etm_tpcEvdo(kal_uint16 tpcDataEnd){
+ kal_bool TpcDataEnd=KAL_FALSE;
+ EXT_ASSERT(TpcDataEnd,tpcDataEnd,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etm_tpcEvdo(kal_uint8 etmBufferIndex){
+ kal_bool EtmBufferIndex=KAL_FALSE;
+ EXT_ASSERT(EtmBufferIndex,etmBufferIndex,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etm_tpcEvdo(kal_uint16 mipiDataSeq){
+ kal_bool MipiDataSeq=KAL_FALSE;
+ EXT_ASSERT(MipiDataSeq,mipiDataSeq,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_num(kal_bool is_start,kal_uint16 mipiDataNum){
+ kal_bool MipiDataNum=KAL_FALSE;
+ EXT_ASSERT(MipiDataNum,is_start,mipiDataNum,0);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_check(void *infoPtr,kal_uint8 band, kal_uint8 act){
+ kal_bool MipiDataCheck=KAL_FALSE;
+ EXT_ASSERT(MipiDataCheck,(kal_uint32)infoPtr,band,act);
+}
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_get_subband_check(kal_uint32 subband_freq, kal_uint32 freq){
+ kal_bool MipiSubbandCheck=KAL_FALSE;
+ EXT_ASSERT(MipiSubbandCheck,subband_freq,freq,0);
+}
+
+void CL1D_ErrorCheck_Dev_tx_poc_band(kal_uint32 band_class){
+ kal_bool TxPocBand=KAL_FALSE;
+ EXT_ASSERT(TxPocBand,band_class,0,0);
+}
+#endif
+
+void CL1D_ErrorCheck_CUST_cal_illegal_rat(kal_uint8 rat){
+ kal_bool Rat=KAL_FALSE;
+ EXT_ASSERT(Rat,rat,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_cal_illegal_chanNum(kal_uint16 chanNum){
+ kal_bool ChanNum=KAL_FALSE;
+ EXT_ASSERT(ChanNum,chanNum,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_cal_illegal_devSenario(kal_uint8 devSenario){
+ kal_bool DevSenario=KAL_FALSE;
+ EXT_ASSERT(DevSenario,devSenario,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_cal_runtime_illegal_devSenario(kal_uint8 devSenario){
+ kal_bool DevSenario=KAL_FALSE;
+ EXT_ASSERT(DevSenario,devSenario,0,0);
+}
+void CL1D_ErrorCheck_CUST_elna_illegal_desSubband(kal_uint8 dstSubband){
+ kal_bool DstSubband=KAL_FALSE;
+ EXT_ASSERT(DstSubband,dstSubband,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_elna_illegal_elnaSwitch(kal_uint8 elnaSel){
+ kal_bool ElnaSel=KAL_FALSE;
+ EXT_ASSERT(ElnaSel,elnaSel,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_elna_illegal_category(kal_uint8 elnaCategory){
+ kal_bool ElnaCategory=KAL_FALSE;
+ EXT_ASSERT(ElnaCategory,elnaCategory,0,0);
+}
+void CL1D_ErrorCheck_TEMP_meas(kal_uint8 rat,kal_uint8 tmp_mode){
+ kal_bool TEMP_meas=KAL_FALSE;
+ EXT_ASSERT(TEMP_meas,rat,tmp_mode,0);
+}
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Hal_Rat_Type()
+
+ DESCRIPTION: This fucntion is used to check rat type.
+
+ PARAMETERS: rat type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Hal_Rat_Type(kal_uint8 rat)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,rat,0,0);
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Hal_Rx()
+
+ DESCRIPTION: This fucntion is used to check HAL rx path control conflict.
+
+ PARAMETERS: void
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Hal_Rx_Conflict(CL1D_RF_HAL_RX_ERROR_E error_type,kal_uint8 cur_bmp, kal_uint8 req_bmp)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,error_type,cur_bmp,req_bmp);
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Hal_Afc_Band_Class()
+
+ DESCRIPTION: This fucntion is used to check bandclass supported status.
+
+ PARAMETERS: 3GPP2 band class
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Hal_Afc_Band_Class(kal_uint32 band_class)
+{
+ kal_bool bc = KAL_FALSE;
+#if defined(__MD93__) || defined(__MD95__)
+ EXT_ASSERT(bc,band_class,0,0);
+#else
+ DEBUG_ASSERT(bc);
+ MODEM_WARNING_MESSAGE(bc, "Invalid: Band_Class");
+#endif
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Hal_Afc_Channel()
+
+ DESCRIPTION: This fucntion is used to check channel of the bandclass supported status.
+
+ PARAMETERS: 3GPP2 band class and channel
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Hal_Afc_Channel(kal_uint32 band_class, kal_uint32 channel)
+{
+ kal_bool ch = KAL_FALSE;
+#if defined(__MD93__) || defined(__MD95__)
+ EXT_ASSERT(ch,band_class,channel,0);
+#else
+ DEBUG_ASSERT(ch);
+ MODEM_WARNING_MESSAGE(ch, "Invalid: Channel_Number");
+#endif
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Cuif_Tpc()
+
+ DESCRIPTION: This fucntion is used to check TPC cuif transfer error.
+
+ PARAMETERS: error type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Cuif_Tpc(CL1D_RF_CUIF_TPC_CFG_ERROR_E error_type)
+{
+#ifndef L1_SIM
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,error_type,0,0);
+#endif
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Cuif_Agc()
+
+ DESCRIPTION: This fucntion is used to check AGC cuif transfer error.
+
+ PARAMETERS: error type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Cuif_Agc(CL1D_RF_CUIF_AGC_ERROR_E error_type, kal_uint32 param0, kal_uint32 param1)
+{
+#ifndef L1_SIM
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,error_type,param0,param1);
+#endif
+}
+
+void CL1D_ErrorCheck_Rf_Confict(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2)
+{
+#ifndef L1_SIM
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,param0,param1,param2);
+#endif
+}
+
+void CL1D_ErrorCheck_Rf_PaVddSel_CustomFileSetting(kal_uint8 rf_band){
+ kal_bool Pa_Vdd_Ctrl=KAL_FALSE;
+ EXT_ASSERT(Pa_Vdd_Ctrl,rf_band,0,0);
+}
+#if defined(__MD93__)||defined(__MD95__)
+void CL1D_ErrorCheck_Rf_Hpue_Interface_Info(kal_uint8 param){
+ kal_bool hpue_ret_info=KAL_FALSE;
+ EXT_ASSERT(hpue_ret_info,param,0,0);
+}
+#endif
+/***********************************************
+ FUNCTION NAME: C2K_FEC_MMRF_Error_Check()
+
+ DESCRIPTION: This fucntion is used to check C2K abnormal CW error. It will be called by MMRF.
+
+ PARAMETERS: error type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void C2K_FEC_MMRF_Error_Check(kal_uint32 op_code, kal_uint32 bin_mode)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,op_code,bin_mode,0);
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_CUST_param_dpd_illegal_bandsupport()
+
+ DESCRIPTION: This fucntion is used to check C2K abnormal band class when parsing DPD enable flag.
+
+ PARAMETERS: error type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_CUST_param_dpd_illegal_bandsupport(kal_uint8 band)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,band,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_elna_illegal_gain_type(kal_uint8 elnaGain){
+ kal_bool ElnaGainType = KAL_FALSE;
+ EXT_ASSERT(ElnaGainType,elnaGain,0,0);
+}
+
+#if defined(__MD93__) || defined(__MD95__)
+void CL1D_ErrorCheck_CUST_tas_illegal_ant_index(kal_uint8 ant_index, kal_uint8 rf_band)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, ant_index, rf_band, 0);
+}
+
+void CL1D_ErrorCheck_CUST_tas_illegal_c2k_band(kal_uint8 c2k_band)
+{
+ kal_bool C2k_Band=KAL_FALSE;
+ EXT_ASSERT(C2k_Band,c2k_band,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_tas_illegal_rf_band(kal_uint8 rf_band)
+{
+ kal_bool Rf_Band=KAL_FALSE;
+ EXT_ASSERT(Rf_Band,rf_band,0,0);
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_hw_group_index(kal_uint8 rf_band, kal_uint8 hw_group_index)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, hw_group_index, rf_band, 0);
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_state_index(kal_uint8 rf_band, kal_uint8 tas_state)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, tas_state, rf_band, 0);
+}
+#else
+void CL1D_ErrorCheck_CUST_utas_illegal_nv_status(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: R/W_NVRAM_Fail");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_ant_port_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_ANT_PORT_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_ant_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_ANT_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_c2k_band(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_C2K_Band");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_rf_band(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_RF_Band");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_hw_group_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: ANT_HW_Group_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_state_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_State_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_nw_group_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: ANT_Switch_NW_Group_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_tuner_setting_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_Tuner_Setting_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_cdf_intf_error(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_CDF_Interface_Error");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_fem_scenario(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_FEM_Scenario");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_switch_bitmap(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_Switch_Bitmap");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_boot_mode(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_Boot_Mode");
+}
+
+void CL1D_ErrorCheck_CUST_utas_illegal_init_scenario(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: TAS_Init_Scenario");
+}
+
+void CL1D_ErrorCheck_CUST_ANT_illegal_route_index(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: DAT_Route_IDX");
+}
+
+void CL1D_ErrorCheck_CUST_ANT_illegal_split_band_num(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: ANT_Split_Band_NUM");
+}
+
+void CL1D_ErrorCheck_Is_Null_Pointer(void)
+{
+ kal_bool error = KAL_FALSE;
+
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "Invalid: Null_Pointer");
+}
+#endif
+
+void CL1D_ErrorCheck_Agc_Rat_Type(kal_uint16 rat_type)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, rat_type, 0, 0);
+}
+
+void CL1D_ErrorCheck_Agc_Rx_Path(kal_uint16 rx_path)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, rx_path, 0, 0);
+}
+
+void CL1D_ErrorCheck_Agc_FSM(kal_uint16 rat_type, kal_uint16 agc_fsm)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, rat_type, agc_fsm, 0);
+}
+
+#ifdef L1_SIM
+void CL1D_ErrorCheck_Agc_Test_Mode(kal_uint16 test_mode)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, test_mode, 0, 0);
+}
+
+void CL1D_ErrorCheck_Agc_Cell_Index(kal_uint16 cell_index)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, cell_index, 0, 0);
+}
+#endif
+
+void CL1D_ErrorCheck_Agc_Ping_Pong_Buffer(kal_uint16 ping_valid, kal_uint16 pong_valid)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, ping_valid, pong_valid, 0);
+}
+
+void CL1D_ErrorCheck_Agc_Dma_Status(kal_uint16 status, kal_uint16 trig_status)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, status, trig_status, 0);
+}
+
+void CL1D_ErrorCheck_Agc_Query_Elna_Index_Error(kal_uint16 err_type)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, err_type, 0, 0);
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_Tpc_FSM_Conflict()
+
+ DESCRIPTION: This fucntion is used to check TPC FSM.
+
+ PARAMETERS: error type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_Tpc_FSM_Conflict(kal_uint32 param0, kal_uint32 param1)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, param0, param1, 0);
+}
+
+void CL1D_ErrorCheck_Cfg_Tpc(CL1D_RF_TPC_CFG_ERROR_E error_type)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, error_type, 0, 0);
+}
+
+void CL1D_ErrorCheck_Tpc_DMA_Pre(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, param0, param1, param2);
+}
+
+void CL1D_ErrorCheck_Tpc_DMA_Post(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, param0, param1, param2);
+}
+
+void CL1D_ErrorCheck_Tpc_TQ_Gen_Fail(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2)
+{
+ kal_bool error = KAL_FALSE;
+ //EXT_ASSERT(error, param0, param1, param2);
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "TPC TQ Gen Fail!");
+}
+
+void CL1D_ErrorCheck_Tpc_HAL_FSM_Error(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2)
+{
+ kal_bool error = KAL_FALSE;
+ //EXT_ASSERT(error, param0, param1, param2);
+ DEBUG_ASSERT(error);
+ MODEM_WARNING_MESSAGE(error, "TPC HAL FSM Error!");
+}
+
+/***********************************************
+ FUNCTION NAME: CL1D_ErrorCheck_RxDfe_set_rcc_cq()
+
+ DESCRIPTION: This fucntion is used to check C2K abnormal CW error. It will be called by RXDFE.
+
+ PARAMETERS: error type
+
+ RETURNS VALUES: void
+ ***********************************************/
+void CL1D_ErrorCheck_RxDfe_set_rcc_cq(kal_uint32 rat ,kal_uint32 rcc_cq_idx)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,rat, rcc_cq_idx,0);
+}
+
+
+void CL1D_ErrorCheck_RxDfe_fc_semi_rat(kal_uint32 rat)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,rat,0,0);
+}
+void CL1D_ErrorCheck_RxDfe_p_path_check(kal_uint32 rat,kal_uint32 p_idx,kal_uint32 l_idx)
+{
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error,rat,p_idx,l_idx);
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* NVRAM error check */
+void CL1D_ErrorCheck_NVRAM_query_item_index(kal_uint32 lid, kal_uint32 rec_idx, kal_uint32 i){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, rec_idx, i);
+}
+
+void CL1D_ErrorCheck_NVRAM_read_multi_record(kal_uint32 lid, kal_uint32 lid_size){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, lid_size, 0);
+}
+
+void CL1D_ErrorCheck_NVRAM_check_record_size(kal_uint32 nvram_item_idx, kal_uint32 current_record_size, kal_uint32 first_record_size){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, nvram_item_idx, current_record_size, first_record_size);
+}
+
+void CL1D_ErrorCheck_NVRAM_illegal_out_buffer(kal_uint32 op_code, kal_uint32 lid, kal_uint16 record_index){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, op_code, lid, record_index);
+}
+
+void CL1D_ErrorCheck_NVRAM_illegal_record_index(kal_uint32 lid, kal_uint32 rec_idx, kal_uint16 rec_num){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, rec_idx, rec_num);
+}
+
+void CL1D_ErrorCheck_NVRAM_illegal_in_buffer(kal_uint32 op_code, kal_uint32 lid, kal_uint16 record_index){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, op_code, lid, record_index);
+}
+
+void CL1D_ErrorCheck_NVRAM_write_fail(kal_uint32 error_no, kal_uint32 lid, kal_uint32 record_index){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, error_no, lid, record_index);
+}
+
+void CL1D_ErrorCheck_NVRAM_check_record_index(kal_uint32 lid, kal_uint32 rec_idx, kal_uint32 rec_num){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, rec_idx, rec_num);
+}
+
+void CL1D_ErrorCheck_NVRAM_check_buffer_size(kal_uint32 lid, kal_uint32 buffer_size, kal_uint32 nvram_item_size){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, buffer_size, nvram_item_size);
+}
+
+void CL1D_ErrorCheck_NVRAM_check_record_num_2nd(kal_uint32 lid, kal_uint32 last_rec_num, kal_uint32 rec_num){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, last_rec_num, rec_num);
+}
+
+void CL1D_ErrorCheck_NVRAM_check_item_size_2nd(kal_uint32 lid, kal_uint32 last_nvram_item_size, kal_uint32 nvram_item_size){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, lid, last_nvram_item_size, nvram_item_size);
+}
+
+void CL1D_ErrorCheck_NVRAM_check_dpd_1x_default_write(kal_uint32 band_idx, kal_uint32 last_rec_num, kal_uint32 rec_num){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, band_idx, last_rec_num, rec_num);
+
+}
+
+void CL1D_ErrorCheck_NVRAM_check_dpd_do_default_write(kal_uint32 band_idx, kal_uint32 last_rec_num, kal_uint32 rec_num){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, band_idx, last_rec_num, rec_num);
+
+}
+
+void CL1D_ErrorCheck_CDF_query_fail(kal_uint32 error_type, kal_uint32 return_err){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, error_type, return_err, 0);
+}
+
+void CL1D_ErrorCheck_SX_bmp_query(kal_uint32 module_type, kal_uint32 sx1_valid, kal_uint32 sx2_valid){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, module_type, sx1_valid, sx2_valid);// module_type:0 => DEV module_type:1 => FEM
+}
+
+void CL1D_ErrorCheck_FEM_usage_list_query(kal_uint32 fem_senario){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, fem_senario, 0, 0);
+}
+
+void CL1D_ErrorCheck_FEM_route_list_query(kal_uint32 fem_senario){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, fem_senario, 0, 0);
+}
+
+void CL1D_ErrorCheck_DEV_route_list_query(kal_uint32 location){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, location, 0, 0);
+}
+
+void CL1D_ErrorCheck_CDF_timing_offset_query(kal_uint32 error_type){
+ kal_bool error = KAL_FALSE;
+ EXT_ASSERT(error, error_type, 0, 0);
+}
+
+#endif
+
+void CL1D_ErrorCheck_RxDfe_fc_rcc_use_up(kal_uint16 rat_type, kal_uint16 rcc_num)
+{
+ kal_bool rcc = KAL_FALSE;
+ EXT_ASSERT(rcc,rat_type ,rcc_num ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_get_path_band(kal_uint16 band, kal_uint16 rf_band,kal_uint16 scen)
+{
+ kal_bool path = KAL_FALSE;
+ EXT_ASSERT(path,band ,rf_band ,scen);
+}
+
+void CL1D_ErrorCheck_RxDfe_fc_dyn_scen_path(kal_uint16 path )
+{
+ EXT_ASSERT(KAL_FALSE,path ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_get_free_rcc(kal_uint16 rat )
+{
+ EXT_ASSERT(KAL_FALSE,rat ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_d_die_dump(kal_uint16 rat )
+{
+ EXT_ASSERT(KAL_FALSE,rat ,0 ,0);
+}
+
+void CL1D_ErrorCheck_RxDfe_ccq_trg_usedup_path(kal_uint16 rat )
+{
+EXT_ASSERT(KAL_FALSE,rat ,0 ,0);
+}
+/*******************************************************************************
+ * #define
+ ******************************************************************************/
+
+/*******************************************************************************
+ * typedef
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Constant
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global Variables
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Local Variables
+ * Static variables declaration
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local Functions
+ * Static Functions Prototype
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Static Functions declaration
+ ******************************************************************************/
+
+
+
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_error_check.h b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_error_check.h
new file mode 100644
index 0000000..12ec00f
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_error_check.h
@@ -0,0 +1,676 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_error_check.h
+ *
+ * Project:
+ * --------
+ * MT6177L
+ *
+ * Description:
+ * ------------
+ * Error check assert function
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *----------------------------------------------------------------------------
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+ *----------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file cl1d_rf_error_check.h
+ * @author Make.Wu (MTK11049)
+ * @date 2016.09.06
+ * @brief Error check (header file)
+ * @details
+ ******************************************************************************/
+
+#ifndef _CL1D_RF_ERROR_CHECK_H_
+#define _CL1D_RF_ERROR_CHECK_H_
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "event_info_utility.h"
+
+/*******************************************************************************
+ * #define
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+typedef enum
+{
+ CL1D_RF_HAL_RX_ERR_MAIN_SEC_BOTH_ON = 0,
+ CL1D_RF_HAL_RX_ERR_DIV_SEC_BOTH_ON = 1,
+ CL1D_RF_HAL_RX_ERR_PATH_ON_CONFLICT = 2,
+}CL1D_RF_HAL_RX_ERROR_E;
+
+typedef enum
+{
+ CL1D_RF_CUIF_TPC_CFG_ERR_BUF_FULL = 0,
+ CL1D_RF_CUIF_TPC_CFG_TEST_ERR_CMD_INVALID = 1,
+ CL1D_RF_CUIF_TPC_CFG_TEST_ERR_CMD_VLD_FLAG_NOT_CLEAR = 2,
+ CL1D_RF_CUIF_TPC_CFG_TEST_ERR_BUF_VLD_FLAG_NOT_CLEAR = 3
+}CL1D_RF_CUIF_TPC_CFG_ERROR_E;
+
+typedef enum
+{
+ CL1D_RF_TPC_CFG_ERR_BUF_FULL = 0,
+ CL1D_RF_TPC_CFG_TEST_ERR_CMD_INVALID = 1,
+ CL1D_RF_TPC_CFG_TEST_ERR_CMD_VLD_FLAG_NOT_CLEAR = 2,
+ CL1D_RF_TPC_CFG_TEST_ERR_BUF_VLD_FLAG_NOT_CLEAR = 3
+}CL1D_RF_TPC_CFG_ERROR_E;
+
+typedef enum
+{
+ CL1D_RF_CUIF_AGC_ERR_INIT_BUF_FULL = 0,
+ CL1D_RF_CUIF_AGC_ERR_SCH_BUF_FULL = 1,
+ CL1D_RF_CUIF_AGC_ERR_TEST_CMD_INVALID = 2,
+ CL1D_RF_CUIF_AGC_ERR_CELL_IDX_INVALID = 3,
+}CL1D_RF_CUIF_AGC_ERROR_E;
+
+typedef enum
+{
+ /* TPC PA Bias Part */
+ CL1D_RF_CUST_TPC_PA_BIAS_0 = 0, //[Init] Query num of pa bias setting
+ CL1D_RF_CUST_TPC_PA_BIAS_1 = 1, //[Init] Query control info for all pa bias setting index
+ CL1D_RF_CUST_TPC_PA_BIAS_2 = 2, //[Init] Query BW info for all pa bias setting index
+ CL1D_RF_CUST_TPC_PA_BIAS_3 = 3, //[Init] Query sub_band info by pa_pias_set_index and by bw_set_index
+ CL1D_RF_CUST_TPC_PA_BIAS_4 = 4, //[Init] Query a unit of PA bias data by pa_bias_set_index and by bw_index and by sub_band
+ CL1D_RF_CUST_TPC_PA_BIAS_5 = 5, //[RunTime] Query pa bias setting index
+
+ /* TPC ETM Part*/
+ CL1D_RF_CUST_TPC_ETM_0 = 6, // Query num of ETM bias setting
+ CL1D_RF_CUST_TPC_ETM_1 = 7, // Query control info with one setting index
+ CL1D_RF_CUST_TPC_ETM_2 = 8, // Query a unit of ETM bias data by setting index
+ CL1D_RF_CUST_TPC_ETM_3 = 9, // Create mapping table between RF_BAND and ETM/PA setting index
+
+ /* DEV COMMON Part */
+ CL1D_RF_DEV_RX_PATH_MAP_0 = 9, // Query CDF SX index service
+ CL1D_RF_DEV_RX_PATH_MAP_1 = 10, // Query CDF ADC MIMO index service
+ CL1D_RF_DEV_USAGE_LIST_0 = 11, // Query DEV SX1 usage list
+ CL1D_RF_DEV_USAGE_LIST_1 = 12, // Query DEV SX2 usage list
+ CL1D_RF_DEV_USAGE_LIST_2_0 = 13, // Query DEV SX1+SX2 usage list (SX1)
+ CL1D_RF_DEV_USAGE_LIST_2_1 = 14, // Query DEV SX1+SX2 usage list (SX2)
+ CL1D_RF_DEV_ROUTE_LIST_0 = 15, // Query DEV SX1 route list
+ CL1D_RF_DEV_ROUTE_LIST_1 = 16, // Query DEV SX2 route list
+ CL1D_RF_DEV_ROUTE_LIST_2_0 = 17, // Query DEV SX1+SX2 route list (SX1)
+ CL1D_RF_DEV_ROUTE_LIST_2_1 = 18, // Query DEV SX1+SX2 route list (SX2)
+
+ /* DEV-AFC Part */
+ CL1D_RF_DEV_AFC_0 = 19, // Create Container
+ CL1D_RF_DEV_AFC_1 = 20, // Do CMD
+ CL1D_RF_DEV_AFC_2 = 21, // Release Container
+
+ /* DEV-TEM Part */
+ CL1D_RF_DEV_TEM_MEAS_0 = 22, // Create Container
+ CL1D_RF_DEV_TEM_MEAS_1 = 23, // Do CMD
+ CL1D_RF_DEV_TEM_MEAS_2 = 24, // Release Container
+
+ /* DEV-RX Part */
+ CL1D_RF_DEV_RX_ON_0 = 25, // Create Container
+ CL1D_RF_DEV_RX_ON_1 = 26, // Do CMD
+ CL1D_RF_DEV_RX_ON_2 = 27, // Release Container
+
+ CL1D_RF_DEV_RX_OFF_0 = 28, // Create Container
+ CL1D_RF_DEV_RX_OFF_1 = 29, // Do CMD
+ CL1D_RF_DEV_RX_OFF_2 = 30, // Release Container
+
+ CL1D_RF_DEV_RX_PON_0 = 31, // Create Container
+ CL1D_RF_DEV_RX_PON_1 = 32, // Do CMD
+ CL1D_RF_DEV_RX_PON_2 = 33, // Release Container
+
+ CL1D_RF_DEV_RX_POFF_0 = 34, // Create Container
+ CL1D_RF_DEV_RX_POFF_1 = 35, // Do CMD
+ CL1D_RF_DEV_RX_POFF_2 = 36, // Release Container
+
+ /* DEV-TX Part */
+ CL1D_RF_DEV_TX_ON_0 = 37, // Create Container
+ CL1D_RF_DEV_TX_ON_1 = 38, // Do CMD
+ CL1D_RF_DEV_TX_ON_2 = 39, // Release Container
+
+ CL1D_RF_DEV_TX_OFF_0 = 37, // Create Container
+ CL1D_RF_DEV_TX_OFF_1 = 38, // Do CMD
+ CL1D_RF_DEV_TX_OFF_2 = 39, // Release Container
+
+ /* FEM COMMON Part */
+ CL1D_RF_FEM_USAGE_LIST_0 = 40, // Query FEM SX1 usage list
+ CL1D_RF_FEM_USAGE_LIST_1 = 41, // Query FEM SX2 usage list
+ CL1D_RF_FEM_USAGE_LIST_2_0 = 42, // Query FEM SX1+SX2 usage list (SX1)
+ CL1D_RF_FEM_USAGE_LIST_2_1 = 43, // Query FEM SX1+SX2 usage list (SX2)
+
+ CL1D_RF_FEM_ROUTE_LIST_0 = 44, // Query FEM SX1 route list
+ CL1D_RF_FEM_ROUTE_LIST_1 = 45, // Query FEM SX2 route list
+ CL1D_RF_FEM_ROUTE_LIST_2_0 = 46, // Query FEM SX1+SX2 route list (SX1)
+ CL1D_RF_FEM_ROUTE_LIST_2_1 = 47, // Query FEM SX1+SX2 route list (SX2)
+
+ /* FEM-RX Part */
+ CL1D_RF_FEM_RX_ON_0 = 48, // Create Container
+ CL1D_RF_FEM_RX_ON_1 = 49, // Do CMD
+ CL1D_RF_FEM_RX_ON_2 = 50, // Release Container
+
+ CL1D_RF_FEM_RX_OFF_0 = 51, // Create Container
+ CL1D_RF_FEM_RX_OFF_1 = 52, // Do CMD
+ CL1D_RF_FEM_RX_OFF_2 = 53, // Release Container
+
+ /* FEM-TX Part */
+ CL1D_RF_FEM_TX_ON_0 = 54, // Create Container
+ CL1D_RF_FEM_TX_ON_1 = 55, // Do CMD
+ CL1D_RF_FEM_TX_ON_2 = 56, // Release Container
+
+ CL1D_RF_FEM_TX_OFF_0 = 57, // Create Container
+ CL1D_RF_FEM_TX_OFF_1 = 58, // Do CMD
+ CL1D_RF_FEM_TX_OFF_2 = 59, // Release Container
+
+ /* FEM-Timing Part */
+ CL1D_RF_FEM_TIMING_RX_ON_0 = 60, // Get FEM timing table
+ CL1D_RF_FEM_TIMING_RX_ON_1 = 61, // Get FEM timing offset [ASM set port]
+ CL1D_RF_FEM_TIMING_RX_ON_2 = 62, // Get FEM timing offset [ELNA bias on]
+ CL1D_RF_FEM_TIMING_RX_ON_3 = 63, // Get FEM timing offset [ELNA on]
+
+ CL1D_RF_FEM_TIMING_RX_OFF_0 = 64, // Get FEM timing table
+ CL1D_RF_FEM_TIMING_RX_OFF_1 = 65, // Get FEM timing offset [ASM disable]
+ CL1D_RF_FEM_TIMING_RX_OFF_2 = 66, // Get FEM timing offset [ELNA disable bias]
+ CL1D_RF_FEM_TIMING_RX_OFF_3 = 67, // Get FEM timing offset [ELNA disable]
+
+ CL1D_RF_FEM_TIMING_TX_ON_0 = 68, // Get FEM timing table
+ CL1D_RF_FEM_TIMING_TX_ON_1 = 69, // Get FEM timing offset [ASM set port]
+ CL1D_RF_FEM_TIMING_TX_ON_2 = 70, // Get FEM timing offset [MRX ASM set port]
+ CL1D_RF_FEM_TIMING_TX_ON_3 = 71, // Get FEM timing offset [Coupler set port]
+ CL1D_RF_FEM_TIMING_TX_ON_4 = 72, // Get FEM timing offset [PA on]
+ CL1D_RF_FEM_TIMING_TX_ON_5 = 73, // Get FEM timing offset [ETM on]
+ CL1D_RF_FEM_TIMING_TX_ON_6 = 74, // Get FEM timing offset [ETM trigger]
+
+ CL1D_RF_FEM_TIMING_TX_OFF_0 = 75, // Get FEM timing table
+ CL1D_RF_FEM_TIMING_TX_OFF_1 = 76, // Get FEM timing offset [ASM off]
+ CL1D_RF_FEM_TIMING_TX_OFF_2 = 77, // Get FEM timing offset [MRX ASM off]
+ CL1D_RF_FEM_TIMING_TX_OFF_3 = 78, // Get FEM timing offset [Coupler off]
+ CL1D_RF_FEM_TIMING_TX_OFF_4 = 79, // Get FEM timing offset [PA off]
+ CL1D_RF_FEM_TIMING_TX_OFF_5 = 80, // Get FEM timing offset [ETM off]
+ CL1D_RF_FEM_TIMING_TX_OFF_6 = 81, // Get FEM timing offset [ETM trigger]
+
+ CL1D_RF_DEV_RX_PATH_MAP_2 = 82, // Query CDF ADC RF path index
+
+ CL1D_RF_FEM_CONFLICT_WIN_CTRL_0 = 83, // RF Conflict check - get container
+ CL1D_RF_FEM_CONFLICT_WIN_CTRL_1 = 84, // RF Conflict check - do cmd
+ CL1D_RF_FEM_CONFLICT_WIN_CTRL_2 = 85, // RF Conflict check - release container
+
+ CL1D_RF_FEM_CLEAR_BPI_TX_BUF = 86, // Clear TX BPI buffer when TX off
+ CL1D_RF_DEV_TX_PATH_MAP_0 = 87, // Query CDF TX SX index service
+ CL1D_RF_DEV_TX_PATH_MAP_1 = 88, // Query CDF TX DAC MIMO index service
+}CL1D_RF_CDF_QUERY_ERROR_E;
+
+typedef enum{
+ CL1D_RF_FEM_TIMING_OFFSET_RX_ON_1 = 1, // [Timing valid] ASM set port
+ CL1D_RF_FEM_TIMING_OFFSET_RX_ON_2 = 2, // [Timing valid] ELNA bias on
+ CL1D_RF_FEM_TIMING_OFFSET_RX_ON_3 = 3, // [Timing valid] ELNA on
+
+ CL1D_RF_FEM_TIMING_OFFSET_RX_OFF_1 = 4, // [Timing valid] ASM disable
+ CL1D_RF_FEM_TIMING_OFFSET_RX_OFF_2 = 5, // [Timing valid] ELNA disable bias
+ CL1D_RF_FEM_TIMING_OFFSET_RX_OFF_3 = 6, // [Timing valid] ELNA disable
+
+ CL1D_RF_FEM_TIMING_OFFSET_TX_ON_1 = 7, // [Timing valid] ASM set port
+ CL1D_RF_FEM_TIMING_OFFSET_TX_ON_2 = 8, // [Timing valid] MRX ASM set port
+ CL1D_RF_FEM_TIMING_OFFSET_TX_ON_3 = 9, // [Timing valid] Coupler set port
+ CL1D_RF_FEM_TIMING_OFFSET_TX_ON_4 = 10, // [Timing valid] PA on
+ CL1D_RF_FEM_TIMING_OFFSET_TX_ON_5 = 11, // [Timing valid] ETM on
+ CL1D_RF_FEM_TIMING_OFFSET_TX_ON_6 = 12, // [Timing valid] ETM tigger
+
+ CL1D_RF_FEM_TIMING_OFFSET_TX_OFF_1 = 13, // [Timing valid] ASM off
+ CL1D_RF_FEM_TIMING_OFFSET_TX_OFF_2 = 14, // [Timing valid] MRX ASM off
+ CL1D_RF_FEM_TIMING_OFFSET_TX_OFF_3 = 15, // [Timing valid] Coupler off
+ CL1D_RF_FEM_TIMING_OFFSET_TX_OFF_4 = 16, // [Timing valid] PA off
+ CL1D_RF_FEM_TIMING_OFFSET_TX_OFF_5 = 17, // [Timing valid] ETM off
+ CL1D_RF_FEM_TIMING_OFFSET_TX_OFF_6 = 18, // [Timing valid] ETM tigger
+
+}CL1D_RF_CDF_TIMING_OFFSET_VALID_E;
+/*******************************************************************************
+ * Constant
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variables (Extern)
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global Functions Prototype (Interface)
+ ******************************************************************************/
+void CL1D_ErrorCheck_Dev_config_rf_scenario(kal_uint16 rf_scen);
+void CL1D_ErrorCheck_Dev_afc_config(kal_uint16 path);
+void CL1D_ErrorCheck_Dev_c2k_bsi_switch_to_mml1_bsi(kal_uint16 bsi);
+void CL1D_ErrorCheck_Dev_get_rx1_warmup_code_word(kal_uint16 band_class, kal_uint16 band);
+void CL1D_ErrorCheck_Dev_get_rx2_warmup_code_word(kal_uint16 band_class, kal_uint16 band);
+void CL1D_ErrorCheck_Dev_get_prx_port(kal_uint16 prxPort);
+void CL1D_ErrorCheck_Dev_get_drx_port(kal_uint16 drxPort);
+#if defined(__MD93__)||defined(__MD95__)
+void CL1D_ErrorCheck_Dev_build_rx_warmup_script(kal_uint16 path);
+void CL1D_ErrorCheck_Dev_build_rx_burst_script(kal_uint16 path);
+#endif
+void CL1D_ErrorCheck_Dev_build_rx_patial_on_script(kal_uint16 path);
+void CL1D_ErrorCheck_Dev_build_rx_patial_off_script(kal_uint16 path);
+void CL1D_ErrorCheck_Dev_build_rx_sleep_script(kal_uint16 path);
+void CL1D_ErrorCheck_Dev_rx_on_rx_path(kal_uint16 path);
+void CL1D_ErrorCheck_Dev_rx_on_path_band(kal_uint16 rx_path,kal_uint16 band_class,kal_uint16 rf_band);
+void CL1D_ErrorCheck_Dev_rx_on_mode_rf_config(kal_uint16 mode);
+void CL1D_ErrorCheck_Dev_rx_off_path_mode(kal_uint16 rx_path, kal_uint16 mode);
+void CL1D_ErrorCheck_Dev_tx_on_band_mode(kal_uint16 cdma_band, kal_uint16 band,kal_uint16 rat_type);
+void CL1D_ErrorCheck_Dev_get_tx_warmup_code_word(kal_uint16 band_class, kal_uint16 band);
+void CL1D_ErrorCheck_Dev_get_tx_port(kal_uint16 txPort);
+void CL1D_ErrorCheck_Dev_gate_on(kal_uint16 rat_type);
+void CL1D_ErrorCheck_Dev_tx_off(kal_uint16 rat_type);
+void CL1D_ErrorCheck_Dev_gate_off(kal_uint16 rat_type);
+void CL1D_ErrorCheck_Dev_get_rx_dc_tbl(kal_uint8 rx_path,kal_uint8 rf_band);
+#if defined(__MD93__) || defined(__MD95__)
+void CL1D_ErrorCheck_Dev_pll_srx(kal_uint16 band_class);
+void CL1D_ErrorCheck_Dev_pll_stx(kal_uint16 band_class);
+#endif
+#if defined(__PMIC_VS1_LOW_POWER_CTRL_SUPPORT__)
+void CL1D_ErrorCheck_Dev_vs1(kal_uint16 path_type, kal_uint16 path_on);
+#endif
+void CL1D_ErrorCheck_RxDfe_path_rat(kal_uint16 rat_type);
+void CL1D_ErrorCheck_RxDfe_path_scen(kal_uint16 scen);
+void CL1D_ErrorCheck_RxDfe_fc_rat(kal_uint16 rat_type);
+void CL1D_ErrorCheck_RxDfe_fc_write_rat(kal_uint16 rat_type);
+void CL1D_ErrorCheck_RxDfe_tq_type(kal_uint16 tq_type);
+void CL1D_ErrorCheck_RxDfe_fc_type(kal_uint16 tq_type);
+void CL1D_ErrorCheck_RxDfe_fc_tq_type(kal_uint16 tq_type);
+void CL1D_ErrorCheck_RxDfe_fc_rcc_use_up(kal_uint16 rat_type, kal_uint16 rcc_num);
+void CL1D_ErrorCheck_RxDfe_get_path_band(kal_uint16 band, kal_uint16 rf_band,kal_uint16 scen);
+void CL1D_ErrorCheck_RxDfe_fc_dyn_scen_path(kal_uint16 path );
+void CL1D_ErrorCheck_RxDfe_get_free_rcc(kal_uint16 rat );
+void CL1D_ErrorCheck_RxDfe_d_die_dump(kal_uint16 rat );
+void CL1D_ErrorCheck_RxDfe_ccq_trg_usedup_path(kal_uint16 rat );
+void CL1D_ErrorCheck_TxDfe_path_scen(kal_uint16 scen);
+void CL1D_ErrorCheck_TxDfe_evt_scen(kal_uint16 scen);
+void CL1D_ErrorCheck_TxDfe_evt_rat(kal_uint16 rat_type);
+void CL1D_ErrorCheck_TxDfe_ttg_scen(kal_uint16 scen);
+void CL1D_ErrorCheck_TxDfe_ttg_rat(kal_uint16 rat);
+void CL1D_ErrorCheck_TxDfe_ttg_phi(kal_uint16 phi);
+void CL1D_ErrorCheck_RxDfe_p_path_check(kal_uint32 rat,kal_uint32 p_idx,kal_uint32 l_idx);
+
+/* CUST PARAMETER */
+void CL1D_ErrorCheck_CUST_param_illegal_sysBandClass(kal_uint8 bandClass);
+#if defined(__MD93__) || defined(__MD95__)
+/* CUST MIPI */
+/** RX & TX **/
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_rx(kal_uint16 dataEnd);
+void CL1D_ErrorCheck_CUST_mipi_illegal_event_type_rx(kal_uint16 rxEventType);
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_tx(kal_uint16 txDataEnd);
+void CL1D_ErrorCheck_CUST_mipi_illegal_event_type_tx(kal_uint16 txEventType);
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index(kal_uint8 txRxBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq(kal_uint16 mipiDataSeq);
+/** TPC 1xrtt **/
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_tpc1xrtt(kal_uint16 tpcDataEnd);
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_tpc1xrtt(kal_uint8 tpcBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_tpc1xrtt(kal_uint16 mipiDataSeqTpc);
+/** TPC evdo **/
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_tpcEvdo(kal_uint16 tpcDataEnd);
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_tpcEvdo(kal_uint8 tpcBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_tpcEvdo(kal_uint16 mipiDataSeqTpc);
+/** ETM **/
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_etm(kal_uint16 etmDataEnd);
+void CL1D_ErrorCheck_CUST_mipi_illegal_event_type_etm(kal_uint16 etmEventType);
+/*** ETM TX ON ***/
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etmTxOn(kal_uint8 etmBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etmTxOn(kal_uint16 mipiDataSeq);
+/*** ETM TX OFF ***/
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etmTxOff(kal_uint8 etmBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etmTxOff(kal_uint16 mipiDataSeq);
+/*** ETM TPC 1XRTT ***/
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_etm_tpc1xrtt(kal_uint16 tpcDataEnd);
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etm_tpc1xrtt(kal_uint8 etmBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etm_tpc1xrtt(kal_uint16 mipiDataSeq);
+/*** ETM TPC EVDO ***/
+void CL1D_ErrorCheck_CUST_mipi_illegal_data_tab_num_etm_tpcEvdo(kal_uint16 tpcDataEnd);
+void CL1D_ErrorCheck_CUST_mipi_illegal_buffer_index_etm_tpcEvdo(kal_uint8 etmBufferIndex);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_seq_etm_tpcEvdo(kal_uint16 mipiDataSeq);
+
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_num(kal_bool is_start,kal_uint16 mipiDataNum);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_data_check(void *infoPtr,kal_uint8 band, kal_uint8 act);
+void CL1D_ErrorCheck_CUST_mipi_illegal_mipi_get_subband_check(kal_uint32 subband_freq, kal_uint32 freq);
+
+void CL1D_ErrorCheck_Dev_tx_poc_band(kal_uint32 band_class);
+#endif //__MD93__||__MD95__
+
+/* CUST CALIBRATION */
+void CL1D_ErrorCheck_CUST_cal_illegal_rat(kal_uint8 rat);
+void CL1D_ErrorCheck_CUST_cal_illegal_chanNum(kal_uint16 chanNum);
+void CL1D_ErrorCheck_CUST_cal_illegal_devSenario(kal_uint8 devSenario);
+void CL1D_ErrorCheck_CUST_cal_runtime_illegal_devSenario(kal_uint8 devSenario);
+
+
+/* CUST ELNA */
+void CL1D_ErrorCheck_CUST_elna_illegal_desSubband(kal_uint8 dstSubband);
+void CL1D_ErrorCheck_CUST_elna_illegal_elnaSwitch(kal_uint8 elnaSel);
+void CL1D_ErrorCheck_CUST_elna_illegal_category(kal_uint8 elnaCategory);
+void CL1D_ErrorCheck_CUST_elna_illegal_gain_type(kal_uint8 elnaGain);
+
+
+/* CUST TAS */
+#if defined(__MD93__) || defined(__MD95__)
+void CL1D_ErrorCheck_CUST_tas_illegal_c2k_band(kal_uint8 c2k_band);
+void CL1D_ErrorCheck_CUST_tas_illegal_rf_band(kal_uint8 rf_band);
+void CL1D_ErrorCheck_CUST_tas_illegal_ant_index(kal_uint8 ant_index,kal_uint8 rf_band);
+void CL1D_ErrorCheck_CUST_utas_illegal_hw_group_index(kal_uint8 rf_band,kal_uint8 hw_group_index);
+void CL1D_ErrorCheck_CUST_utas_illegal_state_index(kal_uint8 rf_band,kal_uint8 tas_state);
+#else
+void CL1D_ErrorCheck_CUST_utas_illegal_nv_status(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_ant_index(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_ant_port_index(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_c2k_band(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_rf_band(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_hw_group_index(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_state_index(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_nw_group_index(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_tuner_setting_index(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_cdf_intf_error(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_fem_scenario(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_switch_bitmap(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_boot_mode(void);
+void CL1D_ErrorCheck_CUST_utas_illegal_init_scenario(void);
+void CL1D_ErrorCheck_CUST_ANT_illegal_route_index(void);
+void CL1D_ErrorCheck_CUST_ANT_illegal_split_band_num(void);
+void CL1D_ErrorCheck_Is_Null_Pointer(void);
+#endif
+
+
+/* TEMPERATURE*/
+void CL1D_ErrorCheck_TEMP_meas(kal_uint8 rat,kal_uint8 tmp_mode);
+
+/* HAL common*/
+void CL1D_ErrorCheck_Hal_Rat_Type(kal_uint8 rat);
+
+/* HAL_RX*/
+void CL1D_ErrorCheck_Hal_Rx_Conflict(CL1D_RF_HAL_RX_ERROR_E error_type,kal_uint8 cur_bmp, kal_uint8 req_bmp);
+
+/* HAL_AFC*/
+void CL1D_ErrorCheck_Hal_Afc_Band_Class(kal_uint32 band_class);
+void CL1D_ErrorCheck_Hal_Afc_Channel(kal_uint32 band_class, kal_uint32 channel);
+
+/* CUIF*/
+void CL1D_ErrorCheck_Cuif_Tpc(CL1D_RF_CUIF_TPC_CFG_ERROR_E error_type);
+void CL1D_ErrorCheck_Cuif_Agc(CL1D_RF_CUIF_AGC_ERROR_E error_type, kal_uint32 param0, kal_uint32 param1);
+
+/*BPI Conflict*/
+void CL1D_ErrorCheck_Rf_Confict(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2);
+/*--HPUE --*/
+/*custom file*/
+void CL1D_ErrorCheck_Rf_PaVddSel_CustomFileSetting(kal_uint8 rf_band);
+/*interface info illegal */
+#if defined(__MD93__)||defined(__MD95__)
+void CL1D_ErrorCheck_Rf_Hpue_Interface_Info(kal_uint8 param);
+#endif
+/*dpd support illegal band class*/
+void CL1D_ErrorCheck_CUST_param_dpd_illegal_bandsupport(kal_uint8 band);
+
+/* AGC */
+void CL1D_ErrorCheck_Agc_Rat_Type(kal_uint16 rat_type);
+void CL1D_ErrorCheck_Agc_Rx_Path(kal_uint16 rx_path);
+void CL1D_ErrorCheck_Agc_FSM(kal_uint16 rat_type, kal_uint16 agc_fsm);
+#ifdef L1_SIM
+void CL1D_ErrorCheck_Agc_Test_Mode(kal_uint16 test_mode);
+void CL1D_ErrorCheck_Agc_Cell_Index(kal_uint16 cell_index);
+#endif
+void CL1D_ErrorCheck_Agc_Ping_Pong_Buffer(kal_uint16 ping_valid, kal_uint16 pong_valid);
+void CL1D_ErrorCheck_Agc_Dma_Status(kal_uint16 status, kal_uint16 trig_status);
+void CL1D_ErrorCheck_Agc_Query_Elna_Index_Error(kal_uint16 err_type);
+
+/* TPC */
+void CL1D_ErrorCheck_Tpc_FSM_Conflict(kal_uint32 param0, kal_uint32 param1);
+void CL1D_ErrorCheck_Cfg_Tpc(CL1D_RF_TPC_CFG_ERROR_E error_type);
+void CL1D_ErrorCheck_Tpc_DMA_Pre(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2);
+void CL1D_ErrorCheck_Tpc_DMA_Post(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2);
+void CL1D_ErrorCheck_Tpc_TQ_Gen_Fail(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2);
+void CL1D_ErrorCheck_Tpc_HAL_FSM_Error(kal_uint32 param0, kal_uint32 param1, kal_uint32 param2);
+void CL1D_ErrorCheck_RxDfe_set_rcc_cq(kal_uint32 rat ,kal_uint32 rcc_cq_idx);
+void CL1D_ErrorCheck_RxDfe_fc_semi_rat(kal_uint32 rat);
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* NVRAM */
+void CL1D_ErrorCheck_NVRAM_query_item_index(kal_uint32 lid, kal_uint32 rec_idx, kal_uint32 i);
+void CL1D_ErrorCheck_NVRAM_read_multi_record(kal_uint32 lid, kal_uint32 lid_size);
+void CL1D_ErrorCheck_NVRAM_check_record_size(kal_uint32 nvram_item_idx, kal_uint32 current_record_size, kal_uint32 first_record_size);
+void CL1D_ErrorCheck_NVRAM_illegal_out_buffer(kal_uint32 op_code, kal_uint32 lid, kal_uint16 record_index);
+void CL1D_ErrorCheck_NVRAM_illegal_record_index(kal_uint32 lid, kal_uint32 rec_idx, kal_uint16 rec_num);
+void CL1D_ErrorCheck_NVRAM_illegal_in_buffer(kal_uint32 op_code, kal_uint32 lid, kal_uint16 record_index);
+void CL1D_ErrorCheck_NVRAM_write_fail(kal_uint32 error_no, kal_uint32 lid, kal_uint32 record_index);
+void CL1D_ErrorCheck_NVRAM_check_record_index(kal_uint32 lid, kal_uint32 rec_idx, kal_uint32 rec_num);
+void CL1D_ErrorCheck_NVRAM_check_buffer_size(kal_uint32 lid, kal_uint32 buffer_size, kal_uint32 nvram_item_size);
+void CL1D_ErrorCheck_NVRAM_check_record_num_2nd(kal_uint32 lid, kal_uint32 last_rec_num, kal_uint32 rec_num);
+void CL1D_ErrorCheck_NVRAM_check_item_size_2nd(kal_uint32 lid, kal_uint32 last_nvram_item_size, kal_uint32 nvram_item_size);
+void CL1D_ErrorCheck_NVRAM_check_dpd_1x_default_write(kal_uint32 band_idx, kal_uint32 last_rec_num, kal_uint32 rec_num);
+void CL1D_ErrorCheck_NVRAM_check_dpd_do_default_write(kal_uint32 band_idx, kal_uint32 last_rec_num, kal_uint32 rec_num);
+
+/* CDF query error */
+void CL1D_ErrorCheck_CDF_query_fail(kal_uint32 error_type, kal_uint32 return_err);
+void CL1D_ErrorCheck_SX_bmp_query(kal_uint32 module_typ, kal_uint32 sx1_valid, kal_uint32 sx2_valid);
+void CL1D_ErrorCheck_FEM_usage_list_query(kal_uint32 fem_senario);
+void CL1D_ErrorCheck_FEM_route_list_query(kal_uint32 fem_senario);
+void CL1D_ErrorCheck_DEV_route_list_query(kal_uint32 location);
+void CL1D_ErrorCheck_CDF_timing_offset_query(kal_uint32 error_type);
+
+#endif // __MD97__ || __MD97P__
+
+
+#endif //_CL1D_RF_ERROR_CHECK_H_
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_mmrf_pcore.c b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_mmrf_pcore.c
new file mode 100644
index 0000000..130fc76
--- /dev/null
+++ b/mcu/interface/l1/cl1/rfd/external/comm/rf_custom/cl1d_rf_mmrf_pcore.c
@@ -0,0 +1,87 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cl1d_rf_mmrf_pcore.c
+ *
+ * Project:
+ * --------
+ * 93
+ *
+ * Description:
+ * ------------
+ * Interface implementation provided to MMRF.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+
+#include "kal_general_types.h"
+#include "cl1d_rf_cid.h"
+
+#if IS_C2K_DRDI_SUPPORT
+#include "mml1_custom_drdi.h"
+#include "c2k_custom_drdi.h"
+#endif
+
+kal_bool cl1_custom_drdi_enable =
+#if IS_C2K_DRDI_SUPPORT
+#if defined(__MD93__)
+ IS_MML1_DRDI_ENABLE
+#else
+ 1
+#endif
+#else
+ 0
+#endif
+;
+
+
+