[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6

MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF  modem version: NA

Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/l1/cl1/common/cl1fhrtbaconstant.h b/mcu/interface/l1/cl1/common/cl1fhrtbaconstant.h
new file mode 100644
index 0000000..f9d1f93
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1fhrtbaconstant.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2016
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef  _CL1FHRTBACONSTANT_H_
+#define  _CL1FHRTBACONSTANT_H_
+
+#ifdef MTK_DEV_93M_PREIT
+
+
+/*****************************************************************************
+
+  FILE NAME: cl1fhrtbaconstant.h
+
+  DESCRIPTION:
+
+     This file contains the constant definition of RTBA module in 93m
+
+*****************************************************************************/
+
+/*----------------------------------------------------------------------------
+* Definitions
+*----------------------------------------------------------------------------*/
+#define FEC_DDL_RX_MARGIN                       (850)
+#define FEC_DDL_TRX_MARGIN                      (950)
+#define FEC_DDL_RX_MARGIN_CONN_STANDBY_MEAS     (5000)
+
+/** Define for the RTBA Channel related block info. */
+#define RTBA_BASIC_BLOCK_LENGTH                  (20000)                             /** The RTBA basic block length in us unit. */
+#define RTBA_XL1_ICS_SYNC_SMALL_BLOCK_LENGTH     (80000/3)                           /** The XL1 sync channel small block reserve length, in us unit. */   
+#define RTBA_XL1_CONN_PS_RX_BLOCK_LENGTH         (RTBA_BASIC_BLOCK_LENGTH * 6)             /** The XL1 connect ps block length. */
+#define RTBA_XL1_SLT_PCH_LOST_DET_BLOCK_LENGTH   RTBA_BASIC_BLOCK_LENGTH             /** The XL1 PCH Lost block length. */
+#define RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH      RTBA_BASIC_BLOCK_LENGTH             /** The XL1 non-slotted PCH overhead block length. */
+#define RTBA_XL1_NSLT_PCH_LONG_BLOCK_LENGTH      (RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH * 16)
+    
+#ifdef  MTK_CBP_SYNC_OPTIMIZE
+#define XL1_MINI_ACQ_FAST_AGC_ICS_LENGTH         (3500)    
+#endif
+    
+#define XL1_MINI_ACQ_FAST_AGC_LENGTH             (5750)                             /** The XL1 mini acquisition length,which needs to be added to RTB block 
+                                                                                                                                        when previously preempt, in us unit. */  
+#define RTBA_EVL1_ICS_SYNC_SMALL_BLOCK_LENGTH    RTBA_BASIC_BLOCK_LENGTH            /** The EvL1 Sync pch channel basic block length in us unit. */                                                                                                                                  
+#define RTBA_EVL1_NSLT_CC_OVHD_BLOCK_LENGTH      RTBA_BASIC_BLOCK_LENGTH            /** The EvL1 non-slotted pch channel basic block length in us unit. */
+#define RTBA_EVL1_CONN_RX_BLOCK_LENGTH           RTBA_BASIC_BLOCK_LENGTH            /** The EvL1 Connect Rx channel basic block length in us unit. */
+
+#define RTBA_XL1_BRP_TAIL_MARGIN_20MS            (3*1250)                           /** 1xRTT's BRP Tail Margin for 20ms frame size (3PCG).*/
+#define RTBA_XL1_BRP_TAIL_MARGIN_26MS            (3*1667)                           /** 1xRTT's BRP Tail Margin for 26ms frame size (3PCG).*/
+#define RTBA_XL1_BRP_TAIL_MARGIN_20MS_TRAFFIC    (6*1250)														/** 1xRTT's BRP Tail Margin for 20ms FCH frame size (3PCG).*/
+
+#define RTBA_SCHE_FAKE_MARGIN_20MS               (1250)                             /** The fake margin for RTBA schedule for RC control.*/
+#define RTBA_SCHE_FAKE_MARGIN_26MS               (1667)                             /** The fake margin for RTBA schedule for RC control.*/
+
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS       (1250)                           /** The check dsp idle margin for RC control.*/
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS       (1667)                           /** The check dsp idle margin for RC control.*/
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS_LONG  (6250)                           /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 5*1250.*/
+
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_LONG  (10000)                          /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 6*1667us.*/
+#define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED   (6666)                           /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 4*1667us.*/
+
+
+#define RTBA_SCHE_HSC_PREEMPT_ADVANCE_OFFSET    (RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED)   /** Indicate the HSC preempt gap for HSC fully/div preemption.*/
+#define RTBA_INVALID_GAP_START_TIME             (0xFFFFFFFF)
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+#endif
+