[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/l1/cl1/common/cl1rcreq.h b/mcu/interface/l1/cl1/common/cl1rcreq.h
new file mode 100644
index 0000000..a6a7e15
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1rcreq.h
@@ -0,0 +1,299 @@
+ /*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CL1_RC_REQ_H_
+#define _CL1_RC_REQ_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1rcreq.h
+*
+* DESCRIPTION : This file contains data type definitions about RC Req
+*
+*
+************************************************************************************/
+
+/*Essential Definitions*/
+#include "sysdefs.h"
+#include "sysapi.h"
+#include "sysfrc.h"
+#include "cl1fr.h"
+#include "cl1fhrtbadefs.h"
+#include "cl1fhrtbaconstant.h"
+#include "hscapi.h"
+
+#if defined(MTK_DEV_93M_PREIT) && defined(MTK_PLT_ON_PC) && defined(MTK_PLT_ON_PC_IT) && defined(MTK_DEV_93M_C2K_L1_UT)
+#define CL1_RC_UNIT_TEST
+#endif
+
+#ifdef CL1_RC_UNIT_TEST
+#define M_CL1_RC_UT_LOG(a,b) Cl1RcUtLoggingBitmap(a,b)
+#else
+#define M_CL1_RC_UT_LOG(a,b)
+#endif
+
+
+
+/******************************** FEATURES MACROS ********************************/
+
+/*Define this macro to enable flow only, no rcd function invoked*/
+/*#define CL1_RC_REQ_SEQ_FLOW_ONLY (0)*/
+
+/*Define this macro to enable power control, but real api will be redefined as dummy function*/
+/*#define CL1_RC_DRV_PWR_CTRL_FLOW_ONLY (1)*/
+
+/*Define this macro to enable clock control, but no real hw will be accessed if this is macro defined*/
+/*#define CL1_RC_DRV_CLK_CTRL_FLOW_ONLY (2)*/
+
+/*Define this macro to enable sram control, but no real hw will be accessed if this is macro defined*/
+/*#define CL1_RC_DRV_SRAM_CTRL_FLOW_ONLY (3)*/
+
+/*Define this macro to enable modem dvfs, should be compatible with the flow only option enabled in dvfs driver*/
+/*#define CL1_RC_DRV_MODEM_DVFS_FLOW_ONLY (4)*/
+
+/*Define this macro to enable dsp sleep flow control, but real api will be redefined as dummy function*/
+/* #define CL1_RC_DRV_DSP_SLEEP_FLOW_ONLY (5) */
+
+/*Define this macro to enable dsp sleep flow control, but real api will be redefined as dummy function*/
+/* #define CL1_RC_DRV_DSP_DDL_FLOW_ONLY (6) */
+
+/******************************** Local Const Definitions ********************************/
+
+#define CL1_RC_PCG_DURATION (1536 << 3)
+#define CL1_RC_SLOT_DURATION (2048 << 3)
+
+#define CL1_RC_SFRAME_PCG_NUM (64)
+#define CL1_RC_SFRAME_SLOT_NUM (48)
+
+/*DDL duration in 1/8 chip unit*/
+#define CL1_RC_FEC_RX_DDL_DURATION (8356) /*unit is 1/8 chip*/
+#define CL1_RC_FEC_TRX_DDL_DURATION (9339) /*unit is 1/8 chip*/
+#define CL1_RC_RAKE_MD32_DDL_DURATION (47262) /*unit is 1/8 chip*/
+
+/*Different period to return to Arbiter to help decide how many TSs to protect*/
+#define CL1_RC_REQ_TXON_PERIOD (3)
+
+/* This macro used for RC internal Tx off flow schedule, value 3 is to guarantee that turn off Tx RC HW after Tx path off */
+#define CL1_RC_REQ_TXOFF_DELAY_PERIOD (3) /* 3 lots */
+
+#define CL1_RC_REQ_EVDO_TXOFF_DELAY_DURATION (CL1_RC_REQ_TXOFF_DELAY_PERIOD*1666) /* 3*1666=4998us, EVDO slot:1666us */
+#define CL1_RC_REQ_1XRTT_TXOFF_DELAY_DURATION (CL1_RC_REQ_TXOFF_DELAY_PERIOD*1250) /* 3*1250=3750us, 1xRTT slot:1250us */
+
+#if (CL1_RC_REQ_EVDO_TXOFF_DELAY_DURATION) > (CL1_IF_EVDO_RC_REQ_TXOFF_DELAY*1000)
+#error ("CL1_RC_REQ_EVDO_TXOFF_DELAY_DURATION) > (CL1_IF_EVDO_RC_REQ_TXOFF_DELAY*1000")
+#endif
+
+#if (CL1_RC_REQ_1XRTT_TXOFF_DELAY_DURATION) > (CL1_IF_1XRTT_RC_REQ_TXOFF_DELAY*1000)
+#error ("CL1_RC_REQ_1XRTT_TXOFF_DELAY_DURATION) > (CL1_IF_1XRTT_RC_REQ_TXOFF_DELAY*1000")
+#endif
+
+/*The maximum length of the request queue*/
+#define CL1_RC_REQ_QDEPTH (2)
+
+/*If the ongoing is 0xFF, the queue is empty*/
+#define CL1_RC_REQ_QEMPTY (0xFF)
+
+/*Magic number for optimize div3*/
+#define CL1_RC_DIV3_MAGIC_NUM (0xAAAAAAAB)
+
+#define CL1_RC_DIV3(Num) ((kal_uint32)((((kal_uint64)(Num))*CL1_RC_DIV3_MAGIC_NUM) >> 33))
+
+#define Cl1RcReqEchipOffset2TsNum(Mode, EchipOffset) (SysFrameSizeIs26ms(Mode)? ((EchipOffset) >> 14):(CL1_RC_DIV3(EchipOffset >> 12)))
+
+#define Cl1RcReqGetTsLength(Mode) (SysFrameSizeIs26ms(Mode)? CL1_RC_SLOT_DURATION : CL1_RC_PCG_DURATION)
+
+#define CL1_RC_REQ_FEC_HRT_MARGIN 1966 /*(200*6144/625)*/
+/******************************** Local Enumerations ********************************/
+
+typedef enum
+{
+ CL1_RC_SEQ_GROUP_TYPE_RX,
+ CL1_RC_SEQ_GROUP_TYPE_TX,
+ CL1_RC_SEQ_GROUP_TYPE_NUM
+}Cl1RcSeqGrpTypeT;
+
+/*Different type will lead to different RX ON RCsequence*/
+typedef enum
+{
+ CL1_RC_REQ_RXON_SCHONLY,
+ CL1_RC_REQ_RXON_CHANNELRX,
+ CL1_RC_REQ_RXON_STDBYMEAS,
+ CL1_RC_REQ_RXON_TYPENUM
+}Cl1RcReqRxOnTypeT;
+
+/*Different type means different resource to OFF*/
+typedef enum
+{
+ CL1_RC_REQ_RXOFF_SCHONLY,
+ CL1_RC_REQ_RXOFF_CHANNELRX,
+ CL1_RC_REQ_RXOFF_TYPENUM
+}Cl1RcReqRxOffTypeT;
+
+/*Different enum means different receiver of RC OFF COMPLETE EVENT*/
+typedef enum
+{
+ CL1_RC_REQ_OFF_COMPLETE_NOIND = 0, /*No need to send indication after RC OFF complete*/
+ CL1_RC_REQ_OFF_COMPLETE_2RI, /*Send indication to sleep RI after RC OFF complete*/
+ CL1_RC_REQ_OFF_COMPLETE_2NORMAL, /*Send indication to FT after RC OFF complete*/
+ CL1_RC_REQ_OFF_COMPELTE_TYPE_NUM
+}Cl1RcReqEndIndT;
+
+typedef enum
+{
+ CL1_RC_REQ_PARALLEL,
+ CL1_RC_REQ_CANCEL_ONGOING,
+ CL1_RC_REQ_PEND,
+ CL1_RC_REQ_INVALID,
+ CL1_RC_REQ_MERGE,
+ CL1_RC_REQ_ARB_NUM
+}Cl1RcReqArbT;
+
+typedef enum
+{
+ CL1_RC_REQ_RXON,
+ CL1_RC_REQ_RXOFF,
+ CL1_RC_REQ_TXON,
+ CL1_RC_REQ_TXOFF,
+ CL1_RC_REQ_SCHOFF,
+ CL1_RC_REQ_TYPENUM
+}Cl1RcReqTypeT;
+
+typedef enum
+{
+ CL1_RC_REQ_MODEM_DVFS_SET_RC,
+ CL1_RC_REQ_MODEM_DVFS_SET_HL,
+ CL1_RC_REQ_MODEM_DVFS_SET_NUM,
+}Cl1RcReqModemDvfsUsrT;
+
+typedef enum
+{
+ CL1_RCD_DVFS_SCEN_DEFAULT,
+ CL1_RCD_DVFS_SCEN_CHANNELTX,
+ CL1_RCD_DVFS_SCEN_CHANNELRX,
+ CL1_RCD_DVFS_SCEN_SCHONLY,
+ CL1_RCD_DVFS_SCEN_NUM
+}Cl1RcdDvfsScenT;
+
+/******************************** Local Structures ********************************/
+
+/*Define the RX ON request*/
+typedef struct
+{
+ RtbaRcTimingTypeT RtbTiming;
+ kal_bool RakeDdlInd; /*False: Need not to do Rake DDL; True: Need to do Rake DDL*/
+ kal_bool RcCotnrol; /*False: RF operation only; TRUE: RF operation with RC operation;*/
+ SysAirInterfaceT Mode;
+}Cl1RcReqRxOnT;
+
+/*Define the RX OFF request*/
+typedef struct
+{
+ SysSFrameTimeT EventTime;
+ Cl1RcReqEndIndT EndIndication;
+ SysAirInterfaceT Mode;
+}Cl1RcReqRxOffT;
+
+/*Define the TX ON/OFF request*/
+typedef struct
+{
+ SysSFrameTimeT EventTime;
+ kal_bool TxForAccess;
+ SysAirInterfaceT Mode;
+}Cl1RcReqTxOnOffT;
+
+/*A func ptr which should pooint to the function by which we can judge whether SCH post process is ongoing*/
+typedef kal_bool (*Cl1RcSchPostProcStatusFuncPtr)(void);
+
+/*Define the SCH OFF request*/
+typedef struct
+{
+ SysAirInterfaceT Mode;
+}Cl1RcReqSchOffT;
+
+/* RX/TX Req Data Stored */
+
+/*Define this union to merge the two kinds of request to simplify data manage and save memory*/
+typedef union
+{
+ Cl1RcReqRxOnT RxOnReq;
+ Cl1RcReqRxOffT RxOffReq;
+}Cl1RcReqRxOnOffT;
+
+typedef struct
+{
+ Cl1RcReqTypeT RcReqType;
+ Cl1RcReqRxOnOffT RcReqInfo;
+}Cl1RcReqRxOnOffInfoT;
+
+
+typedef struct
+{
+ Cl1RcReqRxOnOffInfoT Cl1RcReqRxQ[CL1_RC_REQ_QDEPTH];
+ kal_uint8 Ongoing;
+ kal_bool Pending;
+}Cl1RcReqRxOnOffInfoQueT;
+
+
+typedef struct
+{
+ Cl1RcReqTypeT RcReqType;
+ Cl1RcReqTxOnOffT RcReqInfo;
+}Cl1RcReqTxOnOffInfoT;
+
+
+typedef struct
+{
+ Cl1RcReqTxOnOffInfoT Cl1RcReqTxQ[CL1_RC_REQ_QDEPTH];
+ kal_uint8 Ongoing;
+ kal_bool Pending;
+}Cl1RcReqTxOnOffInfoQueT;
+
+
+/*********************************** RcReq internal functions ***********************************/
+void Cl1RcReqInit(void);
+void Cl1RcTestDDLStart(void);
+
+//void Cl1RcReqRxOnParse(Cl1RcReqRxOnT *RxOn, Cl1RcSeqRxParaT *RcSeq);
+
+//void Cl1RcReqRxOffParse(Cl1RcReqRxOffT *RxOff, Cl1RcSeqRxParaT *RcSeq);
+
+kal_bool Cl1RcReqRxEnque(Cl1RcReqRxOnOffInfoQueT *InfoQ, Cl1RcReqTypeT RcReqType, Cl1RcReqRxOnOffT *ReqInfo);
+
+void Cl1RcReqModemDvfsScenSet(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr, Cl1RcdDvfsScenT Scen);
+
+void Cl1RcReqModemDvfsScenCancel(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr);
+
+#endif
+