[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/l1/cl1/common/cl1shrfc.h b/mcu/interface/l1/cl1/common/cl1shrfc.h
new file mode 100644
index 0000000..62dfff5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cl1shrfc.h
@@ -0,0 +1,294 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CL1_SH_RFC_H_
+#define _CL1_SH_RFC_H_
+
+/***********************************************************************************
+*
+* FILE NAME : cl1shrfc.h
+*
+* DESCRIPTION : RF control interface defination
+*
+* HISTORY :
+* See Log at end of file
+*
+************************************************************************************/
+
+
+#include "kal_public_api.h"
+#include "sysapi.h"
+#include "cl1rcapi.h"
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+#include "../rfd/cl1_rf_tas_public.h"
+#include "cl1d_rf_common_defs.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ Global Defines
+----------------------------------------------------------------------------*/
+/* Pll settling time In Echip, TBD, would be replaced by RFD interface*/
+#define RFC_PLL_TIM_ECHIP (246*8)
+
+#if defined( __MD93__)||defined( __MD95__)
+#define RFC_DO_RXPATH_DELAY (128)
+#else
+#if defined(MT6297)
+#define RFC_DO_RXPATH_DELAY (213)
+#elif defined(MT6885) || defined(MT6873)
+#define RFC_DO_RXPATH_DELAY (193)
+#else
+#define RFC_DO_RXPATH_DELAY (193)
+#endif
+#endif
+
+/**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/
+#ifdef __MD93__
+#define RFC_DO_TRXPATH_DELAY (278) //Same as DO_TXRXDELAY
+#elif defined __MD95__
+#define RFC_DO_TRXPATH_DELAY (273) //Same as DO_TXRXDELAY
+#else
+/**Used to Other Setting ,for example MD97*/
+#if defined(MT6297)
+#define RFC_DO_TRXPATH_DELAY (419) //Same as DO_TXRXDELAY /**415 -->419, Tx Transmite Error change from 0.5us to 0.05us for Apollo*/
+#elif defined(MT6885)|| defined(MT6873)
+#define RFC_DO_TRXPATH_DELAY (402) //Same as DO_TXRXDELAY /**419 -->399, Tx Transmite Error change from 1.9us to 0.05us for Petrus*/
+#else
+#define RFC_DO_TRXPATH_DELAY (402) //Same as DO_TXRXDELAY
+#endif
+
+#endif
+
+/**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/
+#ifdef __MD93__
+#define RFC_RTT_TRXPATH_DELAY (278) //Same as RTT_TXRXDELAY_INIT
+#define RFC_RTT_RXPATH_DELAY (128)
+#elif defined __MD95__
+#define RFC_RTT_TRXPATH_DELAY (273) //Same as RTT_TXRXDELAY_INIT
+#define RFC_RTT_RXPATH_DELAY (128)
+#else
+/**Used to Other Setting ,for example MD97*/
+#if defined(MT6297)
+#define RFC_RTT_TRXPATH_DELAY (419) //Same as RTT_TXRXDELAY_INIT /**415 -->419, Tx Transmite Error change from 0.5us to 0.05us for Apollo*/
+#define RFC_RTT_RXPATH_DELAY (213)
+#elif defined(MT6885) || defined(MT6873)
+#define RFC_RTT_TRXPATH_DELAY (402) //Same as RTT_TXRXDELAY_INIT /**419 -->399, Tx Transmite Error change from 1.9us to 0.05us for Petrus*/
+#define RFC_RTT_RXPATH_DELAY (193)
+#else
+#define RFC_RTT_TRXPATH_DELAY (402) //Same as RTT_TXRXDELAY_INIT
+#define RFC_RTT_RXPATH_DELAY (193)
+#endif
+#endif
+
+#define RFC_RTT_TXPATH_DELAY (RFC_RTT_TRXPATH_DELAY - RFC_RTT_RXPATH_DELAY)
+
+#define RFC_RTT_GATE_ON_OFF_DELAY (400/*TBD*/)
+
+
+/* 80ms Period length in Echip*/
+#define RFC_80MS_PERIOD 0xC0000
+
+/* PCG Period Length In Echip*/
+#define RFC_RTT_PCG_PERIOD (1536*8)
+
+/* Slot Period Length In Echip*/
+#define RFC_EVDO_SLOT_PERIOD (2048*8)
+
+
+typedef enum
+{
+ RFC_PATH_RxM = 0,
+ RFC_PATH_RxD,
+ RFC_PATH_RxS,
+ RFC_PATH_Tx,
+ RFC_MAX_PATH
+}RfcPathTypT;
+
+typedef enum
+{
+ RFC_FREEZE_NONE = 0,
+ RFC_TX_FREEZE,
+ RFC_TX_UNFREEZE,
+}RfcFreezeTypT;
+
+
+typedef enum
+{
+ RFC_TASK_REQUEST = 0,
+ RFC_FRAME_REQUEST,
+ RFC_SLOT_PCG_REQUEST
+}RfcRequestTypT;
+
+
+typedef enum
+{
+ RFC_PATH_OFF,
+ RFC_PATH_OFF_ONGOING,
+ RFC_PATH_ON,
+ RFC_PATH_ON_ONGOING
+}RfcPathStatusT;
+
+
+typedef enum
+{
+ RFC_PATH_RC_OFF,
+ RFC_PATH_RC_ONGOING,
+ RFC_PATH_RC_ON
+}RfcPathRcStatusT;
+
+
+typedef enum
+{
+ RFC_IDLE,
+ RFC_1X_MAIN_ONLY,
+ RFC_1X_DIV_ONLY,
+ RFC_1X_DIV_RX,
+ RFC_DO_MAIN_ONLY,
+ RFC_DO_DIV_ONLY,
+ RFC_DO_DIV_RX,
+ RFC_SHDR,
+ RFC_1X_DFS,
+ RFC_DO_DFS
+}RfcScenarioT;
+
+
+typedef enum
+{
+ ACTION_OFF = 0,
+ ACTION_ON = 1,
+ ACTION_NUM = 2
+}RfcActionOnOffT;
+
+typedef struct
+{
+ SysAirInterfaceT Interface;
+ SysCdmaBandT Band;
+ kal_uint16 Chan;
+ RfcPathTypT Path;
+ RfcActionOnOffT ActionTyp;
+ RfcRequestTypT RequestTyp;
+ void* CommonParmPtr;
+}RfcActionT;
+
+
+typedef struct
+{
+ /* 80ms timing, in echip*/
+ kal_int32 Timing;
+
+ /* Super Frame number*/
+ kal_uint64 SuperFrame;
+
+ /* Immaction, if TRUE, "Timing&SuperFrame" would be obmitted*/
+ kal_bool ImmAction;
+}RfcActionTimeT;
+
+
+typedef struct
+{
+ /* Req Timing Info, Filled Rx Modules(RTBA) in FH
+ * if "RcCtrl" is TRUE, filled with RC timing.
+ * Otherwise, filled with RF timing.
+ */
+ RtbaRcTimingTypeT ReqTiming;
+
+ /* Rake Ddl Indication , for Rx Only*/
+ kal_bool RakeDdlInd;
+
+ /* Rc Control Indication*/
+ kal_bool RcCtrl;
+
+ /* Used for Rc RxOff with "RcCtrl"== TRUE Only*/
+ Cl1RcReqEndIndT EndIndication;
+
+ /* Access Tx Indication*/
+ kal_bool AcTxInd;
+
+ /* Action body*/
+ RfcActionT Action;
+
+ /* Action Timing, Filled by Tx Modules in Task(Without RTBA)
+ * "ImmAction" is valid for both Tx and Rx immedaite action.
+ */
+ RfcActionTimeT ActionTiming;
+}RfcActionReqT;
+
+
+/*----------------------------------------------------------------------------
+ Global Data
+----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Global Variables
+----------------------------------------------------------------------------*/
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+extern C2K_CUSTOM_TAS_STATE_E AntCurrentState[RF_Band_NUM_MAX];
+extern C2K_CUSTOM_TAS_STATE_E GetAntCurrentState(SysCdmaBandT band);
+#endif
+
+/*----------------------------------------------------------------------------
+ Global Function Prototypes
+----------------------------------------------------------------------------*/
+void Cl1ShRfcInit(void);
+void Cl1ShRfcActionReq(RfcActionReqT *ActionReqPtr);
+void Cl1ShRfcMain(SysAirInterfaceT Interface);
+void Cl1ShRfcStatChange(kal_uint32 Param);
+void Cl1ShRfcRcStatToOff(kal_uint32 Param);
+void Cl1ShRfcRcStatToOn(kal_uint32 Param);
+RfcPathStatusT Cl1ShRfcRfStatGet(SysAirInterfaceT Interface, RfcPathTypT Path);
+RfcScenarioT Cl1ShRfcScenarioGet(void);
+void Cl1ShRfcTxFreezeReq(SysAirInterfaceT Interface);
+void Cl1ShRfcTxUnFreezeReq(SysAirInterfaceT Interface);
+kal_bool Cl1ShRfcTxFreezeReqCheck(SysAirInterfaceT Interface);
+RfcPathRcStatusT Cl1ShRfcRcStatGet(SysAirInterfaceT Interface, RfcPathTypT Path);
+void Cl1RfcGetNextRxBoundary(SysAirInterfaceT Interface, kal_int32 *EchipTime, kal_uint64 *SuperFrame);
+void Cl1ShRfcRcReq(SysAirInterfaceT Interface, RfcPathTypT Path, RfcActionOnOffT ActionTyp, RtbaRcTimingTypeT *RcReqTimingPtr, Cl1RcReqEndIndT EndIndication, kal_bool RakeDdlInd, kal_bool AcTxInd);
+void Cl1ShRfcrRxPathInfoGet(SysAirInterfaceT Interface, kal_uint16 *BandPtr, kal_uint16 *ChanPtr);
+void Cl1ShRfcTxOnTimingLogging(void);
+
+#ifdef SYS_OPTION_TX_TAS_ENABLE
+kal_bool Cl1ShRfcOnlyRfImmediateOn(SysAirInterfaceT CurrInterface, kal_uint16 CurrBand,
+ kal_uint16 CurrChan);
+kal_bool Cl1ShRfcOnlyRfImmediateOff(SysAirInterfaceT CurrInterface, kal_uint16 CurrBand,
+ kal_uint16 CurrChan);
+#endif
+#ifdef MTK_DEV_TEMP_C2K_OTFC
+extern kal_uint8 Cl1ShTxDpdOtfcHistoryRecPush(SysAirInterfaceT Interface, kal_uint32 Channel, SysCdmaBandT BandClass);
+extern kal_uint8 Cl1ShTxDpdOtfcGetHistoryRecIdx(SysAirInterfaceT Interface, kal_uint32 Channel, SysCdmaBandT BandClass);
+#endif
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+#endif
+