[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/l1/cl1/common/cl1tstmetaif.h b/mcu/interface/l1/cl1/common/cl1tstmetaif.h
new file mode 100644
index 0000000..9cb49e2
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+++ b/mcu/interface/l1/cl1/common/cl1tstmetaif.h
@@ -0,0 +1,1943 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* Filename:
+* ---------
+* cl1tstmetaif.h
+*
+* Project:
+* --------
+* MTXXXX Project
+*
+* Description:
+* ------------
+* This file contains the log IQ functions.
+*
+* Author:
+* -------
+*
+*
+*==============================================================================
+* HISTORY
+* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*------------------------------------------------------------------------------
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+*------------------------------------------------------------------------------
+* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+*==============================================================================
+******************************************************************************/
+
+#ifndef _CL1TST_META_IF_H_
+#define _CL1TST_META_IF_H_
+
+/*----------------------------------------------------------------------------
+ Include Files
+----------------------------------------------------------------------------*/
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "ft_msg_common.h"
+#include "cl1d_rf_public.h"
+#include "systyp.h"
+#include "cl1_rf_public.h"
+
+#define CL1TST_TEMP_SECTION_NUM 8
+#define CL1TST_FREQ_SECTION_NUM 16
+#define CL1TST_RX_PATH_NUM 3
+#define CL1TST_POWER_MODE_NUM 2
+#define CL1TST_LNA_MODE_NUM 8
+#define CL1TST_PA_SECTION_NUM 8
+#define CL1TST_PA_MODE_NUM 3
+
+#define CL1TST_FHC_TX_ELEMENT_NUM 1000
+#define CL1TST_FHC_RX_ELEMENT_NUM 1000
+
+#define CL1TST_RX_PATH_MAIN (1 << 0)
+#define CL1TST_RX_PATH_DIV (1 << 1)
+#define CL1TST_RX_PATH_SHDR (1 << 2)
+
+#define CL1TST_CAL_RSSI_WIN_ECHIP 0x1000 /* unit E chip (512 chips) */
+#define CL1TST_SUP_FRAME_LEN_ECHIP ST_9M_CNTS_PER_80MS /* unit E chip (80 ms) */
+#define CL1TST_SLOT_LEN_ECHIP ST_9M_CNTS_PER_1PT67MS /* unit E chip (1.66666 ms) */
+#define CL1TST_PCG_LEN_ECHIP ST_9M_CNTS_PER_1PT25MS /* unit E chip (1.25 ms) */
+#define CL1TST_HALF_SLOT_LEN_ECHIP 0x2000 /* unit E chip (1.66666 ms)/2 */
+#define CL1TST_HALF_SLOT_LEN_US 0x341 /* unit us (0.83333 ms) */
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+#define CL1TST_FIVE_PCG_LEN_US 0x186A /* unit us (6.25 ms) */
+#endif
+#define CL1TST_QUART_SLOT_LEN_ECHIP 0x1000 /* unit E chip (1.66666 ms)/4 */
+#define CL1TST_TRC_RSSI_WIN_NUM 12 /* 5ms */
+#define CL1TST_RX_ON_HRT_ECHIP 0x7AE /* unit E chip (200 us), TBD */
+#define CL1TST_RX_DELAY_ECHIP 20 /* unit E chip (20chip), TBD */
+
+#define CL1TST_MOD_HALF_SLOT_ECHIP(A) (A & 0x000001FFF)
+#define CL1TST_MOD_SLOT_ECHIP(A) (A & 0x000003FFF)
+#define CL1TST_MOD_CAL_RSSI_WIN_ECHIP(A) (A & 0x000000FFF)
+
+#define CL1TST_MOD_SUP_FRAME_ECHIP(A) while (A >= ST_9M_CNTS_PER_80MS) \
+ { \
+ A -=ST_9M_CNTS_PER_80MS; \
+ }
+
+
+#define CL1TST_NST_MAX_LIST_NUM 50
+#define CL1TST_NST_MAX_TX_PWR_COUNT 20
+#define CL1TST_NST_MAX_RX_PWR_COUNT 20
+#define CL1TST_RF_BAND_NUM_MAX 5
+#if defined( __MD93__)||defined( __MD95__)
+#define CL1TST_93M_95M_RXAGC_CFG_DELAY 14 /*in 93M and 95M, cfg complete after 10.84ms, and after 1slot,dsp send rssi to IA(after 12.5ms), delay 14ms to make sure rssi is readed after cfg really set*/
+#else
+#define CL1TST_97M_RXAGC_CFG_DELAY 7 /*in 97M,invoking cfg Api in n slot(or pcg). cfg take affect in slot(pcg)n+1,RFD get rssi in n+2 slot(pcg), L1 get it in n+3 slot(pcg), delay 7ms to rssi is readed after cfg really set*/
+#endif
+
+
+/** Tx power differ between bb sine tone and modulate signal if bb sine freq sel is 6 and AMP is 1/2 */
+#define CL1TST_TX_DIFFER_BB_TONE_MODULDATE_SIG (84)
+
+/** define RFD test mode enumeration */
+typedef enum
+{
+ CL1TST_RFD_RX_TST_MODE = 0,
+ CL1TST_RFD_TX_TST_MODE = 1,
+ CL1TST_RFD_META_MODE = 2,
+ CL1TST_RFD_INVALID = 0xFF
+} Cl1TstRfdTstModeT;
+
+typedef enum
+{
+ CL1TST_RX_AGC_FSM_ICS = 0,
+ CL1TST_RX_AGC_FSM_CAL = 1,
+ CL1TST_RX_AGC_FSM_INVALID = 0x7FFF
+}Cl1TstRxAgcFsmT;
+
+/* this enum is TBD (temp use) */
+typedef enum
+{
+ MIPI0,
+ MIPI1,
+ MIPI2,
+ MIPI3,
+ MIPI_END,
+ BSI1 = MIPI_END,
+ BSI_NAME_MAX,
+ BSI_NAME_INVALID = BSI_NAME_MAX
+} BsiNameT;
+
+/** define the RF mode enumeration */
+typedef enum
+{
+ CL1TST_RF_MODE_1XRTT,
+ CL1TST_RF_MODE_EVDO
+} Cl1TstRfModeT;
+
+/** define the RX agc control mode */
+typedef enum
+{
+ CL1TST_RX_AGC_AUTO = 0,
+ CL1TST_RX_AGC_MANUAL = 1
+} Cl1TstRxAgcModeT;
+
+/** define the command action enumeration */
+typedef enum
+{
+ CL1TST_ACTION_OFF,
+ CL1TST_ACTION_ON
+} Cl1TstActionT;
+
+/** define the NVRAM operation enumeration */
+typedef enum
+{
+ CL1TST_NV_NOT_UPDATE,
+ CL1TST_NV_UPDATE,
+ CL1TST_NV_INVALID = 0xFF
+} Cl1TstNvOptT;
+
+/** define the step indication enumeration */
+typedef enum
+{
+ CL1TST_FHC_STEP_IND_NORMAL, /* next step is normal step */
+ CL1TST_FHC_STEP_IND_RETUNE, /* next step is retune step */
+ CL1TST_FHC_STEP_IND_END, /* current step is last step */
+ CL1TST_FHC_STEP_IND_SWITCH, /* next step is switch step */
+ CL1TST_FHC_STEP_IND_NUM
+} Cl1TstFhcStepIndT;
+
+/** define the transmission signal type enumeration */
+typedef enum
+{
+ CL1TST_TX_SIG_TYPE_RF_TONE,
+ CL1TST_TX_SIG_TYPE_BB_TONE,
+ CL1TST_TX_SIG_TYPE_1X,
+ CL1TST_TX_SIG_TYPE_DO_PILOT,
+ CL1TST_TX_SIG_TYPE_DO_ST2
+} Cl1TstTxSigTypeT;
+
+/** define the command execute status enumeration */
+typedef enum
+{
+ CL1TST_REQ_SUCCESS,
+ CL1TST_REQ_FAILURE,
+ CL1TST_REQ_NOT_SUPPORT,
+ CL1TST_REQ_INVALID = 0x7FFFFFFF
+} Cl1TstReqStatusE;
+
+/** define the command Nst Cmd Status enumeration */
+typedef enum
+{
+ CL1TST_NST_CMD_SUCCESS,
+ CL1TST_NST_CMD_FAILURE_CMD,
+ CL1TST_NST_CMD_FAILURE_ICS,
+
+ CL1TST_NST_CMD_FAILURE_SYNC,
+
+ CL1TST_NST_CMD_FAILURE_TCH,
+
+ CL1TST_NST_CMD_FAILURE_HHO,
+ CL1TST_NST_CMD_FAILURE_NOT_SUPPORT,
+ CL1TST_NST_CMD_INVALID = 0x7FFFFFFF
+} Cl1TstNstCmdStatusE;
+
+
+/* CL1TST command type */
+typedef enum
+{
+ CL1TST_CMD_GET_RF_PLAT_INFO =0,
+ CL1TST_CMD_RFD_TEST_MODE_REQ =1,
+ CL1TST_CMD_RFD_INIT_REQ =2,
+ CL1TST_CMD_SET_MIPI_CW =3,
+ CL1TST_CMD_GET_MIPI_CW =4,
+ CL1TST_CMD_SET_SPI_DATA =5,
+ CL1TST_CMD_GET_SPI_DATA =6,
+ CL1TST_CMD_TRANSMIT_CTRL =7,
+ CL1TST_CMD_RECEIVE_CTRL =8,
+ CL1TST_CMD_AFC_CONFIG =9,
+ CL1TST_CMD_TX_AGC_CONFIG =10,
+ CL1TST_CMD_TX_POWER_QUERY =11,
+ CL1TST_CMD_RX_AGC_CONFIG =12,
+ CL1TST_CMD_RX_RSSI_QUERY =13,
+ CL1TST_CMD_AFC_CAL_DATA_SET =14,
+ CL1TST_CMD_AFC_CAL_DATA_GET =15,
+ CL1TST_CMD_RX_CAL_DATA_SET =16,
+ CL1TST_CMD_RX_CAL_DATA_GET =17,
+ CL1TST_CMD_TX_CAL_DATA_SET =18,
+ CL1TST_CMD_TX_CAL_DATA_GET =19,
+ CL1TST_CMD_FHC_START =20,
+ CL1TST_CMD_DPD_PA_DATA_SET =21,
+ CL1TST_CMD_DPD_PA_DATA_GET =22,
+ CL1TST_CMD_DPD_AM_PM_DATA_SET =23,
+ CL1TST_CMD_DPD_AM_PM_DATA_GET =24,
+ CL1TST_CMD_DPD_FAC_START =25,
+#ifndef __MD93__
+ CL1TST_CMD_RX_LNA_PWR_RANGE_GET =26,
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+ CL1TST_CMD_RX_GAIN_GET =27,
+ CL1TST_CMD_TX_GAIN_GET =28,
+ CL1TST_CMD_SET_BPI_DATA =29,
+ CL1TST_CMD_GET_BPI_DATA =30,
+ CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG =31,
+ CL1TST_CMD_RXDFE_IQ_DUMP_CFG =32,
+ CL1TST_CMD_TXDFE_IQ_DUMP_CFG =33,
+ CL1TST_CMD_TXKDFE_IQ_DUMP_CFG =34,
+ CL1TST_CMD_RXTXDFE_IQ_DUMP_QUERY =35,
+#endif
+
+ CL1TST_CMD_FACTORY_MODE_REQ =40,
+ CL1TST_CMD_NORMAL_MODE_REQ =41,
+ CL1TST_CMD_SET_MEID =42,
+ CL1TST_CMD_GET_MEID =43,
+ CL1TST_CMD_UBIN_INIT =44,
+ CL1TST_CMD_UBIN_DEINIT =45,
+
+ CL1TST_CMD_NST_POWER_UP =0x100,
+ CL1TST_CMD_NST_TCH_FER_CFG =0x101,
+ CL1TST_CMD_NST_TX_PWR_MEAS_CFG =0x102,
+ CL1TST_CMD_NST_RX_PWR_MEAS_CFG =0x103,
+ CL1TST_CMD_NST_LIST_MODE_SET_CFG =0x104,
+ CL1TST_CMD_NST_ENTER_TEST_MODE =0x105,
+ CL1TST_CMD_NST_EXIT_TEST_MODE =0x106,
+
+ CL1TST_CMD_RX_ANT_TESTMODE_SET_REQ =0x120,
+
+ CL1TST_CMD_TARGET_ASSERT =0x3E8,
+
+ CL1TST_CMD_INVALID =0x7FFFFFFF
+} Cl1TstCmdTypeE;
+
+#if 0
+#ifdef MTK_PLT_ON_PC_IT
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+/** define RF platform information getting command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstGetRfPlatInfoCmdT;
+
+/** define RF platform information for calibration */
+typedef struct
+{
+ kal_uint16 RfId;
+ kal_uint16 XoType;
+ kal_uint32 BandSupportBmp; // Band support bitmap
+ kal_uint32 RxDivSupportBmp;// RXD band support bitmap
+
+ kal_uint32 MipiSupportBmp; // MIPI band support bitmap
+ kal_uint32 DpdSupportBmp; // DPD band support bitmap
+ kal_uint32 RxSynthNum; // 1: main+div, 2: main+div+SHDR
+ kal_uint32 C2kNsftCapability; // Bit0 indicate the List Nsft Support: 0 means modmem is not support List Nsft; 1: modmem is support List Nsft(5Frame Tx Meas);
+#ifndef __MD93__
+ kal_uint32 OtherCapability; //bit0 used indicate if using cw for rx cal: 0 is disable, 1 is enable, other bits reserved.
+#endif
+}Cl1TstPlatInfoFacT;
+
+/** define RF platform information getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Platform info for factory calibration */
+ Cl1TstPlatInfoFacT PlatInfoFac;
+}Cl1TstGetRfPlatInfoRspT;
+
+/** define RFD test mode request structure */
+typedef struct
+{
+ /** [in] - 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /** [in] - 1: test mode enable
+ 0: test mode disablein */
+ kal_uint8 TstModeEn;
+
+ /** [in] - bit0: RX test mode
+ bit1: TX test mode
+ bit2: META mode
+ Note: just one bit can be set/clear every time
+ */
+ kal_uint8 TstModeBmp;
+
+ /** [in] - 1: L1 normal mode enable */
+ kal_uint8 L1NorModeEn;
+} Cl1TstRfdTestModeReqCmdT;
+
+/** define RFD test mode confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRfdTestModeReqRspT;
+
+/** define RF driver init command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstRfdInitReqCmdT;
+
+/** define RF driver init response structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRfdInitReqRspT;
+
+/** define MIPI codeword setting command structure */
+typedef struct
+{
+ kal_uint16 MipiPort;
+ kal_uint16 Reserved;
+ kal_uint32 MipiUsid;
+ kal_uint32 MipiAddr;
+ kal_uint32 MipiData;
+} Cl1TstSetMipiCodeWordCmdT;
+
+/** define MIPI codeword setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetMipiCodeWordRspT;
+
+/** define MIPI codeword getting command structure */
+typedef struct
+{
+ kal_uint16 MipiPort;
+ kal_uint16 Reserved;
+ kal_uint32 MipiUsid;
+ kal_uint32 MipiAddr;
+} Cl1TstGetMipiCodeWordCmdT;
+
+/** define MIPI codeword getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* MIPI data */
+ kal_uint32 MipiData;
+} Cl1TstGetMipiCodeWordRspT;
+
+/** define SPI data setting command structure */
+typedef struct
+{
+ kal_uint16 SpiId;
+ kal_uint16 Reserved;
+ kal_uint32 SpiAddr;
+ kal_uint32 SpiData;
+} Cl1TstSetSpiDataCmdT;
+
+/** define SPI data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetSpiDataRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ kal_uint16 SpiId;
+ kal_uint16 Reserved;
+ kal_uint32 SpiAddr;
+} Cl1TstGetSpiDataCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* SPI data */
+ kal_uint32 SpiData;
+} Cl1TstGetSpiDataRspT;
+
+/** define 1xRTT signal parameters */
+typedef struct
+{
+ /* Only for RTT */
+ /**0->RC1,1->RC2, etc*/
+ kal_uint8 RevRc;
+ /* Only for RTT */
+ //0: ACCESS, 1: FCH 2: FCH+SCH
+ kal_uint8 ChnType;
+ /* Only for RTT */
+ /**0->Full,1->Half Rate, etc*/
+ kal_uint8 FchRate;
+ /* Only for RTT */
+ kal_uint8 SchRate;
+
+ /* Only for RTT */
+ kal_uint16 GatePat; //GateOn/Off pattern
+
+ /* Only for RTT */
+ kal_uint16 FpcPat; //FPC pattern
+
+ /* Only for RTT */
+ kal_uint16 TxPreamble;
+
+ /* Only for RTT */
+ kal_uint16 LcmLow;
+
+ /* Only for RTT */
+ kal_uint16 SchWc; //Walsh code for SCH channel
+
+ /* Only for RTT */
+ kal_uint16 RaDly; //RA chip delay for access transmission
+
+ /* Only for RTT */
+ kal_uint16 TurboEn; //Indicate Turbo or CC encode for SCH channel
+ kal_uint16 Reserved;
+
+} Cl1Tst1xSigParaT;
+
+/** define RF transmitter control command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: OFF, 1: ON */
+ kal_uint8 Action;
+
+ /* 0: TXDFE RF tone for 1xRTT and EVDO
+ 1: TXDFE BB signal tone for 1xRTT and EVDO
+ 2: reverse 1xRTT signal for 1xRTT
+ 3: reverse EVDO pilot only for EVDO
+ 4: reverse EVDO subtype2 for EVDO */
+ kal_uint8 SigType;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Channel Number to turn on*/
+ kal_uint16 ChannelNum;
+
+ /* Reserved */
+ kal_uint16 Reserved1;
+
+ /* Frequency offset for RF tone transmission */
+ kal_uint32 FreqOffset;
+
+ /* BB tone configuration parameters */
+ kal_uint32 BbToneCfg;
+
+ Cl1Tst1xSigParaT RttSigPara;
+
+} Cl1TstTransmitCtrlCmdT;
+
+/** define RF transmitter control confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTransmitCtrlRspT;
+
+/** define RF receive control command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: OFF, 1: ON */
+ kal_uint8 Action;
+
+ /* bit0 for Main, bit1 for Div, bit2 for SHDR */
+ kal_uint8 PathBitmap;
+
+ /* Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Channel number to turn on*/
+ kal_uint16 ChannelNum;
+
+ /* Rx AGC FSM, 0 : Auto(RSSI scan) 1: calibration */
+ kal_uint16 RxAgcFsm;
+
+} Cl1TstReceiveCtrlCmdT;
+
+/** define RF receive control confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstReceiveCtrlRspT;
+
+/** define AFC configure command structure */
+typedef struct
+{
+ /* Manual for auto mode*/
+ kal_uint8 CtrlMode;
+
+ /* Cap Id valid indication*/
+ kal_uint8 CapIdValid;
+
+ /* Cap Id*/
+ kal_uint16 CapId;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* AFC DAC valid indication*/
+ kal_uint8 DacValid;
+
+ /*AFC DAC value*/
+ kal_uint16 DacValue;
+} Cl1TstAfcConfigCmdT;
+
+/** define AFC configure confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstAfcConfigRspT;
+
+/** define Tx AGC configuration command structure for RF test and traditional calibration */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* 0: APT mode, 1: DPD mode */
+ kal_uint8 PaType;
+
+ /* 0: fix power 1: manual mode */
+ kal_uint8 CtrlMode;
+
+ /* ILPC enable or disable */
+ kal_uint8 IlpcEnable;
+
+ /* PA table index */
+ kal_uint8 PaTblIdx;
+
+ /* PA mode, 0: high, 1: middle, 2: low */
+ kal_uint8 PaMode;
+
+ /* Tx Power in dBm for fix power, Q5*/
+ kal_int16 TxPwr;
+
+ /* Tx Power in dBm for calibration, Q5*/
+ kal_int16 TxPwrCal;
+
+ /* PA gain, Q5 dBm */
+ kal_int16 PaGain;
+
+ /* Coupler loss, Q5 dB */
+ kal_int16 CpLoss;
+
+ /* AM */
+ kal_int16 Am;
+
+ /* PM */
+ kal_int16 Pm;
+
+ /* 0/1*/
+ kal_uint8 Vm1;
+
+ /*0/1*/
+ kal_uint8 Vm2;
+
+ /* voltage, in unit of mV*/
+ kal_uint16 Vcc;
+
+} Cl1TstTxAgcConfigCmdT;
+
+/** define Tx AGC configuration confirm structure for RF test and traditional calibration */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTxAgcConfigRspT;
+
+/** define DDPC result getting command structure */
+typedef struct
+{
+ kal_uint8 Reserved;
+} Cl1TstTxPowerQueryCmdT;
+
+/** define DDPC result getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Tx power, unit is Q5 dBm */
+ kal_int16 Power;
+ kal_int16 Reserved;
+} Cl1TstTxPowerQueryRspT;
+
+/** define Rx AGC configuration command structure for RF test and traditional calibration */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+
+ /* 0: Auto, 1: Manual for calibration and test, 2: RSSI scan */
+ kal_uint8 CtrlMode;
+
+ /* 0: high power mode, 1: low power mode */
+ kal_uint8 PwrMode;
+
+ /* 0: stage 0, 1: stage 1....5: stage 5 */
+ kal_uint8 LnaMode;
+
+#ifdef __MD93__
+ kal_uint8 Reserved1;
+#else
+ /* 0: disable, 1: enable */
+ kal_uint8 DigGainFix;
+#endif
+
+ /* Reserved */
+ kal_uint16 Reserved2;
+
+} Cl1TstRxAgcConfigCmdT;
+
+/** define Rx AGC configuration confirm structure for RF test and traditional calibration */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAgcConfigRspT;
+
+
+/** define RSSI query command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+} Cl1TstRxRssiQueryCmdT;
+
+/** define RSSI query confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Main antenna Rx power, unit is Q5 dBm */
+ kal_int16 RxMainPower;
+
+ /* Diversity antenna Rx power, unit is Q5 dBm */
+ kal_int16 RxDivPower;
+
+} Cl1TstRxRssiQueryRspT;
+
+/** define AFC calibration data setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* Reserved */
+ kal_uint8 Reserved1;
+
+ /* Reserved */
+ kal_uint16 Reserved2;
+
+ /* AFC calibration data */
+ CL1D_RF_AFC_DATA_T AfcCalData;
+
+} Cl1TstAfcCalDataSetCmdT;
+
+/** define AFC calibration data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstAfcCalDataSetRspT;
+
+/** define AFC calibration data getting command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstAfcCalDataGetCmdT;
+
+/** define AFC calibration data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* AFC calibration data */
+ /* LID:NVRAM_EF_CL1_AFC_DATA__LID */
+ CL1D_RF_AFC_DATA_T AfcCalData;
+
+} Cl1TstAfcCalDataGetRspT;
+
+/** define Rx calibration data structure */
+typedef struct
+{
+ /* High power mode path loss */
+ /* LID NVRAM_EF_CL1_MAIN_RX_PATH_LOSS_HPM_BAND_X_LID */
+ CL1D_RF_RX_PATH_LOSS_COMP_T RxPLossHPM;
+
+ /* Low power mode path loss */
+ /* LID:NVRAM_EF_CL1_MAIN_RX_PATH_LOSS_LPM_BAND_X_LID */
+ CL1D_RF_RX_PATH_LOSS_COMP_T RxPLossLPM;
+} Cl1TstRxCalDataT;
+
+/** define Rx calibration data setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* CDMA Band Class to turn on */
+ kal_uint8 BandClass;
+
+ /* path bitmap, bit0--main, bit1--diversity, bit2--SHDR */
+ kal_uint8 PathBmp;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* Rx calibration data */
+ Cl1TstRxCalDataT RxCalData;
+
+} Cl1TstRxCalDataSetCmdT;
+
+/** define Rx calibration data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxCalDataSetRspT;
+
+/** define Rx calibration data getting command structure */
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* path bitmap, bit0--main, bit1--diversity, bit2--SHDR */
+ kal_uint8 PathBmp;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstRxCalDataGetCmdT;
+
+/** define Rx calibration data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Rx calibration data */
+ Cl1TstRxCalDataT RxCalData;
+
+} Cl1TstRxCalDataGetRspT;
+
+/** define Tx calibration data structure */
+typedef struct
+{
+ /* PA context */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_CONTEXT_XX_BAND_X_LID */
+ CL1D_RF_TX_APT_PA_CONTEXT_T TxAptPaCtx;
+
+ /* PA gain temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_TX_APT_PA_GAIN_COMP_XX_BAND_X_LID */
+ CL1D_RF_TX_APT_PA_GAIN_COMP_T TxAptPaGainComp;
+
+ /* Coupler loss temperature and frequency compensation, Q5 dB */
+ /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_COMP_XX_BAND_X_LID */
+ CL1D_RF_DET_COUPLE_LOSS_COMP_T CplLossComp;
+
+ /* Coupler loss, Q5 dB */
+ /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_XX_BAND_X_LID */
+ CL1D_RF_DET_COUPLE_LOSS_T CplLoss;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+} Cl1TstTxCalDataT;
+
+/** define Tx calibration data setting command structure */
+typedef struct
+{
+ /* update NVRAM flag, 0: do not update, 1: update */
+ kal_uint8 UpdateNvram;
+
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* Tx calibration data */
+ Cl1TstTxCalDataT TxCalData;
+
+} Cl1TstTxCalDataSetCmdT;
+
+/** define Tx calibration data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstTxCalDataSetRspT;
+
+/** define Tx calibration data getting command structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstTxCalDataGetCmdT;
+
+/** define Tx calibration data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Tx calibration data */
+ Cl1TstTxCalDataT TxCalData;
+
+} Cl1TstTxCalDataGetRspT;
+
+#ifndef __MD93__
+/** define Lna calibration power point getting command structure */
+typedef struct
+{
+ /* Band Num to cal */
+ kal_uint8 BandNum;
+
+ /* CDMA Band Class to turn on*/
+ kal_uint8 BandClass[RF_Band_NUM_MAX];
+
+ /* Reserved */
+ kal_uint16 Reserved;
+
+} Cl1TstLnaCalPwrPointGetCmdT;
+
+/** define Lna calibration power point and range confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Lna calibration power point and range */
+ CL1D_RF_RX_LNA_CALIBRATION_POWER_AND_RANGE_T LnaCalPwrPoint[RF_Band_NUM_MAX];
+
+} Cl1TstLnaCalPwrPointGetRspT;
+#endif
+
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+/** define Rx Agc Gain getting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType;
+ CL1D_RF_PATH_E Path;
+}Cl1TstRxGainGetCmdT;
+
+/** define Rx Agc Gain getting command structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ CL1D_RF_AGC_ALGO_RESULT_QUERY_T RxGainPara;
+}Cl1TstRxGainGetRspT;
+
+/** define Tx Agc Gain getting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType;
+}Cl1TstTxGainGetCmdT;
+
+/** define Tx Agc Gain getting command structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ CL1D_RF_TPC_ALGO_RESULT_QUERY_T TxGainPara;
+}Cl1TstTxGainGetRspT;
+
+/** define SPI data setting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType; // is need add Reserved?
+ kal_uint32 BpiData;
+} Cl1TstSetBpiDataCmdT;
+
+/** define SPI data setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetBpiDataRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ CL1D_RF_RAT_TYPE_E RatType;
+} Cl1TstGetBpiDataCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* SPI data */
+ kal_uint32 BpiData;
+} Cl1TstGetBpiDataRspT;
+
+/** define Rx AGC configuration command structure for RF test and traditional calibration */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitMap;
+
+ /* 0: fixed gain, 1:manual */
+ kal_uint8 TestMode;
+
+ /* C2K RX AGC FSM type, 0:FAST, 1:STEADY, 2:ICS, 3:CAL, 4:FIX_GAIN*/
+ kal_uint8 AgcFsm;
+
+ /* 0: high power mode, 1: low power mode */
+ kal_uint8 PwrMode;
+
+ /* 0: stage 0, 1: stage 1....5: stage 5 */
+ kal_uint8 LnaMode;
+
+ /** PGA index of CL1D_RF_PGA_INDEX_E */
+ kal_uint8 PgaIndex;
+
+ /* indicate which parameters to be fixed, bit0: rf gain, bit1: rf DC, bit2: digital gain, bit3: digital DC */
+ kal_uint8 AgcDcFixBmp;
+
+ /* digital gain in DB2 format, S5.5*/
+ kal_uint32 DigGain;
+} Cl1TstRxAgcFixManualConfigCmdT;
+
+/** define Rx AGC configuration confirm structure for RF test and traditional calibration */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAgcFixManualConfigRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ /* Rat,0:1x,1:DO */
+ kal_uint32 RatType;
+ /* PathBitMap*/
+ kal_uint32 PathBmp;
+ /* Dump node*/
+ kal_uint32 DumpNode;
+ /* IQ number*/
+ kal_uint32 IqNum;
+} Cl1TstRxDfeIqDumpCfgCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /*Total block size */
+ kal_uint32 BufferSize;
+ /*bock number */
+ kal_uint32 BlockNum;
+} Cl1TstRxDfeIqDumpCfgRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ /* Rat,0:1x,1:DO */
+ kal_uint32 RatType;
+ /** [in] - BB or RF or MRX**/
+ kal_uint32 DumpSel;
+ /** [in] - For TXDFE_BB:0:bb input; 1:firad input; 2:src input; 3:cic1x input; 4:cic2x input; 5:nco input; 6:nco ouput
+ For TXDFE_RF:0:gain_bb; 1:dpd comp; 2:gain bkf; 3:ga comp; 4:ad comp; 5:main phase r delay; 6:main dc; 7:main fi; 8:main fd**/
+ kal_uint32 NodeSel;
+ /* IQ number*/
+ kal_uint32 IqNum;
+} Cl1TstTxDfeIqDumpCfgCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /*Total block size */
+ kal_uint32 BufferSize;
+ /*bock number */
+ kal_uint32 BlockNum;
+} Cl1TstTxDfeIqDumpCfgRspT;
+
+/** define SPI data getting command structure */
+typedef struct
+{
+ /* Rat,0:1x,1:DO */
+ kal_uint32 RatType;
+ /** [in] - 0:TXK_REF; 1:TXDFE_BB; 2:TXDFE_RF; 3:TXDFE_ET; 4:TXK_DET**/
+ kal_uint32 DumpSel;
+ /** [in] - For TXK DET: 0:det afifo out; 1:det cic out; 2:det out;
+ For TXK REF: 0:ref scale out; 1:ref i delay out; 2:ref f delay out; 3:ref dcm out**/
+ kal_uint32 NodeSel;
+ /* IQ number*/
+ kal_uint32 IqNum;
+} Cl1TstTxkDfeIqDumpCfgCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /*Total block size */
+ kal_uint32 BufferSize;
+ /*bock number */
+ kal_uint32 BlockNum;
+} Cl1TstTxkDfeIqDumpCfgRspT;
+
+typedef struct
+{
+ kal_uint32 BlockIndex;
+} Cl1TstRxTxDfeIqDumpQryCmdT;
+
+/** define SPI data getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+ /* last block flag */
+ kal_uint16 LastBlockInd;
+ /* partial block size */
+ kal_uint16 PtBlockSize;
+ /* block offset */
+ kal_uint32 BlockOffset;
+ /* Data buffer*/
+ kal_uint32 Data[CL1TST_RX_TX_IQ_DUMP_NUM];
+} Cl1TstRxTxDfeIqDumpQryRspT;
+#endif
+
+/** define FHC start common data structure */
+typedef struct
+{
+ /* Tx RX delay for FHC, unit us (> 10us) */
+ kal_uint16 TxRxDelay;
+
+ /* Tx step length, unit us (>= 1000us and <= 20000 us) */
+ kal_uint16 TxStepLength;
+
+ /* Tx retune length, unit us (>= 500us) */
+ kal_uint16 TxRetuLength;
+
+ /* RF mode switch length, unit us, the integer multiple of step length */
+ kal_uint16 RfMSwhLength;
+
+ /* Rx step length, unit us (>= 1000us and <= 20000 us) */
+ kal_uint16 RxStepLength;
+
+ /* Rx retune length, unit us (>= 500us) */
+ kal_uint16 RxRetuLength;
+
+} Cl1TstFhcCommonT;
+
+/** define Tx calibration element structure */
+typedef struct
+{
+ /* 0: 1xRTT, 1: EVDO */
+ kal_uint8 RfMode;
+
+ /* Step indication, 0: next step is normal step,
+ 1: next step is retune step,
+ 2: the current step is the last step,
+ 3: next step is RF mode switch step
+ */
+ kal_uint8 StepInd;
+
+ /* CDMA band class */
+ kal_uint8 BandClass;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+ /* CDMA channel */
+ kal_uint16 ChanNum;
+
+ /* RF calibration power points, dBm, Q5 */
+ kal_int16 TxPwr;
+
+} Cl1TstFhcTxElementT;
+
+/** define Rx calibration element structure */
+typedef struct
+{
+ /* Step indication, 0: next step is normal step,
+ 1: next step is retune step,
+ 2: the current step is the last step
+ */
+ kal_uint8 StepInd;
+
+ /* CDMA band class */
+ kal_uint8 BandClass;
+
+ /* CDMA channel */
+ kal_uint16 ChanNum;
+
+ /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
+ kal_uint8 PathBitmap;
+
+ /* Power mode, 0: high power mode, 1: low power mode */
+ kal_uint8 PwrMode;
+
+ /* LNA mode, 0~7 */
+ kal_uint8 LnaMode;
+
+ /* Reserved */
+ kal_uint8 Reserved;
+
+} Cl1TstFhcRxElementT;
+
+/** define FHC calibration start command structure */
+typedef struct
+{
+ /* FHC calibration common data */
+ Cl1TstFhcCommonT CommonData;
+
+ /* Reserved */
+ kal_uint16 Reserved1;
+
+ /* Tx calibration elements number (1~1000) */
+ kal_uint16 TxElementNum;
+
+ /* Tx calibration elements */
+ Cl1TstFhcTxElementT TxElement[CL1TST_FHC_TX_ELEMENT_NUM];
+
+ /* Reserved */
+ kal_uint16 Reserved2;
+
+ /* Rx calibration elements number (1~1000) */
+ kal_uint16 RxElementNum;
+
+ /* Rx calibration elements */
+ Cl1TstFhcRxElementT RxElement[CL1TST_FHC_RX_ELEMENT_NUM];
+
+} Cl1TstFhcStartCmdT;
+
+/** define FHC report result structure */
+typedef struct
+{
+ /* power detect result number */
+ kal_uint16 PdetNum;
+
+ /* RSSI number */
+ kal_uint16 RssiNum;
+
+ /* power detect result, unit is Q5 dBm */
+ kal_int16 Pdet[CL1TST_FHC_TX_ELEMENT_NUM];
+
+ /* Main antenna RSSI, unit is Q5 dBm */
+ kal_int16 RssiMain[CL1TST_FHC_RX_ELEMENT_NUM];
+
+ /* Diversity antenna RSSI, unit is Q5 dBm */
+ kal_int16 RssiDiv[CL1TST_FHC_RX_ELEMENT_NUM];
+} Cl1TstFhcRptDataT;
+
+/** define FHC calibration start confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* FHC report result */
+ Cl1TstFhcRptDataT RptData;
+} Cl1TstFhcStartRspT;
+
+/** define 1xrtt NST Relation command and confirm structure */
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+ /* CDMA Walsh Code Channel*/
+ kal_uint8 CodeChan;
+ /* CDMA Radio configuration,1 is RC1, 2 is RC2 Etc*/
+ kal_uint8 RadioConfig;
+} Cl1TstNstPowerUpCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstPowerUpRspT;
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+ /* Number of Fer cacualte Frames*/
+ kal_uint16 NumFrames;
+ /* Flag of Enable AFC Config*/
+ kal_bool EnableAFC;
+} Cl1TstNstTchFerCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+ kal_uint16 BadFrames;
+ kal_uint16 TotalFrames;
+} Cl1TstNstTchFerCfgRspT;
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+ /* Tx Power Level ,unint is Q6*/
+ kal_uint16 TxPwrQ6;
+} Cl1TstNstTxPwrMeasCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstTxPwrMeasCfgRspT;
+
+typedef struct
+{
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass;
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel;
+} Cl1TstNstRxPwrMeasCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+ /* Current PN Offset */
+ kal_uint16 PnOffset;
+ /* Current Aset Pilot Strength */
+ kal_int16 Strength;
+ /* Current Main Ant Rx Power,unit is Q5 */
+ kal_int16 MainRxPwrQ5;
+ /* Current Div Ant Rx Power,unit is Q5 */
+ kal_int16 DivRxPwrQ5;
+} Cl1TstNstRxPwrMeasCfgRspT;
+
+typedef struct
+{
+ /* Total Count of NST List */
+ kal_uint8 Count;
+ /* Num of frame offset */
+ kal_uint8 Offset[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Walsh Code Channel*/
+ kal_uint8 CodeChan[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Radio configuration,1 is RC1, 2 is RC2 Etc*/
+ kal_uint8 RadioConfig[CL1TST_NST_MAX_LIST_NUM];
+
+ /* Number of Fer cacualte Frames*/
+ kal_uint16 NumFrames[CL1TST_NST_MAX_LIST_NUM];
+ /* Count of Meas Tx Pwr Level for Per Freq Chan*/
+ kal_uint8 TxPwrCount[CL1TST_NST_MAX_LIST_NUM];
+ /* Meas Tx Pwr Level for Per Freq Chan*/
+ kal_uint16 TxPwrLevelQ6[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_TX_PWR_COUNT];
+ /* Count of Meas Rx Pwr Level for Per Freq Chan*/
+ kal_uint8 RxPwrCount[CL1TST_NST_MAX_LIST_NUM];
+} Cl1TstNstListSetCfgCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+ /* Total Count of NST List */
+ kal_uint8 Count;
+ /* Index of list */
+ kal_uint8 Index[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Band Class to turn on*/
+ kal_uint16 BandClass[CL1TST_NST_MAX_LIST_NUM];
+ /* CDMA Freq Channel to turn on*/
+ kal_uint16 Channel[CL1TST_NST_MAX_LIST_NUM];
+ /* Number of Bad Frames for Per Freq Chan */
+ kal_uint8 BadFrames[CL1TST_NST_MAX_LIST_NUM];
+ /* Number of Total Meas Frames for Per Freq Chan */
+ kal_uint8 TotalFrames[CL1TST_NST_MAX_LIST_NUM];
+ /* Current Main Ant Rx Power,unit is Q5 */
+ kal_int16 MainRxPwrQ5[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_RX_PWR_COUNT];
+ /* Current Div Ant Rx Power,unit is Q5 */
+ kal_int16 DivRxPwrQ5[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_RX_PWR_COUNT];
+} Cl1TstNstListSetCfgRspT;
+
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstNstEnterTestModeCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstEnterTestModeRspT;
+
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstNstExitTestModeCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* Nst Cmd Result status */
+ Cl1TstNstCmdStatusE NstStatus;
+} Cl1TstNstExitTestModeRspT;
+
+/** define enter factory mode request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstFactoryModeReqCmdT;
+
+/** define enter factory mode confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstFactoryModeReqRspT;
+
+/** define enter normal mode request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstNormalModeReqCmdT;
+
+/** define enter normal mode confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstNormalModeReqRspT;
+
+typedef struct
+{
+ kal_uint32 Meid_L;
+ kal_uint32 Meid_H;
+} Cl1TstSetMeidCmdT;
+
+/** define MEID setting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstSetMeidRspT;
+
+/** define MEID getting command structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstGetMeidCmdT;
+
+/** define MEID getting confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+
+ /* MEID data */
+ kal_uint32 Meid_L;
+ kal_uint32 Meid_H;
+
+ /* ESN data */
+ kal_uint32 Esn;
+} Cl1TstGetMeidRspT;
+
+/** define UBIN init request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstUbinInitCmdT;
+
+/** define UBIN init confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstUbinInitRspT;
+
+/** define UBIN De init request structure */
+typedef struct
+{
+ kal_uint32 Reserved;
+} Cl1TstUbinDeInitCmdT;
+
+/** define UBIN Deinit confirm structure */
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstUbinDeInitRspT;
+
+
+
+typedef struct
+{
+ /* Ant Test Mode Set:0 means disable test Mode,1 means Main Rx Only,and
+ * 2 means Div Rx Only Mode,3 means Dual Mode(Main+Div).*/
+ kal_uint32 AntTestMode;
+} Cl1TstRxAntTestModeSetCmdT;
+
+typedef struct
+{
+ /* Request execute status */
+ Cl1TstReqStatusE Status;
+} Cl1TstRxAntTestModeSetRspT;
+
+
+#if 0
+#ifdef MTK_PLT_ON_PC_IT
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+/* C2K meta interface command union */
+typedef union
+{
+ Cl1TstGetRfPlatInfoCmdT GetRfPlatInfoCmd; // for CL1TST_CMD_GET_RF_PLATFORM_INFO
+ Cl1TstRfdTestModeReqCmdT RfdTestModeReqCmd; // for CL1TST_CMD_RFD_ENTER_TEST_MODE
+ Cl1TstRfdInitReqCmdT RfdInitReqCmd; // for CL1TST_CMD_RFD_INIT_REQ
+ Cl1TstSetMipiCodeWordCmdT SetMipiCodeWordCmd; // for CL1TST_CMD_SET_MIPI_CW
+ Cl1TstGetMipiCodeWordCmdT GetMipiCodeWordCmd; // for CL1TST_CMD_GET_MIPI_CW
+ Cl1TstSetSpiDataCmdT SetSpiDataCmd; // for CL1TST_CMD_SET_SPI_DATA
+ Cl1TstGetSpiDataCmdT GetSpiDataCmd; // for CL1TST_CMD_GET_SPI_DATA
+ Cl1TstTransmitCtrlCmdT TransmitCtrlCmd; // for CL1TST_CMD_TRANSMIT_CTRL
+ Cl1TstReceiveCtrlCmdT ReceiveCtrlCmd; // for CL1TST_CMD_RECEIVE_CTRL
+ Cl1TstAfcConfigCmdT AfcConfigCmd; // for CL1TST_CMD_AFC_CONFIG
+ Cl1TstTxAgcConfigCmdT TxAgcConfigCmd; // for CL1TST_CMD_TX_AGC_CONFIG
+ Cl1TstTxPowerQueryCmdT TxPowerQueryCmd; // for CL1TST_CMD_TX_POWER_QUERY
+ Cl1TstRxAgcConfigCmdT RxAgcConfigCmd; // for CL1TST_CMD_RX_AGC_CONFIG
+ Cl1TstRxRssiQueryCmdT RxRssiQueryCmd; // for CL1TST_CMD_RX_RSSI_QUERY
+ Cl1TstAfcCalDataSetCmdT AfcCalDataSetCmd; // for CL1TST_CMD_AFC_CAL_DATA_SET
+ Cl1TstAfcCalDataGetCmdT AfcCalDataGetCmd; // for CL1TST_CMD_AFC_CAL_DATA_GET
+ Cl1TstRxCalDataSetCmdT RxCalDataSetCmd; // for CL1TST_CMD_RX_CAL_DATA_SET
+ Cl1TstRxCalDataGetCmdT RxCalDataGetCmd; // for CL1TST_CMD_RX_CAL_DATA_GET
+ Cl1TstTxCalDataSetCmdT TxCalDataSetCmd; // for CL1TST_CMD_TX_CAL_DATA_SET
+ Cl1TstTxCalDataGetCmdT TxCalDataGetCmd; // for CL1TST_CMD_TX_CAL_DATA_GET
+#ifndef __MD93__
+ Cl1TstLnaCalPwrPointGetCmdT LnaCalPwrPointGetCmd; // for CL1TST_CMD_RX_LNA_PWR_RANGE_GET
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+ Cl1TstRxGainGetCmdT RxGainGetCmd; // for CL1TST_CMD_RX_GAIN_GET
+ Cl1TstTxGainGetCmdT TxGainGetCmd; // for CL1TST_CMD_TX_GAIN_GET
+ Cl1TstSetBpiDataCmdT SetBpiDataCmd; // for CL1TST_CMD_SET_BPI_DATA
+ Cl1TstGetBpiDataCmdT GetBpiDataCmd; // for CL1TST_CMD_GET_BPI_DATA
+ Cl1TstRxAgcFixManualConfigCmdT RxAgcFixManualConfigCmd; // for CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG
+ Cl1TstRxDfeIqDumpCfgCmdT RxDfeIqDumpCfgCmd; // for CL1TST_CMD_RXDFE_IQ_DUMP_CFG
+ Cl1TstTxDfeIqDumpCfgCmdT TxDfeIqDumpCfgCmd; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
+ Cl1TstTxkDfeIqDumpCfgCmdT TxkDfeIqDumpCfgCmd; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
+ Cl1TstRxTxDfeIqDumpQryCmdT RxTxDfeIqDumpQryCmd; // for CL1TST_CMD_RXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY
+#endif
+
+ Cl1TstFhcStartCmdT FhcStartCmd; // for CL1TST_CMD_FHC_START
+ Cl1TstFactoryModeReqCmdT FactoryModeReqCmd; // for CL1TST_CMD_FACTORY_MODE_REQ
+ Cl1TstNormalModeReqCmdT NormalModeReqCmd; // for CL1TST_CMD_NORMAL_MODE_REQ
+ Cl1TstSetMeidCmdT SetMeidCmd; // for CL1TST_CMD_SET_MEID
+ Cl1TstGetMeidCmdT GetMeidCmd; // for CL1TST_CMD_GET_MEID
+ Cl1TstUbinInitCmdT UbinInitCmd; // for CL1TST_CMD_UBIN_INIT
+ Cl1TstUbinDeInitCmdT UbinDeInitCmd; // for CL1TST_CMD_UBIN_DEINIT
+
+ Cl1TstNstPowerUpCmdT NstPowerUpCmd;
+ Cl1TstNstTchFerCfgCmdT NstTchFerCfgCmd;
+ Cl1TstNstTxPwrMeasCfgCmdT NstTxPwrMeasCfgCmd;
+
+ Cl1TstNstRxPwrMeasCfgCmdT NstRxPwrMeasCfgCmd;
+ Cl1TstNstListSetCfgCmdT NstListSetCfgCmd;
+ Cl1TstNstEnterTestModeCmdT NstEnterTestModeCmd;
+ Cl1TstNstExitTestModeCmdT NstExitTestModeCmd;
+
+ Cl1TstRxAntTestModeSetCmdT RxAntTestModeSetCmd;
+}Cl1TstCmdParam;
+
+/* C2K meta interface confirm union */
+typedef union
+{
+ Cl1TstGetRfPlatInfoRspT GetRfPlatInfoRsp; // for CL1TST_CMD_GET_RF_PLATFORM_INFO
+ Cl1TstRfdTestModeReqRspT RfdTestModeReqRsp; // for CL1TST_CMD_RFD_EXIT_TEST_MODE
+ Cl1TstRfdInitReqRspT RfdInitReqRsp; // for CL1TST_CMD_RFD_INIT_REQ
+ Cl1TstSetMipiCodeWordRspT SetMipiCodeWordRsp; // for CL1TST_CMD_SET_MIPI_CW
+ Cl1TstGetMipiCodeWordRspT GetMipiCodeWordRsp; // for CL1TST_CMD_GET_MIPI_CW
+ Cl1TstSetSpiDataRspT SetSpiDataRsp; // for CL1TST_CMD_SET_SPI_DATA
+ Cl1TstGetSpiDataRspT GetSpiDataRsp; // for CL1TST_CMD_GET_SPI_DATA
+ Cl1TstTransmitCtrlRspT TransmitCtrlRsp; // for CL1TST_CMD_TRANSMIT_CTRL
+ Cl1TstReceiveCtrlRspT ReceiveCtrlRsp; // for CL1TST_CMD_RECEIVE_CTRL
+ Cl1TstAfcConfigRspT AfcConfigRsp; // for CL1TST_CMD_AFC_CONFIG
+ Cl1TstTxAgcConfigRspT TxAgcConfigRsp; // for CL1TST_CMD_TX_AGC_CONFIG
+ Cl1TstTxPowerQueryRspT TxPowerQueryRsp; // for CL1TST_CMD_TX_POWER_QUERY
+ Cl1TstRxAgcConfigRspT RxAgcConfigRsp; // for CL1TST_CMD_RX_AGC_CONFIG
+ Cl1TstRxRssiQueryRspT RxRssiQueryRsp; // for CL1TST_CMD_RX_RSSI_QUERY
+ Cl1TstAfcCalDataSetRspT AfcCalDataSetRsp; // for CL1TST_CMD_AFC_CAL_DATA_SET
+ Cl1TstAfcCalDataGetRspT AfcCalDataGetRsp; // for CL1TST_CMD_AFC_CAL_DATA_GET
+ Cl1TstRxCalDataSetRspT RxCalDataSetRsp; // for CL1TST_CMD_RX_CAL_DATA_SET
+ Cl1TstRxCalDataGetRspT RxCalDataGetRsp; // for CL1TST_CMD_RX_CAL_DATA_GET
+ Cl1TstTxCalDataSetRspT TxCalDataSetRsp; // for CL1TST_CMD_TX_CAL_DATA_SET
+ Cl1TstTxCalDataGetRspT TxCalDataGetRsp; // for CL1TST_CMD_TX_CAL_DATA_GET
+#ifndef __MD93__
+ Cl1TstLnaCalPwrPointGetRspT LnaCalPwrPointGetRsp; // for CL1TST_CMD_RX_LNA_PWR_RANGE_GET
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+ Cl1TstRxGainGetRspT RxGainGetRsp; // for CL1TST_CMD_RX_GAIN_GET
+ Cl1TstTxGainGetRspT TxGainGetRsp; // for CL1TST_CMD_TX_GAIN_GET
+ Cl1TstSetBpiDataRspT SetBpiDataRsp; // for CL1TST_CMD_SET_BPI_DATA
+ Cl1TstGetBpiDataRspT GetBpiDataRsp; // for CL1TST_CMD_GET_BPI_DATA
+ Cl1TstRxAgcFixManualConfigRspT RxAgcFixManualConfigRsp; // for CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG
+ Cl1TstRxDfeIqDumpCfgRspT RxDfeIqDumpCfgRsp; // for CL1TST_CMD_RXDFE_IQ_DUMP_CFG
+ Cl1TstTxDfeIqDumpCfgRspT TxDfeIqDumpCfgRsp; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
+ Cl1TstTxkDfeIqDumpCfgRspT TxkDfeIqDumpCfgRsp; // for CL1TST_CMD_TXkDFE_IQ_DUMP_CFG
+ Cl1TstRxTxDfeIqDumpQryRspT RxTxDfeIqDumpQryRsp; // for CL1TST_CMD_RXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXkDFE_IQ_DUMP_QUERY
+#endif
+
+ Cl1TstFhcStartRspT FhcStartRsp; // for CL1TST_CMD_FHC_START
+ Cl1TstFactoryModeReqRspT FactoryModeReqRsp; // for CL1TST_CMD_FACTORY_MODE_REQ
+ Cl1TstNormalModeReqRspT NormalModeReqRsp; // for CL1TST_CMD_NORMAL_MODE_REQ
+ Cl1TstSetMeidRspT SetMeidRsp; // for CL1TST_CMD_SET_MEID
+ Cl1TstGetMeidRspT GetMeidRsp; // for CL1TST_CMD_GET_MEID
+ Cl1TstUbinInitRspT UbinInitRsp; // for CL1TST_CMD_UBIN_INIT
+ Cl1TstUbinDeInitRspT UbinDeInitRsp; // for CL1TST_CMD_UBIN_DEINIT
+
+ Cl1TstNstPowerUpRspT NstPowerUpRsp;
+ Cl1TstNstTchFerCfgRspT NstTchFerCfgRsp;
+ Cl1TstNstTxPwrMeasCfgRspT NstTxPwrMeasCfgRsp;
+
+ Cl1TstNstRxPwrMeasCfgRspT NstRxPwrMeasCfgRsp;
+ Cl1TstNstListSetCfgRspT NstListSetCfgRsp;
+ Cl1TstNstEnterTestModeRspT NstEnterTestModeRsp;
+ Cl1TstNstExitTestModeRspT NstExitTestModeRsp;
+
+ Cl1TstRxAntTestModeSetRspT RxAntTestModeSetRsp;
+}Cl1TstRspParam;
+
+/* FT peer buffer request structure */
+typedef struct
+{
+ Cl1TstCmdTypeE Type;
+ Cl1TstCmdParam Para;
+}FT_CRF_PEER_CMD;
+
+/* FT peer buffer confirm structure */
+typedef struct
+{
+ Cl1TstCmdTypeE Type;
+ Cl1TstRspParam Para;
+}FT_CRF_PEER_RSP;
+
+/* struct definition for FT request & confirm */
+typedef FT_H FT_CRF_LOCAL_PARA;
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+extern void CL1TST_ALLOC_MSG_CC(ilm_struct* ilm_ptr, kal_uint32 local_param_size, kal_uint32 peer_pdu_size);
+extern void CL1TST_SEND_MSG_TO_FT(ilm_struct *ilm_ptr);
+extern void CL1TST_BackupFtHeader(kal_uint16 taken);
+extern void CL1TST_SetFtHeader(FT_CRF_LOCAL_PARA *rsp_loc);
+
+extern void Cl1TstRfdTestModeReqPro(Cl1TstRfdTestModeReqCmdT *Ptr);
+
+extern void Cl1TstTxPathOnTimingCalc(kal_uint8 RfMode,
+ kal_uint16 RaDly,
+ kal_uint32 *TxStartOfst,
+ kal_uint32 *RxStartOfst);
+
+extern void Cl1TstTxPathOffTimingCalc(kal_uint8 RfMode,
+ kal_uint32 *TxStartOfst,
+ kal_uint32 *RxStartOfst);
+
+extern void Cl1TstTxPathOn1xSigPro(kal_uint8 Action, Cl1Tst1xSigParaT *Ptr, kal_bool FlagL1d);
+
+extern kal_uint8 Cl1TstDoActionQuery(kal_uint8 Action);
+
+extern void Cl1TstTransmitCtrlPathPro(Cl1TstTransmitCtrlCmdT *Ptr);
+extern void Cl1TstTransmitCtrlSigPro(Cl1TstTransmitCtrlCmdT *Ptr, kal_bool L1dFlag);
+extern void Cl1TstReceiveCtrlPathPro(Cl1TstReceiveCtrlCmdT *Ptr);
+extern void Cl1TstAfcConfigPro(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstAfcConfigPro(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstTxAgcConfigPro(Cl1TstTxAgcConfigCmdT *Ptr);
+extern void Cl1TstRxAgcConfigPro(Cl1TstRxAgcConfigCmdT *Ptr);
+extern void CltstAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
+extern void CltstAfcCalDataGet(CL1D_RF_AFC_DATA_T *Ptr);
+extern void CltstRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
+extern void CltstRxCalDataGet(Cl1TstRxCalDataGetCmdT *GetPtr, Cl1TstRxCalDataT *DatPtr);
+extern void CltstTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
+extern void CltstTxCalDataGet(Cl1TstTxCalDataGetCmdT *GetPtr, Cl1TstTxCalDataT *DatPtr);
+extern void Cl1tstTxDfeBbToneCfg(kal_uint32 CfgData);
+extern void Cl1TstRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr,
+ CL1D_RF_AGC_RSSI_QUERY_T *AdsPtr);
+extern void Cl1TstRxRssiQueryPduFill(Cl1TstRxRssiQueryCmdT *Ptr,
+ CL1D_RF_AGC_RSSI_QUERY_T *AdsPtr,
+ Cl1TstRxRssiQueryRspT *RspPdu);
+extern void Cl1TstMetaIfGetRfPlatInfo(Cl1TstGetRfPlatInfoCmdT *Ptr);
+extern void Cl1TstMetaIfRfdTestModeReq(Cl1TstRfdTestModeReqCmdT *Ptr);
+extern void Cl1TstMetaIfRfdInitReq(Cl1TstRfdInitReqCmdT *Ptr);
+extern void Cl1TstMetaIfSetMipiCodeWord(Cl1TstSetMipiCodeWordCmdT *Ptr);
+extern void Cl1TstMetaIfGetMipiCodeWord(Cl1TstGetMipiCodeWordCmdT *Ptr);
+extern void Cl1TstMetaIfSetSpiData(Cl1TstSetSpiDataCmdT *Ptr);
+extern void Cl1TstMetaIfGetSpiData(Cl1TstGetSpiDataCmdT *Ptr);
+extern void Cl1TstMetaIfTransmitCtrl(Cl1TstTransmitCtrlCmdT *Ptr);
+extern void Cl1TstMetaIfReceiveCtrl(Cl1TstReceiveCtrlCmdT *Ptr);
+extern void Cl1TstMetaIfAfcConfig(Cl1TstAfcConfigCmdT *Ptr);
+extern void Cl1TstMetaIfTxAgcConfig(Cl1TstTxAgcConfigCmdT *Ptr);
+extern void Cl1TstMetaIfTxPowerQuery(Cl1TstTxPowerQueryCmdT *Ptr);
+extern void Cl1TstMetaIfRxAgcConfig(Cl1TstRxAgcConfigCmdT *Ptr);
+extern void Cl1TstMetaIfRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr);
+extern void Cl1TstMetaIfAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
+extern void Cl1TstMetaIfAfcCalDataGet(Cl1TstAfcCalDataGetCmdT *Ptr);
+extern void Cl1TstMetaIfRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
+extern void Cl1TstMetaIfRxCalDataGet(Cl1TstRxCalDataGetCmdT *Ptr);
+extern void Cl1TstMetaIfTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
+extern void Cl1TstMetaIfTxCalDataGet(Cl1TstTxCalDataGetCmdT *Ptr);
+#ifndef __MD93__
+extern void Cl1TstMetaIfLnaCalPwrPointGet(Cl1TstLnaCalPwrPointGetCmdT *Ptr);
+#endif
+#if (!defined(__MD93__)) && (!defined(__MD95__))
+extern void Cl1TstMetaIfRxGainGet(Cl1TstRxGainGetCmdT *Ptr);
+extern void Cl1TstMetaIfTxGainGet(Cl1TstTxGainGetCmdT *Ptr);
+extern void Cl1TstMetaIfSetBpiData(Cl1TstSetBpiDataCmdT *Ptr);
+extern void Cl1TstMetaIfGetBpiData(Cl1TstGetBpiDataCmdT *Ptr);
+extern void Cl1TstRxAgcFixManualConfigPro(Cl1TstRxAgcFixManualConfigCmdT *Ptr);
+extern void Cl1TstMetaIfRxAgcFixManualConfig(Cl1TstRxAgcFixManualConfigCmdT *Ptr);
+extern void Cl1TstMetaIfRxDfeIqDumpCfg(Cl1TstRxDfeIqDumpCfgCmdT *Ptr);
+extern void Cl1TstMetaIfTxDfeIqDumpCfg(Cl1TstTxDfeIqDumpCfgCmdT *Ptr);
+extern void Cl1TstMetaIfTxkDfeIqDumpCfg(Cl1TstTxkDfeIqDumpCfgCmdT *Ptr);
+extern void Cl1TstMetaIfRxTxDfeIqDumpQry(Cl1TstRxTxDfeIqDumpQryCmdT *Ptr);
+#endif
+extern void Cl1TstMetaIfFhcStart(Cl1TstFhcStartCmdT *Ptr);
+extern void Cl1tstMetaIfFactoryModeReq(Cl1TstFactoryModeReqCmdT * Ptr);
+extern void Cl1tstMetaIfNormalModeReq(Cl1TstNormalModeReqCmdT * Ptr);
+extern void Cl1TstMetaIfSetMeid(Cl1TstSetMeidCmdT *Ptr);
+extern void Cl1TstMetaIfGetMeid(Cl1TstGetMeidCmdT *Ptr);
+extern void Cl1TstMetaIfUbinInit(Cl1TstUbinInitCmdT *Ptr);
+extern void Cl1TstMetaIfUbinDeInit(Cl1TstUbinDeInitCmdT *Ptr);
+extern void Cl1TstMetaIfTargetAssert();
+extern kal_uint32 CltstNvOperBmpGet(kal_uint8 UpdateNvram);
+extern kal_bool Cl1tstDoTrigTxSlpRsmDlyQuery();
+extern void Cl1tstDoTrigTxSlpRsmDlyClear();
+
+#endif /* _CL1TST_META_IF_H_ */
+