[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/l1/cl1/common/cph1xflrake.h b/mcu/interface/l1/cl1/common/cph1xflrake.h
new file mode 100644
index 0000000..ff37a35
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cph1xflrake.h
@@ -0,0 +1,463 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XFLRAKE_H_
+#define _CPH1XFLRAKE_H_
+
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+#define D2BIF_WORK_AROUND_MORE_ANT 1
+
+//#define D2BIF_WORK_AROUND_T2_DISD2BIF 1
+
+
+#define SECTOR_NUM_1X 6
+#define FINGER_NUM_1X 8
+
+#define SPEED_UPPERROUND 0xff
+
+#define DEFAULT_T1_PCG (0)
+#define DEFAULT_T6_PCG (0)
+#define DEFAULT_T7_PCG (15)
+#if defined(__MD93__)||defined(__MD95__)
+#define BIGRAM_BASE_ADDR_L1 0xa9000000
+#endif
+
+#ifdef __MD97__
+#define BIGRAM_BASE_ADDR_L1 0xab000000
+#endif
+/*Rake Bootup*/
+typedef enum
+{
+ BOOT_UP_WCDMA_MODE = 0,
+ BOOT_UP_C2K_MODE
+} CphBootUpMode;
+
+
+/*Rake Generate*/
+typedef enum
+{
+ B2R_MODE_WCDMA,
+ B2R_MODE_C1X,
+ B2R_MODE_CDO,
+ B2R_MODE_SHDR
+} Cph1xB2RifMode;
+
+typedef enum
+{
+ D2B_MODE_WCDMA,
+ D2B_MODE_C1X,
+ D2B_MODE_CDO,
+ D2B_MODE_QLIC
+} Cph1xD2BifMode;
+
+
+/*Rake Generate*/
+typedef enum
+{
+ CPH_NULL_STATE = 0,
+ CPH_SYNC_STATE = 1,
+ CPH_IDLE_STATE = 2,
+ CPH_CONNECTED_STATE = 4
+} Cph1xL1dState;
+
+typedef enum
+{
+ DISABLE_MODE,
+ RTT_MODE,
+ EVDO_MODE,
+ SHDR_STATE
+} CphL1dMode;
+
+typedef enum
+{
+ ANT_MAIN_ONLY,
+ ANT_DIV_ONLY,
+ ANT_DIVERSITY,
+ ANT_SHDR,
+ ANT_DISABLE
+} CphAntMod;
+
+
+typedef enum
+{
+ CH_NULL = 0,
+ CH_PCH = 3,
+ CH_FCH = 3,
+ CH_SCH = 4,
+ CH_SYNC = 5
+} Cph1xCHType;
+
+typedef enum
+{
+ SF4 = 0,
+ SF8,
+ SF16,
+ SF32,
+ SF64,
+ SF128,
+ SF256
+} Cph1xSFType;
+
+
+typedef enum
+{
+ FNG_RELEASED = 0,
+ FNG_ACTIVATED,
+ FNG_OBSERVED
+} Cph1xFngStatus;
+
+typedef struct
+{
+ kal_bool QlicEn;
+ kal_uint32 T7Timing;
+}Cph1xFlRakeQlicCfgT;
+
+
+typedef struct
+{
+ /*For normal init*/
+ kal_uint32 T3Time; /*Uint is 1/8 chip*/
+ kal_uint32 T2Time; /*Uint is 1/8 chip*/
+ kal_uint16 T3Dist; /*Uint is 1/8 chip, last 7 bit not valid*/
+ /*from Rfc state*/
+ CphAntMod AntMode;
+ /*For shdr init*/
+ kal_uint16 PagingOffset;
+ kal_uint32 GsrSlotIndx;
+ kal_uint32 T3GsrAddr;
+
+ /*For all init*/
+ kal_uint8 T7SlotIdx;
+ /*uint is 100kHz*/
+ kal_uint16 DlCarrierFreq;
+ Cph1xL1dState L1dState1x;
+ kal_bool QlicEn;
+ kal_uint16 QlicDelay; /*EChip*/
+ kal_uint32 T7Timing;
+ kal_uint32 LcMask[2];
+ kal_uint32 LcState[2];
+ /*LcState timing*/
+ kal_uint32 LcFrame;
+ kal_uint8 LcPcg;
+ kal_uint8 Pich1xrttRshBit;
+ kal_uint8 FchRshBit;
+ /*Pilot on evdo chip*/
+ kal_uint32 PichOnDoChip;
+} Cph1xFlRakeInitT;
+
+
+
+typedef struct
+{
+ kal_uint8 T6SlotIdx;
+ kal_bool IsShdr;
+} Cph1xFlRakeDeactiveT;
+
+typedef struct
+{
+ kal_bool ChChange;
+ kal_bool ChEn;
+ Cph1xCHType Type;/*CH_TYPE: 1 PCH 2 SYNC 3 FCH */
+ kal_uint8 ForRc;
+ kal_uint8 RevRc;
+ kal_uint32 RshBit;
+ kal_uint16 PnOffset[SECTOR_NUM_1X];
+ kal_uint16 WalshCode[SECTOR_NUM_1X];
+ kal_uint8 QofCode[SECTOR_NUM_1X];
+ kal_uint8 PwrSecSetId[SECTOR_NUM_1X];
+ kal_uint8 Sf;/*0 SF4 1 SF8 ....6 SF 256*/
+ kal_uint16 CfgChangeBit;
+ kal_uint8 ValidBit;
+ kal_uint8 FrameOffset;
+ kal_uint8 Phch0RshBit;
+ kal_uint8 Phch2RshBit;
+} Cph1xFlRakeCh0T;
+
+typedef struct
+{
+ kal_bool ChChange;
+ kal_bool ChEn;
+ kal_uint8 ForRc;
+ kal_uint16 RshBit;
+ kal_uint16 WalshCode[SECTOR_NUM_1X];
+ kal_uint8 QofCode[SECTOR_NUM_1X];
+ kal_uint8 Sf; /*0 SF4 1 SF8 ....6 SF 256*/
+ kal_uint8 CfgChangeBit;
+ kal_uint8 ValidBit;
+ kal_uint8 FrameOffset;
+ kal_uint8 Phch1RshBit;
+} Cph1xFlRakeCh1T;
+
+
+typedef struct
+{
+ Cph1xFlRakeCh0T RakeCh0Cfg;
+ Cph1xFlRakeCh1T RakeCh1Cfg;
+} Cph1xFlRakeChCfgT;
+
+
+
+typedef struct
+{
+ CphAntMod AntMode;
+ kal_uint32 RefTimeEChip;
+ kal_uint32 RefGsrHChip;
+ kal_bool RefGsrSyncReadState;
+ kal_bool RefGsrTimingReadState;
+} Cph1xFlRakeGsrT;
+
+
+typedef struct
+{
+ kal_bool FngEnFlag;
+ kal_uint8 FngIdx;
+
+ kal_uint8 SecId;
+ kal_bool FngReassignFlag;
+ Cph1xFngStatus FngStatus;
+ kal_uint32 FngAddr;
+ kal_uint32 FngSymIdx;
+ kal_uint32 FngInitPower;
+
+ kal_int16 FngAccuDrift;
+ } Cph1xFlRakeFingerCfgT;
+
+typedef struct
+{
+ kal_uint16 PwrTshdA2OH;
+ kal_uint16 PwrTshdO2AH;
+} Cph1xFlRakeTrackerTshdCfgT;
+
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_uint8 FngAccuDrift;
+} Cph1xFlRakeTrackerDriftCfgT;
+
+typedef struct
+{
+ kal_bool RssiStableFlag;
+ kal_uint16 PreviousSpeedResult;
+} Cph1xFlRakeSpestT;
+
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_int8 FngAccuDrift;
+ kal_uint32 FngMicPower;
+ kal_uint8 FngStatus;
+} Cph1xFlRakeTrackerReadT;
+
+
+typedef struct
+{
+ kal_uint8 currSpeed;
+
+} Cph1xFlRakeCurrSpeedT;
+
+
+
+typedef struct
+{
+ kal_bool RxDFlag;
+} Cph1xFlRakeRxdT;
+
+
+
+typedef struct
+{
+ kal_bool OcEn;
+ kal_bool OcSelEn;
+ kal_uint16 OcSelSlotIdx;
+ kal_uint16 OcSelSymIdx;
+ kal_uint16 OcSelLength;
+}Cph1xFlRakeOcCfgT;
+
+
+
+typedef struct
+{
+ kal_uint8 FngIdx;
+ kal_bool Enable;
+ kal_int32 FngPos[8]; // finger number
+}Cph1xFlRakeQlicFingerCfgT;
+
+
+typedef struct
+{
+ kal_bool Enable;
+ kal_uint32 ChEnState;
+ kal_uint32 ActionTimeChip;
+ kal_uint16 ValidBitFch;
+ kal_uint16 ValidBitSch;
+}Cph1xFlRakeCfsCfgT;
+
+
+typedef struct
+{
+ kal_bool FpcEnable;
+ kal_uint16 FpcMode;
+ kal_uint16 FwdRc; /*FWD RC:Rc1 1,RC2 2,...RC11 6, RC12 7*/
+ kal_uint16 RpcMode;
+ kal_uint16 RevRc;
+
+ kal_int32 FpcSubChanGain;
+ kal_bool FchSetPtIncl;
+ kal_int32 FchCurrSetPt;
+ kal_bool SchSetPtIncl;
+ kal_int32 SchCurrSetPt;
+
+}Cph1xFlRakePcModeCfgT;
+
+typedef struct
+{
+ kal_bool FchSetPtIncl;
+ kal_int32 FchCurrSetPt;
+ kal_bool SchSetPtIncl;
+ kal_uint32 SchCurrSetPt;
+}Cph1xFlRakePcSetPtCfgT;
+
+
+typedef struct
+{
+ kal_bool FchFpcValid;
+ kal_uint16 FchFpcDecision;
+ kal_int32 FchEbNt; /*PCG level*/
+
+ kal_bool SchFpcValid;
+ kal_uint16 SchFpcDecision;
+ kal_int32 SchEbNt; /*PCG level*/
+}Cph1xFlRakeFpcBitT;
+
+
+typedef struct
+{
+ kal_bool RpcValid;
+ kal_uint16 RpcDecision;
+ kal_uint16 Index;
+}Cph1xFlRakeRpcBitT;
+
+
+typedef struct
+{
+ kal_bool ChChange;
+ kal_uint16 FchAckMask;
+ kal_uint16 RevFchAckMask;
+ kal_uint32 RxSrpAckTsh;
+}Cph1xFlRakeAckCfgT;
+
+
+typedef struct
+{
+ kal_bool FoeReady;
+ kal_int32 FineFoe;
+ kal_uint32 SqPwr;
+
+}Cph1xFlRakeFoeReadT;
+
+typedef struct
+{
+ kal_uint32 IirPilotPwr;
+ kal_uint32 IirNoisePwr;
+ kal_uint32 IirPcbPwr;
+ kal_uint32 IirFschPwr;
+}Cph1xFlRakeSrpAlphaT;
+
+typedef struct
+{
+ kal_uint32 FchDecodeOK;
+ kal_uint32 FchDecodeUpdate;
+ kal_uint32 FschDecodeOK;
+ kal_uint32 FschDecodeUpdate;
+}Cph1xFlRakeSrpEibT;
+
+extern void Cph1xFlRakeInit(Cph1xFlRakeInitT *adsPtr);
+extern void Cph1xFlRakeShdrInit(Cph1xFlRakeInitT *adsPtr);
+extern kal_bool Cph1xFlRakeSleepIndRead();
+extern kal_bool Cph1xFlRakeStatusRead();
+extern void Cph1xFlRakeChannelDisable();
+extern void Cph1xRlRakeDeactive(Cph1xFlRakeDeactiveT *adsPtr);
+extern void Cph1xFlRakeDisableLoad();
+extern void Cph1xFlRakeDisableD2bifB2rif();
+extern void Cph1xFlRakeDisableA1C1(void);
+extern void Cph1xFlRakeCh0Config(Cph1xFlRakeCh0T *adsPtr);
+extern void Cph1xFlRakeCh1Config(Cph1xFlRakeCh1T *adsPtr);
+extern void Cph1xFlRakeCh2Config(Cph1xFlRakeCh0T *adsPtr);
+extern void Cph1xFlRakeGsrRead(Cph1xFlRakeGsrT *adsPtr);
+extern void Cph1xFlRakeT6Config(kal_uint8 T6SlotIdx);
+extern void Cph1xFlRakeT7Config(kal_uint8 T7SlotIdx);
+extern void Cph1xFlRakeFingerConfig(Cph1xFlRakeFingerCfgT *adsPtr);
+extern void Cph1xFlRakeTrackerRead(Cph1xFlRakeTrackerReadT *adsPtr);
+extern void Cph1xFlRakeTrackerInfo();
+extern void Cph1xFlRakeTrackerTshConfig(Cph1xFlRakeTrackerTshdCfgT *adsPtr);
+extern void Cph1xFlRakeTrackerConfig(Cph1xFlRakeTrackerDriftCfgT *adsPtr);
+extern void Cph1xFlRakeOcConfig(Cph1xFlRakeOcCfgT *adsPtr);
+extern void Cph1xFlRakeOCResultConfig(kal_bool OcSelEn);
+extern void Cph1xFlRakeSpestConfig(Cph1xFlRakeSpestT *adsPtr);
+extern void Cph1xFlRakeSpestForceConfig(kal_uint32 SpeedEstFinal);
+extern void Cph1xFlRakeSpestRead(Cph1xFlRakeCurrSpeedT *adsPtr);
+extern void Cph1xFlRakeRxdConfig(kal_bool Enable);
+extern kal_bool Cph1xFlRakeRxdCheck();
+extern void Cph1xFlRakeQlicConfig(kal_bool QlicEn, kal_uint32 T7Timing);
+extern void Cph1xFlRakeQlicFingerConfig(Cph1xFlRakeQlicFingerCfgT *adsPtr);
+extern void Cph1xFlRakeCfsConfig(Cph1xFlRakeCfsCfgT *adsPtr);
+extern void Cph1xFlRakeFpcModeConfig(Cph1xFlRakePcModeCfgT *adsPtr);
+extern void Cph1xFlRakeFpcSetPtConfig(Cph1xFlRakePcModeCfgT *adsPtr);
+extern void Cph1xFlRakeFpcBitRead(Cph1xFlRakeFpcBitT *adsPtr);
+extern kal_int32 Cph1xFlRakeSyncPchEbNtRead();
+extern void Cph1xFlRakeRpcBitRead(Cph1xFlRakeRpcBitT *adsPtr);
+extern void Cph1xFlRakeAckConfig(Cph1xFlRakeAckCfgT *adsPtr);
+extern kal_bool Cph1xFlRakeAckRead();
+extern void Cph1xFlRakeAckClr();
+extern void Cph1xFlRakeLongCodeMaskConfig(kal_uint32 *adsPtr);
+extern void Cph1xFlRakeLongCodeStateConfig(kal_uint32 *adsPtr);
+extern void Cph1xFlRakeLongCodeStateRead(kal_uint32 *adsPtr);
+extern void Cph1xFlRakeAfcRst();
+extern void Cph1xFlRakeAfcRead(Cph1xFlRakeFoeReadT *adsPtr);
+extern kal_uint32 Cph1xFlRakePilotEbNtRead();
+extern void Cph1xFlRakeSrpAlphaCfg(Cph1xFlRakeSrpAlphaT *adsPtr);
+extern void Cph1xFlRakeEibCfg(Cph1xFlRakeSrpEibT *adsPtr);
+extern kal_bool Cph1xFlRakeC1A1EnCheck();
+extern kal_bool Cph1xFlRakeC0A0EnCheck(void);
+extern void Cph1xFlRakeTrkInitCfg();
+extern void Cph1xFlRakeOcInitCfg();
+extern void Cph1xFlRakeTrkConfThCfg(kal_uint32 PwrTshdO2AH);
+extern void Cph1xFlRakeBigramDumpAccessEnable();
+extern kal_uint32 Cph1xFlRakeBigramIqAddress(CphAntMod AntMode);
+extern void Cph1xFlRakeShdrGsrRead(Cph1xFlRakeGsrT *adsPtr);
+#endif