[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/protocol/general/l5_structs.h b/mcu/interface/protocol/general/l5_structs.h
new file mode 100644
index 0000000..63ee5c0
--- /dev/null
+++ b/mcu/interface/protocol/general/l5_structs.h
@@ -0,0 +1,276 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _L5_STRUCTS_H_
+#define _L5_STRUCTS_H_
+
+#include "ps_public_struct.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#include "atp_public_defs.h"
+#ifndef __MTK_TARGET__
+#include "dcl_uart.h"
+#endif
+#include "l5_common.h"
+
+#define L5_TABLE_DATA_SIZE (20)
+#define L5_L5IO_MBCI_MAX_PENDING_NUM (16)
+#define L5_L5IO_MBCI_MAX_CONTROL_TRANSFER (4096)
+#define L5_L5IO_MBCI_SUPPORT_VERSION (0x0100)
+#define L5_L5IO_MBCI_SUPPORT_EXT_VERSION (0x0300)
+
+#define L5SEQ_ID_URC (0xffffffff)
+/**********L5IO<->L5U***************/
+
+#define L5IO_AT_CMD_REQ_LOCAL_PARA_HDR\
+ L5IO_L5U_LOCAL_PARA_HDR \
+ atp_channel_enum md_ch_id;
+
+#define L5IO_AT_CMD_CNF_LOCAL_PARA_HDR\
+ L5IO_L5U_LOCAL_PARA_HDR \
+ atp_channel_enum md_ch_id; \
+ proxy_cmd_result_enum result; \
+ atp_err_id_enum cause; \
+ kal_bool stuff;
+
+#define L5IO_AT_URC_IND_LOCAL_PARA_HDR\
+ L5IO_L5U_LOCAL_PARA_HDR \
+ atp_channel_enum md_ch_id; \
+ kal_bool stuff;
+
+typedef struct {
+ L5IO_AT_CMD_REQ_LOCAL_PARA_HDR
+}l5io_at_cmd_req_struct;
+
+typedef struct {
+ L5IO_AT_CMD_CNF_LOCAL_PARA_HDR
+}l5io_at_cmd_cnf_struct;
+
+typedef struct {
+ L5IO_AT_URC_IND_LOCAL_PARA_HDR
+}l5io_at_urc_ind_struct;
+
+/**********L5U<->ATP***************/
+
+#define L5U_ATP_CMD_REQ_LOCAL_PARA_HDR\
+ LOCAL_PARA_HDR \
+ atp_channel_enum md_ch_id;
+
+#define L5U_ATP_CMD_CNF_LOCAL_PARA_HDR\
+ LOCAL_PARA_HDR \
+ atp_channel_enum md_ch_id; \
+ proxy_cmd_result_enum result; \
+ atp_err_id_enum cause; \
+ kal_bool stuff;
+
+#define L5U_ATP_URC_IND_LOCAL_PARA_HDR\
+ LOCAL_PARA_HDR \
+ atp_channel_enum md_ch_id; \
+ kal_bool stuff;
+
+
+typedef struct {
+ L5U_ATP_CMD_REQ_LOCAL_PARA_HDR
+}l5u_atp_at_cmd_req_struct;
+
+
+
+typedef struct {
+ L5U_ATP_CMD_CNF_LOCAL_PARA_HDR
+}l5u_atp_at_cmd_cnf_struct;
+
+typedef struct {
+ L5U_ATP_URC_IND_LOCAL_PARA_HDR
+}l5u_atp_at_urc_ind_struct;
+
+typedef struct{
+ LOCAL_PARA_HDR
+ UART_PORT port;
+ kal_uint8 client_name[16];
+}l5io_l5io_mipc_dump_struct;
+typedef l5io_l5io_mipc_dump_struct l5io_l5io_mipc_recv_dump_struct;
+typedef l5io_l5io_mipc_dump_struct l5io_l5io_mipc_send_dump_struct;
+
+typedef struct{
+ LOCAL_PARA_HDR
+ kal_uint8 context_id;
+ kal_uint8 is_frag_msg;
+ kal_uint16 mbim_ver;
+ kal_uint16 mbim_ext_ver;
+}l5io_l5io_mbci_dump_struct;
+typedef l5io_l5io_mbci_dump_struct l5io_l5io_mbci_recv_dump_struct;
+typedef l5io_l5io_mbci_dump_struct l5io_l5io_mbci_send_dump_struct;
+
+/***** UT begin *****/
+#define L5IO_UT_MAX_UART_LENGTH (128)
+
+/* MSG_ID_L5IO_UT_AT_CMD_CNF */
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint16 ch_id;
+ kal_bool stuff;
+ kal_uint8 at_string[L5IO_UT_MAX_UART_LENGTH];
+} l5io_ut_at_cmd_cnf_struct;
+
+#ifndef __MTK_TARGET__
+/* MSG_ID_L5IO_UT_UART_RTR_IND */
+typedef struct {
+ LOCAL_PARA_HDR
+ UART_PORT port;
+ kal_uint16 at_length;
+ kal_uint8 at_string[L5IO_UT_MAX_UART_LENGTH];
+} l5io_ut_uart_rtr_ind_struct;
+
+/* MSG_ID_L5IO_UT_UART_RTW_IND */
+typedef struct {
+ LOCAL_PARA_HDR
+ UART_PORT port;
+} l5io_ut_uart_rtw_ind_struct;
+
+/* MSG_ID_L5IO_UT_AT_CMD_REQ */
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint16 ch_id;
+ kal_uint8 at_string[L5IO_UT_MAX_UART_LENGTH];
+} l5io_ut_at_cmd_req_struct;
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 mode[ATP_REPORT_MODE_MAX];
+} l5io_ut_urc_report_mode_ind_struct;
+
+//MSG_ID_L5_UT_IO_CONTEXT_REQ
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cid;
+ kal_uint16 head;
+ kal_uint16 length;
+ kal_uint8 data[ATP_MAX_DATA_QUEUE_LENGTH];
+ kal_uint8 uart_sim_mapping[ATP_CHANNEL_NUMBER];
+} l5io_ut_io_context_req_struct;
+
+#endif /* __MTK_TARGET__ */
+/***** UT end *****/
+
+#define MAX_CELL_NUM_3G (1)
+#define MAX_CELL_NUM_4G (8)
+#define MAX_CELL_NUM_5G (8)
+
+typedef struct {
+ kal_bool activated;
+ kal_uint32 ul_arfcn;
+ kal_uint32 dl_arfcn;
+ kal_uint32 dl_center_frequency;
+ //kal_uint32 ul_center_frequency;
+ kal_uint32 ul_bandwidth;
+ kal_uint32 dl_bandwidth;
+ kal_bool is_connected;
+ kal_uint32 pci;
+} l5_cell_info1_t; //if changed, need to notify L5IO
+
+typedef struct {
+ kal_bool configured;
+ kal_int16 rsrp; //in dbm,range[-162, 22], -32768 means invalid
+ kal_int8 rsrq; //in db,range[-40, 10], -128 means invalid
+ kal_int8 sinr; //in db,range[-20, 40], -128 means invalid
+ kal_int16 rssi; //in dbm,range[-150, -10], -32768 means invalid
+ kal_uint32 pci;
+} l5_cell_info2_t; //if changed, no need to notify L5IO
+
+
+extern kal_uint32 eifconfig[1];
+
+
+
+typedef enum
+{
+ L5IO_TABLE_CMD_MODE_QUEUE, // AT commands in Whitelist need to be queued
+ L5IO_TABLE_CMD_MODE_EXE, // AT commands in Whitelist need to be executed
+ L5IO_TABLE_CMD_MODE_ERROR, // AT commands in Whitelist need to return Error
+ L5IO_TABLE_CMD_MODE_NONBLOCK,
+
+} l5io_table_cmd_mode_enum;
+
+typedef struct
+{
+ kal_uint16 cmd_id;
+ atp_cmd_mode_enum cmd_mode;
+ l5io_table_cmd_mode_enum mode;
+
+} l5io_list_table_item;
+
+typedef struct
+{
+ kal_uint8 urc[L5_TABLE_DATA_SIZE];
+ atp_urc_report_mode_enum rpt_mode;
+
+} l5io_urc_rpt_mode_chk_tbl_item;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 src_id;
+ kal_char apn[APN_STRING_LEN];
+}l5updn_get_disabled_apn_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 src_id;
+ kal_bool disabled; // TRUE means apn is disabled
+}l5updn_get_disabled_apn_cnf_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 ctx_id;
+ kal_uint32 mbim_msg_len;
+} mbim_l5io_mbci_command_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 ctx_id;
+ kal_uint32 mbim_msg_len;
+} mbim_l5io_mbci_command_cnf_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 ctx_id;
+ kal_uint32 mbim_msg_len;
+} mbim_l5io_mbci_status_ind_struct;
+
+#endif