[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/service/dhl/v1/L1Trc.h b/mcu/interface/service/dhl/v1/L1Trc.h
new file mode 100644
index 0000000..94912b0
--- /dev/null
+++ b/mcu/interface/service/dhl/v1/L1Trc.h
@@ -0,0 +1,892 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * L1Trc.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Layer 1 trace interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 21 2019 yh.sung
+ * [MOLY00392990] [VMOLY][UTF] Phase 2 Landing
+ * [UTF][DHL] UTF Trace API - trace interface
+ *
+ * 06 22 2018 yancy.chien
+ * [MOLY00331449] [Gen97] DHL logging development
+ * Migration on UMOLYE.
+ *
+ * 05 24 2018 yancy.chien
+ * [MOLY00258174] [Gen95][DHL] logging development.
+ *
+ * 01 31 2018 yancy.chien
+ * [MOLY00304870] [DHL] L1 Trace array support
+ * 1. ULSP version macro & function
+ * 2. SW version macro & function, for L1: VPE0~5 & L2: ert/hif/el2
+ * 3. COND&HW_COND version macro & function
+ * 4. Mechanism for check max argument size
+ *
+ * 12 20 2017 kenneth.lin
+ * [MOLY00253909] [DHL] Gen 95 development
+ *
+ * [DHL] API change on xl1sim
+ * - for cgen update
+ *
+ * 12 20 2017 kenneth.lin
+ * [MOLY00253909] [DHL] Gen 95 development
+ * [DHL] API change on xl1sim
+ * - for cgen update
+ *
+ * 11 30 2017 yu-hsiang.peng
+ * [MOLY00292252] [6293] Print L2 timestamp when current is non-4G
+ * [UMOLYA.TRUNK] L2 23G time
+ *
+ * 11 03 2017 yancy.chien
+ * [MOLY00258174] [Gen95][DHL] logging development
+ * Merge from DEV branch.
+ *
+ * 09 07 2017 yu-hsiang.peng
+ * [MOLY00275876] [Gen93] L1 trace code size silm
+ * [UMOLYA.TRUNK] L1 trace redefine
+ *
+ * 08 16 2017 yu-hsiang.peng
+ * [MOLY00266204] [Gen93] Common feature development before control
+ * [UMOLYA.TRUNK] Two features
+ * 1. OTA message filter
+ * 2. Non-smp use function check
+ *
+ * 06 20 2017 kenneth.lin
+ * [MOLY00257978] conditional trace development
+ *
+ * add typedef cgen_use_L1ULSP_NOT_PREPROCESS in 92 gen flow
+ *
+ * 06 19 2017 yancy.chien
+ * [MOLY00257978] conditional trace development
+ * Fix build error.
+ *
+ * 06 19 2017 yancy.chien
+ * [MOLY00257978] conditional trace development
+ * 1st phase-in.
+ *
+ * 04 27 2017 yancy.chien
+ * [MOLY00242548] [DHL] Build warning removal
+ * Apply A style.
+ *
+ * 04 27 2017 yancy.chien
+ * [MOLY00242548] [DHL] Build warning removal
+ * Apply A style.
+ *
+ * 04 20 2017 yu-hsiang.peng
+ * [MOLY00243236] [6293] L1trace LISR check use macro
+ * [UMOLYA.TRUNK] ulsp lisr check use macro to enhance debug flow
+ *
+ * 03 20 2017 kenneth.lin
+ * [MOLY00235284] [xL1SIM][DHL] support ulsp logging feature in xl1sim
+ * [xl1sim][DHL] ulsp code refactoring
+ *
+ * 03 14 2017 kenneth.lin
+ * [MOLY00235284] [xL1SIM][DHL] support ulsp logging feature in xl1sim
+ * fixed build failed on UESIM
+ *
+ * 03 14 2017 kenneth.lin
+ * [MOLY00235284] [xL1SIM][DHL] support ulsp logging feature in xl1sim
+ *
+ * DHL support ulsp logging feature in xl1sim
+ *
+ * 1. enable __USE_ULSP__
+ * 2. implement ulsp macro to send ELT directly
+ *
+ * 03 10 2017 yu-hsiang.peng
+ * [MOLY00224307] [MT6293] General feature change before MP branch create
+ * [UMOLYA.TRUNK] add L1 time trace new format
+ *
+ * 03 10 2017 yu-hsiang.peng
+ * [MOLY00224307] [MT6293] General feature change before MP branch create
+ * [UMOLYA.TRUNK] Fix target build warning
+ *
+ * 03 07 2017 yu-hsiang.peng
+ * [MOLY00224307] [MT6293] General feature change before MP branch create
+ * [UMOLYA.TRUNK] move filter to L2 cached lock
+ *
+ * 03 01 2017 yu-hsiang.peng
+ * [MOLY00231055] [Bianco Bring-up] [6293] L1L2 trace new verison (CGen & DHL)
+ * [UMOLYA.TRUNK] Fix non-smp trace api build warning
+ *
+ * 02 22 2017 yu-hsiang.peng
+ * [MOLY00231055] [Bianco Bring-up] [6293] L1L2 trace new verison (CGen & DHL)
+ * [UMOLYA.TRUNK] change L1/L2 trace macro.
+ *
+ * 02 08 2017 willie.pan
+ * [MOLY00163869] [6293][ULS+] Support 9~16 words for L2 logging in MoDIS
+ *
+ * .
+ *
+ * 12 15 2016 willie.pan
+ * [MOLY00163869] Support 8 word API for MODIS L2 Logging
+ *
+ * 11 29 2016 yu-hsiang.peng
+ * [MOLY00210769] [MT6293] MT6292 CCB service migrate to MT6293 and MT6293 ULSP logging on CCB development
+ * [UMOLYA] Add bound sync in L1L2 redump info.
+ *
+ * 11 28 2016 yu-hsiang.peng
+ * [MOLY00210769] [MT6293] MT6292 CCB service migrate to MT6293 and MT6293 ULSP logging on CCB development
+ * .UMOLYA] Add idle sync in L1L2 redump info.
+ *
+ * 11 14 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * . Suooprt L2 logging @ xL1SIM
+ *
+ * 11 11 2016 yancy.chien
+ * [MOLY00212754] [MT6293][NWSIM][3G][R6][All case][BLOCK] UESIM power on always error at l2trc_send_4_word_int
+ * Fix build error.
+ *
+ * 11 11 2016 yancy.chien
+ * [MOLY00212754] [MT6293][NWSIM][3G][R6][All case][BLOCK] UESIM power on always error at l2trc_send_4_word_int
+ *
+ * 11 08 2016 yancy.chien
+ * [MOLY00211534] [DHL] [L1/L2] Workaround for pass funtion in macro parameter issue
+ *
+ * 11 02 2016 yu-hsiang.peng
+ * [MOLY00210965] [MT6293] Patch MT6290, MT6291, MT6292 change into UMOLYA
+ * [UMOLYA.TRUNK] merge Yancy's CL3048791 & CL#3049395
+ *
+ * 11 01 2016 yancy.chien
+ * [MOLY00200296] [DHL] C2K Time Trace API.
+ * 1. Enlarge ping/pong buffer size to 128KB on UT env
+ * 2. Wrap time trace API by C2K_RAT option
+ *
+ * 11 01 2016 yu-hsiang.peng
+ * [MOLY00210769] [MT6293] MT6292 CCB service migrate to MT6293 and MT6293 ULSP logging on CCB development
+ * [UMOLYA.TRUNK] ULSP on CCB full load logging, normal logging(stage 1)
+ *
+ * 10 27 2016 yancy.chien
+ * [MOLY00181823] [DHL] UMOLY Migrate to UMOLYA - W16.44 Migration.
+ *
+ * 10 14 2016 yancy.chien
+ * [MOLY00181823] [DHL] UMOLY Migrate to UMOLYA
+ * [93Only] Add C2K time API for trigger flush event in MoDIS / UESIM
+ *
+ * 10 03 2016 yancy.chien
+ * [MOLY00181823] [DHL] UMOLY Migrate to UMOLYA
+ * W16.41 Migration
+ * Merge L1Trc related function to fix MoDIS logging issue.
+ *
+ * 09 22 2016 jean.tsao
+ * [MOLY00185213] [UMOLYA] DHL 92 SW logging migrate to 93
+ * [ULSP] MCU side driver API
+ *
+ * 09 21 2016 yu-hsiang.peng
+ * [MOLY00201169] [MT6293] DHL EBS support
+ * [UMOLYA.TRUNK] ULSP buffer put in non-cached
+ * (Required by Cynthia.Sun & Willie Pan)
+ *
+ * 09 20 2016 yu-hsiang.peng
+ * [MOLY00190921] [MT6293] Fix DHL Build Warning
+ * [UMOLYA.TRUNK]. Fix XL1SIM build warning
+ *
+ * 09 20 2016 yu-hsiang.peng
+ * [MOLY00185213] [MT6293] DHL MT6292 SW logging migrate to MT6293 & MT6293 ULSP logging development
+ * [UMOLYA.TRUNK] EX flow L1/L2 redump trace
+ *
+ * 09 14 2016 yu-hsiang.peng
+ * [MOLY00185213] [MT6293] DHL MT6292 SW logging migrate to MT6293 & MT6293 ULSP logging development
+ * [UMOLYA.TRUNK] Exception TMD & Macross templete
+ *
+ * 09 13 2016 yu-hsiang.peng
+ * [MOLY00190921] [MT6293] Fix DHL Build Warning
+ * [UMOLYA.TRUNK] Fix mask interrupt build warning
+ *
+ * 08 11 2016 yu-hsiang.peng
+ * [MOLY00185213] [MT6293] DHL MT6292 SW logging migrate to MT6293 & MT6293 ULSP logging development
+ * [UMOLYA.TRUNK] Merge back 93 ULSP 1st connect ELT code - increase LS buffer size (stage 4)
+ *
+ * 08 03 2016 yu-hsiang.peng
+ * [MOLY00185213] [MT6293] DHL MT6292 SW logging migrate to MT6293 & MT6293 ULSP logging development
+ * [UMOLYA.TRUNK] Merge back 93 ULSP 1st connect ELT code (stage 4)
+ *
+ * 07 22 2016 yancy.chien
+ * [MOLY00192766] [DHL] L1/L2 Trace optimization
+ * Remove redundant "filter[0]==1" checking
+ *
+ * 07 14 2016 yu-hsiang.peng
+ * [MOLY00190921] [MT6293] Fix DHL Build Warning
+ * Kuo-Wei Hung requirement : Fix xL1SIM warning
+ *
+ * 06 24 2016 yu-hsiang.peng
+ * [MOLY00185213] [UMOLYA] DHL 92 SW logging migrate to 93
+ * [UMOLYA.TRUNK] 93 ULSP trace macro & LS 1st integrate (stage 2)
+ *
+ * 06 21 2016 yu-hsiang.peng
+ * [MOLY00185213] [UMOLYA] DHL 92 SW logging migrate to 93
+ * [UMOLYA.TRUNK] 92 SW logging migration & 93 L1 L2 trace macro (stage 1)
+ *
+ * 05 26 2016 yancy.chien
+ * [MOLY00181823] [DHL] UMOLY Migrate to UMOLYA
+ * .
+ *
+ * 05 16 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] Fix warning of ULSP macro
+ *
+ * .
+ *
+ * 04 26 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] ULS+ PAE Log Parsing Feature Phase In
+ *
+ * .
+ *
+ * 04 25 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] Fix ULS+ offset for PAE
+ *
+ * .
+ *
+ * 04 15 2016 eason.lai
+ * [MOLY00173976] [6292][DHL] L1/L2 trace integrated with log DMA
+ * logDMA is not enabled yet due to logDMA sperious IRQ is not fixed
+ *
+ * 04 14 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .Optimize interrupt disable in ULS+ solution
+ *
+ * 04 13 2016 eason.lai
+ * [MOLY00173976] [6292][DHL] L1/L2 trace integrated with log DMA
+ * This change haven't enable the log DMA due to log DMA IRQ has
+ * spurious interrupt.
+ *
+ * 04 13 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] Modification for L1/L2 Logging Profiling
+ *
+ * .
+ *
+ * 04 07 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .
+ *
+ * 04 06 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * . Update for new L1/L2 logging API
+ *
+ * 04 06 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .
+ *
+ * 04 05 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .
+ *
+ * 03 31 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] Temporary use old inerrupt disable API on ULS+
+ *
+ * .
+ *
+ * 03 30 2016 eason.lai
+ * [MOLY00171573] [DHL] apply CIRQ EI/DI marco (without 40Qbit check)
+ * fixed xl1sim L1D cosim regression fail issue
+ *
+ * 03 29 2016 eason.lai
+ * [MOLY00171573] [DHL] apply CIRQ EI/DI marco (without 40Qbit check)
+ * 1. apply CIRQ EI/DI marco on L1 trace
+ * 2. fixed l1trace potential bug
+ * 3. support L1_CATCHER = FALSE
+ *
+ * 03 21 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] Add ULSP L1&L2 Logging Macro
+ *
+ * .
+ *
+ * 03 21 2016 eason.lai
+ * [MOLY00170160] [6292/Elbrus][DHL] L1trace HRT enhancement
+ * reduce caller codesize overhead
+ *
+ * 03 14 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In] Fix auto-TCM issue
+ *
+ * .
+ *
+ * 03 14 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .
+ *
+ * 02 26 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .
+ *
+ * 02 26 2016 willie.pan
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ *
+ * .ULS+ for L1 PAE
+ *
+ * 02 26 2016 eason.lai
+ * [MOLY00163869] [6293][ULS+][ULS+ Phase In]
+ * disabled L2 timesatmp hardcode
+ *
+ * 02 01 2016 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ * l1/l2 log redump
+ *
+ * 01 28 2016 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ *
+ * replace SaveAndSetIRQMask with kal_hrt_SaveAndSetIRQMask
+ *
+ * 01 26 2016 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ * 1. load filter from nvram at task init
+ * 2. exception log dump
+ *
+ * 11 25 2015 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ * refine the xl1sim option in DHL and restore the patch of CL#1796032.
+ *
+ * 11 23 2015 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ * xl1sim introduce SMP DHL
+ *
+ * 10 30 2015 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ *
+ * remove __PCORE__ and __L1CORE__ option
+ *
+ * 10 26 2015 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ * enable L1/L2 trace bit decoding
+ *
+ * 10 23 2015 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ *
+ * SMP DHL logging migration
+ *
+ * 09 21 2015 yu-hsiang.peng
+ * [MOLY00142553] [DHL] fix build warning for LR11 MP/Trunk
+ * [UMOLY.Trunk] Fix build warning(0921)
+ *
+ * 08 27 2015 eason.lai
+ * [MOLY00134958] [MT6292] [DHL] logging service migration
+ * fixed link error
+ *
+ * 07 22 2015 eason.lai
+ * [MOLY00130157] [TK6291][DHL] smart logging migration
+ * fixed dhl_trace.c assert @ 1340
+ *
+ * 07 22 2015 eason.lai
+ * [MOLY00130157] [TK6291][DHL] smart logging migration
+ * .
+ *
+ * 07 10 2015 eason.lai
+ * merge code
+ *
+ * 05 15 2015 eason.lai
+ * [MOLY00113901] [TK6291][DHL] change pcore/l1core l1trace buffer size
+ * base on PAE result, pcore 8KB, l1core 64KB
+ *
+ * 04 26 2015 eason.lai
+ * [MOLY00109038] [TK6291E1][pre 1st Call][UMOLY][4G][FDD] There's no assert/fatal error message on "System Trace(L1CORE)" window
+ * 1. fixed l1core assert log missing by the potential problem.
+ * 2. start to support l1core l1 filer store in NVRAM
+ *
+ * 04 15 2015 eason.lai
+ * [MOLY00107803] [TK6291][DHL] PAE simulation code and option patch back.
+ * as CR title.
+ *
+ * 04 09 2015 eason.lai
+ * [MOLY00105513] [TK6291][DHL] introduce GPD/SPD wrapper
+ * GPD/SPD wrapper and L2copro log dma
+ *
+ * 03 17 2015 eason.lai
+ * [MOLY00084440] [MT6291][DHL] Patch back UMOLY trunk from MT6291_DEV
+ * move L1 trace buffer to L2SRAM, and change tst ring buffer as cacheable
+ *
+ * 02 10 2015 eason.lai
+ * [MOLY00095350] [TK6291][DHL] enable 64us timestamp in modis/uesim
+ * move l2 trace timestamp marco to be function call
+ *
+ * 11 24 2014 eason.lai
+ * [MOLY00084440] [MT6291][DHL] Patch back UMOLY trunk from MT6291_DEV
+ * FMA global timer
+ *
+ * 11 14 2014 eason.lai
+ * [MOLY00084440] [MT6291][DHL] Patch back UMOLY trunk from MT6291_DEV
+ * first time patch back
+ *
+ * 06 09 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * re-enable l1 boxster.
+ *
+ * 05 07 2014 eason.lai
+ * [MOLY00064969] [DHL]expand tab to 4 spaces to have better typesettings
+ * .
+ *
+ * 04 29 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * rollback L1boxster to align ELT support.
+ *
+ * 04 16 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * disable l1boxster on modis.
+ *
+ * 04 16 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * enable l1boxster by default.
+ *
+ * 04 15 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * Disable l1boxster by default due to incorrect usage of L1 trace API in AST L1 module.
+ *
+ * 04 15 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * fix modis build error.
+ *
+ * 04 15 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * fix modis build error.
+ *
+ * 04 15 2014 ken.liu
+ * [MOLY00062708] [DHL] enable L1Boxster support.
+ * enable L1Boxster support and optimization.
+ *
+ * 04 07 2014 eason.lai
+ * [MOLY00061900] [DHL][K95 MD2] merge code from DEV branch
+ * .
+ *
+ * 03 24 2014 ken.liu
+ * [MOLY00060207] [DHL] support L2 log buffer in TCM
+ * support l2 buffer from tcm sections.
+ *
+ * 03 13 2014 ken.liu
+ * [MOLY00059075] [xL1SIM] Patch back to MOLY
+ * add TRC_L2_PAD define.
+ *
+ * 03 10 2014 willie.pan
+ * [MOLY00059007] [MT6290E2][EL1] Sync DSP log and L1 trace by A time
+ * .
+ *
+ * 03 07 2014 ken.liu
+ * [MOLY00058420] [DHL] Fast interrupt mask/unmask via inline assembly for L2 trace
+ * enable __L2_LOGGING_IRQ_LOC__.
+ *
+ * 03 06 2014 ken.liu
+ * [MOLY00058420] [DHL] Fast interrupt mask/unmask via inline assembly for L2 trace
+ * fix modis build error.
+ *
+ * 03 06 2014 ken.liu
+ * [MOLY00058420] [DHL] Fast interrupt mask/unmask via inline assembly for L2 trace
+ * replace l2 trace interrupt mask/unmask with inline assembly.
+ *
+ * 02 26 2014 eason.lai
+ * [MOLY00057680] [L2][HMU][DHL] L2 trace and L2 timestamp support
+ * Provide L2 trace timestamp API and change L2 trace type number
+ *
+ * 08 26 2013 mojo.lai
+ * [MOLY00035110] Fix DHL L1 trace decode fail issue
+ *
+ * 05 15 2013 ken.liu
+ * [MOLY00020676] [MT6290 Bring-up] Layer 2 trace enum arg and filter support
+ * enable l2 trace enum support.
+ *
+ * 04 30 2013 ken.liu
+ * [MOLY00021076] [MT6290 Bring-up] DHL flush log uses too much CPU time before entering idle task
+ * sync from MT6290E1_FirstCall.
+ *
+ * 03 08 2013 ken.liu
+ * [MOLY00009212] LTE Multimode merge back to MOLY
+ * 1. add dhl_EM_logger api.
+ * 2. resend exception log on first tool connection.
+ *
+ * 01 24 2013 ken.liu
+ * [MOLY00005322] TATAKA merge to MOLY
+ * enable flush log on assert
+ *
+ * 12 26 2012 ken.liu
+ * [MOLY00005322] TATAKA merge to MOLY
+ * sync TST new api trc_UpdateTimeStamp.
+ *
+ * 11 29 2012 ken.liu
+ * [MOLY00005322] TATAKA merge to MOLY
+ * sync section attribute for layer 1 trace and l1 sim task/hisr config for DHL.
+ *
+ * 11 07 2012 ken.liu
+ * [MOLY00005322] TATAKA merge to MOLY
+ * dhl module check-in.
+ ****************************************************************************/
+/* Normal L1 traces exmaple
+
+1. default
+#define UMTS_3G_GEMINI_TIME(v1, v2, v3, v4, v5) do {\
+ {\
+ TRC_START_FILTER_CHECK_L1(DHL_L1Trace_Filter, 1, 0x01);\
+ TRC_PREPROCESS_DATA_SECTION1_L1(cgen_local_v1,v1);\
+ TRC_PREPROCESS_DATA_SECTION1_L1(cgen_local_v2,v2);\
+ TRC_PREPROCESS_DATA_SECTION1_L1(cgen_local_v3,v3);\
+ TRC_PREPROCESS_DATA_SECTION1_L1(cgen_local_v4,v4);\
+ TRC_PREPROCESS_DATA_SECTION1_L1(cgen_local_v5,v5);\
+ TRC_START_FILL_L1();\
+ TRC_PREPROCESS_DATA_SECTION2_L1(cgen_local_v1,v1);\
+ TRC_PREPROCESS_DATA_SECTION2_L1(cgen_local_v2,v2);\
+ TRC_PREPROCESS_DATA_SECTION2_L1(cgen_local_v3,v3);\
+ TRC_PREPROCESS_DATA_SECTION2_L1(cgen_local_v4,v4);\
+ TRC_PREPROCESS_DATA_SECTION2_L1(cgen_local_v5,v5);\
+ TRC_OUTPUT_16_FIRST_WRAPPER_L1(0x0000,0x0000);\
+ TRC_OUTPUT_8_MID_WRAPPER_L1(cgen_local_v1,v1);\
+ TRC_OUTPUT_16_MID_WRAPPER_L1(cgen_local_v2,v2);\
+ TRC_OUTPUT_32_MID_WRAPPER_L1(cgen_local_v3,v3);\
+ TRC_OUTPUT_16_MID_WRAPPER_L1(cgen_local_v4,v4);\
+ TRC_OUTPUT_32_LAST_WRAPPER_L1(cgen_local_v5,v5);\
+ TRC_END_FILL_L1();\
+ TRC_END_FILTER_CHECK_L1(DHL_L1Trace_Filter, 1, 0x01);\
+ }\
+} while(0)
+
+2. non_smp
+#define UMTS_3G_GEMINI_TIME(v1, v2, v3, v4, v5) do {\
+ {\
+ TRC_START_FILTER_CHECK_L1_NON_SMP(DHL_L1_Trace_Filter, 1, 0x01);\
+ TRC_PREPROCESS_DATA_SECTION1_L1_NON_SMP(cgen_local_v1,v1);\
+ TRC_PREPROCESS_DATA_SECTION1_L1_NON_SMP(cgen_local_v2,v2);\
+ TRC_PREPROCESS_DATA_SECTION1_L1_NON_SMP(cgen_local_v3,v3);\
+ TRC_PREPROCESS_DATA_SECTION1_L1_NON_SMP(cgen_local_v4,v4);\
+ TRC_PREPROCESS_DATA_SECTION1_L1_NON_SMP(cgen_local_v5,v5);\
+ TRC_START_FILL_L1_NON_SMP();\
+ TRC_PREPROCESS_DATA_SECTION2_L1_NON_SMP(cgen_local_v1,v1);\
+ TRC_PREPROCESS_DATA_SECTION2_L1_NON_SMP(cgen_local_v2,v2);\
+ TRC_PREPROCESS_DATA_SECTION2_L1_NON_SMP(cgen_local_v3,v3);\
+ TRC_PREPROCESS_DATA_SECTION2_L1_NON_SMP(cgen_local_v4,v4);\
+ TRC_PREPROCESS_DATA_SECTION2_L1_NON_SMP(cgen_local_v5,v5);\
+ TRC_OUTPUT_16_FIRST_WRAPPER_L1_NON_SMP(0x0000,0x0000);\
+ TRC_OUTPUT_8_MID_WRAPPER_L1_NON_SMP(cgen_local_v1,v1);\
+ TRC_OUTPUT_16_MID_WRAPPER_L1_NON_SMP(cgen_local_v2,v2);\
+ TRC_OUTPUT_32_MID_WRAPPER_L1_NON_SMP(cgen_local_v3,v3);\
+ TRC_OUTPUT_16_MID_WRAPPER_L1_NON_SMP(cgen_local_v4,v4);\
+ TRC_OUTPUT_32_LAST_WRAPPER_L1_NON_SMP(cgen_local_v5,v5);\
+ TRC_END_FILL_L1_NON_SMP();\
+ TRC_END_FILTER_CHECK_L1_NON_SMP(DHL_L1_Trace_Filter, 1, 0x01);\
+ }\
+} while(0)
+
+
+*/
+// __USE_ULSP__ : Use ULSP HW logger
+// __USE_ULSP_SW_SIMULATOR__ : Use ULSP SW Simulator, this option shouldn't co-exist with __USE_USLP__
+
+/**********************/
+/* CGen gen format */
+/**********************/
+
+#if defined(__USE_ULSP__) || defined(__USE_ULSP_SW_SIMULATOR__)
+
+typedef int cgen_use_L1ULSP;
+typedef int cgen_use_L1BitField;
+typedef int cgen_use_L1CondTrace;
+
+#if defined(__USE_ULSP_SW_SIMULATOR__)
+typedef int cgen_use_L1ULSP_Func_Impl;
+#endif
+
+#else
+
+typedef int cgen_use_L1Boxster;
+typedef int cgen_use_L2Boxster;
+typedef int cgen_use_L1BitField;
+typedef int cgen_use_L1ULSP_NOT_PREPROCESS; //workaround for cgen
+
+#endif
+
+#if defined (L1_CATCHER)
+#ifndef _L1TRC_H
+#define _L1TRC_H
+
+// legacy SW logging format, but still need for conditional trace
+#define TRC_L2_PAD (0xFA)
+#define TRC_BOXSTER_PAD (0xFA)
+//Use MACRO
+#define TRC_MERGE_2S_MACRO(v1, v2) ( (kal_uint32)(v1&0xFFFF) + ( ((kal_uint32)v2)<<16 ))
+#define TRC_MERGE_1S2C_MACRO(v1, v2, v3) ( (kal_uint32)(v1&0xFFFF) + ( ( (kal_uint32)(v2&0xFF) )<<16) + ( ((kal_uint32)v3)<<24) )
+#define TRC_MERGE_4C_MACRO(v1, v2, v3, v4) ( (kal_uint32)(v1&0xFF) + ( ((kal_uint32)(v2&0xFF))<<8) + ( ((kal_uint32)(v3&0xFF))<<16) + ( ((kal_uint32)v4)<<24))
+
+#define TRC_MERGE_2S(v1, v2) TRC_MERGE_2S_MACRO((v1), (v2))
+#define TRC_MERGE_1S2C(v1, v2, v3) TRC_MERGE_1S2C_MACRO((v1), (v2), (v3))
+#define TRC_MERGE_4C(v1, v2, v3, v4) TRC_MERGE_4C_MACRO((v1), (v2), (v3), (v4))
+
+
+
+/* for Cgen 92 SW logging, need Cgen help to remove, otherwise build error */
+typedef enum
+{
+ L1CSPM_DEFAULT,
+ SPIN_LOCK,
+ HW_ITC
+} E_DHL_TMD_CRIT_PROT;
+typedef enum
+{
+ L2_BUFFER_DEFAULT = 0,
+ L2_BUFFER_EL2 = L2_BUFFER_DEFAULT,
+ L2_BUFFER_HIF = 1,
+ L2_BUFFER_ERT = 2,
+ L2_BUFFER_END = 3
+} E_DHL_L2_BUFFER_MAPPING_TABLE;
+
+/*must some with MAX_UNIFIED_TRACE_CLASS_BYTE */
+typedef enum
+{
+ MAX_L1_TRACE_CLASS_BYTE = 8
+} E_NUM_L1_TRACE_CLASS;
+
+//#define __DHL_LEGACY_TRACE_API_ENABLE__
+
+/***************************/
+/* Include */
+/***************************/
+
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#if defined(__USE_ULSP__)
+#include "ulsp_mcu_logging.h"
+#endif//#if defined(__USE_ULSP__)
+
+
+/************************/
+/* Definition - IRQ */
+/************************/
+#if defined(__MTK_TARGET__)
+#if !defined(__L2_LOGGING_IRQ_LOC__)
+#define __L2_LOGGING_IRQ_LOC__
+#endif
+#endif
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+extern kal_uint32 dhl_SaveAndSetIRQMask_cirq_wrap(void);
+extern void dhl_RestoreIRQMask_cirq_wrap(kal_uint32 status);
+#define DHL_LOCK_CPU_INTERRUPT(oldmask) \
+ do{ \
+ oldmask = dhl_SaveAndSetIRQMask_cirq_wrap(); \
+ }while(0)
+
+#define DHL_UNLOCK_CPU_INTERRUPT(oldmask) \
+ do{ \
+ dhl_RestoreIRQMask_cirq_wrap(oldmask); \
+ }while(0)
+#elif defined(__MTK_TARGET__)
+
+extern kal_uint32 kal_hrt_SaveAndSetIRQMask(void);
+extern void kal_hrt_RestoreIRQMask(kal_uint32 irq);
+extern kal_uint32 dhl_SaveAndSetIRQMask_cirq_wrap(void);
+extern void dhl_RestoreIRQMask_cirq_wrap(kal_uint32 status);
+
+
+
+#define DHL_LOCK_CPU_INTERRUPT(oldmask) \
+ do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+ }while(0)
+
+#define DHL_UNLOCK_CPU_INTERRUPT(oldmask) \
+ do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+ }while(0)
+#else
+#define DHL_LOCK_CPU_INTERRUPT(oldmask) \
+ do{ \
+ oldmask = 0; \
+ }while(0)
+
+#define DHL_UNLOCK_CPU_INTERRUPT(oldmask) \
+ do{ \
+ oldmask = 0; \
+ }while(0)
+#endif /* __L2_LOGGING_IRQ_LOC__ */
+
+/**************************/
+/* Definition - */
+/* code setting */
+/**************************/
+#if !defined(GEN_FOR_PC)
+
+#if defined(__MTK_TARGET__)
+#define __DHL_L2CACHE_LOCK_DATA __attribute__ ((section("L2CACHE_LOCK_RW")))
+#else
+#define __DHL_L2CACHE_LOCK_DATA
+#endif
+#define __DHL_Core0IspRAM
+#define __DHL_Core1IspRAM
+#define __DHL_Core2IspRAM
+
+#if defined(__MD97__) || !defined(__MTK_TARGET__)
+#define __DHL_L2SRAM_ROCODE
+#else
+#define __DHL_L2SRAM_ROCODE __attribute__((section ("L2SRAM_L2C_ROCODE")))
+#endif
+
+#define __DHL_Core0DspRAM
+#define __DHL_Core1DspRAM
+#define __DHL_Core2DspRAM
+
+#if defined(__MD97__) || !defined(__MTK_TARGET__)
+#define __DHL_L2SRAM_DATA
+#define __DHL_L2SRAM_RW
+#else
+#define __DHL_L2SRAM_DATA __attribute__((section ("L2SRAM_L2C_ZI")))
+#define __DHL_L2SRAM_RW __attribute__((section ("L2SRAM_L2C_RW")))
+#endif
+
+
+typedef void (*trc_setfilterfunc)(unsigned char *);
+#define TRC_FILTER_FUNC_ARRAY trc_filterfuncarray
+#define TRC_NBR_MODULE trc_filterfuncnbr
+#define TRC_SET_FILTER_FUNC trc_setfilterfunc
+
+/*********************************************/
+/* Macro for declaring filter in codegen */
+/*********************************************/
+//force all to l2 cache in 93 to reduce mips, the conclusion after W16 PAE
+#define DECLARE_TMD_FILTER(VAR_TYPE, VAR_NAME, VAR_SIZE, P0, P1, P2, P3, P4, P5, P6, P7) \
+ VAR_TYPE VAR_NAME[VAR_SIZE] = {P0, P1, P2, P3, P4, P5, P6, P7};
+
+#define DECLARE_TMD_FILTER_L2SRAM(VAR_TYPE, VAR_NAME, VAR_SIZE, P0, P1, P2, P3, P4, P5, P6, P7) \
+ VAR_TYPE VAR_NAME[VAR_SIZE] = {P0, P1, P2, P3, P4, P5, P6, P7};
+
+#define DECLARE_TMD_FILTER_TCM(VAR_TYPE, VAR_NAME, VAR_SIZE, P0, P1, P2, P3, P4, P5, P6, P7) \
+ VAR_TYPE VAR_NAME[VAR_SIZE] = {P0, P1, P2, P3, P4, P5, P6, P7};
+
+/*********************************************/
+/* Macro for extern filter in codegen */
+/*********************************************/
+#define EXTERN_TMD_FILTER(VAR_TYPE, VAR_NAME, VAR_SIZE) \
+ extern VAR_TYPE VAR_NAME[VAR_SIZE];
+
+#define SET_TMD_FILTER(VAR_NAME, VAR_ARRAY_PTR, VAR_ARRAY_SIZE) \
+ do{ \
+ kal_uint32 i; \
+ for(i=0; i<VAR_ARRAY_SIZE; i++) VAR_NAME[i] = VAR_ARRAY_PTR[i]; \
+ }while(0)
+
+#define FILTER_COPY(DES_BUFFER, FILTER_NAME, FILTER_SIZE) \
+ do{ \
+ memcpy(DES_BUFFER, FILTER_NAME, FILTER_SIZE); \
+ }while(0);
+
+#define FILTER_CHECK(FILTER_NAME, FILTER_ARRAY_INDEX, FILTER_CLASS) ((FILTER_NAME[FILTER_ARRAY_INDEX] & FILTER_CLASS) != 0)
+
+
+#endif // #if !defined(GEN_FOR_PC)
+
+/***********************/
+/* Definition - ULSP */
+/***********************/
+
+#if defined(__LTE_L1SIM__)
+extern kal_bool l1_trc_assure_lisr(const char *func, const char *file, int line);
+#else
+extern kal_bool l1_trc_assure_lisr();
+#endif
+
+#include "L1Trc_array.h"
+
+#if defined(__USE_ULSP_SW_SIMULATOR__)
+ #include "dhl_ulsp_swsim_interface.h"
+ #include "dhl_cond_l1_trace.h"
+ #include "L1Trc_ulsp_func_interface.h"
+#elif defined(__USE_ULSP__)
+ #if defined(__MTK_TARGET__)
+ #include "dhl_ulsp_hw_interface.h"
+
+ #elif defined(L1_SIM)
+ #include "dhl_ulsp_xl1sim_interface.h"
+
+ #endif // #if defined(__MTK_TARGET__)
+
+ #include "dhl_cond_l1_trace.h"
+
+#else
+ #include "dhl_l1_legacy_sw_interface.h"
+
+#endif
+
+
+
+
+/************/
+/*Functions */
+/************/
+void trc_fillFrameNumber_multiple(kal_uint32 framenumber, kal_uint32 ebit, kal_uint32 time, kal_uint32 sim_index);
+void trc_UFillFrameNumber_multiple(kal_uint16 framenumber, kal_uint32 ebit, kal_int16 bsfn, kal_uint32 time, kal_uint32 sim_index);
+void trc_fill_4g_time(kal_uint32 phytimer, kal_uint16 sample, kal_uint32 time, kal_uint16 sfn, kal_uint8 subframe);
+void trc_fill_4g_time_2(kal_uint32 phytimer, kal_uint16 sample, kal_uint32 time, kal_uint16 sfn, kal_uint8 subframe, kal_uint32 _4g_time);
+void trc_fill_4g_time_gfrc2(kal_uint32 phytimer, kal_uint32 time, kal_uint16 sfn, kal_uint8 subframe, kal_uint32 absH, kal_uint32 absL);
+void trc_UpdateTimeStamp(kal_uint32 time);
+// Export for HIF GPT use
+void l2trc_fill_4G_time();
+void l2trc_update_4G_time(kal_uint32 celltime, kal_uint32 abstick);
+void l2trc_fill_23G_time();
+#if defined(__C2K_RAT__)
+extern void trc_fill_c2k_do_time(kal_uint8 fn_up, kal_uint32 fn_low, kal_uint8 slot, kal_uint32 echip, kal_uint32 frc);
+extern void trc_fill_c2k_1x_time(kal_uint8 fn_up, kal_uint32 fn_low, kal_uint8 slot, kal_uint32 echip, kal_uint32 frc);
+#endif // defined(__C2K_RAT__)
+//if remove , will build error in el1
+void Trc_Init(void);
+void trc_4g_trigger();
+void trc_UTrigger();
+void trc_handover(kal_uint32 handovertime, kal_uint32 framenumber);
+void trc_Uhandover(kal_uint32 handovertime, kal_uint32 framenumber);
+
+// legacy wrapper, to avoid build error on MoDIS
+void trc_l2_flush();
+
+void trc_setfilter(kal_uint8 *setting, kal_uint32 len);
+void trc_set_l1_filter(kal_uint8 *setting, kal_uint32 len);
+void trc_set_l2_filter(kal_uint8 *setting, kal_uint32 len);
+kal_int32 trc_getfilter(kal_uint8 *buffer, kal_int32 len);
+
+
+#endif //_L1TRC_H
+#endif /* #if defined(L1_CATCHER) */