[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/service/sst/coresonic_access_ctrl_public.h b/mcu/interface/service/sst/coresonic_access_ctrl_public.h
new file mode 100644
index 0000000..8df3be7
--- /dev/null
+++ b/mcu/interface/service/sst/coresonic_access_ctrl_public.h
@@ -0,0 +1,91 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * coresonic_access_ctrl_public.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef CORESONIC_ACCESS_CTRL_PUBLIC_H
+#define CORESONIC_ACCESS_CTRL_PUBLIC_H
+
+#include "kal_public_api.h"
+
+#define MAX_CORESONIC_NUM (3)
+
+typedef enum {
+ C2CRF_DISABLE=0,
+ C2CRF_ENABLE,
+} C2CRF_ACCESS_CTRL;
+
+typedef enum
+{
+ PM_ICM_DISABLE=0,
+ PM_ICM_ENABLE
+}PM_ICM_ACCESS_CTRL;
+
+kal_int32 Coresonic_C2CRF_Ctrl(C2CRF_ACCESS_CTRL ctrl_state);
+kal_int32 Coresonic_PM_ICM_Ctrl(PM_ICM_ACCESS_CTRL ctrl_state);
+#endif /* CORESONIC_BOOT_PUBLIC_H */
\ No newline at end of file
diff --git a/mcu/interface/service/sst/coresonic_boot_public.h b/mcu/interface/service/sst/coresonic_boot_public.h
new file mode 100644
index 0000000..388763b
--- /dev/null
+++ b/mcu/interface/service/sst/coresonic_boot_public.h
@@ -0,0 +1,110 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * coresonic_boot_public.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef CORESONIC_BOOT_PUBLIC_H
+#define CORESONIC_BOOT_PUBLIC_H
+
+#include "kal_public_api.h"
+
+typedef enum
+{
+ DSP_CORESONIC_CORE_ICC=0,
+ DSP_CORESONIC_CORE_IMC,
+ DSP_CORESONIC_CORE_MPC
+}DSP_CORESONIC_CORE;
+
+//typedef enum {
+// C2CRF_DISABLE=0,
+// C2CRF_ENABLE,
+//} C2CRF_ACCESS_CTRL;
+
+
+
+typedef enum {
+ DL_INIT,
+ DL_IN_PROGRESS,
+ DL_DONE
+} CORESONIC_DOWNLOAD_STATUS;
+
+kal_int32 Coresonic_Load(void);
+kal_int32 Coresonic_Status(void);
+kal_int32 Coresonic_Handshake(void);
+kal_int32 Coresonic_ungate(void);
+
+extern kal_char *Coresonic_GetCoreName(DSP_CORESONIC_CORE core);
+extern kal_char *Coresonic_GetProject(DSP_CORESONIC_CORE core);
+extern kal_char *Coresonic_GetFlavor(DSP_CORESONIC_CORE core);
+extern kal_char *Coresonic_GetLabel(DSP_CORESONIC_CORE core);
+extern kal_char *Coresonic_GetBuildTime(DSP_CORESONIC_CORE core);
+extern kal_int32 Coresonic_Init();
+
+//kal_int32 Coresonic_C2CRF_Ctrl(C2CRF_ACCESS_CTRL ctrl_state);
+
+#endif /* CORESONIC_BOOT_PUBLIC_H */
\ No newline at end of file
diff --git a/mcu/interface/service/sst/csif_struct_check_public.h b/mcu/interface/service/sst/csif_struct_check_public.h
new file mode 100644
index 0000000..51cbc9d
--- /dev/null
+++ b/mcu/interface/service/sst/csif_struct_check_public.h
@@ -0,0 +1,9 @@
+#ifndef __CSIF_STRUCT_CHECK_PUBLIC_H__
+#define __CSIF_STRUCT_CHECK_PUBLIC_H__
+
+////////////////
+// public APIs
+/////////////////
+void CSIFStructure_Check_Fill(void);
+
+#endif //__CSIF_STRUCT_CHECK_PUBLIC_H__
\ No newline at end of file
diff --git a/mcu/interface/service/sst/dsp_boot.h b/mcu/interface/service/sst/dsp_boot.h
new file mode 100644
index 0000000..f01215e
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_boot.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dsp_boot.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef DSP_BOOT_H
+#define DSP_BOOT_H
+
+/* common part */
+/* WARNNING: The start of each type of DSP must be multiple of 0x1000 */
+
+#define DSP_TYPE_INTERVAL 0x1000
+
+typedef enum {
+ DSP_MD32 = 0x1000,
+ DSP_MD32_START = 0x0000,
+ DSP_MD32_RAKE,
+ DSP_MD32_END,
+
+ DSP_SC = 0x2000,
+ DSP_SC_START = 0x2000,
+ DSP_SC_ICC,
+ DSP_SC_IMC,
+ DSP_SC_MPC,
+ DSP_SC_END,
+
+ DSP_TYPE_END,
+} DSP_TYPE;
+
+
+/* target specific part */
+#ifndef __DSP_PBP__
+
+#include "kal_general_types.h"
+
+kal_int32 DSP_Init();
+kal_int32 DSP_Load(DSP_TYPE dsp_type);
+kal_uint32 DSP_Image[1024 * 1024 >> 2];
+
+#else /* __DSP_PBP__ */
+/* DSP PBP specific part */
+
+#endif /* __DSP_PBP__ */
+
+#endif /* DSP_BOOT_H */
diff --git a/mcu/interface/service/sst/dsp_cache_public.h b/mcu/interface/service/sst/dsp_cache_public.h
new file mode 100644
index 0000000..e45a0a6
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_cache_public.h
@@ -0,0 +1,19 @@
+#ifndef __SVC_USIP_CACHE_PUBLIC_H__
+#define __SVC_USIP_CACHE_PUBLIC_H__
+
+/***************************************************************/
+/********* Enum for EX uSIP Cache Dump**************************/
+/***************************************************************/
+typedef enum{
+ EX_USIP_IABT_NONE,
+ EX_USIP_IABT_USIP0,
+ EX_USIP_IABT_USIP1,
+ EX_USIP_IABT_USIP0_USIP1
+} EX_USIP_IABT_CORE;
+
+/***************************************************************/
+/********* Function Prototype **********************************/
+/***************************************************************/
+extern void ex_usip_dump_cache_content(kal_uint32 usip0_iabt_pc, kal_uint32 usip1_iabt_pc, EX_USIP_IABT_CORE usip_iabt_cores);
+
+#endif
diff --git a/mcu/interface/service/sst/dsp_dbg_ctrl_public.h b/mcu/interface/service/sst/dsp_dbg_ctrl_public.h
new file mode 100644
index 0000000..56cc9a5
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_dbg_ctrl_public.h
@@ -0,0 +1,10 @@
+#ifndef __SVC_DSP_DBG_CTRL_PUBLIC_H__
+#define __SVC_DSP_DBG_CTRL_PUBLIC_H__
+
+/*******************************************************************************
+ * Function Prototype
+ *******************************************************************************/
+extern kal_uint32 resume_SCq16_from_dbgmode(kal_uint32 scq16_core_idx);
+
+#endif
+
diff --git a/mcu/interface/service/sst/dsp_file_public.h b/mcu/interface/service/sst/dsp_file_public.h
new file mode 100644
index 0000000..0f65fbd
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_file_public.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dsp_boot_public.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DSP_FILE_PUBLIC_H
+#define DSP_FILE_PUBLIC_H
+
+#include "kal_general_types.h"
+
+
+/*******************************************************************************
+ * Macro definitions
+ *******************************************************************************/
+#define DSP_VER_SZ 32
+#define DSP_VER_STR_OVHD 512
+#define DSP_VER_STR_TTL_SZ (DSP_VER_SZ * 4 * 6 + DSP_VER_STR_OVHD)
+
+#define ERROR_DUMP_CORE_TYPE_UNDEFINED 0xDEADBEEF
+#define ERROR_DUMP_CORE_TYPE_NOT_USIP_SCQ16 0xDEAD0000
+#define ERROR_DUMP_NO_USIP_SCQ16_MAPPING 0xDEAD0010
+#define ERROR_DUMP_CORE_TYPE_NOT_RAKE 0xDEAD0006
+#define ERROR_DUMP_NO_RAKE_MAPPING 0xDEAD0016
+#define ERROR_DUMP_CORE_TYPE_NOT_SONIC 0xDEAD0026
+#define ERROR_DUMP_NO_SONIC_MAPPING 0xDEAD0036
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+kal_uint32 DSP_Init(void);
+kal_bool DSP_IsVersionMismatched(void);
+const kal_char *DSP_GetVersionString(void);
+
+/* TO DO: refine this to adapt to MIPS */
+//#ifdef __L1CORE__
+
+typedef enum {
+ DSP_DUMP_USIP0,
+ DSP_DUMP_USIP1,
+ DSP_DUMP_SCQ16_0,
+ DSP_DUMP_SCQ16_1,
+ DSP_DUMP_RAKE,
+ DSP_DUMP_SCQ16_2,
+ DSP_DUMP_SCQ16_3,
+#if defined(__MD97__)
+ DSP_DUMP_MSONIC0,
+ DSP_DUMP_VSONIC0,
+ DSP_DUMP_MSONIC0_PHASE2,
+#endif
+ DSP_DUMP_INVALID
+} DSP_DUMP_CORE_TYPE;
+
+
+typedef enum {
+ DSP_MD32_BRP,
+ DSP_MD32_DFE,
+ DSP_MD32_RAKE,
+ DSP_CS_ICC,
+ DSP_CS_IMC,
+ DSP_CS_MPC,
+ DSP_CORE_NUM,
+} DSP_CORE_TYPE;
+
+void DSP_OutputVersionInfo();
+const kal_char *DSP_GetProject(DSP_CORE_TYPE dsp_type);
+const kal_char *DSP_GetFlavor(DSP_CORE_TYPE dsp_type);
+const kal_char *DSP_GetLabel(DSP_CORE_TYPE dsp_type);
+const kal_char *DSP_GetBuildTime(DSP_CORE_TYPE dsp_type);
+//#endif /* __L1CORE__ */
+
+#endif /* DSP_FILE_PUBLIC_H */
+
diff --git a/mcu/interface/service/sst/dsp_module_based_api_public.h b/mcu/interface/service/sst/dsp_module_based_api_public.h
new file mode 100644
index 0000000..4a7c63a
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_module_based_api_public.h
@@ -0,0 +1,229 @@
+#ifndef __DSP_MODULE_BASED_API_PUBLIC_H__
+#define __DSP_MODULE_BASED_API_PUBLIC_H__
+#if defined(__MD97__) || defined(__MD97P__)
+
+#include "dsp_control_public.h"
+
+//usip part
+
+
+typedef enum{
+ SRAM_DEC_BUS_CK,
+ DSPLOG_CK,
+ USIP_AFE_CK
+} DSP_CTRL_PERI_CLOCK_CTRL;
+
+#define SRAM_DEC_BUS_CK_ENABLE_BIT (1 << SRAM_DEC_BUS_CK)
+#define DSPLOG_CK_ENABLE_BIT (1 << DSPLOG_CK)
+#define USIP_AFE_CK_ENABLE_BIT (1 << USIP_AFE_CK)
+
+#define SRAM_DEC_BUS_CK_DISABLE_BIT (1 << SRAM_DEC_BUS_CK)
+#define DSPLOG_CK_DSIABLE_BIT (1 << DSPLOG_CK)
+#define USIP_AFE_CK_DISABLE_BIT (1 << USIP_AFE_CK)
+
+typedef enum{
+ FORCE_CCC_CK,
+ FORCE_USIP_BUS_CK,
+ FORCE_USIPCORE_BUS_CK,
+ FORCE_CORE0_CK,
+ FORCE_CORE1_CK,
+ FORCE_L1_ALL_CK,
+ FORCE_USIP_ALL_BUS_CK,
+ FORCE_USIP_DDR_CK,
+ FORCE_INT_CORE0_CK,
+ FORCE_INT_CORE1_CK,
+ FORCE_SLOW_INT_CK_DIV2
+} DSP_CTRL_PERI_CLOCK_FORCE_CTRL;
+
+#define FORCE_CCC_CK_ENABLE_BIT (1 << FORCE_CCC_CK)
+#define FORCE_USIP_BUS_CK_ENABLE_BIT (1 << FORCE_USIP_BUS_CK)
+#define FORCE_USIPCORE_BUS_CK_ENABLE_BIT (1 << FORCE_USIPCORE_BUS_CK)
+#define FORCE_CORE0_CK_ENABLE_BIT (1 << FORCE_CORE0_CK)
+#define FORCE_CORE1_CK_ENABLE_BIT (1 << FORCE_CORE1_CK)
+#define FORCE_L1_ALL_CK_ENABLE_BIT (1 << FORCE_L1_ALL_CK)
+#define FORCE_USIP_ALL_BUS_CK_ENABLE_BIT (1 << FORCE_USIP_ALL_BUS_CK)
+#define FORCE_USIP_DDR_CK_ENABLE_BIT (1 << FORCE_USIP_DDR_CK)
+#define FORCE_INT_CORE0_CK_ENABLE_BIT (1 << FORCE_INT_CORE0_CK)
+#define FORCE_INT_CORE1_CK_ENABLE_BIT (1 << FORCE_INT_CORE1_CK)
+#define FORCE_SLOW_INT_CK_DIV2_ENABLE_BIT (1 << FORCE_SLOW_INT_CK_DIV2)
+
+#define FORCE_CCC_CK_DISABLE_BIT (1 << FORCE_CCC_CK)
+#define FORCE_USIP_BUS_CK_DISABLE_BIT (1 << FORCE_USIP_BUS_CK)
+#define FORCE_USIPCORE_BUS_CK_DISABLE_BIT (1 << FORCE_USIPCORE_BUS_CK)
+#define FORCE_CORE0_CK_DISABLE_BIT (1 << FORCE_CORE0_CK)
+#define FORCE_CORE1_CK_DISABLE_BIT (1 << FORCE_CORE1_CK)
+#define FORCE_L1_ALL_CK_DISABLE_BIT (1 << FORCE_L1_ALL_CK)
+#define FORCE_USIP_ALL_BUS_CK_DISABLE_BIT (1 << FORCE_USIP_ALL_BUS_CK)
+#define FORCE_USIP_DDR_CK_DISABLE_BIT (1 << FORCE_USIP_DDR_CK)
+#define FORCE_INT_CORE0_CK_DISABLE_BIT (1 << FORCE_INT_CORE0_CK)
+#define FORCE_INT_CORE1_CK_DISABLE_BIT (1 << FORCE_INT_CORE1_CK)
+#define FORCE_SLOW_INT_CK_DIV2_DISABLE_BIT (1 << FORCE_SLOW_INT_CK_DIV2)
+
+
+/***************************************************************/
+/********* Variable Prototype **********************************/
+/***************************************************************/
+extern kal_uint32 duty_rat[DSP_CONTROL_CDIF_CORE_NUM];
+
+
+/***************************************************************/
+/********* Function Prototype **********************************/
+/***************************************************************/
+
+/*****cosim only API****/
+extern void usip_boot(void);
+extern void usip_power_aware(void);
+extern void usip_peripheral_clock_enable(kal_uint32);
+extern void usip_peripheral_clock_disable(kal_uint32);
+extern void usip_peripheral_clock_force_enable(kal_uint32);
+extern void usip_peripheral_clock_force_disable(kal_uint32);
+
+extern DSP_CONTROL_STATUS usip0_thread0_boot_done_check(void);
+extern DSP_CONTROL_STATUS usip0_thread1_boot_done_check(void);
+extern DSP_CONTROL_STATUS usip1_thread0_boot_done_check(void);
+
+extern void rake_ungate(void);
+
+extern DSP_CONTROL_STATUS rake_boot_done_check(void);
+
+/* FirstBoot API */
+extern kal_uint32 firstboot_topsm_query(DSP_CDIF_CORE_ENUM);
+
+/***** Common API *****/
+extern void query_usip_pc(kal_uint32*, kal_uint32*);
+extern kal_uint32 return_dutyrat_of_thread(DSP_CDIF_CORE_ENUM);
+
+
+/* Check Boot Done API*/
+extern kal_bool is_usip_vic_enable(DSP_CDIF_CORE_ENUM);
+extern void rake_later_trigger_ungate();
+/* Check status APIs */
+extern kal_bool dsp_uSIP_thread_is_deactive(DSP_CDIF_CORE_ENUM);
+
+/* DDL Relatives */
+extern void uSIP_inner_ddl_start(L1_MODULE_REGISTRATION, DDL_MODE);
+extern void uSIP_brp_ddl_start(L1_MODULE_REGISTRATION, DDL_MODE);
+/*extern void uSIP_fec_tx_ddl_start(uSIP_API_USER_FEC , DDL_MODE);
+extern void uSIP_fec_rx_ddl_start(uSIP_API_USER_FEC , DDL_MODE);*/
+extern void uSIP_inner_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_brp_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_fec_tx_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_fec_rx_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_rake_as_tcm_for_inner_ddl_status_mode_query(DDL_STATUS *status, DDL_MODE *bin_mode);
+extern void ddl_clear_inner_ddl_protection_trigger();
+extern kal_uint32 dsp_check_ddl_user_status(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_bool ddl_has_user_call_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***** Sleep Flow APIs for user *****/
+/* FirstBoot API */
+#define topsm_return_dutyrat_of_inner firstboot_topsm_query(DSP_CONTROL_USIP0_INNER)
+#define topsm_return_dutyrat_of_brp firstboot_topsm_query(DSP_CONTROL_USIP0_BRP)
+#define topsm_return_dutyrat_of_fec firstboot_topsm_query(DSP_CONTROL_USIP1_FEC)
+#define topsm_return_dutyrat_of_speech firstboot_topsm_query(DSP_CONTROL_USIP1_SPEECH)
+
+
+/* Check idle APIs */
+extern kal_uint32 inner_user_mask;
+extern kal_uint32 brp_user_mask;
+extern kal_uint32 rake_user_mask;
+extern kal_uint32 ddl_check_idle_flag(kal_uint32);
+#define ddl_uSIP_inner_check_idle_flag() ddl_check_idle_flag(inner_user_mask)
+#define ddl_uSIP_brp_check_idle_flag() ddl_check_idle_flag(brp_user_mask)
+
+
+/* Check status APIs */
+#define dsp_uSIP_inner_is_deactive dsp_uSIP_thread_is_deactive(DSP_CONTROL_USIP0_INNER)
+
+/***** DDL Flow APIs for user *****/
+// Trigger DDL
+#define dsp_uSIP_inner_ddl_start(user_id, bin_mode) uSIP_inner_ddl_start(user_id, bin_mode)
+#define dsp_uSIP_brp_ddl_start(user_id,bin_mode) uSIP_brp_ddl_start(user_id, bin_mode)
+/*#define dsp_uSIP_fec_tx_ddl_start(user_id,bin_mode) uSIP_fec_tx_ddl_start(user_id, bin_mode)
+#define dsp_uSIP_fec_rx_ddl_start(user_id,bin_mode) uSIP_fec_rx_ddl_start(user_id, bin_mode) */
+
+// Check uSIP inner DDL mode/status
+#define dsp_uSIP_inner_ddl_status_mode_query(status, bin_mode) uSIP_inner_ddl_status_mode_query(status, bin_mode)
+#define dsp_uSIP_brp_ddl_status_mode_query(status, bin_mode) uSIP_brp_ddl_status_mode_query(status, bin_mode)
+#define dsp_uSIP_fec_tx_ddl_status_mode_query(status, bin_mode) uSIP_fec_tx_ddl_status_mode_query(status, bin_mode)
+#define dsp_uSIP_fec_rx_ddl_status_mode_query(status, bin_mode) uSIP_fec_rx_ddl_status_mode_query(status, bin_mode)
+#define usip_check_ddl_user_status(thread, user_bitmap) dsp_check_ddl_user_status(thread, user_bitmap)
+
+// clear inner ddl_protection
+#define dsp_uSIP_inner_clear_ddl_protection() ddl_clear_inner_ddl_protection_trigger()
+
+// for exception flow use. Query the active units
+typedef enum
+{
+ DSP_CTRL_GROUP_USIP,
+ DSP_CTRL_GROUP_RAKE,
+ DSP_CTRL_GROUP_MSONIC,
+ DSP_CTRL_GROUP_VSONIC,
+ DSP_CTRL_GROUP_NUM
+} EX_DSP_CORES_ENUM;
+
+#define dsp_ex_active_status_query(core_group) 0xF
+
+//Rake part
+
+
+/***************************************************************/
+/********* Function Prototype **********************************/
+/***************************************************************/
+
+
+/* Common API */
+
+extern kal_bool is_myself_duty_rat(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_uint32 return_dutyrat_of_thread(DSP_CDIF_CORE_ENUM);
+
+
+
+/* DDL Relatives */
+extern void rake_ddl_start(L1_MODULE_REGISTRATION , DDL_MODE);
+extern void rake_ddl_status_mode_query(DDL_STATUS*, DDL_MODE*);
+extern kal_bool ddl_check_all_target_user_are_deactive(DSP_CDIF_CORE_ENUM);
+extern kal_bool ddl_has_rake_user_call_deactivate(kal_uint32);
+extern kal_uint32 dsp_check_ddl_user_status(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***************************************************************/
+/********* Function Definition *********************************/
+/***************************************************************/
+/***** Sleep Flow APIs for user *****/
+/* FirstBoot API */
+#define topsm_return_dutyrat_of_rake firstboot_topsm_query(DSP_CONTROL_RAKE)
+
+#define is_myself_duty_user_of_rake(user_id) is_myself_duty_rat(DSP_CONTROL_RAKE, user_id)
+
+
+/* Check idle APIs */
+#define rake_check_ddl_user_status(user_bitmap) dsp_check_ddl_user_status(DSP_CONTROL_RAKE, user_bitmap)
+#define ddl_rake_check_idle_flag() ddl_check_idle_flag(rake_user_mask)
+#define rake_ddl_check_idle_flag_bitmap(user_bitmap) dsp_check_ddl_user_status(DSP_CONTROL_RAKE, user_bitmap)
+
+
+/***** DDL Flow APIs for user *****/
+// DDL check if RAKE is deactive
+#define ddl_l2tcm_is_rake_deactive() ddl_check_all_target_user_are_deactive(DSP_CONTROL_RAKE)
+
+// Trigger DDL
+#define dsp_rake_ddl_start(user_id, bin_mode) rake_ddl_start(user_id, bin_mode)
+
+// Check rake DDL mode/status
+#define dsp_rake_ddl_status_mode_query(status, bin_mode) rake_ddl_status_mode_query(status, bin_mode)
+
+
+
+/***************************************************************/
+/********* Module based Function Prototype **********************************/
+/***************************************************************/
+
+extern void dsp_firstboot_activate_by_module(kal_uint32);
+extern void dsp_activate_by_module(kal_uint32);
+extern DSP_CONTROL_STATUS dsp_activate_done_check_by_module(kal_uint32);
+extern void dsp_deactivate_by_module(kal_uint32);
+extern DSP_CONTROL_STATUS dsp_deactivate_done_check_by_module(kal_uint32);
+extern kal_uint32 dsp_check_idle_flag_by_module(kal_uint32);
+extern kal_uint32 dsp_check_idle_flag_by_firmware(kal_uint32);
+
+#endif //defined(__MD97__) || defined(__MD97P__)
+#endif /* __DSP_MODULE_BASED_API_PUBLIC_H__ */
diff --git a/mcu/interface/service/sst/dsp_public_dbgc.h b/mcu/interface/service/sst/dsp_public_dbgc.h
new file mode 100644
index 0000000..9440949
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_public_dbgc.h
@@ -0,0 +1,28 @@
+#ifndef __DSP_DBGC_PUBLIC_H__
+#define __DSP_DBGC_PUBLIC_H__
+
+
+#if defined(__MD97__)
+
+typedef enum{
+ DSP_DBGC_IDLE_THREAD_NONE = 0x0,
+ DSP_DBGC_IDLE_THREAD0 = 0x1 << 0,
+ DSP_DBGC_IDLE_THREAD1 = 0x1 << 1,
+ DSP_DBGC_IDLE_THREAD2 = 0x1 << 2,
+ DSP_DBGC_IDLE_THREAD3 = 0x1 << 3,
+
+ DSP_DBGC_IDLE_ALL_THREAD = DSP_DBGC_IDLE_THREAD0 | DSP_DBGC_IDLE_THREAD1 | DSP_DBGC_IDLE_THREAD2 | DSP_DBGC_IDLE_THREAD3,
+
+}DSP_DBGC_IDLE_SIGNAL_ENUM;
+
+
+extern void dsp_dbgc_set_idle_signal(DSP_DBGC_IDLE_SIGNAL_ENUM value);
+extern void dsp_dbgc_clr_idle_signal(DSP_DBGC_IDLE_SIGNAL_ENUM value);
+extern DSP_DBGC_IDLE_SIGNAL_ENUM dsp_dbgc_idle_signal_status(void);
+
+#else /* Not MD97 */
+
+// let it empty, because only MD97 has the DBGC module
+#endif
+
+#endif /* __DSP_DBGC_PUBLIC_H__ */
diff --git a/mcu/interface/service/sst/dsp_public_eintc.h b/mcu/interface/service/sst/dsp_public_eintc.h
new file mode 100644
index 0000000..1cd430c
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_public_eintc.h
@@ -0,0 +1,10 @@
+#ifndef DSP_PUBLIC_EINTC_H
+#define DSP_PUBLIC_EINTC_H
+
+#include "kal_public_api.h"
+
+extern void dsp_eintc_set_idle_signal(kal_uint32 thread);
+extern void dsp_eintc_clr_idle_signal(kal_uint32 thread);
+extern kal_uint32 dsp_eintc_idle_signal_status();
+
+#endif /* DSP_PUBLIC_EINTC_H */
\ No newline at end of file
diff --git a/mcu/interface/service/sst/dsp_swla_public.h b/mcu/interface/service/sst/dsp_swla_public.h
new file mode 100644
index 0000000..97c76af
--- /dev/null
+++ b/mcu/interface/service/sst/dsp_swla_public.h
@@ -0,0 +1,40 @@
+
+#ifndef __DSP_SWLA_PUBLIC_H__
+#define __DSP_SWLA_PUBLIC_H__
+#include "drv_asm.h"
+
+#if defined(__MD93__) || defined(__MD95__)
+typedef enum
+{
+ USIP_BRP_SWLA = ASM_NUM,
+ USIP_INNER_SWLA,
+ USIP_FEC_SWLA,
+ USIP_SPEECH_SWLA,
+ USIP_SWLA_NUM,
+ MCU_DSP_SWLA_NUM = USIP_SWLA_NUM,
+}DSP_SWLA_THREAD_ID;
+#elif defined(__MD97__) || defined(__MD97P__)
+typedef enum
+{
+ USIP_INNER_SWLA = ASM_NUM,
+ USIP_BRP_SWLA,
+ USIP_SPEECH_SWLA,
+ USIP_SWLA_NUM,
+}USIP_SWLA_THREAD_ID;
+
+typedef enum
+{
+ MSONIC_CORE0_SWLA = USIP_SWLA_NUM,
+ VSONIC_CORE0_SWLA,
+ SONIC_SWLA_NUM,
+ MCU_DSP_SWLA_NUM = SONIC_SWLA_NUM,
+ /*remove cores*/
+ MSONIC_CORE1_SWLA,
+}SONIC_SWLA_THREAD_ID;
+
+#else
+ #error "Unknown Arch"
+#endif
+
+#endif //__DSP_SWLA_PUBLIC_H__
+
diff --git a/mcu/interface/service/sst/ex_mem_manager_public.h b/mcu/interface/service/sst/ex_mem_manager_public.h
new file mode 100644
index 0000000..65f3708
--- /dev/null
+++ b/mcu/interface/service/sst/ex_mem_manager_public.h
@@ -0,0 +1,320 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_mem_manager_public.h
+ *
+ * Project:
+ * --------
+ * Moly
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __EX_MEM_MANAGER_PUBLIC_H__
+#define __EX_MEM_MANAGER_PUBLIC_H__
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#include "kal_public_defs.h"
+#endif /* __OFFLINE_EX_LOG_PARSER__ */
+
+typedef enum{
+//EPOF
+ EMM_EPOF_ENTER = 0,
+//EPON
+ EMM_EPON,
+//offending exception enter count
+ EMM_INT_EXCEPTION_COUNT,
+//WDT: enable caller/timestamp
+ EMM_WDT1_EN_CALLER,
+ EMM_WDT1_EN_TIME,
+ EMM_WDT2_EN_CALLER,
+ EMM_WDT2_EN_TIME,
+//WDT: disable caller/timestamp
+ EMM_WDT1_DIS_CALLER,
+ EMM_WDT1_DIS_TIME,
+ EMM_WDT2_DIS_CALLER,
+ EMM_WDT2_DIS_TIME,
+//WDT: DRV/ABN caller/timestamp
+ EMM_WDT_DRV_RST_CALLER,
+ EMM_WDT_DRV_RST_TIME,
+ EMM_WDT_ABN_RST_CALLER,
+ EMM_WDT_ABN_RST_TIME,
+//WDT: Set Check bit caller/callervpe/timestamp per VPE
+ EMM_VPE0_WDT_SET_CHK_CALLER,
+ EMM_VPE0_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE0_WDT_SET_CHK_TIME,
+ EMM_VPE1_WDT_SET_CHK_CALLER,
+ EMM_VPE1_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE1_WDT_SET_CHK_TIME,
+ EMM_VPE2_WDT_SET_CHK_CALLER,
+ EMM_VPE2_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE2_WDT_SET_CHK_TIME,
+ EMM_VPE3_WDT_SET_CHK_CALLER,
+ EMM_VPE3_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE3_WDT_SET_CHK_TIME,
+ EMM_VPE4_WDT_SET_CHK_CALLER,
+ EMM_VPE4_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE4_WDT_SET_CHK_TIME,
+ EMM_VPE5_WDT_SET_CHK_CALLER,
+ EMM_VPE5_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE5_WDT_SET_CHK_TIME,
+#if defined(__MD97__) || defined(__MD97P__)
+ EMM_VPE6_WDT_SET_CHK_CALLER,
+ EMM_VPE6_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE6_WDT_SET_CHK_TIME,
+ EMM_VPE7_WDT_SET_CHK_CALLER,
+ EMM_VPE7_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE7_WDT_SET_CHK_TIME,
+ EMM_VPE8_WDT_SET_CHK_CALLER,
+ EMM_VPE8_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE8_WDT_SET_CHK_TIME,
+ EMM_VPE9_WDT_SET_CHK_CALLER,
+ EMM_VPE9_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE9_WDT_SET_CHK_TIME,
+ EMM_VPE10_WDT_SET_CHK_CALLER,
+ EMM_VPE10_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE10_WDT_SET_CHK_TIME,
+ EMM_VPE11_WDT_SET_CHK_CALLER,
+ EMM_VPE11_WDT_SET_CHK_CALLERVPE,
+ EMM_VPE11_WDT_SET_CHK_TIME,
+#endif
+//WDT: Clear Check bit caller/callervpe/timestamp per VPE
+ EMM_VPE0_WDT_CLR_CHK_CALLER,
+ EMM_VPE0_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE0_WDT_CLR_CHK_TIME,
+ EMM_VPE1_WDT_CLR_CHK_CALLER,
+ EMM_VPE1_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE1_WDT_CLR_CHK_TIME,
+ EMM_VPE2_WDT_CLR_CHK_CALLER,
+ EMM_VPE2_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE2_WDT_CLR_CHK_TIME,
+ EMM_VPE3_WDT_CLR_CHK_CALLER,
+ EMM_VPE3_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE3_WDT_CLR_CHK_TIME,
+ EMM_VPE4_WDT_CLR_CHK_CALLER,
+ EMM_VPE4_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE4_WDT_CLR_CHK_TIME,
+ EMM_VPE5_WDT_CLR_CHK_CALLER,
+ EMM_VPE5_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE5_WDT_CLR_CHK_TIME,
+#if defined(__MD97__) || defined(__MD97P__)
+ EMM_VPE6_WDT_CLR_CHK_CALLER,
+ EMM_VPE6_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE6_WDT_CLR_CHK_TIME,
+ EMM_VPE7_WDT_CLR_CHK_CALLER,
+ EMM_VPE7_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE7_WDT_CLR_CHK_TIME,
+ EMM_VPE8_WDT_CLR_CHK_CALLER,
+ EMM_VPE8_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE8_WDT_CLR_CHK_TIME,
+ EMM_VPE9_WDT_CLR_CHK_CALLER,
+ EMM_VPE9_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE9_WDT_CLR_CHK_TIME,
+ EMM_VPE10_WDT_CLR_CHK_CALLER,
+ EMM_VPE10_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE10_WDT_CLR_CHK_TIME,
+ EMM_VPE11_WDT_CLR_CHK_CALLER,
+ EMM_VPE11_WDT_CLR_CHK_CALLERVPE,
+ EMM_VPE11_WDT_CLR_CHK_TIME,
+#endif
+//Reserved
+ EMM_Reserved1,
+ EMM_Reserved2,
+ EMM_MDCCCI_RECORD0,
+ EMM_MDCCCI_RECORD1,
+ EMM_MDCCCI_RECORD2,
+ EMM_MDCCCI_RECORD3,
+
+ EMM_HIFCLDMA_RECORD1,
+ EMM_HIFCLDMA_RECORD2,
+ EMM_HIFCLDMA_RECORD3,
+ EMM_HIFCLDMA_RECORD4,
+ EMM_HIFCLDMA_RECORD5,
+
+ EMM_INDEX_MAX,
+}EMM_LOG_INDEX;
+
+typedef enum {
+ EMM_EXCEPTION_RECORD = 0x0,
+ EMM_DBG_INFO,
+ EMM_BOOTUP_TRACE,
+} EMM_BUF_TYPE;
+
+typedef enum
+{
+ EMM_DIRECT_WRITE_IDLETASK,
+ EMM_DIRECT_WRITE_SLP,
+ EMM_DIRECT_WRITE_DORMANT,
+ EMM_DIRECT_WRITE_ELM,
+ EMM_DIRECT_WRITE_BUS,
+ EMM_DIRECT_WRITE_SWLA,
+ EMM_DIRECT_WRITE_NVRAM,
+ EMM_DIRECT_WRITE_MAX,
+} EMM_DIRECT_WRITE_SM_INDEX;
+
+extern const kal_uint32 g_EMM_BOOTTRC_INDEX_ADDR;
+
+extern kal_bool EMM_Init(void);
+extern kal_bool EMM_WriteBootupTrace(kal_uint32 block_idx, kal_uint32 index, kal_uint32 value);
+extern kal_bool EMM_WriteDbgInfo(kal_uint32 index, void* addr);
+extern kal_bool EMM_ClearDbgInfo(void);
+extern kal_bool EMM_GetBufInfo(kal_uint32 *pAddr, kal_uint32 *pSize, EMM_BUF_TYPE type);
+extern kal_bool EMM_DirInfo_Query(kal_uint32 index, kal_uint32 *addr, kal_uint32 *size);
+extern kal_bool EMM_Write_ExceptRecord(void);
+extern kal_bool EMM_Write_Ex_Steplogging(kal_uint32 vpeid);
+extern kal_bool EMM_Write_Ex_Count(kal_uint32 vpeid);
+extern kal_bool EMM_Write_Offending_Pcmon(void);
+extern kal_bool EMM_Set_RebootPattern(void);
+extern kal_bool EMM_SetSAPReboot_Pattern(kal_char *data, kal_uint32 len);
+#endif //__EX_MEM_MANAGER_PUBLIC_H__
+
diff --git a/mcu/interface/service/sst/ex_public.h b/mcu/interface/service/sst/ex_public.h
new file mode 100644
index 0000000..b7ec812
--- /dev/null
+++ b/mcu/interface/service/sst/ex_public.h
@@ -0,0 +1,389 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_public.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Header file for exception handling
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _EX_PUBLIC_H
+#define _EX_PUBLIC_H
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#include <mips_ia_utils_public.h>
+#endif /*__OFFLINE_EX_LOG_PARSER__*/
+/*******************************************************************************
+ * Globally Constant definition
+ *******************************************************************************/
+#define EX_FORCEMEMORYDUMP 0x26409001
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define EX_CC_LOG_SIZE (10*1024)
+#define EX_LOG_SIZE 3584
+#define TOTAL_EXPTR_SIZE EX_CC_LOG_SIZE /*for nvram */
+#define EX_LOG_SIZE_IN_HS1 (2*1024)
+#else
+#error No config yet
+#endif
+/*******************************************************************************
+ * Data Structure Definition - Common
+ *******************************************************************************/
+typedef enum {
+ BBREG_CALLBACK_STARTED,
+ BBREG_CALLBACK_DONE,
+} BBREG_BITMASK;
+/* bb register dump */
+typedef struct ex_bbreg_dump
+{
+ kal_uint32 *regions;
+ /* pointer to an array: base_1, len_1, type_1, base_2, len_2, type_2, ... */
+ /* type: 0 -- Default , Current : Byte Access */
+ /* 1 -- Byte Access */
+ /* 2 -- Word Access */
+ /* 4 -- 32-bit Access */
+ kal_bool (*bbreg_dump_callback)();
+ kal_char* owner;
+ kal_uint16 num; /* number of regions */
+ kal_bool is_registered;
+ kal_uint8 call_back_status;
+ void* next_dump;
+} EX_BBREG_DUMP_T;
+
+typedef enum{
+ EX_FULL_DUMP,
+ EX_MINI_DUMP,
+} ex_dump_level_enum;
+
+typedef enum{
+ EX_NO_CLEAN_SENSITIVE,
+ EX_CLEAN_SENSITIVE,
+} ex_sensitive_flag_enum;
+
+#if defined(__MTK_TARGET__)
+#define __NONCACHEDZI __attribute__ ((zero_init, section ("NONCACHEDZI")))
+#define EX_BBREG_DUMP __NONCACHEDZI EX_BBREG_DUMP_T
+#else
+#define EX_BBREG_DUMP EX_BBREG_DUMP_T
+#endif /*__MTK_TARGET__*/
+
+#if defined(__MTK_TARGET__)
+#define EX_MINIDUMP_SYMBOL_CLEAR
+#endif
+
+typedef enum ex_trace_type
+{
+ ex_trace_type_cadefa = 0,
+ ex_trace_type_common,
+ ex_trace_type_afound,
+} EX_TRACE_TYPE;
+
+typedef enum {
+ MINIDUMP_ITEM_CLEAN_STARTED,
+ MINIDUMP_ITEM_CLEAN_DONE,
+} MINIDUMP_ITEM_BITMASK;
+
+typedef enum {
+ EX_BOOT_MD = 0,
+ EX_BOOT_SYSTEM,
+ EX_POST_RESET_CORE_DUMP,
+} ex_boot_type;
+
+typedef struct ex_minidump_item
+{
+ kal_char* name;
+ kal_uint32 start;
+ kal_uint32 len;
+ kal_uint8 item_status;
+} EX_MINIDUMP_ITEM_T;
+
+typedef struct ex_minidump_clear_area EX_MINIDUMP_AREA_T;
+struct ex_minidump_clear_area
+{
+ EX_MINIDUMP_ITEM_T *regions;
+ kal_char* owner;
+ kal_uint16 num; /* number of regions */
+ kal_bool is_registered;
+ EX_MINIDUMP_AREA_T* next_dump;
+};
+#define CLEAR_SYMBOL_WHEN_MINIDUMP(symbol) {#symbol, (kal_uint32)&symbol, sizeof(symbol)}
+
+/*******************************************************************************
+ * Globally Exported function
+ *******************************************************************************/
+extern void ex_register_bbreg_dump(EX_BBREG_DUMP_T *dump, kal_char* filename);
+
+#if defined(EX_MINIDUMP_SYMBOL_CLEAR)
+extern void ex_register_minidump_area(EX_MINIDUMP_AREA_T *dump, kal_char* filename);
+extern void ex_clean_symbols();
+#else
+#define ex_register_minidump_area(dump, filename) {(void)(dump); (void)(filename);}
+#define ex_clean_symbols()
+#endif
+
+extern void ex_set_memorydump_level(ex_dump_level_enum dump_level);
+
+extern void ex_set_sensitive_flag(ex_sensitive_flag_enum sensitive_flag);
+extern ex_sensitive_flag_enum ex_get_sensitive_flag();
+extern kal_bool ex_isNested(void);
+extern kal_bool ex_set_reboot_type(ex_boot_type type);
+
+/*******************************************************************************
+ * Globally Exported macro
+ *******************************************************************************/
+#define INT_DefaultMemoryDumpFlag SHARED_VAR(g_INT_DefaultMemoryDumpFlag)
+#define INT_MemoryDumpFlag SHARED_VAR(g_INT_MemoryDumpFlag)
+#define INT_MemoryDumpLevel SHARED_VAR(g_INT_MemoryDumpLevel)
+
+/* memory dump related APIs */
+#if defined(__PRODUCTION_RELEASE__)
+/* production release: depends on set/clear's setting */
+#define ex_is_forcememorydump() (INT_MemoryDumpFlag == EX_FORCEMEMORYDUMP)
+#define ex_get_memorydump_flag(ptr) (*ptr = INT_MemoryDumpFlag)
+#else
+/* under construction !*/
+/* under construction !*/
+#if !defined(__FCS_SUPPORT__)
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* __PRODUCTION_RELEASE__ */
+#define ex_set_memorydump_flag() (INT_MemoryDumpFlag = EX_FORCEMEMORYDUMP)
+#define ex_clear_memorydump_flag() (INT_MemoryDumpFlag = 0)
+
+/* INT_DefaultMemoryDumpFlag is for Catcher/ELT to refer to disconnection behaviour */
+#define ex_get_default_memorydump_flag(ptr) (*ptr = INT_DefaultMemoryDumpFlag)
+#define ex_set_defult_memorydump_flag() (INT_DefaultMemoryDumpFlag = EX_FORCEMEMORYDUMP)
+#define ex_clear_default_memorydump_flag() (INT_DefaultMemoryDumpFlag = 0)
+
+#define EX_REGISTER_BBREG_DUMP(dump) \
+ do { \
+ ex_register_bbreg_dump(dump, (kal_char *)__FILE__); \
+ } while (0)
+
+#if defined(EX_MINIDUMP_SYMBOL_CLEAR)
+#define EX_REGISTER_MINIDUMP_AREA(dump, items) \
+ do { \
+ (dump)->regions = (EX_MINIDUMP_ITEM_T*)(items); \
+ (dump)->num = sizeof(items) / (sizeof(EX_MINIDUMP_ITEM_T)); \
+ ex_register_minidump_area((dump), (kal_char *)__FILE__); \
+ } while (0)
+#else
+#define EX_REGISTER_MINIDUMP_AREA(dump, items) {(void)(dump); (void)(items);}
+#endif
+/*******************************************************************************
+ * Globally Exported variables
+ *******************************************************************************/
+DECLARE_SHARED_VAR(kal_uint32, g_INT_DefaultMemoryDumpFlag)
+DECLARE_SHARED_VAR(kal_uint32, g_INT_MemoryDumpFlag )
+
+
+
+#ifdef __MTK_TARGET__
+#define sst_get_exception_count() miu_mfc0(MIU_C0_KSCRATCH3)
+#define INT_QueryExceptionStatus() (sst_get_exception_count() > 0)
+#else
+extern kal_uint8 sst_get_exception_count(void);
+extern kal_bool INT_QueryExceptionStatus(void);
+#endif
+
+#endif /* _EX_PUBLIC_H */
+
+
diff --git a/mcu/interface/service/sst/md32_access_ctrl_public.h b/mcu/interface/service/sst/md32_access_ctrl_public.h
new file mode 100644
index 0000000..336ec4b
--- /dev/null
+++ b/mcu/interface/service/sst/md32_access_ctrl_public.h
@@ -0,0 +1,77 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * md32_access_ctrl_public.h
+ *
+ * Project:
+ * --------
+ * UMOMLY
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef MD32_ACCESS_CTRL_PUBLIC_H
+#define MD32_ACCESS_CTRL_PUBLIC_H
+
+
+void INT_EnableMD32DBGEn(void);
+
+#endif /* MD32_ACCESS_CTRL_PUBLIC_H */
diff --git a/mcu/interface/service/sst/md32_boot_public.h b/mcu/interface/service/sst/md32_boot_public.h
new file mode 100644
index 0000000..66e8996
--- /dev/null
+++ b/mcu/interface/service/sst/md32_boot_public.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * md32_boot.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef MD32_BOOT_PUBLIC_H
+#define MD32_BOOT_PUBLIC_H
+
+typedef enum {
+ CORE_USIP,
+ CORE_RAKE,
+ CORE_SCQ16,
+ CORE_SONIC,
+ CORE_NUM,
+ CORE_MAX = 0xFFFFFFFF,
+} MD32_CORE_TYPE;
+
+#ifndef __MD32_PBP__
+#define HWITC_START kal_hrt_take_itc_lock(KAL_ITC_DSP_DOWNLOAD , KAL_INFINITE_WAIT)
+#define HWITC_END kal_hrt_give_itc_lock(KAL_ITC_DSP_DOWNLOAD)
+
+#include "kal_public_api.h"
+
+#if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6297) || defined(__MD97__) || defined(MT6779) || defined(__MD97P__)
+ #define SCQ_PM_CRC32_OFFSET 0x20
+ #define SCQ_DM_CRC32_OFFSET 0x24
+#if defined(MT6297) || defined(__MD97__) || defined(__MD97P__)
+ #define SCQ_GLOBAL_CON_base BASE_MADDR_INR0_SCQ_GLOBAL_CON
+ #define SHARE_PM_base BASE_MADDR_INR0_MEM
+ #define SHARE_DM_base BASE_MADDR_INR0_SHARED_DM
+ #define PRIVATE_DM0_base BASE_MADDR_INR0_LOCAL_DM
+ #define PRIVATE_DM1_base BASE_MADDR_INR0_LOCAL_DM_1
+ #define PRIVATE_DM2_base BASE_MADDR_INR0_LOCAL_DM_2
+ #define PRIVATE_DM3_base BASE_MADDR_INR0_LOCAL_DM_3
+ #define SCq16_0_CTRLREGS_base BASE_MADDR_INR0_SCQ_VU_CR
+ #define SCq16_1_CTRLREGS_base BASE_MADDR_INR0_SCQ_VU_CR_1
+ #define SCq16_2_CTRLREGS_base BASE_MADDR_INR0_SCQ_VU_CR_2
+ #define SCq16_3_CTRLREGS_base BASE_MADDR_INR0_SCQ_VU_CR_3
+#else
+ #define SCQ_GLOBAL_CON_base BASE_MADDR_BRAM_SCQ_GLOBAL_CON
+ #define SHARE_PM_base BASE_MADDR_BRAM_SCQ_SHARED_PM
+ #define SHARE_DM_base BASE_MADDR_BRAM_SCQ_SHARED_DM
+ #define PRIVATE_DM0_base BASE_MADDR_BRAM_SCQ0_LOCAL_DM
+ #define PRIVATE_DM1_base BASE_MADDR_BRAM_SCQ1_LOCAL_DM
+ #define SCq16_0_CTRLREGS_base BASE_MADDR_BRAM_SCQ0_VU_CR
+ #define SCq16_1_CTRLREGS_base BASE_MADDR_BRAM_SCQ1_VU_CR
+#endif
+#else
+ #error "need to define address for new chip"
+#endif
+
+
+/****************************/
+/*********** Init ***********/
+/****************************/
+extern kal_int32 MD32_Init();
+extern kal_int32 Coresonic_Init();
+
+
+/****************************/
+/********** Loader **********/
+/****************************/
+typedef enum {
+ MD32_LOADER_RAKE_RET_OK,
+ MD32_LOADER_USIP_RET_OK,
+#if defined(__MD97__) || defined(__MD97P__)
+ MD32_LOADER_SONIC_RET_OK,
+#endif
+ MD32_LOADER_RAKE_DDL_RET_OK,
+ MD32_LOADER_UNGATE_RET_OK,
+ MD32_LOADER_RET_DMA_RUNNING,
+ MD32_LOADER_RET_ERR,
+} MD32_LOADER_RET;
+
+extern MD32_LOADER_RET RAKE_Load();
+extern MD32_LOADER_RET USIP_Load();
+extern MD32_LOADER_RET SONIC_Load();
+extern MD32_LOADER_RET MD32_Ungate(MD32_CORE_TYPE md32_core);
+//MD32_LOADER_RET MD32_BootByDMA(MD32_BIN_TYPE *md32_bins, kal_uint32 bin_num);
+extern void Init_uSIP_bootuppattern();
+extern kal_bool is_rake_user_using_ddl_api();
+extern kal_bool can_sleep_flow_active_rake();
+extern kal_bool DSP_IsFirstMpuSettingDone(void);
+/****************************/
+/********** Query ***********/
+/****************************/
+typedef enum {
+ MD32_3G_FDD,
+ MD32_3G_TDD,
+} MD32_3G_MODE;
+
+typedef struct {
+ kal_uint32 pm_com;
+ kal_uint32 dm_com;
+ kal_uint32 pm_3g;
+ kal_uint32 dm_3g;
+ kal_uint32 pm_lte;
+ kal_uint32 dm_lte;
+ kal_uint32 pm_unused;
+ kal_uint32 dm_unused;
+} MD32_MEM_STATUS;
+
+const MD32_MEM_STATUS *MD32_GetBRPMemStatus(MD32_3G_MODE mode);
+const MD32_MEM_STATUS *MD32_GetDFEMemStatus(void);
+const MD32_MEM_STATUS *MD32_GetDFE1MemStatus(void);
+//kal_bool MD32_IsMD32Running(MD32_BIN_TYPE md32_type);
+
+/****************************/
+/********* Version **********/
+/****************************/
+/*
+const kal_char *MD32_GetProject(MD32_BIN_TYPE md32_type);
+const kal_char *MD32_GetFlavor(MD32_BIN_TYPE md32_type);
+const kal_char *MD32_GetLabel(MD32_BIN_TYPE md32_type);
+const kal_char *MD32_GetBuildTime(MD32_BIN_TYPE md32_type);
+*/
+
+/****************************/
+/********* RTLCOSIM *********/
+/****************************/
+#define BRP_RTLCOSIM_LTE (0x1)
+#define BRP_RTLCOSIM_FDD (0x1<<1)
+#define BRP_RTLCOSIM_TDD (0x1<<2)
+
+//void MD32_SetBRPMode_RTLCOSIM(kal_uint32 mode);
+//void MD32_Ungate_RTLCOSIM(MD32_BIN_TYPE md32_type);
+#endif /* __MD32_PBP__ */
+
+#endif /* MD32_BOOT_PUBLIC_H */
diff --git a/mcu/interface/service/sst/mddbg_public.h b/mcu/interface/service/sst/mddbg_public.h
new file mode 100644
index 0000000..2c4ce2e
--- /dev/null
+++ b/mcu/interface/service/sst/mddbg_public.h
@@ -0,0 +1,225 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mddbg_pulbic.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Modem debugging related implementation
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MDDBG_PUBLIC_H__
+#define __MDDBG_PUBLIC_H__
+// remove to enable MDDBG for Gen97 FPGA debug temporarily, let user call
+// mddbg_set_bp_int_shaolin_temp
+// mddbg_set_wp_int_shaolin_temp
+#if (defined(__MTK_SECURE_PLATFORM__) || defined(__PRODUCTION_RELEASE__) || !defined(__MTK_TARGET__))
+ #define DISABLE_MDDBG_FUNCTION
+#endif
+
+
+typedef enum MDDBG_HDL_TYPE_e {
+ MDDBG_HT_MEMDUMP,
+ MDDBG_HT_LOG,
+ MDDBG_HT_MAX,
+} MDDBG_HDL_TYPE;
+
+typedef enum MDDBG_WP_ACCESS_TYPE_e {
+ MDDBG_WAT_WRITE = 1,
+ MDDBG_WAT_READ,
+ MDDBG_WAT_RW,
+} MDDBG_WP_ACCESS_TYPE;
+
+typedef enum MDDBG_WP_MONITOR_BYTE_e {
+ MDDBG_WMB_1BYTE = 1,
+ MDDBG_WMB_2BYTES,
+ MDDBG_WMB_3BYTES,
+ MDDBG_WMB_4BYTES,
+ MDDBG_WMB_MAX,
+} MDDBG_WP_MONITOR_BYTE;
+
+typedef enum MDDBG_RESULT_e {
+ MDDBG_SUCCESS,
+ MDDBG_INVALID_PARAM,
+ MDDBG_BP_TOO_MANY,
+ MDDBG_BP_ALREADY_ENABLED,
+ MDDBG_BP_ALREADY_DISABLED,
+ MDDBG_WP_TOO_MANY,
+ MDDBG_WP_MON_OUT_OF_RANGE,
+ MDDBG_VPE_INDEX_OUT_OF_RANGE,
+ MDDBG_BP_INDEX_OUT_OF_RANGE,
+ MDDBG_WP_INDEX_OUT_OF_RANGE,
+ MDDBG_SHOULD_NOT_CALL_IN_SYSTEMINIT,
+} MDDBG_RESULT;
+
+typedef enum MDDBG_BP_NUM_e{
+ MDDBG_BP_0,
+ MDDBG_BP_1,
+#if defined (__MIPS_I7200__)
+ MDDBG_BP_2,
+ MDDBG_BP_3,
+#endif
+}MDDBG_BP_NUM;
+
+typedef enum MDDBG_WP_NUM_e{
+ MDDBG_WP_0,
+#if defined (__MIPS_I7200__)
+ MDDBG_WP_1,
+ MDDBG_WP_2,
+#endif
+}MDDBG_WP_NUM;
+
+
+typedef struct mddbg_bp_info {
+ kal_uint32 address;
+ kal_bool enable;
+} mddbg_bp_info_st;
+
+typedef struct mddbg_wp_info {
+ kal_uint32 address;
+ kal_uint32 mask;
+ MDDBG_WP_ACCESS_TYPE access_type;
+ kal_bool enable;
+} mddbg_wp_info_st;
+
+typedef struct mddbg_reg_t{
+ kal_uint32 ctrl_addr;
+ kal_uint32 watchHi;
+ kal_uint32 queryNum;
+}mddbg_reg_t;
+
+
+
+
+#define CONFIG_TAG_BP0 0 // should not be used here, because used as stack protection. Check: KAL_WATCHPOINT_3_SET
+#define CONFIG_TAG_BP1 1
+#define CONFIG_TAG_WP0 2
+#define CONFIG_TAG_WP1 3
+
+#define CONFIG_ADDRESS(addr) (addr << 3)
+#define CONFIG_EXCEPTION_TYPE_BIT 0X7
+#define CONFIG_WRITE 0x1
+#define CONFIG_READ 0x2
+#define CONFIG_INSTRUCTION 0x4
+#define CONFIG_MASK_BIT 0X1FF
+#define CONFIG_MASK(mask) (mask << 3)
+#define CONFIG_NO_MASK 0
+#define CONFIG_NIL_ADDR 0xdead0000
+
+#define CONFIG_VPE0 1
+#define CONFIG_VPE1 1 << 1
+#define CONFIG_VPE2 1 << 2
+#define CONFIG_VPE3 1 << 3
+
+#if defined(__MIPS_IA__)
+ #define CONFIG_MAX_VPE 4
+ #define CONFIG_VPE_ALL CONFIG_VPE0 | CONFIG_VPE1 | CONFIG_VPE2 | CONFIG_VPE3
+
+#elif defined(__MIPS_I7200__)
+
+ #define CONFIG_VPE4 1 << 4
+ #define CONFIG_VPE5 1 << 5
+ #define CONFIG_VPE6 1 << 6
+ #define CONFIG_VPE7 1 << 7
+ #define CONFIG_VPE8 1 << 8
+ #define CONFIG_VPE9 1 << 9
+ #define CONFIG_VPE10 1 << 10
+ #define CONFIG_VPE11 1 << 11
+
+ #define CONFIG_MAX_VPE 12
+ /* 12 bit is 0xfff, too painful to OR all above */
+ #define CONFIG_VPE_ALL 0xfff
+
+#endif
+
+
+MDDBG_RESULT mddbg_init_public(void);
+MDDBG_RESULT mddbg_set_breakpoint(kal_uint32 vpeIndexes, kal_uint32 selectBP, kal_uint32 bp_addr, kal_uint32 addr_mask);
+MDDBG_RESULT mddbg_set_watchpoint(kal_uint32 vpeIndexes, kal_uint32 selectWP, kal_uint32 wp_addr, kal_uint32 addr_mask, kal_uint32 type);
+MDDBG_RESULT mddbg_remove_watchpoint(kal_uint32 vpeIndexes, kal_uint32 selectWP);
+MDDBG_RESULT mddbg_remove_breakpoint(kal_uint32 vpeIndexes, kal_uint32 selectBP);
+MDDBG_RESULT mddbg_applyAll(void/*MDDBG_HDL_TYPE*/);
+MDDBG_RESULT mddbg_resetAll(void);
+MDDBG_RESULT mddbg_query(void);
+mddbg_reg_t mddbg_get_queryBPResult(kal_uint32 vpeInd, kal_uint32 selectBP);
+mddbg_reg_t mddbg_get_queryWPResult(kal_uint32 vpeInd, kal_uint32 selectWP);
+kal_uint32 mddbg_get_offender(kal_uint32 vpe,kal_uint32 watchpoint);
+#if defined (__MIPS_I7200__)
+MDDBG_RESULT mddbg_set_bp_int_shaolin_temp (kal_uint32 tcIndex, kal_uint32 selectBP, kal_uint32 bp_addr, kal_uint32 addr_mask);
+MDDBG_RESULT mddbg_set_wp_int_shaolin_temp (kal_uint32 tcIndex, kal_uint32 selectWP, kal_uint32 wp_addr, kal_uint32 addr_mask, kal_uint32 type);
+#endif
+
+#endif // __MDDBG_PUBLIC_H__
diff --git a/mcu/interface/service/sst/rake_api_public.h b/mcu/interface/service/sst/rake_api_public.h
new file mode 100644
index 0000000..3f1ce7f
--- /dev/null
+++ b/mcu/interface/service/sst/rake_api_public.h
@@ -0,0 +1,89 @@
+#ifndef RAKE_API_PUBLIC_H
+#define RAKE_API_PUBLIC_H
+
+#if defined(__MD97__) || defined(__MD97P__)
+#include "dsp_module_based_api_public.h"
+#else //defined(__MD97__)
+
+#include "dsp_control_public.h"
+
+/***************************************************************/
+/********* Enum for BootDoneCheck Return Value *************/
+/***************************************************************/
+typedef enum{
+ RAKE_NOTYETDONE,
+ RAKE_BOOTDONE,
+ RAKE_NOT_DEACTIVEDONE,
+ RAKE_DEACTIVEDONE
+}RAKE_BOOTDONECHECK_RETVALUE;
+
+#define RAKE_NOT_ACTIVEDONE RAKE_NOTYETDONE
+#define RAKE_ACTIVEDONE RAKE_BOOTDONE
+
+/***************************************************************/
+/********* Function Prototype **********************************/
+/***************************************************************/
+extern RAKE_BOOTDONECHECK_RETVALUE RAKE_BootDoneCheck(RAKE_API_USER);
+
+/* Common API */
+extern DSP_CONTROL_IDLE_FLAG_STATUS rake_check_idle_flag(RAKE_API_USER);
+extern kal_uint32 rake_ddl_check_idle_flag_bitmap(kal_uint32);
+extern kal_bool is_myself_duty_rat(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_uint32 return_dutyrat_of_thread(DSP_CDIF_CORE_ENUM);
+extern void firstboot_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/* Activate Relatives */
+extern void rake_activate(RAKE_API_USER);
+
+/* Deactivate Relatives */
+extern void rake_deactivate(RAKE_API_USER, CMIFZI_CTRL);
+extern RAKE_CONTROL_STATUS rake_deactive_done_check(RAKE_API_USER);
+
+/* DDL Relatives */
+extern void rake_ddl_start(RAKE_API_USER , DDL_MODE);
+extern void rake_ddl_status_mode_query(DDL_STATUS*, DDL_MODE*);
+extern kal_bool ddl_check_all_target_user_are_deactive(DSP_CDIF_CORE_ENUM);
+extern kal_bool ddl_has_rake_user_call_deactivate(kal_uint32);
+extern kal_uint32 dsp_check_ddl_user_status(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***************************************************************/
+/********* Function Definition *********************************/
+/***************************************************************/
+/***** Sleep Flow APIs for user *****/
+/* FirstBoot API */
+#define topsm_return_dutyrat_of_rake firstboot_topsm_query(DSP_CONTROL_RAKE)
+
+#define is_myself_duty_user_of_rake(user_id) is_myself_duty_rat(DSP_CONTROL_RAKE, user_id)
+/* First Boot Activate Use */
+#define rake_firstboot_activate(user_id) firstboot_activate(DSP_CONTROL_RAKE, user_id)
+
+/* Check idle APIs */
+#define rake_check_ddl_user_status(user_bitmap) dsp_check_ddl_user_status(DSP_CONTROL_RAKE, user_bitmap)
+#define dsp_rake_check_idle_flag(user_id) rake_check_idle_flag(user_id)
+
+/* Activate APIs*/
+#define dsp_rake_activate(user_id) rake_activate(user_id)
+
+/* Activate check APIs */
+#define dsp_rake_done_check(user_id) RAKE_BootDoneCheck(user_id)
+#define dsp_rake_active_done_check(user_id) RAKE_BootDoneCheck(user_id)
+
+/* Deactivate APIs */
+#define dsp_rake_deactivate(user_id) rake_deactivate(user_id, CMIFZI_EN)
+#define dsp_rake_deactivate_wo_cmifzi(user_id) rake_deactivate(user_id, CMIFZI_DIS)
+
+/* Deactivate check APIs */
+#define dsp_rake_deactive_done_check(user_id) rake_deactive_done_check(user_id)
+
+/***** DDL Flow APIs for user *****/
+// DDL check if RAKE is deactive
+#define ddl_l2tcm_is_rake_deactive() ddl_check_all_target_user_are_deactive(DSP_CONTROL_RAKE)
+
+// Trigger DDL
+#define dsp_rake_ddl_start(user_id, bin_mode) rake_ddl_start(user_id, bin_mode)
+
+// Check rake DDL mode/status
+#define dsp_rake_ddl_status_mode_query(status, bin_mode) rake_ddl_status_mode_query(status, bin_mode)
+
+#endif //defined(__MD97__)
+#endif /* RAKE_API_PUBLIC_H */
diff --git a/mcu/interface/service/sst/sst_interface.h b/mcu/interface/service/sst/sst_interface.h
new file mode 100644
index 0000000..460a8a9
--- /dev/null
+++ b/mcu/interface/service/sst/sst_interface.h
@@ -0,0 +1,139 @@
+#ifndef SST_INTERFACE_H
+#define SST_INTERFACE_H
+
+#include "nvram_data_items.h"
+
+#define SST_PROTECTED_NVRAM_LID_READ_LIMIT 0x1
+#define SST_PROTECTED_NVRAM_LID_WRITE_LIMIT 0x2
+
+typedef struct sst_protected_nvram_lid_struct {
+ nvram_lid_enum m_lid;
+ kal_uint16 m_attr;
+} SST_PROTECTED_NVRAM_LID;
+
+typedef struct sst_allowed_task_struct {
+ module_type m_mod_id;
+} SST_ALLOWED_TASK;
+
+/*
+ * Efuse region index definition
+ */
+#define EFUSE_IDX_C_DAT0 0
+#define EFUSE_IDX_C_DAT1 1
+#define EFUSE_IDX_C_DAT2 2
+#define EFUSE_IDX_C_DAT3 3
+#define EFUSE_IDX_C_DAT4 4
+#define EFUSE_IDX_C_DAT5 5
+#define EFUSE_IDX_C_CTRL0 6
+#define EFUSE_IDX_C_CTRL1 7
+
+/*SST Efuse blowing error code*/
+#define SST_EFUSE_BLOW_DONE 0
+#define SST_EFUSE_BLOW_AP_NOT_READY 0x10000000
+#define SST_EFUSE_BLOW_DATA_FAIL 0x20000000
+#define SST_EFUSE_BLOW_START_FAIL 0x40000000
+#define SST_EFUSE_BLOW_LOCK_FAIL 0x80000000
+#define SST_EFUSE_BLOW_END_FAIL 0x01000000
+#define SST_EFUSE_BLOW_BIT_NOT_SUPPORT 0x02000000
+#define SST_EFUSE_BLOW_REGION_NOT_SUPPORT 0x04000000
+#define SST_EFUSE_BLOW_CHIP_NOT_SUPPORT 0x08000000
+#define SST_EFUSE_BLOW_NOT_INIT 0x00100000
+#define SST_EFUSE_BLOW_PROCESS_FAIL 0x00200000
+#define SST_EFUSE_BLOW_REINIT_FAIL 0x00400000
+#define SST_EFUSE_BLOW_CCCI_FAIL 0x00800000
+
+/*****************************************************************************
+ * FUNCTION
+ * SST_Get_ChipRID
+ *
+ * DESCRIPTION
+ * The function returns per-chip random ID to the caller.
+ *
+ * PARAMETERS
+ * [INPUT/OUTPUT] pRid : The buffer that is used to store the per-chip random ID.
+ * [INPUT] buf_len : Length that the caller wants for the per-chip random ID in "bits".
+ *
+ * RETURNS
+ * KAL_TRUE : Get random ID Success
+ * KAL_FALSE : Get random ID failed
+ *
+ * NOTES
+ * N/A
+ *
+ *****************************************************************************/
+extern kal_bool SST_Get_ChipRID(kal_char *pRid, kal_int32 buf_len);
+
+
+/*****************************************************************************
+ * FUNCTION
+ * SST_Get_ChipRK
+ *
+ * DESCRIPTION
+ * The function returns per-chip random key to the caller.
+ *
+ * PARAMETERS
+ * [INPUT/OUTPUT] key : The buffer that is used to store the per-chip random key.
+ * [INPUT] len : Length that the caller wants for the per-chip random key in bytes.
+ *
+ * RETURNS
+ * KAL_TRUE : Get random key Success
+ * KAL_FALSE : Get random key failed
+ *
+ * NOTES
+ * N/A
+ *
+ *****************************************************************************/
+extern kal_bool SST_Get_ChipRK(kal_char *key, kal_int32 len);
+
+/*************************************************************************
+* FUNCTION
+* SST_Get_EFUSE_Data
+*
+* DESCRIPTION
+* This function get specified length of efuse data and put in the buffer
+*
+* PARAMETERS
+* data_type - efuse field
+* buf - pointer to the buffer to store efuse data
+* len - efuse data length expected to read
+*
+* RETURNS
+* KAL_TRUE/KAL_FALSE
+*
+*************************************************************************/
+typedef enum{
+ AP_SBC_EN = 1,
+ C_CTRL0,
+ C_CTRL1,
+ C_DAT0,
+ C_DAT1,
+ C_DAT2,
+ C_DAT3,
+ C_DAT4,
+ C_DAT5,
+ C_DAT6,
+ C_DAT7,
+}EFUSE_DATA_TYPE;
+
+
+kal_bool SST_Get_EFUSE_Data(EFUSE_DATA_TYPE data_type, kal_uint8* buf, kal_uint8 len);
+
+/*************************************************************************
+* FUNCTION
+* SST_ilm_inject_check
+*
+* DESCRIPTION
+* This function checks whether input ILM is permitted to access the specified NVRAM LID
+*
+* PARAMETERS
+* ilm_ptr - read/write request ILM
+*
+* RETURNS
+* KAL_TRUE/KAL_FALSE
+* KAL_TRUE: The access is permitted, i.e. pass checking successfully
+* KAL_FALSE: The access is prohibited, i.e. fails checking
+*************************************************************************/
+
+kal_uint32 SST_ilm_inject_check(ilm_struct *ilm_ptr);
+
+#endif
diff --git a/mcu/interface/service/sst/sst_temp_ex_handlers.h b/mcu/interface/service/sst/sst_temp_ex_handlers.h
new file mode 100644
index 0000000..a1a0f2e
--- /dev/null
+++ b/mcu/interface/service/sst/sst_temp_ex_handlers.h
@@ -0,0 +1,176 @@
+#ifndef __SST_TEMP_EX_HANDLERS_H__
+#define __SST_TEMP_EX_HANDLERS_H__
+
+.extern error_epc_trap
+
+/* The assembly instructions in two parts have no difference.
+ Must keep nop in BD slot, even the ISA has no BD slot.(keep consistency)
+ The macro user/caller may(or not) include regbase.h */
+
+
+.macro INSTALL_TEMP_EXCEPTION_VECTOR
+.set push
+.set noreorder
+
+#if defined(_MIPS_REGDEF_H_)
+/* reg symbols would be replaced by those defined in regbase.h */
+
+ la a0, INT_TEMP_general_ex_vector
+ ins a0, zero, 0, 12
+ ori a0, a0, EBASE_WG
+ mtc0 a0, C0_EBASE
+ ehb
+
+#if !defined(__MIPS_I7200__) /* I7200 CFG5.K & CV are RO */
+ li a0, 0
+ li a1, 0x1
+ ins a0, a1, CFG5_CV_SHIFT, 1
+ ins a0, a1, CFG5_K_SHIFT, 1
+ mtc0 a0, C0_CONFIG5
+ ehb
+#endif
+
+#if defined(__MIPS_I7200__)
+ li a0, 0x38 /* write 1 to clear */
+#else
+ li a0, 0x7
+#endif
+ mtc0 a0, C0_WATCHHI
+ mtc0 zero, C0_WATCHLO
+ mtc0 a0, C0_WATCHHI, 1
+ mtc0 zero, C0_WATCHLO, 1
+ mtc0 a0, C0_WATCHHI, 2
+ mtc0 zero, C0_WATCHLO, 2
+ mtc0 a0, C0_WATCHHI, 3
+ mtc0 zero, C0_WATCHLO, 3
+#if defined(__MIPS_I7200__)
+ mtc0 a0, C0_WATCHHI, 4
+ mtc0 zero, C0_WATCHLO, 4
+ mtc0 a0, C0_WATCHHI, 5
+ mtc0 zero, C0_WATCHLO, 5
+ mtc0 a0, C0_WATCHHI, 6
+ mtc0 zero, C0_WATCHLO, 6
+ mtc0 a0, C0_WATCHHI, 7
+ mtc0 zero, C0_WATCHLO, 7
+#endif
+
+ la a0, error_epc_trap
+ mtc0 a0, C0_ERRPC
+ mtc0 zero, C0_CAUSE
+ mtc0 zero, C0_COMPARE
+ mtc0 zero, C0_KSCRATCH3 // zero scratch3 for exception status
+ mtc0 zero, C0_STATUS // write C0_STATUS
+ ehb
+
+#else /* _MIPS_REGDEF_H_ */
+
+ la $a0, INT_TEMP_general_ex_vector
+ ins $a0, $zero, 0, 12
+ ori $a0, $a0, EBASE_WG
+ mtc0 $a0, C0_EBASE
+ ehb
+
+#if !defined(__MIPS_I7200__) /* I7200 CFG5.K & CV are RO */
+ li $a0, 0
+ li $a1, 0x1
+ ins $a0, $a1, CFG5_CV_SHIFT, 1
+ ins $a0, $a1, CFG5_K_SHIFT, 1
+ mtc0 $a0, C0_CONFIG5
+ ehb
+#endif
+
+
+#if defined(__MIPS_I7200__)
+ li $a0, 0x38 /* write 1 to clear */
+#else
+ li $a0, 0x7 /* write 1 to clear */
+#endif
+ mtc0 $a0, C0_WATCHHI
+ mtc0 $zero, C0_WATCHLO
+ mtc0 $a0, C0_WATCHHI, 1
+ mtc0 $zero, C0_WATCHLO, 1
+ mtc0 $a0, C0_WATCHHI, 2
+ mtc0 $zero, C0_WATCHLO, 2
+ mtc0 $a0, C0_WATCHHI, 3
+ mtc0 $zero, C0_WATCHLO, 3
+#if defined(__MIPS_I7200__)
+ mtc0 $a0, C0_WATCHHI, 4
+ mtc0 $zero, C0_WATCHLO, 4
+ mtc0 $a0, C0_WATCHHI, 5
+ mtc0 $zero, C0_WATCHLO, 5
+ mtc0 $a0, C0_WATCHHI, 6
+ mtc0 $zero, C0_WATCHLO, 6
+ mtc0 $a0, C0_WATCHHI, 7
+ mtc0 $zero, C0_WATCHLO, 7
+#endif
+
+ la $a0, error_epc_trap
+ mtc0 $a0, C0_ERRPC
+ mtc0 $zero, C0_CAUSE
+ mtc0 $zero, C0_COMPARE
+ mtc0 $zero, C0_KSCRATCH3 // $zero scratch3 for exception status
+ mtc0 $zero, C0_STATUS // write C0_STATUS
+ ehb
+
+#endif
+
+.set pop
+.endm INSTALL_TEMP_EXCEPTION_VECTOR
+
+
+
+
+
+.macro RESET_EXCEPTION_SP_ARRAY
+.set push
+.set noreorder
+ /* Only Core0 VPE0 do exception stack reset. SST_Exception_SP is set to $zero for exception vector
+ * to know if we are in early boot flow or in dormant flow.
+ */
+
+#if defined(_MIPS_REGDEF_H_)
+/* reg symbols would be replaced by those defined in regbase.h */
+
+ mfc0 a0, C0_EBASE
+ ext a0, a0, 0, 10
+#if defined(__MIPS_I7200__)
+ srl a1, a0, 2
+ subu a0, a0, a1
+#endif
+ bgtz a0, INT_excep_sp_reset_done
+ nop
+
+ li a0, 0xFFFFFFFF
+ la a1, dormant_exception_area_ptr
+ sw a0, 0(a1)
+
+INT_excep_sp_reset_done:
+ // function end!
+
+#else /* _MIPS_REGDEF_H_ */
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 0, 10
+#if defined(__MIPS_I7200__)
+ srl $a1, $a0, 2
+ subu $a0, $a0, $a1
+#endif
+ bgtz $a0, INT_excep_sp_reset_done
+ nop
+
+ li $a0, 0xFFFFFFFF
+ la $a1, dormant_exception_area_ptr
+ sw $a0, 0($a1)
+
+INT_excep_sp_reset_done:
+ // function end!
+
+#endif
+
+.set pop
+.endm RESET_EXCEPTION_SP_ARRAY
+
+
+
+
+#endif // __SST_TEMP_EX_HANDLERS_H__
diff --git a/mcu/interface/service/sst/swla_public.h b/mcu/interface/service/sst/swla_public.h
new file mode 100644
index 0000000..7984c83
--- /dev/null
+++ b/mcu/interface/service/sst/swla_public.h
@@ -0,0 +1,43 @@
+#ifndef SWLA_PUBLIC_H
+#define SWLA_PUBLIC_H
+
+#include "kal_public_defs.h"
+
+
+typedef enum
+{
+ SA_stop = 0,
+ SA_start = 1,
+ SA_label = 2
+} SA_ACTION_T;
+
+typedef enum
+{
+ TAG_NEST_BEGIN = 0xE0,
+ TAG_NEST_END = 0xE1,
+ TAG_SINGLE_LABEL = 0xE2,
+ TAG_BEGIN_POINT = 0xE3,
+ TAG_END_POINT = 0xE4,
+ TAG_VPE1_CHILD_BEGIN = 0xE5,
+ TAG_VPE1_CHILD_END = 0xE6,
+ TAG_CPU_FREQUENCY = 0xE7
+} SA_TAG_T;
+
+
+
+
+
+kal_uint32 SLA_Enable(void);
+kal_uint32 SLA_Disable(void);
+kal_uint32 SLA_Respond(void);
+kal_uint32 SLA_Pause(void);
+
+
+void SLA_CustomLogging(kal_char *customJob, SA_ACTION_T saAction);
+void SLA_CustomLogging_NoEMM(kal_char *customJob, SA_ACTION_T saAction);
+void SLA_HWLogging(kal_char *customJob, SA_ACTION_T saAction);
+void SLA_VPE1ChildFunctionLogging(kal_uint32 index, SA_ACTION_T saAction, kal_uint8 TCID, kal_uint8 coreID) DECLARE_MIPS16;
+
+
+
+#endif
diff --git a/mcu/interface/service/sst/swtr_public.h b/mcu/interface/service/sst/swtr_public.h
new file mode 100644
index 0000000..5f8df0a
--- /dev/null
+++ b/mcu/interface/service/sst/swtr_public.h
@@ -0,0 +1,4 @@
+#ifndef SWTR_PUBLIC_H
+#define SWTR_PUBLIC_H
+
+#endif
diff --git a/mcu/interface/service/sst/system_profiler_public.h b/mcu/interface/service/sst/system_profiler_public.h
new file mode 100644
index 0000000..744358a
--- /dev/null
+++ b/mcu/interface/service/sst/system_profiler_public.h
@@ -0,0 +1,611 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * system_profiler.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef SYSPROFILER_PUBLIC_H
+#define SYSPROFILER_PUBLIC_H
+
+#include "swla_public.h"
+#include "mcu_pmu_montr_public.h"
+#include "kal_public_defs.h"
+#include "cpu_info.h"
+#include "ex_public.h"
+
+
+typedef enum {
+ SYSPRO_SW_SWLA_MODE = 0,
+ SYSPRO_SW_SWTR_MODE,
+ SYSPRO_MODE_END
+}SYSPRO_MODE;
+
+typedef enum
+{
+ SYSPRO_CORE0 = 0,
+ SYSPRO_CORE1,
+#if defined(__MD95__)
+#ifndef __MD95_IS_2CORES__
+ SYSPRO_CORE2,
+#endif // ifndef(__MD95_IS_2CORES__)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ SYSPRO_CORE2,
+ SYSPRO_CORE3,
+#endif
+ SYSPRO_NUM
+}SYSPRO_MCU_CORE;
+
+
+#if defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__) && !defined(__ESL_HRT__)
+
+#if defined(__MD95__)
+
+#define __SYSTEM_PROFILER_ON__
+#define __SWLA_SNAPSHOT_FEATURE__
+#define __SWLA_SNAPSHOT_FEATURE_DEBUG__
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define __SYSTEM_PROFILER_ON__
+#define __SYSPRO_DEFAULT_MIN_BUFF_SIZE__
+//#define __SWLA_SNAPSHOT_FEATURE__
+//#define __SWLA_SNAPSHOT_FEATURE_DEBUG__
+
+#else
+ #error "Unsupported chip"
+#endif
+#endif
+
+/* DHL will call PMU API. So APIs should be exported to be linked.*/
+#if defined(__MTK_TARGET__)
+#define __SWLA_MIPS_PMU_EXIST__
+#endif
+
+#define MAX_SYSPRO_NUMBER (SYS_MCU_NUM_CORE)
+#define MAX_SWLA_NUMBER (SYS_MCU_NUM_CORE)
+#define MAX_SWTR_NUMBER (SYS_MCU_NUM_CORE)
+#define MAX_SW_SWTR_NUMBER (SYS_MCU_NUM_CORE)
+#define BASIC_INFO_SIZE (8)
+#define SYSPROFILER_INITCORE (0)
+#define SYSPRO_HW_SWTR_DEFAULT_SAMPLE_RATE (4096)
+
+#if defined(__MD95__)
+#define MAX_TC_NUMBER (4)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define MAX_TC_NUMBER (6)
+#else
+ #error "Unsupported chip"
+#endif
+
+#if defined(__MD95__)
+#define SYS_PRO_HEADER_MINOR_VER (3)
+#define SYS_PRO_HEADER_MAJOR_VER (1)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define SYS_PRO_HEADER_MINOR_VER (0)
+#define SYS_PRO_HEADER_MAJOR_VER (4)
+#else
+ #error "Unsupported chip"
+#endif
+#define SYS_PRO_HEADER_PADDING (0)
+#define SYS_PRO_HEADER_MAGIC (0xEE)
+
+/*
+ * IF extra add-on parts are required, please modify this following number
+ */
+// 14 is the number of ASM add-on (6 built-in and 8 extra data) --> but current is no ASM, can change
+#define MAX_ADDON_INFO_NUM 14
+#define MAX_PLATFORM_NAME_LEN 16
+#define MAX_FLAVOR_NAME_LEN 32
+#define MAX_SW_LABEL_LEN 64
+#define HEADER_SCRATCHPAD_LEN 128
+
+typedef struct SysProfiler_SummayHeader_T
+{
+ // version Info: since ver 1.03
+ kal_uint8 minor_ver;
+ kal_uint8 major_ver;
+ kal_uint8 padding;
+ kal_uint8 magic; // should always be 0xEE
+
+#if defined(__MD95__) // version Info: since ver1.03(For Gen93/95)
+ kal_uint32 header_sz;
+ kal_uint32 main_desc_sz;
+#elif defined(__MD97__) || defined(__MD97P__) // version Info: since ver4.0 (For Gen97)
+ kal_uint8 vpe0_ic_info;
+ kal_uint8 vpe1_ic_info;
+ kal_uint8 vpe2_ic_info;
+ kal_uint8 vpe3_ic_info;
+ kal_uint32 platform_info;
+#else
+ #error "Unsupported chip"
+#endif
+ kal_uint32 addon_desc_sz;
+} SysProfiler_SummaryHeader;
+
+typedef struct SysProfiler_MainDescHeader_T
+{
+ kal_char mode_name[4];
+ kal_uint32 core_id;
+ kal_uint32 mdsys_timebase;
+ kal_uint32 modemsys_timebase_low;
+ kal_uint32 modemsys_timebase_high;
+ kal_uint32 log_sz;
+ kal_uint32 raw_begin_pos;
+#if defined(__MD97__) || defined(__MD97P__)
+ kal_uint32 cpu_clock_mhz;
+#else
+ kal_uint32 padding;
+#endif
+ kal_char platformName[MAX_PLATFORM_NAME_LEN];
+ kal_char flavorName[MAX_FLAVOR_NAME_LEN];
+ kal_char SWLabel[MAX_SW_LABEL_LEN];
+} SysProfiler_MainDescHeader;
+
+typedef struct SysProfiler_AddonDescHeader_T
+{
+ kal_uint32 log_sz;
+ kal_char ext_name[12];
+} SysProfiler_AddonDescHeader;
+
+typedef struct SysProfiler_LoggingHeader_T
+{
+ SysProfiler_SummaryHeader summary;
+ SysProfiler_MainDescHeader main_desc;
+ SysProfiler_AddonDescHeader addon_info[MAX_ADDON_INFO_NUM];
+ kal_char header_padding[HEADER_SCRATCHPAD_LEN]; /* SPV scratchpad, content will be output to header region of sla.bins */
+} SysProfiler_LoggingHeader;
+
+typedef struct SysProfiler_DumpMemoryInfo_T
+{
+ kal_uint32 base_addr1;
+ kal_uint32 length1;
+ kal_uint32 base_addr2;
+ kal_uint32 length2;
+} SysProfiler_DumpMemInfo;
+
+#if defined(__MD95__)
+#if defined(__SWLA_MIPS_PMU_EXIST__)
+typedef struct SysProfiler_PMCSettingParameter_T
+{
+ SYSPRO_MODE mode;
+ SYSPRO_MCU_CORE coreID;
+ kal_uint8 TCID;
+ IAPMU_MONITOR_EVENT_TYPE PMC0Event;
+ IAPMU_MONITOR_TARGET_TYPE PMC0Type;
+ IAPMU_MONITOR_EVENT_TYPE PMC1Event;
+ IAPMU_MONITOR_TARGET_TYPE PMC1Type;
+} SysProfiler_PMCSettingParameter;
+
+typedef struct SysProfiler_DHLPMCParameter_T
+{
+ SysProfiler_PMCSettingParameter parameter[MAX_SWLA_NUMBER * MAX_TC_NUMBER];
+} SysProfiler_DHLPMCParameter;
+
+typedef struct SysProfiler_PMCSettingLocalParameterForILM_T
+{
+ LOCAL_PARA_HDR
+ SysProfiler_PMCSettingParameter parameter[MAX_TC_NUMBER];
+} SysProfiler_PMCSettingLocalParameterForILM;
+
+#endif
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define SYSPROFILER_CM2_NUM 4
+typedef struct CM2ConfigParameter_T
+{
+ kal_uint32 Event;
+ kal_uint32 Qualifier;
+ kal_uint32 BegAddr;
+ kal_uint32 EndAddr;
+ kal_uint32 VPEMask;
+}CM2ConfigParameter;
+
+#define SYSPROFILER_PMC_NUM 4
+typedef struct PMCConfigParameter_T
+{
+ kal_uint32 Event;
+ kal_uint32 Type;
+}PMCConfigParameter;
+
+typedef struct SysProfiler_CM2SettingParameter_T
+{
+ SYSPRO_MODE mode;
+ SYSPRO_MCU_CORE coreID;
+ CM2ConfigParameter CM2_parameter[SYSPROFILER_CM2_NUM];
+}SysProfiler_CM2SettingParameter;
+
+typedef struct SysProfiler_PMCSettingParameter_T
+{
+ SYSPRO_MODE mode;
+ SYSPRO_MCU_CORE coreID;
+ PMCConfigParameter PMC_parameter[SYSPROFILER_PMC_NUM];
+} SysProfiler_PMCSettingParameter;
+
+typedef struct SysProfiler_DHLPMCParameter_T
+{
+ SysProfiler_PMCSettingParameter parameter[MAX_SWLA_NUMBER * MAX_TC_NUMBER];
+} SysProfiler_DHLPMCParameter;
+
+typedef struct SysProfiler_PMCSettingLocalParameterForILM_T
+{
+ LOCAL_PARA_HDR
+ SysProfiler_PMCSettingParameter parameter;
+} SysProfiler_PMCSettingLocalParameterForILM;
+
+#else
+ #error "Unsupported chip"
+#endif
+
+
+typedef enum
+{
+ SYSPRO_SW_ADDON,
+ SYSPRO_ADDON_TYPE_END,
+} SYSPROFILER_ADDON_TYPE;
+
+typedef enum
+{
+ SYSPRO_SWLA_ADDON,
+ SYSPRO_SWTR_ADDON,
+ SYSPRO_ADDON_PROFILER_TYPE_END,
+} SYSPROFILER_ADDON_PROFILER_TYPE;
+
+typedef enum{
+ SYSPRO_ERROR_CODE_SUCCESS = 0,
+ SYSPRO_ERROR_CODE_START = 0x10,
+ SYSPRO_ERROR_CODE_BUFFER_TOO_SMALL,
+ SYSPRO_ERROR_CODE_BUFFER_TOO_LARGE,
+ SYSPRO_ERROR_CODE_WRONG_MODE,
+ SYSPRO_ERROR_CODE_WAIT_IDLE_FAIL,
+ SYSPRO_ERROR_CODE_OVER_ADDON_INDEX,
+ SYSPRO_ERROR_CODE_OVER_ADDON_SIZE,
+ SYSPRO_ERROR_CODE_INVALID_SAMPLE_RATE,
+ SYSPRO_ERROR_CODE_SW_START = 0x20,
+ SYSPRO_ERROR_CODE_SWLA_ALREADY_ENABLE,
+ SYSPRO_ERROR_CODE_SWLA_RAM_BUFFER_IN_USED,
+ SYSPRO_ERROR_CODE_SWTR_ALREADY_ENABLE,
+ SYSPRO_ERROR_CODE_SWTR_RAM_BUFFER_IN_USED,
+ SYSPRO_ERROR_CODE_OUT_OF_SUPPORT_COREID,
+ SYSPRO_ERROR_CODE_INVALID_MODE,
+ SYSPRO_ERROR_CODE_BUFFER_ADDRESS_SIZE,
+ SYSPRO_ERROR_CODE_PROFILER_NOT_ENABLE,
+ SYSPRO_ERROR_CODE_INVALID_PROFILER_ADDON,
+ SYSPRO_ERROR_CODE_INVALID_ADDON_OPTION,
+ SYSPRO_ERROR_CODE_NO_ADDON_AVAILABLE,
+ SYSPRO_ERROR_CODE_NO_EXTRA_ADDON_AVAILABLE,
+ SYSPRO_ERROR_CODE_DUPLICATED_ADDON,
+ SYSPRO_ERROR_CODE_NULL_FUNCTION_PTR,
+ SYSPRO_ERROR_CODE_PMC_PARAMETER_INVALID,
+ SYSPRO_ERROR_CODE_DEPRECATED_FUNCTION,
+ SYSPRO_ERROR_CODE_NO_AVAILABLE_SNAPSHOT_BUFFER,
+ SYSPRO_ERROR_CODE_SNAPSHOT_AGAIN_IN_SHORT_TIME,
+ SYSPRO_ERROR_CODE_NO_SUPPORT_DUMP_LEVEL,
+ SYSPRO_ERROR_CODE_INIT_FAIL,
+
+
+ SYSPRO_ERROR_CODE_CORE_0 = 0x0000,
+ SYSPRO_ERROR_CODE_CORE_1 = 0x0100,
+ SYSPRO_ERROR_CODE_CORE_2 = 0x0200,
+ SYSPRO_ERROR_CODE_CORE_3 = 0x0300,
+ //SYSPRO_ERROR_CODE_MCU_ASM = 0x0400,
+ //SYSPRO_ERROR_CODE_INFRA_ASM = 0x0500,
+
+ SYSPRO_ERROR_CODE_END,
+} SYSPROFILER_ERROR_CODE;
+
+
+#if defined(__SWLA_SNAPSHOT_FEATURE__)
+
+typedef enum
+{
+ SYSPRO_SNAPSHOT_CORE_IDLE,
+ SYSPRO_SNAPSHOT_CORE_START,
+ SYSPRO_SNAPSHOT_CORE_DONE
+} SYSPROFILER_SNAPSHOT_CORE_STATUS_TYPE ;
+
+
+typedef enum
+{
+ SYSPRO_SNAPSHOT_BUFF_INDEX_0,
+/*
+ SYSPRO_SNAPSHOT_BUFF_INDEX_1,
+ SYSPRO_SNAPSHOT_BUFF_INDEX_2,
+ SYSPRO_SNAPSHOT_BUFF_INDEX_3,
+ SYSPRO_SNAPSHOT_BUFF_INDEX_4,
+ SYSPRO_SNAPSHOT_BUFF_INDEX_5,
+ SYSPRO_SNAPSHOT_BUFF_INDEX_19=19,
+*/
+ SYSPRO_SNAPSHOT_BUFF_NUM,
+ SYSPRO_SNAPSHOT_BUFF_COMMON, /* Reserved for common case */
+ SYSPRO_SNAPSHOT_BUFF_HRT_FAIL, /* For Hard-Read-Time fail case */
+ SYSPRO_SNAPSHOT_BUFF_END = 0xFFFFFFFF /* Force this enum 32bit */
+} SYSPROFILER_SNAPSHOT_BUFF_ID_ENUM ;
+
+/* if this structure change, should also modify tool */
+typedef struct SysProifler_Snapshot_Core_t
+{
+ kal_uint32 seg1_src_addr;
+ kal_uint32 seg1_dst_addr;
+ kal_uint32 seg1_size;
+ kal_uint32 seg1_gdma_result;
+ kal_uint32 seg2_src_addr;
+ kal_uint32 seg2_dst_addr;
+ kal_uint32 seg2_size;
+ kal_uint32 seg2_gdma_result;
+ kal_uint32 lisr_used;
+ kal_uint32 lisr_in_time;
+ kal_uint32 lisr_out_time;
+ SysProfiler_LoggingHeader header;
+ SYSPROFILER_ERROR_CODE err_code;
+ SYSPROFILER_SNAPSHOT_CORE_STATUS_TYPE status;
+ SYSPRO_MODE mode;
+
+} SysProfiler_Snapshot_Core;
+
+/* if this structure change, should also modify tool */
+typedef struct SysProfiler_Snapshot_Info_t
+{
+ kal_uint32 has_snapshot;
+ kal_uint32 trigger_time_us;
+ kal_uint32 trigger_time_tick;
+ kal_uint32 trigger_vpe;
+ kal_uint32 caller;
+ SysProfiler_Snapshot_Core core[MAX_SYSPRO_NUMBER];
+}SysProfiler_Snapshot_Info;
+
+#endif
+
+typedef enum
+{
+ SYSPRO_MIN_BUFF_SIZE,
+ SYSPRO_MAX_BUFF_SIZE,
+ SYSPRO_CUSTOM_BUFF_SIZE,
+}SYSPROFILER_ADJUST_BUFF_TYPE;
+
+#define IS_SWLA_MODE(MODE) ( MODE == SYSPRO_SW_SWLA_MODE )
+#define IS_SWTR_MODE(MODE) ( MODE == SYSPRO_SW_SWTR_MODE )
+
+void SysProfiler_Init(void);
+kal_uint32 SysProfiler_Start(void);
+kal_uint32 SysProfiler_StartCoreProfilerByMode( SYSPRO_MODE mode, kal_uint32 samplingRate);
+kal_uint32 SysProfiler_StartPlatformProfilerByMode( SYSPRO_MODE mode, kal_uint32 sysSamplingRate, kal_uint32 infraSamplingRate);
+kal_uint32 SysProfiler_Stop(void);
+kal_uint32 SysProfiler_StopCoreProfiler(void);
+kal_uint32 SysProfiler_StopPlatformProfiler(void);
+void SysProfiler_ASMStop(void);
+SYSPROFILER_ERROR_CODE SysProfiler_SetMode(SYSPRO_MODE mode);
+SYSPROFILER_ERROR_CODE SysProfiler_SetSampleRate(kal_uint32 sampleRate);
+kal_uint32 SysProfiler_RetriveHeader( kal_uint8** headerStartAddress, kal_uint32* headerSize, kal_uint8 coreID);
+kal_uint32 SysProfiler_RetriveLoggingBuffer(kal_uint32 **info, kal_uint16 *count, kal_uint8* region_config, kal_uint8 coreID);
+kal_bool SysProfiler_CheckRAMAvailability(kal_uint32 idx, kal_uint8 coreID);
+SYSPROFILER_ERROR_CODE SysProfiler_RegisterAddon( SYSPROFILER_ADDON_TYPE addonType, kal_uint32 addonSize, kal_char addonName[], void (*SYSPRO_AddonInfoInitFunc)(void), void *SA_AddonInfoLoggingFunc, kal_bool SA_SwapOutLogging, SYSPROFILER_ADDON_PROFILER_TYPE profilerType, SYSPRO_MCU_CORE coreID);
+kal_bool SysProfiler_QueryCoreProfilerModeAndRunningStatus( SYSPRO_MODE* returnMode, kal_bool* returnRunningStatus);
+kal_bool SysProfiler_QueryPlatformProfilerModeAndRunningStatus( SYSPRO_MODE* returnMode, kal_bool* returnRunningStatus);
+kal_bool SysProfiler_QueryAddonExist(char *addonPrefix, SYSPRO_MODE mode, kal_uint32 coreID);
+kal_bool SysProfiler_QueryHeaderScratchpad(kal_uint8 coreID, kal_uint8** addr, kal_uint32* size, kal_uint32* header_offset);
+
+#if defined(__SWLA_MIPS_PMU_EXIST__)
+SYSPROFILER_ERROR_CODE SysProfiler_PassPMCParameterFromDHL(SysProfiler_DHLPMCParameter* DHLParameter);
+#if defined(__MD95__)
+kal_bool SysProfiler_PassPMCParameterFromMDDBG(SysProfiler_PMCSettingParameter PMCParameter[], ilm_struct ilm);
+#elif defined(__MD97__) || defined(__MD97P__)
+kal_bool SysProfiler_PassPMCParameterFromMDDBG(SysProfiler_PMCSettingParameter PMCParameter, ilm_struct ilm);
+#else
+ #error "Unsupported chip"
+#endif
+#endif
+SYSPROFILER_ERROR_CODE SysProfiler_PassPMCParameterByATCMD(kal_uint8* data_str);
+SYSPROFILER_ERROR_CODE SysProfiler_TurnOnELMAddon(kal_uint32 coreID);
+SYSPROFILER_ERROR_CODE SysProfiler_TurnOnEBMAddon(kal_uint32 coreID);
+#if defined(__MD95__)
+SYSPROFILER_ERROR_CODE SysProfiler_TurnOnCM2Addon(kal_uint32 coreID, kal_uint32 counter);
+SYSPROFILER_ERROR_CODE SysProfiler_TurnOnICM2Addon(kal_uint32 coreID, kal_uint32 counter);
+#elif defined(__MD97__) || defined(__MD97P__)
+SYSPROFILER_ERROR_CODE SysProfiler_ConfigCM2fromATCMD(kal_uint32 coreID, kal_uint8* data_str, SysProfiler_CM2SettingParameter* config);
+SYSPROFILER_ERROR_CODE SysProfiler_TurnOnCM2Addon(kal_uint32 coreID, SysProfiler_CM2SettingParameter *config);
+#else
+ #error "Unsupported chip"
+#endif
+void SysProfiler_Adjust_buffer(SYSPROFILER_ADJUST_BUFF_TYPE type, kal_uint32 buffersize);
+SYSPROFILER_ERROR_CODE SysProfiler_TriggerInitAddonByATCMD(kal_uint8 *data_str);
+kal_bool SysProfiler_RegisterDefaultAddonFromMDDBG(void);
+#if defined(__SWLA_SNAPSHOT_FEATURE__)
+SYSPROFILER_ERROR_CODE SysProfiler_BufferSnapshot(SYSPROFILER_SNAPSHOT_BUFF_ID_ENUM* buffer_id);
+#endif
+
+#endif
diff --git a/mcu/interface/service/sst/usip_api_public.h b/mcu/interface/service/sst/usip_api_public.h
new file mode 100644
index 0000000..4d30c43
--- /dev/null
+++ b/mcu/interface/service/sst/usip_api_public.h
@@ -0,0 +1,145 @@
+#ifndef __USIP_API_PUBLIC_H__
+#define __USIP_API_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+#include "dsp_module_based_api_public.h"
+#else //defined(__MD97__)
+
+#include "dsp_control_public.h"
+
+/***************************************************************/
+/********* Enum for BootDoneCheck Return Value *************/
+/***************************************************************/
+typedef enum{
+ uSIP_NOTYETDONE,
+ uSIP_BOOTDONE,
+ uSIP_NOT_DEACTIVEDONE,
+ uSIP_DEACTIVEDONE
+}uSIP_BOOTDONECHECK_RETVALUE;
+
+#define uSIP_NOT_ACTIVEDONE uSIP_NOTYETDONE
+#define uSIP_ACTIVEDONE uSIP_BOOTDONE
+
+/***************************************************************/
+/********* Variable Prototype **********************************/
+/***************************************************************/
+extern kal_uint32 duty_rat[DSP_CONTROL_CDIF_CORE_NUM];
+
+/***************************************************************/
+/********* Function Prototype **********************************/
+/***************************************************************/
+/* FirstBoot API */
+extern kal_uint32 firstboot_topsm_query(DSP_CDIF_CORE_ENUM);
+
+/***** Common API *****/
+extern DSP_CONTROL_IDLE_FLAG_STATUS usip_check_idle_flag(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern void query_usip_pc(kal_uint32*, kal_uint32*);
+extern void query_scq16_waite_signal(kal_uint8*, kal_uint8*);
+extern void firstboot_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_bool is_myself_duty_rat(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_uint32 return_dutyrat_of_thread(DSP_CDIF_CORE_ENUM);
+
+/***** Activate Relatives *****/
+extern void usip_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***** Deactivate Relatives *****/
+extern void usip_deactivate(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern USIP_CONTROL_STATUS usip_deactive_done_check(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/* Check Boot Done API*/
+extern USIP_CONTROL_STATUS usip_active_done_check(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_bool is_usip_vic_enable(DSP_CDIF_CORE_ENUM);
+extern void rake_later_trigger_ungate();
+/* Check status APIs */
+extern kal_bool dsp_uSIP_thread_is_deactive(DSP_CDIF_CORE_ENUM);
+
+/* DDL Relatives */
+extern void uSIP_inner_ddl_start(uSIP_API_USER_INNER ,DDL_MODE);
+extern void uSIP_brp_ddl_start(uSIP_API_USER_BRP , DDL_MODE);
+extern void uSIP_fec_tx_ddl_start(uSIP_API_USER_FEC , DDL_MODE);
+extern void uSIP_fec_rx_ddl_start(uSIP_API_USER_FEC , DDL_MODE);
+extern void uSIP_inner_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_brp_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_fec_tx_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_fec_rx_ddl_status_mode_query(DDL_STATUS* , DDL_MODE*);
+extern void uSIP_rake_as_tcm_for_inner_ddl_status_mode_query(DDL_STATUS *status, DDL_MODE *bin_mode);
+extern void ddl_clear_inner_ddl_protection_trigger();
+extern kal_uint32 dsp_check_ddl_user_status(DSP_CDIF_CORE_ENUM, kal_uint32);
+extern kal_bool ddl_has_user_call_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***** Sleep Flow APIs for user *****/
+/* FirstBoot API */
+#define topsm_return_dutyrat_of_inner firstboot_topsm_query(DSP_CONTROL_USIP0_INNER)
+#define topsm_return_dutyrat_of_brp firstboot_topsm_query(DSP_CONTROL_USIP0_BRP)
+#define topsm_return_dutyrat_of_fec firstboot_topsm_query(DSP_CONTROL_USIP1_FEC)
+#define topsm_return_dutyrat_of_speech firstboot_topsm_query(DSP_CONTROL_USIP1_SPEECH)
+
+#define is_myself_duty_user_of_inner(user_id) is_myself_duty_rat(DSP_CONTROL_USIP0_INNER, user_id)
+#define is_myself_duty_user_of_brp(user_id) is_myself_duty_rat(DSP_CONTROL_USIP0_BRP, user_id)
+#define is_myself_duty_user_of_fec(user_id) is_myself_duty_rat(DSP_CONTROL_USIP1_FEC, user_id)
+#define is_myself_duty_user_of_speech(user_id) is_myself_duty_rat(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+/* Check idle APIs */
+#define dsp_uSIP_inner_check_idle_flag(user_id) usip_check_idle_flag(DSP_CONTROL_USIP0_INNER, user_id)
+#define dsp_uSIP_brp_check_idle_flag(user_id) usip_check_idle_flag(DSP_CONTROL_USIP0_BRP, user_id)
+#define dsp_uSIP_fec_check_idle_flag(user_id) usip_check_idle_flag(DSP_CONTROL_USIP1_FEC, user_id)
+#define dsp_uSIP_speech_check_idle_flag(user_id) usip_check_idle_flag(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+/* First Boot Activate Use */
+#define inner_firstboot_activate(user_id) firstboot_activate(DSP_CONTROL_USIP0_INNER, user_id)
+#define brp_firstboot_activate(user_id) firstboot_activate(DSP_CONTROL_USIP0_BRP, user_id)
+#define fec_firstboot_activate(user_id) firstboot_activate(DSP_CONTROL_USIP1_FEC, user_id)
+#define speech_firstboot_activate(user_id) firstboot_activate(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+/* Activate APIs*/
+#define dsp_uSIP_inner_activate(user_id) usip_activate(DSP_CONTROL_USIP0_INNER, user_id)
+#define dsp_uSIP_brp_activate(user_id) usip_activate(DSP_CONTROL_USIP0_BRP, user_id)
+#define dsp_uSIP_fec_activate(user_id) usip_activate(DSP_CONTROL_USIP1_FEC, user_id)
+#define dsp_uSIP_speech_activate(user_id) usip_activate(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+/* Activate check APIs */
+#define uSIP_INNER_BootDoneCheck(user_id) usip_active_done_check(DSP_CONTROL_USIP0_INNER, user_id)
+#define uSIP_BRP_BootDoneCheck(user_id) usip_active_done_check(DSP_CONTROL_USIP0_BRP, user_id)
+#define uSIP_FEC_BootDoneCheck(user_id) usip_active_done_check(DSP_CONTROL_USIP1_FEC, user_id)
+#define uSIP_SPEECH_BootDoneCheck(user_id) usip_active_done_check(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+#define dsp_uSIP_inner_active_done_check(user_id) uSIP_INNER_BootDoneCheck(user_id)
+#define dsp_uSIP_brp_active_done_check(user_id) uSIP_BRP_BootDoneCheck(user_id)
+#define dsp_uSIP_fec_active_done_check(user_id) uSIP_FEC_BootDoneCheck(user_id)
+#define dsp_uSIP_speech_active_done_check(user_id) uSIP_SPEECH_BootDoneCheck(user_id)
+
+
+/* Deactivate APIs */
+#define dsp_uSIP_inner_deactivate(user_id) usip_deactivate(DSP_CONTROL_USIP0_INNER, user_id)
+#define dsp_uSIP_brp_deactivate(user_id) usip_deactivate(DSP_CONTROL_USIP0_BRP, user_id)
+#define dsp_uSIP_fec_deactivate(user_id) usip_deactivate(DSP_CONTROL_USIP1_FEC, user_id)
+#define dsp_uSIP_speech_deactivate(user_id) usip_deactivate(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+/* Deactivate check APIs */
+#define dsp_uSIP_inner_deactive_done_check(user_id) usip_deactive_done_check(DSP_CONTROL_USIP0_INNER, user_id)
+#define dsp_uSIP_brp_deactive_done_check(user_id) usip_deactive_done_check(DSP_CONTROL_USIP0_BRP, user_id)
+#define dsp_uSIP_fec_deactive_done_check(user_id) usip_deactive_done_check(DSP_CONTROL_USIP1_FEC, user_id)
+#define dsp_uSIP_speech_deactive_done_check(user_id) usip_deactive_done_check(DSP_CONTROL_USIP1_SPEECH, user_id)
+
+/* Check status APIs */
+#define dsp_uSIP_inner_is_deactive dsp_uSIP_thread_is_deactive(DSP_CONTROL_USIP0_INNER)
+
+/***** DDL Flow APIs for user *****/
+// Trigger DDL
+#define dsp_uSIP_inner_ddl_start(user_id, bin_mode) uSIP_inner_ddl_start(user_id, bin_mode)
+#define dsp_uSIP_brp_ddl_start(user_id,bin_mode) uSIP_brp_ddl_start(user_id, bin_mode)
+#define dsp_uSIP_fec_tx_ddl_start(user_id,bin_mode) uSIP_fec_tx_ddl_start(user_id, bin_mode)
+#define dsp_uSIP_fec_rx_ddl_start(user_id,bin_mode) uSIP_fec_rx_ddl_start(user_id, bin_mode)
+
+// Check uSIP inner DDL mode/status
+#define dsp_uSIP_inner_ddl_status_mode_query(status, bin_mode) uSIP_inner_ddl_status_mode_query(status, bin_mode)
+#define dsp_uSIP_brp_ddl_status_mode_query(status, bin_mode) uSIP_brp_ddl_status_mode_query(status, bin_mode)
+#define dsp_uSIP_fec_tx_ddl_status_mode_query(status, bin_mode) uSIP_fec_tx_ddl_status_mode_query(status, bin_mode)
+#define dsp_uSIP_fec_rx_ddl_status_mode_query(status, bin_mode) uSIP_fec_rx_ddl_status_mode_query(status, bin_mode)
+#define usip_check_ddl_user_status(thread, user_bitmap) dsp_check_ddl_user_status(thread, user_bitmap)
+
+// clear inner ddl_protection
+#define dsp_uSIP_inner_clear_ddl_protection() ddl_clear_inner_ddl_protection_trigger()
+
+#endif //defined(__MD97__)
+#endif /* __USIP_API_PUBLIC_H__ */