[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/protocol/interface/enl2/el2/el1_public_api.h b/mcu/protocol/interface/enl2/el2/el1_public_api.h
new file mode 100644
index 0000000..4a644b4
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/el1_public_api.h
@@ -0,0 +1,114 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * el1_public_api.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 23 2016 ali.su
+ * [MOLY00195216] [UMOLYA][EL1] move efuse function to EL1
+ * (UMOLYA) efuse fix.
+ *
+ * 09 01 2014 c-h.huang
+ * [MOLY00077683] [New feature] Improved fast phy tracking
+ * audio inform el1 volte on/off.
+ *
+ * 10 01 2013 popcafa.shih
+ * [MOLY00039514] [MT6290][Capture Card] related code check in OA
+ *
+ ****************************************************************************/
+
+#ifndef _EL1_PUBLIC_API_H
+#define _EL1_PUBLIC_API_H
+
+#include "kal_public_api.h"
+
+#if 0 // 6293: move efuse function to lte_efuse.h
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#ifdef __MTK_TARGET__
+/* Start capture */
+INLINE void _el1_start_capture(void);
+
+/* Stop capture */
+INLINE void _el1_stop_capture(void);
+#endif /*__MTK_TARGET__*/
+
+/**
+ *@brief el1_phs_volte_on
+ *For L1 Audio to inform EL1 if VOLTE is on
+ *
+ */
+void el1_phs_volte_on(kal_bool volte_on);
+
+#endif /* _EL1_PUBLIC_API_H */
+
diff --git a/mcu/protocol/interface/enl2/el2/el2_api.h b/mcu/protocol/interface/enl2/el2/el2_api.h
new file mode 100644
index 0000000..4253d2a
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/el2_api.h
@@ -0,0 +1,258 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * el2_api.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * prototypes of EL2 export function
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 09 2019 peter.chiang
+ * [MOLY00396869] [MODIS HW Copro] Work on making Modis to run with ESL HW models and Uplane with ESL
+ * Check-in for MASE
+ *
+ * 07 08 2019 yk.liu
+ * [MOLY00419753] check in for 97 MASE
+ *
+ * Check in for MASE
+ *
+ * 01 11 2018 jia-shi.lin
+ * [MOLY00301451] [SMO release][93/95]EL1 relative interface
+ * emac/el1 interface re-arch
+ *
+ * 08 03 2017 wen-jiunn.liu
+ * [MOLY00268551] Task batch scheduling for LTE Low power
+ * [EL2] Task Rescheduling for Low Power Polling Tick Change
+ *
+ * 08 03 2017 wen-jiunn.liu
+ * [MOLY00268551] Task batch scheduling for LTE Low power
+ * [EL2] Task Rescheduling for Low Power Polling Tick Change
+ *
+ * 04 07 2017 steve.kao
+ * [MOLY00230062] [UMOLYA] M-PS related interface changes for UPCM, RATDM, and EPDCP
+ *
+ * [UMOLYA][TRUNK]
+ *
+ * [UPCM][M-PS] Code changes
+ * 1. Duplicating UPCM contexts,
+ * 2. Use protocol_idx in UL/DL callback/ILM interfaces,
+ * 3. Check protocol_idx in LHIF PIT entries,
+ * 4. Fix test mode UL data processing flow,
+ * 5. Allowing test mode on protocol 2/3/4,
+ * 6. Wrap interfaces with RATDM with __MULTIPLE_PS__,
+ *
+ * [EPDCP][L+L] Code changes
+ *
+ * [RATDM][L+L] Code changes
+ *
+ * 09 26 2016 slifer.hsueh
+ * [MOLY00205085] [MT6293][EL2] ERLC source codes integration from DEV to TRUNK
+ * ERLC source codes integration from DEV to TRUNK
+ *
+ * 01 12 2016 kathie.ho
+ * [MOLY00156229] [MT6292] Code sync from MT6291: AuDRX
+ * CodeSync from LR11 (from 2015/09/21~11/15, exclude TSTM, MBMS)PART4
+ * CL 1800644[MT6291]Autonomous DRX
+ *
+ * 09 07 2015 nienteh.hsu
+ * [MOLY00140671] [6292] ERLC code sync from LR11 to UMOLY (August)
+ * .
+ *
+ * 09 04 2015 nienteh.hsu
+ * .
+ *
+ * 09 04 2015 nienteh.hsu
+ * Code sync from LR11 to UMOLY.
+ * CL1542770: DL & UL print SDU raw data.
+ * CL1582626: Fix of DL print SDU raw data.
+ * CL1590595: ERLC build warning fix.
+ * CL1525169: EM HO duration reporting. ERLC-UL part is merged.
+ * CL1546539: Backup SIT head and tail index when copro power off.
+ * CL1564394: Avoid early return in sched_grant_main function and not trigger poll re-TX.
+ * CL1586893: Fix of EM HO duration reporting.
+ *
+ * 12 04 2014 shengyi.ho
+ * [MOLY00083854] [TK6291] eL2 development checkin CR
+ * 1) fix erlc gtest ut case HWB leakage
+ * 2) rename am/um var reset macro with ERLCUL/ERLCDL prefix
+ * 3) fix HWB C-model function of get UL/DL alloc hwb num
+ *
+ * 11 11 2014 yiting.cheng
+ * [MOLY00084042] [UMOLY] merge UMOLY_DEV to UMOLY trunk
+ * .
+ *
+ * 10 27 2014 sh.yang
+ * [MOLY00082211] [MT6291_DEV] EMBMS check-in
+ * embms check-in
+ *
+ * 10 08 2014 shengyi.ho
+ * [MOLY00077592] [TK6291] emac/erlc development check-in - 1) tti bundle/msg3 collide rv setting. 2) sr prohibit check. 3) add emac ut framework for tx req. 4) remove unused function in MT6291
+ * .
+ *
+ * 07 31 2014 yiting.cheng
+ * [MOLY00073830] [MT6291_DEV] check-in MT6291 modification
+ * for fix potential target build error
+ *
+ * 07 30 2014 yiting.cheng
+ * [MOLY00073830] [MT6291_DEV] check-in MT6291 modification
+ * MT6291 modification, using temp interface with EL1
+ *
+ * 01 15 2014 slifer.hsueh
+ * [MOLY00053104] [MT6290E2][NAS RTD][MM][FDD] Assert fail: driver/l2copro/cipher/src/cipher_common.c 196 - L2COPRO
+ * Merge codes related to L2 copro delay power off back to MOLY TRUNK in LTE domain
+ *
+ * 01 09 2014 moja.hsu
+ * [MOLY00052975] Fine tune RAR/EAR 1ms protection to prevent false alarm.
+ * .
+ *
+ * 12 03 2013 timothy.yao
+ * [MOLY00048832] power down/on in EL2 task context and refine the flow
+ * 1. power-off/on L2 copro in EL2 task context.
+ * 2. refine the flow betwwen EL1 & EL2.
+ *
+ * 09 27 2013 steve.kao
+ * [MOLY00039195] [MT6290] [Low Power] LTE L2 copro power down in LTE flight mode
+ * Unshelved from pending changelist '272199':
+ *
+ * Fix link error
+ *
+ * 08 20 2013 mf.jhang
+ * [MOLY00034292] [MT6290E1] Move PHR to SW
+ * Move PHR report to SW
+ *
+ * 07 23 2013 mf.jhang
+ * [MOLY00030911] [MT6290E1][EMAC] EMAC code enhancement
+ * Register UL LMAC error interrupt handler
+ * Update some trace
+ *
+ * 06 10 2013 mf.jhang
+ * [MOLY00025349] [MT6290E1][GCF][MD8430][LTE][TC 7.1.5.4] Assert fail driverl2coprolmacsrcl2lmac_drv.c 268 - L2COPRO
+ * Add EL2 API for DL LMAC handler
+ *
+ * 05 16 2013 moja.hsu
+ * [MOLY00007625] Maintain code
+ * fix edyn compile warning.
+ ****************************************************************************/
+
+/**
+ * @date 2012/1/10
+ */
+
+#ifndef EL2_EXPORT_API
+#define EL2_EXPORT_API
+
+//#include "drv/drv_lmac.h"
+//#include "el1_enum.h"
+#include "kal_public_api.h"
+//#include "el2_def.h"
+#include "lte_time_common.h"
+
+/* EL2 constructor */
+void el2_init();
+
+// EL2 Tick Source Handler
+void el2_tick_source_dispatch_tick();
+
+/* EMAC export API */
+kal_bool emac_drx_is_drx_sleep(); // query whether EMAC DRX sleep or not
+void emac_rcv_ilm(ilm_struct *pIlm); ///< EMAC message handler
+void emac_el2task_rcv_ilm(ilm_struct *p_ilm); ///< EMAC message handler on EL2 task
+void emac_ctrl_data_rcv(); ///< control data receiving handler TO_BE_REMOVE: please use emac_ctrl_data_check().
+void emac_ctrl_data_check(); ///< check DL control swo bits
+void emac_early_protect_cancel_reg(void(*func)(void)); //Register early protect cancel callback
+void emac_rar_protect_cancel_reg(void(*func)(void)); //Register rar protect cancel callback
+#if MBMS_SUPPORT
+void emac_mch_data_check(); ///< check MCH swo bits
+#endif
+
+#if EL2_SBP_ON_AUDRX
+void emac_audrx_rrc_cmd(kal_uint32 time);
+void emac_audrx_nas_cmd(kal_uint32 time);
+void emac_epdcp_audrx_timer_timeout(void);
+void emac_epdcp_audrx_timer_restart(void);
+kal_uint32 emac_audrx_rrc_sleep_report(void);
+#endif
+
+/**
+ * @brief emac_check_rar_protect
+ * Check if we need to RAR 1ms protection.
+ * Prevent False alarm of frame boundary
+ *
+ * @return KAL_TRUE: Need to protection.
+ * KAL_FALSE: No need to do protection.
+ */
+//kal_bool emac_check_rar_protect(void);
+
+/**
+ * @brief emac_check_ear_protect
+ * Check if we need to RAR 1ms protection.
+ * Prevent False alarm of frame boundary
+ *
+ * @param vect SWO bit to indicate which HT contain EAR LCID
+ *
+ * @return KAL_TRUE: Need to protection.
+ * KAL_FALSE: No need to do protection.
+ */
+//kal_bool emac_check_ear_protect(ht_ear_vect *vect);
+kal_int32 _lte_dl_lmac_err_hndlr(kal_uint32 vect, void *ptr); //DL LMAC error interrupt callback
+kal_int32 _lte_ul_lmac_err_hndlr(kal_uint32 vect, void *ptr); //UL LMAC error interrupt callback
+
+/* ERLC export API */
+void erlcul_rcv_ilm(ilm_struct *pIlm); ///< ERLC-UL message handler
+void erlcdl_rcv_ilm(ilm_struct *pIlm); ///< ERLC-DL message handler
+void erlcul_poll(kal_uint32 protocol_idx); ///< ERLC-UL polling
+void erlcdl_poll(); ///< ERLC-DL polling
+void erlcul_reset(); ///< ERLC-UL reset
+void erlcdl_reset(); ///< ERLC-DL reset
+
+kal_uint32 erlcul_query_sleep_allow(); ///< ERLC-UL sees if we can sleep copro
+void erlcul_copro_power_down_backup(); ///back up info used when copro power off
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/el2_esl_txlisr.h b/mcu/protocol/interface/enl2/el2/el2_esl_txlisr.h
new file mode 100644
index 0000000..3b45fae
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/el2_esl_txlisr.h
@@ -0,0 +1,75 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * el2_esl_txlisr.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 17 2017 jia-shi.lin
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * esl setting refinement: support multiple case running
+ *
+ * 01 06 2017 jia-shi.lin
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * ESL: get esl scenario id for srs tx
+ *
+ ****************************************************************************/
+
+#include "el1cd_common_esl.h"
+
+void el2_esl_txlisr_init(kal_uint32 dl_cc_num, kal_uint32 ul_cc_num, kal_uint32 scenario_id);
+void el2_esl_txlisr_1st_subframe_prepare(void);
+void el2_esl_txlisr_2nd_subframe_prepare(void);
+
+void el2_esl_txlisr_subframe_post_check(void);
+
+
diff --git a/mcu/protocol/interface/enl2/el2/el2_public_api.h b/mcu/protocol/interface/enl2/el2/el2_public_api.h
new file mode 100644
index 0000000..e5a79db
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/el2_public_api.h
@@ -0,0 +1,198 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * el2_pulbic_api.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * EL2 API for other modules
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+
+#ifndef _EL2_PUBLIC_API_H_
+#define _EL2_PUBLIC_API_H_
+
+
+// ===========================================================================
+// VRB release API for other layer: ERRC
+// ===========================================================================
+
+void epdcp_errc_mcch_data_buffer_free(void *p_data, kal_uint32 data_len);
+void enpdcp_rrc_dcch_data_buffer_free(void *p_data, kal_uint32 data_len);
+void emac_errc_ccch_data_buffer_free(void *p_data, kal_uint32 data_len);
+void epdcp_errc_dcch_data_buffer_free(void *p_data, kal_uint32 data_len);
+
+
+
+
+// ===========================================================================
+// EL2 API for other layer: ERRC
+// ===========================================================================
+
+/*
+ * @brief using detection timer 3 to check ENPDCP is in data activity or not
+ * ENPDCP would use T_x (= T3 + T_rand) to check, which is used for RRC timeout
+ *
+ * @param protocol_idx (can be 0 or 1)
+ *
+ * @return kal_bool
+ * KAL_TRUE:
+ * There is data activity according to detection timer 3 (T_x)
+ * KAL_FALSE:
+ * Can be one of the following conditions:
+ * 1. There is no data activity according to detection timer 3 (T_x)
+ * 2. RRC connection does not exist
+ * 3. Detection timer 3 is not configured
+ */
+kal_bool enpdcp_errc_check_data_activity_by_detection_timer3(kal_uint32 protocol_idx);
+
+/*
+ * @brief For ERRC to query if CDRX is configured or not (For detection timer3)
+ *
+ * @param void
+ *
+ * @return kal_bool
+ * KAL_TRUE:
+ * EMAC is configured with DRX by NW
+ * KAL_FALSE:
+ * EMAC is NOT configured with DRX by NW
+*/
+kal_bool emac_errc_is_drx_config();
+
+// ===========================================================================
+// EL2POW API for other layer: ERRC/L1S
+// ===========================================================================
+
+void el2pow_errc_config_copro_power_on_req(kal_uint8 protocol_idx);
+void el2pow_errc_config_copro_power_off_req(kal_uint8 protocol_idx);
+
+void el2pow_l1s_power_on();
+
+// ===========================================================================
+// EL2 API for other layer: RSVAS
+// ===========================================================================
+// @brief Tell RSVAS the sequence to send SUSPEND_SERVICE_REQ for each modules
+
+// EMACDLPORTAL ID: b'01
+// EL2HPORTAL ID: b'10
+// EL2PORTAL ID: b'11
+
+// Default sequence: EL2HPORTAL -> EMACDLPORTAL -> EL2PORTAL
+// Default return value: b'00 11 01 10 (0x36)
+
+// return B7B6 B5B4 B3B2 B1B0
+// meaning N/A 3rd 2nd 1st
+// module N/A EL2PORTAL EMACDLPORTAL EL2HPORTAL
+// module id 00 11 01 10
+
+kal_uint32 el2_rsvas_forward_sequence_for_suspend_service_req();
+
+// ===========================================================================
+// EL2 API for other layer: UPCM
+// ===========================================================================
+
+/*
+ * @brief epdcp_is_non_ims_ul_psn_print_by_epdcp
+ * Query if EPDCP is printing PSN for uplink packets of non-IMS DRBs for the
+ * protocol_idx specified.
+ *
+ * @param protocol_idx
+ *
+ * @return kal_bool
+ * KAL_TRUE:
+ * EPDCP prints PSN for uplink packets of non-IMS DRBs periodically
+ * for the protocol_idx specified.
+ * KAL_FALSE:
+ * EPDCP dows not print PSN for uplink packets at all for the
+ * protocol_idx specified.
+ */
+kal_bool epdcp_is_non_ims_ul_psn_print_by_epdcp(kal_uint32 protocol_idx);
+
+void emac_opt_internet_disconnect_handler();
+
+// API for UPCM to turn off 1st arrow optimization when PDN disconnect
+void erlcdl_1st_arrow_disable_hndlr();
+void erlcul_1st_arrow_disable_hndlr();
+
+
+// ===========================================================================
+// EL2 API for other layer: ICD
+// ===========================================================================
+
+// For MAC_DL_TB record
+void el2icd_mac_dl_transport_block_paging_handler(kal_uint32 protocol_idx, kal_uint32 sfn, kal_uint32 subframe);
+void el2icd_mac_dl_transport_block_si_handler(kal_uint32 protocol_idx, kal_uint32 sfn, kal_uint32 subframe, kal_bool is_si);
+
+// ===========================================================================
+// EL2 API for other layer: ERRC
+// ===========================================================================
+kal_bool enpdcp_errc_is_udc_supported();
+
+// ===========================================================================
+// EL2 API for other layer: IPCORE
+// ===========================================================================
+void enpdcp_ipcore_unknown_header_statistics(
+kal_uint32 unknown_header_num, // unknown header num in this polling
+kal_uint16 begin_cntl, // begin cntl of rb_idx in this polling
+kal_uint16 end_cntl, // end cntl of rb_idx in this polling
+kal_uint16 rb_idx, // rb_idx 0~36
+kal_uint16 protocol_idx); // protocol_idx (sim_idx 0~1)
+
+// ===========================================================================
+// EL2 API for other layer: ESM
+// ===========================================================================
+/*
+ * @brief For ESM to query if ebi is connected with NR-PDCP
+ *
+ * @param protocol_idx (0: SIM1, 1: SIM2)
+ *
+ * @return ebi_bmp_with_nr, bit is only valid for EPS Bearer range (bit-31 maps to ebi=31, bit-0 maps to ebi=0)
+ * 1: RB connected to EPS Bearer is active and connected with NR-PDCP (CN is EPS)
+ * 0: others
+*/
+kal_uint32 enpdcp_esm_get_ebi_bmp_with_nr(kal_uint32 protocol_idx);
+
+#endif /* _EL2_PUBLIC_API_H_ */
diff --git a/mcu/protocol/interface/enl2/el2/el2_sap_common.h b/mcu/protocol/interface/enl2/el2/el2_sap_common.h
new file mode 100644
index 0000000..f4174f3
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/el2_sap_common.h
@@ -0,0 +1,391 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * el2_sap_common.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Common header file for all EL2 SAPs.
+ * This file defines the common structures used by all EL2 SAPs.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 03 2020 pilin.lin
+ * [MOLY00477649] 【市场反馈】【试用版本minidump】(MCU_core1,vpe0,tc0(VPE3)) [ASSERT] file:mcu/protocol/lte_sec/errc/chm/src/errc_chm_l2_control.c line:3763
+ *
+ * 09 25 2019 yiting.cheng
+ * [MOLY00443312] [MT6885][Petrus][Sanity][VMOLY][VMOLY][2019-09-21_1700] ASSERT = [1][core1,vpe0,tc0(vpe3)] Assert fail: epdcp_rbm.c 6392 - EL2 _
+ * .
+ *
+ * 12 17 2018 chenyen.huang
+ * [MOLY00347658] [Gen97] eRLC development check-in
+ *
+ * Fix typo.
+ *
+ * 12 17 2018 chenyen.huang
+ * [MOLY00347658] [Gen97] eRLC development check-in
+ *
+ * Fix build error when build 95 project.
+ *
+ * 12 17 2018 mingtsung.sun
+ * [MOLY00372769] [VMOLY] enable ENL2 on Gen95 HW platform
+ * ENL2 migration - MPD (errc_emac_msg.h move to MAC CL)
+ *
+ * 07 24 2018 chi-pin.yeh
+ * [MOLY00341764] [Gen97] remove enum errc_el2_cfg_result_enum
+ * rollback enum errc_el2_cfg_result_enum
+ *
+ * 07 24 2018 chi-pin.yeh
+ * [MOLY00341764] [Gen97] remove enum errc_el2_cfg_result_enum
+ * Remove enum errc_el2_cfg_result_enum that used for config confirm result
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: NO]
+ * [Group CL list: CL6028187;CL6028430;CL6007875;CL6016735]
+ *
+ * 06 20 2018 peter.chiang
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * 1. remove enum and codes related to RLC UL suspend.
+ * 2. Don't set DK in poll if the RB has been locked by PDCP (to avoid race condition)
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ *
+ * 05 30 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * RRC-ENPDCP Gemini VC interface naming change
+ *
+ * 05 30 2018 peter.chiang
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * [ENL2][Interface] BSR and interface modification patchback
+ *
+ * 05 18 2018 head.hsu
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * port latest interface and code on Gen97.DEV (interface)
+ *
+ * 03 28 2018 shin.chen
+ * [MOLY00316692] [6297] Interface build-up for ERRC-NRRC, ERRC/NRRC-ENL2, ERRC-EL2 SAP
+ * update el2 interfaces.
+ *
+ * 08 17 2017 steve.kao
+ * [MOLY00271504] [6293][SRLTE Enhancement][EL2][EPDCP] Sync from LR11.MP5
+ * [UMOLYA][TRUNK][EPDCP] SRLTE enhancement.
+ *
+ * 02 06 2017 peter.yu
+ * [MOLY00207733] [MT6293][EL2] ERLCDL development
+ * [M-SIM] Sync R-SIM related interfaces, remove redundant message IDs related to ERLC.
+ *
+ * 09 26 2016 slifer.hsueh
+ * [MOLY00205085] [MT6293][EL2] ERLC source codes integration from DEV to TRUNK
+ * ERLC source codes integration from DEV to TRUNK
+ *
+ * 04 08 2015 katie.tseng
+ * [MOLY00104186] [UMOLY] UMOLY code maintenance.
+ * 1. March 2015 MOLY CR sync on ERLC-DL: (1) VoLTE early RLF (2) log reduction
+ * 2. RLC gtest UT fix: set/reset gERLC_Trap_Msg_EN at setup() and teardown()
+ *
+ * 11 11 2014 yiting.cheng
+ * [MOLY00084042] [UMOLY] merge UMOLY_DEV to UMOLY trunk
+ * .
+ *
+ * 10 27 2014 sh.yang
+ * [MOLY00082211] [MT6291_DEV] EMBMS check-in
+ * embms check-in
+ *
+ * 09 19 2014 chi-chung.lin
+ * [MOLY00073836] [MT6291][ERRC][CHM] LTE-A CHM development code check-in
+ * [CHM] MBMS interface check in
+ *
+ * 07 29 2014 sh.yang
+ * [MOLY00073922] [MT6291_DEV] EMBMS general check-in
+ * .
+ *
+ * 07 28 2014 yiting.cheng
+ * [MOLY00073830] [MT6291_DEV] check-in MT6291 modification
+ * Check-in EMAC-ERRC interface
+ ****************************************************************************/
+
+/// @date 08/10/11
+
+#ifndef _MTK_LTE_EL2_COMMON_SAP_H_
+#define _MTK_LTE_EL2_COMMON_SAP_H_
+
+#include "kal_public_api.h"
+
+#ifdef __EL2_ARCH_V2__
+#include "enl2_sap_common.h"
+#endif /* __EL2_ARCH_V2__ */
+
+/*--------------------------------------------------------------------------
+ * RBID (used RLCUL SAP, RLCDL SAP, and PDCP SAP)
+ *--------------------------------------------------------------------------*/
+
+/// RBID (radio bearer identity)
+typedef enum
+{
+ RBID_SRB0 = 0x00,
+ RBID_SRB1 = 0x01,
+ RBID_SRB2 = 0x02,
+ RBID_SRB3 = 0x03,
+ RBID_DRB1 = 0x10,
+ RBID_DRB2 = 0x11,
+ RBID_DRB3 = 0x12,
+ RBID_DRB4 = 0x13,
+ RBID_DRB5 = 0x14,
+ RBID_DRB6 = 0x15,
+ RBID_DRB7 = 0x16,
+ RBID_DRB8 = 0x17,
+ RBID_DRB9 = 0x18,
+ RBID_DRB10 = 0x19,
+ RBID_DRB11 = 0x1A,
+ RBID_DRB12 = 0x1B,
+ RBID_DRB13 = 0x1C,
+ RBID_DRB14 = 0x1D,
+ RBID_DRB15 = 0x1E,
+ RBID_DRB16 = 0x1F,
+ RBID_DRB17 = 0x20,
+ RBID_DRB18 = 0x21,
+ RBID_DRB19 = 0x22,
+ RBID_DRB20 = 0x23,
+ RBID_DRB21 = 0x24,
+ RBID_DRB22 = 0x25,
+ RBID_DRB23 = 0x26,
+ RBID_DRB24 = 0x27,
+ RBID_DRB25 = 0x28,
+ RBID_DRB26 = 0x29,
+ RBID_DRB27 = 0x2A,
+ RBID_DRB28 = 0x2B,
+ RBID_DRB29 = 0x2C,
+ RBID_DRB30 = 0x2D,
+ RBID_DRB31 = 0x2E,
+ RBID_DRB32 = 0x2F
+
+} errc_el2_rbid_enum;
+
+
+/*--------------------------------------------------------------------------
+ * RRC configuration result (used by all SAPs)
+ *--------------------------------------------------------------------------*/
+
+/// result of RRC configuration
+typedef enum
+{
+ ERRC_EL2_CFG_SUCCESS = 0x00,
+ ERRC_EL2_CFG_PARAM_ERR = 0x10,
+ ERRC_EL2_CFG_STATUS_ERR = 0x20
+
+} errc_el2_cfg_result_enum;
+
+
+/*--------------------------------------------------------------------------
+ * RRC configuration to enter/leave virtual connected state
+ *--------------------------------------------------------------------------*/
+
+/*--------------------------------------------------------------------------
+ * EL1-EL2 result
+ *--------------------------------------------------------------------------*/
+
+/// result of EL1<->EL2 configuration
+typedef enum
+{
+ EL2_EL1_SUCCESS = 0x00,
+ EL2_EL1_PARAM_ERR = 0x10,
+ EL2_EL1_STATUS_ERR = 0x20
+
+} el2_el1_result_enum;
+
+
+/*--------------------------------------------------------------------------
+ * logical channel configuration (used by EMAC SAP and ERLCUL SAP)
+ *--------------------------------------------------------------------------*/
+
+/// prioritised bit rate (PBR)
+typedef enum
+{
+ PBR_KBPS_0 = 0x00,
+ PBR_KBPS_8 = 0x01,
+ PBR_KBPS_16 = 0x02,
+ PBR_KBPS_32 = 0x03,
+ PBR_KBPS_64 = 0x04,
+ PBR_KBPS_128 = 0x05,
+ PBR_KBPS_256 = 0x06,
+ PBR_KBPS_512 = 0x07,
+ PBR_KBPS_1024= 0x08,
+ PBR_KBPS_2048= 0x09,
+ PBR_KBPS_INF = 0x0a
+} errc_el2_pbr_enum;
+
+
+/// bucket size duration (BSD)
+typedef enum
+{
+ BSD_MS50 = 0x00,
+ BSD_MS100 = 0x01,
+ BSD_MS150 = 0x02,
+ BSD_MS300 = 0x03,
+ BSD_MS500 = 0x04,
+ BSD_MS1000 = 0x05,
+ BSD_INVALID = 0x06
+} errc_el2_bsd_enum;
+
+
+#define INVALID_LCG (0x04)
+
+/// logical channel configuration
+typedef struct
+{
+ kal_uint8 pri; ///< priority
+ errc_el2_pbr_enum pbr; ///< prioritised bit rate (PBR)
+ errc_el2_bsd_enum bsd; ///< bucket size duration (BSD)
+ kal_uint8 lcg; ///< logical channel group (LCG)
+
+} errc_el2_lch_cfg;
+
+
+
+/*--------------------------------------------------------------------------
+ * RB configuration (used by ERLCUL SAP and ERLCDL SAP)
+ *--------------------------------------------------------------------------*/
+
+/// maximum number of RBs in ERLC configured by ERRC
+#define MAX_NUM_RLC_CONFIG_RB (18)
+
+/// maximum number of MRBs in ERLC configured by ERRC
+#define MAX_NUM_RLC_CONFIG_MRB (29)
+
+/// RB configuration mode in ERLCUL and ERLCDL
+typedef enum
+{
+ ERLC_MODE_REL = 0x00,
+ ERLC_MODE_EST = 0x10,
+ ERLC_MODE_REEST = 0x20,
+ ERLC_MODE_RECFG = 0x30,
+ ERLC_MODE_REEST_NO_CFG = 0x40,
+ ERLC_MODE_RESUME = 0x50
+} errc_erlc_rb_mode_enum;
+
+
+/// RLC mode
+typedef enum
+{
+ ERLC_AM = 0,
+ ERLC_UM = 1
+
+} errc_erlc_rb_type_enum;
+
+
+/// RLC SN field length
+typedef enum
+{
+ SN_SIZE_5 = 0,
+ SN_SIZE_10 = 1
+
+} errc_erlc_sn_field_len_enum;
+
+
+#ifdef __EL2_ARCH_V2__
+typedef enum
+{
+ ERRC_EL2_CELL_GROUP_MCG,
+ ERRC_EL2_CELL_GROUP_SCG
+} errc_el2_cell_group_enum;
+
+
+typedef enum {
+ ERRC_EL2_RB_TYPE_SRB,
+ ERRC_EL2_RB_TYPE_DRB
+} errc_el2_rb_type_enum;
+#endif /* __EL2_ARCH_V2__ */
+
+/*--------------------------------------------------------------------------
+ * EMBMS configuration
+ *--------------------------------------------------------------------------*/
+
+/*--------------------------------------------------------------------------
+ * radio link failure (RLF) (used by ERLCUL SAP and ERLCDL SAP)
+ *--------------------------------------------------------------------------*/
+
+/// cause of ERRC-ERLC RLF indication
+typedef enum
+{
+ ERLC_UL_MAX_RETX = 0x00, ///< max retransmission for a specific SN (TS36.322)
+ ERLC_DL_MAX_RETX = 0x01 ///< max duplication for a specific SN (MTK proprietary)
+
+} errc_erlc_rlf_enum;
+
+/// additional information about RLF indication
+typedef enum
+{
+ ERLC_RLF_ADD_INVALID = 0x00, ///< No additional information
+ ERLC_RLF_ADD_UL_EAR_REEST = 0x01, ///< UL early re-establishment
+ ERLC_RLF_ADD_DL_EAR_REEST = 0x02 ///< DL early re-establishment
+
+} errc_erlc_rlf_ind_add_enum;
+
+/// message structure of ERRC_ERLC_RLF_IND
+typedef struct
+{
+ LOCAL_PARA_HDR
+#ifdef __EL2_ARCH_V2__
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+#else
+ errc_el2_rbid_enum rbid;
+#endif /* __EL2_ARCH_V2__ */
+ kal_uint8 rb_idx; // RB index
+ kal_bool is_old_rb; // is old RB RLF or not
+ errc_erlc_rlf_enum cause; // reason of RLF
+
+ kal_uint8 add_info; // additional information (MTK proprietary)
+ kal_uint8 rsvd8; // reserved 1 byte
+ kal_uint16 rsvd16; // reserved 2 bytes
+
+} errc_erlc_rlf_ind_struct;
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/em/el2em_legacy_stats_struct.h b/mcu/protocol/interface/enl2/el2/em/el2em_legacy_stats_struct.h
new file mode 100644
index 0000000..ee675f3
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/el2em_legacy_stats_struct.h
@@ -0,0 +1,73 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * el2em_legacy_stats_struct.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Define legacy statistic structures (not used in 93)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 11 2019 frank.song
+ * [MOLY00438942] [VMOLY] DMF patches need to be ported to VMOLY TRUNK
+ *
+ * DMF porting.
+ *
+ ****************************************************************************/
+
+#ifndef LEGACY_STATS_STRUCT_H
+#define LEGACY_STATS_STRUCT_H
+#include "kal_public_api.h"
+
+//================================== not exist for 93 ==================================//
+
+
+
+#endif /*EMAC_STATS_STRUCT_H*/
+
diff --git a/mcu/protocol/interface/enl2/el2/em/el2em_report_msg.h b/mcu/protocol/interface/enl2/el2/em/el2em_report_msg.h
new file mode 100644
index 0000000..c26a0a6
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/el2em_report_msg.h
@@ -0,0 +1,234 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * el2em_report_msg.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Define message structure of EM report
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 11 2019 frank.song
+ * [MOLY00438942] [VMOLY] DMF patches need to be ported to VMOLY TRUNK
+ *
+ * DMF porting.
+ *
+ * 06 06 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Fix build error for MT3967 - rollback EM structure
+ *
+ * 06 01 2018 hamilton.liang
+ * [MOLY00330466] DL 5CCs upgraded on Gen97
+ *
+ * DL 5CCs upgrade modification
+ *
+ * 05 22 2018 peter.chiang
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * [GEN97]ENL2 Common files
+ *
+ *
+ * 04 27 2018 shu-wei.ho
+ * [MOLY00322854] [EL2] Patch back from UMOLYE to GEN97.DEV
+ *
+ * . EMAC part
+ *
+ * 04 27 2018 shu-wei.ho
+ * [MOLY00322854] [EL2] Patch back from UMOLYE to GEN97.DEV
+ * . EMAC part
+ *
+ * 04 23 2018 shu-wei.ho
+ * .Patch from UMOLYE since 2/1 to 4/20
+ *
+ * 01 11 2018 jia-shi.lin
+ * [MOLY00301451] [SMO release][93/95]EL1 relative interface
+ * emac/el1 interface re-arch
+ *
+ * 03 09 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * EL2EM re-arch/sync to LR12 CL3601142
+ *
+ * 01 25 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * fix compile option
+ *
+ ****************************************************************************/
+/**
+ * @file el2em_report_msg.h
+ * @brief Define message structure of EM report
+ *
+ * @author mtk05495
+ * @date 2016/09/08
+ *
+ **/
+
+#ifndef __EL2EM_REPORT_MSG_H__
+#define __EL2EM_REPORT_MSG_H__
+
+#include "enl2_def.h"
+
+#if defined(__EL2_EM_MODE__)
+
+#include "kal_public_api.h"
+
+#include "em_enl2_public_struct.h"
+#include "lte_time_common.h"
+
+#include "emac_stats_struct.h"
+#include "erlc_stats_struct.h"
+#include "epdcp_stats_struct.h"
+#include "el2em_legacy_stats_struct.h"
+
+/*---------------------------------------------------------------------------
+ * msg struct for EM report
+ *---------------------------------------------------------------------------*/
+
+//================================== EL2_OV ==================================//
+#define EL2_OV_MSG___________________________________
+
+
+
+//================================== EMAC EM MSG ==================================//
+#define EMAC_EM_MSG__________________________________
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ em_info_enum em_info;
+ kal_uint16 system_fn;
+ kal_uint8 sub_fn;
+ /*
+ For VzW EM, required to report avg received UL grant bytes in 500ms
+ Here we acumulate the total UL grant bytes,
+ and divide by emac_ul_grant_bytes_count
+ for 92 with UL CA, this field aggregate both cells' grant bytes
+ */
+ kal_uint32 emac_ul_grant_bytes_total;
+ /*
+ For VzW EM, required to report avg UL padding bytes in 500ms
+ Here we acumulate the total padding bytes,
+ and divide by emac_ul_grant_bytes_count
+ for 92 with UL CA, this field aggregate both cells' padding bytes
+ */
+ kal_uint32 emac_ul_padding_bytes_total;
+ /*
+ Total transmitted tb count in 500ms
+ for 92 with UL CA, this field aggregate both cells' grant count
+ */
+ kal_uint16 emac_ul_grant_bytes_count;
+
+ /*Below fields is for KOR MNO*/
+ kal_uint32 ra_rar_error_cnt;
+ kal_uint32 ra_cr_error_cnt;
+ kal_uint32 ra_error_ind_cnt;
+
+ kal_uint32 emac_rx_bits;
+ kal_uint32 emac_tx_bits;
+ kal_uint32 phich_nack_cnt;
+ kal_uint32 phich_ack_cnt;
+ kal_uint32 rx_cnt_pcell;
+ kal_uint32 rx_cnt_scell;
+ kal_uint32 rx_crc_ng_cnt_pcell;
+ kal_uint32 rx_crc_ng_cnt_scell;
+
+ /* For R12 Feature EM view, consider up to DL4CC, UL2CC in 92 gen, don't reset below regions after primitive send (refer to _edyn_em_reset_emac_ov_status_500ms),
+ EL2_OV_STATUS_IND also has similar EM info, but its access privilege is HQ_ONLY (refer to em_mapping_for_tool.h), so to allow customer/outsourcing
+ to see R12 Feature EM view working, the view needs to be binded to customer/outsourcing accessible primitives, and we choose EMAC_OV_STATUS_500_IND to do so.
+ */
+ emac_scell_state_enum state_scell[MAX_NUM_SUPPORT_SCELL];
+
+ kal_uint32 accumulate_rx_cnt_pcell;
+
+ kal_uint32 accumulate_rx_cnt_scell[MAX_NUM_SUPPORT_SCELL];
+
+ kal_uint32 accumulate_tx_cnt_pcell;
+ kal_uint32 accumulate_tx_cnt_scell;
+ kal_uint64 accumulate_tx_byte_pcell;
+ kal_uint64 accumulate_tx_byte_scell;
+ /**************/
+
+ //For titan
+ //acumulate the bsr_bytes in reporting period, report the total value
+ kal_uint32 emac_tx_bsr_bytes;
+} em_emac_ov_status_500_ind_struct;
+
+/*---------------------------------------------------------------------------
+ * EMAC event EM
+ *---------------------------------------------------------------------------*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ em_info_enum em_info;
+ lte_cell_time rcv_time;
+ kal_uint32 rar_ta_value;
+ kal_bool ra_type_contention;
+ kal_uint32 tc_rnti;
+} em_emac_msg2_report_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ em_info_enum em_info;
+ lte_cell_time rcv_time;
+ emac_cr_result_enum cr_result;
+} em_emac_msg4_report_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ em_info_enum em_info;
+ emac_timer_expiry_event_enum emac_timer_expiry;
+} em_emac_timer_expire_ind_struct;
+
+#endif
+#endif
+
diff --git a/mcu/protocol/interface/enl2/el2/em/emac_ota.h b/mcu/protocol/interface/enl2/el2/em/emac_ota.h
new file mode 100644
index 0000000..1c048b9
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/emac_ota.h
@@ -0,0 +1,291 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * emac_ota.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Define EMAC statistic structures
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 13 2017 nicole.hsu
+ * [MOLY00277396] [MT6293] EL2 L+L EM development
+ * [TRUNK] L+L EM - EL2EM, EMAC, EMACDL
+ *
+ * 06 29 2017 nicole.hsu
+ * [MOLY00258660] [BIANCO][MT6763][MP1][EVB][PHYTest][ASSERT] Assert fail: dpcopro_mmu_drv.c 1608
+ * [TRUNK] send rach_trigger em when PRACH is really scheduled by EL1
+ * refine EMAC DL OTA
+ *
+ * 02 09 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * modify OTA compile option
+ *
+ * 01 25 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * fix compile option
+ *
+ ****************************************************************************/
+#ifndef EMAC_OTA_H
+#define EMAC_OTA_H
+
+#if defined(__EM_MODE__)
+
+#include "kal_public_api.h"
+#include "dhl_trace.h"
+
+typedef struct
+{
+ kal_uint8 truncated:1;
+ kal_uint8 type:3;
+ kal_uint8 version:4;
+ kal_uint8 direction:1;
+ kal_uint8 transport_channel:3; // 1:bch 2:dl-sch 3:pch 4:mch 5:ul-sch 6:rach
+ kal_uint8 mac_hdr_len:4; // 1~11
+ kal_uint8 mac_hdr[11];
+}emac_ota_header_t;
+
+/**** EMAC OTA header struct (for both UL/DL EMAC TB)
+ *
+ * +-----+-----+-----+-----+-----+-----+-----+-----+
+ * | t | type | version |
+ * +-----+-----+-----+-----+-----+-----+-----+-----+
+ * | d | trch | mac_hdr_len |
+ * +-----+-----+-----+-----+-----+-----+-----+-----+
+ * | sfn[9:2] |
+ * +-----+-----+-----+-----+-----+-----+-----+-----+
+ * | sfn[1:0] | subframe number[3:0] | Reserved |
+ * +-----+-----+-----+-----+-----+-----+-----+-----+
+ *
+ * t: truncated, set to 1 if the MAC header size is larger than EMAC_OTA_MAC_HDR_LEN bytes
+ * sfn: LTE system frame number (0..1023)
+ * subframe number: LTE subframe number (0..9)
+ *
+ */
+
+// EMAC OTA: length setting
+#define EMAC_OTA_BUFFER_LEN 15
+#define EMAC_OTA_MAC_HDR_LEN 11
+#define EMAC_OTA_OVERHEAD 4
+
+// EMAC OTA: header.type
+#define EMAC_OTA_TYPE_MAC DHL_L2_PDU_MAC_TYPE
+
+// EMAC OTA: header.version
+#define EMAC_OTA_VERSION 1
+
+// EMAC OTA: header.d (direction)
+#define EMAC_OTA_DIR_UL 0
+#define EMAC_OTA_DIR_DL 1
+
+// EMAC OTA: header.trch (transport channel)
+#define EMAC_OTA_BCH 1
+#define EMAC_OTA_DLSCH 2
+#define EMAC_OTA_PCH 3
+#define EMAC_OTA_MCH 4
+#define EMAC_OTA_ULSCH 5
+#define EMAC_OTA_RACH 6
+
+#define EMAC_SUB_HDR_E (0x20) // E in MAC subheader
+#define EMAC_SUB_HDR_F (0x80) // F in MAC subheader
+
+extern kal_uint8* p_emac_dl_ota_buffer;
+extern kal_uint8 emac_dl_ota_length;
+extern kal_uint8 emac_ul_ota_buffer[];
+extern kal_uint8 emac_ul_ota_length;
+
+// 2 byte is minimum overhead for emac ota structure
+#define EMAC_DL_OTA_DECLARE(_pOta, _pCur, _bTruncate, _len, _is_dl_tb_report_needed_in, _pTb_report_in, _pidx) \
+ kal_uint8* _pOta = p_emac_dl_ota_buffer; \
+ kal_uint8* _pCur = p_emac_dl_ota_buffer + EMAC_OTA_OVERHEAD; \
+ kal_uint8 _bTruncate = 0; \
+ kal_bool _is_dl_tb_report_needed = el2em_is_em_on(EL2EM_EM_TYPE_EMAC_DL_TBS_REPORT, _pidx); \
+ kal_uint32 _len = 0; \
+ emac_el2task_dl_tb_report_ind_struct* _pTb_report = (_pTb_report_in);
+
+#define EMAC_DL_OTA_CLEAR_BUFFER()\
+ do {\
+ EMAC_MEM_SET(p_emac_dl_ota_buffer, 0, EMAC_OTA_BUFFER_LEN);\
+ } while(0);
+
+#define _FILL_EMAC_OTA_BYTE1(ota_ptr, truncated, type, version) \
+ do {\
+ *(kal_uint8 *)(ota_ptr) = (((kal_uint8)(truncated) & 0x01) << 7) | (((kal_uint8)(type) & 0x07) << 4) | ((kal_uint8)(version) & 0x0F);\
+ } while(0);
+
+#define _FILL_EMAC_OTA_BYTE2(ota_ptr, direction, tch, ota_len) \
+ do {\
+ *(kal_uint8 *)((ota_ptr)+1) = (((kal_uint8)(direction) & 0x01) << 7) | (((kal_uint8)(tch) & 0x07) << 4) | ((kal_uint8)(ota_len) & 0x0F);\
+ } while(0);
+
+#define _FILL_EMAC_OTA_BYTE3_4(ota_ptr, system_fn, sub_fn) \
+ do {\
+ *(kal_uint8 *)((ota_ptr)+2) = ((kal_uint8)((system_fn) >> 2));\
+ *(kal_uint8 *)((ota_ptr)+3) = (((kal_uint8)(system_fn) & 0x03) << 6 ) | ((((kal_uint8)(sub_fn) & 0x0F)) << 2);\
+ } while(0);
+
+#define _FILL_EMAC_OTA_LCID(cur_ptr, ota_len, _bTruncate, lcid) \
+ do {\
+ if( !(_bTruncate) && ((ota_len)+MAC_SUBHDR_L_0_SZ) <= EMAC_OTA_MAC_HDR_LEN){ \
+ *(kal_uint8 *)(cur_ptr) = ((kal_uint8)(lcid) & 0x1F);\
+ (ota_len)++;\
+ (cur_ptr)++;\
+ } \
+ else{ \
+ (_bTruncate) = 1; \
+ } \
+ } while(0);
+
+#define FILL_EMAC_OTA_E_LCID(cur_ptr, ota_len, _bTruncate, lcid) \
+ do {\
+ if(DHL_MAC_CHECK_L2_PDU() || _is_dl_tb_report_needed){\
+ if( !(_bTruncate) && ((ota_len)+MAC_SUBHDR_L_0_SZ) <= EMAC_OTA_MAC_HDR_LEN){ \
+ *(kal_uint8 *)(cur_ptr) = ((kal_uint8)EMAC_SUB_HDR_E) | (((kal_uint8)(lcid) & 0x1F));\
+ (ota_len)++;\
+ (cur_ptr)++;\
+ } \
+ else{ \
+ (_bTruncate) = 1; \
+ } \
+ }\
+ } while(0);
+
+#define FILL_EMAC_OTA_LAST_LCID(cur_ptr, ota_len, _bTruncate, lcid, ota_ptr, direction, tch, system_fn, sub_fn) \
+ do {\
+ if(DHL_MAC_CHECK_L2_PDU() || _is_dl_tb_report_needed){\
+ _FILL_EMAC_OTA_LCID((cur_ptr), (ota_len), (_bTruncate), (lcid)); \
+ _FILL_EMAC_OTA_BYTE1((ota_ptr), (_bTruncate), EMAC_OTA_TYPE_MAC, EMAC_OTA_VERSION); \
+ _FILL_EMAC_OTA_BYTE2((ota_ptr), (direction), (tch), (ota_len)); \
+ _FILL_EMAC_OTA_BYTE3_4((ota_ptr), (system_fn), (sub_fn)); \
+ emac_dl_ota_length = (ota_len) + EMAC_OTA_OVERHEAD;\
+ if(DHL_MAC_CHECK_L2_PDU()) {\
+ DHL_MAC_LOG_L2_PDU(emac_dl_ota_buffer, emac_dl_ota_length);\
+ }\
+ if(_is_dl_tb_report_needed && _pTb_report) {\
+ kal_uint32 copy_len = (ota_len) <= EM_EMAC_MAX_HEADER_LEN ?\
+ (ota_len) : EM_EMAC_MAX_HEADER_LEN;\
+ EMAC_MEM_CPY(_pTb_report->tb.mac_header_data,\
+ emac_dl_ota_buffer + EMAC_OTA_OVERHEAD, copy_len);\
+ _pTb_report->tb.mac_header_len = copy_len;\
+ }\
+ }\
+ } while(0);
+
+// requested by ERRC Paging/SIB reporting, ERRC will prepare OTA data buffer
+#define FILL_EMAC_OTA_NO_LCID(ota_len, _bTruncate, ota_ptr, direction, tch, system_fn, sub_fn) \
+ do {\
+ if(DHL_MAC_CHECK_L2_PDU()){\
+ _FILL_EMAC_OTA_BYTE1((ota_ptr), (_bTruncate), EMAC_OTA_TYPE_MAC, EMAC_OTA_VERSION); \
+ _FILL_EMAC_OTA_BYTE2((ota_ptr), (direction), (tch), (ota_len)); \
+ _FILL_EMAC_OTA_BYTE3_4((ota_ptr), (system_fn), (sub_fn)); \
+ DHL_MAC_LOG_L2_PDU(ota_ptr, (ota_len)+ EMAC_OTA_OVERHEAD);\
+ }\
+ } while(0);
+
+#define FILL_EMAC_OTA_E_SUBHDR(cur_ptr, ota_len, _bTruncate, lcid, len)\
+do {\
+ if(DHL_MAC_CHECK_L2_PDU() || _is_dl_tb_report_needed){\
+ if ((len) <= MAC_SUBHDR_L_7_MAX_VAL) {\
+ if( !(_bTruncate) && ((ota_len)+MAC_SUBHDR_L_7_SZ) <= EMAC_OTA_MAC_HDR_LEN){ \
+ *(kal_uint8 *)(cur_ptr) = ((kal_uint8)EMAC_SUB_HDR_E) | (((kal_uint8)(lcid) & 0x1F));\
+ *(kal_uint8 *)((cur_ptr)+1) = (((kal_uint8)(len) & 0x7F));\
+ (ota_len) += MAC_SUBHDR_L_7_SZ;\
+ (cur_ptr) += MAC_SUBHDR_L_7_SZ;\
+ } \
+ else{ \
+ (_bTruncate) = 1; \
+ } \
+ } else {\
+ if( !(_bTruncate) && (ota_len+MAC_SUBHDR_L_15_SZ) <= EMAC_OTA_MAC_HDR_LEN){ \
+ *(kal_uint8 *)(cur_ptr) = ((kal_uint8)EMAC_SUB_HDR_E) | (((kal_uint8)(lcid) & 0x1F));\
+ *(kal_uint8 *)((cur_ptr)+1) = ((kal_uint8)EMAC_SUB_HDR_F) | (((kal_uint8)((len)>>8)) & 0x7F);\
+ *(kal_uint8 *)((cur_ptr)+2) = ((kal_uint8)((len) & 0xFF));\
+ (ota_len) += MAC_SUBHDR_L_15_SZ;\
+ (cur_ptr) += MAC_SUBHDR_L_15_SZ;\
+ } \
+ else{ \
+ (_bTruncate) = 1; \
+ } \
+ }\
+ }\
+} while (0);
+
+#define FILL_EMAC_UL_OTA(direction, tch, mac_hdr_ptr, ota_len, system_fn, sub_fn)\
+do {\
+ if(DHL_MAC_CHECK_L2_PDU()){\
+ if((ota_len) > EMAC_OTA_MAC_HDR_LEN){\
+ _FILL_EMAC_OTA_BYTE1(emac_ul_ota_buffer, 1, EMAC_OTA_TYPE_MAC, EMAC_OTA_VERSION); \
+ _FILL_EMAC_OTA_BYTE2(emac_ul_ota_buffer, (direction), (tch), EMAC_OTA_MAC_HDR_LEN); \
+ _FILL_EMAC_OTA_BYTE3_4(emac_ul_ota_buffer, (system_fn), (sub_fn)); \
+ EMAC_MEM_CPY(emac_ul_ota_buffer+EMAC_OTA_OVERHEAD, (void*)(mac_hdr_ptr), EMAC_OTA_MAC_HDR_LEN);\
+ emac_ul_ota_length = EMAC_OTA_BUFFER_LEN;\
+ }\
+ else{\
+ _FILL_EMAC_OTA_BYTE1(emac_ul_ota_buffer, 0, EMAC_OTA_TYPE_MAC, EMAC_OTA_VERSION); \
+ _FILL_EMAC_OTA_BYTE2(emac_ul_ota_buffer, (direction), (tch), (ota_len)); \
+ _FILL_EMAC_OTA_BYTE3_4(emac_ul_ota_buffer, (system_fn), (sub_fn)); \
+ EMAC_MEM_CPY(emac_ul_ota_buffer+EMAC_OTA_OVERHEAD, (void*)(mac_hdr_ptr), (ota_len));\
+ emac_ul_ota_length = (ota_len) + EMAC_OTA_OVERHEAD;\
+ }\
+ DHL_MAC_LOG_L2_PDU(emac_ul_ota_buffer, emac_ul_ota_length);\
+ }\
+}while(0);
+
+#else
+#define EMAC_DL_OTA_DECLARE(_pOta, _pCur, _bTruncate, _len, _is_dl_tb_report_needed_in, _pTb_report_in)
+#define EMAC_DL_OTA_CLEAR_BUFFER()
+#define FILL_EMAC_OTA_E_LCID(cur_ptr, ota_len, _bTruncate, lcid)
+#define FILL_EMAC_OTA_E_SUBHDR(cur_ptr, ota_len, _bTruncate, lcid, len)
+#define FILL_EMAC_OTA_LAST_LCID(cur_ptr, ota_len, _bTruncate, lcid, ota_ptr, direction, tch, system_fn, sub_fn)
+#define FILL_EMAC_OTA_NO_LCID(ota_len, _bTruncate, ota_ptr, direction, tch, system_fn, sub_fn)
+#define FILL_EMAC_UL_OTA(direction, tch, mac_hdr_ptr, ota_len, system_fn, sub_fn)
+#endif /* __EL2_EM_MODE__ */
+
+#endif /*EMAC_STATS_STRUCT_H*/
+
diff --git a/mcu/protocol/interface/enl2/el2/em/emac_stats_struct.h b/mcu/protocol/interface/enl2/el2/em/emac_stats_struct.h
new file mode 100644
index 0000000..58371d5
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/emac_stats_struct.h
@@ -0,0 +1,115 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * emac_stats_struct.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Define EMAC statistic structures
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 11 2019 frank.song
+ * [MOLY00438942] [VMOLY] DMF patches need to be ported to VMOLY TRUNK
+ *
+ * DMF porting.
+ *
+ * 07 24 2019 frank.song
+ * [MOLY00420694] [MT6297][Apollo][MP1][SQC][EM][China][Shenzhen][FDD][4GMM][CU+NA][TCID:EM_EL2_001]SRB/DRB number doesn't display the value.
+ * .
+ *
+ * 06 01 2018 hamilton.liang
+ * [MOLY00330466] DL 5CCs upgraded on Gen97
+ *
+ * DL 5CCs upgrade modification
+ *
+ * 06 23 2017 nicole.hsu
+ * [MOLY00259119] [MT6763][EL2] EMAC/EL2EM/EL2POW maintenance
+ * [TRUNK] sync EM from LR12
+ *
+ * 03 09 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * EL2EM re-arch/sync to LR12 CL3601142
+ *
+ * 02 21 2017 jia-shi.lin
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * emac em struct update
+ *
+ ****************************************************************************/
+#ifndef EMAC_STATS_STRUCT_H
+#define EMAC_STATS_STRUCT_H
+#include "kal_public_api.h"
+#include "lte_abs_time.h"
+#include "dhl_trace.h"
+#include "em_enl2_public_struct.h"
+
+/* This constant has the same value as MAX_NUM_SCELL constant in EL1-EMAC IF. */
+#define EMAC_STATS_MAX_NUM_SCELL 7
+/* This constant has the same value as MAX_NUM_SUPPORT_UL_CELLS constant in EL1-EMAC IF. */
+#define EMAC_STATS_MAX_NUM_SUPPORT_UL_CELLS 2
+
+//=================================================================================
+// EM update use
+typedef enum
+{
+ EM_EMAC_FUNC_STATUS_BIT_DRX = 0,
+ EM_EMAC_FUNC_STATUS_BIT_PHR = 1,
+ EM_EMAC_FUNC_STATUS_BIT_SPS = 2,
+ EM_EMAC_FUNC_STATUS_BIT_TTI_BUNDLING = 3
+} em_emac_func_status_bit_e;
+
+typedef enum
+{
+ EM_EMAC_CH_MODE_CLOSE = 0,
+ EM_EMAC_CH_MODE_SRB0 = 1,
+ EM_EMAC_CH_MODE_OPEN = 2
+} em_emac_ch_mode_e;
+
+
+#endif /*EMAC_STATS_STRUCT_H*/
+
diff --git a/mcu/protocol/interface/enl2/el2/em/epdcp_ota.h b/mcu/protocol/interface/enl2/el2/em/epdcp_ota.h
new file mode 100644
index 0000000..9a1396f
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/epdcp_ota.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * epdcp_ota.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * ePDCP statistics
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ ****************************************************************************/
+
+#ifndef _LTE_EL2_EPDCP_OTA_H_
+#define _LTE_EL2_EPDCP_OTA_H_
+
+#include "kal_public_api.h"
+
+
+
+/*****************************************************************************
+* global variables
+*****************************************************************************/
+
+
+#endif //_LTE_EL2_EPDCP_STATS_STRUCT_H_
+
diff --git a/mcu/protocol/interface/enl2/el2/em/epdcp_stats_struct.h b/mcu/protocol/interface/enl2/el2/em/epdcp_stats_struct.h
new file mode 100644
index 0000000..93df127
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/epdcp_stats_struct.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * epdcp_stats.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * ePDCP statistics
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 11 2019 frank.song
+ * [MOLY00438942] [VMOLY] DMF patches need to be ported to VMOLY TRUNK
+ *
+ * DMF porting.
+ *
+ * 06 06 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Fix build error for MT3967 - rollback EM structure
+ *
+ * 06 01 2017 i-feng.chen
+ * [MOLY00252815] [6293] EPDCP EM statistics
+ *
+ * [UMOLYA][TRUNK][EPDCP] EPDCP EM Statics
+ *
+ * 03 09 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * EL2EM re-arch/sync to LR12 CL3601142
+ *
+ ****************************************************************************/
+
+#ifndef _LTE_EL2_EPDCP_STATS_STRUCT_H_
+#define _LTE_EL2_EPDCP_STATS_STRUCT_H_
+
+#include "kal_public_api.h"
+
+/*****************************************************************************
+* constants
+*****************************************************************************/
+
+/*****************************************************************************
+* enum types
+*****************************************************************************/
+
+
+
+/*****************************************************************************
+* statistics structure
+*****************************************************************************/
+/* VzW MDMI: EPDCP-OTA-MSG */
+typedef struct
+{
+ /* 1st-byte (DHL used) */
+ kal_uint8 version:4;
+ kal_uint8 type:3; // pdcp 100, rlc 010, mac 001
+ kal_uint8 truncate:1;
+
+ /* 2nd-byte */
+ kal_uint8 direction:1; // upstream: 0, downstream: 1
+ kal_uint8 msg_type:1; // data for drb(null for srb): 0, control for drb: 1
+ kal_uint8 pdcp_hdr_len:1; // 1-byte header: 0, 2-byte header: 1
+ kal_uint8 reserved:1;
+ kal_uint8 rbid:4;
+
+ /* 3rd-byte */
+ kal_uint8 pdcp_sn_bit:2; // null: 0, 7-bit: 1, 12-bit: 2, 15-bit: 3
+ kal_uint8 rb_type:1; // drb: 0, srb: 1
+ kal_uint8 rlc_mode:1; // am: 0, um: 1
+
+ /* raw header */
+ kal_uint8 pdcp_hdr[2];
+} epdcp_ota_msg_t;
+
+/*****************************************************************************
+* global variables
+*****************************************************************************/
+
+
+
+#endif //_LTE_EL2_EPDCP_STATS_STRUCT_H_
+
diff --git a/mcu/protocol/interface/enl2/el2/em/erlc_ota.h b/mcu/protocol/interface/enl2/el2/em/erlc_ota.h
new file mode 100644
index 0000000..4551894
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/erlc_ota.h
@@ -0,0 +1,69 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * erlc_ota.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * ERLC statistics
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 09 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * EL2EM re-arch/sync to LR12 CL3601142
+ *
+ ****************************************************************************/
+
+#ifndef _LTE_EL2_ERLC_OTA_H_
+#define _LTE_EL2_ERLC_OTA_H_
+
+#include "kal_public_api.h"
+
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/em/erlc_stats_struct.h b/mcu/protocol/interface/enl2/el2/em/erlc_stats_struct.h
new file mode 100644
index 0000000..d3fb8eb
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/em/erlc_stats_struct.h
@@ -0,0 +1,93 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * erlc_stats_struct.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * ERLC statistics
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 11 2019 frank.song
+ * [MOLY00438942] [VMOLY] DMF patches need to be ported to VMOLY TRUNK
+ *
+ * DMF porting.
+ *
+ * 07 31 2019 peter.yu
+ * [MOLY00425851] [MT6297][Apollo][MP1][SQC][EM][China][Shenzhen][FDD][4GMM][CU+NA][TCID:EM_EL2_003]the config of all DRB display KAL_FALSE.
+ * Fix lte_sec EL2 EM structure including for DHL database.
+ *
+ * 07 24 2019 peter.yu
+ * [MOLY00420694] [MT6297][Apollo][MP1][SQC][EM][China][Shenzhen][FDD][4GMM][CU+NA][TCID:EM_EL2_001]SRB/DRB number doesn't display the value.
+ * Refine ERLC EM/ICD reporting.
+ *
+ * 10 31 2018 chi-pin.yeh
+ * [MOLY00342363] [Gen97] eRLC development check-in
+ * move define RB macro to enl2 cdb
+ *
+ * 05 22 2018 peter.chiang
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * [GEN97]ERLC Latest code patch back
+ *
+ *
+ * 03 09 2017 nicole.hsu
+ * [MOLY00223067] [MT6293] EL2 EM implementation
+ * EL2EM re-arch/sync to LR12 CL3601142
+ *
+ ****************************************************************************/
+
+#ifndef _LTE_EL2_ERLC_STATS_STRUCT_H_
+#define _LTE_EL2_ERLC_STATS_STRUCT_H_
+
+#include "kal_public_api.h"
+#include "common_def.h"
+#include "el2_sap_common.h"
+#include "em_enl2_public_struct.h"
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/emac_api.h b/mcu/protocol/interface/enl2/el2/emac_api.h
new file mode 100644
index 0000000..3c66adb
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/emac_api.h
@@ -0,0 +1,598 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * emac_api.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 08 2019 kathie.ho
+ * [MOLY00428800] [MT6297] EMAC LTO warning clean up
+ * Solve LTO warning.
+ *
+ * 05 08 2019 kathie.ho
+ * [MOLY00404035] ENDC TDM PHICH Revision
+ * .
+ *
+ * 05 06 2019 shu-wei.ho
+ * [MOLY00402042] [Gen97][EMAC][EL1][ERLC] HRT Improvemnt, default off
+ * [EMAC][HRT] TXLISR part.
+ *
+ * 04 30 2019 frank.song
+ * [MOLY00401952] Sync Gen95 CL 6591981 to Gen97
+ *
+ * .
+ *
+ * 10 29 2018 shu-wei.ho
+ * [MOLY00361397] [B180623-440]¡i¥«?§ë?¡j¡iFT-¦¿?©y?¡jTSXXFK-2018062300002¡G¤âÉ󴡤J²¾?4G¥d¡AVOLTE³q?????¡]3/10¡^
+ * D4U5.
+ *
+ * 08 17 2018 shu-wei.ho
+ * [MOLY00339449] [Gen97][EMAC] General development check-in
+ * .Merge to VMOLY. (non MPD)
+ *
+ * 01 11 2018 jia-shi.lin
+ * [MOLY00301451] [SMO release][93/95]EL1 relative interface
+ * emac/el1 interface re-arch
+ *
+ * 07 12 2017 jia-shi.lin
+ * [MOLY00263796] [Gen93] EL1C always ticks PCSI during DRX off period which locks sleep mode
+ * add emac api emac_slp_cqi_srs_predict_result_rxlisr
+ *
+ * 07 11 2017 jia-shi.lin
+ * [MOLY00263426] [Bianco][N1][SRLTE][CT 6M C][LTE IOT][FT][CD][HW][TC-SMFT-07005]EE md1:(MCU_core0.vpe1.tc1(VPE1)) [ASSERT] file:mcu/pcore/modem/el2/common/el2_utility.c line:509
+ * relax the 1ms timing protection for ert sf proc
+ *
+ * 06 22 2017 nicole.hsu
+ * [MOLY00259119] [MT6763][EL2] EMAC/EL2EM/EL2POW maintenance
+ * [TRUNK] potential bug fix, RSIM EM, AT&T EM
+ *
+ * 06 09 2017 jia-shi.lin
+ * [MOLY00254140] [MT6293][EL1C] Reduce processing in RRC idle
+ * check in emac_txlisr_mt_chk_stage3()
+ *
+ * 06 09 2017 mf.jhang
+ * [MOLY00254140] [MT6293][EL1C] Reduce processing in RRC idle
+ * .Provide is emac_txlisr_active for EL1
+ *
+ * 05 19 2017 jia-shi.lin
+ * [MOLY00249306] [SE2 Internal Test][MT6293][UMOLYA][ATE][20170512][1][core0,vpe1,tc2(vpe1)] Assert fail emac_drx.c 811 - (LISR)EL1_C_TX
+ * 1. drx bug fix
+ * 2. mid ind to ert
+ * 3. dl wo pdsch ind
+ *
+ * 05 19 2017 nicole.hsu
+ * [MOLY00250929] [Copy CR][BIANCO][MT6763][RDIT][PHONE][Overnight][HQ][MTBF][Lab][Ericsson][ASSERT] file:mcu/l1core/modem/el1/el1c/phs/src/el1_phs_msg.c line:2429
+ * SCell new interface/design
+ *
+ * 04 18 2017 mf.jhang
+ * [MOLY00241929] [BIANCO][MT6763][RDIT][4GPS][RTD][HEAT][LTE_04_13_02_R12_UL64QUAM_2_UL64QAMonBothCCs_Type0]Assert fail: el1_meas_ctrl.c 11916 - EL1_MPC
+ * . Add EL1C command queue
+ *
+ * 04 05 2017 jia-shi.lin
+ * [MOLY00237731] [MT6293][L+L] Feature development
+ * [EMAC] Update EL1TX EMAC interface (EMAC part).
+ *
+ * 03 02 2017 jia-shi.lin
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * remove emac_force_phy_config_sch_close
+ *
+ * 01 19 2017 mf.jhang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * Split emac txlisr process into 3 stages for load balance
+ *
+ * 12 21 2016 nicole.hsu
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * [Seamless Meta Mode] EMAC part
+ * - provide dummy API to be called in Meta Mode
+ * - provide force sch_close API to be called before leaving Meta Mode
+ *
+ * 10 18 2016 jia-shi.lin
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * add one phich result type
+ *
+ * 10 05 2016 mf.jhang
+ * [MOLY00206476] [MT6293][NWSIM][Regression][TC_7_1_4_16] Failed at step 6
+ * add emac_ta_stag_ta_diff_exceeded
+ *
+ * 10 03 2016 nicole.hsu
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * 1. RAR grant size check and handling
+ * 2. fix PHR api for ra group selection
+ *
+ * 08 11 2016 yu-chun.chen
+ * [MOLY00176078] [EL1C] UMOLYA code sync
+ * Back out changelist 2711251
+ *
+ * 08 11 2016 nicole.hsu
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * 1. fix sim api warning
+ * 2. fix sim api prototype
+ * 3. provide rar_acsi_trigger assert function for el1tx
+ *
+ * 08 10 2016 shang-lun.chiu
+ * [MOLY00196539] [MT6293][EL1TX] Update comments to generate doxygen document
+ *
+ * 08 02 2016 wen-jiunn.liu
+ * [MOLY00194298] [UMOLYA] EL2 + EMAC Code Review
+ * Revise EL1-EMAC Interface
+ * - CRC Handler
+ * - DL Assignment
+ *
+ * 08 02 2016 nicole.hsu
+ * [MOLY00194987] [MT6293][PS DEV] EMAC maintenance
+ * [EMAC] ra api fix
+ *
+ * 08 01 2016 jeremy.chen
+ * [MOLY00190683] [UMOLYA][6293] EL2 merge back to UMOLYA TRUNK & PS DEV
+ *
+ * [EL2][RD domain] Sync EL2 interface from Aric CBr
+ *
+ ****************************************************************************/
+/**
+ * @file emac_api.h
+ * @brief EMAC Exported APIs to Other Libraries
+ *
+ * @author
+ * @date 2016/2/22
+ *
+ **/
+
+#ifndef __EMAC_API_H__
+#define __EMAC_API_H__
+
+#include "kal_public_api.h"
+#include "lte_time_common.h"
+#include "abs_time.h"
+#include "el1_emac_str.h"
+
+// =========================================
+// TTI Execution Process
+// =========================================
+
+/***************************************//**
+ * @brief Initialize the EMAC context before each TTI process
+ * @note Get air time from global variables / reset EMAC TTI related context
+ * @param protocol_idx
+ * @return (void)
+ ******************************************/
+void
+emac_txlisr_init_tti_proc(kal_uint32 protocol_idx);
+
+void
+emac_txlisr_proc_stage1();
+
+/***************************************//**
+ * @brief Main process for EMAC \n
+ * E.g., SCELL / TA / DL HARQ / UL HARQ / BSR / SR / RA / DRX
+ * @note Execution after all handler inputs are ready
+ * @param[in] p_sf_input Tx subframe parameter for EMAC, including information of
+ * - gap
+ * - subframe type
+ * .
+ * @return (void)
+ ******************************************/
+void
+emac_txlisr_proc_stage2(
+ emac_el1tx_tti_input_t* p_sf_input
+);
+
+void
+emac_txlisr_proc_stage3();
+
+kal_bool
+emac_txlisr_mt_chk_stage3();
+
+/***************************************//**
+ * @brief Invoke this function \@ g_abs_time to check if any
+ * EMAC handled TX requirement for tx_abs_time (g_abs_time +2)
+ * @note Called by EL1TX to query EMAC if there is any tx requirement \n
+ * One TXLISR / one TX requirement invoked (1-to-1 mapping) \n
+ * EL1 could NOT modify tx_bmp in the pointer
+ * @param (void)
+ * @return emac_el1tx_tx_req_struct* Pointer to TX request of this TTI
+ * in EMAC context \n
+ * The returned EMAC context will be cleared
+ * \@ emac_txlisr_init_tti_proc()
+ ******************************************/
+emac_el1tx_tx_req_struct*
+emac_txlisr_get_tx_req();
+
+#if EL1TX_EMAC_EARLY_ERT_SUPPORT
+/***************************************//**
+ * @brief TX process for EMAC \n
+ * E.g., MUX Decision ...
+ * @param[in] tx_results Bitmap of emac_el1tx_tx_bitmap_e
+ * @return (void)
+ ******************************************/
+void
+emac_el1_tx_result_handler(kal_uint32 tx_results);
+#endif
+/***************************************//**
+ * @brief Post process for EMAC \n
+ * E.g., MUX Decision / Clear UL HARQ Context / Clear TX Timeline / ...
+ * @note Execution after all handler inputs are ready
+ * @param[in] tx_results Bitmap of emac_el1tx_tx_bitmap_e
+ * @return (void)
+ ******************************************/
+void
+emac_txlisr_post_proc(
+ kal_uint32 tx_results
+);
+
+/***************************************//**
+ * @brief EMAC process in TXHISR for 93 (e.g., send ERT polling ILM)
+ * EMAC process in TXLISR for 95 (e.g., send ERT polling ILM)
+ * @note Called only in TXHISR for 93, called only in TXLISR for 95
+ * @param (void)
+ * @return (void)
+ ******************************************/
+void
+emac_tti_done_proc();
+
+// =========================================
+// TTI Input Handler Related APIs
+// =========================================
+
+/***************************************//**
+ * @brief Report n-2 or n-1 (i.e., g_abs_time -2 or -1) DCI result for DL HARQ \n
+ * Support only
+ * - C-RNTI
+ * - TC-RNTI
+ * - RA-RNTI
+ * - SPS-CRNTI (Act/Retx/Rel)
+ * .
+ * @note This function is used to update EMAC DL HARQ status \n
+ * DL unsolicited is NOT included (EMAC will calculate DL SPS) \n
+ * Indicate TB "new transmission" or not (instead of raw NDI value)
+ * @param[in] rcv_abs_time g_abs_time -1 or -2
+ * @param[in] p_pdcch_dl_info DL information carried in PDCCH
+ * @return (void)
+ ******************************************/
+void
+emac_pdcch_dl_assign_handler(
+ ABS_TICK_TIME rcv_abs_time,
+ el1tx_pdcch_dl_info_struct* p_pdcch_dl_info
+);
+
+/***************************************//**
+ * @brief Report n-2 or n-1 (i.e., g_abs_time -2 or -1) DCI result for UL HARQ \n
+ * Support only
+ * - C-RNTI
+ * - TC-RNTI
+ * - RA-RNTI
+ * - SPS-CRNTI (Act/Retx/Rel)
+ * .
+ * @note This function is used to update EMAC UL HARQ status \n
+ * UL unsolicited is NOT included (EMAC will calculate UL SPS)
+ * @param[in] ul_cc_idx UL CC index
+ * @param[in] rcv_abs_time g_abs_time -1 or -2
+ * @param[in] p_pdcch_ul_info UL information carried in PDCCH
+ * @return (void)
+ ******************************************/
+void
+emac_pdcch_ul_info_handler(
+ kal_uint8 ul_cc_idx,
+ ABS_TICK_TIME rcv_abs_time,
+ el1tx_pdcch_ul_info_struct* p_pdcch_ul_info
+);
+
+/***************************************//**
+ * @brief Report n-2 or n-1 (i.e., g_abs_time -2 or -1) PHICH result for UL HARQ
+ * @note This function is used to update EMAC UL HARQ status
+ * @param[in] ul_cc_idx UL CC index
+ * @param[in] harq_id HARQ ID
+ * @param[in] el1tx_phich_rlt_enum PHICH result
+ * @return (void)
+ ******************************************/
+void
+emac_pdcch_set_phich_result_handler(
+ kal_uint8 ul_cc_idx,
+ ABS_TICK_TIME rcv_abs_time,
+ kal_uint8 harq_id,
+ el1tx_phich_rlt_enum phich_result
+);
+
+/***************************************//**
+ * @brief - [TBC] Report n-3 or n-2 (i.e., g_abs_time -3 or -2)
+ * with each TB CRC decoding result
+ * - [TBC] Invoked after DL Assignment Handler\n
+ * With assumption of ignorance DCI for same TB within 4 subframes
+ * - [TBC] DCI v.s. CRC report is 1-to-1 mapping
+ * - Report only
+ * -- C-RNTI
+ * -- TC-RNTI
+ * -- SPS-CRNTI (Act/Retx/Config)
+ * .
+ * .
+ * @note TB information is with bitwise operation (BIT0 for TB0 : BIT1 for TB1)
+ * @param[in] p_crc_result CRC result information
+ * @return (void)
+ ******************************************/
+void
+emac_pdcch_set_crc_result_handler(
+ el1tx_pdcch_crc_result_struct* p_crc_result
+);
+
+/***************************************//**
+ * @brief Report n-2 or n-1 (i.e., g_abs_time -2 or -1) PDCCH order for RA
+ * @note If PDCCH order is received, call function to trigger PDCCH order RA process
+ * @param[in] rcv_abs_time g_abs_time -1 or -2
+ * @param[in] ul_cc_idx UL CC index
+ * @param[in] rapid RA preamble ID
+ * @param[in] mask RA mask index
+ * @return (void)
+ ******************************************/
+void
+emac_ra_pdcch_order_rcv(
+ ABS_TICK_TIME rcv_time,
+ kal_uint8 ul_cc_idx,
+ kal_uint8 rapid,
+ kal_uint8 mask
+);
+
+
+// =========================================
+// SPS Related APIs
+// =========================================
+
+/***************************************//**
+ * @brief Get UL SPS Active State in EMAC context
+ * @note This function is used to check current UL SPS state in
+ * EMAC context \@ TXLISR \n
+ * May be called in different threads, not TXLISR \n
+ * Caller should take care of multi-thread effects
+ * @param (void)
+ * @return KAL_TRUE: UL SPS is active \n
+ * KAL_FALSE: UL SPS is not active
+ ******************************************/
+kal_bool
+emac_sps_ul_get_active_state();
+
+
+// =========================================
+// UL HARQ Related APIs
+// =========================================
+
+/***************************************//**
+ * @brief Check if any UL HARQ for an UL CC is on-going
+ * @note This function is used to check PUSCH UL HARQ status \n
+ * Caller should take care of multi-thread effects \n
+ * @param[in] ul_cc_idx UL CC index
+ * @return KAL_TRUE: one or more UL HARQ are on-going \n
+ * KAL_FALSE: no UL HARQ is on-going
+ ******************************************/
+kal_bool
+emac_ul_harq_is_any_on_going(kal_uint8 ul_cc_idx);
+
+/***************************************//**
+ * @brief Predict if the grant is applied for TX based on
+ * the current UL HARQ view (Best Effort)
+ * @note This function is used to predict if the grant can be applied for TX
+ * based on the current EMAC UL HARQ view (Best Effort) \n
+ * Caller should take care of multi-thread effects \n
+ * May be called in TXLISR and RXLISR,
+ * EL1 should guarantees no simultaneous execution (no lock needed) for
+ * the same tx_abs_time
+ * @param[in] ul_cc_idx UL CC index
+ * @param[in] p_predict_req Grant to be predicted
+ * @return KAL_TRUE: grant is predicted as applied for TX in the
+ * current EMAC UL HARQ view \n
+ * KAL_FALSE: grant is predicted as NOT applied for TX in the
+ * current EMAC UL HARQ view
+ ******************************************/
+kal_bool
+emac_ul_harq_predict_grant_apply(
+ kal_uint8 ul_cc_idx,
+ el1tx_grant_apply_predict_req_struct* p_predict_req
+);
+
+/***************************************//**
+ * @brief emac_el1_txtimeline_extension_t should be defined by EL1 \n
+ * Return the EL1 extension memory (e.g., for implementing CQI only)
+ * @note Caller should take care of multi-thread effects \n
+ * EL1 extension will be cleared when TX timeline entry is cleared
+ * (\@ EMAC TXLISR post process)
+ * @param[in] ul_cc_idx UL CC index
+ * @param[in] tx_abs_time The time to refer to the timeline enrty
+ * @return Start address of EL1 extension
+ ******************************************/
+emac_el1_txtimeline_extension_t*
+emac_ul_harq_get_timeline_el1_extension(
+ kal_uint8 ul_cc_idx,
+ ABS_TICK_TIME tx_abs_time
+);
+
+/***************************************//**
+ * @brief Turn on/off EMAC's D4U5 UL64QAM workaround feature
+ * @note Call after tti init and before PDCCH procedure \n
+ * Caller should take care of multi-thread effects
+ * @param[in] is_feature_on on/off
+ * @return (void)
+ ******************************************/
+void
+emac_ul_harq_D4U5_Check_UL64QAM_feature_ctrl(
+ kal_bool is_feature_on
+);
+
+/***************************************//**
+ * @brief Notify EMAC config of tdm pattern change
+ * @note Call after tti init (emac_txlisr_init_tti_proc), and before other TTI function call
+ * Caller should take care of multi-thread effects
+ * @param[in] is_tdm_on on/off
+ * @param[in] subframe_bitmap (bit n represents subframe n in one frame, value 1'b means it's TX subframe;otherwise 0.
+ * @return (void)
+ ******************************************/
+ #ifdef __ENDC__
+void
+emac_tdm_pattern_config_change_handler(
+ kal_bool is_tdm_on,
+ kal_uint16 subframe_bitmap
+);
+#endif
+
+// =========================================
+// DRX Related APIs
+// =========================================
+
+/***************************************//**
+ * @brief When EL1TX has a periodic CQI transmission on PUCCH,
+ * EL1TX needs to
+ * call this function no later than <b>cqi_tx_time - 5</b>
+ * (EL1TX does NOT support now).
+ * The reason is that EMAC needs to calculate the admission for
+ * this CQI TX
+ * @note Caller should take care of multi-thread effects \n
+ * Currently, EL1TX need not call this API since EMAC will
+ * calculate the admission for CQI TX for every TTI \n
+ * When EL1TX can support the call of this function no later
+ * than <b>cqi_tx_time -5</b>, EMAC will only calculate the admission
+ * for CQI TX in <b>cqi_tx_time</b> to save the MIPS
+ * @param[in] cqi_tx_time CQI TX time
+ * @return (void)
+ ******************************************/
+void emac_drx_set_cqi_tx_time(ABS_TICK_TIME cqi_tx_time);
+
+/***************************************//**
+ * @brief When EL1TX has a type0 SRS transmission, EL1TX needs to
+ * call this function no later than <b>type0_srs_tx_time - 5</b>.
+ * The reason is that EMAC needs to calculate the admission for this SRS TX
+ * @note Caller should take care of multi-thread effects \n
+ * Currently, EL1TX need not call this API since EMAC will
+ * calculate the admission for type0 SRS TX for every TTI \n
+ * When EL1TX can support the call of this function no later
+ * than <b>type0_srs_tx_time -5</b>, EMAC will only calculate the admission
+ * for type0 SRS TX in <b>type0_srs_tx_time</b> to save the MIPS
+ * @param[in] type0_srs_tx_time type0 SRS TX time
+ * @return (void)
+ ******************************************/
+void emac_drx_set_type0_srs_tx_time(ABS_TICK_TIME type0_srs_tx_time);
+
+/***************************************//**
+ * @brief EMAC will return the TX admission of cqi and type0 srs
+ * for tx_abs_time
+ * @note emac_drx_set_cqi_tx_time or emac_drx_set_type0_srs_tx_time should be called
+ * before emac_drx_cqi_srs_admin is called \n
+ * Caller should take care of multi-thread effects \n
+ * The timing for calling this API is expected to be after the EMAC TTI
+ * process of <b>tx_abs_time -2</b>
+ * @param[in] tx_abs_time periodic CQI and type0 SRS time
+ * @param[out] p_cqi_srs_admin_info admission information of periodic CQI and type0 SRS
+ * @return (void)
+ ******************************************/
+void emac_drx_cqi_srs_admin(ABS_TICK_TIME tx_abs_time,
+ emac_el1tx_drx_cqi_srs_admin_info_struct * p_cqi_srs_admin_info);
+
+
+/***************************************//**
+ * @brief DL without PDSCH occurs
+ * @note when DL without PDSCH occurs, call this api
+ * @param[in] rcv_abs_time the rcv_abs_time for this DL
+ * @return (void)
+ ******************************************/
+void emac_drx_dl_wo_pdsch_handler(ABS_TICK_TIME rcv_abs_time);
+
+
+
+// =========================================
+// SLEEP Related APIs
+// =========================================
+
+kal_bool emac_slp_is_prev1_dci_info_required(void);
+kal_bool emac_slp_cqi_srs_predict_result_rxlisr(ABS_TICK_TIME tx_abs_time);
+
+// =========================================
+// RA Related APIs
+// =========================================
+
+kal_bool emac_ra_is_rar_grant_valid(el1tx_pdcch_ul_info_struct* p_grant);
+void emac_ra_set_max_txpower_reached();
+void emac_ra_rar_acsi_trigger_fail();
+void emac_ra_tcrnti_ack_add_fail();
+void emac_ra_set_last_prach_tx_power(kal_uint8 prach_tx_power);
+
+// =========================================
+// PHR Related APIs
+// =========================================
+
+kal_bool emac_el1_phr_res_handler(emac_el1tx_phr_res_struct phr_content);
+
+// =========================================
+// TA Related APIs
+// =========================================
+void emac_ta_stag_ta_diff_exceeded(kal_uint32 stag_id);
+
+// =========================================
+// SCELL Related APIs
+// =========================================
+#if defined(__MD93__)
+ //just for fix build fail, not final solution
+ void emac_scell_el1c_cnf();
+#elif(CUR_GEN>=MD_GEN95)
+ void emac_scell_el1c_cnf(kal_uint8 cc_cnf_bmp);
+#endif
+void emac_scell_rel(kal_uint32 cc_idx);
+
+kal_bool emac_txlisr_active(ABS_TICK_TIME cur_abs_time);
+kal_bool emac_txlisr_tx_checksum_error_bypass_check(ABS_TICK_TIME tx_abs_time);
+
+// =========================================
+// META_MODE Related APIs
+// =========================================
+void emac_dummy_txlisr_init_tti_proc(kal_uint32 protocol_idx);
+void emac_dummy_txlisr_post_proc(kal_uint32 tx_results);
+void emac_dummy_txlisr_proc(emac_el1tx_tti_input_t* p_sf_input);
+void emac_dummy_tti_done_proc();
+void emac_dummy_txlisr_proc_stage1();
+void emac_dummy_txlisr_proc_stage3();
+
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/emacmch_rxlisr_interface.h b/mcu/protocol/interface/enl2/el2/emacmch_rxlisr_interface.h
new file mode 100644
index 0000000..d242a3c
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/emacmch_rxlisr_interface.h
@@ -0,0 +1,171 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * emacmch_rxlisr_interface.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * Declare the structures/enum/functions(api)/global variables that are
+ * shared with or called by RX LISR.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 31 2017 eddie.wang
+ * [MOLY00236421] [MT6293][UMOLYA][TRUNK]
+ * [EMACMCH][L+L] Add pidx for RXLISR query next mch interface
+ *
+ * 12 12 2016 eddie.wang
+ * [MOLY00210650] [MT6293][UMOLYA TRUNK] EMAC maintenance
+ * [EMUX][EMACMCH] Introduce debug mode
+ *
+ * 09 23 2016 eddie.wang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * Sync PS.DEV to TRUNK up to CL2868873
+ *
+ * 09 20 2016 eddie.wang
+ * [MOLY00197177] Code maintenance on UMOLYA.PS.DEV
+ * EMUX and EMACMCH code/trace maintenance
+ *
+ * 07 27 2016 jeremy.chen
+ * [MOLY00190683] [UMOLYA][6293] EL2 merge back to UMOLYA TRUNK & PS DEV
+ * [EL2][RD domain] Sync latest EL2 from LTE domain
+ *
+ ****************************************************************************/
+/**
+ * @file emacmch_rxlisr_interface.h
+ * @brief Declare the structures/enum/functions(api)/global variables that are
+ * shared with or called by RX LISR
+ * @author mtk04120
+ * @date 2016/2/22
+ *
+ **/
+#ifndef EMACMCH_RXLISR_INTERFACE_H
+#define EMACMCH_RXLISR_INTERFACE_H
+
+#include "kal_public_api.h"
+
+#include "el1_enum.h"
+
+/*---------------------------------------------------------------------------
+ * DEFINITION
+ *---------------------------------------------------------------------------*/
+/* Configurable */
+
+/* User-defined */
+
+/* Constant */
+
+/*---------------------------------------------------------------------------
+ * ENUM
+ *---------------------------------------------------------------------------*/
+
+
+/*---------------------------------------------------------------------------
+ * STRUCTURE
+ *---------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------
+ * STRUCTURE
+ *---------------------------------------------------------------------------*/
+/*------------------
+ * Structure Level 3
+ *------------------*/
+
+/*------------------
+ * Structure Level 2
+ *------------------*/
+
+/*------------------
+ * Structure Level 1
+ *------------------*/
+typedef struct{
+
+ kal_uint32 tid;
+ kal_bool b_valid;
+
+ kal_uint8 syncarea_id;
+ kal_uint8 area_id; //0-255
+ kal_uint8 pmch_id; //pmch_ie_idx
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ kal_uint8 non_mbsfn_region_len;
+
+ kal_bool is_mch_reliable; // True when MCCH, MSI, UE-interested MTCH in MSI
+
+ kal_bool is_signal_mcs;
+ kal_bool is_higher_order_mcs; // FALSE if signalMCS
+ kal_uint8 mcs;
+
+ el1_embms_gemini_priority_enum gemini_priority;
+
+ kal_uint32 sf_no;
+ kal_uint64 abs_time;
+
+}emacmch_rxlisr_sched_mch_t;
+/*---------------------------------------------------------------------------
+ * Extern global variable declarations
+ *---------------------------------------------------------------------------*/
+
+/*---------------------------------------------------------------------------
+ * public methods prototype for RX LISR
+ *---------------------------------------------------------------------------*/
+
+void
+emacmch_rxlisr_query_next_sched_mch(kal_uint64 _abs_time, //IN
+ kal_uint8 _syncarea_id, //IN
+ emacmch_rxlisr_sched_mch_t* _next_sched, //OUT
+ kal_uint32 _pidx); //IN
+
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/epdcp_enum.h b/mcu/protocol/interface/enl2/el2/epdcp_enum.h
new file mode 100644
index 0000000..128d82d
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/epdcp_enum.h
@@ -0,0 +1,321 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * epdcp_enum.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 25 2019 jia-shi.lin
+ * [MOLY00460829] [MT6885][Petrus][MP1][SQC][CT][NSIOT][HQ][KS][N78][SA][CTC_DP_6.2.3][TC-MF_NR_DT-02003]SA UL256QAM Tput not as expected
+ * 1. new sit_update msg from nl1
+ * 2. sit update profile
+ *
+ * 10 14 2019 yiting.cheng
+ * [MOLY00442846] [Gen97] Modem´¼¯à«ÝÉófeature - NSA part (implementation)
+ * .
+ *
+ * 04 25 2019 ken.li
+ * [MOLY00383711] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G]: Assert Fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ *
+ * EPDCP DL OOB and HFN desync handling
+ *
+ * 04 22 2019 ken.li
+ * [MOLY00383711] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G]: Assert Fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ *
+ * EPDCP DL OOB and HFN desync handling
+ *
+ * 08 17 2018 yk.liu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * merge EMOLY CLs to VMOLY
+ *
+ * 07 05 2018 head.hsu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * restructure:
+ * 1.fix some warning
+ * 2.remove legacy file
+ * 3.remove some phase-out context
+ * 4.rename internal term from epdcp to enpdcp
+ * 5.add trace
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ *
+ * 05 18 2018 head.hsu
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * port latest interface and code on Gen97.DEV (PDCP UL dummy)
+ *
+ * 07 13 2017 steve.kao
+ * [MOLY00264004] [6293] EPDCP R-SIM code changes and UT with bugfixes
+ *
+ * [UMOLYA][TRUNK] EPDCP changes for L+L, R-SIM, UT, and bugfixes.
+ *
+ * 05 04 2017 steve.kao
+ * [MOLY00246810] [BIANCO][MT6763][RDIT][FT][CMCC][BJ][TDL Case][1.3.1][ASSERT] file:mcu/pcore/modem/el2/el2/epdcp/src/epdcp_dl.c line:4692
+ * [UMOLYA][TRUNK][EPDCP] Handling flag V in LHIF mode handlers, and modify logs.
+ *
+ * 04 07 2017 steve.kao
+ * [MOLY00230062] [UMOLYA] M-PS related interface changes for UPCM, RATDM, and EPDCP
+ *
+ * [UMOLYA][TRUNK]
+ *
+ * [UPCM][M-PS] Code changes
+ * 1. Duplicating UPCM contexts,
+ * 2. Use protocol_idx in UL/DL callback/ILM interfaces,
+ * 3. Check protocol_idx in LHIF PIT entries,
+ * 4. Fix test mode UL data processing flow,
+ * 5. Allowing test mode on protocol 2/3/4,
+ * 6. Wrap interfaces with RATDM with __MULTIPLE_PS__,
+ *
+ * [EPDCP][L+L] Code changes
+ *
+ * [RATDM][L+L] Code changes
+ *
+ * 02 21 2017 steve.kao
+ * [MOLY00230998] [6293][EL2][EPDCP] Simplified DL mode switching.
+ * [UMOLYA][TRUNK][EPDCP] Simplified DL mode switch for NETIF binding.
+ *
+ * 11 01 2016 steve.kao
+ * [MOLY00195563] [6293][EL2][UPCM][RATDM][EPDCP] Initial feature integrations
+ * [UMOLYA_TRUNK][EPDCP] Add DL traces & fix c-model bugs.
+ *
+ * 01 21 2016 mingtsung.sun
+ * [MOLY00160421] [MT6292] ePDCP CE RAM Optimization
+ * [EPDCP] CE RAM OPT.
+ *
+ * 06 15 2015 mingtsung.sun
+ * [MOLY00121332] [TK6291] 4G EAS low power check in
+ * eL2 low power and ePDCP code sync: mcu\common\modem\lte_sec\...
+ *
+ * 07 04 2013 timothy.yao
+ * [MOLY00028092] [MT6290E1][EL2 IT] fix the log statement
+ * 1. fix variable order in log statement.
+ * 2. apply heximal & enum usage.
+ ****************************************************************************/
+#ifndef ENPDCP_ENUM_INC
+#define ENPDCP_ENUM_INC
+
+#include "enl2_def.h"
+
+/**
+* @brief RB state (SRB/DRB)
+*/
+typedef enum
+{
+ /* for RB entity/record common use */
+ RB_ST_NONE = 0,
+ RB_ST_ACTIVE,
+ RB_ST_SUSPENDED,
+ RB_ST_HANDOVER,
+
+ /* for RB record specific use */
+ RB_ST_HO_N_SUSP,
+ RB_ST_HO_N_ACTV,
+
+#if ENPDCP_REMOTE_SIM
+ /* for virtual connectivity */
+ RB_ST_VIRT_CONN_N_SUSP,
+ RB_ST_VIRT_CONN_N_ACTV,
+#endif
+
+} enpdcp_rb_st_e;
+
+typedef enum
+{
+ DETN_TMR3_MONTR_LV_OFF = 0,
+ DETN_TMR3_MONTR_LV_DRB,
+ DETN_TMR3_MONTR_LV_ALL_RB,
+} detnTmr3_montr_lv_e;
+
+typedef enum
+{
+ DETN_TMR3_PHASE_RRC = 0,
+ DETN_TMR3_PHASE_NAS,
+} detnTmr3_phase_e;
+
+typedef enum
+{
+ TMR_ST_STOPPED = 0,
+ TMR_ST_RUNNING,
+ TMR_ST_TIMEOUT
+} tmr_st_e;
+
+typedef enum
+{
+ ENPDCP_EC_OK = 0,
+
+ /* common */
+ ENPDCP_EC_INV_RB_NUM,
+ ENPDCP_EC_INV_RB_ID,
+ ENPDCP_EC_INV_RB_IDX,
+ ENPDCP_EC_UNEXP_RB_STATE,
+
+ /* Loopback TEST-REQ */
+ ENPDCP_EC_DRB_LB_ENABLED,
+
+ /* CONFIG-REQ */
+ ENPDCP_EC_SEC_CFG_WO_SRB1,
+ ENPDCP_EC_ADD_SRB2_DRB_WO_FULL_SEC,
+ ENPDCP_EC_INV_ADD_RB_ID,
+ ENPDCP_EC_INV_ADD_RB_IDX,
+ ENPDCP_EC_INV_ADD_RB_CMD,
+ ENPDCP_EC_INV_ADD_UM_DIR,
+ ENPDCP_EC_INV_MOD_RB_ID,
+ ENPDCP_EC_INV_MOD_RB_IDX,
+ ENPDCP_EC_INV_MOD_RB_CMD,
+ ENPDCP_EC_INV_MOD_UM_DIR,
+ ENPDCP_EC_INV_DEL_RB_ID,
+ ENPDCP_EC_INV_DEL_RB_IDX,
+ ENPDCP_EC_INV_DEL_RB_CMD,
+
+ /* DCCH_DATA_REQ */
+ ENPDCP_EC_INV_TGPD,
+ ENPDCP_EC_INV_PEER_BUF_PTR,
+
+ /* LTM_DATA_REQ */
+ ENPDCP_EC_INV_PRI_DATA_LIST,
+ ENPDCP_EC_INV_NML_DATA_LIST,
+ ENPDCP_EC_RB_UL_DIR_DISABLED,
+ ENPDCP_EC_RB_UL_FLOW_CTRL,
+
+ ENPDCP_EC_MAX
+} enpdcp_errcode_e;
+
+/////// ENPDCP DL related ///////
+/**
+ * @brief RB DL config stages (DRB)
+ */
+typedef enum
+{
+ DRB_DL_CFG_STG_NORMAL = 0,
+
+ // When the DL CFG STG is not NORMAL, then the DL mode of the DRB might be
+ // in the midst of being changed from VRB-mode to LHIF-mode .
+
+ /* REEST: AM DRB should be with VRB-RO */
+ DRB_DL_CFG_STG_REEST_FLUSHING,
+ DRB_DL_CFG_STG_REEST_REORDERING,
+ DRB_DL_CFG_STG_REEST_WAIT_FOR_HFN_SYNC,
+ DRB_DL_CFG_STG_REEST_DCIP_SUSPENDING,
+ DRB_DL_CFG_STG_REEST_WAIT_FOR_DELIVERY,
+ /* REEST: AM DRB should be with VRB-RO */
+
+ /* HFN Resync when not in reest stage: AM DRB should be with VRB-RO */
+ DRB_DL_CFG_STG_HFN_RESYNC_WAIT_FOR_HFN_SYNC,
+ DRB_DL_CFG_STG_HFN_RESYNC_DCIP_SUSPENDING,
+ DRB_DL_CFG_STG_HFN_RESYNC_WAIT_FOR_DELIVERY,
+ /* HFN Resync when not in reest stage: AM DRB should be with VRB-RO */
+
+ /* LWA */
+ DRB_DL_CFG_STG_EN_LWA_DCIP_SUSPENDING, // suspend DCIP for APRO enabling // TODO: REMOVE
+ DRB_DL_CFG_STG_EN_LWA_WAIT_APRO_CNF// TODO: REMOVE
+ /* LWA */
+} enpdcp_drb_dl_cfg_stg_e;
+
+typedef enum
+{
+ RB_DL_MODE_BIT_RO_ON = 0x1, // o.w. RO_OFF
+ RB_DL_MODE_BIT_DEST_VRB = 0x2, // o.w. DEST_LHIF
+} enpdcp_rb_dl_mode_bit_e;
+
+typedef enum
+{
+ RB_DL_MODE_LHIF_NRO = 0,
+ RB_DL_MODE_LHIF_RO = RB_DL_MODE_BIT_RO_ON,
+ RB_DL_MODE_VRB_NRO = RB_DL_MODE_BIT_DEST_VRB,
+ RB_DL_MODE_VRB_RO = RB_DL_MODE_BIT_DEST_VRB | RB_DL_MODE_BIT_RO_ON
+} enpdcp_rb_dl_mode_e;
+
+typedef enum{
+ ENPDCP_ILM_INVALID,
+ ENPDCP_ILM_ACCEPT,
+ ENPDCP_ILM_IGNORE
+} enpdcp_ilm_check_enum;
+
+typedef enum
+{
+ DL_MODE_SWITCH_CAUSE_BECOME_LHIF_MODE_CAPABLE = 0,
+ DL_MODE_SWITCH_CAUSE_DIS_TESTMODE,
+ DL_MODE_SWITCH_CAUSE_WAIT_FOR_DELIVERY_DONE,
+ DL_MODE_SWITCH_CAUSE_DIS_FORCED_INDIRECT_PATH,
+} dl_mode_switch_cause_e;
+
+typedef enum
+{
+ EPDCP_DL_LOG_LEVEL_RAW = 0,
+ EPDCP_DL_LOG_LEVEL_REFINED,
+} epdcp_dl_log_level_e;
+
+typedef enum
+{
+ EPDCP_UL_LOG_LEVEL_RAW = 0,
+ EPDCP_UL_LOG_LEVEL_REFINED,
+} epdcp_ul_log_level_e;
+
+typedef enum
+{
+ DRB_DL_HFN_SYNC = 0,
+ DRB_DL_HFN_RESYNC_DONE,
+ DRB_DL_HFN_DESYNC_TRY_CUR_HFN,
+ DRB_DL_HFN_DESYNC_DCIP_RESUME_TRYING,
+ DRB_DL_HFN_DESYNC_DCIP_SUSPEND,
+ DRB_DL_HFN_DESYNC_DCIP_SUSPEND_RESET_HFN,
+} epdcp_drb_dl_hfn_sync_stg_e;
+
+typedef enum
+{
+ ENPDCP_FUNC_SIT_UPDATE,
+ ENPDCP_FUNC_NRLC_PREGEN
+} enpdcp_func_profile_e;
+
+
+#endif // ~ #ifndef ENPDCP_ENUM_INC
diff --git a/mcu/protocol/interface/enl2/el2/errc_emac_msg.h b/mcu/protocol/interface/enl2/el2/errc_emac_msg.h
new file mode 100644
index 0000000..ddc7f84
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/errc_emac_msg.h
@@ -0,0 +1,1025 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * errc_emac_msg.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Define ERRC EMAC interface enums, structures and constants
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 06 2020 kathie.ho
+ * [MOLY00555285] [TITAN][M70][Requirement]API requirements to read cell parameters
+ * ICD (for BVD)
+ *
+ * 08 06 2020 kathie.ho
+ * [MOLY00555285] [TITAN][M70][Requirement]API requirements to read cell parameters
+ * ICD for EMAC.
+ *
+ * 12 17 2018 hamilton.liang
+ * [MOLY00332682] Gen97 relevant feature/structure change
+ *
+ * VMOLY Eiger with ENL2 porting - EMAC part
+ *
+ * 12 14 2018 hamilton.liang
+ * [MOLY00332682] Gen97 relevant feature/structure change
+ *
+ * [Interface][EMAC<->ERRC] AS release upgrade (support R14/R15 and relevant category upgrade)
+ * NOTE1: Also add the TB trace for DL5CCs
+ * NOTE2: Currently the LCID start index will be set based on R13 if the support release is either R14 or R15, and it will be changed in the future.(there are some code change)
+ *
+ * 12 13 2018 frank.song
+ * [MOLY00368654] [Gen97][Apollo][SMO][4-D][G2] EMAC_PUBLIC
+ * .
+ *
+ * 11 01 2018 shu-wei.ho
+ * [MOLY00361478] [Gen97] Gemini Compile Option Clean Up
+ * .
+ *
+ * 10 31 2018 shu-wei.ho
+ * [MOLY00346626] [Gen97][EMAC] Merge Gen95 CLs on Gen97 and patch back to VMOLY TRUNK
+ * EMAC-ERRC interface (extend RA/TA configuartion).
+ *
+ * 10 24 2018 frank.song
+ * [MOLY00360281] Sync Gen95 CL 9/10~9/23
+ * .
+ *
+ * 10 04 2018 kathie.ho
+ * [MOLY00351549] Gen97 EMAC check-in
+ * ENDC (TDM pattern) interface
+ *
+ * 08 30 2018 shin.chen
+ * [MOLY00348952] [Gen97]June Version ASN.1 migration patch back
+ * .
+ *
+ * 08 17 2018 shu-wei.ho
+ * [MOLY00339449] [Gen97][EMAC] General development check-in
+ * .Merge to VMOLY. (non MPD)
+ *
+ * 07 24 2018 kathie.ho
+ * [MOLY00341764] [Gen97] remove enum errc_el2_cfg_result_enum
+ * remove errc emac result enum.
+ * [Protocol build tag]
+ * [Is CL self testable: NO]
+ * [Group CL list: WAIT]
+ *
+ * 05 30 2018 kathie.ho
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * Gen97 ENDC ERRC-EMAC interface.
+ *
+ * 04 18 2018 shu-wei.ho
+ * [MOLY00320629] [6297] PS.DEV patch back to GEN97.DEV
+ * .Fix errc_emac msg error
+ *
+ * 03 28 2018 shin.chen
+ * [MOLY00316692] [6297] Interface build-up for ERRC-NRRC, ERRC/NRRC-ENL2, ERRC-EL2 SAP
+ * update el2 interfaces.
+ *
+ * 01 11 2018 jia-shi.lin
+ * [MOLY00301451] [SMO release][93/95]EL1 relative interface
+ * emac/el1 interface re-arch
+ *
+ * 09 20 2017 nicole.hsu
+ * [MOLY00279184] [PCT][Anritsu][CAG50C][E40][7.1.1.2] fail
+ * [TRUNK] LCID vs. support release handling
+ *
+ * 08 16 2017 guang-yu.zheng
+ * [MOLY00271123] [MT6293][EMAC] SRLTE-enhance feature code sync
+ * Add EMAC interface for SRLTE enhancement handling
+ *
+ * 01 25 2017 eddie.wang
+ * [MOLY00210650] [MT6293][UMOLYA TRUNK] EMAC maintenance
+ * [MSIM][RSIM] Add emac config req cause for remote sim scenario
+ *
+ * 12 26 2016 mf.jhang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * update errc_emac_ca_activate_ind_struct
+ *
+ * 11 08 2016 mf.jhang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * Update errc_emac_ca_activate_ind_struct
+ *
+ * 10 06 2016 eddie.wang
+ * [MOLY00206522] [MT6293][NWSIM][Regression][TC_7_1_4_18] Test failed
+ * TRUNK:Remove redundant config like extendedBSR and MBMS in emac_config_req
+ *
+ * 09 13 2016 nicole.hsu
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * [xL1Sim] remove errc_emac_config old field - tti_bundling_flag
+ *
+ * 03 16 2016 yk.liu
+ * [MOLY00165181] Syn EMAC from LR11 TO UMOLY for CL1990358
+ * .
+ *
+ * 03 15 2016 ryan.ou
+ * [MOLY00162291] [MT6292] EMAC code sync from LR11 to UMOLY
+ * CL1867764, [MOLY00151000] [MT6755] SRVCC Enhancement.
+ *
+ * 01 11 2016 ville.pukari
+ * [MOLY00156411] [MT6292] Logical Channel SR prohibit timer: New feature
+ *
+ * 10 16 2015 panu.peisa
+ * [MOLY00145084] DE6 code merge from UMOLY_92dev CBr to UMOLY trunk
+ * Integrated LTE_SEC changes from UMOLY_92dev ( errc part ).
+ *
+ * 10 06 2015 esko.oikarinen
+ * ERRC changes for multiple TA
+ *
+ * 09 10 2015 chun-fan.tsai
+ * [MOLY00098400] [6291] eRRC CONN EM
+ * Add CCCH Data Req cause for EMAC EM
+ *
+ * 03 18 2015 chen-wei.wang
+ * [MOLY00099525] [TK6291] EMAC MDT feature check-in
+ * interface file check-in
+ *
+ * 12 03 2014 sh.yang
+ * [MOLY00084081] [UMOLY] Trunk merge back
+ * .Add carrier index in si_ind_struct
+ *
+ * 11 11 2014 yiting.cheng
+ * [MOLY00084042] [UMOLY] merge UMOLY_DEV to UMOLY trunk
+ * .
+ *
+ * 10 08 2014 henry.lai
+ * [MOLY00079071] [MT6291][U4G] Low Power Modification for CEL Paging
+ * .
+ *
+ * 09 19 2014 chi-chung.lin
+ * [MOLY00073836] [MT6291][ERRC][CHM] LTE-A CHM development code check-in
+ * [CHM] MBMS interface check in
+ *
+ * 07 28 2014 yiting.cheng
+ * [MOLY00073830] [MT6291_DEV] check-in MT6291 modification
+ * Check-in EMAC-ERRC interface
+ *
+ * 08 06 2013 stanleyhy.chen
+ * [MOLY00032633] 4G Nbr Cell Info
+ * 4G Nbr Cell Info in LTE Domain
+ *
+ * 07 22 2013 stanleyhy.chen
+ * [MOLY00029602] [New Feature] NBR_CELL_INFO and TA_INFO related interfaces
+ * Add ERRC_EMAC_TA_INFO_INVALID_IND
+ *
+ * 07 12 2013 stanleyhy.chen
+ * [MOLY00029602] [New Feature] NBR_CELL_INFO and TA_INFO related interfaces
+ * TA_INFO and NBR_CELL_INFO interfaces for LPP feature
+ ****************************************************************************/
+
+#ifndef ERRC_EMAC_MSG_H
+#define ERRC_EMAC_MSG_H
+
+
+#include "kal_public_api.h"
+#include "el2_sap_common.h"
+#include "qmu_bm.h"
+#include "lte_time_common.h"
+#include "common_def.h"
+
+#if !defined(__XL1SIM_EL1__) && defined(__LTE_L1SIM__)
+#define __XL1SIM_EL1__
+#endif
+////////////////////////////////////////////////////////////////
+// MAC configuration request
+////////////////////////////////////////////////////////////////
+
+//mac config request info bitmap
+#define EMAC_CONFIG_INFO_RA_MASK 0x01
+#define EMAC_CONFIG_INFO_SCHED_MASK 0x02
+#define EMAC_CONFIG_INFO_DRX_MASK 0x04
+#define EMAC_CONFIG_INFO_PHR_MASK 0x08
+#define EMAC_CONFIG_INFO_CRNTI_MASK 0x10
+
+#define ERRC_EMAC_CCCH_SZ (6)
+
+//max number of RB
+#define ERRC_EMAC_MAX_RB_NB (10)
+
+//max number of STAG/SCell
+#if(CUR_GEN >= MD_GEN95)
+#define ERRC_EMAC_MAX_STAG_NB (1)
+#define ERRC_EMAC_MAX_SCELL_NB (4)
+#else
+#define ERRC_EMAC_MAX_STAG_NB (1)
+#define ERRC_EMAC_MAX_SCELL_NB (1)
+#endif
+
+
+
+typedef enum
+{
+ ERRC_EMAC_CONFIG_CAUSE_NON_HO = 0,
+ ERRC_EMAC_CONFIG_CAUSE_HO = 1,
+ ERRC_EMAC_CONFIG_CAUSE_RESET = 2,
+#ifdef __GEMINI__
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_ENTER = 3,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE_PREPARE = 4,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE = 5,
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_LEAVE_FAIL = 6,
+ //The design for SRLTE enhancement will be the same as RSIM, but we still seperate the cause
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_ENTER_FOR_SRLTE = 7,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE_PREPARE_FOR_SRLTE = 8,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE_FOR_SRLTE = 9,
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_LEAVE_FAIL_FOR_SRLTE = 10,
+#endif
+} errc_emac_config_cause_enum;
+
+//For ICD MAC_RESET_EVENT and MAC_CONFIGURATION_EVENT
+typedef enum
+{
+ ERRC_EMAC_ICD_RESET_CAUSE_OTHERS = 0,
+ ERRC_EMAC_ICD_RESET_CAUSE_RELEASE = 1,
+ ERRC_EMAC_ICD_RESET_CAUSE_HO = 2,
+ ERRC_EMAC_ICD_RESET_CAUSE_RLF = 3,
+ /* Please must update this if RESET enum increase */
+ ERRC_EMAC_ICD_RESET_CAUSE_MAX_NUM = ERRC_EMAC_ICD_RESET_CAUSE_RLF,
+ ERRC_EMAC_ICD_CONFIG_CAUSE_NORMAL = 4,
+ ERRC_EMAC_ICD_CONFIG_CAUSE_HO = 5,
+} errc_emac_icd_event_cause_enum;
+
+typedef enum
+{
+ ERRC_EMAC_TA_TIMER_500, ERRC_EMAC_TA_TIMER_750, ERRC_EMAC_TA_TIMER_1280, ERRC_EMAC_TA_TIMER_1920,
+ ERRC_EMAC_TA_TIMER_2560, ERRC_EMAC_TA_TIMER_5120, ERRC_EMAC_TA_TIMER_10240, ERRC_EMAC_TA_TIMER_INF
+} errc_emac_ta_timer_enum;
+
+typedef enum
+{
+ RA_PREAMBLE_NB_4, RA_PREAMBLE_NB_8, RA_PREAMBLE_NB_12, RA_PREAMBLE_NB_16,
+ RA_PREAMBLE_NB_20, RA_PREAMBLE_NB_24, RA_PREAMBLE_NB_28, RA_PREAMBLE_NB_32,
+ RA_PREAMBLE_NB_36, RA_PREAMBLE_NB_40, RA_PREAMBLE_NB_44, RA_PREAMBLE_NB_48,
+ RA_PREAMBLE_NB_52, RA_PREAMBLE_NB_56, RA_PREAMBLE_NB_60,RA_PREAMBLE_NB_64
+} errc_emac_ra_preamble_nb_enum;
+
+typedef enum
+{
+ RA_GROUP_A_SZ_4, RA_GROUP_A_SZ_8, RA_GROUP_A_SZ_12, RA_GROUP_A_SZ_16,
+ RA_GROUP_A_SZ_20, RA_GROUP_A_SZ_24, RA_GROUP_A_SZ_28, RA_GROUP_A_SZ_32,
+ RA_GROUP_A_SZ_36, RA_GROUP_A_SZ_40, RA_GROUP_A_SZ_44, RA_GROUP_A_SZ_48,
+ RA_GROUP_A_SZ_52, RA_GROUP_A_SZ_56, RA_GROUP_A_SZ_60
+} errc_emac_ra_group_a_sz_enum;
+
+typedef enum
+{
+ RA_GROUP_A_MSG_SZ_56, RA_GROUP_A_MSG_SZ_144, RA_GROUP_A_MSG_SZ_208, RA_GROUP_A_MSG_SZ_256
+} errc_emac_ra_msg_sz_group_a_enum;
+
+typedef enum
+{
+ MSG_POW_OFFSET_GROUP_B_MINUS_INF, MSG_POW_OFFSET_GROUP_B_0, MSG_POW_OFFSET_GROUP_B_5,
+ MSG_POW_OFFSET_GROUP_B_8, MSG_POW_OFFSET_GROUP_B_10, MSG_POW_OFFSET_GROUP_B_12,
+ MSG_POW_OFFSET_GROUP_B_15, MSG_POW_OFFSET_GROUP_B_18
+} errc_emac_msg_pow_offset_group_b_enum;
+
+typedef enum
+{
+ RA_POW_RAMPING_0, RA_POW_RAMPING_2, RA_POW_RAMPING_4, RA_POW_RAMPING_6
+} errc_emac_ra_pow_ramping_enum;
+
+typedef enum
+{
+ PREAMBLE_INIT_POW_MINUS120, PREAMBLE_INIT_POW_MINUS118, PREAMBLE_INIT_POW_MINUS116,
+ PREAMBLE_INIT_POW_MINUS114, PREAMBLE_INIT_POW_MINUS112, PREAMBLE_INIT_POW_MINUS110,
+ PREAMBLE_INIT_POW_MINUS108, PREAMBLE_INIT_POW_MINUS106, PREAMBLE_INIT_POW_MINUS104,
+ PREAMBLE_INIT_POW_MINUS102, PREAMBLE_INIT_POW_MINUS100,
+ PREAMBLE_INIT_POW_MINUS98, PREAMBLE_INIT_POW_MINUS96, PREAMBLE_INIT_POW_MINUS94,
+ PREAMBLE_INIT_POW_MINUS92, PREAMBLE_INIT_POW_MINUS90
+} errc_emac_preamble_init_pow_enum;
+
+typedef enum
+{
+ PREAMBLE_TX_MAX_3, PREAMBLE_TX_MAX_4, PREAMBLE_TX_MAX_5, PREAMBLE_TX_MAX_6,
+ PREAMBLE_TX_MAX_7, PREAMBLE_TX_MAX_8, PREAMBLE_TX_MAX_10, PREAMBLE_TX_MAX_20,
+ PREAMBLE_TX_MAX_50, PREAMBLE_TX_MAX_100, PREAMBLE_TX_MAX_200
+} errc_emac_preamble_tx_max_enum;
+
+typedef enum
+{
+ RAR_WND_SZ_2, RAR_WND_SZ_3, RAR_WND_SZ_4, RAR_WND_SZ_5, RAR_WND_SZ_6, RAR_WND_SZ_7,
+ RAR_WND_SZ_8, RAR_WND_SZ_10
+} errc_emac_rar_wnd_sz_enum;
+
+typedef enum
+{
+ CR_TIMER_8, CR_TIMER_16, CR_TIMER_24, CR_TIMER_32, CR_TIMER_40, CR_TIMER_48, CR_TIMER_56, CR_TIMER_64
+} errc_emac_cr_timer_enum;
+
+
+typedef enum
+{
+ MAX_HARQ_TX_1, MAX_HARQ_TX_2, MAX_HARQ_TX_3, MAX_HARQ_TX_4, MAX_HARQ_TX_5, MAX_HARQ_TX_6,
+ MAX_HARQ_TX_7, MAX_HARQ_TX_8, MAX_HARQ_TX_10, MAX_HARQ_TX_12, MAX_HARQ_TX_16, MAX_HARQ_TX_20,
+ MAX_HARQ_TX_24, MAX_HARQ_TX_28
+} errc_emac_max_harq_tx_enum;
+
+typedef enum
+{
+ PERIODIC_BSR_5, PERIODIC_BSR_10, PERIODIC_BSR_16, PERIODIC_BSR_20, PERIODIC_BSR_32,
+ PERIODIC_BSR_40, PERIODIC_BSR_64, PERIODIC_BSR_80, PERIODIC_BSR_128, PERIODIC_BSR_160,
+ PERIODIC_BSR_320, PERIODIC_BSR_640, PERIODIC_BSR_1280, PERIODIC_BSR_2560, PERIODIC_BSR_INF
+} errc_emac_periodic_bsr_timer_enum;
+
+typedef enum
+{
+ RETX_BSR_320, RETX_BSR_640, RETX_BSR_1280, RETX_BSR_2560, RETX_BSR_5120, RETX_BSR_10240
+} errc_emac_retx_bsr_timer_enum;
+
+typedef enum
+{
+ ON_DURATION_PS1, ON_DURATION_PS2, ON_DURATION_PS3, ON_DURATION_PS4, ON_DURATION_PS5, ON_DURATION_PS6,
+ ON_DURATION_PS8, ON_DURATION_PS10, ON_DURATION_PS20, ON_DURATION_PS30, ON_DURATION_PS40,
+ ON_DURATION_PS50, ON_DURATION_PS60, ON_DURATION_PS80, ON_DURATION_PS100, ON_DURATION_PS200,
+ ON_DURATION_PS300, ON_DURATION_PS400, ON_DURATION_PS500, ON_DURATION_PS600,
+ ON_DURATION_PS800, ON_DURATION_PS1000, ON_DURATION_PS1200, ON_DURATION_PS1600
+} errc_emac_on_duration_timer_enum;
+
+typedef enum
+{
+ DRX_INACTIVITY_PS1, DRX_INACTIVITY_PS2, DRX_INACTIVITY_PS3, DRX_INACTIVITY_PS4, DRX_INACTIVITY_PS5,
+ DRX_INACTIVITY_PS6, DRX_INACTIVITY_PS8, DRX_INACTIVITY_PS10, DRX_INACTIVITY_PS20, DRX_INACTIVITY_PS30,
+ DRX_INACTIVITY_PS40, DRX_INACTIVITY_PS50, DRX_INACTIVITY_PS60, DRX_INACTIVITY_PS80, DRX_INACTIVITY_PS100,
+ DRX_INACTIVITY_PS200, DRX_INACTIVITY_PS300, DRX_INACTIVITY_PS500, DRX_INACTIVITY_PS750, DRX_INACTIVITY_PS1280,
+ DRX_INACTIVITY_PS1920, DRX_INACTIVITY_PS2560, DRX_INACTIVITY_PS0
+} errc_emac_drx_inactivity_timer_enum;
+
+typedef enum
+{
+ DRX_RETX_TIMER_PS1, DRX_RETX_TIMER_PS2, DRX_RETX_TIMER_PS4, DRX_RETX_TIMER_PS6, DRX_RETX_TIMER_PS8,
+ DRX_RETX_TIMER_PS16, DRX_RETX_TIMER_PS24, DRX_RETX_TIMER_PS33, DRX_RETX_TIMER_PS0,
+ DRX_RETX_TIMER_PS40, DRX_RETX_TIMER_PS64, DRX_RETX_TIMER_PS80, DRX_RETX_TIMER_PS96,
+ DRX_RETX_TIMER_PS112, DRX_RETX_TIMER_PS128, DRX_RETX_TIMER_PS160, DRX_RETX_TIMER_PS320
+} errc_emac_drx_retx_timer_enum;
+
+typedef enum
+{
+ DRX_UL_RETX_TIMER_PS0, DRX_UL_RETX_TIMER_PS1, DRX_UL_RETX_TIMER_PS2, DRX_UL_RETX_TIMER_PS4, DRX_UL_RETX_TIMER_PS6, DRX_UL_RETX_TIMER_PS8,
+ DRX_UL_RETX_TIMER_PS16, DRX_UL_RETX_TIMER_PS24, DRX_UL_RETX_TIMER_PS33, DRX_UL_RETX_TIMER_PS40, DRX_UL_RETX_TIMER_PS64,
+ DRX_UL_RETX_TIMER_PS80, DRX_UL_RETX_TIMER_PS96, DRX_UL_RETX_TIMER_PS112, DRX_UL_RETX_TIMER_PS128, DRX_UL_RETX_TIMER_PS160, DRX_UL_RETX_TIMER_PS320
+} errc_emac_drx_ul_retx_timer_enum;
+
+typedef enum
+{
+ LONG_DRX_CYCLE_10, LONG_DRX_CYCLE_20, LONG_DRX_CYCLE_32, LONG_DRX_CYCLE_40, LONG_DRX_CYCLE_64,
+ LONG_DRX_CYCLE_80, LONG_DRX_CYCLE_128, LONG_DRX_CYCLE_160, LONG_DRX_CYCLE_256, LONG_DRX_CYCLE_320,
+ LONG_DRX_CYCLE_512, LONG_DRX_CYCLE_640, LONG_DRX_CYCLE_1024, LONG_DRX_CYCLE_1280, LONG_DRX_CYCLE_2048,
+ LONG_DRX_CYCLE_2560, LONG_DRX_CYCLE_60, LONG_DRX_CYCLE_70
+} errc_emac_long_drx_cycle_enum;
+
+typedef enum
+{
+ SHORT_DRX_CYCLE_2, SHORT_DRX_CYCLE_5, SHORT_DRX_CYCLE_8, SHORT_DRX_CYCLE_10, SHORT_DRX_CYCLE_16,
+ SHORT_DRX_CYCLE_20, SHORT_DRX_CYCLE_32, SHORT_DRX_CYCLE_40, SHORT_DRX_CYCLE_64, SHORT_DRX_CYCLE_80,
+ SHORT_DRX_CYCLE_128, SHORT_DRX_CYCLE_160, SHORT_DRX_CYCLE_256, SHORT_DRX_CYCLE_320, SHORT_DRX_CYCLE_512,
+ SHORT_DRX_CYCLE_640, SHORT_DRX_CYCLE_4
+} errc_emac_short_drx_cycle_enum;
+
+
+
+typedef enum
+{
+ PERIODIC_PHR_10, PERIODIC_PHR_20, PERIODIC_PHR_50, PERIODIC_PHR_100,
+ PERIODIC_PHR_200, PERIODIC_PHR_500, PERIODIC_PHR_1000, PERIODIC_PHR_INF
+} errc_emac_periodic_phr_timer_enum;
+
+typedef enum
+{
+ PROHIBIT_PHR_0, PROHIBIT_PHR_10, PROHIBIT_PHR_20, PROHIBIT_PHR_50,
+ PROHIBIT_PHR_100, PROHIBIT_PHR_200, PROHIBIT_PHR_500, PROHIBIT_PHR_1000
+} errc_emac_prohibit_phr_timer_enum;
+
+typedef enum
+{
+ DL_PATHLOSS_CHANGE_1, DL_PATHLOSS_CHANGE_3, DL_PATHLOSS_CHANGE_6, DL_PATHLOSS_CHANGE_INF
+} errc_emac_phr_dl_pathloss_change_enum;
+
+typedef enum
+{
+ BRQ_PROHIBIT_S0, BRQ_PROHIBIT_S0DOT4, BRQ_PROHIBIT_S0DOT8, BRQ_PROHIBIT_S1DOT6,
+ BRQ_PROHIBIT_S3, BRQ_PROHIBIT_S6, BRQ_PROHIBIT_S12, BRQ_PROHIBIT_S30
+} errc_emac_brq_prohibit_timer_enum;
+
+typedef enum
+{
+ ERRC_EMAC_TA_INFO_REQ_TYPE_STOP,
+ ERRC_EMAC_TA_INFO_REQ_TYPE_START
+} errc_emac_ta_info_req_type_enum;
+
+typedef enum
+{
+ EMAC_ERRC_RA_ERROR_ERRC_TRIGGER = 0,
+ EMAC_ERRC_RA_ERROR_NON_ERRC_TRIGGER = 0x01
+} emac_errc_ra_error_cause_enum;
+
+typedef enum
+{
+ ERRC_EMAC_HDATA_IND_INVALID = 0,
+ ERRC_EMAC_HDATA_IND_LOW,
+ ERRC_EMAC_HDATA_IND_HIGH
+} errc_emac_hdata_ind_enum;
+
+typedef enum
+{
+ EMAC_ERRC_L1_REL_CAUSE_TA = 0,
+ EMAC_ERRC_L1_REL_CAUSE_SR = 0x01,
+} emac_errc_ul_rel_cause_enum;
+
+typedef enum
+{
+ EMAC_ERRC_DRX_INC_GAP_REQ_TYPE_STOP,
+ EMAC_ERRC_DRX_INC_GAP_REQ_TYPE_START
+} errc_emac_drx_inc_gap_req_type_enum;
+
+typedef enum
+{
+ ERRC_EMAC_CCCH_CAUSE_CONN_REQ = 0,
+ ERRC_EMAC_CCCH_CAUSE_REEST_REQ = 0x01
+} errc_emac_ccch_cause_enum;
+
+typedef enum
+{
+ EMAC_SCELL_DEACTIVATION_TIMER_INFINITY, // defalut value
+ EMAC_SCELL_DEACTIVATION_TIMER_RF2,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF4,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF8,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF16,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF32,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF64,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF128
+}emac_scell_deactivation_timer_enum;
+
+typedef enum
+{
+ ERRC_EMAC_TTI_BUNDLING_DISABLED,
+ ERRC_EMAC_TTI_BUNDLING_NORMAL,
+ ERRC_EMAC_TTI_BUNDLING_ENHANCED_FDD
+} errc_emac_tti_bundling_mode_enum;
+
+#if defined(__XL1SIM_EL1__)
+// old struct for XL1Sim test case use
+typedef struct
+{
+ errc_emac_ra_pow_ramping_enum power_ramping_step;
+ errc_emac_preamble_init_pow_enum preamble_init_rec_target_power;
+ errc_emac_preamble_tx_max_enum preamble_trans_max;
+} errc_emac_ul_scell_params_struct;
+#endif
+
+typedef struct
+{
+ kal_uint8 scell_index;
+ errc_emac_ra_pow_ramping_enum power_ramping_step;
+ errc_emac_preamble_init_pow_enum preamble_init_rec_target_power;
+ errc_emac_preamble_tx_max_enum preamble_trans_max;
+} errc_emac_scell_ul_params_struct;
+
+typedef enum
+{
+ ERRC_EMAC_SCELL_NOT_CONFIGURED = 0,
+ ERRC_EMAC_SCELL_ALL_DEACTIVATED = 1,
+ ERRC_EMAC_1_SCELL_ACTIVATED = 2
+}errc_emac_ca_activate_state_enum;
+
+typedef struct
+{
+ errc_emac_ra_preamble_nb_enum ra_preamble_nb_index;
+ errc_emac_ra_pow_ramping_enum ra_pow_ramping_index;
+ errc_emac_preamble_init_pow_enum ra_preamble_init_pow_index;
+ errc_emac_preamble_tx_max_enum ra_preamble_tx_max_index;
+ errc_emac_rar_wnd_sz_enum ra_rar_wnd_sz_index;
+ errc_emac_cr_timer_enum ra_cr_timer_index;
+
+ kal_uint8 ra_msg3_tx_max;
+
+ kal_bool group_a_valid;
+ errc_emac_ra_group_a_sz_enum ra_group_a_sz_index;
+ errc_emac_ra_msg_sz_group_a_enum ra_msg_sz_group_a_index;
+ errc_emac_msg_pow_offset_group_b_enum ra_msg_pow_offset_group_b_index;
+ kal_bool ra_dedicated_valid;
+ kal_uint8 rapid;
+ kal_uint8 prach_mask;
+
+#if defined(__XL1SIM_EL1__)
+ // old struct for XL1Sim test case use
+ errc_emac_ul_scell_params_struct ul_scell_params;
+ kal_bool ul_scell_params_are_valid;
+#else
+ errc_emac_scell_ul_params_struct scell_params[ERRC_EMAC_MAX_SCELL_NB];
+ kal_uint8 valid_scell_param_num;
+#endif
+} emac_ra_config_info_struct;
+
+
+typedef struct
+{
+ errc_emac_max_harq_tx_enum max_harq_tx_index;
+ errc_emac_periodic_bsr_timer_enum periodic_bsr_timer_index;
+ errc_emac_retx_bsr_timer_enum retx_bsr_timer_index;
+ errc_emac_tti_bundling_mode_enum tti_bundling;
+
+ kal_bool extended_bsr_sizes;
+} emac_sched_config_info_struct;
+
+
+
+typedef struct
+{
+ errc_emac_on_duration_timer_enum on_duration_timer_index;
+ errc_emac_drx_inactivity_timer_enum drx_inactivity_timer_index;
+ errc_emac_drx_retx_timer_enum drx_retx_timer_index;
+ errc_emac_long_drx_cycle_enum long_drx_cycle_index;
+
+ kal_bool drx_ul_retx_timer_valid;
+ errc_emac_drx_ul_retx_timer_enum drx_ul_retx_timer_index;
+
+ kal_bool short_cycle_valid;
+ errc_emac_short_drx_cycle_enum short_drx_cycle_index;
+ kal_uint8 drx_short_cycle_timer;
+
+ kal_uint16 drx_start_offset;
+} emac_drx_config_info_struct;
+
+
+typedef struct
+{
+ errc_emac_periodic_phr_timer_enum periodic_phr_timer_index;
+ errc_emac_prohibit_phr_timer_enum prohibit_phr_timer_index;
+ errc_emac_phr_dl_pathloss_change_enum phr_dl_pathloss_change_index;
+
+ kal_bool extended_phr;
+//#ifdef __ENDC__
+ kal_bool dualconnectivity_phr;
+ kal_bool dualconnectivity_phrModeOtherCG; // KAL_TRUE: real, otherwise KAL_FALSE. only valid if dualconnectivity_phr is TRUE.
+//#endif /*__ENDC__*/
+} emac_phr_config_info_struct;
+
+
+typedef struct
+{
+ kal_bool sr_mask; //r9 sr mask
+ kal_uint8 lcid;
+ kal_uint8 rb_idx;
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+
+ ///RB direction
+ ///UL: 0x01 DL: 0x02 Bi-direction 0x03
+ ///EMAC_RB_UL_MASK 0x01
+ ///EMAC_RB_DL_MASK 0x02
+ kal_uint8 direction;
+ kal_uint8 lcg;
+ kal_uint8 ul_priority;
+ kal_bool logical_channel_sr_prohibit_timer_is_used;
+ kal_bool logical_channel_brq_prohibit_timer_index_is_valid;
+ errc_emac_brq_prohibit_timer_enum logical_channel_brq_prohibit_timer_index;
+} errc_emac_open_rb_struct;
+
+typedef struct
+{
+ kal_uint8 rb_idx;
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+ kal_uint8 direction;
+} errc_emac_close_rb_struct;
+
+// MSG_ID_ERRC_EMAC_MEAS_GAP_IND
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 gap_pattern; //0: gap=40, 1: gap=80
+ kal_uint8 offset; //0xFF: no gap
+
+#ifdef __EL2_ARCH_V2__
+ /**
+ * The parameter 'fr1-Gap-r15' in MeasConfig.
+ * Indicates whether the gap is only applicable for measurements on FR1.
+ * Should be set to FALSE when ENDC is not configured.*/
+ kal_bool fr1_gap;
+ /**
+ * The parameter 'mgta-r15' in MeasConfig.
+ * Indicates whether a timing advance value of 0.5ms is applicable to the measurement gap configuration provided by E-UTRAN.*/
+ kal_bool mgta;
+#endif /* __EL2_ARCH_V2__ */
+} errc_emac_meas_gap_ind_struct;
+
+#ifdef __EL2_ARCH_V2__
+// refer el1_ch_tdm_pattern_cfg_struct in el1_errc_struct.h
+typedef struct
+{
+ /** Indicates whether tdm-PatternConfig-r15 in RRCConnectionReconfiguration-v15x0-IEs is setup or not**/
+ /** UL/DL reference configuration indicating the time during which a UE configured with EN-DC is allowed to transmit. **/
+ kal_bool pattern_valid;
+
+ /** The following parameters are only valid when pattern_valid = KAL_TRUE **/
+ /** Corresponds to subframeAssignment-r15,
+ * Indicates UL/ DL subframe configuration where 0:Configuration 0, 1: Configuration 1 etc.
+ * value: 0..6
+ **/
+ kal_uint8 subframe_assign;
+
+ /** Corresponds to harq-Offset-r15,
+ * Indicates a HARQ subframe offset that is applied to the subframes designated as UL in the associated subrame assignment.
+ * value: 0..9
+ **/
+ kal_uint8 harq_offset;
+
+} emac_tdm_pattern_config_info_struct;
+#endif
+
+/* CHM MBMS support start */
+typedef enum
+{
+ ERRC_EMAC_CONFIG_TYPE_ALL = 0, // configure SCH only, or configure both SCH+MCH
+ ERRC_EMAC_CONFIG_TYPE_MCH_ONLY = 1 // configure MCH only
+} errc_emac_config_type_enum;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255
+
+ // numbered by eRRC and not from NW,
+ // If one carrier is supported, range 0~7
+ // If two carriers are supported, range 0~15
+ kal_uint8 mcch_idx;
+} errc_emac_open_mcch_struct;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255, currently for debug purpose only
+ kal_uint8 mcch_idx;
+} errc_emac_close_mcch_struct;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255
+ kal_uint8 pmch_id; // 0~15, numbered by eRRC and not from NW (directly use the index in asn)
+ kal_uint8 lcid; // 0~28
+ kal_uint8 mrb_idx; // numbered by eRRC, The range of mrb_idx depends on L2 HW capability
+} errc_emac_open_mrb_struct;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255, currently for debug purpose only
+ kal_uint8 pmch_id; // 0~15, currently for debug purpose only
+ kal_uint8 lcid; // 0~28, currently for debug purpose only
+ kal_uint8 mrb_idx; // numbered by eRRC, The range of mrb_idx depends on L2 HW capability
+} errc_emac_close_mrb_struct;
+
+/* CHM MBMS support end */
+
+typedef struct
+{
+ kal_uint8 stag_id;
+ errc_emac_ta_timer_enum s_tag_ta_timer;
+} errc_emac_stag_timer_info_struct;
+
+// MSG_ID_ERRC_EMAC_CONFIG_REQ
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_config_type_enum config_type; //configure either MCH only or all
+ errc_emac_config_cause_enum cause; //HO or RESET or not
+ errc_emac_ta_timer_enum ta_timer_index; //TA timer index
+ kal_uint8 sr_prohibit_timer; //SR prohibit timer index
+ kal_uint8 open_rb_nb; //number of open RB
+ kal_uint8 close_rb_nb; //number of close RB
+ errc_emac_open_rb_struct open_rb[ERRC_EMAC_MAX_RB_NB];
+ errc_emac_close_rb_struct close_rb[ERRC_EMAC_MAX_RB_NB];
+
+ errc_emac_icd_event_cause_enum icd_event_cause; //ICD MAC_RESET_EVENT and MAC_CONFIGURATION_EVENT
+
+ //EMAC_CONFIG_INFO_RA_MASK
+ //EMAC_CONFIG_INFO_SCHED_MASK
+ //EMAC_CONFIG_INFO_DRX_MASK
+ //EMAC_CONFIG_INFO_PHR_MASK
+ //EMAC_CONFIG_INFP_CRNTI_MASK
+ kal_uint8 info_bitmap;
+ emac_ra_config_info_struct ra_config_info;
+ emac_sched_config_info_struct schd_config_info;
+ emac_drx_config_info_struct drx_config_info;
+ emac_phr_config_info_struct phr_config_info;
+ kal_uint16 c_rnti; //new C-RNTI value
+ kal_bool dl_data_sus_flg;
+
+ emac_scell_deactivation_timer_enum scell_deactivation_timer;
+ kal_uint8 configured_scell_bitmap;
+ kal_bool simultaneous_pucch_pusch;
+ kal_bool pusch_enhancement_mode;
+
+/* CHM MBMS support start */
+ //kal_uint8 open_mcch_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //kal_uint8 close_mcch_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //errc_emac_open_mcch_struct open_mcch[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+ //errc_emac_close_mcch_struct close_mcch[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+
+ //kal_uint8 open_mrb_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //kal_uint8 close_mrb_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //errc_emac_open_mrb_struct open_mrb[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MRB_SUPPORT];
+ //errc_emac_close_mrb_struct close_mrb[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MRB_SUPPORT];
+/* CHM MBMS support end */
+
+ #if defined(__XL1SIM_EL1__)
+ // old struct for XL1Sim test case use
+ errc_emac_ta_timer_enum s_tag_ta_timer;
+ kal_bool s_tag_ta_timer_is_valid;
+ #else
+ kal_uint8 s_tag_ta_timer_valid_nb; //number of valid stag timer info nb
+ errc_emac_stag_timer_info_struct s_stag_ta_timer_info[ERRC_EMAC_MAX_STAG_NB];
+ #endif
+
+ kal_bool logical_channel_sr_prohibit_timer_is_valid;
+ kal_uint16 logical_channel_sr_prohibit_timer; /* Value in subframes */
+
+ errc_el2_cell_group_enum cell_group;
+#ifdef __EL2_ARCH_V2__
+ emac_tdm_pattern_config_info_struct tdm_pattern_info;
+#endif
+
+} errc_emac_config_req_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ emac_errc_ra_error_cause_enum cause;
+} errc_emac_ra_error_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_hdata_ind_enum ul_hdata;
+ errc_emac_hdata_ind_enum dl_hdata;
+} errc_emac_hdata_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 crnti;
+ kal_uint8 preamble_tx_nb;
+ kal_bool contention_ind;
+} errc_emac_contention_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 preamble_tx_nb;
+ kal_bool contention_ind;
+} errc_emac_ra_info_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 preamble_tx_nb;
+ kal_bool contention_ind;
+ kal_bool max_txpower_reached;
+} errc_emac_estfail_report_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ emac_errc_ul_rel_cause_enum cause;
+ kal_bool s_tag_is_valid;
+ kal_uint8 s_tag;
+} errc_emac_l1_ul_rel_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 ccch_size;
+ kal_uint8 ccch[6];
+ errc_emac_ccch_cause_enum cause;
+} errc_emac_ccch_data_req_struct;
+
+/* Need to remove for TK6291 U4G */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 paging_ctrl_info;
+ qbm_gpd* p_rgpd;
+ ABS_TICK_TIME proc_abs_time;
+ lte_cell_time proc_lte_time;
+} errc_emac_paging_ind_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 si_ctrl_info;
+ qbm_gpd* p_rgpd;
+ ABS_TICK_TIME proc_abs_time;
+ lte_cell_time proc_lte_time;
+
+ kal_uint8 carrier_info; //Carrier Index, only valid for 0 and 1
+} errc_emac_si_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ void* p_data; //93, start address of SRB data in VRB
+ kal_uint32 data_len; //93, length of SRB data in VRB
+
+} errc_emac_ccch_data_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_ta_info_req_type_enum req_type;
+} errc_emac_ta_info_req_struct;
+
+typedef struct
+{
+ kal_uint32 ta;
+ kal_uint8 s_tag_id;
+} errc_emac_s_tag_ta_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_valid;
+ kal_uint32 ta;
+ kal_bool s_tag_ta_is_valid;
+ errc_emac_s_tag_ta_struct s_tag_ta;
+} errc_emac_ta_info_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 ta;
+ kal_uint8 tag_id;
+} errc_emac_ta_info_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tag_id;
+} errc_emac_ta_info_invalid_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_drx_inc_gap_req_type_enum req_type;
+ kal_uint32 max_interval;
+} errc_emac_drx_inc_gap_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 scell_activate_bmp_dl;
+ kal_uint8 scell_activate_bmp_ul;
+} errc_emac_ca_activate_ind_struct;
+
+
+typedef enum
+{
+ ERRC_EMAC_SUPPORT_REL_R9,
+ ERRC_EMAC_SUPPORT_REL_R10,
+ ERRC_EMAC_SUPPORT_REL_R11,
+ ERRC_EMAC_SUPPORT_REL_R12,
+ ERRC_EMAC_SUPPORT_REL_R13,
+ ERRC_EMAC_SUPPORT_REL_R14,
+ ERRC_EMAC_SUPPORT_REL_R15,
+ ERRC_EMAC_SUPPORT_REL_INVALID
+} errc_emac_support_release_enum;
+
+
+typedef enum
+{
+ ERRC_EMAC_DL_QAM_64 = 0,
+ ERRC_EMAC_DL_QAM_256 = 1,
+ ERRC_EMAC_DL_QAM_NUM = 2,
+ ERRC_EMAC_DL_QAM_INVALID
+} errc_emac_dl_modulation_enum;
+
+
+typedef enum
+{
+ ERRC_EMAC_UL_QAM_16 = 0,
+ ERRC_EMAC_UL_QAM_64 = 1,
+ ERRC_EMAC_UL_QAM_256 = 2,
+ ERRC_EMAC_UL_QAM_NUM = 3,
+ ERRC_EMAC_UL_QAM_INVALID
+} errc_emac_ul_modulation_enum;
+
+typedef enum
+{
+ ERRC_EMAC_DL_CAT_1 = 0,
+ ERRC_EMAC_DL_CAT_2 = 1,
+ ERRC_EMAC_DL_CAT_3 = 2,
+ ERRC_EMAC_DL_CAT_4 = 3,
+ ERRC_EMAC_DL_CAT_5 = 4,
+ ERRC_EMAC_DL_CAT_6 = 5,
+ ERRC_EMAC_DL_CAT_7 = 6,
+ ERRC_EMAC_DL_CAT_8 = 7,
+ ERRC_EMAC_DL_CAT_9 = 8,
+ ERRC_EMAC_DL_CAT_10 = 9,
+ ERRC_EMAC_DL_CAT_11 = 10,
+ ERRC_EMAC_DL_CAT_12 = 11,
+ ERRC_EMAC_DL_CAT_13 = 12,
+ ERRC_EMAC_DL_CAT_14 = 13,
+ ERRC_EMAC_DL_CAT_15 = 14,
+ ERRC_EMAC_DL_CAT_16 = 15,
+ ERRC_EMAC_DL_CAT_17 = 16,
+ ERRC_EMAC_DL_CAT_18 = 17,
+ ERRC_EMAC_DL_CAT_19 = 18,
+ ERRC_EMAC_DL_CAT_20 = 19,
+ ERRC_EMAC_DL_CAT_21 = 20,
+ ERRC_EMAC_DL_CAT_NUM = 20,
+ ERRC_EMAC_DL_CAT_INVALID
+} errc_emac_dl_category_enum;
+
+typedef enum
+{
+ ERRC_EMAC_UL_CAT_1 = 0,
+ ERRC_EMAC_UL_CAT_2 = 1,
+ ERRC_EMAC_UL_CAT_3 = 2,
+ ERRC_EMAC_UL_CAT_4 = 3,
+ ERRC_EMAC_UL_CAT_5 = 4,
+ ERRC_EMAC_UL_CAT_6 = 5,
+ ERRC_EMAC_UL_CAT_7 = 6,
+ ERRC_EMAC_UL_CAT_8 = 7,
+ ERRC_EMAC_UL_CAT_9 = 8,
+ ERRC_EMAC_UL_CAT_10 = 9,
+ ERRC_EMAC_UL_CAT_11 = 10,
+ ERRC_EMAC_UL_CAT_12 = 11,
+ ERRC_EMAC_UL_CAT_13 = 12,
+ ERRC_EMAC_UL_CAT_14 = 13,
+ ERRC_EMAC_UL_CAT_15 = 14,
+ ERRC_EMAC_UL_CAT_16 = 15,
+ ERRC_EMAC_UL_CAT_17 = 16,
+ ERRC_EMAC_UL_CAT_18 = 17,
+ ERRC_EMAC_UL_CAT_19 = 18,
+ ERRC_EMAC_UL_CAT_20 = 19,
+ ERRC_EMAC_UL_CAT_21 = 20,
+ ERRC_EMAC_UL_CAT_NUM = 20,
+ ERRC_EMAC_UL_CAT_INVALID
+} errc_emac_ul_category_enum;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ // Support Release
+ errc_emac_support_release_enum support_release;
+
+ // Capability
+
+ errc_emac_dl_category_enum dl_category;
+ errc_emac_ul_category_enum ul_category;
+ errc_emac_dl_modulation_enum highest_dl_modulation;
+ errc_emac_ul_modulation_enum highest_ul_modulation;
+
+
+ // Features
+ kal_bool recommendBitRate_enable;
+
+} errc_emac_support_capability_ind_struct;
+
+
+#endif /*ERRC_EMAC_INTERFACE_H*/
diff --git a/mcu/protocol/interface/enl2/el2/errc_emacmch_msg.h b/mcu/protocol/interface/enl2/el2/errc_emacmch_msg.h
new file mode 100644
index 0000000..0649064
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/errc_emacmch_msg.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * errc_emacmch_msg.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Define ERRC EMACMCH interface enums, structures and constants
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+
+#ifndef ERRC_EMACMCH_MSG_H
+#define ERRC_EMACMCH_MSG_H
+
+#include "kal_public_api.h"
+#include "el2_sap_common.h"
+#include "common_def.h"
+#include "el1_enum.h"
+
+typedef struct {
+ kal_uint8 num; //fdd: 1-6, tdd: 1-5
+ kal_uint8 sf[MAX_SF_IN_ONE_RF]; //fdd: 123678, tdd: 34789
+}sf_alloc_map_t;
+
+typedef struct {
+ kal_uint8 rf_alloc_period; /*1, 2, 4, 8, 16, 32 */
+ kal_uint8 rf_alloc_offset; /* 0.. 7*/ // TODO: if offset > period?
+ kal_bool is_one_frame_alloc;
+ sf_alloc_map_t sf_alloc_map[4];
+}sf_config_t;
+
+typedef struct {
+ kal_uint8 num_sf_config; /* 0...8 */
+ sf_config_t sf_config_list[MAX_MBSFN_ALLOCATIONS];
+}mbsfn_sf_config_list_t;
+
+// SYNCAREA_CFG
+typedef struct {
+ kal_uint8 mbsfn_area_id; // 0-255
+ kal_uint8 non_mbsfn_region_len; // 1-2
+ kal_uint8 signalMCS; // 2,7,13,19
+ kal_uint8 offset; // 0-10
+ kal_uint16 repetition_period; // 32, 64, 128, 256
+ kal_uint16 modification_period; // 512, 1024
+ sf_alloc_map_t sf_alloc_info;
+ el1_ch_mch_mcch_reception_mode_enum recv_mode; // EVY_RP, EVY_MP, CNG_DTT
+}mcch_config_t;
+
+typedef struct
+{
+ //kal_uint8 syncarea_id;
+ kal_uint8 mcch_cfg_num; // 0-8
+ mcch_config_t mcch_cfg[MAX_AREA_NUM_PER_CELL];
+ mbsfn_sf_config_list_t sib2_sf_config_list;
+
+} errc_emacmch_syncarea_cfg_t;
+
+// AREA_CFG
+typedef struct {
+ kal_uint8 pmch_id;
+ kal_bool is_cfg_pmch_info_list_ext; //MT6293
+ kal_bool is_higher_order_data_mcs; //MT6293
+ kal_uint8 dataMCS; /* 0 ..28*/
+ kal_uint8 session_num_in_pmch; //MT6293
+ kal_uint16 sf_alloc_start;
+ kal_uint16 sf_alloc_end;
+ kal_uint16 mch_sched_period; /* 8, 16, 32, 64, 128, 256, 512, 1024 */
+
+}pmch_info_t;
+
+typedef struct {
+ kal_uint8 mbsfn_area_id; /* 0 .. 255 */
+ kal_uint16 common_sf_alloc_period; /* 4, 8, 16, 32, 64, 128, 256 */
+
+ kal_uint8 num_sf_config;
+ sf_config_t sf_config_list[MAX_MBSFN_ALLOCATIONS];
+
+ kal_uint8 num_pmch_info; /* 0 represent all PMCH close */
+ pmch_info_t pmch_info_list[MAX_PMCH_PER_MBSFN];
+
+}mbsfn_area_config_t;
+
+typedef struct
+{
+ //kal_uint8 syncarea_id;
+ kal_uint8 area_cfg_num;
+ mbsfn_area_config_t area_cfg[MAX_AREA_NUM_PER_CELL];
+
+} errc_emacmch_syncarea_area_cfg_t;
+
+// MXCH_CFG
+typedef struct
+{
+ kal_uint8 area_id; // 0~255
+ kal_uint8 mcch_idx; // numbered by ERRC
+
+} errc_emacmch_establish_mcch_t;
+
+typedef struct
+{
+ kal_uint8 area_id; // 0~255, currently for debug purpose only
+ kal_uint8 mcch_idx; // numbered by ERRC
+
+} errc_emacmch_release_mcch_t;
+
+typedef struct
+{
+ kal_uint8 area_id; // 0~255
+ kal_uint8 pmch_id; // 0~15, numbered by ERRC (directly use the index in asn ie) = pmch_ie_idx
+ kal_uint8 lcid; // 0~28
+ kal_uint8 mtch_idx; // numbered by ERRC, The range of mrb_idx depends on L2 HW capability
+ kal_uint8 tmgi[6]; // tmgi info to identify MBMS session, required by VZW EM
+
+} errc_emacmch_establish_mtch_t;
+
+typedef struct
+{
+ kal_uint8 area_id; // 0~255, currently for debug purpose only
+ kal_uint8 pmch_id; // 0~15, currently for debug purpose only
+ kal_uint8 lcid; // 0~28, currently for debug purpose only
+ kal_uint8 mtch_idx; // numbered by ERRC, The range of mrb_idx depends on L2 HW capability
+ kal_uint8 tmgi[6]; // tmgi info to identify MBMS session, required by VZW EM
+
+} errc_emacmch_release_mtch_t;
+
+typedef struct
+{
+ //kal_uint8 syncarea_id;
+ kal_uint8 release_mcch_num;
+ errc_emacmch_release_mcch_t release_mcch[MAX_EMBMS_MCCH_SUPPORT];
+
+ kal_uint8 establish_mcch_num;
+ errc_emacmch_establish_mcch_t establish_mcch[MAX_EMBMS_MCCH_SUPPORT];
+
+ kal_uint8 release_mtch_num;
+ errc_emacmch_release_mtch_t release_mtch[MAX_EMBMS_MTCH_SUPPORT];
+
+ kal_uint8 establish_mtch_num;
+ errc_emacmch_establish_mtch_t establish_mtch[MAX_EMBMS_MTCH_SUPPORT];
+
+} errc_emacmch_syncarea_mxch_cfg_t;
+
+// MCCH_RCV_MODE_CHANGE
+typedef struct
+{
+ kal_uint8 mbsfn_area_id;
+ el1_ch_mch_mcch_reception_mode_enum recv_mode;
+
+}mcch_rept_mode_config_t;
+
+typedef struct
+{
+ //kal_uint8 syncarea_id;
+ kal_uint8 mcch_rcv_mode_change_num;
+ mcch_rept_mode_config_t mcch_rcv_mode_change[MAX_AREA_NUM_PER_CELL];
+
+} errc_emacmch_syncarea_mcch_rcv_mode_change_t;
+
+// MTCH_SUSPEND_IND
+typedef struct
+{
+ kal_uint8 lcid; // 0~28
+ kal_uint8 mtch_idx; // numbered by ERRC, The range of mrb_idx depends on L2 HW capability
+
+} errc_emacmch_mtch_t;
+
+
+/****************************************************************************
+ * ERRC -> EMACMCH
+ ****************************************************************************/
+
+// MSG_ID_ERRC_EMACMCH_SYNCAREA_CFG_REQ
+typedef struct
+{
+
+ LOCAL_PARA_HDR
+ kal_uint32 tid; // 0x00000000 - 0x7FFFFFFF
+ kal_bool syncarea_cfg_valid[MAX_EMBMS_FREQ_SUPPORT];
+ errc_emacmch_syncarea_cfg_t syncarea_cfg[MAX_EMBMS_FREQ_SUPPORT];
+
+} errc_emacmch_syncarea_cfg_req_struct;
+
+// MSG_ID_ERRC_EMACMCH_AREA_CFG_REQ
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 tid; // 0x00000000 - 0x7FFFFFFF
+ kal_bool syncarea_area_cfg_valid[MAX_EMBMS_FREQ_SUPPORT];
+ errc_emacmch_syncarea_area_cfg_t syncarea_area_cfg[MAX_EMBMS_FREQ_SUPPORT];
+
+} errc_emacmch_area_cfg_req_struct;
+
+// MSG_ID_ERRC_EMACMCH_MXCH_CFG_REQ
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emacmch_syncarea_mxch_cfg_t syncarea_mxch_cfg[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+
+} errc_emacmch_mxch_cfg_req_struct;
+
+
+/* MSG_ID_ERRC_EMACMCH_MCCH_RCV_MODE_CHANGE_REQ */
+// Possible modes that could be changed by ERRC includes:
+// EL1_RECV_EVERY_REPETITION_PERIOD = 0,
+// EL1_RECV_EVERY_MODIFICATION_PERIOD = 1,
+// EL1_RECV_CHANGE_DETECTION = 2,
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 tid; // 0x00000000 - 0x7FFFFFFF
+ kal_bool syncarea_mcch_rcv_mode_change_valid[MAX_EMBMS_FREQ_SUPPORT];
+ errc_emacmch_syncarea_mcch_rcv_mode_change_t syncarea_mcch_rcv_mode_change[MAX_EMBMS_FREQ_SUPPORT];
+
+} errc_emacmch_mcch_rcv_mode_change_req_struct;
+
+
+/****************************************************************************
+ * EMACMCH -> ERRC
+ ****************************************************************************/
+
+
+// MSG_ID_ERRC_EMACMCH_MTCH_SUSPEND_IND
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 syncarea_id; // 0:PCELL 1:SCELL
+ kal_uint8 area_id; // 0~255
+ kal_uint8 pmch_id; // 0~15
+ kal_uint8 suspend_mtch_num;
+ errc_emacmch_mtch_t suspend_mtch[MAX_MTCH_NUM_PER_PMCH_29];
+
+} errc_emacmch_mtch_suspend_ind_struct;
+
+
+#endif /*ERRC_EMACMCH_MSG_H*/
diff --git a/mcu/protocol/interface/enl2/el2/errc_epdcp_msg.h b/mcu/protocol/interface/enl2/el2/errc_epdcp_msg.h
new file mode 100644
index 0000000..1f2cacc
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/errc_epdcp_msg.h
@@ -0,0 +1,553 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * errc_epdcp_msg.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * eRRC-ePDCP SAP message structure definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 17 2018 mingtsung.sun
+ * [MOLY00372769] [VMOLY] enable ENL2 on Gen95 HW platform
+ * ENL2 migration - MPD (errc_emac_msg.h move to MAC CL)
+ *
+ * 08 17 2018 yk.liu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * merge EMOLY CLs to VMOLY
+ *
+ * 06 01 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * RRC-ENPDCP Gemini VC interface naming change
+ *
+ * 05 30 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * RRC-ENPDCP Gemini VC interface naming change - fix
+ *
+ * 05 30 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * RRC-ENPDCP Gemini VC interface naming change
+ *
+ * 05 28 2018 shihyu.wang
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in protocol interface patchback
+ *
+ * 03 28 2018 shin.chen
+ * [MOLY00316692] [6297] Interface build-up for ERRC-NRRC, ERRC/NRRC-ENL2, ERRC-EL2 SAP
+ * update el2 interfaces.
+ *
+ * 02 06 2018 yi-shing.liou
+ * [MOLY00299866] [UMOLYE][ERRC/El2][R13]FeMDT UL PDCP delay measurement report
+ * [EPDCP] PDCP queuing delay (EMDT), common part.
+ *
+ * 10 31 2017 mazi.yu
+ * [MOLY00286412] [MT6293] Change EPDCP ERRC RB add/mod interface
+ * Change epdcp_rb_addmod_struct interface and support new qci value
+ *
+ * 09 18 2017 timothy.yao
+ * [MOLY00274939] patch back bugfix of RoHC-TCP IOT
+ * for UL-ROHC:
+ * 1) RoHC TCP bugfix patch
+ * 2) UL-ROHC interface
+ *
+ * 07 13 2017 steve.kao
+ * [MOLY00264004] [6293] EPDCP R-SIM code changes and UT with bugfixes
+ *
+ * [UMOLYA][TRUNK] EPDCP changes for L+L, R-SIM, UT, and bugfixes.
+ *
+ * 02 10 2017 steve.kao
+ * [MOLY00228972] [UMOLYA][EPDCP][R-SIM] Interface with ERRC for Remote SIM
+ * [EPDCP][R-SIM] Interface with ERRC for Remote SIM.
+ *
+ * 11 15 2016 cammie.yang
+ * [MOLY00211938] [UMOLYA][EM][AT&T] EUTRA air message
+ * [TRUNK][EPDCP]
+ * 1. Modification of ERRC-EPDCP interface for change of RRC buffer type (non-cachable AFM will be used)
+ * 2. Add handling for NULL Alogrithm in EPDCP UL
+ *
+ * 11 10 2016 steve.kao
+ * [MOLY00195563] [6293][EL2][UPCM][RATDM][EPDCP] Initial feature integrations
+ * [UMOLYA_TRUNK][EPDCP] Fix MCCH delivery interface.
+ *
+ * 09 26 2016 cammie.yang
+ * [MOLY00195563] [6293][EL2][UPCM][RATDM][EPDCP] Initial feature integrations
+ * [TRUNK] UPCM/RATDM/EPDCP feature integrations from PS.DEV
+ *
+ * 01 21 2016 mingtsung.sun
+ * [MOLY00160421] [MT6292] ePDCP CE RAM Optimization
+ * [EPDCP] CE RAM OPT
+ *
+ * 01 04 2016 tero.miettinen
+ * [MOLY00155820] ERRC UMOLY updates
+ * NVRAM IF, ERRC - EL2 IF and ERRC update for 15 bit RLC LI field length.
+ *
+ * 06 03 2015 mingtsung.sun
+ * [MOLY00118161] [MT6291] EPDCP CR Sync - Early reestablishment to prevent certain kind of VoLTE call drop
+ * LTE domain
+ *
+ * 02 05 2015 cooper.lin
+ * [MOLY00090532] [MT6291] Change Feature Check-in
+ * Code sync from MOLY (W15.06)
+ * 1. Not check in C2K related code because 91 C2K is under implementation and not checked in yet
+ * 2. Not check in VSIM related code, need to further discuss
+ * 3. Comment some DETECTION_TIMER related code, will confirm soon and patch it
+ *
+ * 11 12 2014 chi-chung.lin
+ * [MOLY00068710] [MT6291_DEV] Sync MOLY to MT6291_DEV
+ * [CHM] code sync from MT6291_DEV to UMOLY
+ *
+ * 11 11 2014 andrew.wu
+ * [MOLY00084096] [UMOLY]MT6291_DEV sync to UMOLY TRUNK
+ * MT6291_DEV sync to UMOLY
+ *
+ * 02 25 2013 timothy.yao
+ * [MOLY00007127] [MT7208] EL2 enhancement in MOLY
+ * [merged from L1SL2S-IT CBr]
+ * 1. modify the MACROs checking SIT index in ePDCP.
+ * 2. [bugfix] update BD chksum after removing PDCP header.
+ * 3. [bugfix] fix assert when deactivating loopback test mode
+ * -> also fix UT cases.
+ * 4. [bugfix] cache flush for the scaled data
+ * 5. [modify] patch the random method in freerun.
+ * 6. [modify] set the padding enums as 0x7fffffff for cgen.
+ ****************************************************************************/
+
+/*
+* mtk02353, 2011/07/28
+*
+* eRRC-ePDCP SAP message structure definition
+*
+* - the file only defines the message structure.
+* - naming rule : similar to message id
+* (a) exclude the prefix "MSG_ID_"
+* (b) add the postfix "_struct"
+* - message id is defined in epdcp_sap.h
+* MSG_ID_ERRC_EPDCP_DCCH_DATA_REQ,
+* MSG_ID_ERRC_EPDCP_DCCH_DATA_CNF,
+* MSG_ID_ERRC_EPDCP_DCCH_DATA_IND,
+* MSG_ID_ERRC_EPDCP_DCCH_DATA_RES,
+* MSG_ID_ERRC_EPDCP_TEST_REQ,
+* MSG_ID_ERRC_EPDCP_TEST_CNF,
+* MSG_ID_ERRC_EPDCP_CONFIG_REQ,
+* MSG_ID_ERRC_EPDCP_CONFIG_CNF,
+* MSG_ID_ERRC_EPDCP_CNTINFO_REQ,
+* MSG_ID_ERRC_EPDCP_CNTINFO_CNF,
+* MSG_ID_ERRC_EPDCP_EXCESS_DELAY_IND
+*
+* history:
+* 2011/11/16 - timothy
+* seperate the configuration array of CONFIG_REQ into 2 arrays,
+* one is for add_and_modify, and the other is for deletion.
+*/
+#ifndef _LTE_ERRC_EPDCP_SAP_STRUCT_DEF_H_
+#define _LTE_ERRC_EPDCP_SAP_STRUCT_DEF_H_
+
+#include "kal_public_api.h"
+
+#include "qmu_bm.h"
+#include "el2_sap_common.h"
+#include "common_def.h"
+
+#ifdef __EL2_ARCH_V2__
+#include "rrc_enpdcp_msg.h"
+#endif /* __EL2_ARCH_V2__ */
+
+/*****************************************************************************
+* constants
+*****************************************************************************/
+#define EPDCP_SAP_MAX_NUM_QUEUING_DELAY_RSLT (6)
+#define EPDCP_SAP_MAX_NUM_DRB (8)
+
+/*****************************************************************************
+* message structure
+*****************************************************************************/
+typedef enum
+{
+ EPDCP_SAP_INTCHK_OK = 0,
+ EPDCP_SAP_INTCHK_FAILURE, //integrity check failure
+ EPDCP_SAP_INTCHK_SKIPPED, //integrity check is not applied
+
+ EPDCP_SAP_INTCHK_PAD = 0x7fffffff
+} epdcp_intchk_result_enum;
+
+typedef enum
+{
+ EPDCP_SAP_DRB_TYPE_LTE = 0,
+ EPDCP_SAP_DRB_TYPE_LWA
+} epdcp_drb_type_enum;
+
+typedef enum
+{
+ EPDCP_SAP_STUS_PDU_ON_POLL_TYPE_1 = 0,
+ EPDCP_SAP_STUS_PDU_ON_POLL_TYPE_2
+} epdcp_stus_rpt_type_on_poll_enum;
+
+typedef enum
+{
+ EPDCP_SAP_MEASUREMENT_OFF = 0,
+ EPDCP_SAP_MEASUREMENT_ON,
+ EPDCP_SAP_MEASUREMENT_MODIFY
+} epdcp_delay_measurement_enum;
+
+
+typedef enum
+{
+ EPDCP_SAP_DELAY_THRESH_MS_30 = 0,
+ EPDCP_SAP_DELAY_THRESH_MS_40,
+ EPDCP_SAP_DELAY_THRESH_MS_50,
+ EPDCP_SAP_DELAY_THRESH_MS_60,
+ EPDCP_SAP_DELAY_THRESH_MS_70,
+ EPDCP_SAP_DELAY_THRESH_MS_80,
+ EPDCP_SAP_DELAY_THRESH_MS_90,
+ EPDCP_SAP_DELAY_THRESH_MS_100,
+ EPDCP_SAP_DELAY_THRESH_MS_150,
+ EPDCP_SAP_DELAY_THRESH_MS_300,
+ EPDCP_SAP_DELAY_THRESH_MS_500,
+ EPDCP_SAP_DELAY_THRESH_MS_750,
+ EPDCP_SAP_DELAY_THRESH_MS_PAD = 0x7fffffff
+} epdcp_delay_thresh_enum;
+
+
+typedef enum
+{
+ EPDCP_SAP_DELAY_RPT_INTV_MS_1024 = 0,
+ EPDCP_SAP_DELAY_RPT_INTV_MS_2048,
+ EPDCP_SAP_DELAY_RPT_INTV_MS_5120,
+ EPDCP_SAP_DELAY_RPT_INTV_MS_10240,
+ EPDCP_SAP_DELAY_RPT_INTV_PAD = 0x7fffffff
+} epdcp_delay_rpt_intv_enum;
+
+/* queuing delay result structure */
+typedef struct
+{
+ kal_uint8 qci;
+ kal_uint32 excess_delay_num;
+ kal_uint32 total_num;
+} epdcp_delay_result_struct;
+
+
+/* PDCP queuing delay config structure */
+typedef struct{
+ kal_bool valid;
+ epdcp_delay_measurement_enum measurement_status; // if valid=false, delay_theshold and delay_report_interval should be ignored
+ epdcp_delay_thresh_enum threshold;
+ epdcp_delay_rpt_intv_enum report_interval;
+} epdcp_delay_cfg_struct;
+
+/*
+ * MSG_ID_ERRC_EPDCP_EXCESS_DELAY_IND
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 list_num;
+ epdcp_delay_result_struct result_list[EPDCP_SAP_MAX_NUM_QUEUING_DELAY_RSLT];
+ epdcp_delay_thresh_enum threshold;
+ epdcp_delay_rpt_intv_enum report_interval;
+} errc_epdcp_excess_delay_ind_struct;
+
+/*
+* MSG_ID_ERRC_EPDCP_DCCH_DATA_REQ
+*
+* note: read peer_buffer_pointer to get tgpd pointer.
+*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rb_id;
+ kal_uint8 rb_idx;
+ kal_uint16 trans_id;
+ kal_uint16 flag_bmp;
+
+ void *p_addr;
+ kal_uint32 data_len;
+
+ // this is used during buffer release
+ KAL_AFM_ID afm_id;
+
+} errc_epdcp_dcch_data_req_struct;
+
+/*
+* MSG_ID_ERRC_EPDCP_DCCH_DATA_IND,
+*
+* note: read peer_buffer_pointer to get rgpd pointer
+*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rb_id;
+ kal_uint8 rb_idx;
+ kal_uint16 pad02;
+ epdcp_intchk_result_enum result;
+ kal_uint32 pdcp_count; // XXX: not needed if DL security is activated?
+ void *p_data;
+ kal_uint32 data_len; // including RRC message & MAC-I
+
+ qbm_gpd *p_rgpd; //TODO: to be removed
+} errc_epdcp_dcch_data_ind_struct;
+
+
+/* command for RB */
+typedef enum
+{
+ EPDCP_SAP_RB_CMD_ESTABLISH = 0,
+ EPDCP_SAP_RB_CMD_EST_N_SUSP,
+ EPDCP_SAP_RB_CMD_SUSPEND,
+ EPDCP_SAP_RB_CMD_RECONFIG,
+ EPDCP_SAP_RB_CMD_HO_IND,
+ EPDCP_SAP_RB_CMD_RESUME,
+ EPDCP_SAP_RB_CMD_RELEASE,
+ EPDCP_SAP_RB_CMD_RELEASE_FROM_LTE, //inter-RAT (from LTE)
+
+ EPDCP_SAP_RB_CMD_NUM,
+ EPDCP_SAP_RB_CMD_PAD = 0x7fffffff
+} epdcp_rb_cmd_enum;
+
+/* discard timer enum */
+typedef enum
+{
+ EPDCP_SAP_DISC_TMR_MS_50 = 0,
+ EPDCP_SAP_DISC_TMR_MS_100,
+ EPDCP_SAP_DISC_TMR_MS_150,
+ EPDCP_SAP_DISC_TMR_MS_300,
+ EPDCP_SAP_DISC_TMR_MS_500,
+ EPDCP_SAP_DISC_TMR_MS_750,
+ EPDCP_SAP_DISC_TMR_MS_1500,
+ EPDCP_SAP_DISC_TMR_MS_INFINITY,
+
+ EPDCP_SAP_DISC_TMR_MS_PAD = 0x7fffffff
+} epdcp_disc_tmr_enum;
+
+typedef enum
+{
+ EPDCP_SAP_ROHC_EN_DISABLED = 0,
+ EPDCP_SAP_ROHC_EN_ENABLED_BIDIR,
+ EPDCP_SAP_ROHC_EN_ENABLED_UL_ONLY
+} epdcp_rohc_en_enum;
+
+typedef struct
+{
+ /* polling param */
+ kal_bool type_on_poll_valid;
+ epdcp_stus_rpt_type_on_poll_enum type_on_poll;
+
+ /* periodic param */
+ kal_bool type1_periodicity_valid;
+ kal_bool type2_periodicity_valid;
+ kal_bool offset_valid;
+ kal_bool type1_periodicity_recfg;
+ kal_bool type2_periodicity_recfg;
+ kal_uint32 type1_periodicity;
+ kal_uint32 type2_periodicity;
+ kal_uint32 offset;
+} epdcp_stus_rpt_param_struct;
+
+
+typedef struct
+{
+ epdcp_drb_type_enum drb_type;
+ kal_uint8 flag_rlc_um;
+ kal_uint8 flag_um_long_sn; // UM only
+ kal_uint8 bmp_um_dir; // UM only : bit#0:UL, bit#1:DL
+
+
+ kal_uint8 flag_am_stus_rpt; // AM only
+ kal_uint8 flag_am_long_sn; // AM only
+ kal_bool flag_am_rlc_li_field_15_bit; // AM only
+ kal_uint8 pad1;
+
+ epdcp_rohc_en_enum rohc_enabled;
+ kal_uint16 rohc_max_cid;
+ kal_uint8 rohc_profs[9];
+
+ kal_bool reorder_tmr_is_valid;
+ kal_uint32 reorder_tmr;
+ epdcp_disc_tmr_enum disc_tmr; // spec-enum
+
+ epdcp_stus_rpt_param_struct stus_rpt_param;
+} epdcp_drb_attr_struct;
+
+
+/* RB addition/modification config structure */
+typedef struct
+{
+ kal_uint8 rb_idx; //primary index
+ kal_uint8 rb_id;
+ kal_uint8 eps_br_id;
+ kal_uint8 qci;
+ kal_bool is_gbr_bearer;
+
+ epdcp_rb_cmd_enum cmd;
+ epdcp_drb_attr_struct drb_attr;
+} epdcp_rb_addmod_struct;
+
+
+/* RB deletion config */
+typedef struct
+{
+ kal_uint8 rb_idx;
+ kal_uint8 rb_id;
+ kal_uint8 ho_failure; //if failure, remove the new RB.
+ kal_uint8 pad;
+
+ epdcp_rb_cmd_enum cmd;
+} epdcp_rb_del_struct;
+
+/* integrity algorithm enum */
+typedef enum
+{
+ EPDCP_SAP_INT_ALG_EIA0 = 0,
+ EPDCP_SAP_INT_ALG_EIA1,
+ EPDCP_SAP_INT_ALG_EIA2,
+ EPDCP_SAP_INT_ALG_EIA3, // ZUC algorithm
+
+ EPDCP_SAP_INT_ALG_NUM,
+ EPDCP_SAP_INT_ALG_PAD = 0x7fffffff
+} epdcp_int_alg_enum;
+
+
+/* cipher algorithm enum */
+typedef enum
+{
+ EPDCP_SAP_CIP_ALG_EEA0 = 0,
+ EPDCP_SAP_CIP_ALG_EEA1, // SNOW 3G
+ EPDCP_SAP_CIP_ALG_EEA2, // AES-based
+ EPDCP_SAP_CIP_ALG_EEA3, // ZUC algorithm
+
+ EPDCP_SAP_CIP_ALG_NUM,
+ EPDCP_SAP_CIP_ALG_PAD = 0x7fffffff
+} epdcp_cip_alg_enum;
+
+
+/* PDCP security config structure */
+typedef struct
+{
+ kal_uint8 valid;
+ kal_uint8 cip_key_up_idx;
+ kal_uint8 cip_key_cp_idx;
+ kal_uint8 int_key_idx;
+ epdcp_int_alg_enum int_alg; //integrity algorithm
+ epdcp_cip_alg_enum cip_alg; //cipher algorithm
+} epdcp_sec_cfg_struct;
+
+
+//MSG_ID_ERRC_EPDCP_CONFIG_REQ,
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 add_num;
+ kal_uint8 mod_num;
+ kal_uint8 del_num;
+ kal_bool drb_continue_rohc;
+
+ epdcp_rb_addmod_struct rb_add[10];
+ epdcp_rb_addmod_struct rb_mod[10];
+ epdcp_rb_del_struct rb_del[10];
+
+ epdcp_sec_cfg_struct sec_cfg;
+ epdcp_delay_cfg_struct delay_cfg;
+
+ //for eMBMS related
+ kal_uint8 mcch_add_num[2];
+ kal_uint8 mcch_del_num[2];
+ epdcp_mcch_add_struct mcch_add[2][8];
+ epdcp_mcch_del_struct mcch_del[2][8];
+
+ kal_uint8 mrb_add_num[2];
+ kal_uint8 mrb_del_num[2];
+ epdcp_mrb_add_struct mrb_add[2][8];
+ epdcp_mrb_del_struct mrb_del[2][8];
+} errc_epdcp_config_req_struct;
+/*
+ * MSG_ID_ERRC_EPDCP_DETECTION_TIMER_2_START_REQ,
+ *
+ * note: ERRC configure EPDPC detection timer value
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 detection_time_value; // in seconds
+} errc_epdcp_detection_timer_2_start_req_struct;
+
+/* RB loopback config structure */
+typedef struct
+{
+ kal_uint8 rb_idx; //RB index
+ kal_uint8 rb_id;
+ kal_uint8 pad;
+
+ kal_uint8 scaling; //need scaling or not?
+ kal_uint16 size; //scaling size
+} epdcp_rb_lbcfg_struct;
+
+/* LB command for PDCP */
+typedef enpdcp_lb_cmd_enum epdcp_lb_cmd_enum;
+
+//MSG_ID_ERRC_EPDCP_TEST_REQ,
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rb_num; // only valid for mode A
+ kal_uint8 pad0;
+ kal_uint16 pad1;
+ epdcp_rb_lbcfg_struct rb_cfg[8]; // only valid for mode A
+ kal_uint8 mbsfn_area_id; //0~255, only valid for mode C
+ kal_uint8 pmch_id; //0~15, only valid for mode C
+ kal_uint8 lcid; //0~28, only valid for mode C
+ kal_uint8 ci; //0~MAX_EMBMS_FREQ_SUPPORT-1, only valid for mode C
+ epdcp_lb_cmd_enum cmd;
+} errc_epdcp_test_req_struct;
+
+
+#endif //_LTE_ERRC_EPDCP_SAP_STRUCT_DEF_H_
diff --git a/mcu/protocol/interface/enl2/el2/errc_erlcdl_msg.h b/mcu/protocol/interface/enl2/el2/errc_erlcdl_msg.h
new file mode 100644
index 0000000..587fee5
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/errc_erlcdl_msg.h
@@ -0,0 +1,439 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * errc_erlcdl_msg.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * ERRC-ERLCDL SAP header file.
+ * This file defines the structures and enumerations for the SAP between ERRC and ERLCDL
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 25 2019 peter.yu
+ * [MOLY00443312] [MT6885][Petrus][Sanity][VMOLY][VMOLY][2019-09-21_1700] ASSERT = [1][core1,vpe0,tc0(vpe3)] Assert fail: epdcp_rbm.c 6392 - EL2 _
+ * [ERLC] Apply new VC cause.
+ *
+ * 12 17 2018 mingtsung.sun
+ * [MOLY00372769] [VMOLY] enable ENL2 on Gen95 HW platform
+ * ENL2 migration - MPD (errc_emac_msg.h move to MAC CL)
+ *
+ * 07 24 2018 chi-pin.yeh
+ * [MOLY00341764] [Gen97] remove enum errc_el2_cfg_result_enum
+ * Remove enum errc_el2_cfg_result_enum that used for config confirm result
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: NO]
+ * [Group CL list: CL6028187;CL6028430;CL6007875;CL6016735]
+ *
+ * 05 30 2018 peter.chiang
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * [ENL2][Interface] BSR and interface modification patchback
+ *
+ * 03 28 2018 shin.chen
+ * [MOLY00316692] [6297] Interface build-up for ERRC-NRRC, ERRC/NRRC-ENL2, ERRC-EL2 SAP
+ * update el2 interfaces.
+ *
+ * 02 06 2017 peter.yu
+ * [MOLY00207733] [MT6293][EL2] ERLCDL development
+ * [M-SIM] Sync R-SIM related interfaces, remove redundant message IDs related to ERLC.
+ *
+ * 10 07 2016 chih-cheng.yang
+ * [MOLY00206307] [MT6293][NWSIM][Regression][FDD][TC_17_4_1] error in CONN_CHM_LPBK_CNF
+ * fix loop mode C
+ *
+ * 10 06 2016 chih-cheng.yang
+ * [MOLY00206307] [MT6293][NWSIM][Regression][FDD][TC_17_4_1] error in CONN_CHM_LPBK_CNF
+ * changes for loop mode C
+ *
+ * 09 26 2016 slifer.hsueh
+ * [MOLY00205085] [MT6293][EL2] ERLC source codes integration from DEV to TRUNK
+ * ERLC source codes integration from DEV to TRUNK
+ *
+ * 01 04 2016 tero.miettinen
+ * [MOLY00155820] ERRC UMOLY updates
+ * NVRAM IF, ERRC - EL2 IF and ERRC update for 15 bit RLC LI field length.
+ *
+ * 07 03 2015 chi-chung.lin
+ * [MOLY00123918] [MT6291] Modify CHM code to provide eps_br_id in errc_erlcdl_rb_cfg_struct/errc_erlcul_rb_cfg_struct and fix compile warning
+ * [CHM] Code sync. from TK6291_DEV
+ *
+ * 02 02 2015 chi-chung.lin
+ * [MOLY00068710] [MT6291_DEV] Sync MOLY to MT6291_DEV
+ * MOLY->UMOLY code sync.
+ *
+ * 11 11 2014 yiting.cheng
+ * [MOLY00084042] [UMOLY] merge UMOLY_DEV to UMOLY trunk
+ * .
+ *
+ * 09 19 2014 chi-chung.lin
+ * [MOLY00073836] [MT6291][ERRC][CHM] LTE-A CHM development code check-in
+ * [CHM] MBMS interface check in
+ ****************************************************************************/
+
+/// @author mtk01733
+/// @date 08/10/11
+
+#ifndef _MTK_LTE_ERRC_ERLCDL_SAP_H_
+#define _MTK_LTE_ERRC_ERLCDL_SAP_H_
+
+
+#include "el2_sap_common.h"
+#include "common_def.h"
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERLCDL_ERRC_CCCH_DATA_IND
+ *--------------------------------------------------------------------------*/
+// no local parameters
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_CONFIG_REQ (enum)
+ *--------------------------------------------------------------------------*/
+
+// t-Reordering
+typedef enum
+{
+ T_REORDER_MS0 = 0x00,
+ T_REORDER_MS5 = 0x01,
+ T_REORDER_MS10 = 0x02,
+ T_REORDER_MS15 = 0x03,
+ T_REORDER_MS20 = 0x04,
+ T_REORDER_MS25 = 0x05,
+ T_REORDER_MS30 = 0x06,
+ T_REORDER_MS35 = 0x07,
+ T_REORDER_MS40 = 0x08,
+ T_REORDER_MS45 = 0x09,
+ T_REORDER_MS50 = 0x0A,
+ T_REORDER_MS55 = 0x0B,
+ T_REORDER_MS60 = 0x0C,
+ T_REORDER_MS65 = 0x0D,
+ T_REORDER_MS70 = 0x0E,
+ T_REORDER_MS75 = 0x0F,
+ T_REORDER_MS80 = 0x10,
+ T_REORDER_MS85 = 0x11,
+ T_REORDER_MS90 = 0x12,
+ T_REORDER_MS95 = 0x13,
+ T_REORDER_MS100 = 0x14,
+ T_REORDER_MS110 = 0x15,
+ T_REORDER_MS120 = 0x16,
+ T_REORDER_MS130 = 0x17,
+ T_REORDER_MS140 = 0x18,
+ T_REORDER_MS150 = 0x19,
+ T_REORDER_MS160 = 0x1A,
+ T_REORDER_MS170 = 0x1B,
+ T_REORDER_MS180 = 0x1C,
+ T_REORDER_MS190 = 0x1D,
+ T_REORDER_MS200 = 0x1E,
+ T_REORDER_MS1600 = 0x1F
+} errc_erlcdl_t_reorder_enum;
+
+// t-StatusProhibit
+typedef enum
+{
+ T_STUS_PROH_MS0 = 0x00,
+ T_STUS_PROH_MS5 = 0x01,
+ T_STUS_PROH_MS10 = 0x02,
+ T_STUS_PROH_MS15 = 0x03,
+ T_STUS_PROH_MS20 = 0x04,
+ T_STUS_PROH_MS25 = 0x05,
+ T_STUS_PROH_MS30 = 0x06,
+ T_STUS_PROH_MS35 = 0x07,
+ T_STUS_PROH_MS40 = 0x08,
+ T_STUS_PROH_MS45 = 0x09,
+ T_STUS_PROH_MS50 = 0x0A,
+ T_STUS_PROH_MS55 = 0x0B,
+ T_STUS_PROH_MS60 = 0x0C,
+ T_STUS_PROH_MS65 = 0x0D,
+ T_STUS_PROH_MS70 = 0x0E,
+ T_STUS_PROH_MS75 = 0x0F,
+ T_STUS_PROH_MS80 = 0x10,
+ T_STUS_PROH_MS85 = 0x11,
+ T_STUS_PROH_MS90 = 0x12,
+ T_STUS_PROH_MS95 = 0x13,
+ T_STUS_PROH_MS100 = 0x14,
+ T_STUS_PROH_MS105 = 0x15,
+ T_STUS_PROH_MS110 = 0x16,
+ T_STUS_PROH_MS115 = 0x17,
+ T_STUS_PROH_MS120 = 0x18,
+ T_STUS_PROH_MS125 = 0x19,
+ T_STUS_PROH_MS130 = 0x1A,
+ T_STUS_PROH_MS135 = 0x1B,
+ T_STUS_PROH_MS140 = 0x1C,
+ T_STUS_PROH_MS145 = 0x1D,
+ T_STUS_PROH_MS150 = 0x1E,
+ T_STUS_PROH_MS155 = 0x1F,
+ T_STUS_PROH_MS160 = 0x20,
+ T_STUS_PROH_MS165 = 0x21,
+ T_STUS_PROH_MS170 = 0x22,
+ T_STUS_PROH_MS175 = 0x23,
+ T_STUS_PROH_MS180 = 0x24,
+ T_STUS_PROH_MS185 = 0x25,
+ T_STUS_PROH_MS190 = 0x26,
+ T_STUS_PROH_MS195 = 0x27,
+ T_STUS_PROH_MS200 = 0x28,
+ T_STUS_PROH_MS205 = 0x29,
+ T_STUS_PROH_MS210 = 0x2A,
+ T_STUS_PROH_MS215 = 0x2B,
+ T_STUS_PROH_MS220 = 0x2C,
+ T_STUS_PROH_MS225 = 0x2D,
+ T_STUS_PROH_MS230 = 0x2E,
+ T_STUS_PROH_MS235 = 0x2F,
+ T_STUS_PROH_MS240 = 0x30,
+ T_STUS_PROH_MS245 = 0x31,
+ T_STUS_PROH_MS250 = 0x32,
+ T_STUS_PROH_MS300 = 0x33,
+ T_STUS_PROH_MS350 = 0x34,
+ T_STUS_PROH_MS400 = 0x35,
+ T_STUS_PROH_MS450 = 0x36,
+ T_STUS_PROH_MS500 = 0x37,
+ T_STUS_PROH_MS800 = 0x38,
+ T_STUS_PROH_MS1000 = 0x39,
+ T_STUS_PROH_MS1200 = 0x3A,
+ T_STUS_PROH_MS1600 = 0x3B,
+ T_STUS_PROH_MS2000 = 0x3C,
+ T_STUS_PROH_MS2400 = 0x3D,
+
+} errc_erlcdl_t_stus_proh_enum;
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_CONFIG_REQ (struct)
+ *--------------------------------------------------------------------------*/
+
+/// structure for AM entity (receiving side)
+typedef struct
+{
+ errc_erlcdl_t_reorder_enum t_reorder;
+ errc_erlcdl_t_stus_proh_enum t_stus_proh;
+ kal_bool li_field_len_15_bit;
+} errc_erlcdl_am_struct;
+
+
+/// configuration for DL UM entity
+typedef struct
+{
+ errc_erlc_sn_field_len_enum snf_len;
+ errc_erlcdl_t_reorder_enum t_reorder;
+ kal_uint8 flag_pdcp_long_sn;
+ kal_uint8 rsvd[3];
+
+} errc_erlcdl_um_struct;
+
+
+/// DL RB configuration (for RB establish/re-establish/re-configure)
+typedef struct
+{
+#ifdef __EL2_ARCH_V2__
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+#else
+ errc_el2_rbid_enum rbid;
+#endif /* __EL2_ARCH_V2__ */
+ kal_uint8 lcid;
+ kal_uint8 rb_idx;
+ kal_uint8 rsvd;
+
+ errc_erlc_rb_mode_enum mode;
+ errc_erlc_rb_type_enum type;
+
+ /// RLC configuration
+ union {
+ errc_erlcdl_am_struct am_cfg;
+ errc_erlcdl_um_struct um_cfg;
+ } am_um_cfg;
+
+ /// eps bearer id, valid only when DRB and ERLC_MODE_EST/REEST/RECFG
+ kal_uint8 eps_br_id;
+
+} errc_erlcdl_rb_cfg_struct;
+
+
+/// DL RB configuration (for RB release)
+typedef struct
+{
+ kal_uint8 rb_idx; ///< RB index
+#ifdef __EL2_ARCH_V2__
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+#else
+ errc_el2_rbid_enum rbid;
+#endif /* __EL2_ARCH_V2__ */
+ kal_bool ho_failure; ///< if HO failure, remove the new RB.
+ kal_uint8 rsvd;
+
+} errc_erlcdl_rb_rel_struct;
+
+/* CHM MBMS support start */
+typedef struct
+{
+
+ kal_uint8 mcch_idx;
+
+} errc_erlcdl_mcch_cfg_struct;
+
+typedef struct
+{
+
+ kal_uint8 mcch_idx;
+
+} errc_erlcdl_mcch_rel_struct;
+
+typedef struct
+{
+
+ // numbered by eRRC and not from NW,
+ // If one carrier is supported, range 0~7
+ // If two carriers are supported, range 0~15
+ kal_uint8 mrb_idx;
+ kal_uint8 loop_mode_c;
+
+} errc_erlcdl_mrb_cfg_struct;
+
+typedef struct
+{
+
+ kal_uint8 mrb_idx;
+
+} errc_erlcdl_mrb_rel_struct;
+
+/* CHM MBMS support end */
+
+/// MSG_ID_ERRC_ERLCDL_CONFIG_REQ structure
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 n_est_rb; // the number of RBs to be established
+ kal_uint8 n_mod_rb; // the number of RBs to be modified
+ kal_uint8 n_rel_rb; // the number of RBs to be released
+ kal_uint8 rsvd;
+
+ /** RB configurations for the RB to be established */
+ errc_erlcdl_rb_cfg_struct est_rb[MAX_NUM_RLC_CONFIG_RB];
+
+ /** RB configurations for the RB to be modified */
+ errc_erlcdl_rb_cfg_struct mod_rb[MAX_NUM_RLC_CONFIG_RB];
+
+ /** RB configurations for the RB to be released */
+ errc_erlcdl_rb_rel_struct rel_rb[MAX_NUM_RLC_CONFIG_RB];
+
+#ifdef __EL2_ARCH_V2__
+ errc_el2_cell_group_enum cell_group; /* indicate this RB belongs to MCG or SCG, for EN-DC, LTE RB is always MCG */
+#endif /* __EL2_ARCH_V2__ */
+
+/* CHM MBMS support start */
+ kal_uint8 n_est_mcch[MAX_EMBMS_FREQ_SUPPORT];
+ kal_uint8 n_rel_mcch[MAX_EMBMS_FREQ_SUPPORT];
+ errc_erlcdl_mcch_cfg_struct est_mcch[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+ errc_erlcdl_mcch_rel_struct rel_mcch[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+
+ kal_uint8 n_est_mrb[MAX_EMBMS_FREQ_SUPPORT];
+ kal_uint8 n_rel_mrb[MAX_EMBMS_FREQ_SUPPORT];
+ errc_erlcdl_mrb_cfg_struct est_mrb[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MRB_SUPPORT];
+ errc_erlcdl_mrb_rel_struct rel_mrb[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MRB_SUPPORT];
+/* CHM MBMS support end */
+} errc_erlcdl_config_req_struct;
+
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_SWITCH_VIRTUAL_CONNECTED_REQ
+ *--------------------------------------------------------------------------*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ rrc_enl2_switch_virtual_connected_enum status;
+
+} errc_erlcdl_switch_virtual_connected_req_struct;
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_SWITCH_VIRTUAL_CONNECTED_CNF
+ *--------------------------------------------------------------------------*/
+
+//no contents in this CNF, success only
+
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_TESTG_REQ (enum)
+ *--------------------------------------------------------------------------*/
+typedef enum
+{
+ ERLCDL_SAP_LB_CMD_MODE_C_DEACTIVATE = 0,
+ ERLCDL_SAP_LB_CMD_MODE_C_ACTIVATE,
+ ERLCDL_SAP_LB_CMD_MODE_NUM,
+ ERLCDL_SAP_LB_CMD_PAD = 0X7FFFFFFF
+}erlcdl_lb_cmd_enum;
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_TEST_REQ (struct)
+ *--------------------------------------------------------------------------*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 ci;
+ kal_uint8 mrb_idx;
+
+ erlcdl_lb_cmd_enum cmd;
+}errc_erlcdl_test_req_struct;
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCDL_MTCH_PC_CNF (struct)
+ *--------------------------------------------------------------------------*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 packet_count;
+} errc_erlcdl_mtch_pc_cnf_struct;
+
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/errc_erlcul_msg.h b/mcu/protocol/interface/enl2/el2/errc_erlcul_msg.h
new file mode 100644
index 0000000..065d008
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/errc_erlcul_msg.h
@@ -0,0 +1,470 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * errc_erlcul_msg.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * ERRC-ERLCUL SAP file
+ * This file defines the structures and enumerations for the SAP between ERRC and ERLCUL
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 15 2020 nancy.chang
+ * [MOLY00505240] [6297] EN-DC gaming HO enhancement
+ * .
+ *
+ * 12 04 2019 sh.pan
+ * [MOLY00462979] [Gen97]MOB/MEAS/NL1MOB 1001DEV to VMOLY patch back
+ *
+ * .
+ *
+ * 11 13 2019 tsung-ming.lee
+ * [MOLY00441387] [Gen97][ERRC][MOB] NSA& LTE Gaming cell list for mobility enhancement
+ *
+ * -new gaming proposal.
+ *
+ * 09 25 2019 peter.yu
+ * [MOLY00443312] [MT6885][Petrus][Sanity][VMOLY][VMOLY][2019-09-21_1700] ASSERT = [1][core1,vpe0,tc0(vpe3)] Assert fail: epdcp_rbm.c 6392 - EL2 _
+ * [ERLC] Apply new VC cause.
+ *
+ * 09 18 2019 nancy.chang
+ * [MOLY00440286] [6297] ENRLC gaming latency detection
+ * (interface)
+ *
+ * 12 17 2018 mingtsung.sun
+ * [MOLY00372769] [VMOLY] enable ENL2 on Gen95 HW platform
+ * ENL2 migration - MPD (errc_emac_msg.h move to MAC CL)
+ *
+ * 07 24 2018 chi-pin.yeh
+ * [MOLY00341764] [Gen97] remove enum errc_el2_cfg_result_enum
+ * Remove enum errc_el2_cfg_result_enum that used for config confirm result
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: NO]
+ * [Group CL list: CL6028187;CL6028430;CL6007875;CL6016735]
+ *
+ * 05 30 2018 peter.chiang
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * [ENL2][Interface] BSR and interface modification patchback
+ *
+ * 03 28 2018 shin.chen
+ * [MOLY00316692] [6297] Interface build-up for ERRC-NRRC, ERRC/NRRC-ENL2, ERRC-EL2 SAP
+ * update el2 interfaces.
+ *
+ * 02 06 2017 peter.yu
+ * [MOLY00207733] [MT6293][EL2] ERLCDL development
+ * [M-SIM] Sync R-SIM related interfaces, remove redundant message IDs related to ERLC.
+ *
+ * 09 26 2016 slifer.hsueh
+ * [MOLY00205085] [MT6293][EL2] ERLC source codes integration from DEV to TRUNK
+ * ERLC source codes integration from DEV to TRUNK
+ *
+ * 08 04 2016 wei.liao
+ * [MOLY00194969] [MT6293][EL2] ERLC-UL source codes integration from LTE to RD domain
+ * 1.Bug fix: Setup function ptr for retx port.
+ * 2.Bug fix: Fix lsf/rf info registeration for nack.
+ * 3.Add timer enum and config setting in ERLCUL for R13
+ * 4.Init D_ADDR=NULL to prevent the case first desc is normal
+ * (original queue encounter CLDMBA buffer shortage and stop processing)g
+ *
+ * 07 27 2016 jeremy.chen
+ * [MOLY00190683] [UMOLYA][6293] EL2 merge back to UMOLYA TRUNK & PS DEV
+ * [EL2][RD domain] Sync latest EL2 from LTE domain
+ *
+ * 01 04 2016 tero.miettinen
+ * [MOLY00155820] ERRC UMOLY updates
+ * NVRAM IF, ERRC - EL2 IF and ERRC update for 15 bit RLC LI field length.
+ *
+ * 07 03 2015 chi-chung.lin
+ * [MOLY00123918] [MT6291] Modify CHM code to provide eps_br_id in errc_erlcdl_rb_cfg_struct/errc_erlcul_rb_cfg_struct and fix compile warning
+ * [CHM] Code sync. from TK6291_DEV
+ *
+ * 04 08 2015 katie.tseng
+ * [MOLY00104186] [UMOLY] UMOLY code maintenance.
+ * 1. March 2015 MOLY CR sync on ERLC-DL: (1) VoLTE early RLF (2) log reduction
+ * 2. RLC gtest UT fix: set/reset gERLC_Trap_Msg_EN at setup() and teardown()
+ *
+ * 01 22 2014 jeremy.chen
+ * [MOLY00054589] [MT6290E2] add RLF indication from ERLC-DL
+ * rename ERRC_ERLCUL_STATUS_IND to ERRC_ERLC_RLF_IND and modify the interface for both ERLC-UL and ERLC-DL use
+ *
+ * 02 18 2013 jeremy.chen
+ * [MOLY00007127] [MT7208] EL2 enhancement in MOLY
+ * update the comments.
+ ****************************************************************************/
+
+/// @author mtk01733
+/// @date 08/10/11
+
+#ifndef _MTK_LTE_ERRC_ERLCUL_SAP_H_
+#define _MTK_LTE_ERRC_ERLCUL_SAP_H_
+
+
+#include "el2_sap_common.h"
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCUL_CONFIG_REQ (enum)
+ *--------------------------------------------------------------------------*/
+
+/// t-PollRetransmit
+typedef enum
+{
+ T_POLL_RETX_MS5 = 0x00,
+ T_POLL_RETX_MS10 = 0x01,
+ T_POLL_RETX_MS15 = 0x02,
+ T_POLL_RETX_MS20 = 0x03,
+ T_POLL_RETX_MS25 = 0x04,
+ T_POLL_RETX_MS30 = 0x05,
+ T_POLL_RETX_MS35 = 0x06,
+ T_POLL_RETX_MS40 = 0x07,
+ T_POLL_RETX_MS45 = 0x08,
+ T_POLL_RETX_MS50 = 0x09,
+ T_POLL_RETX_MS55 = 0x0A,
+ T_POLL_RETX_MS60 = 0x0B,
+ T_POLL_RETX_MS65 = 0x0C,
+ T_POLL_RETX_MS70 = 0x0D,
+ T_POLL_RETX_MS75 = 0x0E,
+ T_POLL_RETX_MS80 = 0x0F,
+ T_POLL_RETX_MS85 = 0x10,
+ T_POLL_RETX_MS90 = 0x11,
+ T_POLL_RETX_MS95 = 0x12,
+ T_POLL_RETX_MS100 = 0x13,
+ T_POLL_RETX_MS105 = 0x14,
+ T_POLL_RETX_MS110 = 0x15,
+ T_POLL_RETX_MS115 = 0x16,
+ T_POLL_RETX_MS120 = 0x17,
+ T_POLL_RETX_MS125 = 0x18,
+ T_POLL_RETX_MS130 = 0x19,
+ T_POLL_RETX_MS135 = 0x1A,
+ T_POLL_RETX_MS140 = 0x1B,
+ T_POLL_RETX_MS145 = 0x1C,
+ T_POLL_RETX_MS150 = 0x1D,
+ T_POLL_RETX_MS155 = 0x1E,
+ T_POLL_RETX_MS160 = 0x1F,
+ T_POLL_RETX_MS165 = 0x20,
+ T_POLL_RETX_MS170 = 0x21,
+ T_POLL_RETX_MS175 = 0x22,
+ T_POLL_RETX_MS180 = 0x23,
+ T_POLL_RETX_MS185 = 0x24,
+ T_POLL_RETX_MS190 = 0x25,
+ T_POLL_RETX_MS195 = 0x26,
+ T_POLL_RETX_MS200 = 0x27,
+ T_POLL_RETX_MS205 = 0x28,
+ T_POLL_RETX_MS210 = 0x29,
+ T_POLL_RETX_MS215 = 0x2A,
+ T_POLL_RETX_MS220 = 0x2B,
+ T_POLL_RETX_MS225 = 0x2C,
+ T_POLL_RETX_MS230 = 0x2D,
+ T_POLL_RETX_MS235 = 0x2E,
+ T_POLL_RETX_MS240 = 0x2F,
+ T_POLL_RETX_MS245 = 0x30,
+ T_POLL_RETX_MS250 = 0x31,
+ T_POLL_RETX_MS300 = 0x32,
+ T_POLL_RETX_MS350 = 0x33,
+ T_POLL_RETX_MS400 = 0x34,
+ T_POLL_RETX_MS450 = 0x35,
+ T_POLL_RETX_MS500 = 0x36,
+ T_POLL_RETX_MS800 = 0x37,
+ T_POLL_RETX_MS1000 = 0x38,
+ T_POLL_RETX_MS2000 = 0x39,
+ T_POLL_RETX_MS4000 = 0x3A
+
+} errc_erlcul_t_pollretx_enum;
+
+/// Poll PDU counter
+typedef enum
+{
+ POLL_PDU_P4 = 0x00,
+ POLL_PDU_P8 = 0x01,
+ POLL_PDU_P16 = 0x02,
+ POLL_PDU_P32 = 0x03,
+ POLL_PDU_P64 = 0x04,
+ POLL_PDU_P128 = 0x05,
+ POLL_PDU_P256 = 0x06,
+ POLL_PDU_PINF = 0x07
+} errc_erlcul_poll_pdu_enum;
+
+
+/// Poll byte counter
+typedef enum
+{
+ POLL_BYTE_KB25 = 0x00,
+ POLL_BYTE_KB50 = 0x01,
+ POLL_BYTE_KB75 = 0x02,
+ POLL_BYTE_KB100 = 0x03,
+ POLL_BYTE_KB125 = 0x04,
+ POLL_BYTE_KB250 = 0x05,
+ POLL_BYTE_KB375 = 0x06,
+ POLL_BYTE_KB500 = 0x07,
+ POLL_BYTE_KB750 = 0x08,
+ POLL_BYTE_KB1000 = 0x09,
+ POLL_BYTE_KB1250 = 0x0A,
+ POLL_BYTE_KB1500 = 0x0B,
+ POLL_BYTE_KB2000 = 0x0C,
+ POLL_BYTE_KB3000 = 0x0D,
+ POLL_BYTE_KBINF = 0x0E
+
+} errc_erlcul_poll_byte_enum;
+
+
+/// maximum retranmsission threshold
+typedef enum
+{
+ MAX_RETX_T1 = 0x00,
+ MAX_RETX_T2 = 0x01,
+ MAX_RETX_T3 = 0x02,
+ MAX_RETX_T4 = 0x03,
+ MAX_RETX_T6 = 0x04,
+ MAX_RETX_T8 = 0x05,
+ MAX_RETX_T16 = 0x06,
+ MAX_RETX_T32 = 0x07
+
+} errc_erlcul_max_retx_enum;
+
+
+
+/// PDCP SN length
+typedef enum
+{
+ PDCP_SN_LEN_05 = 05, // PDCP SN length = 05 bits (SRB)
+ PDCP_SN_LEN_07 = 07, // PDCP SN length = 07 bits (DRB UM)
+ PDCP_SN_LEN_12 = 12, // PDCP SN length = 12 bits (DRB AM or UM)
+ PDCP_SN_LEN_15 = 15, // PDCP SN length = 15 bits (DRB AM)
+ PDCP_SN_LEN_18 = 18, // PDCP SN length = 18 bits (DRB AM)
+
+} errc_erlcul_pdcp_sn_len_enum;
+
+typedef enum
+{
+ CELL_STATUS_INVALID = 0,
+ CELL_STATUS_NEW = 1,
+ CELL_STATUS_LONG_GOOD = 2,
+ CELL_STATUS_GOOD = 3,
+ CELL_STATUS_BAD = 4,
+ CELL_STATUS_VERY_BAD = 5,
+ CELL_STATUS_LONG_VERY_BAD = 6,
+ CELL_STATUS_NUM
+} errc_erlcul_gaming_status_enum;
+
+typedef enum
+{
+ CELL_GROUP_MCG = 0,
+ CELL_GROUP_SCG = 1,
+ CELL_GROUP_HISTORICAL = 2
+} errc_erlcul_gaming_cell_group_enum;
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCUL_CONFIG_REQ (struct)
+ *--------------------------------------------------------------------------*/
+
+/// configuration AM entity (transmitting side)
+typedef struct
+{
+ errc_erlcul_t_pollretx_enum t_pollretx;
+ errc_erlcul_poll_pdu_enum poll_pdu;
+ errc_erlcul_poll_byte_enum poll_byte;
+ errc_erlcul_max_retx_enum max_retx;
+ kal_bool li_field_len_15_bit;
+} errc_erlcul_am_struct;
+
+
+/// configuration for UL UM entity
+typedef struct
+{
+ errc_erlc_sn_field_len_enum snf_len;
+
+} errc_erlcul_um_struct;
+
+
+/// UL RB configuration (for RB establish/re-establish/re-configure)
+typedef struct
+{
+#ifdef __EL2_ARCH_V2__
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+#else
+ errc_el2_rbid_enum rbid;
+#endif /* __EL2_ARCH_V2__ */
+ kal_uint8 lcid;
+ kal_uint8 rb_idx;
+
+ errc_erlc_rb_mode_enum mode;
+ errc_erlc_rb_type_enum type;
+
+ /// RLC configuration
+ union {
+ errc_erlcul_am_struct am_cfg;
+ errc_erlcul_um_struct um_cfg;
+ } am_um_cfg;
+
+ /// logical channel configuration
+ errc_el2_lch_cfg lch_cfg;
+
+ /// eps bearer id, valid only when DRB and ERLC_MODE_EST/REEST/RECFG
+ kal_uint8 eps_br_id;
+
+ kal_uint8 rsvd_1;
+ kal_uint16 rsvd_2;
+
+} errc_erlcul_rb_cfg_struct;
+
+
+/// UL RB configuration (for RB release)
+typedef struct
+{
+ kal_uint8 rb_idx; ///< RB index
+#ifdef __EL2_ARCH_V2__
+ errc_el2_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-2, DRB: 1-32 */
+#else
+ errc_el2_rbid_enum rbid; ///< RBID
+#endif /* __EL2_ARCH_V2__ */
+ kal_bool ho_failure; ///< if HO failure, remove the new RB.
+ kal_uint8 rsvd;
+
+} errc_erlcul_rb_rel_struct;
+
+
+/// MSG_ID_ERRC_ERLCDL_CONFIG_REQ structure
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 n_est_rb; // the number of RBs to be established
+ kal_uint8 n_mod_rb; // the number of RBs to be modified
+ kal_uint8 n_rel_rb; // the number of RBs to be released
+ kal_uint8 rsvd;
+
+ /** RB configurations for the RB to be established */
+ errc_erlcul_rb_cfg_struct est_rb[MAX_NUM_RLC_CONFIG_RB];
+
+ /** RB configurations for the RB to be modified */
+ errc_erlcul_rb_cfg_struct mod_rb[MAX_NUM_RLC_CONFIG_RB];
+
+ /** RB configurations for the RB to be released */
+ errc_erlcul_rb_rel_struct rel_rb[MAX_NUM_RLC_CONFIG_RB];
+
+#ifdef __EL2_ARCH_V2__
+ errc_el2_cell_group_enum cell_group; /* indicate this RB belongs to MCG or SCG, for EN-DC, LTE RB is always MCG */
+#endif /* __EL2_ARCH_V2__ */
+
+ kal_uint16 pci;
+ kal_uint32 earfcn;
+} errc_erlcul_config_req_struct;
+
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCUL_SRB1_ACK_REQ
+ *--------------------------------------------------------------------------*/
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ /// report control flag
+ /// - KAL_TRUE: start report
+ /// - KAL_FALSE: stop report
+ kal_bool report;
+
+ kal_uint8 rsvd_1;
+ kal_uint16 rsvd_2;
+
+} errc_erlcul_srb1_ack_req_struct;
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERLCUL_ERRC_SRB1_ACK_CNF
+ *--------------------------------------------------------------------------*/
+// no local parameters
+
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCUL_SWITCH_VIRTUAL_CONNECTED_REQ
+ *--------------------------------------------------------------------------*/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ rrc_enl2_switch_virtual_connected_enum status;
+
+} errc_erlcul_switch_virtual_connected_req_struct;
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCUL_SWITCH_VIRTUAL_CONNECTED_CNF
+ *--------------------------------------------------------------------------*/
+
+//no contents in this CNF, success only
+
+/*--------------------------------------------------------------------------
+ * MSG_ID_ERRC_ERLCUL_GAMING_CELL_INFO_NTF
+ *--------------------------------------------------------------------------*/
+
+#define MAX_REPORTED_CELL_NUM (10)
+
+typedef struct
+{
+ kal_uint16 pci;
+ kal_uint16 rsvd;
+ kal_uint32 earfcn;
+ errc_erlcul_gaming_status_enum cell_status;
+ errc_erlcul_gaming_cell_group_enum cell_group;
+} errc_erlcul_gaming_cell_info_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 cell_num;
+ kal_uint16 rsvd;
+ errc_erlcul_gaming_cell_info_struct cell_info[MAX_REPORTED_CELL_NUM];
+
+} errc_erlcul_gaming_cell_info_ntf_struct;
+
+#endif
diff --git a/mcu/protocol/interface/enl2/el2/etc_upcm_struct.h b/mcu/protocol/interface/enl2/el2/etc_upcm_struct.h
new file mode 100644
index 0000000..9f932f9
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/etc_upcm_struct.h
@@ -0,0 +1,92 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * etc_upcm_struct.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * message and common structure definition between ETC and UPCM module
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ ****************************************************************************/
+
+#ifndef ETC_UPCM_STRUCT_INC
+#define ETC_UPCM_STRUCT_INC
+
+#include "l3_inc_local.h"
+
+/***** message structure definition *****/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_activate; /* KAL_TRUE: activate, KAL_FALSE: deactivate */
+} etc_upcm_testmode_req_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 result; /* 0: success, 1: status error */
+} etc_upcm_testmode_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_close; /* KAL_TRUE: close loop, KAL_FALSE: open loop */
+ kal_uint8 delay_time;
+} etc_upcm_testloop_req_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 result; /* 0: success, 1: status error */
+} etc_upcm_testloop_cnf_struct;
+
+
+#endif /* ----- #ifndef ETC_UPCM_STRUCT_INC ----- */
+
diff --git a/mcu/protocol/interface/enl2/el2/ltm.h b/mcu/protocol/interface/enl2/el2/ltm.h
new file mode 100644
index 0000000..4596c71
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/ltm.h
@@ -0,0 +1,152 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * ltm.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 17 2012 moja.hsu
+ * [MOLY00007625] Maintain code
+ * adjust interface usage.
+ ****************************************************************************/
+/*
+ * =====================================================================================
+ *
+ * Filename: ltm.h
+ *
+ * Description: LTM (LTE traffic manager exported header file)
+ *
+ * Created: 2011/10/28 ¤U¤È 07:03:55
+ * Author: mtk01641 (moja)
+ * =====================================================================================
+ */
+#ifndef LTM_INC
+#define LTM_INC
+
+#include "kal_public_api.h"
+#include "ratcommon.h"
+
+/*
+ * lte tick source notify callback prototype.
+ * is_lte_tick: KAL_TRUE - has LTE tick.
+ * KAL_FLAE - may no LTE tick.
+ */
+typedef void (*ltm_multi_notify_lte_tick_f)(kal_bool is_lte_tick);
+
+/**
+ * @brief ltm_multiinit
+ * Init LTM module.
+ *
+ * @return TRUE
+ */
+kal_bool ltm_multi_init(void);
+
+/**
+ * @brief ltm_multiinit
+ * Reset LTM module.
+ *
+ * @return TRUE
+ */
+kal_bool ltm_multi_reset(void);
+
+/**
+ * @brief ltm_multion_ilm
+ * Receive ILM message
+ *
+ * @param ilm
+ */
+void ltm_multi_on_ilm(ilm_struct *p_ilm);
+
+/**
+ * @brief ltm_multircv_ul_sdu
+ * Receive UL SDUs. UL SDU are GPD list.
+ *
+ * @param ebi EPSB ID
+ * @param p_head SDU list head. (GPD based)
+ * @param p_tail SDU list tail. (GPD based)
+ */
+void ltm_multi_rcv_ul_sdu(kal_uint32 ebi, ratcmn_ul_sdu_t *p_sdus);
+
+/**
+ * @brief ltm_multireg_cbk_notify_lte_tick
+ * Register callback function.
+ * For get if there is a LTE tick source.
+ *
+ * @param pf_notify callback function.
+ */
+void ltm_multi_reg_cbk_notify_lte_tick(ltm_multi_notify_lte_tick_f pf_notify);
+
+/**
+ * @brief ltm_multireg_cbk_dlvr_dl_sdu
+ * Register callback for deliver DL SDUs.
+ *
+ * @param pf_dlvr_sdu
+ */
+void ltm_multi_reg_cbk_dlvr_dl_sdu(ratcmn_dlvr_dl_sdu_f pf_dlvr_sdu);
+
+/**
+ * @brief ltm_multi_reg_cbk_hook_ul
+ * Register callback for LTE UL traffic.
+ *
+ * @param pf_hook
+ */
+void ltm_multi_reg_cbk_hook_ul(ratcmn_hook_ul_f pf_hook);
+
+/**
+ * @brief ltm_multi_reg_cbk_rollback_ul_sdu
+ * Register callback for LTE UL traffic rollback.
+ *
+ * @param pf_hook
+ */
+void ltm_multi_reg_cbk_rollback_ul_sdu(ratcmn_rollback_sdu_f pf_rollback);
+#endif /* ----- #ifndef LTM_INC ----- */
+
diff --git a/mcu/protocol/interface/enl2/el2/ltm_el2_struct.h b/mcu/protocol/interface/enl2/el2/ltm_el2_struct.h
new file mode 100644
index 0000000..e853777
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/ltm_el2_struct.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * ltm_el2_struct.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * message and common structure definition between LTM and EL2 modules.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 13 2013 steve.kao
+ * [MOLY00048789] [MT6290E2][EL2 RTD] UE not triggering UL data transmission
+ * Integrate change for using OS tick in OA domain
+ *
+ * 11 22 2013 timothy.yao
+ * [MOLY00047052] add trace/code for LV
+ * modify ulsdu_info structure for ipid
+ *
+ * 06 17 2013 clark.peng
+ * [MOLY00025883] [MT6290][EL2] Move shared definitions in ROHC and EL2 to OA domain
+ *
+ ****************************************************************************/
+
+
+#ifndef LTM_EL2_STRUCT_INC
+#define LTM_EL2_STRUCT_INC
+
+#include "qmu_bm.h"
+
+/**
+ * @brief DRB UL-SDU info Header
+ *
+ * note:
+ * - location : in SW control field of BM-header
+ */
+typedef struct
+{
+ /*** this 4 bytes is reserved for UPCM, DO NOT change the location ***/
+ kal_uint16 ipid;
+ kal_uint16 rsvd;
+
+ /*** Don't change the following 4 bytes layout, because ltm will use 4 bytes write to clean it***/
+#define ULSDU_INFO_HEAD_FLAG_PRIORITY 0x01
+#define ULSDU_INFO_HEAD_FLAG_CTRL_PDU 0x02
+#define ULSDU_INFO_HEAD_FLAG_RETX_WI_SN 0x04
+ kal_uint8 flag_bmp;
+ kal_uint8 rsv1;
+ kal_uint16 ori_hdr_sz;
+ /*** Don't change the above 4 bytes layout, because ltm will use 4 bytes write to clean it***/
+ /* pad for maintaining original structure when ABS TICK was used */
+ kal_uint32 rsv2;
+ /* entry tick, it will be filled by ltm using 32-bit OS tick */
+ kal_uint32 tick;
+
+ /* Tx HFN & SN */
+ kal_uint32 pdcp_count;
+}drb_ulsdu_info_head_t;
+#define GET_ULSDU_INFO_HEAD(_p) ((drb_ulsdu_info_head_t*)QBM_DES_GET_SW_CTRL_FIELD(_p))
+
+/* Get Macros */
+#define GET_DRB_ULSDU_PRIDATA(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp & ULSDU_INFO_HEAD_FLAG_PRIORITY)
+#define GET_DRB_ULSDU_CTRLPDU(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp & ULSDU_INFO_HEAD_FLAG_CTRL_PDU)
+#define GET_DRB_ULSDU_RETX(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp & ULSDU_INFO_HEAD_FLAG_RETX_WI_SN)
+
+/* Set Macros */
+#define SET_DRB_ULSDU_PRIDATA(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp |= ULSDU_INFO_HEAD_FLAG_PRIORITY)
+#define SET_DRB_ULSDU_CTRLPDU(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp |= ULSDU_INFO_HEAD_FLAG_CTRL_PDU)
+#define SET_DRB_ULSDU_RETX(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp |= ULSDU_INFO_HEAD_FLAG_RETX_WI_SN)
+
+/* Clear Macros */
+#define CLR_DRB_ULSDU_PRIDATA(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp &= ~ULSDU_INFO_HEAD_FLAG_PRIORITY)
+#define CLR_DRB_ULSDU_CTRLPDU(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp &= ~ULSDU_INFO_HEAD_FLAG_CTRL_PDU)
+#define CLR_DRB_ULSDU_RETX(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp &= ~ULSDU_INFO_HEAD_FLAG_RETX_WI_SN)
+#define CLR_DRB_ULSDU_FLAG_BMP(_p) \
+ (GET_ULSDU_INFO_HEAD(_p)->flag_bmp = 0)
+
+
+#endif /* ----- #ifndef LTM_EL2_STRUCT_INC ----- */
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/el2_trc.h b/mcu/protocol/interface/enl2/el2/trace/el2_trc.h
new file mode 100644
index 0000000..47bcffb
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/el2_trc.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * el2_trc.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * LTE Layer 2 trace definition.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 14 2017 i-feng.chen
+ * [MOLY00295624] [EPDCP][RJIL] Print ROHC compression and decompression info on PS integrated
+ *
+ * [R3][EPDCP][RJIL] Print ROHC compression and decompression info on PS integrated
+ *
+ * 06 22 2017 nicole.hsu
+ * [MOLY00259119] [MT6763][EL2] EMAC/EL2EM/EL2POW maintenance
+ * [TRUNK] add emacdl trace dump
+ *
+ * 03 30 2017 mf.jhang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * . Add PS trace while assert
+ *
+ ****************************************************************************/
+
+#ifndef _EL2_TRC_H
+#define _EL2_TRC_H
+
+#ifndef GEN_FOR_PC
+ #include "stack_config.h"
+#endif
+
+#include "kal_public_defs.h"
+#include "dhl_trace.h"
+
+#if !defined(GEN_FOR_PC)
+#if defined(__DHL_MODULE__) || defined(__CUSTOM_RELEASE__)
+ #include "el2_trc_gen.h"
+#endif
+#endif
+
+/* ---------------------- Trace Function ------------------ */
+/*#define EL2_PUBLIC_TRACE0(msg_index) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index)*/
+/*#define EL2_PUBLIC_TRACE1(msg_index, a1) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1)*/
+/*#define EL2_PUBLIC_TRACE2(msg_index, a1, a2) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2) */
+/*#define EL2_PUBLIC_TRACE3(msg_index, a1, a2, a3) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3) */
+/*#define EL2_PUBLIC_TRACE4(msg_index, a1, a2, a3, a4) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3, a4)*/
+/*#define EL2_PUBLIC_TRACE5(msg_index, a1, a2, a3, a4, a5) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3, a4, a5)*/
+/*#define EL2_PUBLIC_TRACE6(msg_index, a1, a2, a3, a4, a5, a6) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3, a4, a5, a6)*/
+/*#define EL2_PUBLIC_TRACE7(msg_index, a1, a2, a3, a4, a5, a6, a7) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3, a4, a5, a6, a7)*/
+/*#define EL2_PUBLIC_TRACE8(msg_index, a1, a2, a3, a4, a5, a6, a7, a8) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3, a4, a5, a6, a7, a8)*/
+/*#define EL2_PUBLIC_TRACE9(msg_index, a1, a2, a3, a4, a5, a6, a7, a8, a9) \
+ dhl_internal_trace(TRACE_INFO, 0, DHL_ACCESS_LEVEL_1_ALL_USER, msg_index, a1, a2, a3, a4, a5, a6, a7, a8, a9)*/
+
+
+BEGIN_TRACE_MAP(MOD_EL2PORTAL)
+
+TRC_MSG(EL2_ASSERT_LOG_ENTER, "Enter el2_exception_custom_logging ")
+TRC_MSG(EL2_ASSERT_LOG_EXIT, "Exit el2_exception_custom_logging")
+TRC_MSG(EL2_TRACE_TIME, "abs_time: %u, cell_time %u")
+TRC_MSG(EMAC_TRACE_INPUT_0001, "[EMAC][DL-HARQ] \n<crc: cc_idx=%u, dl_harq_id=%u, tb_valid=%u%u, rlt=%u%u>")
+TRC_MSG(EMAC_TRACE_INPUT_0010, "[EMAC][UL-HARQ] \n<phich: ul_cc_idx=%u, harq_id=%u, rlt=%u>")
+TRC_MSG(EMAC_TRACE_INPUT_0100, "[EMAC][DL-HARQ] \n<dldci: t-%u, cc_idx=%u, dl_harq_id=%u, type=1, sps=0, tb_valid=%u%u, new=%u%u>")
+TRC_MSG(EMAC_TRACE_INPUT_1000, "[EMAC][UL-HARQ] \n<uldci: t-%u, ul_cc_idx=%u, type=0, ndi=%u, rv=%u, tbs=%u, k=%u>")
+TRC_MSG(EMAC_TRACE_UL_HARQ_TL_INFO, "[EMAC][UL-HARQ] ul_cc_idx=%u <ul status=%X, type=%u, harq_id=%u, ndi=%u, mode=%u, ack=%u, tx=%u, mux=%u>")
+TRC_MSG(EMAC_TRACE_UL_HARQ_TX_INFO, "[EMAC][UL-HARQ] ul_cc_idx=%u <harq status=%X, buffer=%u, bundle=%u, rv=%u, cnt=%u, tbs=%u>")
+TRC_MSG(EMAC_TRACE_UL_HARQ_RETX_INFO, "[EMAC][UL-HARQ] ul_cc_idx=%u <retx time=%u, phich time=%u, uldci num=%u, uldci1=%u, uldci2=%u>")
+TRC_MSG(EMAC_TRACE_UL_HARQ_CLOSE, "[EMAC][UL-HARQ] ul_cc_idx=%u <harq_id=%u close>")
+TRC_MSG(EMAC_TRACE_UL_HARQ_ACTIVATE, "[EMAC][UL-HARQ] ul_cc_idx=%u <harq_id=%u activate>")
+TRC_MSG(EMAC_TRACE_DRX_STATUS,"[EMAC][TTI] <dci_decode_time_diff=%u> <drx_status: n1=%u, n2=%u> <slp_status: r_n1=%u, r_n2=%u, c_n1=%u, c_n2=%u>")
+TRC_MSG(EMAC_TRACE_DL_TB_INFO, "[EMAC][DL][TB] \n<TB %u: %X>")
+
+TRC_MSG(EPDCP_TRACE_UL_ROHC_C_INFO, "[EPDCP][UL][ROHC] DRB RoHC data compressed: rb_idx=%d, ori hdr sz =%u, compr hdr sz=%u")
+TRC_MSG(EPDCP_TRACE_DL_ROHC_IN_OUT, "[EPDCP][DL][ROHC] DRB RoHC data processed: rb_idx=%d, input num=%u, output num=%u")
+END_TRACE_MAP(MOD_EL2PORTAL)
+
+
+#endif /* _EL2_TRC_H */
diff --git a/mcu/protocol/interface/enl2/el2/trace/emac_trace_1.tmd b/mcu/protocol/interface/enl2/el2/trace/emac_trace_1.tmd
new file mode 100644
index 0000000..fd84eab
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/emac_trace_1.tmd
@@ -0,0 +1,481 @@
+[Default]
+EMAC_1
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 15
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+EMAC_LV1_H ON // Internal use (basic information)
+EMAC_LV2_H ON // Internal use (more information)
+EMAC_LV3_H ON // Internal use (detail)
+EMAC_WARN_H ON // Internal use
+EMAC_ERROR_H ON // Internal use
+EMAC_DEBUG_H ON // For temp log
+
+[String]
+
+[Message]
+
+// ============================================================================================================
+// COMMON
+// ============================================================================================================
+info EMAC_LOG_DUMMY_4 EMAC_LV1_H "[EMAC] Dummy Log %l, %l, %l, %l"
+info EMAC_LOG_DUMP_4 EMAC_LV1_H "[EMAC] Dump: %xl %xl %xl %xl"
+info EMAC_LOG_GROUP_ASSERT EMAC_LV1_H "[EMAC] group_assert_id=%ul"
+info (non_smp) EMAC_LOG_TTI_ALL_INFO EMAC_LV1_H "[EMAC][TTI] \n<dci_decode_time_diff=%ul:2> \n<drx_status: n1=%ul:2, n2=%ul:2> \n<slp_status: r_n1=%ul:3, r_n2=%ul:3, c_n1=%ul:3, c_n2=%ul:3> \n<drx_inact_tmr_start: p1=%ul:1, p2=%ul:1%pl:12>"
+warn (non_smp) EMAC_LOG_TX_REQ_CHANGE EMAC_LV1_H "[EMAC][WARN][UL-HARQ][RA][SR] TX REQ BMP %xl changed by L1 to %xl"
+info (non_smp) EMAC_LOG_PROTOCOL_IDX_CHANGE EMAC_LV1_H "[EMAC] old el1_protocol_idx=%ub, new el1_protocol_idx=%ub"
+warn (non_smp) EMAC_LOG_PROTOCOL_IDX_RRC_EL1_MISMATCH EMAC_LV1_H "[EMAC][WARN] protocol_idx mismatch during rrc non-reset, el1_protocol_idx=%ub, errc_protocol_idx=%ub"
+warn (non_smp) EMAC_LOG_ERT_SF_PROC_ONGOING EMAC_LV1_H "[EMAC][WARN] ert sf proc is still on-going, abs_time=%ul"
+warn EMAC_LOG_CHECKSUM_ERROR_BYPASS EMAC_LV1_H "[EMAC][WARN] tx checksum error bypass, tx_abs_time=%ul, bypass=%ub"
+info (non_smp) EMAC_LOG_HRT_PROFILE_START EMAC_LV1_H "[EMAC][HRT] start: %Memac_txlisr_func_e, frc=%ul"
+info (non_smp) EMAC_LOG_HRT_PROFILE_END EMAC_LV1_H "[EMAC][HRT] end: %Memac_txlisr_func_e, frc=%ul"
+info EMAC_ERT_LOG_OUTPUT_BMP EMAC_LV1_H "[EMAC][ERT] TXLISR output bitmap: %xl:4 %xl:4 %xl:4 %xl:4 %xl:4 %xl:4 %xl:4 %xl:4"
+
+info EMAC_LOG_EL2_SBP_FEAT EMAC_LV1_H "[EMAC][SBP] el2 SBP feature: protocol_idx_0=%xl, protocol_idx_1=%xl, protocol_idx_2=%xl, protocol_idx_3=%xl"
+info EMAC_LOG_EMAC_EDYN_FEAT EMAC_LV1_H "[EMAC][FEAT] emac dynamic feature=%xl"
+
+
+// ============================================================================================================
+// PDCCH Input
+// ============================================================================================================
+
+// Level 1
+
+// Level 2
+
+// Level 3
+
+// Others
+warn (non_smp) EMAC_PDCCH_WARN___PHICH_TARGET_INVALID EMAC_WARN_H "[EMAC][PDCCH][PHICH] invalid target harq"
+warn (non_smp) EMAC_PDCCH_WARN___DCI_SLEEP_DROP EMAC_WARN_H "[EMAC][PDCCH] dci sleep state drop"
+warn (non_smp) EMAC_PDCCH_WARN___ASYNC_SYNC_MODE_DCI_DROP EMAC_WARN_H "[EMAC][PDCCH] async-sync mode dci drop: reason=%ub"
+
+// ============================================================================================================
+// UL HARQ
+// ============================================================================================================
+
+// Level 1
+info EMAC_UL_HARQ_LOG___INIT EMAC_LV1_H "[EMAC][UL-HARQ] initialization"
+
+info (non_smp) EMAC_UL_HARQ_LOG___GRANT_RESOLUTION EMAC_LV1_H "[EMAC][UL-HARQ][GRANT] resolve with ulsch_grant_type=%ub, discard_input_grant=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___GRANT_CLEAR_RAR EMAC_LV1_H "[EMAC][UL-HARQ][GRANT] clear rar grant: ul_cc_idx=%ub, tx_abs_time_32=%ul"
+
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_TX_MAX_REACHED EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: tx max reached: ul_cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_TX_MAX_REACHED_SKIP_RETX EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: tx max reached after skip retx: ul_cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_TX_MAX_REACHED_REPETITION EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: tx max reached for async harq repetition: ul_cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_MSG3_RETX_COLLISION EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: msg3 harq collision: ul_cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_PRONE_TO_UNSUCCESS EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: prone to unsuccess: ul_cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_L2_LATENCY_REDUCTION EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: l2 latency reduction: ul_cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_FLUSH_MSG3 EMAC_LV1_H "[EMAC][UL-HARQ] harq flush msg3"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_CLOSE_ALL EMAC_LV1_H "[EMAC][UL-HARQ] harq close all"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_CLOSE_SCELL_ALL EMAC_LV1_H "[EMAC][UL-HARQ] harq close scell all: cc_idx=%ub, ul_cc_idx=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_CLOSE EMAC_LV1_H "[EMAC][UL-HARQ] ul_cc_idx=%ub <harq_id=%ub close>"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_DETACH EMAC_LV1_H "[EMAC][UL-HARQ] ul_cc_idx=%ub <harq_id=%ub detach>"
+
+info (non_smp) EMAC_UL_HARQ_LOG___TTI_PCELL_TA_NOT_RUNNING EMAC_LV1_H "[EMAC][UL-HARQ][TTI] pcell ta timer not running"
+info (non_smp) EMAC_UL_HARQ_LOG___TTI_NO_TX_OPPORTUNITY EMAC_LV1_H "[EMAC][UL-HARQ][TTI] ul_cc_idx=%ub, cell_active=%ub, ta_running=%ub, b_ul_sf=%ub"
+
+
+info (non_smp) EMAC_UL_HARQ_LOG___TX_MODE_GRANT_TCRNTI_AS_NEW_CRNTI EMAC_LV1_H "[EMAC][UL-HARQ][TM] grant only: tc-rnti as new c-rnti"
+info (non_smp) EMAC_UL_HARQ_LOG___TX_MODE_CRNTI_GRANT_AS_TCRNTI EMAC_LV1_H "[EMAC][UL-HARQ][TM] c-rnti grant: as for tc-rnti harq"
+info (non_smp) EMAC_UL_HARQ_LOG___TX_MODE_TCRNTI_GRANT_AS_CRNTI EMAC_LV1_H "[EMAC][UL-HARQ][TM] tc-rnti grant: as c-rnti"
+info (non_smp) EMAC_UL_HARQ_LOG___TX_MODE_RV0_TBS_MISMATCHED_RETX_AS_NEW EMAC_LV1_H "[EMAC][UL-HARQ][TM] rv0 tbs mismatched retx as new"
+info (non_smp) EMAC_UL_HARQ_LOG___TX_MODE_DROP_GRANT_FOR_NONADP_RETX EMAC_LV1_H "[EMAC][UL-HARQ][TM] drop configured grant for non-adaptive retx"
+
+info (non_smp) EMAC_UL_HARQ_LOG___SETTING_NEW_MSG3 EMAC_LV1_H "[EMAC][UL-HARQ][RA][SETTING] new msg3"
+
+info (non_smp) EMAC_UL_HARQ_LOG___RETX_INFO_FOR_CANCELLED_RETX EMAC_LV1_H "[EMAC][UL-HARQ][RETX] for cancelled retx: time_to_retx=%ub, pdcch_num=%ub, time_to_phich=%ub, time_to_pdcch[0]=%ub, time_to_pdcch[1]=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___RETX_NON_MSG3_HARQ_COLLISION EMAC_LV1_H "[EMAC][UL-HARQ][RETX] non-msg3 harq collision : close collided harq"
+
+info (non_smp) EMAC_UL_HARQ_LOG___ACKED_HARQ_WITH_RETX_GRANT EMAC_LV1_H "[EMAC][UL-HARQ][KPI] acked harq with retx grant"
+
+info (non_smp) EMAC_UL_HARQ_LOG___UL_HARQ_GAP_END_SKIP_TX EMAC_LV1_H "[EMAC][UL-HARQ] tx not allowed: harq id=%ud, rv=%ud, actual_tx_cnt=%ud, tx_skip_reason=%ub"
+// Level 2
+
+// Level 3
+
+// Others
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_GRANT_INVALID EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: grant only: invalid grant"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_CRNTI_GRANT_RETX_INVALID EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: c-rnti grant: retx invalid"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_CRNTI_GRANT_AS_TCRNTI_RETX_INVALID EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: c-rnti grant: as for tc-rnti retx invalid"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_CRNTI_GRANT_DROP EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: c-rnti grant: harq: rnti_type=%ub, b_same_ndi=%ub, b_index=%ub"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_TCRNTI_GRANT_DROP EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: tc-rnti grant: harq: rnti_type=%ub, b_same_ndi=%ub, grant: rv=%ub"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_SPS_RETX_TARGET_INVALID EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: sps retx grant: target invalid"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_SPS_RETX_GRANT_INVALID EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: sps retx grant: rv=%ub, b_tbs_matched=%ub"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_SPS_NEWTX_COLLISION_WITH_TCRNTI EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: sps newtx grant: collision with tc-rnti"
+warn (non_smp) EMAC_UL_HARQ_WARN___TX_MODE_ASYNC_GRANT_COLLISION_WITH_HARQ EMAC_WARN_H "[EMAC][UL-HARQ][TM] discard grant: async grant: collision with online harq"
+
+
+// ============================================================================================================
+// UL HARQ - IM Buffer [IM]
+// ============================================================================================================
+
+// Level 1
+info EMAC_UL_HARQ_LOG___IM_BUFFER_RESET EMAC_LV1_H "[EMAC][UL-HARQ][IM] reset"
+info (non_smp) EMAC_UL_HARQ_LOG___IM_BUFFER_RENEW EMAC_LV1_H "[EMAC][UL-HARQ][IM] renew: ul_cc_idx=%ub, harq_id=%ub, im_buffer_idx=%ub, lost_im_buffer_user=%xl"
+info (non_smp) EMAC_UL_HARQ_LOG___IM_BUFFER_GET_MSG3_BUFFER EMAC_LV1_H "[EMAC][UL-HARQ][IM] msg3_harq_user=%xl, msg3_tbs=%ud, b_reconstruct_msg3=%ub"
+info (non_smp) EMAC_LOG_IM_BUFFER_GET_START_ADDRESS EMAC_LV1_H "[EMAC][UL-HARQ][IM] Get im_buffer_addr: im_buffer_idx=%ul, mux_req=%ub, base_addr=%xl, shift_addr = %xl"
+info (non_smp) EMAC_LOG_IM_BUFFER_ROLLBACK_START_ADDRESS EMAC_LV1_H "[EMAC][UL-HARQ][IM] Rollback im_buffer_addr: im_buffer_idx=%ul"
+
+// Level 2
+
+// Level 3
+
+// Others
+warn (non_smp) EMAC_UL_HARQ_WARN___IM_BUFFER_INVALID_MSG3_HARQ_USER EMAC_WARN_H "[EMAC][UL-HARQ][IM] invalid msg3 harq user"
+
+
+// ============================================================================================================
+// Gemini
+// ============================================================================================================
+
+// Level 1
+info EMAC_GEMINI_LOG___GEMINI_INIT EMAC_LV1_H "[EMAC][Gemini] initialization: retx_mode=%ub"
+info (non_smp) EMAC_GEMINI_LOG___GEMINI_RETX_MODE_CHANGE EMAC_LV1_H "[EMAC][Gemini] change retx_mode=%ub"
+info (non_smp) EMAC_GEMINI_LOG___GEMINI_SKIP_TX EMAC_LV1_H "[EMAC][Gemini] tx not allowed: tx_skip_reason=%ub"
+
+info (non_smp) EMAC_GEMINI_LOG___GEMINI_EXACT_GAP_START EMAC_LV1_H "[EMAC][Gemini] exact gap start: gemini_gap_rx_start_time_32=%ul"
+info (non_smp) EMAC_GEMINI_LOG___GEMINI_EXACT_GAP_END EMAC_LV1_H "[EMAC][Gemini] exact gap end: gemini_gap_rx_end_time_32=%ul"
+info (non_smp) EMAC_GEMINI_LOG___GEMINI_PREDICTED_GAP_INFO EMAC_LV1_H "[EMAC][Gemini] predicted gap info: gap0_start_time_32=%ul, gap0_len=%ub, gap1_start_time_32=%ul, gap1_len=%ub"
+
+info (non_smp) EMAC_LOG_CFG_RRC_RESET_VIRTUAL_CONNECTED_ENTER EMAC_LV1_H "[EMAC][CFG] EMAC reset cause=VIRTUAL_CONNECTED_ENTER"
+info (non_smp) EMAC_LOG_CFG_RRC_RESET_VIRTUAL_CONNECTED_LEAVE_FAIL EMAC_LV1_H "[EMAC][CFG] EMAC reset cause=VIRTUAL_CONNECTED_LEAVE_FAIL"
+// Level 2
+
+// Level 3
+
+// Others
+
+
+// ============================================================================================================
+// DL HARQ
+// ============================================================================================================
+
+// Level 1
+info EMAC_DL_HARQ_LOG___INIT EMAC_LV1_H "[EMAC][DL-HARQ] initialization"
+
+info (non_smp) EMAC_DL_HARQ_LOG___CRC_TARGET_ORIGINAL_STATE EMAC_LV1_H "[EMAC][DL-HARQ][CRC] original state: cc_idx=%ud:4, dl_harq_id=%ud:4, status=%xd:2, tb_crc_0=%ud:2, tb_crc_1=%ud:2%pd:2"
+
+info (non_smp) EMAC_DL_HARQ_LOG___DCI_TARGET_HARQ_ORIGINAL_STATE EMAC_LV1_H "[EMAC][DL-HARQ][DCI] original state: cc_idx=%ud:4, dl_harq_id=%ud:4, status=%xd:2, tb_crc_0=%ud:2, tb_crc_1=%ud:2%pd:2"
+info (non_smp) EMAC_DL_HARQ_LOG___DCI_TB_FLUSH_REQUESTED EMAC_LV1_H "[EMAC][DL-HARQ][DCI] tb flush requested: b_different_rnti=%ub, b_spsc_rnti=%ub"
+
+info (non_smp) EMAC_DL_HARQ_LOG___FALSE_ALARM_TB_DETECTED EMAC_LV1_H "[EMAC][DL-HARQ] false alarm tb detected: cc_idx=%ub, harq_id=%ub, tb_id=%ub"
+
+info (non_smp) EMAC_DL_HARQ_LOG___CLOSE_TB EMAC_LV1_H "[EMAC][DL-HARQ] close tb: cc_idx=%ub, harq_id=%ub, tb_id=%ub"
+info (non_smp) EMAC_DL_HARQ_LOG___CLOSE_HARQ EMAC_LV1_H "[EMAC][DL-HARQ] close harq: cc_idx=%ub, harq_id=%ub"
+info (non_smp) EMAC_DL_HARQ_LOG___CLOSE_HARQ_ALL EMAC_LV1_H "[EMAC][DL-HARQ] close harq all"
+info (non_smp) EMAC_DL_HARQ_LOG___CLOSE_HARQ_SCELL EMAC_LV1_H "[EMAC][DL-HARQ] close harq scell: cc_idx=%ub"
+
+// Level 2
+
+// Level 3
+
+// Others
+warn (non_smp) EMAC_DL_HARQ_WARN___CRC_TARGET_INVALID EMAC_WARN_H "[EMAC][DL-HARQ][CRC] invalid for target dci: tb_id=%ub"
+
+
+// ============================================================================================================
+// SPS
+// ============================================================================================================
+
+// Level 1
+info EMAC_SPS_LOG___INIT EMAC_LV1_H "[EMAC][SPS] initialization"
+info (non_smp) EMAC_SPS_LOG___DEACTIVATE EMAC_LV1_H "[EMAC][SPS] deactivate ul/dl sps"
+
+info (non_smp) EMAC_SPS_LOG___DL_RELEASE EMAC_LV1_H "[EMAC][SPS][DL-HARQ] release"
+info (non_smp) EMAC_SPS_LOG___DL_ACTIVATION EMAC_LV1_H "[EMAC][SPS][DL-HARQ] activation: current_dl_sps_abs_tx_time_32=%ul, next_dl_sps_abs_tx_time_32=%ul, dl_harq_id=%ub"
+info (non_smp) EMAC_SPS_LOG___DL_UPDATE_NEXT EMAC_LV1_H "[EMAC][SPS][DL-HARQ] update next: next_dl_sps_abs_tx_time_32=%ul, dl_harq_id=%ub"
+
+info (non_smp) EMAC_SPS_LOG___UL_RELEASE EMAC_LV1_H "[EMAC][SPS][UL-HARQ] release"
+info (non_smp) EMAC_SPS_LOG___UL_ACTIVATION EMAC_LV1_H "[EMAC][SPS][UL-HARQ] activation: next_ul_sps_abs_tx_time_32=%ul, ul_sps_two_interval_offset=%ub"
+info (non_smp) EMAC_SPS_LOG___UL_UPDATE_NEXT EMAC_LV1_H "[EMAC][SPS][UL-HARQ] update next: next_ul_sps_abs_tx_time_32=%ul, ul_sps_n_toggle=%ub"
+info (non_smp) EMAC_SPS_LOG___UL_GRANT_INPUT EMAC_LV1_H "[EMAC][SPS][UL-HARQ] <uldci: t-0, ul_cc_idx=0, type=%ub, ndi=%ub, rv=%ub, tbs=%ud, k=%ul>"
+
+info (non_smp) EMAC_SPS_LOG___UL_MONITOR_MUX_REQ EMAC_LV1_H "[EMAC][SPS][UL-HARQ] monitor mux: newtx"
+info (non_smp) EMAC_SPS_LOG___UL_MONITOR_MUX_RESULTS EMAC_LV1_H "[EMAC][SPS][UL-HARQ] monitor mux: result: b_ul_sps_active=%ub, b_mux_with_sdu=%ub"
+
+info (non_smp) EMAC_SPS_LOG___UL_GRANT_PHICH_RX_TIME_INFO EMAC_LV1_H "[EMAC][SPS][UL-HARQ] grant phich rx info: pdcch_num=%ub, time_to_phich=%ub, time_to_pdcch[0]=%ub, time_to_pdcch[1]=%ub"
+
+info (non_smp) EMAC_SPS_LOG___UL_IMPLICIT_RELEASE_REACHED EMAC_LV1_H "[EMAC][SPS][UL-HARQ] implicit release reached"
+
+info (non_smp) EMAC_SPS_LOG___UL_CONFIRMATION_TRIGGER EMAC_LV1_H "[EMAC][SPS][UL-HARQ] SPS Confirmation is triggered"
+
+// Level 2
+
+// Level 3
+
+// Others
+warn (non_smp) EMAC_SPS_WARN___DL_DROP_COMMAND EMAC_WARN_H "[EMAC][SPS][DL-HARQ] drop dl sps command: sps_cmd=%xb"
+warn (non_smp) EMAC_SPS_WARN___UL_DROP_COMMAND EMAC_WARN_H "[EMAC][SPS][UL-HARQ] drop ul sps command: sps_cmd=%xb"
+
+// ============================================================================================================
+// LATRED
+// ============================================================================================================
+
+// Level 1
+info (non_smp) EMAC_LATRED_LOG___SKIP_TX_BUFFER_INFO EMAC_LV1_H "[EMAC][LATRED][SKIP] Buffer INFO: BSR_size=%ul, PHR_size=%ul, Buffer_size=%ul"
+info (non_smp) EMAC_LATRED_LOG___SKIP_TX_CC_IDX EMAC_LV1_H "[EMAC][LATRED][SKIP] skip cc_idx: %xb"
+
+// Level 2
+
+// Level 3
+
+// Others
+
+
+// ============================================================================================================
+// SCELL
+// ============================================================================================================
+info (non_smp) EMAC_LOG_SCELL_ENQUEUE_EL1CMD EMAC_LV1_H "[EMAC][SCELL] enqueue el1c cmd w_idx %d, r_idx %d"
+info (non_smp) EMAC_LOG_SCELL_DEQUEUE_EL1CMD EMAC_LV1_H "[EMAC][SCELL] dequeue el1c cmd w_idx %d, r_idx %d"
+info (non_smp) EMAC_LOG_SCELL_DROP_DUP_EL1CMD EMAC_LV1_H "[EMAC][SCELL] drop duplicate el1c cmd type %d, cc_idx %d"
+
+// ============================================================================================================
+// SR
+// ============================================================================================================
+warn (non_smp) EMAC_LOG_SR_NO_TX EMAC_LV1_H "[EMAC][SR] SR no tx due to gap, reset count/tx_time"
+warn (non_smp) EMAC_LOG_SR_CFG_TA_EXIPIRED EMAC_LV1_H "[EMAC][SR] SR resource cfg during TA timer expired! action=%ub (0: Wait until SR trigger, 1: Notify ERRC TA expired)"
+info (non_smp) EMAC_LOG_SR_NEXT_SR_OCCASION_INFO EMAC_LV1_H "[EMAC][SR][SLP] next sr occasion info, next_tick_time=%ul, next_pdcch_time=%ul, sched_result_bmp=%ud"
+warn (non_smp) EMAC_LOG_SR_UNEXPECTED_SLP_TX_STATUS EMAC_LV1_H "[EMAC][SR][SLP] unexpected slp and tx_status=%ub (0: tx forbidden in sleep, 1: pdcch off after sr tx, 2: tx forbidden in wakingup)"
+info EMAC_ERT_LOG_SR_NEXT_SR_OCCASION_INFO EMAC_LV1_H "[EMAC][ERT][SR][SLP] next sr occasion info, delay_time=%ud, next_tick_time=%ul, next_pdcch_time=%ul"
+info EMAC_ERT_LOG_SR_MEAS_CONFLICT EMAC_LV1_H "[EMAC][ERT][SR] SR occasion in meas gap, meas_pattern=%ub, meas_offset=%ub, SR_period=%ub, SR_offset=%ub"
+
+// ============================================================================================================
+// RA
+// ============================================================================================================
+info EMAC_RA_LOG_INIT EMAC_LV1_H "[EMAC][RA] init"
+info (non_smp) EMAC_RA_LOG_RESET EMAC_LV1_H "[EMAC][RA][CFG] <state = NO_RA> RA reset"
+
+info (non_smp) EMAC_RA_LOG_TRIG_FAIL EMAC_LV1_H "[EMAC][RA] %Memac_ra_event_e trigger fail, collides with IDC=%b"
+info (non_smp) EMAC_RA_LOG_TRIG EMAC_LV1_H "[EMAC][RA] %Memac_ra_event_e trigger, current trigger event=%Memac_ra_event_e"
+
+info (non_smp) EMAC_RA_LOG_GAP_STOP_SEND EMAC_LV1_H "[EMAC][RA] <state = WAIT_GAP_STOP> send GAP_STOP_REQ"
+info (non_smp) EMAC_RA_LOG_GAP_STOP_RCV EMAC_LV1_H "[EMAC][RA] <state = WAIT_PREAMBLE_TX> rcv GAP_STOP_CNF"
+info (non_smp) EMAC_RA_LOG_GAP_RESUME_RCV EMAC_LV1_H "[EMAC][RA] <state = NO_RA> rcv GAP_RESUME_CNF"
+
+info (non_smp) EMAC_RA_LOG_PREAM_TRIG_NOT_READY EMAC_LV2_H "[EMAC][RA] trigger event not ready yet"
+info (non_smp) EMAC_RA_LOG_PREAM_TX_NOT_READY EMAC_LV2_H "[EMAC][RA] TX not ready yet due to=%d (0: earliest_tx_avail_time, 1: sleep_status)"
+info (non_smp) EMAC_RA_LOG_PREAM_CB_RAPID_SELECT EMAC_LV1_H "[EMAC][RA] msg3_valid=%d, group_b=%d, pathloss=%d"
+info (non_smp) EMAC_RA_LOG_PREAM_GROUPB_SZ_0 EMAC_LV3_H "[EMAC][RA] preamble group b size = 0, use group a"
+info (non_smp) EMAC_RA_LOG_PREAM_POW_CHK_PASS EMAC_LV3_H "[EMAC][RA] pathloss (%d) < pmax (%b) - init_pow (%b) - delta_msg3 (%b) - pow_oft_b (%b)"
+info (non_smp) EMAC_RA_LOG_PREAM_POW_CHK_FAIL EMAC_LV3_H "[EMAC][RA] pathloss (%d) >= pmax (%b) - init_pow (%b) - delta_msg3 (%b) - pow_oft_b (%b), use group a"
+info (non_smp) EMAC_RA_LOG_PREAM_POTENTIAL_MSG_SZ EMAC_LV3_H "[EMAC][RA] msg_sz_group_a=%b, potential_msg_sz=%l"
+info (non_smp) EMAC_RA_LOG_PREAM_VALID_INFO EMAC_LV1_H "[EMAC][RA] preamble valid: rapid=%b, prefer_tx_time=%l, prach_tx_time=%l"
+
+info (non_smp) EMAC_RA_LOG_RAR_RCV_DCI EMAC_LV1_H "[EMAC][RA] rcv %ubth DCI for ra-rnti, update rar_delay_time=%ul"
+info (non_smp) EMAC_RA_LOG_RAR_RCV_DCI_OUT_WND EMAC_LV1_H "[EMAC][RA][WARN] rcv %ubth DCI for ra-rnti at %ul outside RAR WND"
+info (non_smp) EMAC_RA_LOG_RAR_MISMATCH EMAC_LV1_H "[EMAC][RA] RAR mismatch, misatch_rapid=%ub"
+info (non_smp) EMAC_RA_LOG_RAR_TB_RCV EMAC_LV3_H "[EMAC][RA] rcv RAR, match=%b, at subframe=%ub, abs_time=%ul"
+info (non_smp) EMAC_RA_LOG_CR_RCV_TCRNTI_DCI EMAC_LV1_H "[EMAC][RA] rcv tc-rnti DL DCI, update cr_delay_time=%l"
+
+info (non_smp) EMAC_RA_LOG_MAX_POW_REACHED EMAC_LV1_H "[EMAC][RA][WARN] preamble max tx power reached"
+error (non_smp) EMAC_RA_LOG_RAR_TIMING_FAIL EMAC_LV1_H "[EMAC][RA][ERROR] RAR too late for acsi el1d rx timing"
+error (non_smp) EMAC_RA_LOG_TCRNTI_TIMING_FAIL EMAC_LV1_H "[EMAC][RA][ERROR] tc-rnti too late for ack add el1d tx timing"
+info (non_smp) EMAC_RA_LOG_RCV_TCRNTI_CR_CNF EMAC_LV3_H "[EMAC][RA] rcv tc-rnti CR: result=%b at %l"
+info (non_smp) EMAC_RA_LOG_RCV_RA_RESTART EMAC_LV1_H "[EMAC][RA] <state = WAIT_PREAMBLE_TX> RA restart"
+info (non_smp) EMAC_RA_LOG_RA_ABORT EMAC_LV1_H "[EMAC][RA][WARN] <state = WAIT_GAP_RESUME> RA abort (directly clear RA status)"
+info (non_smp) EMAC_RA_LOG_TA_TIMEOUT_PCELL_RETRY EMAC_LV1_H "[EMAC][RA][WARN] <state = WAIT_CR> TA Timeout, RA retry on PCell (leave WAIT_MSG3 or WAIT_CR)"
+
+warn (non_smp) EMAC_RA_LOG_PDCCH_ORDER_FOR_TA_RUNNING EMAC_LV1_H "[EMAC][RA][WARN] rcv PDCCH order for TA timer running, ul_cc_idx=%ub"
+
+// ============================================================================================================
+// IDC
+// ============================================================================================================
+info EMAC_LOG_IDC_INIT EMAC_LV1_H "[EMAC][IDC] init"
+info (non_smp) EMAC_LOG_IDC_IDC_STATE_UPDATE EMAC_LV1_H "[EMAC][IDC] IDC state update: ul_cc_idx=%ub, state=%Memac_idc_state_enum"
+warn (non_smp) EMAC_LOG_IDC_FORCE_REGULAR_BSR_TRIGGER EMAC_LV1_H "[EMAC][IDC][BSR] IDC forces regular BSR trigger"
+warn (non_smp) EMAC_LOG_IDC_TDM_IDC_IND_IGNORE EMAC_LV1_H "[EMAC][IDC] ignore IDC ind info due to emac reset or sch close"
+info (non_smp) EMAC_LOG_IDC_TDM_IDC_IND_INFO EMAC_LV1_H "[EMAC][IDC] rcv IDC ind info, cc_idx=%ub, start_time=%ul, lead_time=%ul, duration=%ul"
+
+// ============================================================================================================
+// VOLTE
+// ============================================================================================================
+info EMAC_ERT_LOG_SR_VOLTE_MODE EMAC_LV1_H "[EMAC][VOLTE][SR] volte prediction mode: mode=%ub (0: silence mode, 1: talk mode, 2: sid first mode, 3: invalid mode)"
+info EMAC_ERT_LOG_SR_VOLTE_RB_STATUS EMAC_LV1_H "[EMAC][VOLTE][SR] volte rb_idx=%ub, config=%ub (0: activation, 1: deactivation, 2: reactivation)"
+info EMAC_ERT_LOG_SR_VOLTE_PREDICTION EMAC_LV1_H "[EMAC][VOLTE][SR] volte prediction: \npredicted air_abs_time=%ul, \npredicted_next_volte_time=%ul, \ntype=%ub:1 (0: data, 1: mode change notify), \nhit=%ub:1, \nvolte_mode=%ub:2, \nis_sent_to_txlisr=%ub:1%pb:3"
+
+// ============================================================================================================
+// PHR
+// ============================================================================================================
+info (non_smp) EMAC_LOG_TRIGGERD_BY_CONFIG EMAC_LV1_H "[EMAC][PHR] PHR triggered by reconfig or scell activate"
+info (non_smp) EMAC_LOG_TRIGGERD_BY_PERIOD_TIMER EMAC_LV1_H "[EMAC][PHR] PHR triggered by periodic timer"
+info (non_smp) EMAC_LOG_TRIGGERD_BY_PATHLOSS EMAC_LV1_H "[EMAC][PHR] PHR triggered by pathloss ul_cc_idx=%ub, previous pathloss=%b, current pathloss=%b"
+info (non_smp) EMAC_LOG_TRIGGERD_BY_MPR EMAC_LV1_H "[EMAC][PHR] PHR triggered by MPR ul_cc_idx=%ub, previous MPR=%b, current MPR=%b"
+info (non_smp) EMAC_LOG_TRIGGERD_IF_PUCCH_BY_MPR EMAC_LV1_H "[EMAC][PHR] PHR triggered by MPR if has PUCCH ul_cc_idx=%ub, previous MPR=%b, current MPR=%b"
+info (non_smp) EMAC_LOG_PHR_RES EMAC_LV1_H "[EMAC][PHR] PHR response: length=%ub, has pucch=%ub"
+
+// ============================================================================================================
+// DRX
+// ============================================================================================================
+info EMAC_DRX_LOG_INIT_RESET EMAC_LV1_H "[EMAC][DRX] situation: initialization or reset"
+info (non_smp) EMAC_DRX_LOG_NON_RESET EMAC_LV1_H "[EMAC][DRX] situation: non reset"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_1CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_2CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_3CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, rtt2_status=%xd, retx2_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_4CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, rtt2_status=%xd, retx2_status=%xd, rtt3_status=%xd, retx3_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_5CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, rtt2_status=%xd, retx2_status=%xd, rtt3_status=%xd, retx3_status=%xd, rtt4_status=%xd, retx4_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_6CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, rtt2_status=%xd, retx2_status=%xd, rtt3_status=%xd, retx3_status=%xd, rtt4_status=%xd, retx4_status=%xd, rtt5_status=%xd, retx5_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_7CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, rtt2_status=%xd, retx2_status=%xd, rtt3_status=%xd, retx3_status=%xd, rtt4_status=%xd, retx4_status=%xd, rtt5_status=%xd, retx5_status=%xd, rtt6_status=%xd, retx6_status=%xd"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_7CC_2 EMAC_LV1_H "[EMAC][DRX] ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_8CC EMAC_LV1_H "[EMAC][DRX] tti retx status: rtt0_status=%xd, retx0_status=%xd, rtt1_status=%xd, retx1_status=%xd, rtt2_status=%xd, retx2_status=%xd, rtt3_status=%xd, retx3_status=%xd, rtt4_status=%xd, retx4_status=%xd, rtt5_status=%xd, retx5_status=%xd, rtt6_status=%xd, retx6_status=%xd"
+info (non_smp) EMAC_DRX_LOG_TTI_RETX_TMR_STATUS_8CC_2 EMAC_LV1_H "[EMAC][DRX] rtt7_status=%xd, retx7_status=%xd, ear_fut_retx_start_time=%ul, n1_retx_tmr_flag=%ub, n2_retx_tmr_flag=%ub"
+info (non_smp) EMAC_DRX_LOG_UL_RETX_TMR_INFO EMAC_LV1_H "[EMAC][DRX] ul retx tmr info: ul_cc_idx=%ub, harq_id=%ub, start_time=%ul, expired_time=%ul"
+warn (non_smp) EMAC_DRX_LOG_MIB_INVALID EMAC_LV1_H "[EMAC][DRX] mib invalid"
+info (non_smp) EMAC_DRX_LOG_CYC_CHANGE_NEXT_ONDU_INFO EMAC_LV1_H "[EMAC][DRX] (cycle change)ondu tmr: start_time=%ul and expired_time=%ul, next ondu tmr: start_time=%ul and expired_time=%ul, cur_cycle=%Memac_drx_cycle_type_e, next_predict_cycle=%Memac_drx_cycle_type_e"
+info (non_smp) EMAC_DRX_LOG_SHORT_CYC_TMR_RESET_TMR_END EMAC_LV1_H "[EMAC][DRX] short cycle tmr reset: short cycle tmr end"
+info (non_smp) EMAC_DRX_LOG_SHORT_CYC_TMR_RESET_LONG_DRX_CMD EMAC_LV1_H "[EMAC][DRX] short cycle tmr reset: rcv long drx cmd"
+warn (non_smp) EMAC_DRX_LOG_TURN_OFF_PAST_SHORT_CYCLE_ONDU_TMR_LONG_DRX_CMD EMAC_LV1_H "[EMAC][DRX] turn off past short cycle ondu tmr: rcv long drx cmd"
+info (non_smp) EMAC_DRX_LOG_N5_DRX_STATUS_PREDICTION EMAC_LV1_H "[EMAC][DRX] n5 drx status prediction: n5_time=%ul, n5_status_bmp=%ub, rest_active_event_code=%ub"
+info (non_smp) EMAC_DRX_LOG_DCI_RCV_NEW_CRNTI_DCI_FOR_CF_RAR EMAC_LV1_H "[EMAC][DRX] rcv new c-rnti dci for cf rar: new c-rnti dci rcv_time=%ul, cf rar rcv_time=%ul"
+warn (non_smp) EMAC_DRX_LOG_DCI_RCV_NEW_CRNTI_DCI_BEFORE_CF_RAR_DECODED EMAC_LV1_H "[EMAC][DRX] rcv new c-rnti dci before cf rar is decoded: new c-rnti dci rcv_time=%ul, cf rar rcv_time=%ul"
+info (non_smp) EMAC_DRX_LOG_N5_DRX_STATUS_UPDATE_CF_RAR EMAC_LV1_H "[EMAC][DRX] n5 drx status update (cf rar): n5_time=%ul, n5_status_bmp=%ub"
+info (non_smp) EMAC_DRX_LOG_N5_DRX_STATUS_UPDATE_DRX_CMD EMAC_LV1_H "[EMAC][DRX] n5 drx status update (drx/long drx cmd): n5_time=%ul, n5_status_bmp=%ub"
+info (non_smp) EMAC_DRX_LOG_DRX_CMD_ONDU_TMR_STOP EMAC_LV1_H "[EMAC][DRX] drx/long drx cmd stops ondu tmr"
+info (non_smp) EMAC_DRX_LOG_DRX_CMD_DRX_INACT_TMR_STOP EMAC_LV1_H "[EMAC][DRX] drx/long drx cmd stops drx inact tmr"
+info (non_smp) EMAC_DRX_LOG_DRX_CMD_DRX_SHORT_CYC_TMR_START EMAC_LV1_H "[EMAC][DRX] drx cmd starts short cycle tmr: start_time=%ul, expired_time=%ul"
+info (non_smp) EMAC_DRX_LOG_CQI_SRS_TX_ADMIN EMAC_LV1_H "[EMAC][DRX] tx time=%ul: cqi_tx_admin=%ub, type0-srs_tx_admin=%ub"
+warn (non_smp) EMAC_DRX_LOG_NEXT_ONDU_CONSIDERING_INACT_SHORT_TMR_EXPIRY EMAC_LV1_H "[EMAC][DRX] next ondu info considering drx inact/short cycle tmr: next ondu start_time=%ul and expired_time=%ul"
+info (non_smp) EMAC_DRX_LOG_DRX_DISABLE_POST_PROC EMAC_LV1_H "[EMAC][DRX] drx disable post proc: status=%ub (0: enable, 1: disable)"
+info (non_smp) EMAC_DRX_LOG_PSF_MAPPING_TBL_UPDATE_DUMP EMAC_LV1_H "[EMAC][DRX] dump psf mapping table %ub (0: ondu, 1: retx, 2: inact, 3: ul_retx)=%3ud %3ud %3ud %3ud %3ud %3ud %3ud %3ud %3ud %3ud"
+
+warn (non_smp) EMAC_DRX_LOG_DL_WO_PDCCH_IND EMAC_LV1_H "[EMAC][DRX][WARN] dl without pdsch ind: rcv_abs_time=%ul"
+
+info (non_smp) EMAC_DRX_LOG_CHK_DRX_CYCLE_NTF EMAC_LV3_H "[EMAC][DRX] DRX_CYCLE_NTF: start_time=%ul, ondu_len=%ud, cycle_len=%ud, is_cycle_changed=%ub"
+
+// ============================================================================================================
+// SLP
+// ============================================================================================================
+info EMAC_SLP_LOG_SITUATION EMAC_LV1_H "[EMAC][SLP] situation: %ub (0: initialization, 1: reset, 2: non reset, 3: drx disable)"
+info (non_smp) EMAC_SLP_LOG_SLP_LAST_PDCCH_ON_TIME EMAC_LV1_H "[EMAC][SLP] last pdcch_on_time=%ul"
+info (non_smp) EMAC_SLP_LOG_TICK_OPERATION EMAC_LV1_H "[EMAC][SLP] txlisr tick operation: status=%ub (0: lock, 1: unlock), errc_protocol_idx=%ub"
+info (non_smp) EMAC_SLP_LOG_SLP_STATUS_CHANGE_TO_AWAKE EMAC_LV1_H "[EMAC][SLP] slp status changes to EMAC_SLP_STATUS_AWAKE: reason=%ub (0: normal wakeup, 1: dynamic wakeup, 2: force awake)"
+info (non_smp) EMAC_SLP_LOG_SLP_STATUS_CHANGE_TO_TX_READY EMAC_LV1_H "[EMAC][SLP] slp status changes to EMAC_SLP_STATUS_TX_READY"
+info (non_smp) EMAC_SLP_LOG_SLP_STATUS_CHANGE_TO_WAKINGUP EMAC_LV1_H "[EMAC][SLP] slp status changes to EMAC_SLP_STATUS_WAKINGUP"
+info (non_smp) EMAC_SLP_LOG_SLP_STATUS_PREDICT_RESULT EMAC_LV1_H "[EMAC][SLP] slp status changes to %Memac_slp_status_e from EMAC_SLP_STATUS_WAITING_SLEEP_WITH_PREDICT_MSG"
+info (non_smp) EMAC_SLP_LOG_NEXT_WAKEUP_TIME_INFO EMAC_LV1_H "[EMAC][SLP] next wakeup time info: \ntick_updated=%ub:1, \npredicted=%ub:1, \nnext2_off=%ub:1, \ncycle_type=%ub:1%pb:4, \ntick_awake_type=%Memac_slp_awake_type_e, next_tick_time=%ul, \npdcch_awake_type=%Memac_slp_awake_type_e, next_pdcch_time=%ul \n(note: <drx_tick_awake_type=%Memac_slp_awake_type_e, drx_tick_awake_time=%ul, drx_pdcch_awake_type=%Memac_slp_awake_type_e, drx_pdcch_awake_time=%ul> <ul_harq_tick_awake_type=%Memac_slp_awake_type_e, ul_harq_tick_awake_time=%ul, ul_harq_pdcch_awake_type=%Memac_slp_awake_type_e, ul_harq_pdcch_awake_time=%ul> <sr_tick_awake_time=%ul, sr_pdcch_awake_time=%ul>)"
+info (non_smp) EMAC_SLP_LOG_NEXT_SPS_WAKEUP_TIME_INFO EMAC_LV1_H "[EMAC][SLP][SPS] (note: <sps_tick_awake_time=%ul, sps_pdcch_awake_time=%ul>)"
+info (non_smp) EMAC_SLP_LOG_RCV_DYNAMIC_REQ EMAC_LV1_H "[EMAC][SLP] rcv dynamic_wakeup_req"
+info (non_smp) EMAC_SLP_LOG_RCV_DYNAMIC_TX_READY EMAC_LV1_H "[EMAC][SLP] rcv dynamic_wakeup_tx_ready: dynamic_wakeup_tick_time=%ul"
+info (non_smp) EMAC_SLP_LOG_RCV_DYNAMIC_CNF EMAC_LV1_H "[EMAC][SLP] rcv dynamic_wakeup_cnf: dynamic_wakeup_pdcch_time=%ul"
+warn (non_smp) EMAC_SLP_LOG_UNEXPECTED_SLEEP_STATUS_DURING_AWAKE EMAC_LV1_H "[EMAC][SLP][WARN] unexpected EMAC_SLP_STATUS_SLEEP during awake"
+warn (non_smp) EMAC_SLP_LOG_UNEXPECTED_DCI_DURING_SLEEP EMAC_LV1_H "[EMAC][SLP][WARN] unexpected dci during EMAC_SLP_STATUS_SLEEP"
+warn (non_smp) EMAC_SLP_LOG_UL_HARQ_SPS_CHANGE_PDCCH_TIME_DUR_SLEEP EMAC_LV1_H "[EMAC][SLP][WARN] pdcch time is changed during sleep: source=%ub (0: ul harq, 1: sps), original_tick_time=%ul, original_pdcch_time=%ul"
+
+info EMAC_ERT_SLP_LOG_INIT EMAC_LV1_H "[EMAC][ERT][SLP] initialization"
+info EMAC_ERT_SLP_LOG_SLP_STATUS_CHANGE_TO_SLEEP EMAC_LV1_H "[EMAC][ERT][SLP] slp status changes to EMAC_ERT_SLP_STATUS_SLEEP: cur_os_tick=%ul, air_abs_time=%ul, cell_time_cnt=%ud"
+info EMAC_ERT_SLP_LOG_RCV_DYNAMIC_WAKEUP_REQ EMAC_LV1_H "[EMAC][ERT][SLP] rcv dynamic wakeup req: module=%ub (0: without wakeup time, 1: with wakeup time)"
+info EMAC_ERT_SLP_LOG_CUR_TIME_INFO_PREDICT EMAC_LV1_H "[EMAC][ERT][SLP] timer prediction: cur_os_tick=%ul, predicted air_abs_time=%ul, predicted cell_time_cnt=%ud"
+warn EMAC_ERT_SLP_LOG_DYNAMIC_WAKEUP_DROP EMAC_LV1_H "[EMAC][ERT][SLP] drop dynamic wakeup: reason=%ub (0: no need, 1: not in EMAC_ERT_SLP_STATUS_SLEEP, 2: close to next_pdcch_time, 3: sch is closed or mac reset)"
+info EMAC_ERT_SLP_LOG_SLP_STATUS_CHANGE_TO_AWAKE EMAC_LV1_H "[EMAC][ERT][SLP] slp status changes to EMAC_ERT_SLP_STATUS_AWAKE"
+info EMAC_ERT_SLP_LOG_UPPER_LAYER_DYNAMIC_WAKEUP_CTRL EMAC_LV1_H "[EMAC][ERT][SLP] upper layer dynamic wakeup operation: status=%ub (0: enable, 1: disable)"
+info EMAC_ERT_SLP_LOG_SEND_HOST_DATA_REQ EMAC_LV1_H "[EMAC][ERT][SLP] send host data request: cnt=%ub, msg_sent_time=%ul, dynamic_wakeup_tick_time=%ul, dynamic_wakeup_pdcch_time=%ul"
+info EMAC_ERT_SLP_LOG_RCV_HOST_DATA_READY EMAC_LV1_H "[EMAC][ERT][SLP] rcv host data ready"
+info EMAC_ERT_SLP_LOG_RCV_HOST_DATA_CNF EMAC_LV1_H "[EMAC][ERT][SLP] rcv host data cnf"
+warn EMAC_ERT_SLP_LOG_ENQUEUE_HOST_DATA_REQ EMAC_LV1_H "[EMAC][ERT][SLP] enqueue host data req"
+
+info EMAC_ERT_SLP_LOG_TICK_OPERATION EMAC_LV1_H "[EMAC][ERT][SLP] ert tick operation: status=%ub (0: lock, 1: unlock)"
+
+// ============================================================================================================
+// EMUX
+// ============================================================================================================
+// WARN
+warn EMUX_WAR___PRINT_E EMAC_WARN_H "[EMAC][EMUX][WARN] %Memux_log_e"
+
+// Error
+error EMUX_ERR___PRINT_E EMAC_ERROR_H "[EMAC][EMUX][ERROR] %Memux_log_e"
+
+// Debug
+info EMUX_DBG___PRINT_E1_I4 EMAC_WARN_H "[EMAC][EMUX][DBG] %Memux_log_e %l %l %l %l"
+
+// General
+info EMUX_LOG___PRINT_E EMAC_LV1_H "[EMAC][EMUX][LOG] %Memux_log_e"
+
+// Read MUX REQ
+info EMUX_LOG___PROCESS EMAC_LV2_H "[EMAC][EMUX][MR] MUX_REQ: cc_idx=%ub, need_lcp=%Mkal_bool, need_gen_front_tb=%Mkal_bool, need_mux=%Mkal_bool"
+
+// Init LCP (Sync Buffer Status)
+info EMUX_LOG___SYNC_BUFF_STATUS EMAC_LV2_H "[EMAC][EMUX][LCP] Sync buff status: [IN] lcg_buf_inc_opt=%Memux_rb_group_e, lcp_opt=%Memux_rb_group_e, [OUT] lcg_buf_num=%ub"
+
+
+
+info EMUX_LOG___AFTER_MAC_LCP_B EMAC_LV2_H "[EMAC][EMUX][LCP] After mac lcp: c-rnti=%Memux_crnti_status_e, bsr=%Memux_bsr_status_e(%Memux_bsr_format_e), phr=%Memux_phr_status_e, ccch=%Memux_ccch_status_e"
+info EMUX_LOG___AFTER_MAC_LCP_C EMAC_LV2_H "[EMAC][EMUX][LCP] After mac lcp: r_tbs=%ud, last_shdr_type=%Memux_last_shdr_type_e, last_shdr_format=%Memux_last_shdr_format_e"
+
+info EMUX_LOG___AFTER_RLC_LCP_B EMAC_LV2_H "[EMAC][EMUX][LCP] After rlc lcp: bsr=%Memux_bsr_status_e(%Memux_bsr_format_e), pad=%Memux_pad_status_e, dxch=%Memux_dxch_status_e, post_pad_len=%ud"
+info EMUX_LOG___AFTER_RLC_LCP_C EMAC_LV2_H "[EMAC][EMUX][LCP] After rlc lcp: r_tbs=%ud, last_shdr_type=%Memux_last_shdr_type_e, last_shdr_format=%Memux_last_shdr_format_e"
+
+
+warn EMUX_WAR___RAR_GRANT_TOO_SMALL EMAC_WARN_H "[EMAC][EMUX][LCP][WARN] RAR grant is too small(<7bytes) for CCCH: r_tbs=%ud"
+
+
+// Gen front TB
+info EMUX_LOG___MUX_BUF_2 EMAC_LV2_H "[EMAC][EMUX][TB] %xb %xb %xb %xb"
+info EMUX_LOG___MUX_BUF_3 EMAC_LV3_H "[EMAC][EMUX][TB] %xb %xb %xb %xb"
+info EMUX_LOG___MUX_BUF_4 EMAC_LV3_H "[EMAC][EMUX][TB] %xb %xb %xb %xb"
+info EMUX_LOG___PAD_BUF_2 EMAC_LV3_H "[EMAC][EMUX][TB] %xb %xb %xb %xb"
+
+
+// Close UL Harq
+info EMUX_LOG___INIT_HARQ_INFO_QUICK EMAC_LV2_H "[EMAC][EMUX][UL-HARQ] Init harq_info(quick): cc_idx=%ub, harq_id=%ub"
+
+
+
+// MUX option
+info EMUX_LOG___OPTION EMAC_LV1_H "[EMAC][EMUX][IF] Option: pidx=%b, lcg_buf_inc_opt=%Memux_rb_group_e, lcp_opt=%Memux_rb_group_e"
+
+// Force all padding
+info EMUX_LOG___FORCE_ALL_PAD EMAC_LV1_H "[EMAC][EMUX][IF] Force all pad: pidx=%b, ul_cc_idx=%ub, harq_id=%ub"
+
+// EMAC reset
+info EMUX_LOG___EMAC_RESET EMAC_LV1_H "[EMAC][EMUX][IF] EMAC reset: pidx=%b"
+
+// Init // Time format: __DATE__=Mmm dd yyyy, __TIME__=hh:mm:ss
+info EMUX_LOG___INIT EMAC_LV1_H "[EMAC][EMUX][IF] EMUX init"
+info EMUX_LOG___CMPL_DATE EMAC_LV1_H "[EMAC][EMUX][INFO] cmpl_date=%c%c%c/%c%c"
+info EMUX_LOG___CMPL_TIME EMAC_LV1_H "[EMAC][EMUX][INFO] cmpl_time=%c%c:%c%c:%c%c"
+info EMUX_LOG___CURR_TIME EMAC_LV1_H "[EMAC][EMUX][INFO] curr_time=%ul/%ul/%ul %ul:%ul:%ul"
+
+info EMUX_LOG___FEATURE EMAC_LV1_H "[EMAC][EMUX][INFO] Feature: UL_CC_NUM=%ub, PN31_PAD=%ub, BSR_CONSIDER_SUSPEND_RB=%ub, GEMINI=%ub, L+W=%ub, MPS=%ub, L+L=%ub, RSIM=%ub, LTE_NUM=%ub"
+info EMUX_LOG___CONTEXT EMAC_LV1_H "[EMAC][EMUX][INFO] Context: g_emux=%xl, cc0(harq0-3,muxbuf)=(%xl,%xl)(%xl,%xl)(%xl,%xl)(%xl,%xl), cotfq=%xl, cotfq_num=%ul, g_pad_buf=%xl"
+
+info EMUX_LOG___INIT_HARQ_INFO EMAC_LV1_H "[EMAC][EMUX][UL-HARQ] Init harq_info: cc_idx=%ub, harq_id=%ub"
+
+info EMUX_LOG___GEN_PAD_BUF_PN31 EMAC_LV1_H "[EMAC][EMUX][PAD] Generate pad_buf: PN31"
+info EMUX_LOG___GEN_PAD_BUF_ALL0 EMAC_LV1_H "[EMAC][EMUX][PAD] Generate pad_buf: ALL0"
+
+// Reset
+info EMUX_LOG___RESET EMAC_LV1_H "[EMAC][EMUX][IF] EMUX reset"
+
+
+// ============================================================================================================
+// EMACDL
+// ============================================================================================================
+info EMACDL_LOG_RESET EMAC_LV1_H "[EMAC][DL][CFG] reset"
+info EMACDL_LOG_DRB_CFG EMAC_LV1_H "[EMAC][DL][CFG] close_rb_num=%ub, open_rb_num=%ub"
+info EMACDL_LOG_SUPPORT_REL EMAC_LV1_H "[EMAC][DL][CFG] protocol %ub, support release %Merrc_emac_support_release_enum, start fix lcid %ub, RBR enable %ub"
+
+info EMACDL_LOG_HDR_LEN_ERROR EMAC_LV1_H "[EMAC][DL][TB][ERROR] TB %ub: accu_len %ud > tb_len=%ud"
+info EMACDL_LOG_CE_AFTER_SDU EMAC_LV1_H "[EMAC][DL][TB][ERROR] TB %ub: CE %ub after SDU"
+info EMACDL_LOG_INVALID_LCID EMAC_LV1_H "[EMAC][DL][TB][ERROR] TB %ub: logical channel %ub not open"
+info EMACDL_LOG_UEID_IN_C_SPS_TB EMAC_LV1_H "[EMAC][DL][TB][ERROR] TB %ub: UEID exists in C/SPS TB"
+info EMACDL_LOG_SUBHDR_EXCEEDS_TABLE EMAC_LV2_H "[EMAC][DL][TB] TB %ub: subheader number=%ud exceeds pre-record table"
+info EMACDL_LOG_CE_OUT_RECORD EMAC_LV1_H "[EMAC][DL][TB][ERROR] TB %ub: CE %ub falls out of record table"
+info EMACDL_LOG_PADDING_BYTES EMAC_LV1_H "[EMAC][DL][TB] TB %ub: padding len %ul after last lcid %ub"
+info EMACDL_LOG_TOO_MANY_SUBHDR EMAC_LV1_H "[EMAC][DL][TB][ERROR] TB %ub: too many subheader, last lcid %ub"
+info EMACDL_LOG_RCV_4BYTE_SCELL EMAC_LV1_H "[EMAC][DL][WARN] TB %ub: 4-byte SCell MAC CE inside, won't handle it"
+
+info EMACDL_LOG_CR_TIMER_NOT_START_YET EMAC_LV1_H "[EMAC][DL][RA][WARN] Rcv tc-rnti TB before CR timer start at abs=%ul"
+
+info EMACDL_LOG_UEID_EXIST_WHEN_NO_RA EMAC_LV1_H "[EMAC][DL][RA][WARN] UEID exists when not in WAIT_CR"
+
+
+// ============================================================================================================
+// TA
+// ============================================================================================================
+info EMAC_TA_LOG_TA_VALUE EMAC_LV1_H "[EMAC][TA] Result: tag_id=%ub, value=%l"
\ No newline at end of file
diff --git a/mcu/protocol/interface/enl2/el2/trace/emac_trace_2.tmd b/mcu/protocol/interface/enl2/el2/trace/emac_trace_2.tmd
new file mode 100644
index 0000000..af7ab53
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/emac_trace_2.tmd
@@ -0,0 +1,276 @@
+[Default]
+EMAC_2
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 15
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+EMAC_LV1_H ON // Internal use (basic information)
+EMAC_LV2_H ON // Internal use (more information)
+EMAC_LV3_H ON // Internal use (detail)
+EMAC_WARN_H ON // Internal use
+EMAC_ERROR_H ON // Internal use
+EMAC_DEBUG_H ON // For temp log
+
+[String]
+
+[Message]
+
+// ============================================================================================================
+// MCH
+// ============================================================================================================
+// ============================================================================================================
+// EMACDL TASK: Legacy trace from 6291
+// ============================================================================================================
+info EMBMS_LOG_RESET_SYNC_AREA_INIT EMAC_LV1_H "[EMAC][MBMS][CFG] reset_sync_area_info called, reset sync_area_id: %ul, area_num: %ul, onging_flag: %ul"
+info EMBMS_LOG_DELETE_ACTIVE_AREA EMAC_LV1_H "[EMAC][MBMS][CFG] idx_map: %ud, area_num: %ul, area_idx: %ul, areainfo_vaild: %ul"
+info EMBMS_LOG_MCCH_CONFIG_INIT EMAC_LV1_H "[EMAC][MBMS][CFG] mcch_config called, sync_area_id: %ul, num_mcch_cfg: %ud, num_active_area: %ul, onging_flag: %ul"
+info EMBMS_LOG_EXIST_MCCH EMAC_LV1_H "[EMAC][MBMS][CFG] existed mcch config with %ud.idx_map: %ud, area_idx: %ul, area_id: %ul"
+info EMBMS_LOG_NEW_CFG_MCCH EMAC_LV1_H "[EMAC][MBMS][CFG] new mcch config with %ud. area_id: %ul, offset: %ul, RP: %ud, MP: %ud, sf_num: %ul, recv_mode: %Mel1_ch_mch_mcch_reception_mode_enum"
+info EMBMS_LOG_ADD_MCCH EMAC_LV1_H "[EMAC][MBMS][CFG] add new mcch, sync_area_id: %ul, idx_map: %ud, area_idx: %ul, area_id: %ul"
+info EMBMS_LOG_UPDATE_MCCH EMAC_LV1_H "[EMAC][MBMS][CFG] update current mcch, sync_area_id: %ul, area_id: %ul"
+info EMBMS_LOG_DELETE_MCCH EMAC_LV1_H "[EMAC][MBMS][CFG] delete current mcch, sync_area_id: %ul, area_id: %ul"
+info EMBMS_LOG_MCCH_CFG_IDX EMAC_LV1_H "[EMAC][MBMS][CFG] area_info_idx: %ul, mcch_cfg_idx: %ul"
+info EMBMS_LOG_PMCH_CONFIG_INIT EMAC_LV1_H "[EMAC][MBMS][CFG] pmch_config called, sync_area_id: %ul, area_id: %ul, CSA: %ud, sf_num: %ul, num_pmch_info: %ul, onging_flag: %ul"
+info EMBMS_LOG_PMCH_AREA_ID EMAC_LV1_H "[EMAC][MBMS][CFG] area_idx: %ul"
+info EMBMS_LOG_PMCH_RESET EMAC_LV1_H "[EMAC][MBMS][CFG] pmch info reset, is_vaild: %ul, area_id: %ul"
+info EMBMS_LOG_ADD_PMCH EMAC_LV1_H "[EMAC][MBMS][CFG] add new pmch, area_id: %ul, pmch_id: %ul"
+info EMBMS_LOG_PMCH_SF_LIST EMAC_LV1_H "[EMAC][MBMS][CFG] pmch sf list: %ul: %ul"
+warn EMBMS_LOG_PMCH_CFG_ERR_ALLOC_END EMAC_LV1_H "[EMAC][MBMS][CFG] invalid sf-alloc end: %ul, num_csa_sf: %ud, pmch_id: %ul"
+info EMBMS_LOG_UPDATE_MSI_INIT EMAC_LV1_H "[EMAC][MBMS][CFG] update_msi called, sync_area_id: %ul, area_id: %ul, pmch_id: %ul, sf_no %ul, num_mch_sched: %ud"
+warn EMBMS_LOG_INVAILD_AREA_INFO_ID EMAC_LV1_H "[EMAC][MBMS][CFG] Do not have vaild area_info_idx!!!"
+info EMBMS_LOG_RECEPTION_MODE_INIT EMAC_LV1_H "[EMAC][MBMS][CFG] reception_mode_config called, sync_area_id: %ul, sf_no: %ud, onging_flag: %ul"
+info EMBMS_LOG_CFG_RECEPTION_MODE EMAC_LV1_H "[EMAC][MBMS][CFG] el1 config mbms mcch reception mode, current mode: %ul, assigned mode: %ul, area_id: %ul"
+info EMBMS_LOG_QUERY_IDX EMAC_LV1_H "[EMAC][MBMS][CFG] query_index called, sync_area_id: %ul, area_id: %ul"
+info EMBMS_LOG_UPDATE_SCHED_INIT EMAC_LV1_H "[EMAC][MBMS][SCHED] update_schedule called, sync_area_id: %ul, sf_no: %ud, force: %ul, onging_flag: %ul, num_active_area: %ul"
+info EMBMS_LOG_SCHED_NO_VALID_RESULT EMAC_LV1_H "[EMAC][MBMS][SCHED][RESULT] update sched at sf_no %ud but no valid sched result returned"
+info EMBMS_LOG_UPDATE_SCHED_RESULT EMAC_LV1_H "[EMAC][MBMS][SCHED][RESULT] update sched result, sync_area_id: %ul, area_id: %ul, sf_no: %ud, is_mcch: %ul, mcch_mp_id: %ul, pmch_id: %ul, mcs: %ul"
+info EMBMS_LOG_UPDATE_SCHED_RESULT_GEMINI EMAC_LV1_H "[EMAC][MBMS][SCHED][RESULT][Gemini] update sched result, sync_area_id: %ul, area_id: %ul, sf_no: %ud, is_mcch: %ul, mcch_mp_id: %ul, pmch_id: %ul, mcs: %ul, priority: %Mel1_embms_gemini_priority_enum"
+info EMBMS_LOG_MCCH_UPDATE_SCHED EMAC_LV1_H "[EMAC][MBMS][SCHED] update mcch sched, area_id: %ul, sf_no: %ud, force: %ul, mode change: %ul, valid: %ul or passed"
+info EMBMS_LOG_MCCH_SCHED_RESULT EMAC_LV1_H "[EMAC][MBMS][SCHED] mcch sched, area_id: %ul, sf_no: %ud, recv_mode: %ul, valid: %ul"
+info EMBMS_LOG_MCCH_SCHED_NEXT EMAC_LV1_H "[EMAC][MBMS][SCHED] mcch final update, area_id: %ul, sf_no: %ud, area_idx: %ul, mcch_mp_id: %ul"
+warn EMBMS_LOG_MCCH_NO_VAILD_NEXT EMAC_LV1_H "[EMAC][MBMS][SCHED] mcch final update, no vaild next mcch"
+info EMBMS_LOG_RPID_MPID EMAC_LV1_H "[EMAC][MBMS][SCHED][MP_ID] sf_no %ud, rp_id_in_mp %ul, mp_id %ul"
+info EMBMS_LOG_FORCE_RECV_MCCH EMAC_LV1_H "[EMAC][MBMS][SCHED][MP_ID] force to recv mcch when delay across mp, current sf_no %ud, last mcch sf_no %ud, rp_id_in_mp %ul"
+info EMBMS_LOG_PMCH_UPDATE_SCHED EMAC_LV1_H "[EMAC][MBMS][SCHED] update pmch sched, area_id: %ul, pmch_id: %ul, sf_no: %ud, force: %ul, valid: %ul or passed"
+info EMBMS_LOG_PMCH_SCHED_RESULT EMAC_LV1_H "[EMAC][MBMS][SCHED] pmch sched, area_id: %ul, pmch_id: %ul, sf_no: %ud, b_msi_checked: %ud, valid: %ul"
+info EMBMS_LOG_MSI_HANDLE_CSA_IDX EMAC_LV1_H "[EMAC][MBMS][SCHED] MSI handling... find_next_res: %ul, CSA_id: %ud, CSA_id_in_mp: %ud, sf_idx: %ud, cur_sf_no: %ud, sf_idx_in_msp: %ud, num_csa_sf_res: %ud"
+info EMBMS_LOG_PMCH_SCHED_NEXT EMAC_LV1_H "[EMAC][MBMS][SCHED] pmch final update, pmch_idx: %ul, sf_no: %ud, cas_idx: %ud"
+info EMBMS_LOG_SCHED_NEXT_INIT EMAC_LV1_H "[EMAC][MBMS][SCHED] schedule_next called, sync_area_id: %ul, onging_flag: %ul"
+info EMBMS_LOG_REDUNDANT_SCHED_NEXT EMAC_LV1_H "[EMAC][MBMS][SCHED] redundant schedule next, sync_area_id: %ul"
+info EMBMS_LOG_SCHED_NEXT_RESULT EMAC_LV1_H "[EMAC][MBMS][SCHED][RESULT] sched next result, sync_area_id: %ul, area_id: %ul, sf_no: %ud, is_mcch: %ul, mcch_mp_id %ul, pmch_id: %ul, mcs: %ul"
+info EMBMS_LOG_SCHED_NEXT_RESULT_2 EMAC_LV1_H "[EMAC][MBMS][SCHED][RESULT] is_pmch: %Mkal_bool, csap_id: %ud, is_mch_reliable: %Mkal_bool"
+info EMBMS_LOG_SCHED_NEXT_RESULT_GEMINI EMAC_LV1_H "[EMAC][MBMS][SCHED][RESULT][Gemini] sched next result, sync_area_id: %ul, area_id: %ul, sf_no: %ud, is_mcch: %ul, mcch_mp_id %ul, pmch_id: %ul, mcs: %ul, priority: %Mel1_embms_gemini_priority_enum"
+info EMBMS_LOG_NUM_MTCH_RESOURCE EMAC_LV1_H "[EMAC][MBMS][SCHED][Gemini] num_mtch_resource: %ul, threshold: %ul, priority: %Mel1_embms_gemini_priority_enum"
+info EMBMS_LOG_SIB2_MBSFN_CFG_UPDATE EMAC_LV1_H "[EMAC][MBMS][CFG] After SIB2 MBSFN Subframe Cfg update, sync_area_id: %ub, SIB2 valid: %Mkal_bool, period: %ud, num_sf_in_list: %ud"
+warn EMBMS_LOG_SF_CFG_INVALID_WITH_SIB2 EMAC_LV1_H "[EMAC][MBMS][CFG][WARN] detect invalid mbsfn sf ocnfig with SIB2, mbsfn_sync_area_id: %ub, is_mcch: %Mkal_bool"
+info EMBMS_LOG_MBSFN_CFG_UNPACK_SF_LIST_PERIOD_RF EMAC_LV1_H "[EMAC][MBMS][CFG] mbsfn sf config unpack, sf_list_period_rf: %ud"
+
+info EMBMS_LOG_MBSFN_SF_CONFIG_INFO EMAC_LV2_H "[EMAC][MBMS][CFG] MBSFN SF Config[%ub], rf_alloc_period: %ub, rf_alloc_offset: %ub, is_one_frame: %Mkal_bool"
+info EMBMS_LOG_MBSFN_SF_CONFIG_SF_LIST_INFO EMAC_LV2_H "[EMAC][MBMS][CFG] MBSFN SF LIST[%ub]: %ub, %ub, %ub, %ub, %ub, %ub"
+info EMBMS_LOG_MCCH_SF_LIST_INFO EMAC_LV2_H "[EMAC][MBMS][CFG] MCCH SF num: %ub, LIST: %ub, %ub, %ub, %ub, %ub, %ub"
+
+// ============================================================================================================
+// EMACDL TASK: 6293
+// ============================================================================================================
+
+// WARN
+warn EMACMCH_T_WAR___PRINT_E EMAC_WARN_H "[EMAC][MCH][T][WARN] %Memacmch_log_e"
+
+// Error
+error EMACMCH_T_ERR___PRINT_E EMAC_ERROR_H "[EMAC][MCH][T][ERROR] %Memacmch_log_e"
+
+// Debug
+warn EMACMCH_T_DBG___PRINT_E1_I4 EMAC_LV1_H "[EMAC][MCH][T][LOG] %Memacmch_log_e %l, %l, %l, %l"
+
+// General
+info EMACMCH_T_LOG___PRINT_E EMAC_LV1_H "[EMAC][MCH][T][LOG] %Memacmch_log_e"
+info EMACMCH_T_LOG___PRINT_BYTE EMAC_LV1_H "[EMAC][MCH][T][LOG] %xb"
+
+// Init
+info EMACMCH_T_LOG___INIT EMAC_LV1_H "[EMAC][MCH][T][IF] Init"
+info EMACMCH_T_LOG___CMPL_DATE EMAC_LV1_H "[EMAC][MCH][T][INFO] cmpl_date=%c%c%c/%c%c"
+info EMACMCH_T_LOG___CMPL_TIME EMAC_LV1_H "[EMAC][MCH][T][INFO] cmpl_time=%c%c:%c%c:%c%c"
+info EMACMCH_T_LOG___CURR_TIME EMAC_LV1_H "[EMAC][MCH][T][INFO] curr_time=%ul/%ul/%ul %ul:%ul:%ul"
+info EMACMCH_T_LOG___INIT_G_EMACMCH_TASK EMAC_LV2_H "[EMAC][MCH][T][INIT] Init g_emacmch_task"
+info EMACMCH_T_LOG___INIT_G_EMACMCH_CMN EMAC_LV2_H "[EMAC][MCH][T][INIT] Init g_emacmch_cmn"
+
+
+// Reset
+info EMACMCH_T_LOG___RESET EMAC_LV1_H "[EMAC][MCH][T][IF] Reset"
+
+// Suspend
+info EMACMCH_T_LOG___SUSPEND EMAC_LV1_H "[EMAC][MCH][T][IF] Suspend: trans_pid=%ub, active_pid=%ub"
+
+// ILM Syncarea cfg req (RRC)
+info EMACMCH_T_LOG___RCV_SA_CFG_REQ EMAC_LV1_H "[EMAC][MCH][T][ILM] Rcv SA_CFG_REQ: active_pidx=%ub, trans_pidx=%ub, cfg_valid=[%Mkal_bool, %Mkal_bool], tid=%ul"
+info EMACMCH_T_LOG___SND_SA_CFG_CNF EMAC_LV1_H "[EMAC][MCH][T][ILM] Snd SA_CFG_CNF: result=%Merrc_el2_cfg_result_enum"
+
+// ILM Area cfg req (RRC)
+info EMACMCH_T_LOG___RCV_A_CFG_REQ EMAC_LV1_H "[EMAC][MCH][T][ILM] Rcv A_CFG_REQ: active_pidx=%ub, trans_pidx=%ub, cfg_valid=[%Mkal_bool, %Mkal_bool], tid=%ul"
+info EMACMCH_T_LOG___SND_A_CFG_CNF EMAC_LV1_H "[EMAC][MCH][T][ILM] Snd A_CFG_CNF: result=%Merrc_el2_cfg_result_enum"
+
+// ILM Mxch cfg req (RRC)
+info EMACMCH_T_LOG___RCV_MXCH_CFG_REQ EMAC_LV1_H "[EMAC][MCH][T][ILM] Rcv MXCH_CFG_REQ: active_pidx=%ub, trans_pidx=%ub"
+info EMACMCH_T_LOG___SND_MXCH_CFG_CNF EMAC_LV1_H "[EMAC][MCH][T][ILM] Snd MXCH_CFG_CNF: result=%Merrc_el2_cfg_result_enum"
+info EMACMCH_T_LOG___RELEASE_TMGI EMAC_LV2_H "[EMAC][MCH][T][MXCH] Release MTCH: tmgi=[%xb %xb %xb %xb %xb %xb]"
+info EMACMCH_T_LOG___ESTABLISH_TMGI EMAC_LV2_H "[EMAC][MCH][T][MXCH] Establish MTCH: tmgi=[%xb %xb %xb %xb %xb %xb]"
+info EMACMCH_T_LOG___ACTIVE_MCCH_NUM EMAC_LV1_H "[EMAC][MCH][T][MXCH] active_mcch_num=%ub"
+info EMACMCH_T_LOG___ACTIVE_MTCH_NUM EMAC_LV1_H "[EMAC][MCH][T][MXCH] active_mtch_num=%ub"
+error EMACMCH_T_ERR___MCCH_NOT_FOUND EMAC_ERROR_H "[EMAC][MCH][T][MXCH][ERROR] Cannot find mcch_idx"
+error EMACMCH_T_ERR___MTCH_NOT_FOUND EMAC_ERROR_H "[EMAC][MCH][T][MXCH][ERROR] Cannot find mtch_idx"
+
+// ILM Mcch rcv mode change req (RRC)
+info EMACMCH_T_LOG___RCV_MCCH_RMC_REQ EMAC_LV1_H "[EMAC][MCH][T][ILM] Rcv MCCH_RMC_CFG_REQ(RRC): active_pidx=%ub, trans_pidx=%ub, cfg_valid=[%Mkal_bool, %Mkal_bool], tid=%ul"
+info EMACMCH_T_LOG___SND_MCCH_RMC_CNF EMAC_LV1_H "[EMAC][MCH][T][ILM] Snd MCCH_RMC_CFG_CNF: result=%Merrc_el2_cfg_result_enum"
+
+// ILM Mcch rcv mode change ind (EL1)
+info EMACMCH_T_LOG___RCV_MCCH_RMC_IND EMAC_LV1_H "[EMAC][MCH][T][ILM] Rcv MCCH_RMC_IND_REQ(EL1): active_pidx=%ub, trans_pidx=%ub, said=%ub, tid=%ul"
+
+// ILM Poll req (EMACDL)
+info EMACMCH_T_LOG___RCV_POLL_REQ EMAC_LV1_H "[EMAC][MCH][T][ILM] Rcv POLL_REQ: active_pidx=%ub, trans_pidx=%ub, cell_time_cnt=%ul, abs_time=%ul"
+
+// - Detect MCH not received
+warn EMACMCH_T_WAR___MCH_NOT_RCV EMAC_WARN_H "[EMAC][MCH][T][WARN] MCH not received: cell_time=%ul, abs_time=%ul, said=%ub, aid=%ub, pmch_id=%ub, is_mcch_occasion=%Mkal_bool, intr_ch=%Memacmch_ch_group_e"
+
+// - Pre-schedule
+info EMACMCH_T_LOG___START_PRE_SCHED EMAC_LV1_H "[EMAC][MCH][T][PRES] Start pre-sched process: said=%ub"
+info EMACMCH_T_LOG___CONDITION_A EMAC_LV2_H "[EMAC][MCH][T][PRES] Meet condition A: poll time <= last ps time"
+info EMACMCH_T_LOG___CONDITION_B EMAC_LV2_H "[EMAC][MCH][T][PRES] Meet condition B: last ps time < poll time < last ps time + 5120"
+info EMACMCH_T_LOG___CONDITION_C EMAC_LV2_H "[EMAC][MCH][T][PRES] Meet condition C: poll time >= last ps time + 5120"
+info EMACMCH_T_LOG___UPDATE_SCHEDULE EMAC_LV1_H "[EMAC][MCH][T][PRES] Update sched() input: said=%ub, clear_stored_info=%Mkal_bool, cell_time=%ul, abs_time=%ul"
+info EMACMCH_T_LOG___SCHEDULE_NEXT EMAC_LV1_H "[EMAC][MCH][T][PRES] Schedule next() input: said=%ub, abs_time=%ul"
+info EMACMCH_T_LOG___FILL_PSQ_A EMAC_LV1_H "[EMAC][MCH][T][PRES] Fill PSQ: said=%ub, aid=%ub, pmch_id=%ub, sf_idx_in_msp=%ud, mcch_mp_id=%ub"
+info EMACMCH_T_LOG___FILL_PSQ_B EMAC_LV1_H "[EMAC][MCH][T][PRES] Fill PSQ: intr_ch=%Memacmch_ch_group_e, is_mcch_occasion=%Mkal_bool, mcs=%ub, non_mbsfn_region_len=%ub"
+info EMACMCH_T_LOG___FILL_PSQ_C EMAC_LV2_H "[EMAC][MCH][T][PRES] Fill PSQ: gemini_priority=%Mel1_embms_gemini_priority_enum, atm_filterout=%ul, atm_mch_reliable=%ul"
+info EMACMCH_T_LOG___FILL_PSQ_D EMAC_LV1_H "[EMAC][MCH][T][PRES] Fill PSQ: cell_time=%ul, abs_time=%ul"
+info EMACMCH_T_LOG___ENOUGH_VALID_PS_NUM EMAC_LV1_H "[EMAC][MCH][T][PRES] Enough valid_ps_num or large time diff"
+info EMACMCH_T_LOG___STOT_PRE_SCHED EMAC_LV1_H "[EMAC][MCH][T][PRES] Stop pre-sched process"
+warn EMACMCH_T_WAR___CANNOT_FIND_CANDID EMAC_WARN_H "[EMAC][MCH][T][PRES][WARN] Cannot find any candidate"
+
+
+// - Get PDU info from HSQ
+info EMACMCH_T_LOG___TRAVERSE_HSQ_BEFORE EMAC_LV1_H "[EMAC][MCH][T][PDU] Before traverse HSQ: atm_hsq_r_idx=%ul, atm_hsq_w_idx=%ul"
+info EMACMCH_T_LOG___HS_FOUND EMAC_LV1_H "[EMAC][MCH][T][PDU] HS found: hs_idx=%ul"
+info EMACMCH_T_LOG___PDU_INFO_BY_HS_A EMAC_LV1_H "[EMAC][MCH][T][PDU] HS: aid=%ub, pmch_id=%ub, mcch_mp_id=%ub"
+info EMACMCH_T_LOG___PDU_INFO_BY_HS_B EMAC_LV1_H "[EMAC][MCH][T][PDU] HS: intr_ch=%Memacmch_ch_group_e, is_mcch_occasion=%Mkal_bool"
+info EMACMCH_T_LOG___PDU_INFO_BY_HS_C EMAC_LV1_H "[EMAC][MCH][T][PDU] HS: session_num_in_pmch=%ub, is_cfg_pmch_info_list_ext=%Mkal_bool"
+info EMACMCH_T_LOG___TRAVERSE_HSQ_AFTER EMAC_LV1_H "[EMAC][MCH][T][PDU] After traverse HSQ: atm_hsq_r_idx=%ul, atm_hsq_w_idx=%ul"
+warn EMACMCH_T_WAR___HS_NOT_FOUND_A EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] HS not found: hs abs_time > pdu rcv_abs_time"
+warn EMACMCH_T_WAR___HS_NOT_FOUND_B EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] HS not found: no hs match"
+warn EMACMCH_T_WAR___UNKNOWN_PDU EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] Unknown PDU: cannot find the associated HS"
+
+
+// - Process MSI CE
+warn EMACMCH_T_WAR___MSI_IGNORE_A EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MSI is ignored because intr_ch does not include MTCH"
+warn EMACMCH_T_WAR___MSI_IGNORE_B EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MSI is ignored because it locates after MSI or MCCH or MTCH"
+warn EMACMCH_T_WAR___MSI_IGNORE_C EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MSI is ignored because msi length does not match session num: msi_len=%ub, session_num=%ub"
+warn EMACMCH_T_WAR___MSI_IGNORE_PAIR EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MSI: schedule pair is ignored because MTCH is not activated or reserved stop_mtch"
+warn EMACMCH_T_WAR___UPDATE_MSI_FAILURE EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] Update msi() failed: Ignore this MSI"
+
+// - Process MSI CE for MTCH suspend
+info EMACMCH_T_LOG___SND_MTCH_SUS_IND EMAC_LV1_H "[EMAC][MCH][T][ILM] Snd MTCH_SUSPEND_IND: said=%ub, aid=%ub, pmch_id=%ub, suspend_mtch_num=%b"
+
+// - Process MSI CE for MCH reliability and PS filterout
+info EMACMCH_T_LOG___SET_MCH_RELIABLE EMAC_LV1_H "[EMAC][MCH][T][PDU] MSI: Set mch reliable to ps_idx=%ul"
+info EMACMCH_T_LOG___SET_PS_FILTEROUT EMAC_LV1_H "[EMAC][MCH][T][PDU] MSI: Set ps filterout to ps_idx=%ul"
+
+// - Process MCCH
+warn EMACMCH_T_WAR___MCCH_IGNORE_A EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MCCH is ignored because mcch_idx not found"
+warn EMACMCH_T_WAR___MCCH_IGNORE_B EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MCCH is ignored because intr_ch not include MCCH"
+
+// - Process MTCH
+warn EMACMCH_T_WAR___MTCH_IGNORE_A EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MTCHs are all ignored because intr_ch not include MTCH"
+warn EMACMCH_T_WAR___MTCH_IGNORE_B EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MTCH is ignored because mtch_idx not found (not interested ny UE)"
+warn EMACMCH_T_WAR___MTCH_IGNORE_C EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MTCH is ignored because lcid=31(pad) or lcid=29(rsv)"
+warn EMACMCH_T_WAR___MTCH_IGNORE_D EMAC_WARN_H "[EMAC][MCH][T][PDU][WARN] MTCH is ignored because lcid out of range"
+
+
+// PSQ
+info EMACMCH_T_LOG___PSQ_IDX EMAC_LV1_H "[EMAC][MCH][T][PSQ] PSQ: atm_psq_idx=%ul"
+info EMACMCH_T_LOG___PSQ_RW_IDX EMAC_LV1_H "[EMAC][MCH][T][PSQ] PSQ: atm_psq_r_idx=%ul, atm_psq_w_idx=%ul"
+info EMACMCH_T_LOG___DISABLE_PSQ EMAC_LV1_H "[EMAC][MCH][T][PSQ] Disable PSQ"
+info EMACMCH_T_LOG___SWAP_PSQ EMAC_LV1_H "[EMAC][MCH][T][PSQ] Swap PSQ"
+info EMACMCH_T_LOG___PSQ_INFO EMAC_LV1_H "[EMAC][MCH][T][PSQ] PSQ: atm_psq_idx=%ul, atm_psq_r_idx=%ul, atm_psq_w_idx=%ul, valid_ps_num=%ul"
+info EMACMCH_T_LOG___PSQ_EMPTY EMAC_LV1_H "[EMAC][MCH][T][PSQ] PSQ is empty"
+error EMACMCH_T_ERR___PSQ_FULL EMAC_ERROR_H "[EMAC][MCH][T][PSQ][ERROR] PSQ is full"
+
+// HSQ
+info EMACMCH_T_LOG___HSQ_RW_IDX EMAC_LV1_H "[EMAC][MCH][T][HSQ] HSQ: atm_hsq_r_idx=%ul, atm_hsq_w_idx=%ul"
+info EMACMCH_T_LOG___CLEAR_HSQ EMAC_LV1_H "[EMAC][MCH][T][HSQ] Clear all HSQ"
+info EMACMCH_T_LOG___CLEAR_HSQ_BEFORE EMAC_LV1_H "[EMAC][MCH][T][HSQ] Before clear HSQ: said=%ub, atm_hsq_r_idx=%ul, atm_hsq_w_idx=%ul"
+info EMACMCH_T_LOG___CLEAR_HSQ_AFTER EMAC_LV1_H "[EMAC][MCH][T][HSQ] After clear HSQ: said=%ub, atm_hsq_r_idx=%ul, atm_hsq_w_idx=%ul"
+
+// TID
+info EMACMCH_T_LOG___UPDATE_RRC_TID EMAC_LV1_H "[EMAC][MCH][T][TID] Update RRC TID: atm_rrc_tid=%ul"
+info EMACMCH_T_LOG___UPDATE_EL1_TID EMAC_LV1_H "[EMAC][MCH][T][TID] Update EL1 TID: atm_el1_tid=%ul"
+
+// MSIM (L+L)
+warn EMACMCH_T_WAR___PIDX_MISMATCH EMAC_WARN_H "[EMAC][MCH][T][L+L][WARN] pidx mismatch: active_pidx=%ub, trans_pidx=%ub"
+
+// ============================================================================================================
+// RXLISR: 6293
+// ============================================================================================================
+
+// WARN
+warn (non_smp) EMACMCH_L_WAR___PRINT_E EMAC_WARN_H "[EMAC][MCH][L][WARN] %Memacmch_log_e"
+
+// Query next mch
+
+info (non_smp) EMACMCH_L_LOG___QUERY_OUTPUT_A EMAC_LV1_H "[EMAC][MCH][L][QURY] next mch: tid=%ul el1_tid=%ul rrc_tid=%ul"
+info (non_smp) EMACMCH_L_LOG___QUERY_OUTPUT_D EMAC_LV1_H "[EMAC][MCH][L][QURY] next mch: gemini_priority=%Mel1_embms_gemini_priority_enum"
+
+warn (non_smp) EMACMCH_L_WAR___QUERY_FAILURE_A EMAC_WARN_H "[EMAC][MCH][L][WARN] next mch fail due to ongoing configuration in task(T->L). psq_idx=%ul"
+warn (non_smp) EMACMCH_L_WAR___QUERY_FAILURE_B EMAC_WARN_H "[EMAC][MCH][L][WARN] next mch fail due to empty PSQ."
+warn (non_smp) EMACMCH_L_WAR___QUERY_FAILURE_C EMAC_WARN_H "[EMAC][MCH][L][WARN] next mch fail due to ongoing configuration in task(L->T)."
+warn (non_smp) EMACMCH_L_WAR___QUERY_FAILURE_D EMAC_WARN_H "[EMAC][MCH][L][WARN] next mch fail due to no valid PS."
+warn (non_smp) EMACMCH_L_WAR___QUERY_FAILURE_E EMAC_WARN_H "[EMAC][MCH][L][WARN] QUERY_NEXT_MCH is received but active_pidx=INVALID."
+warn (non_smp) EMACMCH_L_WAR___QUERY_FAILURE_F EMAC_WARN_H "[EMAC][MCH][L][WARN] next mch fail due to active_pidx and input_pidx mismatch."
+
+// PSQ
+info (non_smp) EMACMCH_L_LOG___PSQ_IDX EMAC_LV1_H "[EMAC][MCH][L][PSQ] PSQ: atm_psq_idx=%ul"
+info (non_smp) EMACMCH_L_LOG___PSQ_RW_IDX EMAC_LV1_H "[EMAC][MCH][L][PSQ] PSQ: atm_psq_r_idx=%ul atm_psq_w_idx=%ul"
+
+// HSQ
+info (non_smp) EMACMCH_L_LOG___HSQ_RW_IDX EMAC_LV1_H "[EMAC][MCH][L][HSQ] HSQ: atm_hsq_r_idx=%ul atm_hsq_w_idx=%ul"
+error (non_smp) EMACMCH_L_ERR___HSQ_FULL EMAC_ERROR_H "[EMAC][MCH][L][HSQ][ERROR] HSQ is full"
+
+// Format:
+// %-5uc => char
+// xb => 1 bytes
+// d => 2 bytes
+// f => 3 bytes
+// l => 4 bytes
+// m => enum
+// s => string
+//
+// - => left alignment
+// 5 => width
+// u|x => unsigned|hex display mode
+
+// Bit decoding:
+// %-5uc:3 => char
+// xb => 1 bytes
+// sd => 2 bytes
+// pl => 4 bytes
+//
+// - => left alignment
+// 5 => width
+// u|x|s|p => unsigned|hex|string|paadding
+// c|b|d|l => char|1bytes|2bytes|4bytes
+// :3 => bit length
+
+// Example: Bit decoding
+// "X=%ub:2 %pb:3 Y=%ub:3" b7 b6 b5 b4 b3 b2 b1 b0
+// VAR: | Y | RSV | X |
+
+// Example: kal_bool
+// "is_one_frame = %Mkal_bool"
+
+// Example: enum
+// "lcg_buf_inc_opt = %Memux_rb_group_e"
diff --git a/mcu/protocol/interface/enl2/el2/trace/emac_trace_internal.tmd b/mcu/protocol/interface/enl2/el2/trace/emac_trace_internal.tmd
new file mode 100644
index 0000000..a6bd823
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/emac_trace_internal.tmd
@@ -0,0 +1,132 @@
+[Default]
+EMAC_INTERNAL
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 15
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+EMAC_LV1_H ON // Internal use (basic information)
+EMAC_LV2_H ON // Internal use (more information)
+EMAC_LV3_H ON // Internal use (detail)
+EMAC_WARN_H ON // Internal use
+EMAC_ERROR_H ON // Internal use
+EMAC_DEBUG_H ON // For temp log
+
+[String]
+
+[Message]
+
+// ============================================================================================================
+// EMUX
+// ============================================================================================================
+info EMUX_LOG___CACHE_FLUSH_MUX_BUF EMAC_LV3_H "[EMAC][EMUX][TB] Cache flush for mux_buf"
+info EMUX_LOG___CACHE_FLUSH_PAD_BUF EMAC_LV3_H "[EMAC][EMUX][PAD] Cache flush for pad_buf"
+info EMUX_LOG___SYSTEM EMAC_LV1_H "[EMAC][EMUX][INFO] System: LV1_CACHE=%ub, LV2_CACHE=%ub"
+
+// MUX (Fill DSC)
+info EMUX_LOG___FILL_IB_COTF EMAC_LV3_H "[EMAC][EMUX][DSC] Fill IB COTF =[%xl %xl %xl]"
+info EMUX_LOG___FILL_IB_TM EMAC_LV3_H "[EMAC][EMUX][DSC] Fill IB TM =[%xl %xl]"
+info EMUX_LOG___FILL_NM_MUXBUF EMAC_LV3_H "[EMAC][EMUX][DSC] Fill NM MUXBUF =[%xl %xl]"
+info EMUX_LOG___FILL_RLC_DSCS EMAC_LV3_H "[EMAC][EMUX][DSC] Fill RLC DSCs"
+info EMUX_LOG___FILL_NM_PADBUF EMAC_LV3_H "[EMAC][EMUX][DSC] Fill NM PADBUF =[%xl %xl]"
+info EMUX_LOG___QP_START EMAC_LV3_H "[EMAC][EMUX][DSC] QP Start: write_inc_num=%ud"
+
+
+// ============================================================================================================
+// EMACDL
+// ============================================================================================================
+info EMACDL_LOG_RX_PROC EMAC_LV3_H "[EMAC][DL][Poll] rcv Poll at abs %ul, cell_cnt %ud, DL LMAC r_idx %ud, w_idx %ud"
+
+info EMACDL_LOG_RCV_LMAC_RAR_INT EMAC_LV3_H "[EMAC][DL][INT] rcv LMAC RAR interrupt, notify EMACDL"
+info EMACDL_LOG_RCV_LMAC_TC_INT EMAC_LV3_H "[EMAC][DL][INT] rcv LMAC TC-RNTI interrupt, notify EMACDL"
+info EMACDL_LOG_RCV_LMAC_DATA_READY_INT EMAC_LV3_H "[EMAC][DL][INT] rcv LMAC Data Ready interrupt, notify EMACDL"
+
+// ============================================================================================================
+// MCH
+// ============================================================================================================
+// VRB (DL RLC)
+info EMACMCH_T_LOG___RELEASE_VRB EMAC_LV1_H "[EMAC][MCH][T][VRB] Release RLC DL VRB: addr=%xl, len=%ul"
+
+
+// ============================================================================================================
+// EL2POW
+// ============================================================================================================
+info EL2POW_LOG_RCV_EL1_POWER_ON_REQ EMAC_LV2_H "[EL2POW] Rcv on_req from EL1, cause %Mel1_power_on_cause_e, old_bmp %ul"
+info EL2POW_LOG_RCV_POWER_ON_REQ EMAC_LV2_H "[EL2POW] Rcv on_req from %Mel2pow_user_event_e, old_bmp %ul"
+info EL2POW_LOG_RCV_EL1_POWER_OFF_REQ EMAC_LV1_H "[EL2POW] Rcv off_req from EL1, cause %Mel1_power_off_cause_e, cur_bmp %ul"
+info EL2POW_LOG_RCV_POWER_OFF_REQ EMAC_LV1_H "[EL2POW] Rcv off_req from %Mel2pow_user_event_e, cur_bmp %ul"
+info EL2POW_LOG_POWER_ON EMAC_LV1_H "[EL2POW] <Copro on> by %Mel2pow_user_event_e"
+info EL2POW_LOG_POWER_OFF_PENDING EMAC_LV1_H "[EL2POW] <Copro off pending> by %Mel2pow_pending_chk_e"
+info EL2POW_LOG_POWER_OFF_PENDING_ONE_MORE_TICK EMAC_LV1_H "[EL2POW] <Copro off pending> off ready, wait for one more tick"
+info EL2POW_LOG_POWER_OFF EMAC_LV1_H "[EL2POW] <Copro off>"
+info EL2POW_LOG_TICK_OFF_PENDING EMAC_LV1_H "[EL2POW] <Tick off pending> by %Mel2pow_pending_chk_e"
+info EL2POW_LOG_TICK_OFF EMAC_LV1_H "[EL2POW] <Tick off>"
+info EL2POW_LOG_TICK_ON EMAC_LV1_H "[EL2POW] <Tick on>"
+info EL2POW_LOG_RCV_TICK EMAC_LV3_H "[EL2POW] Rcv Tick %ub, expect %ub"
+info EL2POW_LOG_RCV_EL1_SCH_CLOSE_RXBRP_IDLE EMAC_LV1_H "[EL2POW] EL1 notify SCH close and RXBRP idle"
+info EL2POW_LOG_RCV_LMAC_HARQ_RESET_REQ EMAC_LV2_H "[EL2POW] Rcv LMAC HARQ reset req from EMAC"
+info EL2POW_LOG_RCV_VA_SHORTAGE_NTF EMAC_LV2_H "[EL2POW] Rcv DL MAC VRB VA shortage ntf, addr=%xl"
+
+// ============================================================================================================
+// EL2EM
+// ============================================================================================================
+info EL2EM_LOG_UPDATE_PER_EM_STATUS EMAC_LV2_H "[EL2EM] %Mel2em_em_type_e status update to %Mem_info_status_enum"
+info EL2EM_LOG_CUR_PER_EM_TYPE_BMP EMAC_LV2_H "[EL2EM] %Mel2em_em_type_e current status %ub"
+info EL2EM_LOG_CUR_PER_REG_SRC_BMP EMAC_LV2_H "[EL2EM] %Mel2em_reg_src_e current bmp %ud, current periodic bmp %ud"
+info EL2EM_LOG_DUMMY4 EMAC_LV2_H "[EL2EM] dummy log %ul, %ul, %ul, %ul"
+
+// ============================================================================================================
+// EL2ICD
+// ============================================================================================================
+info EL2ICD_LOG_CTRL_NTF EMAC_LV2_H "[EL2ICD] ctrl cause %Mel2icd_ctrl_cause_e, to task %Mel2icd_task_e"
+info EL2ICD_LOG_TMR_NTF EMAC_LV2_H "[EL2ICD] tmr period %Mel2icd_period_e expire, to task %Mel2icd_task_e"
+info EL2ICD_LOG_DUMMY4 EMAC_LV2_H "[EL2ICD] dummy log %ul, %ul, %ul, %ul"
+info EL2ICD_LOG_SPS_DL_TB_INFO EMAC_LV2_H "[EL2ICD] SPS DL INFO: cell_time_cnt=%ul, dl_harq_id=%ub"
+error EL2ICD_LOG_RECORD_LOGGING_ERROR EMAC_LV2_H "[EL2ICD] ICD record %ud: logging error %ub, icd_protocol_id %ub, ptr %ul, len/num %ud"
+error EL2ICD_LOG_EVENT_LOGGING_ERROR EMAC_LV2_H "[EL2ICD] ICD event %ud: logging error %ub, icd_protocol_id %ub, ptr %ul, len/num %ud"
+error EL2ICD_LOG_REGISTER_CB_FAIL EMAC_LV2_H "[EL2ICD] SYSTEM_NTF CB register fail"
+
+// ============================================================================================================
+// EMAC config
+// ============================================================================================================
+
+// ============================================================================================================
+// EL2DVFS
+// ============================================================================================================
+warn EL2DVFS_MCU_GEAR_NOT_MEET_REQUIREMENT EMAC_LV1_H "[EL2DVFS] MCU gear not meet el2 requirement! current_md_gear=%ul, el2_gear=%ul"
+info EL2DVFS_MCU_GEAR_INFO EMAC_LV1_H "[EL2DVFS] el2 gear change: current_md_gear=%ul, el2_gear=%ul, required_gear=%ul, reason=%ul"
+// ============================================================================================================
+// EL2 SEC Library (VOLTE)
+// ============================================================================================================
+info EMAC_ERT_LOG_CFG_VOLTE_TIMING_REPORT_REQ EMAC_LV1_H "[EMAC][VOLTE][CFG] volte_timing_report_req=%ub (0: disable, 1: enable), period=%ul, report_mode=%ub"
+info EMAC_ERT_LOG_CFG_VOLTE_TIMING_REPORT EMAC_LV1_H "[EMAC][VOLTE] volte timing report: time_to_sr=%ul, sr_period=%ul, time_to_ondu=%ul, drx_cycle=%ul, us_time=%ul"
+info EMAC_ERT_LOG_SR_VSR_CONFIG EMAC_LV1_H "[EMAC][VOLTE][SR] vsr config: drx_cycle=%ud, drx_offset=%ud, sr_period=%ud, sr_offset=%ud, vsr_period=%ud, vsr_offset=%ud, timing_report_vsr_period=%ud, timing_report_vsr_offset=%ud"
+info EMAC_ERT_LOG_SR_VSR_COVER EMAC_LV1_H "[EMAC][VOLTE][SR] vsr cover computation: vsr_offset=%ud, vsr_cover=%ud"
+
+info (non_smp) EMAC_LOG_VOLTE_POW_ENH_EVENT EMAC_LV1_H "[EMAC][VOLTE][POW] volte power enhance event=%Memac_volte_pow_enh_event_e, combo_in_ondu=%ul"
+
+// ============================================================================================================
+// EL2 SEC Library (UL-HARQ)
+// ============================================================================================================
+info (non_smp) EMAC_UL_HARQ_LOG___CFG_EARLY_CLOSE_UL_HARQ_REQ EMAC_LV1_H "[EMAC][UL-HARQ][CFG] early close ul harq req, type=%Memac_early_close_ul_harq_type_bit_e, operation=%ub (0: stop, 1: start), interval=%ul, early_ul_harq_max_nb=%ub"
+info (non_smp) EMAC_UL_HARQ_LOG___HARQ_EARLY_CLOSE_REACHED EMAC_LV1_H "[EMAC][UL-HARQ] harq last tx: early close: reach rule=%ub, ul_cc_idx=%ub, harq_id=%ub"
+
+info (non_smp) EMAC_UL_HARQ_LOG___EARLY_CLOSE_UL_HARQ_OPERATION EMAC_LV1_H "[EMAC][UL-HARQ] early close ul harq operation=%ub (0: disable, 1: enable)"
+info (non_smp) EMAC_UL_HARQ_LOG___EARLY_CLOSE_UL_HARQ_EXPIRY EMAC_LV1_H "[EMAC][UL-HARQ] early close ul harq expiry: type=%Memac_early_close_ul_harq_type_bit_e"
+
+warn (non_smp) EMAC_UL_HARQ_WARN___CFG_EARLY_CLOSE_UL_HARQ_WARN EMAC_WARN_H "[EMAC][UL-HARQ][CFG] early close ul harq is not enabled, reason=%ub (0: sch close, 1: drx is not enabled or tti bundling is enabled)"
+
+// ============================================================================================================
+// EL2 SEC Library (TMC)
+// ============================================================================================================
+warn (non_smp) EMAC_LOG_TMC_THERMAL_CTRL EMAC_LV1_H "[EMAC][SCELL][TMC] rcv thermal_ctrl_req=%ub"
+warn (non_smp) EMAC_LOG_TMC_THERMAL_CTRL_95 EMAC_LV1_H "[EMAC][SCELL][TMC] rcv thermal_ctrl_req %Mtmc_ctrl_cmd_enum, pa_ctrl=%Mtmc_pa_ctrl_enum, ca_ctrl=%Mtmc_ca_ctrl_enum"
+warn (non_smp) EMAC_LOG_TMC_DROP_CMD EMAC_LV1_H "[EMAC][SCELL][TMC] drop scell_cmd due to thermal ctrl enable, cmd=%xb, rcv_time=%ul"
+warn (non_smp) EMAC_LOG_TMC_DROP_CMD_INTERBAND EMAC_LV1_H "[EMAC][SCELL][TMC] drop inter-band cc_idx=%xb due to thermal ctrl enable"
+
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/emac_trace_public.tmd b/mcu/protocol/interface/enl2/el2/trace/emac_trace_public.tmd
new file mode 100644
index 0000000..1335b78
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/emac_trace_public.tmd
@@ -0,0 +1,346 @@
+[Default]
+EMAC_PUBLIC
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 15
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+EMAC_LV0_H ON // For Customer
+
+[String]
+
+[Message]
+
+// ============================================================================================================
+// COMMON
+// ============================================================================================================
+info (non_smp) EMAC_LOG_CRNTI_DL_ASSIGNMENT EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=%ud:4, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:2>"
+info (non_smp) EMAC_LOG_DL_ASSIGNMENT EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ul:2, cc_idx=%ul:4, dl_harq_id=%ul:4, type=%ul:4, sps=%ul:2, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1%pl:12>"
+info (non_smp) EMAC_LOG_UL_GRANT EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=%ul:2, type=%ul:8, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3>"
+info (non_smp) EMAC_LOG_ASYNC_UL_GRANT EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=%ul:2, type=%ul:8, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3, async_harq_id=%ub, repetition=%ub>"
+info (non_smp) EMAC_LOG_PHICH EMAC_LV0_H "[EMAC][UL-HARQ] \n<phich: ul_cc_idx=%ud:2, harq_id=%ud:3, rlt=%ud:2%pd:1>"
+info (non_smp) EMAC_LOG_CRC_RESULT EMAC_LV0_H "[EMAC][DL-HARQ] \n<crc: cc_idx=%ud:4, dl_harq_id=%ud:4, tb_valid=%ud:1%ud:1, rlt=%ud:1%ud:1%pd:4>"
+info (non_smp) EMAC_LOG_TTI_INPUT EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=0, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1> \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=1, dl_harq_id_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0001 EMAC_LV0_H "[EMAC][DL-HARQ] \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0100 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=0, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0101 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=0, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=0, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_0111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=0, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1000 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1001 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<crc: cc_idx=0, dl_harq_id=%ul:4, tb_valid=%ul:1%ul:1, rlt=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<phich:%pl:1 ul_cc_idx=0, harq_id=%ul:3, rlt=%ul:2%pl:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10> \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1100 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=0, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1101 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=0, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=0, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC0_1111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=0, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=0, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=0, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=0, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0001 EMAC_LV0_H "[EMAC][DL-HARQ] \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0100 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=1, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0101 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=1, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=1, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_0111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=1, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1000 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1001 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<crc: cc_idx=1, dl_harq_id=%ul:4, tb_valid=%ul:1%ul:1, rlt=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<phich:%pl:1 ul_cc_idx=1, harq_id=%ul:3, rlt=%ul:2%pl:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10> \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1100 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=1, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1101 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=1, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=1, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC1_1111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=1, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=1, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=1, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=1, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0001 EMAC_LV0_H "[EMAC][DL-HARQ] \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0100 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=2, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0101 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=2, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=2, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_0111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=2, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1000 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1001 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<crc: cc_idx=2, dl_harq_id=%ul:4, tb_valid=%ul:1%ul:1, rlt=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<phich:%pl:1 ul_cc_idx=2, harq_id=%ul:3, rlt=%ul:2%pl:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10> \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1100 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=2, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1101 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=2, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=2, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC2_1111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=2, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=2, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=2, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=2, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0001 EMAC_LV0_H "[EMAC][DL-HARQ] \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0100 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=3, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0101 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=3, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=3, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_0111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=3, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1000 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1001 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<crc: cc_idx=3, dl_harq_id=%ul:4, tb_valid=%ul:1%ul:1, rlt=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<phich:%pl:1 ul_cc_idx=3, harq_id=%ul:3, rlt=%ul:2%pl:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1100 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=3, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1101 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=3, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=3, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC3_1111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=3, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=3, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=3, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0001 EMAC_LV0_H "[EMAC][DL-HARQ] \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<phich:%pb:1 ul_cc_idx=4, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<phich:%pb:1 ul_cc_idx=4, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0100 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=4, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0101 EMAC_LV0_H "[EMAC][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=4, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=4, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=4, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_0111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<dldci: t-%ud:2, cc_idx=4, dl_harq_id=%ud:4, type=1, sps=0, tb_valid=%ud:1%ud:1, new=%ud:1%ud:1%pd:6> \n<phich:%pb:1 ul_cc_idx=4, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1000 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1001 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<crc: cc_idx=4, dl_harq_id=%ul:4, tb_valid=%ul:1%ul:1, rlt=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1010 EMAC_LV0_H "[EMAC][UL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:2> \n<phich:%pl:1 ul_cc_idx=4, harq_id=%ul:3, rlt=%ul:2%pl:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1011 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3%pl:10> \n<phich:%pb:1 ul_cc_idx=4, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1100 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=4, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1101 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=4, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1110 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=4, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2>"
+info (non_smp) EMAC_LOG_TTI_INPUT_CC4_1111 EMAC_LV0_H "[EMAC][UL-HARQ][DL-HARQ] \n<uldci: t-%ul:2, ul_cc_idx=4, type=0, ndi=%ul:1, rv=%ul:2, tbs=%ul:14, k=%ul:3> \n<dldci: t-%ul:2, cc_idx=4, dl_harq_id=%ul:4, type=1, sps=0, tb_valid=%ul:1%ul:1, new=%ul:1%ul:1> \n<phich:%pb:1 ul_cc_idx=3, harq_id=%ub:3, rlt=%ub:2%pb:2> \n<crc: cc_idx=4, dl_harq_id=%ub:4, tb_valid=%ub:1%ub:1, rlt=%ub:1%ub:1>"
+
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_REACTIVE EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<harq status=%xl:5, buffer=%ul:3, bundle=%ul:3, rv=%ul:2, cnt=%ul:5, tbs=%ul:14> \n<retx time=%ul:5, phich time=%ul:5, uldci num=%ul:2, uldci1=%ul:5, uldci2=%ul:5%pl:10> \n<harq_id=%ub:4 close> \n<harq_id=%ub:4 activate>"
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_NEW_HARQ EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<harq status=%xl:5, buffer=%ul:3, bundle=%ul:3, rv=%ul:2, cnt=%ul:5, tbs=%ul:14> \n<retx time=%ul:5, phich time=%ul:5, uldci num=%ul:2, uldci1=%ul:5, uldci2=%ul:5%pl:10%pb:4> \n<harq_id=%ub:4 activate>"
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_RETX EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<harq status=%xl:5, buffer=%ul:3, bundle=%ul:3, rv=%ul:2, cnt=%ul:5, tbs=%ul:14> \n<retx time=%ul:5, phich time=%ul:5, uldci num=%ul:2, uldci1=%ul:5, uldci2=%ul:5%pl:10>"
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_FINAL EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<harq status=%xl:5, buffer=%ul:3, bundle=%ul:3, rv=%ul:2, cnt=%ul:5, tbs=%ul:14> \n<harq_id=%ub:4 close%pb:4>"
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_NEW_LAST EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<harq status=%xl:5, buffer=%ul:3, bundle=%ul:3, rv=%ul:2, cnt=%ul:5, tbs=%ul:14> \n<harq_id=%ub:4 close> \n<harq_id=%ub:4 activate>"
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_RETX_NOTX EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<retx time=%ul:5, phich time=%ul:5, uldci num=%ul:2, uldci1=%ul:5, uldci2=%ul:5%pl:10>"
+info (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_FINAL_NOTX EMAC_LV0_H "[EMAC][UL-HARQ] tx_req: ul_cc_idx=%ud:1 \n<ul status=%xd:2, type=%ud:4, harq_id=%ud:3, ndi=%ud:1, mode=%ud:2, ack=%ud:1, tx=%ud:1, mux=%ud:1> \n<harq_id=%ub:4 close>%pb:4"
+warn (non_smp) EMAC_LOG_TTI_UL_HARQ_INFO_DEFAULT EMAC_LV0_H "[EMAC][UL-HARQ][WARN] tx_req: ul_cc_idx=%ud:2 <ul status=%xd:2, type=%ud:4, harq_id=%ud:3, mode=%ud:2, tx=%ud:1, mux=%ud:1%pd:1> \n<harq status=%xl:5, buffer=%ul:3, bundle=%ul:3, rv=%ul:2, cnt=%ul:5, tbs=%ul:14> \n<retx time=%ul:5, phich time=%ul:5, uldci num=%ul:2, uldci1=%ul:5, uldci2=%ul:5%pl:10> \n<harq_id=%ub:4 close> \n<harq_id=%ub:4 activate>"
+
+// ============================================================================================================
+// CFG
+// ============================================================================================================
+info (non_smp) EMAC_LOG_CFG_RRC_RESET EMAC_LV0_H "[EMAC][CFG] EMAC reset"
+info (non_smp) EMAC_LOG_RA_CFG EMAC_LV0_H "[EMAC][CFG][RA] preamble_nb=%ub, group_a_size=%ub, group_b_size=%ub, msg_sz_group_a=%ub, rar_wnd=%ub, cr_timer=%ub"
+info (non_smp) EMAC_LOG_RA_CFG2 EMAC_LV0_H "[EMAC][CFG][RA] msg3_tx_max=%ub, pow_offset_b=%ub, pmax=%b, delta_msg3=%b"
+info (non_smp) EMAC_LOG_RA_CFG3 EMAC_LV0_H "[EMAC][CFG][RA] cc_idx=%ub, pow_ramping=%b, preamble_tx_max=%ub, preamble_init_pow=%b"
+info (non_smp) EMAC_LOG_CFG_SET_HO_CRNTI EMAC_LV0_H "[EMAC][CFG][HO] HO set c-rnti=%ud"
+info (non_smp) EMAC_LOG_CFG_SET_CRNTI EMAC_LV0_H "[EMAC][CFG] set c-rnti=%ud"
+info (non_smp) EMAC_LOG_CFG_STAG_TMR EMAC_LV0_H "[EMAC][CFG][TA] Config stag TA timer length=%ud"
+info (non_smp) EMAC_LOG_RRC_CFG EMAC_LV0_H "[EMAC][CFG] Function status=%xb, sr_prohibit_cnt=%ub, sr_prohibit_tmr=%ul, ta_timer_len=%ud"
+info (non_smp) EMAC_LOG_CFG_SR EMAC_LV0_H "[EMAC][CFG][SR] SR resource config: sr_offset=%ub, sr_period=%ub, sr_max=%ub"
+info (non_smp) EMAC_LOG_CFG_SR_RELEASE EMAC_LV0_H "[EMAC][CFG][SR] SR resource released"
+info (non_smp) EMAC_LOG_CFG_UL_SPS EMAC_LV0_H "[EMAC][CFG][SPS] UL SPS enable: ul_interval=%ud, imp_rel=%ub, two_interval=%ub, skip_tx=%ub, fixed_rv=%ub"
+info (non_smp) EMAC_LOG_CFG_UL_SPS_DISABLE EMAC_LV0_H "[EMAC][CFG][SPS] UL SPS disable"
+info (non_smp) EMAC_LOG_CFG_DL_SPS EMAC_LV0_H "[EMAC][CFG][SPS] DL SPS enable: dl_interval=%ud, dl_harq_num=%ub"
+info (non_smp) EMAC_LOG_CFG_DL_SPS_DISABLE EMAC_LV0_H "[EMAC][CFG][SPS] DL SPS disable"
+info (non_smp) EMAC_LOG_CFG_SET_SPSCRNTI EMAC_LV0_H "[EMAC][CFG][SPS] Set spsc-rnti=%ud"
+info (non_smp) EMAC_LOG_CFG_CLR_SPSCRNTI EMAC_LV0_H "[EMAC][CFG][SPS] Clear spsc-rnti"
+info (non_smp) EMAC_LOG_CFG_PCELL_CFG EMAC_LV0_H "[EMAC][CFG] Pcell subframe_cfg=%ub"
+info (non_smp) EMAC_LOG_CFG_SCELL_UPDATE EMAC_LV0_H "[EMAC][CFG][SCELL] Update cc_idx=%ub, corss_sched_idx=%ub"
+info (non_smp) EMAC_LOG_CFG_PHR EMAC_LV0_H "[EMAC][CFG][PHR] phr_config=%ub (0: disable, 1: phr, 2: extend_phr)"
+info (non_smp) EMAC_LOG_CFG_UL_HARQ EMAC_LV0_H "[EMAC][CFG][UL-HARQ] max_harq_tx=%ub, tti_bundling_config=%ub (0: disable, 1: normal bundling, 2: enhanced fdd)"
+info (non_smp) EMAC_LOG_CFG_UL_HARQ_PUSCH_ENHANCEMENT EMAC_LV0_H "[EMAC][CFG][UL-HARQ] pusch enhancement mode=%ub"
+info (non_smp) EMAC_LOG_CFG_UL_HARQ_SKIP_DYNAMIC_TX EMAC_LV0_H "[EMAC][CFG][UL-HARQ] skip dynamic tx: %ub"
+info (non_smp) EMAC_LOG_CELL_INFO EMAC_LV0_H "[EMAC][CFG]sch_open=%ub, earfcn=%ul, pci=%ud"
+// ============================================================================================================
+// UL HARQ
+// ============================================================================================================
+
+
+// ============================================================================================================
+// TA
+// ============================================================================================================
+info (non_smp) EMAC_LOG_RCV_TA_CMD EMAC_LV0_H "[EMAC][TA] ta_cmd: ta_value=%ub:6, tag_id=%ub:2, rcv_time=%ul"
+info (non_smp) EMAC_LOG_P_TA_EXP EMAC_LV0_H "[EMAC][TA] ptag TA timer expired"
+info (non_smp) EMAC_LOG_RAR_TA_CMD EMAC_LV0_H "[EMAC][TA] RAR ta_cmd: ta_value=%ub, tag_id=%ub, rcv_time=%ul"
+info (non_smp) EMAC_LOG_TA_STOP_FOR_CR_FAIL EMAC_LV0_H "[EMAC][TA] Stop ptag TA timer for RA CR fail"
+info (non_smp) EMAC_LOG_S_TA_EXP EMAC_LV0_H "[EMAC][TA] stag TA timer expire: tag_id=%ub, cc_idx_bmp=%xb, cur_cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_ADD_STAG_CC EMAC_LV0_H "[EMAC][CFG][TA] Add stag CC: tag_id=%ub, cc_idx=%ub, stag_idx=%ub, cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_ADD_PTAG_CC EMAC_LV0_H "[EMAC][CFG][TA] Add ptag CC: cc_idx=%ub, cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_DEL_PTAG_CC EMAC_LV0_H "[EMAC][CFG][TA] Del ptag CC: cc_idx=%ub, cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_DEL_STAG_CC EMAC_LV0_H "[EMAC][CFG][TA] Del stag CC: tag_id=%ub, cc_idx=%b, stag_idx=%b, cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_P_TIMER_START EMAC_LV0_H "[EMAC][TA] ptag TA timer start=%ul, length=%ud, cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_S_TIMER_START EMAC_LV0_H "[EMAC][TA] stag TA timer tag_id=%ub start=%ul, length=%ud, cc_idx_bmp=%xb"
+info (non_smp) EMAC_LOG_TA_S_TA_ALL_EXP EMAC_LV0_H "[EMAC][TA] all stag TA timers expire"
+// ============================================================================================================
+// SCELL
+// ============================================================================================================
+info (non_smp) EMAC_LOG_SCELL_DEACT EMAC_LV0_H "[EMAC][SCELL] Scell deactivate: cc_idx=%ub"
+info (non_smp) EMAC_LOG_SCELL_DEACT_TIMER_EXP EMAC_LV0_H "[EMAC][SCELL] Scell deactivation timer expired: cc_idx=%ub"
+info (non_smp) EMAC_LOG_SCELL_ACT EMAC_LV0_H "[EMAC][SCELL] Scell activate: cc_idx=%ub, deactivation timer start=%ul, length=%ul"
+info (non_smp) EMAC_LOG_SCELL_RCV_CMD EMAC_LV0_H "[EMAC][SCELL] Rcv scell act_cmd=%xb: rcv_time=%ul"
+info (non_smp) EMAC_LOG_SCELL_ADD_CC EMAC_LV0_H "[EMAC][SCELL][CFG] Add CC: scell_idx=%ub, cc_idx=%ub, tag_id=%ub, corss_sched_idx=%ub, subframe_cfg=%ub, ul_ref_cfg=%ub, ul_supported=%ub"
+info (non_smp) EMAC_LOG_SCELL_REL_CC EMAC_LV0_H "[EMAC][SCELL][CFG] Rel CC: cc_idx=%ub"
+
+// ============================================================================================================
+// BSR & SR
+// ============================================================================================================
+info (non_smp) EMAC_LOG_BSR_TRIGGER EMAC_LV0_H "[EMAC][BSR] BSR triggered: regular=%ub:1, retx_regular=%ub:1, period=%ub:1%pb:5, top_rb=%ub"
+info (non_smp) EMAC_LOG_BSR_CANCEL EMAC_LV0_H "[EMAC][BSR] BSR cancel"
+info (non_smp) EMAC_LOG_BSR_LC_SR_TMR_START EMAC_LV0_H "[EMAC][BSR][SR] LC SR prohibit timer start=%ul, length=%ud"
+info (non_smp) EMAC_LOG_BSR_LC_SR_TMR_STOP EMAC_LV0_H "[EMAC][BSR][SR] LC SR prohibit timer stopped"
+info (non_smp) EMAC_LOG_BSR_LC_SR_TMR_EXPIRE EMAC_LV0_H "[EMAC][BSR][SR] LC SR prohibit timer expired"
+info (non_smp) EMAC_LOG_SR_TRIGGERED EMAC_LV0_H "[EMAC][SR] SR triggered"
+info (non_smp) EMAC_LOG_SR_CANCEL EMAC_LV0_H "[EMAC][SR] SR cancel: sr_count=%ub"
+info (non_smp) EMAC_LOG_SR_TX EMAC_LV0_H "[EMAC][SR] SR tx_cnt=%ub, prohibit timer start=%ul, length=%ud (0: no prohibit)"
+warn (non_smp) EMAC_SR_LOG_SR_TX_MAX EMAC_LV0_H "[EMAC][SR][WARN] SR tx max, tx_cnt=%ub"
+
+// ============================================================================================================
+// RA
+// ============================================================================================================
+info (non_smp) EMAC_RA_LOG_TRIG_READY EMAC_LV0_H "[EMAC][RA] RA trigger ready: ra_event=%Memac_ra_event_e, ra_type=%Memac_ra_type_e, preamble_tx_max=%b"
+info (non_smp) EMAC_RA_LOG_PREAM_SCHED_TX EMAC_LV0_H "[EMAC][RA] schedule preamble tx: ul_cc_idx=%b, rapid=%b, preamble_tx_cnt=%l, format=%b, tx_prb=%b"
+info (non_smp) EMAC_RA_LOG_PREAM_TX EMAC_LV0_H "[EMAC][RA] <state = WAIT_RAR> preamble tx, ra-rnti=%d, RAR WND start=%l, end=%l"
+info (non_smp) EMAC_RA_LOG_RAR_WND_END EMAC_LV0_H "[EMAC][RA] RAR WND end, RAR fail"
+info (non_smp) EMAC_RA_LOG_RAR_MATCH_INFO_CF EMAC_LV0_H "[EMAC][RA][UL-HARQ] RAR matched: ta_cmd=%l, tc-rnti=%d, tx_time=%ul, tbs=%ud"
+info (non_smp) EMAC_RA_LOG_RAR_MATCH_INFO_CB EMAC_LV0_H "[EMAC][RA][UL-HARQ] <state = WAIT_MSG3_TX> RAR matched: ta_cmd=%ul, tc-rnti=%ud, msg3_tx_time=%ul, tbs=%ud"
+
+info (non_smp) EMAC_RA_LOG_MSG3_TX EMAC_LV0_H "[EMAC][RA] <state = WAIT_CR> MSG3 TX, CR timer start=%l, end=%l"
+info (non_smp) EMAC_RA_LOG_MSG3_RETX EMAC_LV0_H "[EMAC][RA][UL-HARQ] MSG3 RETX: CR timer restart end=%l"
+info (non_smp) EMAC_RA_LOG_CR_EXPIRE EMAC_LV0_H "[EMAC][RA] CR timer expire"
+
+info (non_smp) EMAC_RA_LOG_RETRY EMAC_LV0_H "[EMAC][RA] <state = WAIT_PREAMBLE_TX> RA retry, preamble_tx_cnt=%l, ra_error_cnt=%l, backoff_time=%l"
+info (non_smp) EMAC_RA_LOG_COMPLETE EMAC_LV0_H "[EMAC][RA] <state = WAIT_GAP_RESUME> RA complete, is_success=%b"
+info (non_smp) EMAC_RA_LOG_PDCCH_ORDER_INACT_CC EMAC_LV0_H "[EMAC][RA][WARN] rcv PDCCH order for inactive Scell: ul_cc_idx=%b"
+info (non_smp) EMAC_RA_LOG_PDCCH_ORDER_INVALID EMAC_LV0_H "[EMAC][RA][WARN] rcv invalid PDCCH order: ul_cc_idx=%b, rapid=%b"
+info (non_smp) EMAC_RA_LOG_PDCCH_ORDER_WHEN_RESET EMAC_LV0_H "[EMAC][RA][WARN] rcv PDCCH order in MAC reset: ul_cc_idx=%b, rapid=%b"
+info (non_smp) EMAC_RA_LOG_PDCCH_ORDER_INFO EMAC_LV0_H "[EMAC][RA] rcv PDCCH order: ul_cc_idx=%b, rapid=%b, mask=%b, tx_time=%l"
+info (non_smp) EMAC_RA_LOG_HO_CFG EMAC_LV0_H "[EMAC][RA] rcv HO RA cfg: rapid=%b, mask=%b"
+warn (non_smp) EMAC_RA_LOG_RA_ERROR_IND EMAC_LV0_H "[EMAC][RA][WARN] RA error ind"
+
+// ============================================================================================================
+// PHR
+// ============================================================================================================
+info (non_smp) EMAC_LOG_PHR_TRIGGERED EMAC_LV0_H "[EMAC][PHR] PHR triggered type=%Memac_phr_triggered_enum"
+
+// ============================================================================================================
+// DRX
+// ============================================================================================================
+info (non_smp) EMAC_DRX_LOG_NORMAL_NEXT_ONDU_INFO EMAC_LV0_H "[EMAC][DRX] (normal) ondu tmr: start_time=%ul and expired_time=%ul, next ondu tmr: start_time=%ul and expired_time=%ul, cur_predict_cycle=%Memac_drx_cycle_type_e, next_predict_cycle=%Memac_drx_cycle_type_e"
+info (non_smp) EMAC_DRX_LOG_DCI_START_DRX_INACT_TMR EMAC_LV0_H "[EMAC][DRX] dci starts drx inact tmr: start_time=%ul"
+info (non_smp) EMAC_DRX_LOG_DRX_INACT_TMR_END EMAC_LV0_H "[EMAC][DRX] drx inact tmr ends, expired_time=%ul"
+info (non_smp) EMAC_DRX_LOG_SHORT_CYC_TMR_START EMAC_LV0_H "[EMAC][DRX] short cycle tmr: start_time=%ul, expired_time=%ul"
+info (non_smp) EMAC_DRX_LOG_DRX_CONFIG EMAC_LV0_H "[EMAC][DRX][CFG] drx_config=%ub (0: enable, 1: reconfig, 2: disable): \ncqi_mask=%ub, \nshort_cycle_valid=%ub, \ndrx_ul_retx_tmr_valid=%ub, \ndrx_ul_retx_tmr_psf_len=%ud, \ndrx_retx_tmr_psf_len=%ud, \ndrx_short_cycle_num=%ub, \nondu_tmr_psf_len=%ud, \ndrx_short_cycle_tmr_len=%ud, \ndrx_inact_tmr_psf_len=%ud, \ndrx_long_cycle=%ud, \ndrx_short_cycle=%ud, \ndrx_long_offset=%ud, \ndrx_short_offset=%ud"
+info (non_smp) EMAC_DRX_LOG_CRC_SET_RTT_RETX_STATUS EMAC_LV0_H "[EMAC][DRX] sets rtt/retx status: cc_idx=%ub, dl_harq_id=%ub, retx tmr start_time=%ul, retx tmr expired_time=%ul"
+info (non_smp) EMAC_DRX_LOG_CLR_RETX_STATUS EMAC_LV0_H "[EMAC][DRX] clears retx status: cc_idx=%ub, dl_harq_id=%ub, source=%ub (0: dci, 1: crc)"
+info (non_smp) EMAC_DRX_LOG_CLR_RTT_STATUS EMAC_LV0_H "[EMAC][DRX] clears rtt status: cc_idx=%ub, dl_harq_id=%ub, source=%ub (0: dci, 1: crc)"
+
+
+// ============================================================================================================
+// RBRQ
+// ============================================================================================================
+info (non_smp) EMAC_LOG_RBRQ_TRIGGERED EMAC_LV0_H "[EMAC][RBRQ] rbrq is triggered: rb_idx=%ub, is_ul=%ub, rbrq=%ul"
+info (non_smp) EMAC_LOG_RBRQ_SCHEDULED EMAC_LV0_H "[EMAC][RBRQ] rbrq is sched: rb_idx=%ub, lcid=%ub, is_ul=%ub, rbrq=%ul, prohibit_time=%ul"
+
+info EMAC_ERT_LOG_RBRQ_SUPPORT_BITMAP EMAC_LV0_H "[EMAC][RBRQ] rbrq support_rb_idx_bitmap=%ul"
+// ============================================================================================================
+// EMUX
+// ============================================================================================================
+
+// Read MUX REQ
+info EMUX_LOG___MUX_REQ EMAC_LV0_H "[EMAC][EMUX][IF] MUX_REQ: pidx=%ub, cc_idx=%ub, harq_id=%ub, tbs=%ud, first_mux=%Mkal_bool"
+
+// Gen front TB
+info EMUX_LOG___MUX_BUF_1 EMAC_LV0_H "[EMAC][EMUX][TB] tbs_in_mux_buf=%ul mux_buf= %xb %xb %xb %xb"
+info EMUX_LOG___PAD_BUF_1 EMAC_LV0_H "[EMAC][EMUX][TB] post_pad_len =%ul pad_buf= %xb %xb %xb %xb"
+
+// LCP
+info EMUX_LOG___LCP_REQ EMAC_LV0_H "[EMAC][EMUX][LCP] Lcp req: c-rnti=%Memux_crnti_status_e, bsr=%Memux_bsr_status_e, phr=%Memux_phr_status_e, phr_len=%ub, ccch=%Memux_ccch_status_e"
+info EMUX_LOG___LCG_AFTER_LCP EMAC_LV0_H "[EMAC][EMUX][LCP] After lcp: lcg_buf_num=%ub, lcg_buf_size=[%ul, %ul, %ul, %ul], top_lcg_id=%ub, top_priority=%ub"
+info EMUX_LOG___AFTER_MAC_LCP_A EMAC_LV0_H "[EMAC][EMUX][LCP] After mac lcp: cc_idx=%ub, harq_id=%ub"
+info EMUX_LOG___AFTER_RLC_LCP_A EMAC_LV0_H "[EMAC][EMUX][LCP] After rlc lcp: cc_idx=%ub, harq_id=%ub"
+
+// Write MUX_RSP
+info EMUX_LOG___MUX_RSP EMAC_LV0_H "[EMAC][EMUX][MR] MUX_RSP: cc_idx=%ub, c-rnti=%Memux_crnti_status_e, bsr=%Memux_bsr_status_e(%Memux_bsr_format_e), phr=%Memux_phr_status_e, ccch=%Memux_ccch_status_e, dxch=%Memux_dxch_status_e"
+
+// Close UL Harq
+info EMUX_LOG___CLOSE_UL_HARQ EMAC_LV0_H "[EMAC][EMUX][IF] Close UL harq: pidx=%ub, ul_cc_idx=%ub, harq_id=%ub"
+
+// Config
+info EMUX_LOG___CFG EMAC_LV0_H "[EMAC][EMUX][IF] Config: pidx=%ub, ebsr=%Mkal_bool"
+
+
+// ============================================================================================================
+// EMACDL
+// ============================================================================================================
+info EMACDL_LOG_TB_TYPE_REF EMAC_LV0_H "[EMAC][DL][INFO] TB type mapping - 0:C/SPS, 1:MCH, 4:RAR, 7:TC"
+info EMACDL_LOG_TB_INFO_SINGLE EMAC_LV0_H "[EMAC][DL][TB] \n<TB %ub: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_1 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_2 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_3 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 3: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_4 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 3: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 4: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_5 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 3: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 4: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 5: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_6 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 3: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 4: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 5: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 6: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_7 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 3: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 4: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 5: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 6: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 7: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_TB_INFO_8 EMAC_LV0_H "[EMAC][DL][TB] \n<TB 1: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 2: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 3: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 4: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 5: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 6: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 7: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16> \n<TB 8: crc=%ul:1,%pl:3 type=%ul:3,%pl:1 tb=%ul:1, cc=%ul:3, harq=%ul:4, len=%ul:16>"
+info EMACDL_LOG_UEID_MISMATCH EMAC_LV0_H "[EMAC][DL][RA] UEID mismatch at abs_time=%ul"
+info EMACDL_LOG_UEID_MATCH EMAC_LV0_H "[EMAC][DL][RA] UEID match at abs_time=%ul"
+info EMACDL_LOG_RCV_TCRNTI_NO_UEID EMAC_LV0_H "[EMAC][DL][RA][WARN] No UEID at abs_time=%ul"
+info EMACDL_LOG_RCV_TCRNTI_INVALID_TB EMAC_LV0_H "[EMAC][DL][RA][WARN] TC-RNTI header parse fail at abs_time=%ul"
+
+// ============================================================================================================
+// MCH
+// ============================================================================================================
+// ILM Mxch cfg req (RRC)
+info EMACMCH_T_LOG___RELEASE_MCCH EMAC_LV0_H "[EMAC][MCH][T][MXCH] Release MCCH: said=%ub, aid=%ub, mcch_idx=%ub"
+info EMACMCH_T_LOG___RELEASE_MTCH EMAC_LV0_H "[EMAC][MCH][T][MXCH] Release MTCH: said=%ub, aid=%ub, pmch_id=%ub, lcid=%ub, mtch_idx=%ub"
+info EMACMCH_T_LOG___ESTABLISH_MCCH EMAC_LV0_H "[EMAC][MCH][T][MXCH] Establish MCCH: said=%ub, aid=%ub, mcch_idx=%ub"
+info EMACMCH_T_LOG___ESTABLISH_MTCH EMAC_LV0_H "[EMAC][MCH][T][MXCH] Establish MTCH: said=%ub, aid=%ub, pmch_id=%ub, lcid=%ub, mtch_idx=%ub"
+
+// ILM Data ind (EMACDL)
+info EMACMCH_T_LOG___RCV_DATA_IND EMAC_LV0_H "[EMAC][MCH][T][ILM] Rcv DATA_IND: active_pidx=%ub, trans_pidx=%ub, tb_rcv_abs_time=%ul"
+
+// - Get PDU info from TB info
+info EMACMCH_T_LOG___PDU_INFO_BY_TB_INFO EMAC_LV0_H "[EMAC][MCH][T][PDU] TB_INFO: said=%ub, tbs=%ul, rcv_cell_time=%ul"
+
+// - Get PDU info from MAC subheader
+info EMACMCH_T_LOG___SHDR_PRE_PAD EMAC_LV0_H "[EMAC][MCH][T][PDU] Shdr: pre-padding shdr=%xb"
+info EMACMCH_T_LOG___SHDR_3OCT EMAC_LV0_H "[EMAC][MCH][T][PDU] Shdr : lcid=%ub, len=%ul, payload_ofs=%ul, shdr=%xb %xb %xb"
+info EMACMCH_T_LOG___SHDR_2OCT EMAC_LV0_H "[EMAC][MCH][T][PDU] Shdr : lcid=%ub, len=%ul, payload_ofs=%ul, shdr=%xb %xb"
+info EMACMCH_T_LOG___SHDR_LAST EMAC_LV0_H "[EMAC][MCH][T][PDU] ShdrLast: lcid=%ub, len=%ul, payload_ofs=%ul, shdr=%xb"
+
+
+// - Process MSI CE
+info EMACMCH_T_LOG___MSI_PROCESS EMAC_LV0_H "[EMAC][MCH][T][PDU] MSI processing: msi_len=%ul"
+info EMACMCH_T_LOG___MSI_SCHED_PAIR_NUM EMAC_LV0_H "[EMAC][MCH][T][PDU] MSI: schedule_pair_num=%ul"
+info EMACMCH_T_LOG___MSI_SCHED_PAIR EMAC_LV0_H "[EMAC][MCH][T][PDU] MSI: lcid=%ub, stop_mtch=%ud"
+info EMACMCH_T_LOG___UPDATE_MSI_INPUT_B EMAC_LV0_H "[EMAC][MCH][T][PDU] Update msi(): mi=%ul, start=%ud, end=%ud"
+info EMACMCH_T_LOG___UPDATE_MSI_INPUT_A EMAC_LV0_H "[EMAC][MCH][T][PDU] Update msi(): said=%ub, aid=%ub, pmch_id=%ub, sf_no=%ul"
+
+// - Process MSI CE for MTCH suspend
+info EMACMCH_T_LOG___MSI_SUSPEND_PAIR_NUM EMAC_LV0_H "[EMAC][MCH][T][PDU] MSI: suspend_pair_num=%ul, is_cfg_pmch_info_list_ext=%Mkal_bool"
+info EMACMCH_T_LOG___MSI_SUSPEND_PAIR EMAC_LV0_H "[EMAC][MCH][T][PDU] MSI: lcid=%ub"
+
+// - Process MCCH
+info EMACMCH_T_LOG___MCCH_PROCESS EMAC_LV0_H "[EMAC][MCH][T][PDU] MCCH processing: mcch_idx=%ub, mxch_info=%ub"
+
+// - Process MTCH
+info EMACMCH_T_LOG___MTCH_PROCESS EMAC_LV0_H "[EMAC][MCH][T][PDU] MTCH processing: mtch_idx=%ub, mxch_info=%ub"
+
+// - Send ILM to ERLCDL
+info EMACMCH_T_LOG___SND_MCH_DATA_IND EMAC_LV0_H "[EMAC][MCH][T][ILM] Snd MCH_DATA_IND: mbms_pdu_num=%ub"
+
+
+// Query next mch
+info (non_smp) EMACMCH_L_LOG___QUERY_NEXT_MCH EMAC_LV0_H "[EMAC][MCH][L][IF] Query next mch: abs_time=%ul, sa_id=%ub, active_pidx=%ub, input_pidx=%ub"
+info (non_smp) EMACMCH_L_LOG___LOOK_UP_NEXT_PS EMAC_LV0_H "[EMAC][MCH][L][QURY] Skip this ps due to filterout or out-of-date"
+info (non_smp) EMACMCH_L_LOG___QUERY_OUTPUT_B EMAC_LV0_H "[EMAC][MCH][L][QURY] Next mch: said=%ub aid=%ub, pmch_id=%ub, non_mbsfn_region_len=%ub, is_mch_reliable=%Mkal_bool"
+info (non_smp) EMACMCH_L_LOG___QUERY_OUTPUT_C EMAC_LV0_H "[EMAC][MCH][L][QURY] Next mch: is_higher_order_mcs=%Mkal_bool, is_signal_mcs=%Mkal_bool, mcs=%ub"
+info (non_smp) EMACMCH_L_LOG___QUERY_OUTPUT_E EMAC_LV0_H "[EMAC][MCH][L][QURY] Next mch: sf_no=%ul, abs_time=%ul"
+
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_internal.tmd b/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_internal.tmd
new file mode 100644
index 0000000..75313db
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_internal.tmd
@@ -0,0 +1,75 @@
+[Default]
+ERLCDL_INTERNAL
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 16
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+ERLCDL_RB_M ON
+ERLCDL_RB_L ON
+ERLCDL_WARN_UH ON
+ERLCDL_WARN_H ON
+ERLCDL_WARN_M ON
+ERLCDL_ERROR_UH ON
+ERLCDL_ERROR_H ON
+ERLCDL_CONFIG_H ON
+ERLCDL_CONFIG_M ON
+ERLCDL_TIMER_L ON
+ERLCDL_TIMER_UL ON
+ERLCDL_DEBUG_UH ON
+ERLCDL_DEBUG_L ON
+ERLCDL_MBMS_UH ON
+ERLCDL_MBMS_M ON
+
+[String]
+
+[Message]
+
+/********************************** FUNC LEVEL, INTERFACE TRACE **********************************/
+info ERLCDL_LOG_INIT ERLCDL_DEBUG_L "[ERLCDL] initialization"
+info ERLCDL_LOG_DLSCH_DATA_IND ERLCDL_DEBUG_L "[ERLCDL] DL-SCH data indication (pdu_num=%ub)"
+info ERLCDL_LOG_MCH_DATA_IND ERLCDL_DEBUG_L "[ERLCDL] MCH data indication (pdu_num=%ub)"
+
+/********************************** CONFIGURATION TRACE **********************************/
+// RB configuration
+info ERLCDL_LOG_VOLTE_RB_NTF ERLCDL_CONFIG_M "[ERLCDL][RB] VoLTE RB notification (cur_pid=%ub,cur_volte_rb_idx=%ub,pid=%ub,volte_rb_idx=%ub)"
+warn ERLCDL_LOG_INVALID_PID ERLCDL_WARN_UH "[ERLCDL][RB] receive configuration with invalid PID (cur_pid=%ub,trans_pid=%ub)"
+warn ERLCDL_LOG_FORCE_SET_UM_REODR_TMR ERLCDL_WARN_UH "[ERLCDL][RB][WARN] Force set UM t-Reordering timer (rb_idx=%ub,old_tmr=%ud,new_tmr=%ud,case=%ub)"
+
+// MBMS RB configuration
+info ERLCDL_LOG_MBMS_SUSPEND ERLCDL_MBMS_UH "[ERLCDL][RB][MBMS] release all MCCH and MRB by RSVAS (mbms_bmp=%ul)"
+info ERLCDL_LOG_MBMS_SUSPEND_SKIP ERLCDL_MBMS_UH "[ERLCDL][RB][MBMS] skip the service suspend"
+
+/********************************** RX DATA ROUTINE TRACE **********************************/
+// RX data error trace
+warn ERLCDL_LOG_SDU_LEN_OVERFLOW ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] SDU len overflow (len=%ud)"
+warn ERLCDL_LOG_PDU_SO_UNREASN ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] unreasonable SO (rb_idx=%ub,len=%ud,sn=%ud,so=%ud)"
+warn ERLCDL_LOG_MBMS_INVALID_PID ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] rx mbms with invalid PID (cur_pid=%ub,trans_pid=%ub)"
+warn ERLCDL_LOG_EXT_PDU_BUF_SHORTAGE ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] ext PDU buffer shortage"
+warn ERLCDL_LOG_EXT_SLI_BUF_OVERFLOW ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] ext SLI buffer overflow"
+warn ERLCDL_LOG_SLI_OVERFLOW ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] discard SDU SEGs (hdr_len=%ud,data_len=%ud,disc_len=%ud,disc_sdu_cnt=%ud)"
+warn ERLCDL_LOG_SLI_BUF_OVERFLOW ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] SLI buf overflow"
+warn ERLCDL_LOG_SRB_PDU_BUF_SHORTAGE ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] SRB PDU buffer shortage, try DRB PDU pool (rb_idx=%ub)"
+warn ERLCDL_LOG_PDU_BUF_WARNNING_1 ERLCDL_WARN_UH "[ERLCDL][PDU][WARN] PDU buffer allocation failed but there are PDU buffers (cur_used=%ud/%ud)"
+
+/********************************** MTK PROPRIETARY FEATURE TRACE **********************************/
+// DL RLF workaround
+error ERLCDL_LOG_REPEAT_PDU_RLF ERLCDL_ERROR_UH "[ERLCDL][PDU][ERROR] repeat PDU RLF (rb_idx=%ud:6,sn=%ud:10,so=%ud,repeat_cnt=%ub)"
+
+// UM5 OOW insepction
+warn ERLCDL_LOG_UM5_PDU_ODR_TS_INVALID ERLCDL_WARN_UH "[ERLCDL][PDU][ERROR] UM5 PDU order inspect: invalid timestamp (rb_idx=%ub,rlc_sn=%ub,reasm_ts_last=%ul,pdu_ts=%ul)"
+info ERLCDL_LOG_UM5_PDU_ODR_TS_PDCP_SN ERLCDL_WARN_M "[ERLCDL][PDU] UM5 PDU order inspect: dump information (rb_idx=%ub,rlc_sn=%ub,pdu_ts=%ul,pdcp_sn_first=%ud,pdcp_sn_last=%ud)"
+info ERLCDL_LOG_UM5_PDU_ODR_NO_PDCP_HDR ERLCDL_WARN_M "[ERLCDL][PDU] UM5 PDU order inspect: no PDCP header (rb_idx=%ub,rlc_sn=%ub,pdu_ts=%ul)"
+warn ERLCDL_LOG_UM5_PDU_ODR_PDCP_OOW ERLCDL_WARN_M "[ERLCDL][PDU][WARN] UM5 PDU order inspect: PDCP SN OOW (rb_idx=%ub,rlc_sn=%ub,pdcp_sn_next=%ud,pdcp_sn_first=%ud,pdcp_sn_last=%ud)"
+
+// Aggregation trace timer inject
+info ERLCDL_LOG_AGG_TMR_SET ERLCDL_DEBUG_UH "[ERLCDL] Aggregation trace timer period update (timer = %ud ms)"
+
+// status re-transmission
+info ERLCDL_LOG_STATUS_PDU_TX_FAIL ERLCDL_RB_M "[ERLCDL][RPT] STATUS PDU tx failure (rb_idx=%ub)"
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_protect.tmd b/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_protect.tmd
new file mode 100644
index 0000000..3a23d86
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_protect.tmd
@@ -0,0 +1,94 @@
+[Default]
+ERLCDL_PROTECT
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 16
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+ERLCDL_SRB_H ON
+ERLCDL_SRB_M ON
+ERLCDL_SRB_L ON
+ERLCDL_SRB_UL ON
+ERLCDL_DRB_H ON
+ERLCDL_DRB_M ON
+ERLCDL_DRB_L ON
+ERLCDL_DRB_UL ON
+ERLCDL_RB_M ON
+ERLCDL_RB_L ON
+ERLCDL_WARN_UH ON
+ERLCDL_WARN_H ON
+ERLCDL_WARN_M ON
+ERLCDL_ERROR_UH ON
+ERLCDL_ERROR_H ON
+ERLCDL_CONFIG_H ON
+ERLCDL_CONFIG_M ON
+ERLCDL_TIMER_L ON
+ERLCDL_TIMER_UL ON
+ERLCDL_DEBUG_H ON
+ERLCDL_DEBUG_M ON
+ERLCDL_DEBUG_L ON
+ERLCDL_MBMS_M ON
+
+
+[String]
+
+[Message]
+
+/********************************** L2 COPRO RELATED TRACE **********************************/
+// Reassemble process
+info ERLCDL_LOG_PRSB_UNDO1 ERLCDL_DEBUG_M "[ERLCDL][RSB][DISC] discard incomplete SDU (len=%ud,n_seg=%ud) before PDU(sn=%ud)"
+info ERLCDL_LOG_PRSB_DISC_1st_SDU ERLCDL_DEBUG_M "[ERLCDL][RSB][DISC] discard the first SDU segment(len=%ud) of PDU(sn=%ud)"
+warn ERLCDL_LOG_PRSB_DISC_INVALID_PDU ERLCDL_WARN_M "[ERLCDL][RSB][WARN] skip invalid pdu (sn=%ud)"
+warn ERLCDL_LOG_PRSB_INCMPLT_SEG ERLCDL_WARN_M "[ERLCDL][RSB][WARN] pdu so(%ud) is not expected so(%ud)"
+info ERLCDL_LOG_PRSB_FILL_RSMT ERLCDL_DEBUG_M "[ERLCDL][RSB] write a reassemble entry (flow_idx=%ud:8,rsb_idx=%ud:8,sdu_num=%ul:16,seg_num=%ul:16,sdu_len=%ul)(incmplt seg=%ul:16, len=%ul:16)"
+info ERLCDL_LOG_PRSB_FILL_FLUSH ERLCDL_DEBUG_M "[ERLCDL][RSB] write a reassemble entry for re-establish (flow_idx=%ud:8, rsb_idx=%ud:8)"
+warn ERLCDL_LOG_PRSB_RSMT_FULL ERLCDL_WARN_M "[ERLCDL][RSB][WARN] RSMT full!! (flow_idx=%ub, rsb_next_idx=%ud)"
+info ERLCDL_LOG_PRSB_DISC_REASM_PDU ERLCDL_DEBUG_M "[ERLCDL][RSB] discard all pending PDUs during flush procedure (flow_idx=%ub,sdu_num=%d, seg_num=%ud,sdu_len=%ul)(incmplt seg=%ud, len=%ud)"
+info ERLCDL_LOG_CRSB_REL_RSMT_EL2 ERLCDL_DEBUG_M "[ERLCDL][RSB] release remaining rsmt entries (flow_idx=%ub,release range=[%ub,%ub))"
+info ERLCDL_LOG_CRSB_REL_RSMT_EL2H ERLCDL_DEBUG_M "[ERLCDL][RSB] release remaining rsmt entries (flow_idx=%ub,release range=[%ub,%ub))"
+info ERLCDL_LOG_CRSB_NML_RSB ERLCDL_DEBUG_M "[ERLCDL][RSB] reassemble RLC SDU(flow_idx=%ud:5,v=%ud:1,rsb_next_idx=%ud:10,dcit_write_idx=%ub)"
+info ERLCDL_LOG_CRSB_MBMS_RSB ERLCDL_DEBUG_M "[ERLCDL][MBMS][RSB] reassemble MBMS SDU(flow_idx=%ud:5,v=%ud:1,rsb_next_idx=%ud:10,dcit_write_idx=%ub)"
+info ERLCDL_LOG_CRSB_SRB_RSB ERLCDL_DEBUG_M "[ERLCDL][RSB] reassemble one SRB RLC SDU(flow_idx=%ud:5,v=%ud:1,rsb_next_idx=%ud:10,dcit_write_idx=%ub)"
+info ERLCDL_LOG_CRSB_LWA_RSB ERLCDL_DEBUG_M "[ERLCDL][RSB] reassemble LWA SDU(flow_idx=%ud:5,lwa_next_idx=%ud:11,dcit_write_idx=%ub)"
+info ERLCDL_LOG_CRSB_NML_DESC1 ERLCDL_DEBUG_M "[ERLCDL][RSB] start fill normal descriptor for pdu (n_skip=%ub,n_sli=%ub,vrb_len=%ud,vrb_addr=%xl)"
+info ERLCDL_LOG_CRSB_NML_DESC2 ERLCDL_DEBUG_M "[ERLCDL][RSB] fill normal descriptor (len=%ul:15,free=%ul:1,vrb_ofst=%ul:14,cont=%ul:2)"
+info ERLCDL_LOG_CRSB_START_DECIP ERLCDL_DEBUG_M "[ERLCDL][RSB] start cipher copro (wc=%ud, dec_write_idx=%ud)"
+info ERLCDL_LOG_CRSB_NML_LIST ERLCDL_DEBUG_M "[ERLCDL][RSB] start to reassemble a rsmt (rsmt_idx=%ud,dec_write_idx=%ud)"
+warn ERLCDL_LOG_CRSB_WC_SHORTAGE1 ERLCDL_WARN_M "[ERLCDL][RSB][WARN] cannot completely serve the entry (flags=%xl:8,flow_idx=%ul:8,n_sdu=%ul:16,n_seg=%ud,sdu_len=%ul)"
+warn ERLCDL_LOG_CRSB_WC_SHORTAGE2 ERLCDL_WARN_M "[ERLCDL][RSB][WARN] truncate result (flags=%xl:8,flow_idx=%ul:8,n_sdu=%ul:16,n_seg=%ud,sdu_len=%ul)"
+warn ERLCDL_LOG_CRSB_WC_SHORTAGE3 ERLCDL_WARN_M "[ERLCDL][RSB][WARN] not enough word count(remain_wc=%ud, dec_write_idx=%ud, allow_len=%ul)"
+info ERLCDL_LOG_CRSB_MBMS_INFO ERLCDL_DEBUG_M "[ERLCDL][RSB] fill mbms info (mcch_mp_id=%ul:8,mcch_idx=%ul:8,ci=%ul:16)"
+info ERLCDL_LOG_CRSB_LWA_CHG_RB_IDX ERLCDL_DEBUG_M "[ERLCDL][RSB] change rb_idx(flags=%xl:8,rb_idx=%ul:8,n_sdu=%ul:16)"
+warn ERLCDL_LOG_CLDMA_NOT_READY ERLCDL_WARN_M "[ERLCDL][RSB][WARN] CLDMA not ready!"
+warn ERLCDL_LOG_PRSB_LARGER_SDU ERLCDL_WARN_M "[ERLCDL][RSB][WARN][DISC] SDU len overflow (len=%ud>%ud)"
+
+// VA shortage check & handling
+info ERLCDL_LOG_VA_CHK_CNTX_IN ERLCDL_WARN_UH "[ERLCDL][VA] check shortage VA in context (vrb_id=%ub,next_add_fail_addr=%xl)"
+warn ERLCDL_LOG_VA_CHK_CNTX_HIT_LIST_1 ERLCDL_WARN_UH "[ERLCDL][VA][WARN] hit shortage VA in context - reassemble list (rb_idx=%ub,p_pdu=%xl,p_vrb=%xl,len=%ud)"
+warn ERLCDL_LOG_VA_CHK_CNTX_HIT_LIST_2 ERLCDL_WARN_UH "[ERLCDL][VA][WARN] hit shortage VA in context - reassemble list (rb_idx=%ub:3,ci=%ub:1,mrb=%ub:1,%pb:3p_pdu=%xl,p_vrb=%xl,len=%ud)"
+warn ERLCDL_LOG_VA_CHK_CNTX_HIT_RO ERLCDL_WARN_UH "[ERLCDL][VA][WARN] hit shortage VA in context - reordering window (rb_idx=%ub,sn=%ud,p_pdu=%xl,p_vrb=%xl,len=%ud)"
+info ERLCDL_LOG_VA_CHK_RSMT_IN ERLCDL_WARN_UH "[ERLCDL][VA] check shortage VA in RSMT (vrb_id=%ub,next_add_fail_addr=%xl)"
+warn ERLCDL_LOG_VA_CHK_RSMT_HIT ERLCDL_WARN_UH "[ERLCDL][VA][WARN] hit shortage VA in RSMT (flow_idx=%ub,cur_idx=%ub,p_pdu=%xl,p_vrb=%xl,len=%ud)"
+warn ERLCDL_LOG_VA_CHK_INVAL_VRB_ID ERLCDL_WARN_UH "[ERLCDL][VA][WARN] check shortage VA - invalid VRB ID (vrb_id=%ub,next_add_fail_addr=%xl)"
+info ERLCDL_LOG_VA_CHK_REL_RB_DATA ERLCDL_WARN_UH "[ERLCDL][VA] Start to clear data (flow_idx=%ub,rb_idx=%ub,sn_r=%ud,sn_h=%ud)"
+info ERLCDL_LOG_VA_CHK_REL_PDU_DATA ERLCDL_WARN_UH "[ERLCDL][VA] free PDU (sn=%ud,so=%ud)"
+
+// VRB shortage check & handling
+warn ERLCDL_LOG_VRB_SHORTAGE ERLCDL_WARN_UH "[ERLCDL][VRB][WARN] VRB shortage status (mode=%ub,remain_size=%ul)"
+info ERLCDL_LOG_VRB_SHORTAGE_TMR_START ERLCDL_WARN_UH "[ERLCDL][VRB][TMR] VRB shortage protect timer start (mode=%ub)"
+info ERLCDL_LOG_VRB_SHORTAGE_TMR_EXPIRE ERLCDL_WARN_UH "[ERLCDL][VRB][TMR] VRB shortage protect timer expire (mode=%ub)"
+
+/********************************** MTK PROPRIETARY FEATURE TRACE **********************************/
+// Virtual connected
+info ERLCDL_LOG_ENTER_V_CONN ERLCDL_DEBUG_L "[ERLCDL][RB][VCONN] enter virtual-connected state"
+info ERLCDL_LOG_LEAVE_V_CONN ERLCDL_DEBUG_L "[ERLCDL][RB][VCONN] leave virtual-connected state"
+
+// MBMS EFUSE
+warn ERLCDL_LOG_MBMS_ADD_MCCH_EFUSE ERLCDL_DEBUG_L "[ERLCDL][RB][MBMS][WARN] not allow establish MCCH (mcch_idx=%ub:3,ci=%ub:1)"
+warn ERLCDL_LOG_MBMS_ADD_MRB_EFUSE ERLCDL_DEBUG_L "[ERLCDL][RB][MBMS][WARN] not allow establish MRB (mrb_idx=%ub:3,ci=%ub:1)"
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_public.tmd b/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_public.tmd
new file mode 100644
index 0000000..90c18b1
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/erlcdl_trace_public.tmd
@@ -0,0 +1,168 @@
+[Default]
+ERLCDL_PUBLIC
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 16
+L2_BUFFER_SETTING L2_BUFFER_EL2
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+ERLCDL_SRB_UH ON
+ERLCDL_SRB_H ON
+ERLCDL_SRB_M ON
+ERLCDL_SRB_L ON
+ERLCDL_SRB_UL ON
+ERLCDL_DRB_UH ON
+ERLCDL_DRB_H ON
+ERLCDL_DRB_M ON
+ERLCDL_DRB_L ON
+ERLCDL_DRB_UL ON
+ERLCDL_RB_M ON
+ERLCDL_RB_L ON
+ERLCDL_WARN_UH ON
+ERLCDL_WARN_H ON
+ERLCDL_ERROR_UH ON
+ERLCDL_ERROR_H ON
+ERLCDL_CONFIG_H ON
+ERLCDL_CONFIG_M ON
+ERLCDL_TIMER_L ON
+ERLCDL_TIMER_UL ON
+ERLCDL_DEBUG_H ON
+ERLCDL_DEBUG_M ON
+ERLCDL_MBMS_M ON
+
+[String]
+
+ERLCDL_RB_CFG_TYPE
+{
+ "release", //0
+ "establish", //1
+ "re-establish", //2
+ "re-config", //3
+ "re-establish(without config)" //4
+}
+
+ERLCDL_RB_MODE_Type
+{
+ "AM10 with LI11", //5
+ "AM10 with LI15", //6
+ "UM5", //7
+ "UM10" //8
+}
+
+[Message]
+/********************************** CONFIGURATION TRACE **********************************/
+// RB configuration
+info ERLCDL_LOG_RB_CFG ERLCDL_CONFIG_M "[ERLCDL][RB] %s RB (rb_idx=%ub,rbid=%ub)"
+info ERLCDL_LOG_DEL_OLD_DRB ERLCDL_CONFIG_H "[ERLCDL][RB] release old DRB (rb_idx=%ud,new_rbid=%ud,old_rbid=%ud)"
+info ERLCDL_LOG_DEL_NEW_DRB ERLCDL_CONFIG_H "[ERLCDL][RB] release new DRB (rb_idx=%ud,new_rbid=%ud,old_rbid=%ud)"
+info ERLCDL_LOG_ADD_2ND_DRB ERLCDL_CONFIG_H "[ERLCDL][RB] establish DRB (rb_idx=%ub,old_rbid=%ub,new_rbid=%ub)"
+info ERLCDL_LOG_SETUP_AM_TIMER ERLCDL_CONFIG_M "[ERLCDL][RB][CFG] %s RB info (rb_idx=%ub,t-Reordering=%ud,t-StatusProhibit=%ud)"
+info ERLCDL_LOG_SETUP_UM_TIMER ERLCDL_CONFIG_M "[ERLCDL][RB][CFG] %s RB info (rb_idx=%ub,t-Reordering=%ud)"
+warn ERLCDL_LOG_RB_PARAM_ERR ERLCDL_CONFIG_M "[ERLCDL][RB][WARN] RB parameter error"
+warn ERLCDL_LOG_RB_STUS_ERR ERLCDL_CONFIG_M "[ERLCDL][RB][WARN] RB status error"
+
+// MBMS RB configuration
+info ERLCDL_LOG_MBMS_ADD_MCCH ERLCDL_CONFIG_H "[ERLCDL][RB][MBMS] establish MCCH (mcch_idx=%ub:3,ci=%ub:1)"
+info ERLCDL_LOG_MBMS_DEL_MCCH ERLCDL_CONFIG_H "[ERLCDL][RB][MBMS] release MCCH (mcch_idx=%ub:3,ci=%ub:1)"
+info ERLCDL_LOG_MBMS_ADD_MRB ERLCDL_CONFIG_H "[ERLCDL][RB][MBMS] establish MRB (mrb_idx=%ub:3,ci=%ub:1)"
+info ERLCDL_LOG_MBMS_DEL_MRB ERLCDL_CONFIG_H "[ERLCDL][RB][MBMS] release MRB (mrb_idx=%ub:3,ci=%ub:1)"
+info ERLCDL_LOG_MBMS_PC_REQ ERLCDL_CONFIG_M "[ERLCDL][LBC] receive total %ud MRB SDUs (mrb_idx=%ub:3,ci=%ub:1%pb:4)"
+info ERLCDL_LOG_MBMS_LB_ACT ERLCDL_CONFIG_M "[ERLCDL][LBC] activate loop mode C (mrb_idx=%ub:3,ci=%ub:1)"
+info ERLCDL_LOG_MBMS_LB_DEACT ERLCDL_CONFIG_M "[ERLCDL][LBC] deactivate loop mode C (mrb_idx=%ub:3,ci=%ub:1)"
+
+/********************************** RX DATA ROUTINE TRACE **********************************/
+// RX data explicit trace: PDU, PDU segment info
+info ERLCDL_LOG_SRB_RX_AM_PDU ERLCDL_SRB_M "[ERLCDL][PDU] rx AM PDU (rb_idx=%ud:6,sn=%ud:10,len=%ud,%pb:2e=%ub:1,fi=%ub:2,p=%ub:1)"
+info ERLCDL_LOG_SRB_RX_AM_SEG ERLCDL_SRB_M "[ERLCDL][PDU] rx AM SEG (rb_idx=%ud:6,sn=%ud:10,len=%ud,so=%ud,%pb:1lsf=%ub:1,e=%ub:1,fi=%ub:2,p=%ub:1)"
+info ERLCDL_LOG_DRB_RX_AM_PDU ERLCDL_DRB_M "[ERLCDL][PDU] rx AM PDU (rb_idx=%ud:6,sn=%ud:10,len=%ud,%pb:2e=%ub:1,fi=%ub:2,p=%ub:1)"
+info ERLCDL_LOG_DRB_RX_AM_SEG ERLCDL_DRB_M "[ERLCDL][PDU] rx AM SEG (rb_idx=%ud:6,sn=%ud:10,len=%ud,so=%ud,%pb:1lsf=%ub:1,e=%ub:1,fi=%ub:2,p=%ub:1)"
+info ERLCDL_LOG_DRB_RX_UM10_PDU ERLCDL_DRB_M "[ERLCDL][PDU] rx UM10 PDU (rb_idx=%ud:6,sn=%ud:10,len=%ud,%pb:2e=%ub:1,fi=%ub:2)"
+info ERLCDL_LOG_DRB_RX_UM5_PDU ERLCDL_DRB_M "[ERLCDL][PDU] rx UM5 PDU (rb_idx=%ud:6,sn=%ud:10,len=%ud,%pb:2e=%ub:1,fi=%ub:2,%pb:3pdu_ts=%l)"
+info ERLCDL_LOG_DRB_RX_MBMS_PDU ERLCDL_MBMS_M "[ERLCDL][PDU] rx MBMS PDU (rb_idx=%ud:3,ci=%ud:1,mrb=%ud:2,sn=%ud:10,len=%ud,%pb:2e=%ub:1,fi=%ub:2)"
+
+// RX data explicit trace: SDU info
+// LI = 11 bits
+info ERLCDL_LOG_SRB_SLI_LI11_1 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ud:11x%ud:5)"
+info ERLCDL_LOG_SRB_SLI_LI11_2 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ul:11x%ul:5,%ul:11x%ul:5)"
+info ERLCDL_LOG_SRB_SLI_LI11_3 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ul:11x%ul:5,%ul:11x%ul:5,%ud:11x%ud:5)"
+info ERLCDL_LOG_SRB_SLI_LI11_4 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5)"
+info ERLCDL_LOG_DRB_SLI_LI11_1 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ud:11x%ud:5)"
+info ERLCDL_LOG_DRB_SLI_LI11_2 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ul:11x%ul:5,%ul:11x%ul:5)"
+info ERLCDL_LOG_DRB_SLI_LI11_3 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ul:11x%ul:5,%ul:11x%ul:5,%ud:11x%ud:5)"
+info ERLCDL_LOG_DRB_SLI_LI11_4 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len x num) (%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5)"
+// LI = 15 bits
+info ERLCDL_LOG_SRB_SLI_LI15_1 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ud)x(%ub)"
+info ERLCDL_LOG_SRB_SLI_LI15_2 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ul:16,%ul:16)x(%ud:8,%ud:8)"
+info ERLCDL_LOG_SRB_SLI_LI15_3 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ul:16,%ul:16,%ud)x(%uf:8,%uf:8,%uf:8)"
+info ERLCDL_LOG_SRB_SLI_LI15_4 ERLCDL_SRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ul:16,%ul:16,%ul:16,%ul:16)x(%ul:8,%ul:8,%ul:8,%ul:8)"
+info ERLCDL_LOG_DRB_SLI_LI15_1 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ud)x(%ub)"
+info ERLCDL_LOG_DRB_SLI_LI15_2 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ul:16,%ul:16)x(%ud:8,%ud:8)"
+info ERLCDL_LOG_DRB_SLI_LI15_3 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ul:16,%ul:16,%ud)x(%uf:8,%uf:8,%uf:8)"
+info ERLCDL_LOG_DRB_SLI_LI15_4 ERLCDL_DRB_L "[ERLCDL][PDU] SDU info: (len)x(num) (%ul:16,%ul:16,%ul:16,%ul:16)x(%ul:8,%ul:8,%ul:8,%ul:8)"
+
+// RX data explicit trace: PDU segment truncate info
+info ERLCDL_LOG_DISC_OLD_DUP_SEG ERLCDL_DEBUG_M "[ERLCDL][PDU] discard old duplicate SEG (so=%ud,len=%ud,%pb:1lsf=%ub:1)"
+info ERLCDL_LOG_TRUNC_OLD_DUP_SEG ERLCDL_DEBUG_M "[ERLCDL][PDU] truncate old duplicate SEG (so=%ud,len=%ud)"
+info ERLCDL_LOG_TRUNC_NEW_DUP_SEG ERLCDL_DEBUG_M "[ERLCDL][PDU] truncate new duplicate SEG (so=%ud,len=%ud)"
+info ERLCDL_LOG_TRUNC_RESULT ERLCDL_DEBUG_M "[ERLCDL][PDU] truncate result (so=%ud,len=%ud,n_skip=%ub,first SDU portion len=%ud)"
+
+// RX data explicit trace: State variable update
+info ERLCDL_LOG_SRB_AM_STATE_VAR_1 ERLCDL_SRB_M "[ERLCDL][VAR] AM state variables (rb_idx=%ud:6,vr_r=%ud:10,vr_ms=%uf:10,vr_h=%uf:10)"
+info ERLCDL_LOG_SRB_AM_STATE_VAR_2 ERLCDL_SRB_M "[ERLCDL][VAR] AM state variables (rb_idx=%ud:6,vr_r=vr_ms=vr_h=%ud:10)"
+info ERLCDL_LOG_DRB_AM_STATE_VAR_1 ERLCDL_DRB_M "[ERLCDL][VAR] AM state variables (rb_idx=%ud:6,vr_r=%ud:10,vr_ms=%uf:10,vr_h=%uf:10)"
+info ERLCDL_LOG_DRB_AM_STATE_VAR_2 ERLCDL_DRB_M "[ERLCDL][VAR] AM state variables (rb_idx=%ud:6,vr_r=vr_ms=vr_h=%ud:10)"
+info ERLCDL_LOG_DRB_UM_STATE_VAR_1 ERLCDL_DRB_M "[ERLCDL][VAR] UM state variables (rb_idx=%ud:6,vr_ur=%ud:10,vr_uh=%ud)"
+info ERLCDL_LOG_DRB_UM_STATE_VAR_2 ERLCDL_DRB_M "[ERLCDL][VAR] UM state variables (rb_idx=%ud:6,vr_ur=vr_uh=%ud:10)"
+
+// RX data aggregation trace
+info ERLCDL_LOG_AGG_SRB_AM_1 ERLCDL_SRB_UH "[ERLCDL][AGG] AM RX data summary (rb_idx=%ud:6,vr_r=%ud:10,vr_ms=%uf:10,vr_h=%uf:10,cmplt_pdu_num=%ub,pdu_seg_num=%ub)"
+info ERLCDL_LOG_AGG_SRB_AM_2 ERLCDL_SRB_UH "[ERLCDL][AGG] AM RX data summary (rb_idx=%ud:6,vr_r=vr_ms=vr_h=%ud:10,cmplt_pdu_num=%ub,pdu_seg_num=%ub)"
+info ERLCDL_LOG_AGG_DRB_AM_1 ERLCDL_DRB_UH "[ERLCDL][AGG] AM RX data summary (rb_idx=%ud:6,vr_r=%ud:10,vr_ms=%uf:10,vr_h=%uf:10,cmplt_pdu_num=%ub,pdu_seg_num=%ub)"
+info ERLCDL_LOG_AGG_DRB_AM_2 ERLCDL_DRB_UH "[ERLCDL][AGG] AM RX data summary (rb_idx=%ud:6,vr_r=vr_ms=vr_h=%ud:10,cmplt_pdu_num=%ub,pdu_seg_num=%ub)"
+info ERLCDL_LOG_AGG_DRB_UM_1 ERLCDL_DRB_UH "[ERLCDL][AGG] UM RX data summary (rb_idx=%ud:6,vr_ur=%ud:10,vr_uh=%ud,pdu_num=%ub)"
+info ERLCDL_LOG_AGG_DRB_UM_2 ERLCDL_DRB_UH "[ERLCDL][AGG] UM RX data summary (rb_idx=%ud:6,vr_ur=vr_uh=%ud:10,pdu_num=%ub)"
+
+// RX data error trace
+warn ERLCDL_LOG_DISC_OOW ERLCDL_WARN_UH "[ERLCDL][PDU] discard PDU due to out-of-window (rb_idx=%ub,SN >= VR(MR),sn=%ud,vr_mr=%ud)"
+warn ERLCDL_LOG_DISC_OOD ERLCDL_WARN_UH "[ERLCDL][PDU] discard PDU due to out-of-date (rb_idx=%ub,SN < VR(UR),sn=%ud,vr_ur=%ud)"
+warn ERLCDL_LOG_DISC_DUP ERLCDL_WARN_UH "[ERLCDL][PDU] discard PDU due to duplicate (rb_idx=%ub,already received,sn=%ud)"
+warn ERLCDL_LOG_UM_PDU_LOSS ERLCDL_WARN_UH "[ERLCDL][PDU] UM PDU loss (rb_idx=%ud:6,loss_num=%ud:10)"
+warn ERLCDL_LOG_PDU_INVALID_RB ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: invalid RB (rb_idx=%ub,len=%ud)"
+warn ERLCDL_LOG_PDU_INVALID_MBMS_RB ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: invalid MBMS RB (rb_idx=%ub,len=%ud)"
+warn ERLCDL_LOG_PDU_ZERO_LEN ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: zero length (rb_idx=%ub)"
+warn ERLCDL_LOG_PDU_BUF_SHORTAGE ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: PDU buffer shortage (rb_idx=%ub,len=%ud)"
+warn ERLCDL_LOG_PDU_LEN_ERROR ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: length error (rb_idx=%ub,len=%ud<=%ud)"
+warn ERLCDL_LOG_PDU_PARSE_ERROR ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: header parsing error (rb_idx=%ub,len=%ud,sn=%ud)"
+warn ERLCDL_LOG_PDU_SO_ERROR ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: invalid SO error (rb_idx=%ub,len=%ud,sn=%ud,so=%ud)"
+warn ERLCDL_LOG_PDU_SEG_ERROR ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: invalid PDU SEG (rb_idx=%ub,old_lsf%ub,old_soe=%ud,new_lsf%ub,new_soe=%ud)"
+warn ERLCDL_LOG_EXT_PDU_HDR_ERROR_1 ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: zero LI (rb_idx=%ub)"
+warn ERLCDL_LOG_EXT_PDU_HDR_ERROR_2 ERLCDL_WARN_UH "[ERLCDL][PDU] drop PDU: invalid length of last SDU portion (rb_idx=%ub)"
+
+/********************************** TIMER TRACE **********************************/
+// Timer handling
+info ERLCDL_LOG_AM_RO_TMR_START ERLCDL_TIMER_L "[ERLCDL][TMR][VAR] t-Reordering timer start (rb_idx=%ud:6,vr_x=%ud:10)"
+info ERLCDL_LOG_AM_RO_TMR_EXPIRE ERLCDL_TIMER_L "[ERLCDL][TMR][VAR] t-Reordering timer expire (rb_idx=%ud:6,vr_ms=%ud:10)"
+info ERLCDL_LOG_UM_RO_TMR_START ERLCDL_TIMER_L "[ERLCDL][TMR][VAR] t-Reordering timer start (rb_idx=%ud:6,vr_ux=%ud:10)"
+info ERLCDL_LOG_UM_RO_TMR_EXPIRE ERLCDL_TIMER_L "[ERLCDL][TMR][VAR] t-Reordering timer expire (rb_idx=%ud:6,vr_ur=%ud:10)"
+info ERLCDL_LOG_XM_RO_TMR_STOP ERLCDL_TIMER_L "[ERLCDL][TMR] t-Reordering timer stop (rb_idx=%ub)"
+info ERLCDL_LOG_STATUS_PROH_TMR_EXPIRE ERLCDL_TIMER_L "[ERLCDL][TMR] t-StatusProhibit timer expire (rb_idx=%ub)"
+info ERLCDL_LOG_STATUS_PROH_TMR_STOP ERLCDL_TIMER_L "[ERLCDL][TMR] t-StatusProhibit timer stop (rb_idx=%ub)"
+
+/********************************** STATUS PDU TRACE **********************************/
+// STATUS PDU
+info ERLCDL_LOG_GEN_STATUS_PDU ERLCDL_RB_M "[ERLCDL][RPT] generate STATUS PDU (rb_idx=%ud:6,ack_sn=%ud:10,len=%ub)"
+info ERLCDL_LOG_REGEN_STATUS_PDU ERLCDL_RB_M "[ERLCDL][RPT] re-generate STATUS PDU (rb_idx=%ud:6,ack_sn=%ud:10,len=%ub)"
+info ERLCDL_LOG_RESEG_STATUS_PDU ERLCDL_RB_M "[ERLCDL][RPT] re-segment STATUS PDU (rb_idx=%ud:6,ack_sn=%ud:10,len=%ub)"
+info ERLCDL_LOG_RPT_NACK_PDU ERLCDL_RB_L "[ERLCDL][RPT] report NACK PDU (rb_idx=%ud:6,sn=%ud:10)"
+info ERLCDL_LOG_RPT_NACK_SEG ERLCDL_RB_L "[ERLCDL][RPT] report NACK SEG (rb_idx=%ud:6,sn=%ud:10,so_s=%ud,so_e=%ud:15)"
+
+/********************************** OTHER SCENARIO **********************************/
+// PDU flush for reestablish
+info ERLCDL_LOG_AM_FLUSH ERLCDL_RB_L "[ERLCDL][PDU] flush AM PDU (rb_idx=%ud:6,vr_r=%ud:10,vr_h=%ud)"
+info ERLCDL_LOG_UM_FLUSH ERLCDL_RB_L "[ERLCDL][PDU] flush UM PDU (rb_idx=%ud:6,vr_ur=%ud:10,vr_uh=%ud)"
+
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_internal.tmd b/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_internal.tmd
new file mode 100644
index 0000000..a48cd16
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_internal.tmd
@@ -0,0 +1,70 @@
+[Default]
+ERLCUL_INTERNAL
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 5
+L2_BUFFER_SETTING L2_BUFFER_ERT
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+ERLCUL_SRB_H ON
+ERLCUL_RB_H ON
+ERLCUL_RB_M ON
+ERLCUL_RB_L ON
+ERLCUL_RB_UL ON
+ERLCUL_WARN_UH ON
+ERLCUL_WARN_H ON
+ERLCUL_ERROR_UH ON
+ERLCUL_ERROR_H ON
+ERLCUL_CONFIG_UH ON
+ERLCUL_CONFIG_H ON
+ERLCUL_CONFIG_M ON
+ERLCUL_TIMER_UH ON
+ERLCUL_TIMER_L ON
+ERLCUL_DEBUG_UH ON
+ERLCUL_DEBUG_H ON
+ERLCUL_DEBUG_L ON
+
+[String]
+
+[Message]
+
+/********************************** STATUS PDU TRACE **********************************/
+// STATUS PDU
+info ERLCUL_LOG_ADD_POLL_NACK ERLCUL_RB_L "[ERLCUL][TMR] add a retx AMD PDU for poll retry (rb_idx=%ul:6,sn=%ul:10,len=%ul:16)"
+info ERLCUL_LOG_DEL_POLL_NACK ERLCUL_RB_L "[ERLCUL][RPT] remove pollnack due to all ack or new SDU (rb_idx=%ub)"
+info ERLCUL_LOG_NACK_TUPLE ERLCUL_DEBUG_L "[ERLCUL][RPT] nack tuple info (idx=%ul:16,sso=%ul:16,len=%ul:16,num=%ul:16)"
+info ERLCUL_LOG_FREE_NACK ERLCUL_DEBUG_L "[ERLCUL][RPT] deregister invalid old nack (sn=%ud)"
+warn ERLCUL_LOG_FAIL_TO_ALLOC_NACK ERLCUL_WARN_H "[ERLCUL][RPT][WARN] fail to allocate NACK (rb_idx=%ul:6,ack_sn=%ul:10,nack_sn=%ul:16,so_s=%ul:16,so_e=%ul:16)"
+info ERLCUL_LOG_POLLNACK_EXIST ERLCUL_DEBUG_L "[ERLCUL][RPT] pollnack exists in old nacklist (sn=%ud)"
+info ERLCUL_LOG_SRB_DATA_CNF ERLCUL_SRB_H "[ERLCUL][RPT] SRB data confirm (rb_idx=%ud:5,sit_idx=%ud:11)"
+info ERLCUL_LOG_SRB_CNF ERLCUL_DEBUG_L "[ERLCUL][RPT] n_ack update for SRB (n_ack=%ub:4,new n_ack=%ub:4)"
+info ERLCUL_LOG_NO_SRB_CNF ERLCUL_DEBUG_L "[ERLCUL][RPT] not any new SRB data confirmed (n_ack=%ud,new n_ack=%ud)"
+
+/********************************** PDCP REESTABLISHMENT TRACE **********************************/
+info ERLCUL_LOG_UPDATE_PDCP_RETX ERLCUL_RB_UL "[ERLCUL][RB][PDCP] update PDCP retx list head (idx=%ul:16,num=%ul:16,len=%uf)"
+info ERLCUL_LOG_CONSTRUCT_RETX_ENTRY ERLCUL_RB_UL "[ERLCUL][RB][PDCP] link PDCP retx entry (idx=%ul:16,len=%ul:16,pdcp_cnt=%ul)"
+
+/********************************** PDCP DISCARD TRACE **********************************/
+info ERLCUL_LOG_CANCEL_POLL_TRGR ERLCUL_RB_L "[ERLCUL][DISC][PDCP] cancel poll trigger due to no SDU"
+info ERLCUL_LOG_PDU_CUR_IDX ERLCUL_RB_UL "[ERLCUL][DISC][PDCP] update a_curr_idx for PDU (sn=%ud)(sdu_idx:%ul)"
+info ERLCUL_LOG_BLOCK_DISCARD ERLCUL_RB_UL "[ERLCUL][DISC][PDCP] block pdcp discard due to RB suspended (rb_idx=%ub)"
+
+/********************************** PDU/SDU FREE TRACE **********************************/
+info ERLCUL_LOG_RELSN_UPDATE ERLCUL_DEBUG_H "[ERLCUL][POLL] PDU release (rb_idx=%ud:6,rel_sn=%ud:10)"
+info ERLCUL_LOG_FREE_END_IDX_UPDATE ERLCUL_DEBUG_H "[ERLCUL][POLL] update free end index to 1st unrelease SIT entry (rb_idx=%ub, sit idx=%ul)"
+
+/********************************** MTK PROPRIETARY FEATURE TRACE **********************************/
+// Aggregation trace timer inject
+info ERLCUL_LOG_AGG_TMR_SET ERLCUL_DEBUG_UH "[ERLCUL] Aggregation trace timer period update (timer = %ud ms)"
+
+// SDU return timer
+info ERLCUL_LOG_SDU_RETURN_START ERLCUL_TIMER_L "[ERLCUL] Start SDU return timer (rb_idx=%ub)"
+info ERLCUL_LOG_SDU_RETURN_STOP ERLCUL_TIMER_L "[ERLCUL] Stop SDU return timer (rb_idx=%ub)"
+info ERLCUL_LOG_SDU_RETURN ERLCUL_TIMER_UH "[ERLCUL] (rb_idx=%ub)SDU return [%ul:16, %ul:16)"
+
+// Force RLC timer value
+info ERLCUL_LOG_FORCE_TIMER_CFG ERLCUL_DEBUG_UH "[ERLCUL][CFG][TMR] set t-PollRetransmit config (rb_idx=%ub,length=%ud)"
diff --git a/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_protect.tmd b/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_protect.tmd
new file mode 100644
index 0000000..73174d2
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_protect.tmd
@@ -0,0 +1,51 @@
+[Default]
+ERLCUL_PROTECT
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 5
+L2_BUFFER_SETTING L2_BUFFER_ERT
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+ERLCUL_RB_UH ON
+ERLCUL_RB_L ON
+
+ERLCUL_ERROR_UH ON
+
+ERLCUL_DEBUG_L ON
+
+ERLCUL_TIMER_M ON
+ERLCUL_TIMER_L ON
+
+[String]
+
+[Message]
+
+/********************************** L2 COPRO RELATED TRACE **********************************/
+// COTF descriptor trace
+// to be added
+
+// VA shortage check & handling
+info ERLCUL_LOG_UL_RB_LOCK ERLCUL_RB_UH "[ERLCUL][RB] lock RB (rb_idx=%ub)"
+info ERLCUL_LOG_UL_RB_UNLOCK ERLCUL_RB_UH "[ERLCUL][RB] unlock RB (rb_idx=%ub)"
+
+/********************************** MTK PROPRIETARY FEATURE TRACE **********************************/
+// Smart scheduling
+info ERLCUL_LOG_SMART_SCHEDULE ERLCUL_RB_L "[ERLCUL][LCP] smart schedule (do_seg=%ub)"
+
+// Virtual connected
+info ERLCUL_LOG_UL_RB_VCON_ENTER_PREPARE ERLCUL_DEBUG_L "[ERLCUL][VC] prepare enter virtual-connected state"
+info ERLCUL_LOG_UL_RB_VCON_ENTER ERLCUL_DEBUG_L "[ERLCUL][VC] enter virtual-connected state"
+info ERLCUL_LOG_UL_RB_VCON_LEAVE ERLCUL_DEBUG_L "[ERLCUL][VC] leave virtual-connected state"
+info ERLCUL_LOG_STATUS_FDBK_START ERLCUL_TIMER_L "[ERLCUL][VC][TMR] t-StatusFeedback timer start"
+info ERLCUL_LOG_STATUS_FDBK_STOP ERLCUL_TIMER_L "[ERLCUL][VC][TMR] t-StatusFeedback timer stop"
+info ERLCUL_LOG_STATUS_FDBK_EXPIRE ERLCUL_TIMER_L "[ERLCUL][VC][TMR] t-StatusFeedback timer expire"
+info ERLCUL_LOG_CRITICAL_SIT ERLCUL_RB_L "[ERLCUL][VC][CRI] critical sit (index=%ul)"
+info ERLCUL_LOG_CRITICAL_SIT_RANGE ERLCUL_RB_L "[ERLCUL][VC][CRI] check critical sdu range (rb_idx=%ul:5)(sched index=%ul:12, tail index=%ul:15))"
+
+// Gemini
+warn ERLCUL_LOG_UL_ADD_LL_RB ERLCUL_ERROR_UH "[ERLCUL][RB][WARN] L+L RB establish detected (protocol_idx=%ub,feature=%ub)"
+
diff --git a/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_public.tmd b/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_public.tmd
new file mode 100644
index 0000000..77e60c3
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/trace/erlcul_trace_public.tmd
@@ -0,0 +1,166 @@
+[Default]
+ERLCUL_PUBLIC
+On
+L2_Buffer
+TCMFORCE
+MAX_ARG 5
+L2_BUFFER_SETTING L2_BUFFER_ERT
+
+[Modem_Type]
+LTE_L2
+
+[Class]
+ERLCUL_SRB_UH ON
+ERLCUL_SRB_M ON
+ERLCUL_SRB_L ON
+ERLCUL_SRB_UL ON
+ERLCUL_DRB_UH ON
+ERLCUL_DRB_M ON
+ERLCUL_DRB_L ON
+ERLCUL_DRB_UL ON
+ERLCUL_RB_UH ON
+ERLCUL_RB_H ON
+ERLCUL_RB_M ON
+ERLCUL_RB_L ON
+ERLCUL_RB_UL ON
+ERLCUL_WARN_UH ON
+ERLCUL_WARN_H ON
+ERLCUL_ERROR_UH ON
+ERLCUL_ERROR_H ON
+ERLCUL_CONFIG_UH ON
+ERLCUL_CONFIG_H ON
+ERLCUL_CONFIG_M ON
+ERLCUL_TIMER_M ON
+ERLCUL_TIMER_L ON
+ERLCUL_TIMER_UL ON
+
+[String]
+ERLCUL_RB_CFG_STRING
+{
+ "release RB",
+ "establish RB",
+ "re-establish RB with config",
+ "re-config RB",
+ "re-establish RB without config",
+ "establish and suspend RB",
+ "suspend RB",
+ "resume RB"
+}
+
+ERLCUL_LI_FMT_STRING
+{
+ "11",
+ "15"
+}
+
+ERLCUL_SN_LEN_STRING
+{
+ "05",
+ "10"
+}
+
+[Message]
+
+/********************************** CONFIGURATION TRACE **********************************/
+info ERLCUL_LOG_UL_RB_CFG ERLCUL_CONFIG_M "[ERLCUL][RB] %s (rb_idx=%ud:8,rbid=%ud:8)"
+info ERLCUL_LOG_UL_ADD_NEW_DRB ERLCUL_CONFIG_H "[ERLCUL][RB] establish and suspend new DRB (rb_idx=%uf:8,old_rbid=%uf:8,new_rbid=%uf:8)"
+info ERLCUL_LOG_UL_DEL_OLD_DRB ERLCUL_CONFIG_H "[ERLCUL][RB] release old DRB (rb_idx=%uf:8,old_rbid=%uf:8,new_rbid=%uf:8)"
+info ERLCUL_LOG_UL_DEL_NEW_DRB ERLCUL_CONFIG_H "[ERLCUL][RB] release new DRB (rb_idx=%uf:8,old_rbid=%uf:8,new_rbid=%uf:8)"
+info ERLCUL_LOG_UL_CFG_AM ERLCUL_CONFIG_M "[ERLCUL][RB][CFG] AM10 with LI%s RB info (t-PollRetransmit=%ul:16,pollPDU=%ul:16,pollByte=%ul:24,maxRetxThreshold=%ul:8)"
+info ERLCUL_LOG_UL_CFG_UM ERLCUL_CONFIG_M "[ERLCUL][RB][CFG] UM%s with LI11 RB info"
+info ERLCUL_LOG_UL_CFG_LCG ERLCUL_CONFIG_M "[ERLCUL][RB][CFG] LCH info (priority=%ub,prioritisedBitRate=%ul:16,bucketSizeDuration=%ul:10,logicalChannelGroup=%ul:3)"
+warn ERLCUL_LOG_UL_RB_PARAM_ERR ERLCUL_CONFIG_M "[ERLCUL][RB][WARN] RB parameter error"
+warn ERLCUL_LOG_UL_RB_STUS_ERR ERLCUL_CONFIG_M "[ERLCUL][RB][WARN] RB status error"
+
+/********************************** TX DATA ROUTINE TRACE **********************************/
+// TX data explicit trace: Overall sched status trace
+info ERLCUL_LOG_RB_UL_SNAPSHOT ERLCUL_RB_M "[ERLCUL][LCP] RB UL snapshot (rb_idx=%ul:5,pending_sz=%ul:24)(pdu_bmp:ctrl=%ul:1,retx=%ul:1,data=%ul:1)(sdu_num:left=%ud:1,sdu_len:left=%ud:14,sit full=%ud:1)"
+info ERLCUL_LOG_START_RESOURCE ERLCUL_RB_M "[ERLCUL][LCP] start resource (tb_idx=%ul:2,sub_hdr_sz=%ul:8,bsr_sz=%ul:8,r_tbs=%ul:14)"
+info ERLCUL_LOG_FINAL_RESOURCE ERLCUL_RB_M "[ERLCUL][LCP] final resource (tb_idx=%ul:2,sub_hdr_sz=%ul:8,bsr_sz=%ul:8,r_tbs=%ul:14)"
+
+// TX data explicit trace: Serve RB trace
+info ERLCUL_LOG_DRB_SERVE_RB_UM_05 ERLCUL_DRB_M "[ERLCUL][LCP] serve UM05 LCH (rb_idx=%ub)"
+info ERLCUL_LOG_DRB_SERVE_RB_UM_10 ERLCUL_DRB_M "[ERLCUL][LCP] serve UM10 LCH (rb_idx=%ub)"
+info ERLCUL_LOG_DRB_SERVE_RB_AM_10 ERLCUL_DRB_M "[ERLCUL][LCP] serve AM10 LCH (rb_idx=%ub)"
+info ERLCUL_LOG_SRB_SERVE_RB_AM_10 ERLCUL_SRB_M "[ERLCUL][LCP] serve AM10 LCH (rb_idx=%ub)"
+
+// TX data explicit trace: PDU info
+info ERLCUL_LOG_DRB_BUILD_DATA_PDU ERLCUL_DRB_M "[ERLCUL][LCP] data PDU (rb_idx=%ul:6,tb_idx=%ul:2,sz=%ul:14,sn=%ul:10,e=%ul:1,fi=%ul:2,idx=%ul:16,sso=%ul:13)"
+info ERLCUL_LOG_SRB_BUILD_DATA_PDU ERLCUL_SRB_M "[ERLCUL][LCP] data PDU (rb_idx=%ul:6,tb_idx=%ul:2,sz=%ul:14,sn=%ul:10,e=%ul:1,fi=%ul:2,idx=%ul:16,sso=%ul:13)"
+info ERLCUL_LOG_DRB_BUILD_RETX_PDU ERLCUL_DRB_M "[ERLCUL][LCP] retx PDU (rb_idx=%ul:6,tb_idx=%ul:2,sz=%ul:14,sn=%ul:10,e=%ul:1,fi=%ul:2,idx=%ul:16,sso=%ul:13)"
+info ERLCUL_LOG_SRB_BUILD_RETX_PDU ERLCUL_SRB_M "[ERLCUL][LCP] retx PDU (rb_idx=%ul:6,tb_idx=%ul:2,sz=%ul:14,sn=%ul:10,e=%ul:1,fi=%ul:2,idx=%ul:16,sso=%ul:13)"
+info ERLCUL_LOG_DRB_BUILD_RETX_SEG ERLCUL_DRB_M "[ERLCUL][LCP] retx SEG (rb_idx=%ul:6,tb_idx=%ul:2,sz=%ul:14,sn=%ul:10,e=%ul:1,fi=%ul:2,idx=%ul:16,sso=%ul:13,pso=%ud:15,lsf=%ud:1)"
+info ERLCUL_LOG_SRB_BUILD_RETX_SEG ERLCUL_SRB_M "[ERLCUL][LCP] retx SEG (rb_idx=%ul:6,tb_idx=%ul:2,sz=%ul:14,sn=%ul:10,e=%ul:1,fi=%ul:2,idx=%ul:16,sso=%ul:13,pso=%ud:15,lsf=%ud:1)"
+info ERLCUL_LOG_DRB_BUILD_CTRL_PDU ERLCUL_DRB_M "[ERLCUL][LCP][RPT] ctrl PDU (rb_idx=%ud:6,tb_idx=%ud:2,sz=%ud:8)"
+info ERLCUL_LOG_SRB_BUILD_CTRL_PDU ERLCUL_SRB_M "[ERLCUL][LCP][RPT] ctrl PDU (rb_idx=%ud:6,tb_idx=%ud:2,sz=%ud:8)"
+info ERLCUL_LOG_DRB_HDR_16 ERLCUL_DRB_L "[ERLCUL][LCP] HDR (%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8)"
+info ERLCUL_LOG_SRB_HDR_16 ERLCUL_SRB_L "[ERLCUL][LCP] HDR (%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8,%xl:8)"
+
+// TX data explicit trace: SDU info
+info ERLCUL_LOG_DRB_SDU_SZ ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%udx1)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%udx1)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_12 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_12 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_16 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16,%ul:16,%ul:16)x(%uf:5,%uf:5,%uf:5,%uf:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_16 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16,%ul:16,%ul:16)x(%uf:5,%uf:5,%uf:5,%uf:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_12_1 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ud:11x%ud:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_12_1 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ud:11x%ud:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_12_2 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_12_2 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_12_3 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5,%ud:11x%ud:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_12_3 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5,%ud:11x%ud:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_12_4 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_12_4 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5,%ul:11x%ul:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_16_1 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ud)x(%ub:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_16_1 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ud)x(%ub:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_16_2 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16)x(%ud:5,%ud:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_16_2 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16)x(%ud:5,%ud:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_16_3 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16,%ud)x(%ud:5,%ud:5,%ud:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_16_3 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16,%ud)x(%ud:5,%ud:5,%ud:5)(len x num)"
+info ERLCUL_LOG_DRB_SDU_SZ_16_4 ERLCUL_DRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16,%ul:16,%ul:16)x(%uf:5,%uf:5,%uf:5,%uf:5)(len x num)"
+info ERLCUL_LOG_SRB_SDU_SZ_16_4 ERLCUL_SRB_L "[ERLCUL][LCP] SDU (%ul:16,%ul:16,%ul:16,%ul:16)x(%uf:5,%uf:5,%uf:5,%uf:5)(len x num)"
+
+// TX data aggregation trace
+info ERLCUL_LOG_SCHED_OVERALL_RESULT ERLCUL_RB_UH "[ERLCUL][AGG] sched result summary (grant_num=%ub,grant_byte_sum_before=%ul,grant_byte_sum_after=%ul)"
+info ERLCUL_LOG_SRB_SCHED_RESULT ERLCUL_SRB_UH "[ERLCUL][AGG] sched result AM RB (rb_idx=%ul:6,poll_bit_set=%ul:1,srvd_byte:ctrl=%ul:10,retx=%ul:15,new=%uf)"
+info ERLCUL_LOG_DRB_AM_SCHED_RESULT ERLCUL_DRB_UH "[ERLCUL][AGG] sched result AM RB (rb_idx=%ul:6,poll_bit_set=%ul:1,srvd_byte:ctrl=%ul:10,retx=%ul:15,new=%uf)"
+info ERLCUL_LOG_DRB_UM_SCHED_RESULT ERLCUL_DRB_UH "[ERLCUL][AGG] sched result UM RB (rb_idx=%uf:5,srvd_byte:new=%uf:19)"
+info ERLCUL_LOG_SRB_STATE_VAR ERLCUL_SRB_UH "[ERLCUL][AGG] UL AM state variables (rb_idx=%ul:6,vt_a=%ul:10,vt_s=%ul:10,poll_sn=%ud)"
+info ERLCUL_LOG_DRB_AM_STATE_VAR ERLCUL_DRB_UH "[ERLCUL][AGG] UL AM state variables (rb_idx=%ul:6,vt_a=%ul:10,vt_s=%ul:10,poll_sn=%ud)"
+info ERLCUL_LOG_DRB_UM_STATE_VAR ERLCUL_DRB_UH "[ERLCUL][AGG] UL UM state variables (rb_idx=%ud:6,vt_us=%ud:10)"
+
+/********************************** TIMER TRACE **********************************/
+// Timer handling
+info ERLCUL_LOG_POLL_RETX_START ERLCUL_TIMER_L "[ERLCUL][TMR] t-PollRetransmit timer start (rb_idx=%ub)"
+info ERLCUL_LOG_POLL_RETX_STOP ERLCUL_TIMER_L "[ERLCUL][TMR] t-PollRetransmit timer stop (rb_idx=%ub)"
+info ERLCUL_LOG_POLL_RETX_EXPIRE ERLCUL_TIMER_L "[ERLCUL][TMR] t-PollRetransmit timer expire (rb_idx=%ub)"
+info ERLCUL_LOG_STATUS_PROH_START ERLCUL_TIMER_L "[ERLCUL][TMR] t-StatusProhibit timer start (rb_idx=%ub)"
+info ERLCUL_LOG_STATUS_PROH_STOP ERLCUL_TIMER_L "[ERLCUL][TMR] t-StatusProhibit timer stop (rb_idx=%ub)"
+info ERLCUL_LOG_STATUS_PROH_EXPIRE ERLCUL_TIMER_L "[ERLCUL][TMR] t-StatusProhibit timer expire (rb_idx=%ub)"
+
+/********************************** STATUS PDU TRACE **********************************/
+// STATUS PDU
+info ERLCUL_LOG_RX_STUS_PDU ERLCUL_RB_H "[ERLCUL][RPT] pre-process: rx UL STATUS PDU (rb_idx=%ul:6,pdu_sz=%ul:10,ack_sn=%ul:10)"
+info ERLCUL_LOG_RX_STUS_PDU_DUP ERLCUL_RB_H "[ERLCUL][RPT] pre-process: rx UL STATUS PDU but duplicate (rb_idx=%ul:6,pdu_sz=%ul:10,ack_sn=%ul:10,vt_a=%uf:10,vt_s=%uf:10)"
+info ERLCUL_LOG_STUS_PDU_IND ERLCUL_RB_M "[ERLCUL][RPT][VAR] main process: rx UL STATUS PDU (rb_idx=%ul:6,vt_a=%ul:10,vt_s=%ul:10,poll_sn=%ud)"
+info ERLCUL_LOG_RX_NACK_PDU ERLCUL_RB_L "[ERLCUL][RPT] rx NACK PDU (sn=%ud:10)"
+info ERLCUL_LOG_RX_NACK_SEG ERLCUL_RB_L "[ERLCUL][RPT] rx NACK SEG (sn=%ud:10,rf=%ud:1,lsf=%ud:5,so_s=%ul:16,so_e=%ul:16)"
+info ERLCUL_LOG_PDU_RETX_CNTR ERLCUL_RB_L "[ERLCUL][RPT] PDU retx count++ (rb_idx=%uf:6,sn=%uf:10,retx_cnt=%uf:6)"
+warn ERLCUL_LOG_MAX_RETX_CNTR ERLCUL_ERROR_UH "[ERLCUL][RPT] max retx count reached (rb_idx=%ud:6,sn=%ud:10)"
+
+// STATUS PDU warning trace
+warn ERLCUL_LOG_RX_STUS_PDU_BAD_E ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx UL STATUS PDU but size unmatched (rb_idx=%ul:6,ind_sz=%ul:10,total_sz=%ul:10)"
+warn ERLCUL_LOG_RX_STUS_PDU_BAD_SZ ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx UL STATUS PDU but bad size (rb_idx=%ub,pdu_sz=1)"
+warn ERLCUL_LOG_RX_STUS_PDU_BAD_CPT ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx UL STATUS PDU but bad CPT (rb_idx=%ul:6,pdu_sz=%ul:10,ack_sn=%ul:10,cpt=%ul:3)"
+warn ERLCUL_LOG_RX_STUS_PDU_INACTIVE ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx UL STATUS PDU for an inactive RB (rb_idx=%ul)"
+warn ERLCUL_LOG_NACK_INVALID ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx NACK but invalid SN (sn=%ul:10,vt_a=%ul:10,vt_s=%ul:10)"
+warn ERLCUL_LOG_NACK_OUT_ORDER ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx NACK but out of order (sn=%ud)"
+warn ERLCUL_LOG_NACK_BAD_SO ERLCUL_WARN_H "[ERLCUL][RPT][WARN] rx NACK SEG with invalid SO (sn=%uf:10,data_sz=%uf:14,so_s=%ul:16,so_e=%ul:16)"
+
+/********************************** PDCP REESTABLISHMENT TRACE **********************************/
+info ERLCUL_LOG_PDCP_STATUS_ACK ERLCUL_RB_UL "[ERLCUL][RPT][PDCP] rx PDCP status ack (tid=%ud:2,idx=%ud:14,count=%ul)"
+warn ERLCUL_LOG_PDCP_STATUS_FMS ERLCUL_RB_UL "[ERLCUL][RPT][PDCP] rx PDCP status report (fms=%ul:24,valid=%ul:1)"
+
+/********************************** PDCP DISCARD TRACE **********************************/
+info ERLCUL_LOG_DISCARD_SIT_RANGE ERLCUL_RB_UH "[ERLCUL][DISC][PDCP] SDU discard confirmed (rb_idx=%ul:5)(sched index=%ul:12,discard tail=%ul:15)"
+info ERLCUL_LOG_PDCP_DISCARD_SCHED_IDX_UPDATE ERLCUL_RB_UH "[ERLCUL][DISC][PDCP] sched index after discard(sched index=%ul)"
diff --git a/mcu/protocol/interface/enl2/el2/upcm_emac_struct.h b/mcu/protocol/interface/enl2/el2/upcm_emac_struct.h
new file mode 100644
index 0000000..1592942
--- /dev/null
+++ b/mcu/protocol/interface/enl2/el2/upcm_emac_struct.h
@@ -0,0 +1,97 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * upcm_emac_struct.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * struct between emac and upcm.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 05 09 2019 tc.chang
+ * [MOLY00404770] [Gen97] Sync Gen95 UMOLYE patch.
+ * RBRQ, USIR, fake A2, and some bug fix
+ *
+ ****************************************************************************/
+
+/// @date 2018/3/15
+
+#ifndef __UPCM_EMAC_STRUCT__
+#define __UPCM_EMAC_STRUCT__
+
+#include "kal_public_api.h"
+
+#define UPCM_EMAC_MAX_RB_NUM (10) //this value should be the same as MAX_RB_NUM
+#define UPCM_EMAC_INVALID_RBR (0xFFFFFFFF)
+
+typedef struct{
+ LOCAL_PARA_HDR
+ kal_uint8 rb_idx;
+ kal_bool is_ul;
+ kal_uint32 rbrq;
+}upcm_emac_rbrq_req_struct;
+
+typedef struct{
+ LOCAL_PARA_HDR
+ kal_uint8 inactive_num;
+ kal_uint8 active_num;
+
+ kal_uint8 inactive_rb[UPCM_EMAC_MAX_RB_NUM];
+ kal_uint8 active_rb[UPCM_EMAC_MAX_RB_NUM];
+}upcm_emac_rbrq_support_rel_ind_struct;
+
+typedef struct{
+ LOCAL_PARA_HDR
+ kal_uint8 rb_idx;
+ kal_bool is_ul;
+ kal_uint32 rbr;
+}upcm_emacdl_rbr_ind_struct;
+
+
+#endif
diff --git a/mcu/protocol/interface/enl2/en_common/enl2_sap_common.h b/mcu/protocol/interface/enl2/en_common/enl2_sap_common.h
new file mode 100644
index 0000000..8752751
--- /dev/null
+++ b/mcu/protocol/interface/enl2/en_common/enl2_sap_common.h
@@ -0,0 +1,639 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * enl2_sap_common.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ * Common header file for all ENL2 SAPs.
+ * This file defines the common structures used by all ENL2 SAPs.
+ *
+ * Author:
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 10 22 2020 head.hsu
+ * [MOLY00574624] [Gen97] [Gemini] NPDCP HW arbitration
+ * [Interface][ENL2 Common]
+ *
+ * 12 09 2019 yiting.cheng
+ * [MOLY00464632] [GEN97] 5G4 IRAT HO with nr_rb configuration
+ * .
+ *
+ * 12 03 2019 sakari.niemela
+ * [MOLY00462238] [Gen97][VMOLY] Smart Idle Feature SA part(MPD)
+ * VGMM-NRRC, NRRC-ENPDCP and NRRC Internal SAP updates for 'Smart Idle'
+ *
+ * 10 14 2019 yiting.cheng
+ * [MOLY00442846] [Gen97] Modem feature - NSA part (implementation)
+ * .
+ *
+ * 09 25 2019 yiting.cheng
+ * [MOLY00443312] [MT6885][Petrus][Sanity][VMOLY][VMOLY][2019-09-21_1700] ASSERT = [1][core1,vpe0,tc0(vpe3)] Assert fail: epdcp_rbm.c 6392 - EL2 _
+ * .
+ *
+ * 09 09 2019 jia-shi.lin
+ * [MOLY00430672] [Gen97][NWSIM][5G][SA][GCF TEST] TC 8.1.4.1.6 Fails ate test step 7
+ * [ENPDCP] change for securty suspension.
+ * - ENPDCP_FLAG_DL_SECURITY_EN and ENPDCP_FLAG_UL_SECURITY_EN only depends on SRB1.
+ * Suspending the security of RBs excluding SRB1 does not change the security flag.
+ * - This change supports for the suspension of indivisual RB.
+ * when the security of a RB is suspended, integrity and cipher of it are turned off (ul: zero MACI/dl: skip & null cipher).
+ *
+ * 08 01 2019 head.hsu
+ * [MOLY00427285] [6297][NRRC][ENPDCP] 5G inter-RAT dev
+ * release from NR (SAP)
+ *
+ * 05 30 2019 charley-cc.cheng
+ * [MOLY00402003] [VMOLY] GEMINI N+L DSDS
+ *
+ * [CONFIG][SA and NSA Gemini] Config code and interface
+ *
+ * 01 31 2019 yiting.cheng
+ * [MOLY00382599] [GEN97][ENPDCP] PDCP entity suspend procedure
+ * .
+ *
+ * 01 25 2019 yiting.cheng
+ * [MOLY00381176] [GEN97][ENPDCP/ERRC/ETC] new loopback mode interface
+ * .
+ *
+ * 01 18 2019 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Modify RRC-ENPDCP SAP constant
+ *
+ * 01 08 2019 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Interface for LBM - new and old interface co-exist
+ *
+ * 11 29 2018 mingtsung.sun
+ * [MOLY00361902] [Gen97][KS-IODT][5G][R15_ENDC_RLC_COMPLETE_SEG_Change_june][1] Assert fail: protocol/enl2/el2_sec/el2it/copro/src/cipher.c 533 - EL1B_U4G_ADAPTOR
+ * Integrate FPGA SEP DEV
+ *
+ * 10 19 2018 nienteh.hsu
+ * [MOLY00352007] [MT6297] NRLC development: NRLCUL Gemini code check-in
+ *
+ * .
+ *
+ * 10 04 2018 shihyu.wang
+ * [MOLY00356595] [Gen97][ENPDCP] EPDCP FeMDT Feature
+ *
+ * upgrade ENPDCP_SAP_MAX_NUM_QUEUING_DELAY_DSLT to align max DRB number
+ *
+ * 10 02 2018 shihyu.wang
+ * [MOLY00356595] [Gen97][ENPDCP] EPDCP FeMDT Feature
+ *
+ * rollback old interface
+ *
+ * 09 14 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * add primary_cgid_valid and primary_lcid_valid
+ *
+ * 08 27 2018 antti.kaisto
+ * [MOLY00346011] [Gen97][NRRC] Merge to VMOLY TRUNK
+ * Merge enl2_sap_common.h from CL#6159798.
+ *
+ * 08 17 2018 yk.liu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * merge EMOLY CLs to VMOLY
+ *
+ * 08 07 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * SDAP configuration and 5QI update
+ *
+ * 07 24 2018 antti.kaisto
+ * [MOLY00309859] [6297][NRRC] CONFIG module EN-DC implementation
+ * NRRC CONFIG: Corrections to L2 configuration handling (prioritisedBitRate for SRBs validation, t-Reordering).
+ *
+ * 07 12 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Remove dc_bearer_type according to SAP
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ *
+ * 07 02 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * New interface for PDCP duplication
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ *
+ * 06 21 2018 doug.shih
+ * [MOLY00324797] [6297][ERRC] CHM development
+ * modification for suspend_scg cmd interface change.
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: NO]
+ * [Group CL list: WAIT]
+ * .
+ *
+ * 05 30 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * RRC-ENPDCP Gemini VC interface naming change
+ *
+ * 05 18 2018 head.hsu
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * port latest interface and code on Gen97.DEV (interface)
+ *
+ ****************************************************************************/
+
+#ifndef _ENL2_SAP_COMMON_H_
+#define _ENL2_SAP_COMMON_H_
+
+#include "kal_public_api.h"
+
+/*****************************************************************************
+ * CONSTANTS
+ *****************************************************************************/
+#define ENPDCP_SAP_MAX_NUM_CFG_RB 32 /* SRB: 3 (SRB1, SRB2, SRB3)
+ * DRB:
+ * - LTE: 8 (36.331 section 11.1 specifies the number of DRBs constraint is 8)
+ * - NR: 29 ((38.331 section 6.4 specifies the number of DRBs constraint is 29))
+ */
+
+#define ENPDCP_SAP_MAX_NUM_RB_IDX 8 /* Although RB Index allocation can be 0~36, but the association of EBI (EBI value range: 0~15)
+ * and RB ID one-to-one mapping attribute and the maximum number of DRBs (8) make the interface
+ * only has a maximum number 8 */
+
+#define ENPDCP_SAP_MAX_ROHC_PROF 9
+
+#define ENPDCP_SAP_MAX_NUM_QUEUING_DELAY_RSLT (8) ///< aligned to maximum number of DRBs in LTE
+
+
+
+#define MAX_EMBMS_MTCH_SUPPORT 8
+#define MAX_EMBMS_MRB_SUPPORT MAX_EMBMS_MTCH_SUPPORT
+#define MAX_EMBMS_MCCH_SUPPORT 8
+#define MAX_AREA_NUM_PER_CELL 8
+#define MAX_MTCH_NUM_PER_PMCH_29 29
+#define MAX_SF_IN_ONE_RF 6
+#define MAX_MBSFN_ALLOCATIONS 8
+#define MAX_PMCH_PER_MBSFN 15
+#define MAX_NUM_MTCH_PER_PMCH 29
+#define MAX_QOS_FLOWS_PER_PDU_SESSION 64
+#define MAX_NUM_PDU_SESSION 16
+#define ENPDCP_T_REORDERING_TIMER_INFINITY 0xFFFF
+#define ENPDCP_DISCARD_TIMER_INFINITY 0xFFFF
+#define ENPDCP_UL_DATA_SPLIT_THRESHOLD_INFINITY 0xFFFFFFFF
+#define ENPDCP_SRB3_RB_IDX_VALUE 16
+#define ENPDCP_SRB2_RB_IDX_VALUE 17
+#define ENPDCP_SRB1_RB_IDX_VALUE 18
+#define ENPDCP_MTCH_RB_IDX_VALUE 15
+#define ENPDCP_MCCH_RB_IDX_VALUE 19
+#define ENPDCP_NR_DRB_RB_IDX_RANGE1_MIN_VALUE 0
+#define ENPDCP_NR_DRB_RB_IDX_RANGE1_MAX_VALUE 14
+#define ENPDCP_NR_DRB_RB_IDX_RANGE2_MIN_VALUE 20
+#define ENPDCP_NR_DRB_RB_IDX_RANGE2_MAX_VALUE 36
+#define ENL2_RB_IDX_DEDICATED_NUM 15
+#define ENL2_RB_IDX_DEDICATED_MIN ENPDCP_NR_DRB_RB_IDX_RANGE1_MIN_VALUE
+#define ENL2_RB_IDX_DEDICATED_MAX ENPDCP_NR_DRB_RB_IDX_RANGE1_MAX_VALUE
+#define ENL2_RB_IDX_SHARED_MIN ENPDCP_NR_DRB_RB_IDX_RANGE2_MIN_VALUE
+#define ENL2_RB_IDX_SHARED_MAX ENPDCP_NR_DRB_RB_IDX_RANGE2_MAX_VALUE
+
+/*****************************************************************************
+ * ENUM TYPES
+ *****************************************************************************/
+typedef enum {
+ ENPDCP_RB_TYPE_SRB,
+ ENPDCP_RB_TYPE_DRB
+} enpdcp_rb_type_enum;
+
+typedef enum {
+ ENPDCP_PDCP_VERSION_LTE_PDCP,
+ ENPDCP_PDCP_VERSION_NR_PDCP
+} enpdcp_pdcp_version_enum;
+
+typedef enum {
+ ENPDCP_RB_CMD_EST_N_SUSP,
+ ENPDCP_RB_CMD_EST_N_RESUME,
+ ENPDCP_RB_CMD_SUSPEND,
+ ENPDCP_RB_CMD_RECONFIG,
+ ENPDCP_RB_CMD_RE_ESTABLISH,
+ ENPDCP_RB_CMD_RECOVERY,
+ ENPDCP_RB_CMD_RESUME,
+ ENPDCP_RB_CMD_DISCARD,
+ ENPDCP_RB_CMD_RELEASE,
+ ENPDCP_RB_CMD_RELEASE_FROM_LTE,
+ ENPDCP_RB_CMD_RELEASE_FROM_NR,
+} enpdcp_rb_cmd_enum;
+
+/* cause of CONFIG_REQ */
+typedef enum
+{
+ ENPDCP_SAP_CONFIG_REQ_CAUSE_OTHERS = 0, // used for those ENPDCP doesn't care
+ ENPDCP_SAP_CONFIG_REQ_CAUSE_HANDOVER,
+ ENPDCP_SAP_CONFIG_REQ_CAUSE_HANDOVER_FROM_LTE, // inter-RAT (from LTE)
+ ENPDCP_SAP_CONFIG_REQ_CAUSE_HANDOVER_FROM_NR, // inter-RAT (from NR)
+
+ ENPDCP_SAP_CONFIG_REQ_CAUSE_NUM,
+ ENPDCP_SAP_CONFIG_REQ_CAUSE_PAD = 0x7fffffff
+} enpdcp_config_req_cause_enum;
+
+typedef enum {
+ ENPDCP_DRB_TYPE_LTE,
+ ENPDCP_DRB_TYPE_LWA
+} enpdcp_drb_type_enum;
+
+typedef enum {
+ ENPDCP_CN_GENERATION_EPS,
+ ENPDCP_CN_GENERATION_5G
+} enpdcp_cn_generation_enum;
+
+typedef enum {
+ ENPDCP_ROHC_STATUS_NOT_CONFIGURED,
+ ENPDCP_ROHC_STATUS_BIDIR,
+ ENPDCP_ROCH_STATUS_UL_ONLY
+} enpdcp_rohc_status_enum;
+
+typedef enum {
+ ENPDCP_STUS_RPT_TYPE_ON_POLL_TYPE_1,
+ ENPDCP_STUS_RPT_TYPE_ON_POLL_TYPE_2
+} enpdcp_stus_rpt_type_on_poll_enum;
+
+typedef enum {
+ ENPDCP_RLC_MODE_AM,
+ ENPDCP_RLC_MODE_UM_BIDIR,
+ ENPDCP_RLC_MODE_UM_UL,
+ ENPDCP_RLC_MODE_UM_DL
+} enpdcp_rlc_mode_enum;
+
+typedef enum
+{
+ ENPDCP_LB_CMD_DEACTIVATE,
+ ENPDCP_LB_CMD_ACTIVATE_MODE_A,
+ ENPDCP_LB_CMD_ACTIVATE_MODE_B
+} enpdcp_lb_cmd_enum;
+
+typedef enum {
+ ENPDCP_CIPHERING_ALG_EEA0_NEA0,
+ ENPDCP_CIPHERING_ALG_EEA1_NEA1,
+ ENPDCP_CIPHERING_ALG_EEA2_NEA2,
+ ENPDCP_CIPHERING_ALG_EEA3_NEA3
+} enpdcp_ciphering_alg_enum;
+
+typedef enum {
+ ENPDCP_INTEGRITY_ALG_EIA0_NIA0,
+ ENPDCP_INTEGRITY_ALG_EIA1_NIA1,
+ ENPDCP_INTEGRITY_ALG_EIA2_NIA2,
+ ENPDCP_INTEGRITY_ALG_EIA3_NIA3
+} enpdcp_integrity_alg_enum;
+
+typedef enum
+{
+ ENPDCP_SAP_MEASUREMENT_OFF = 0,
+ ENPDCP_SAP_MEASUREMENT_ON,
+ ENPDCP_SAP_MEASUREMENT_MODIFY
+} enpdcp_delay_measurement_enum;
+
+
+/* UDC enum */
+typedef enum
+{
+ ENPDCP_SAP_UDC_BUF_SZ_KBYTE_2 = 0,
+ ENPDCP_SAP_UDC_BUF_SZ_KBYTE_4,
+ ENPDCP_SAP_UDC_BUF_SZ_KBYTE_8,
+
+ ENPDCP_SAP_UDC_BUF_SZ_KBYTE_PAD = 0x7fffffff
+} enpdcp_udc_buf_sz_enum;
+
+typedef enum
+{
+ ENPDCP_SAP_UDC_DIC_INVALID = 0,
+ ENPDCP_SAP_UDC_DIC_STANDARD,
+ ENPDCP_SAP_UDC_DIC_OPERATOR,
+
+ ENPDCP_SAP_UDC_DIC_PAD = 0x7fffffff
+} enpdcp_udc_dic_enum;
+
+typedef enum
+{
+ ENPDCP_SEC_CFG_CMD_INVALID = 0,
+ ENPDCP_SEC_CFG_CMD_UPDATE,
+ ENPDCP_SEC_CFG_CMD_SUSPEND
+} enpdcp_sec_cfg_cmd_enum;
+
+/*--------------------------------------------------------------------------
+ * RRC configuration to enter/leave virtual connected state
+ *--------------------------------------------------------------------------*/
+
+/// command to pdcp and rlc
+
+typedef enum
+{
+ RRC_ENL2_VIRTUAL_CONNECTED_ENTER_PREPARE = 0, // PDCP, RLC-UL
+ RRC_ENL2_VIRTUAL_CONNECTED_ENTER = 1, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_ENTER_END = 2, // PDCP, NRLC-UL
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_PREPARE = 3, // PDCP
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE = 4, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_FAIL_TO_RELEASE = 5, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_FAIL_TO_REESTABLISH = 6, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_ENTER_PREPARE_FOR_SRLTE = 7, // RLC-UL
+ RRC_ENL2_VIRTUAL_CONNECTED_ENTER_FOR_SRLTE = 8, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_ENTER_END_FOR_SRLTE = 9, // PDCP
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_PREPARE_FOR_SRLTE = 10, // PDCP
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_FOR_SRLTE = 11, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_FAIL_TO_RELEASE_FOR_SRLTE = 12, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_LEAVE_FAIL_TO_REESTABLISH_FOR_SRLTE = 13, // PDCP, RLC-UL, RLC-DL
+ RRC_ENL2_VIRTUAL_CONNECTED_INVALID_CAUSE = 14,
+} rrc_enl2_switch_virtual_connected_enum;
+
+/*****************************************************************************
+ * STRUCTURES
+ *****************************************************************************/
+typedef struct {
+ kal_uint8 pdu_session_id; /* PDU session ID */
+ kal_bool is_sdap_header_present_in_dl; /* specify if SDAP header is present in DL in this DRB or not */
+ kal_bool is_sdap_header_present_in_ul; /* specify if SDAP header is present in UL in this DRB or not */
+ kal_bool is_default_drb; /* specify if this DRB is the default DRB for the PDU session */
+ kal_uint8 mapped_qos_flows_add_num; /* number of QoS flows of the PDU session indicated by 'pdu_session_id' to be added to be mapped to this DRB */
+ kal_uint8 mapped_qos_flows_add_list[MAX_QOS_FLOWS_PER_PDU_SESSION]; /* Array of QoS flows of the PDU session indicated by 'pdu_session_id' to be added to be mapped to this DRB */
+ kal_uint8 mapped_qos_flows_rel_num; /* number of QoS flows of the PDU session indicated by 'pdu_session_id' to be released from being mapped to this DRB. */
+ kal_uint8 mapped_qos_flows_rel_list[MAX_QOS_FLOWS_PER_PDU_SESSION]; /* Array of QoS flows of the PDU session indicated by 'pdu_session_id' to be released from being mapped to this DRB. */
+} enpdcp_sdap_config_struct;
+
+
+typedef struct {
+ kal_bool type_on_poll_valid; /* specify if 'type_on_poll' is valid or not */
+ enpdcp_stus_rpt_type_on_poll_enum type_on_poll; /* indicate the PDCP Control PDU option when it is triggered by E-UTRAN polling */
+ kal_bool type1_periodicity_valid; /* specify if 'type1_periodicity' is valid or not */
+ kal_bool type2_periodicity_valid; /* specify if 'type2_periodicity' is valid or not */
+ kal_bool offset_valid; /* specify if 'offset' is valid or not */
+ kal_bool type1_periodicity_recfg; /* specify if type1 periodicity configuration is reconfigured */
+ kal_bool type2_periodicity_recfg; /* specify if type2 periodicity configuration is reconfigured */
+ kal_uint32 type1_periodicity; /* indicate the value of the PDCP Status reporting periodicity for type1 Status PDU */
+ kal_uint32 type2_periodicity; /* indicate the value of the PDCP Status reporting periodicity for type2 Status PDU */
+ kal_uint32 offset; /* indicate the value of the offset for type2 Status PDU periodicity */
+} enpdcp_stus_rpt_param_struct;
+
+
+typedef struct {
+ enpdcp_drb_type_enum drb_type; /* specify the DRB Type is LWA or LTE, only for LTE PDCP */
+ enpdcp_sdap_config_struct sdap_config; /* valid only when cn_generation indicate 5G */
+ kal_uint8 eps_bearer_id; /* value range: 0-15 */
+ kal_bool is_gbr_bearer; /* specify if EPS bearer is guaranteed bit rate bearer */
+ kal_bool qci_valid; /* specify if 'qci' is valid or not */
+ kal_uint8 qci; /* QoS Class Identfier */
+ enpdcp_rohc_status_enum rohc_status; /* specify if RoHC is configured or not, and if RoHC is bi-directional or UL only */
+ kal_uint16 rohc_max_cid; /* parameter MAX_CID, see 36.323 and 38.323 */
+ kal_bool rohc_profs[ENPDCP_SAP_MAX_ROHC_PROF]; /* parameter PROFILES, see 36.323 and 38.323 */
+ kal_bool drb_continue_rohc; /* specify if the header compression protocol context continues or is reset */
+ kal_uint16 discard_timer; /* timer discardTimer, see 36.323 and 38.323, please use ENPDCP_DISCARD_TIMER_INFINITY for 'infinity' */
+ kal_bool status_report_required; /* parameter statusReportRequired, see 36.323 and 38.323 */
+ enpdcp_stus_rpt_param_struct stus_rpt_param; /* status report parameter for LWA type DRB */
+ kal_bool out_of_order_delivery; /* parameter outOfOrderDelivery, see 38.323 */
+
+ enpdcp_rlc_mode_enum rlc_mode; /* specify RLC mode, and for RLC UM also direction, of associated RLC bearer(s) */
+ kal_uint8 sn_size_dl; /* PDCP SN size in DL */
+ kal_uint8 sn_size_ul; /* PDCP SN size in UL */
+
+ kal_bool udc_enabled;
+ enpdcp_udc_buf_sz_enum udc_buf_sz;
+ enpdcp_udc_dic_enum udc_dic;
+} enpdcp_drb_params_struct;
+
+
+typedef struct {
+ enpdcp_ciphering_alg_enum ciphering_algorithm; /* ciphering algorithm */
+ enpdcp_integrity_alg_enum integrity_algorithm; /* integrity algorithm */
+ kal_uint8 ciphering_key_idx; /* index of KRRCenc / KUPenc ciphering key in cipher HW, value range: 0-255 */
+ kal_uint8 integrity_key_idx; /* index of KRRCint / KUPint integrity key in cipher HW, value range: 0-255 */
+} enpdcp_sec_cfg_struct;
+
+
+typedef struct {
+ kal_bool primary_path_cell_group_id_valid; /* specify if primary_path_cell_group_id is valid or not */
+ kal_uint8 primary_path_cell_group_id; /* cell group ID of the primary RLC bearer */
+ kal_bool primary_path_lcid_valid; /* specify if primary_path_lcid is valid or not */
+ kal_uint8 primary_path_lcid; /* logical channel identity (LCID) of the primary RLC bearer */
+ kal_bool ul_data_split_threshold_valid; /* specify if 'ul_data_split_threshold' is valid or not */
+ kal_uint32 ul_data_split_threshold; /* parameter ul-DataSplitThreshold, see 38.323, please use ENPDCP_UL_DATA_SPLIT_THRESHOLD_INFINITY for 'Infinity' */
+ kal_bool ul_duplication; /* parameter 'pdcpDuplication', see 38.323 */
+ kal_bool ul_duplication_activated_valid; /* specify if 'ul_duplication_activated' is valid or not */
+ kal_bool ul_duplication_activated;
+} enpdcp_more_than_one_rlc_config_struct;
+
+
+typedef struct {
+ enpdcp_drb_params_struct drb_params; /* Parameters which apply only when radio bearer is DRB, valid only for DRB */
+ enpdcp_sec_cfg_cmd_enum sec_cfg_cmd; /* specify if 'sec_cfg' is valid or not */
+ enpdcp_sec_cfg_struct sec_cfg; /* security parameters for ciphering and integrity */
+ kal_bool t_reordering_valid; /* specify if 't_reordering' is valid or not */
+ kal_uint16 t_reordering; /* specify 't_reordering' value, please use ENPDCP_T_REORDERING_TIMER_INFINITY for 'Infinity' */
+ kal_bool more_than_one_rlc_config_valid; /* specify if 'more_than_once_rlc_config' is valid or not */
+ enpdcp_more_than_one_rlc_config_struct more_than_one_rlc_config; /* parameters for the case when more than one RLC bearers are associated with the PDCP entity, only for NR PDCP */
+} enpdcp_rb_params_struct;
+
+
+typedef struct {
+ kal_uint8 rb_idx; /* RB Index for the added or modified RB, value range: 0-36 */
+ enpdcp_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-3, DRB: 1-32 */
+ enpdcp_cn_generation_enum cn_generation; /* specify core network generation. Identifies the radio bearer together with rb_type and rbid. */
+ enpdcp_pdcp_version_enum pdcp_version; /* specify if PDCP entity is LTE PDCP or NR PDCP */
+ kal_bool pdcp_entity_suspend; /* specify if ENPDCP should perform PDCP entity suspend as per 38.323 or not */
+ enpdcp_rb_cmd_enum cmd; /* operation command for the radio bearer */
+ enpdcp_rb_params_struct rb_params; /* parameters of the radio bearer */
+} enpdcp_rb_addmod_struct;
+
+
+typedef struct {
+ kal_uint8 rb_idx; /* RB Index for the release RB, value range: 0-36 */
+ enpdcp_rb_type_enum rb_type; /* SRB or DRB */
+ kal_uint8 rbid; /* RB Identity, value range: 1-32, SRB: 1-3, DRB: 1-32 */
+ enpdcp_cn_generation_enum cn_generation; /* specify core network generation. Identifies the radio bearer together with rb_type and rbid. */
+ kal_bool release_second_entity; /* Specifies whoich PDCP entity to release. */
+ enpdcp_rb_cmd_enum cmd; /* operation command for the radio bearer */
+} enpdcp_rb_rel_struct;
+
+typedef struct {
+ kal_uint64 lte_rb_bitmap; /// LTE version RB index bitmap
+ kal_uint64 nr_rb_bitmap; /// NR version RB index bitmap
+} enl2_rb_idx_bitmap_struct;
+
+typedef struct {
+ enl2_rb_idx_bitmap_struct config_list; /// current RB index Config list
+ enl2_rb_idx_bitmap_struct temp_list; /// RB index Re-Config list
+ kal_bool temp_list_active; /// if RRC already fork temp_list from config_list (for debug only)
+} enl2_rb_idx_rrc_struct;
+
+typedef struct {
+ enl2_rb_idx_rrc_struct errc; /// ERRC RB index bitmap
+ enl2_rb_idx_rrc_struct nrrc; /// NRRC RB index bitmap
+ kal_bool vc_state; /// is the protocol in VC
+} enl2_rb_idx_struct;
+
+#if defined(__GEMINI_LTE__)
+#define ENL2_RB_IDX_CTXT_NUM (2)
+#elif defined(__GTEST_ENABLE__)
+#define ENL2_RB_IDX_CTXT_NUM (2)
+#else
+#define ENL2_RB_IDX_CTXT_NUM (1)
+#endif
+
+#if __MTK_TARGET__
+#define L2_FLAG_CHK_64(bmp, i) (((kal_uint32 *)&(bmp))[((kal_uint32)i >> 5) & 1] & (1u << ((kal_uint32)i & 0x1F)))
+#define L2_FLAG_SET_64(bmp, i) (((kal_uint32 *)&(bmp))[((kal_uint32)i >> 5) & 1] |= (1u << ((kal_uint32)i & 0x1F)))
+#define L2_FLAG_CLR_64(bmp, i) (((kal_uint32 *)&(bmp))[((kal_uint32)i >> 5) & 1] &= ~(1u << ((kal_uint32)i & 0x1F)))
+#else
+#define L2_FLAG_CHK_64(v, ofst) ((v) & 1ull << (ofst))
+#define L2_FLAG_SET_64(v, ofst) ((v) |= 1ull << (ofst))
+#define L2_FLAG_CLR_64(v, ofst) ((v) &= ~(1ull << (ofst)))
+#endif
+
+/**
+ * @brief initialization function for enl2 rb index contexy
+ */
+void enl2_rb_idx_api_init();
+
+/**
+ * @brief for hacking API working
+ */
+void enl2_rb_idx_hack(kal_uint8 hack);
+
+/**
+ * @brief
+ * When EN-RRC received RRC-Reconfiguration from network and start IE check phase,
+ * the EN-RRC will invoke this API to fork current configure RB index list (called as config_list)
+ * as temp configure RB index list which (called as temp_list) imply
+ * the future RB index list if the reconfiguration result is success.
+ *
+ * @param sim_idx The protocol index to build temp_list
+ * @param src_mod The source RRC to build temp_list
+ */
+void l2_rb_idx_fork_temp_list(kal_uint8 sim_idx, module_type src_mod);
+
+/**
+ * @brief
+ * The API will allocate a new RB index for the source RRC and protocol index.
+ * It will consider the L2 copro resource utilization and best effort ensure UE can stay DSDA mode.
+ * The new RB index will update to temp_list.
+ *
+ * @param sim_idx The protocol index to allocate new RB index to temp_list
+ * @param src_mod The source RRC to allocate new RB index to temp_list
+ * @param pdcp_ver The PDCP version of the new RB index of temp_list
+ *
+ * @return A available RB index for src_mod to be used. Range is [0, 14] and [20, 36]
+ */
+kal_uint8 l2_rb_idx_alloc_on_temp_list(kal_uint8 sim_idx, module_type src_mod, enpdcp_pdcp_version_enum pdcp_ver);
+
+/**
+ * @brief
+ * The API will update configuration of the specified RB index for the source RRC and protocol index.
+ * The change will update to temp_list.
+ *
+ * @param sim_idx The protocol index of the updated RB index
+ * @param src_mod The source RRC of the updated RB index
+ * @param rb_idx The RB index to be updated
+ * @param pdcp_ver The PDCP version of the updated RB index
+ */
+void l2_rb_idx_update_on_temp_list(kal_uint8 sim_idx, module_type src_mod, kal_uint8 rb_idx, enpdcp_pdcp_version_enum pdcp_ver);
+
+/**
+ * @brief
+ * The API will release configuration of the specified RB index for the source RRC and protocol index.
+ * The change will update to temp_list.
+ *
+ * @param sim_idx The protocol index of the released RB index
+ * @param src_mod The source RRC of the released RB index
+ * @param rb_idx The RB index to be released
+ */
+void l2_rb_idx_rel_on_temp_list(kal_uint8 sim_idx, module_type src_mod, kal_uint8 rb_idx);
+
+/**
+ * @brief
+ * When EN-RRC complete IE check phase and confirm the temp_list can be applied as new configuration,
+ * it invoke the API to copy temp_list to config_list.
+ *
+ * @param sim_idx The protocol index to apply the temp_list
+ * @param src_mod The source RRC to apply the temp_list
+ */
+void l2_rb_idx_apply_temp_list(kal_uint8 sim_idx, module_type src_mod);
+
+/**
+ * @brief
+ * When EN-RRC fail the IE check phase or judge the temp_list cannot be applied as new configuration,
+ * it invoke the API to discard temp_list.
+ * The config_list is still the current configuration.
+ *
+ * @param sim_idx The protocol index to discard the temp_list
+ * @param src_mod The source RRC to discard the temp_list
+ */
+void l2_rb_idx_discard_temp_list(kal_uint8 sim_idx, module_type src_mod);
+
+/**
+ * @brief
+ * When EN-RRC launch connection release directly even if the current procedure is not IE check phase,
+ * it will invoke the API to release all RB index in config_list and temp_list of the source RRC and protocol index.
+ *
+ * @param sim_idx The protocol index release all RB index
+ * @param src_mod The source RRC release all RB index
+ */
+void l2_rb_idx_reset(kal_uint8 sim_idx, module_type src_mod);
+
+/**
+ * @brief
+ * EN-RRC will update the VC status of specified protocol index to make ENL2 RB index API learn the information
+ * due to L2 Copro resource can be shared if a protocol is in Virtual Connected.
+ *
+ * @param sim_idx The protocol index to enter/leave VC
+ * @param is_enter_vc The source RRC to enter/leave VC
+ */
+void l2_rb_idx_set_vc(kal_uint8 sim_idx, kal_bool is_enter_vc);
+
+/**
+ * @brief
+ * MSPM invoke the API to query if the L2 Copro resource is conflict.
+ * The compared configuration are (config_list + temp_list) of any 2 SIM index.
+ *
+ * @return
+ * True, if the L2 Copro resource do not conflict by any 2 SIM combination under current state
+ * False, if the L2 Copro resource have conflict by one of 2 SIM combination under current state
+ */
+kal_bool l2_rb_idx_dual_active_status_check();
+
+#endif /* _ENL2_SAP_COMMON_H_ */
diff --git a/mcu/protocol/interface/enl2/en_common/errc_enpdcp_msg.h b/mcu/protocol/interface/enl2/en_common/errc_enpdcp_msg.h
new file mode 100644
index 0000000..e862e0b
--- /dev/null
+++ b/mcu/protocol/interface/enl2/en_common/errc_enpdcp_msg.h
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * errc_enpdcp_msg.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Messages and common definitions for ERRC-ENPDCP interface
+ *
+ * Author:
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ *
+ ****************************************************************************/
+
+
+#ifndef _ERRC_ENPDCP_MSG_H
+#define _ERRC_ENPDCP_MSG_H
+
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+
+#endif /* _ERRC_ENPDCP_MSG_H */
+
diff --git a/mcu/protocol/interface/enl2/en_common/rrc_enpdcp_msg.h b/mcu/protocol/interface/enl2/en_common/rrc_enpdcp_msg.h
new file mode 100644
index 0000000..4cf2c87
--- /dev/null
+++ b/mcu/protocol/interface/enl2/en_common/rrc_enpdcp_msg.h
@@ -0,0 +1,579 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * rrc_enpdcp_msg.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ * Messages and common definitions for RRC-ENPDCP interface
+ *
+ * Author:
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 05 18 2022 penny.wu
+ * [MOLY00775343] SCG failure suddenly and no SCG release received which caused long time PS service stuck
+ *
+ * SCG fail 20157558
+ *
+ * 10 21 2021 atlas.xu
+ * [MOLY00656491] ¡¾21041¡¿ ¡¾EVT¡¿¡¾¼ÃÄÏɨÍø¡¿¡¾5G-SA¡¿¡¾×é¼þ¡¿¡¾Í¨»°¡¿14µã38·Ö 21041CT+CU£¨Ë«5G£©¿¨¶þ¸±¿¨¶¯Ì¬Â·²âMTʧ°Ü3´Î£¨3/50£©
+ *
+ * .
+ *
+ *
+ * .
+ *
+ * 04 06 2020 yiting.cheng
+ * [MOLY00509299] [MT6873][Margaux][Q0][MP3][SQC][NSA][5GMM][NLO FT][Beijing][¤ýªÌ?Ä£][CT+CMCC][Bus]Margaux's total freezed latency lose Mate30(81s vs. 51s)
+ * .
+ *
+ * 03 23 2020 yiting.cheng
+ * [MOLY00502844] 2713368¡G¡i19165¡j¡iMP¡j¡i¤WÊI¡j²¾?¥dª`?5G¡A?ªk¤WÊI
+ * .
+ *
+ * 02 10 2020 yiting.cheng
+ * [MOLY00495934] [MT6873][Margaux][Q0][MP2][SQC][China][Shanghai][4GMM][Internal][FT][MDST][CAT][Moving][CT+CMCC]md1:(MCU_core0.vpe1.tc2(VPE1)) [ASSERT] file:mcu/driver/dpcopro/src/dpcopro_hisr.c line:775
+ * .
+ *
+ * 12 03 2019 sakari.niemela
+ * [MOLY00462238] [Gen97][VMOLY] Smart Idle Feature SA part(MPD)
+ * VGMM-NRRC, NRRC-ENPDCP and NRRC Internal SAP updates for 'Smart Idle'
+ *
+ * 10 14 2019 yiting.cheng
+ * [MOLY00442846] [Gen97] Modem´¼¯à«ÝÉófeature - NSA part (implementation)
+ * .
+ *
+ * 05 30 2019 charley-cc.cheng
+ * [MOLY00402003] [VMOLY] GEMINI N+L DSDS
+ *
+ * [CONFIG][SA and NSA Gemini] Config code and interface
+ *
+ * 04 25 2019 ken.li
+ * [MOLY00383711] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G]: Assert Fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ *
+ * EPDCP DL OOB and HFN desync handling
+ *
+ * 04 22 2019 ken.li
+ * [MOLY00383711] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G]: Assert Fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ *
+ * EPDCP DL OOB and HFN desync handling
+ *
+ * 01 25 2019 yiting.cheng
+ * [MOLY00381176] [GEN97][ENPDCP/ERRC/ETC] new loopback mode interface
+ * .
+ *
+ * 01 23 2019 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Add maci_len in DCCH_DATA_IND
+ *
+ * 01 18 2019 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Modify RRC-ENPDCP SAP constant
+ *
+ * 01 08 2019 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Interface for LBM - new and old interface co-exist
+ *
+ * 11 29 2018 mingtsung.sun
+ * [MOLY00361902] [Gen97][KS-IODT][5G][R15_ENDC_RLC_COMPLETE_SEG_Change_june][1] Assert fail: protocol/enl2/el2_sec/el2it/copro/src/cipher.c 533 - EL1B_U4G_ADAPTOR
+ * Integrate FPGA SEP DEV
+ *
+ * 10 31 2018 sakari.niemela
+ * [MOLY00342137] [6297][NRRC][NCONN] SA implementation
+ * [NCONN] Merge CBr3 to VMOLY.FPGA.SEP.DEV (part 3)
+ *
+ * 08 17 2018 yk.liu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * merge EMOLY CLs to VMOLY
+ *
+ * 06 14 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * Suspend SCG new interface
+ * Update reassemble order for full-configuration + PDCP version change
+ *
+ * 06 07 2018 nicky.chou
+ * [MOLY00320629] [6297] PS.DEV patch back to GEN97.DEV
+ * [ENPDCP] L3_CRITICAL_DATA for Gemini.
+ *
+ * 05 30 2018 yiting.cheng
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * RRC-ENPDCP Gemini VC interface naming change
+ *
+ * 05 28 2018 shihyu.wang
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in protocol interface patchback
+ *
+ * 03 28 2018 hannu.huusko
+ * [MOLY00308815] [6297][NRRC] MAIN module implementation
+ * NRRC-ENPDCP message ID update
+ *
+ *
+ ****************************************************************************/
+
+
+#ifndef _RRC_ENPDCP_MSG_H
+#define _RRC_ENPDCP_MSG_H
+
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+
+#include "enl2_sap_common.h"
+#include "el2_sap_common.h"
+#include "common_def.h"
+#include "as_inter_core_struct.h"
+/*****************************************************************************
+ * CONSTANTS
+ *****************************************************************************/
+/* numbers */
+#define ENPDCP_SAP_MAX_NUM_DRB (29) //8 DRBs
+
+
+/*****************************************************************************
+ * ENUM TYPES
+ *****************************************************************************/
+/* dcch_data_req flag_bmp bit index definition */
+typedef enum
+{
+ ENPDCP_DATAREQ_FLAG_SMC = 0,
+ ENPDCP_DATAREQ_FLAG_DRX_NO_WAKEUP = 1,
+ ENPDCP_DATAREQ_FLAG_TIME_BOUND = 2,
+ ENPDCP_DATAREQ_FLAG_L3_CRITICAL_DATA = 3
+} enpdcp_datareq_flag_enum;
+
+
+/* dcch_data_req result */
+typedef enum
+{
+ ENPDCP_DATAREQ_OK = 0,
+ ENPDCP_DATAREQ_FAILURE = 1
+}enpdcp_datareq_result_enum;
+
+
+/* integrity check result */
+typedef enum
+{
+ ENPDCP_INTCHK_OK = 0,
+ ENPDCP_INTCHK_FAILURE = 1, /* integrity check failure */
+ ENPDCP_INTCHK_SKIPPED = 2 /* integrity check is not applied */
+} enpdcp_intchk_result_enum;
+
+/* HFN desync RLF */
+typedef enum
+{
+ ENPDCP_CUT_CELL_SMALL_GRANT = 0,
+ ENPDCP_CUT_CELL_POSSIBLE_DCI_IN_MEAS_GAP = 1,
+ ENPDCP_CUT_CELL_INV
+} enpdcp_cut_cell_cause_enum;
+
+/* L2 cut cell ind cause */
+typedef enum
+{
+ ENPDCP_SAP_RLF_HFN_DESYNC = 0,
+ ENPDCP_SAP_RLF_ROHC_FAILURE = 1,
+ ENPDCP_SAP_RLF_SCG_ONLY_TX_FAILURE = 2,
+ ENPDCP_SAP_RLF_INV
+} enpdcp_rlf_cause_enum;
+
+
+/*****************************************************************************
+ * STRUCTURES
+ *****************************************************************************/
+typedef struct {
+ kal_uint8 mbsfn_area_id; /* value range: 0-255 */
+ kal_uint8 mcch_idx; /* numbered by eRRC(not from NW), value range 0-7 */
+} epdcp_mcch_add_struct;
+
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; /* value range: 0-255, currently for debug purpose only */
+ kal_uint8 mcch_idx; /* numbered by eRRC(not from NW), value range 0-7 */
+} epdcp_mcch_del_struct;
+
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; /* value range: 0-255 */
+ kal_uint8 pmch_id; /* value range: 0-15 */
+ kal_uint16 sessionId; /* 0xFFFF means no configure session id */
+ kal_uint8 TMGI[6]; /* Temporary Mobile Group Identity */
+ kal_uint8 lc_id; /* value range: 0-28 */
+ kal_uint8 mrb_idx; /* value range: 0-7, numbered by eRRC(not from NW) */
+} epdcp_mrb_add_struct;
+
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; /* value range: 0-255, currently for debug usage only */
+ kal_uint8 pmch_id; /* value range: 0-15, currently for debug usage only */
+ kal_uint16 sessionId; /* currently for debug usage only */
+ kal_uint8 TMGI[6]; /* currently for debug usage only */
+ kal_uint8 lc_id; /* value range: 0-28, currently for debug usage only */
+ kal_uint8 mrb_idx; /* value range: 0-7, numbered by eRRC(not from NW) */
+} epdcp_mrb_del_struct;
+
+
+/* RB COUNT info structure */
+typedef struct
+{
+ kal_uint8 rb_idx; //RB index
+ kal_uint8 rb_id;
+ kal_uint16 pad;
+
+ kal_uint32 rx_count; //HFN + SN
+ kal_uint32 tx_count; //HFN + SN
+} enpdcp_rb_cntinfo_struct;
+
+/* queuing delay result structure */
+typedef struct
+{
+ kal_uint8 qci;
+ kal_uint32 excess_delay_num;
+ kal_uint32 total_num;
+} enpdcp_delay_result_struct;
+
+
+/* PDCP queuing delay config structure */
+typedef struct{
+ kal_bool valid;
+ enpdcp_delay_measurement_enum measurement_status; // if valid=false, delay_theshold and delay_report_interval should be ignored
+ kal_uint32 threshold;
+ kal_uint32 report_interval;
+} enpdcp_delay_cfg_struct;
+
+
+/* RB loopback config structure */
+typedef struct
+{
+ kal_uint8 rbid;
+ kal_uint16 size; //scaling size
+} enpdcp_rb_lbcfg_struct;
+
+
+/*****************************************************************************
+ * MESSAGE STRUCTURE
+ *****************************************************************************/
+/* MSG_ID_ERRC_ENPDCP_CONFIG_REQ / MSG_ID_NRRC_ENPDCP_CONFIG_REQ */
+typedef struct {
+ LOCAL_PARA_HDR
+ /* common for ERRC and NRRC */
+ enpdcp_config_req_cause_enum cause;
+
+ kal_uint8 rel_num;
+ kal_uint8 mod_num;
+ kal_uint8 add_num;
+ enpdcp_rb_rel_struct rb_rel_list[ENPDCP_SAP_MAX_NUM_CFG_RB];
+ enpdcp_rb_addmod_struct rb_mod_list[ENPDCP_SAP_MAX_NUM_CFG_RB];
+ enpdcp_rb_addmod_struct rb_add_list[ENPDCP_SAP_MAX_NUM_CFG_RB];
+
+ /* ERRC only - LTE eMBMS configuration */
+ kal_uint8 mcch_add_num[MAX_EMBMS_FREQ_SUPPORT];
+ kal_uint8 mcch_del_num[MAX_EMBMS_FREQ_SUPPORT];
+ epdcp_mcch_add_struct mcch_add[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+ epdcp_mcch_del_struct mcch_del[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+ kal_uint8 mrb_add_num[MAX_EMBMS_FREQ_SUPPORT];
+ kal_uint8 mrb_del_num[MAX_EMBMS_FREQ_SUPPORT];
+ epdcp_mrb_add_struct mrb_add[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+ epdcp_mrb_del_struct mrb_del[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+
+ kal_bool suspend_scg_valid;
+ kal_bool suspend_scg;
+
+ kal_bool wait_for_key_update; // Specifies if ENPDCP needs to wait KEY_UPDATE_DONE_REQ before applying security procedures on PDCP PDU's.
+ enpdcp_delay_cfg_struct delay_cfg;
+} errc_enpdcp_config_req_struct, nrrc_enpdcp_config_req_struct;
+
+
+/*
+ * MSG_ID_ERRC_ENPDCP_MCCH_DATA_IND,
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 ci; /* 0~MAX_EMBMS_FREQ_SUPPORT-1 */
+ kal_uint8 mcch_idx;
+ kal_uint8 mcch_mp_id;
+ kal_uint8 resv; // this field would be used by ERRC; EPDCP reset it to 0 for ERRC
+ void *p_data;
+ kal_uint32 data_len; /* including RRC message & MAC-I */
+} errc_enpdcp_mcch_data_ind_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_DCCH_DATA_REQ / MSG_ID_NRRC_ENPDCP_DCCH_DATA_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rbid;
+ kal_uint16 trans_id;
+ kal_uint16 flag_bmp;
+ void *data_ptr;
+ kal_uint32 data_len;
+ KAL_AFM_ID afm_id;
+} errc_enpdcp_dcch_data_req_struct, nrrc_enpdcp_dcch_data_req_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_DCCH_DATA_CNF / MSG_ID_NRRC_ENPDCP_DCCH_DATA_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rbid;
+ kal_uint16 trans_id;
+ enpdcp_datareq_result_enum result;
+} errc_enpdcp_dcch_data_cnf_struct, nrrc_enpdcp_dcch_data_cnf_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_DCCH_DATA_IND / MSG_ID_NRRC_ENPDCP_DCCH_DATA_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rbid;
+ enpdcp_intchk_result_enum integrity_check_result;
+ kal_uint32 pdcp_count;
+ kal_uint32 maci_len;
+ void *data_ptr;
+ kal_uint32 data_len; /* including RRC message & MAC-I */
+} errc_enpdcp_dcch_data_ind_struct, nrrc_enpdcp_dcch_data_ind_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_DCCH_DATA_RSP / MSG_ID_NRRC_ENPDCP_DCCH_DATA_RSP */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rbid;
+} errc_enpdcp_dcch_data_rsp_struct, nrrc_enpdcp_dcch_data_rsp_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_CONFIG_CNF / MSG_ID_NRRC_ENPDCP_CONFIG_CNF */
+typedef struct {
+ LOCAL_PARA_HDR
+} errc_enpdcp_config_cnf_struct, nrrc_enpdcp_config_cnf_struct;
+
+/* MSG_ID_ERRC_ENPDCP_KEY_UPDATE_DONE_REQ / MSG_ID_NRRC_ENPDCP_KEY_UPDATE_DONE_REQ */
+typedef struct {
+ LOCAL_PARA_HDR
+} errc_enpdcp_key_update_done_req_struct, nrrc_enpdcp_key_update_done_req_struct;
+
+/* MSG_ID_ERRC_ENPDCP_TEST_REQ / MSG_ID_NRRC_ENPDCP_TEST_REQ */
+typedef struct {
+ LOCAL_PARA_HDR
+
+ enpdcp_lb_cmd_enum cmd;
+ kal_uint8 rb_num; // only valid for mode A
+ enpdcp_rb_lbcfg_struct rb_cfg[ENPDCP_SAP_MAX_NUM_DRB]; // only valid for mode A
+} errc_enpdcp_test_req_struct, nrrc_enpdcp_test_req_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_TEST_CNF / MSG_ID_NRRC_ENPDCP_TEST_CNF */
+typedef struct {
+ LOCAL_PARA_HDR
+} errc_enpdcp_test_cnf_struct, nrrc_enpdcp_test_cnf_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_SWITCH_VIRTUAL_CONNECTED_REQ / MSG_ID_NRRC_ENPDCP_SWITCH_VIRTUAL_CONNECTED_REQ */
+typedef struct {
+ LOCAL_PARA_HDR
+ rrc_enl2_switch_virtual_connected_enum status;
+} errc_enpdcp_switch_virtual_connected_req_struct, nrrc_enpdcp_switch_virtual_connected_req_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_SWITCH_VIRTUAL_CONNECTED_CNF / MSG_ID_NRRC_ENPDCP_SWITCH_VIRTUAL_CONNECTED_CNF */
+typedef struct {
+ LOCAL_PARA_HDR
+} errc_enpdcp_switch_virtual_connected_cnf_struct, nrrc_enpdcp_switch_virtual_connected_cnf_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_CNTINFO_REQ / MSG_ID_NRRC_ENPDCP_CNTINFO_REQ */
+typedef struct {
+ LOCAL_PARA_HDR
+} errc_enpdcp_cntinfo_req_struct, nrrc_enpdcp_cntinfo_req_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_CNTINFO_CNF / MSG_ID_NRRC_ENPDCP_CNTINFO_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rb_num;
+ kal_uint8 pad01;
+ kal_uint16 pad02;
+ enpdcp_rb_cntinfo_struct rb_cntinfo[ENPDCP_SAP_MAX_NUM_DRB];
+} errc_enpdcp_cntinfo_cnf_struct, nrrc_enpdcp_cntinfo_cnf_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_DETECTION_TIMER_START_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 detection_time_value;
+} errc_enpdcp_detection_timer_start_req_struct;
+
+/*
+ * MSG_ID_ERRC_ENPDCP_DETECTION_TIMER_2_START_REQ,
+ *
+ * note: ERRC configure ENPDPC detection timer value
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 detection_time_value; // in seconds
+} errc_enpdcp_detection_timer_2_start_req_struct;
+
+/*
+ * MSG_ID_ERRC_ENPDCP_DETECTION_TIMER_3_START_REQ,
+ *
+ * note: ERRC configure EPDPC detection timer value (T3)
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 detection_time_value; // in seconds
+ kal_bool restart_timer; // PDCP need to restart timer if True
+} errc_enpdcp_detection_timer_3_start_req_struct;
+
+/*
+ * MSG_ID_ERRC_ENPDCP_DETECTION_TIMER_3_TIMEOUT_IND,
+ *
+ * note: ERRC configure EPDPC detection timer (T3) TIMEOUT
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 exp_timer_value; // in seconds
+} errc_enpdcp_detection_timer_3_timeout_ind_struct;
+
+/* MSG_ID_NRRC_ENPDCP_DETECTION_TIMER_3_START_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 detection_time_value;
+ kal_bool restart_timer;
+} nrrc_enpdcp_detection_timer_3_start_req_struct;
+
+/* MSG_ID_NRRC_ENPDCP_DETECTION_TIMER_3_TIMEOUT_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool local_release_needed;
+} nrrc_enpdcp_detection_timer_3_timeout_ind_struct;
+
+/* MSG_ID_NRRC_ENPDCP_DETECTION_TIMER_4_START_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 detection_time_value; // in milliseconds
+} nrrc_enpdcp_detection_timer_4_start_req_struct;
+
+/* MSG_ID_ERRC_ENPDCP_PS_DATA_INACTIVE_TIME_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 inactive_time;
+} errc_enpdcp_ps_data_inactive_time_ind_struct;
+
+/*
+ * MSG_ID_ERRC_ENPDCP_EXCESS_DELAY_IND
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 list_num;
+ enpdcp_delay_result_struct result_list[ENPDCP_SAP_MAX_NUM_QUEUING_DELAY_RSLT];
+ kal_uint32 threshold;
+ kal_uint32 report_interval;
+} errc_enpdcp_excess_delay_ind_struct;
+
+/*
+ * MSG_ID_ERRC_ENPDCP_RLF_IND
+ * is_old_rb: indicate the RLF entity is the first one or second one that established for fullconfig handover
+ * true stands for the first entity
+ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rb_id;
+ kal_bool is_old_rb;
+ enpdcp_rlf_cause_enum cause;
+} errc_enpdcp_rlf_ind_struct;
+
+
+/* MSG_ID_ERRC_ENPDCP_CUT_CELL_IND / MSG_ID_NRRC_ENPDCP_CUT_CELL_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ enpdcp_cut_cell_cause_enum cause;
+ kal_bool is_cell_valid;
+ kal_uint32 earfcn;
+ kal_uint16 pci;
+ kal_uint16 bar_time; // in second
+} errc_enpdcp_cut_cell_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ enpdcp_cut_cell_cause_enum cause;
+ kal_bool is_cell_valid;
+ nr_cell_info nr_cell_info;
+ kal_uint16 bar_time; // in second
+} nrrc_enpdcp_cut_cell_ind_struct;
+
+#endif /* _RRC_ENPDCP_MSG_H */
diff --git a/mcu/protocol/interface/enl2/en_common/upcm_enpdcp_interface.h b/mcu/protocol/interface/enl2/en_common/upcm_enpdcp_interface.h
new file mode 100644
index 0000000..d33790a
--- /dev/null
+++ b/mcu/protocol/interface/enl2/en_common/upcm_enpdcp_interface.h
@@ -0,0 +1,129 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * upcm_enpdcp_interface.h
+ *
+ * Project:
+ * --------
+ * VMOLY
+ *
+ * Description:
+ * ------------
+ * UPCM-ENPDCP interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 12 2019 yiting.cheng
+ * [MOLY00421061] [Gen97] ANBR (RBR,RBRQ) over NR
+ * .
+ *
+ * 05 17 2019 tc.chang
+ * [MOLY00404770] [Gen97] Sync Gen95 UMOLYE patch
+ * BEARER_APP_REQ update.
+ *
+ ****************************************************************************/
+
+#ifndef __UPCM_ENPDCP_INTERFACE_H__
+#define __UPCM_ENPDCP_INTERFACE_H__
+
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+
+#include "ps_public_enum_public.h"
+#include "enl2_sap_common.h"
+
+typedef struct {
+ LOCAL_PARA_HDR
+
+ enpdcp_cn_generation_enum cn_generation;
+
+ /* Bit set to 1 iff the corresponding EPSB or PDU session is Internet.
+ * (DDM_APN_TYPE_DEFAULT)
+ * LSB: for EBI / PSI 0
+ * MSB: for EBI / PSI 15
+ */
+ kal_uint16 internet_bearer_bmp;
+
+ /* Bit set to 1 iff the corresponding EPSB or PDU session is IMS.
+ * (DDM_APN_TYPE_IMS)
+ * LSB: for EBI / PSI 0
+ * MSB: for EBI / PSI 15
+ */
+ kal_uint16 ims_bearer_bmp;
+
+ /* Valid when cn_generation is 5G.
+ * ims_signalling_5g_qfi[1] = 2; // PSI 1 QFI 2 is IMS signalling bearer.
+ */
+ kal_uint8 ims_signalling_5g_qfi[MAX_NUM_OF_SUPPORTED_PDUS + 1];
+
+} upcm_enpdcp_bearer_app_req_struct;
+
+typedef struct {
+ kal_uint8 psi;
+ kal_uint8 num_qfi;
+ kal_uint8 qfi[MAX_QOS_FLOWS_PER_PDU_SESSION];
+} upcm_enpdcp_rb_psi_qfi_struct;
+
+/**
+ * @brief get psi and qfi by rb_idx
+ *
+ * @param rb_idx
+ * @param psi_qfi the psi/num_qfi/qfi[] mapped by rb_idx, the API will update it
+ *
+ * @return void
+ */
+void upcm_enpdcp_rb_to_psi_qfi(kal_uint8 rb_idx, upcm_enpdcp_rb_psi_qfi_struct *psi_qfi, kal_uint8 protocol_idx);
+
+/**
+ * @brief get rb_idx by psi and qfi
+ *
+ * @param psi
+ * @param qfi
+ *
+ * @return rb_idx mapped by the corresponding psi/qfi, 0xFF means no mapped RB
+ */
+kal_uint8 upcm_enpdcp_psi_qfi_to_rb(kal_uint8 psi, kal_uint8 qfi, kal_uint8 protocol_idx);
+
+
+#endif // __UPCM_ENPDCP_INTERFACE_H__