[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/service/sst/include/SST_Concurrent_utility.h b/mcu/service/sst/include/SST_Concurrent_utility.h
new file mode 100644
index 0000000..48f7353
--- /dev/null
+++ b/mcu/service/sst/include/SST_Concurrent_utility.h
@@ -0,0 +1,328 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_concurrent_utility.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the necessary API needed by concurrent ulitity.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _SST_CONCURRENT_UTILITY_
+#define _SST_CONCURRENT_UTILITY_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Platform Capabilities Definition
+ *************************************************************************/
+
+/*************************************************************************
+ * Constant Definition : Option from NVRAM setting
+ *************************************************************************/
+#define SWLA_ADDON_EBM_R_LAT 0x10
+#define SWLA_ADDON_EBM_W_LAT 0x20
+
+/*************************************************************************
+ * Constant Definition : Sync with ELT Addon DLL
+ *************************************************************************/
+#define USAGE_TYPE_ELM (1UL << 0)
+#define USAGE_TYPE_EBM (1UL << 1)
+#define USAGE_TYPE_UR (1UL << 2)
+#define USAGE_TYPE_EBM_RLAT (1UL << 3)
+#define USAGE_TYPE_EBM_WLAT (1UL << 4)
+#define USAGE_TYPE_BMON (1UL << 5)
+
+
+/*************************************************************************
+ * ENUM Definition : Sync with Catcher
+ *************************************************************************/
+typedef enum
+{
+ HEADER_ID_MAIN_TQCNT = 0x00000001,
+ HEADER_ID_MAIN_USEC = 0x00000002,
+ HEADER_ID_RTOS_V1 = 0x00000000,
+ HEADER_ID_RTOS_V2 = 0x00000010,
+ HEADER_ID_TIME_STAMP_BASE = 0x00000100,
+ HEADER_ID_EXTRA_INFO = 0x00000103,
+ HEADER_ID_TWO_RATIOS = 0x00000104,
+ HEADER_ID_OVERHEAD = 0x00000105,
+ HEADER_ID_CUST_OVERHEAD = 0x00000106,
+ HEADER_ID_EXTERNAL_BN = 0x00010005,
+ HEADER_ID_EXTERNAL_EMI_GERNAL = 0x00010006,
+ HEADER_ID_EXTERNAL_EMI_PRO = 0x00010007,
+ HEADER_ID_EXTERNAL_TST = 0x00010008,
+ HEADER_ID_EXTERNAL_INST_COUNT = 0x0001000A,
+ HEADER_ID_EXTERNAL_CONCURRENCY = 0x0001000B,
+ HEADER_ID_EXTERNAL_MAX = 0x00010010,
+
+ /* The following is for MALMO ASM SWLA*/
+ HEADER_ID_MALMO_ASM_BASE = 0x10000000,
+ HEADER_ID_MALMO_ASM_FRAMENO,
+ HEADER_ID_MALMO_ASM_MCU_PC,
+ HEADER_ID_MALMO_ASM_CONTEXT_ID,
+ HEADER_ID_MALMO_ASM_PMC0,
+ HEADER_ID_MALMO_ASM_PMC1,
+ HEADER_ID_MALMO_ASM_PMC2,
+ HEADER_ID_MALMO_ASM_CYCLE_CNT,
+ HEADER_ID_MALMO_ASM_EMI_BCNT,
+ HEADER_ID_MALMO_ASM_EMI_BACT,
+ HEADER_ID_MALMO_ASM_EMI_BSCT,
+ HEADER_ID_MALMO_ASM_EMI_BSCT2,
+ HEADER_ID_MALMO_ASM_EMI_BSCT3,
+ HEADER_ID_MALMO_ASM_TIMESTAMP,
+ /* There might be more MALMO ASM entries in the future */
+
+ HEADER_ID_MALMO_ASM_EXTRA_BASE = 0x10001000,
+ HEADER_ID_MALMO_ASM_EXTRA0,
+ HEADER_ID_MALMO_ASM_EXTRA1,
+ HEADER_ID_MALMO_ASM_EXTRA2,
+ HEADER_ID_MALMO_ASM_EXTRA3
+
+} SA_HEADER_ID_T;
+
+/*************************************************************************
+ * Structure Definition : Basic and Professional EMI Monitor Logging Node
+ *************************************************************************/
+
+typedef struct SA_EBMAddonCounter_T
+{
+ kal_uint32 emi_md_r_wcnt;
+ kal_uint32 emi_md_w_wcnt;
+} SA_EBMAddonCounter;
+
+
+
+typedef struct SA_ELMAddonCounter_T
+{
+ kal_uint32 elm_r_tcnt; //mode 0 read trans count
+ kal_uint32 elm_w_tcnt; //mode 0 wrtie trans count
+ kal_uint32 elm_r_lat; //mode 0 read latency count
+ kal_uint32 elm_w_lat; //mode 0 write latency count
+#if defined(__MD95__)
+ kal_uint32 elm_r_wc; //mode 0 read word count
+ kal_uint32 elm_w_wc; //mode 0 write word count
+#endif
+} SA_ELMAddonCounter;
+
+//#define __SWLA_ADDON_SMIM__
+typedef struct BM_LOG_T
+{
+ // MD ELM
+ #if defined(__SWLA_ADDON_ELM__)
+ kal_uint32 elm_r_tcnt; //mode 1 read trans count
+ kal_uint32 elm_w_tcnt; //mode 1 read word count
+ kal_uint32 elm_r_lat; //mode 1 read latency count
+ kal_uint32 elm_w_lat; //mode 1 write word count
+ #endif
+
+ #if defined(__SWLA_ADDON_EBM__)
+ kal_uint32 emi_md_r_wcnt;
+ kal_uint32 emi_md_w_wcnt;
+ #endif /* __SWLA_ADDON_EBM__ */
+
+ #if defined(__SWLA_ADDON_PMU__)
+ #if defined(__PROFILE_PMU_START_END_CYC__)
+ kal_uint32 cr4_pmu_cycle_start;
+ kal_uint32 cr4_pmu_cycle_end;
+ #else
+ kal_uint32 cr4_pmu_dur;
+ #endif /* __PROFILE_PMU_START_END_CYC__ */
+ kal_uint32 cr4_pmu_event[3];
+ #endif /* __SWLA_ADDON_PMU__ */
+
+ #if defined(__SWLA_ADDON_EBM_LAT__)
+ kal_uint32 emi_md_r_tcnt;
+ kal_uint32 emi_md_w_tcnt;
+ kal_uint32 emi_md_r_lat_cnt;
+ kal_uint32 emi_md_w_lat_cnt;
+ #endif /* __SWLA_ADDON_EBM_LAT__ */
+
+ #if defined(__SWLA_ADDON_BMON__)
+ kal_uint32 busmon_mcu_tot_cyc;
+ /* index 0 for IP0, index 1 for IP1 */
+// kal_uint32 busmon_mcu_tot_nw_cycle[2]; // non weighted transaction cycles
+ kal_uint32 busmon_mcu_max_lat[2]; // maximal latency
+ kal_uint32 busmon_infra_max_lat[2]; // maximal latency
+ #endif /* __SWLA_ADDON_BMON__ */
+
+ #if defined(__SWLA_ADDON_SMIM__)
+ kal_uint32 smi_actCnt;
+ kal_uint32 smi_tCnt;
+ kal_uint32 smi_byteCnt;
+ #endif
+
+ #if !defined(__SWLA_ADDON_ELM__) && !defined(__SWLA_ADDON_EBM__) && !defined(__SWLA_ADDON_EBM_LAT__) && !defined(__SWLA_ADDON_PMU__)
+ kal_uint32 dummy;
+ #endif
+
+} BM_Log;
+
+/*************************************************************************
+ * Structure Definition : Auxiliary Structures
+ *************************************************************************/
+typedef struct EMI_Setting_T
+{
+ kal_uint32 usage_type;
+ kal_uint32 word_cnt;
+}EMI_Setting;
+
+/*************************************************************************
+ * Structure Definition : Basic and Professional EMI Monitor Init Reference
+ *************************************************************************/
+typedef struct BM_REF_T
+{
+ SA_HEADER_ID_T id;
+ kal_uint32 szRef;
+ EMI_Setting emi_settings;
+}BM_Ref;
+
+
+/*************************************************************************
+ * Exported APIs for Software LA
+ *************************************************************************/
+
+extern void Setup_AddOn_RefData(SA_HEADER_ID_T id, kal_uint8 **ARef, kal_uint32 *szARef);
+extern void Get_BM_Log( BM_Log* pLog );
+extern void Enable_Normal_EMI_Monitor(void);
+
+extern void SWLA_EBM_Setup_DLLInfo(kal_uint8 **ARef, kal_uint32 *szARef);
+
+extern void SA_ELM_AddonLogging(kal_uint32 * buff);
+extern void SA_EBM_AddonInit();
+extern kal_uint8* SA_EBM_AddonLogging_HWmode();
+extern void SA_EBM_AddonLogging_SWmode(kal_uint32 * buff);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SST_CONCURRENT_UTILITY_ */
diff --git a/mcu/service/sst/include/SST_fue_encrypt.h b/mcu/service/sst/include/SST_fue_encrypt.h
new file mode 100644
index 0000000..d61732a
--- /dev/null
+++ b/mcu/service/sst/include/SST_fue_encrypt.h
@@ -0,0 +1,99 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_fue_encrypt.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is SST encryption header
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __SST_FUE_ENCRYPT_H__
+#define __SST_FUE_ENCRYPT_H__
+
+#include "kal_public_api.h"
+
+typedef enum {
+ SB_STOP = 0
+ ,SB_DISABLE
+ ,SB_BBCHIP_UNSUPPORT
+ ,SB_HEADER_NOT_FOUND
+ ,SB_FIND_HEADER
+ ,SB_FIND_ENCODING_AREA
+ ,SB_FIND_SEED
+ ,SB_ENCODING
+ ,SB_FINISH
+} SB_ProcessState_E;
+
+// UID struct information
+extern SB_ProcessState_E g_SB_State;
+
+
+extern void EncryptBuffer(void* BufferAddr, const kal_uint32 packet_length);
+extern void EncryptInit(void);
+
+#endif /*__SST_FUE_ENCRYPT_H__*/
diff --git a/mcu/service/sst/include/SST_init.h b/mcu/service/sst/include/SST_init.h
new file mode 100644
index 0000000..0cfdb4c
--- /dev/null
+++ b/mcu/service/sst/include/SST_init.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_init.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for SW minor version.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+
+ ****************************************************************************/
+
+#ifndef _SST_INIT_H
+#define _SST_INIT_H
+
+#if (defined(MT6752) && defined(__MD1__))
+#define SW_MINOR_VER 0x1
+#elif defined(MT6280_S01)
+#define SW_MINOR_VER 0x1
+#else
+#define SW_MINOR_VER 0x0
+#endif
+
+#endif /* _SST_TRC_H */
diff --git a/mcu/service/sst/include/SST_intrCtrl.h b/mcu/service/sst/include/SST_intrCtrl.h
new file mode 100644
index 0000000..14e121f
--- /dev/null
+++ b/mcu/service/sst/include/SST_intrCtrl.h
@@ -0,0 +1,541 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Header file for non-release version of interrupt control.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
+ *
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+ *
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __SST_INTRCTRL_H__
+#define __SST_INTRCTRL_H__
+
+#include "us_timer.h"
+#include "reg_base.h"
+
+#if defined(__MD93__)
+ #if !defined(__FPGA__)
+ #define __QBIT_TIME_CHECK__ // use Qbit for timing check, else use microsecond
+ #define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
+ #else /* else of !defined(__FPGA__)*/
+ #define __QBIT_TIME_CHECK__ // use Qbit for timing check, else use microsecond
+ //#define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ #endif
+#elif defined(__MD95__) /* else if of defined(__MD93__)*/
+ #if !defined(__FPGA__)
+ #define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
+ #else /* else of !defined(__FPGA__)*/
+ //#define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ #endif
+#elif defined(__MD97__) /* else if of defined(__MD95__)*/
+ #if !defined(__FPGA__)
+ #define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
+ #else /* else of !defined(__FPGA__)*/
+ //#define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ #endif
+#elif defined(__MD97P__) /* else if of defined(__MD97__)*/
+ #if !defined(__FPGA__)
+ #define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
+ #else /* else of !defined(__FPGA__)*/
+ #define __HARD_REAL_TIME_CHECK__ //SW timing check
+ //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
+ //#define __DEADLOCK_DETECTION__
+ #endif
+#else /* else of defined(__MD93__)*/
+ #error "no chip definition match"
+#endif
+
+#if defined(__DEADLOCK_DETECTION__) && defined(__MDCIRQ_TIMING_CHECK_EN__)
+#error "deadlock detection and HW timing check cannot use together"
+#endif
+#if defined(__MDCIRQ_TIMING_CHECK_EN__) && !defined(__HARD_REAL_TIME_CHECK__)
+#error "We also need SW timing check for normal domain calling ITC APIs although HW timing check is enable"
+#endif
+
+
+#if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__) && !defined(__HARD_REAL_TIME_CHECK__)
+#error "Qbits check is not enable!! Qbits check fail logging cannot enable standalone!!"
+#endif
+
+
+#if defined(__MD93__)
+ #define SST_HR_DUR_HRT (45)
+ #define SST_HR_DUR_NON_HRT (1000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (55)
+ #endif
+#elif defined(__MD95__) /* else if of defined(__MD93__)*/
+#if defined (__KTEST__)
+ #define SST_HR_DUR_HRT (20000000)
+ #define SST_HR_DUR_NON_HRT (20000000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (20000000)
+ #endif
+#else
+ #define SST_HR_DUR_HRT (50)
+ #define SST_HR_DUR_NON_HRT (1000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (50)
+ #endif
+#endif // #if defined (__KTEST__)
+#elif defined(__MD97__) /* else if of defined(__MD95__)*/
+#if defined (__KTEST__)
+ #define SST_HR_DUR_HRT (200000000)
+ #define SST_HR_DUR_NON_HRT (200000000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (200000000)
+ #endif
+#else
+ #define SST_HR_DUR_HRT (80)
+ #define SST_HR_DUR_NON_HRT (1000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (80)
+ #endif
+#endif // #if defined (__KTEST__)
+#elif defined(__MD97P__) /* else if of defined(__MD97__)*/
+#if defined (__KTEST__)
+ #define SST_HR_DUR_HRT (200000000)
+ #define SST_HR_DUR_NON_HRT (200000000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (200000000)
+ #endif
+#else
+ #define SST_HR_DUR_HRT (60)
+ #define SST_HR_DUR_NON_HRT (1000)
+ #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ #define SST_HR_DUR_HRT_LOG (200)
+ #endif
+#endif // #if defined (__KTEST__)
+#else /* else of defined(__MD93__)*/
+ #error "no chip definition match"
+#endif
+
+#if defined(__FPGA__)
+#define SST_HR_DUR_HRT_WD (2000*1000)
+#define SST_HR_DUR_NON_HRT_WD (2000*1000)
+#else
+#define SST_HR_DUR_HRT_WD (2000)
+#define SST_HR_DUR_NON_HRT_WD (2000)
+
+#endif
+
+#define SST_IRQ_MASK (0x00000001)
+
+#if defined(__HW_US_TIMER_SUPPORT__) /* !__CR4__ */
+
+#define GET_AND_SAVED_TIME(v, vpe_num) do{\
+ IRQMaskCounter[vpe_num] = ust_get_current_time();\
+ IRQMaskValue[vpe_num] = v;\
+ }while(0)
+
+#define GET_AND_SAVED_TIME_HRT(vpe_num) do{\
+ HRTQbitCounter[vpe_num] = ust_get_current_time();\
+ }while(0)
+
+#define GET_CURRENT_TIME(v) do{\
+ v = ust_get_current_time();\
+ }while(0)
+
+#define GET_SAVED_TIME(v,vpe_num) do{\
+ v = IRQMaskCounter[vpe_num];\
+ }while(0)
+
+#define GET_SAVED_TIME_HRT(v,vpe_num) do{\
+ v = HRTQbitCounter[vpe_num];\
+ }while(0)
+
+#define GET_DURATION(d,t1,t2) do{\
+ d = ((t2) >= (t1)) ? ((t2) - (t1)) : (USCNT_WRAP - (t1) + (t2) + 1);\
+ }while(0)
+
+#define TRANS_TO_QBIT(d,s) do{\
+ d = (((s)*13)/12);\
+ }while(0)
+
+#if defined(__FPGA__) && !defined(__KTEST__)
+ /* Check us directly instead of qbits in gen95/gen97 */
+ #if !defined(__QBIT_TIME_CHECK__)
+ #define IRQ_DISABLE_MAX_DURATION_HRT (SST_HR_DUR_HRT*1000)
+ #define IRQ_DISABLE_MAX_DURATION_NON_HRT (SST_HR_DUR_NON_HRT*1000)
+ #else
+ #define IRQ_DISABLE_MAX_DURATION_HRT ((SST_HR_DUR_HRT*12)/13*1000)
+ #define IRQ_DISABLE_MAX_DURATION_NON_HRT ((SST_HR_DUR_NON_HRT*12)/13*1000)
+ #endif
+#else
+ /* Check us directly instead of qbits in gen95/gen97 */
+ #if !defined(__QBIT_TIME_CHECK__)
+ #define IRQ_DISABLE_MAX_DURATION_HRT (SST_HR_DUR_HRT)
+ #define IRQ_DISABLE_MAX_DURATION_NON_HRT (SST_HR_DUR_NON_HRT)
+ #else
+ #define IRQ_DISABLE_MAX_DURATION_HRT ((SST_HR_DUR_HRT*12)/13)
+ #define IRQ_DISABLE_MAX_DURATION_NON_HRT ((SST_HR_DUR_NON_HRT*12)/13)
+ #endif
+#endif
+
+#if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+ /* Check us directly instead of qbits in gen95/gen97 */
+ #if !defined(__QBIT_TIME_CHECK__)
+ #define IRQ_DISABLE_MAX_DURATION_HRT_LOG (SST_HR_DUR_HRT_LOG)
+ #else
+ #define IRQ_DISABLE_MAX_DURATION_HRT_LOG ((SST_HR_DUR_HRT_LOG*12)/13)
+ #endif
+#endif
+
+#if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
+typedef struct{
+ kal_uint32 violationAddress;
+ kal_uint32 violationDuration;
+} HRTQbitFailLogStruct;
+#define HRTQbitFailLogSize 32
+#endif
+
+#else /* !__HW_US_TIMER_SUPPORT__ */
+
+#error "No timing check counter support!"
+
+#endif /* __HW_US_TIMER_SUPPORT__ */
+
+kal_uint32 query_Qbits_criteria_nonHRT(void);
+kal_uint32 query_Qbits_criteria_nonHRT_us(void);
+kal_uint32 query_Qbits_criteria_HRT(void);
+kal_uint32 query_Qbits_criteria_HRT_us(void);
+
+#endif /* __SST_INTRCTRL_H__ */
diff --git a/mcu/service/sst/include/SST_mem_utility.h b/mcu/service/sst/include/SST_mem_utility.h
new file mode 100644
index 0000000..882861f
--- /dev/null
+++ b/mcu/service/sst/include/SST_mem_utility.h
@@ -0,0 +1,106 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2015
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_mem_utility.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _SST_MEM_UTILITY_H
+#define _SST_MEM_UTILITY_H
+
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+/*******************************************************************************
+ * Constant Definition
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Macro definition
+ *******************************************************************************/
+
+
+
+#define L1_NBR_OF_WORDS_IN_LINE 8
+struct l1_icache_line {
+ kal_uint32 address;
+ kal_uint32 line[L1_NBR_OF_WORDS_IN_LINE];
+};
+
+#define L2_NBR_OF_WORDS_IN_LINE 16
+struct l2_cache_line {
+ kal_uint32 address;
+ kal_uint32 line[L2_NBR_OF_WORDS_IN_LINE];
+};
+
+extern kal_uint32 get_program_counter(void);
+extern kal_bool read_instruction(kal_uint32 addr, kal_uint32 *instruction);
+
+extern void SST_GetSysStackInfo(kal_uint32 * const base, kal_uint32 * const end,
+ kal_uint32 core, kal_uint32 tc);
+
+extern void SST_GetCurrentSysStackInfo(kal_uint32 * const base, kal_uint32 * const end);
+extern void SST_GetTaskStackInfo(kal_uint32 task_index, kal_uint32 * const base, kal_uint32 * const end);
+extern void SST_GetTaskStackPointer(kal_uint32 task_index, kal_uint32 * const pointer);
+extern void SST_GetHisrStackInfo(kal_uint32 hisr_index, kal_uint32 * const base, kal_uint32 * const end);
+extern void SST_GetCurrentStackInfo(kal_uint32 * const base, kal_uint32 * const end);
+extern kal_bool SST_CheckIfSP(kal_uint32 mem_ptr);
+
+#endif /* _SST_MEM_UTILITY_H */
diff --git a/mcu/service/sst/include/SST_nvram_record.h b/mcu/service/sst/include/SST_nvram_record.h
new file mode 100644
index 0000000..be460f8
--- /dev/null
+++ b/mcu/service/sst/include/SST_nvram_record.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_nvram_record.h
+ *
+ * Project:
+ * --------
+ *
+ * Description:
+ * ------------
+ *
+ * Author:
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef SST_NVRAM_RECORD_H
+#define SST_NVRAM_RECORD_H
+
+void SST_WriteNVRAMRecord_SystemStatistics(void);
+
+#endif /* SST_NVRAM_RECORD_H */
+
diff --git a/mcu/service/sst/include/SST_secure.h b/mcu/service/sst/include/SST_secure.h
new file mode 100644
index 0000000..4d3ba1b
--- /dev/null
+++ b/mcu/service/sst/include/SST_secure.h
@@ -0,0 +1,505 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_secure.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is header file for SST_secure.c
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __SST_SECURE_H__
+#define __SST_SECURE_H__
+
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+
+#include "kal_general_types.h"
+#include "nvram_data_items.h"
+#include "l4_nvram_def.h"
+
+#include "sst_interface.h"
+#include "kal_public_defs.h"
+#include "reg_base.h"
+
+/*************************************************************************
+ * External global data declaration
+ *************************************************************************/
+
+/*************************************************************************
+ * External Function Declaration
+ *************************************************************************/
+
+/*************************************************************************
+ * Type definitions
+ *************************************************************************/
+
+/* max size of NVRAM secret key in bytes*/
+#define NVRAM_KEY_GEN_AES_LEN 32
+#define NVRAM_KEY_GEN_MAX_KEY_LEN 256
+
+/* Error types of get NVRAM key*/
+#define GET_NVRAM_KEY_ERROR_NONE 0
+#define GET_NVRAM_KEY_ERROR_KEY_BUFFER_INVALID -1 // input buffer pointer is NULL
+#define GET_NVRAM_KEY_ERROR_KEY_SEED_BUFFER_INVALID -2 // input seed buffer pointer is NULL
+#define GET_NVRAM_KEY_ERROR_KEY_LEN_EXCEED_MAX -3 // input len exceed NVRAM_KEY_MAX_LEN
+#define GET_NVRAM_KEY_ERROR_KEY_SEED_LEN_NOT_MATCH -4
+
+
+#define PROTECTED_LID_ERROR_NONE 0x0
+#define PROTECTED_LID_ERROR_SECURE_NOT_ALLOWED 0x1000
+#define PROTECTED_LID_ERROR_NORMAL_R_FORBID 0x1001
+#define PROTECTED_LID_ERROR_NORMAL_W_FORBID 0x1002
+
+/* NVRAM AES en/decrypt related */
+#define NVRAM_AES_KEY_LEN_128BIT 16
+#define NVRAM_AES_KEY_LEN_192BIT 24
+#define NVRAM_AES_KEY_LEN_256BIT 32
+
+#define NVRAM_AES_ERROR_NONE 0
+#define NVRAM_AES_ERROR_KEY_LEN_ERROR -1
+#define NVRAM_AES_ERROR_DATA_LEN_NOT_ALIGN -2
+#define NVRAM_AES_ERROR_DATA_LEN_ERROR -3
+#define NVRAM_AES_ERROR_BUF_PTR_ERROR -4
+
+//AP efuse offset definition
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(MT6893)
+#define OFFSET_EFUSE_C_CTRL0 0x4C4
+#define OFFSET_EFUSE_C_CTRL1 0x4C8
+#define OFFSET_EFUSE_C_DAT0 0x510
+#define OFFSET_EFUSE_C_DAT1 0x514
+#define OFFSET_EFUSE_C_DAT2 0x518
+#define OFFSET_EFUSE_C_DAT3 0x51C
+#define OFFSET_EFUSE_C_DAT4 0x520
+#define OFFSET_EFUSE_C_DAT5 0x524
+#elif defined(CHIP10992)
+#define OFFSET_EFUSE_C_CTRL0 0x4C4
+#define OFFSET_EFUSE_C_CTRL1 0x4C8
+#define OFFSET_EFUSE_C_DAT0 0x510
+#define OFFSET_EFUSE_C_DAT1 0x514
+#define OFFSET_EFUSE_C_DAT2 0x518
+#define OFFSET_EFUSE_C_DAT3 0x51C
+#define OFFSET_EFUSE_C_DAT4 0x520
+#define OFFSET_EFUSE_C_DAT5 0x524
+#define OFFSET_EFUSE_C_DAT6 0x528
+#define OFFSET_EFUSE_C_DAT7 0x52C
+#else
+#define OFFSET_EFUSE_C_CTRL0 0x0
+#define OFFSET_EFUSE_C_CTRL1 0x0
+#define OFFSET_EFUSE_C_DAT0 0x0
+#define OFFSET_EFUSE_C_DAT1 0x0
+#define OFFSET_EFUSE_C_DAT2 0x0
+#define OFFSET_EFUSE_C_DAT3 0x0
+#define OFFSET_EFUSE_C_DAT4 0x0
+#define OFFSET_EFUSE_C_DAT5 0x0
+#endif
+
+#define OFFSET_EFUSE_AP_SBC_EN 0x60
+#define OFFSET_BIT_AP_SBC_EN 0x2
+#define BASE_AP_EFUSE_ADDR EFUSE_base
+
+//AP efuse offset array
+extern kal_uint32 ap_efuse_offset_arr[];
+
+#if defined(__SV5_ENABLED__) || defined(__SV5X_ENABLED__)
+#if defined(__SMART_PHONE_MODEM__) && defined(__X_BOOTING__)
+#define SECURE_RO_SIZE_OVERHEAD 0 //SEC_RO has no GFH for external phone
+#else
+#define SECURE_RO_SIZE_OVERHEAD 404
+#endif /*defined(__SMART_PHONE_MODEM__) && defined(__X_BOOTING__)*/
+#else
+#define SECURE_RO_SIZE_OVERHEAD 0
+#endif
+
+
+// AP HRID location
+#if defined(MT6763) || defined(MT6739) || defined(MT6295M) || defined(MT3967) || defined(MT6297) || defined(MT6779) || defined(MT6885) || defined(MT6873) || defined(MERCURY) || defined(MT6853) || defined(MT6833) || defined(MT6893) || defined(CHIP10992)
+#define EFUSE_HRID0 ((volatile unsigned *)(g_SST_EFUSE_base+0x0140))
+#define EFUSE_HRID1 ((volatile unsigned *)(g_SST_EFUSE_base+0x0144))
+#define EFUSE_HRID2 ((volatile unsigned *)(g_SST_EFUSE_base+0x0148))
+#define EFUSE_HRID3 ((volatile unsigned *)(g_SST_EFUSE_base+0x014C))
+#define SIZE_HRID (16)
+#else
+
+#error "Not Supported Chips"
+
+#endif
+
+/* AP/MD gen common AES key, bit enum */
+typedef enum{
+ AES_128 = 0,
+ AES_256 = 1,
+}AES_MODE;
+
+#define HW_AES_ENCRYPT 1
+#define HW_AES_DECRYPT 0
+/*************************************************************************
+ * Export API of SSS and SST
+ *************************************************************************/
+extern kal_bool SST_Is_Secure_BB(void);
+
+
+
+extern void SST_Secure_Algo (kal_uint8 Direction, kal_uint32 ContentAddr,
+ kal_uint32 ContentLen, kal_uint8 *CustomSeed,
+ kal_uint8 *ResText);
+
+extern void SST_Secure_Algo_With_Level (kal_uint8 Direction, kal_uint32 ContentAddr,
+ kal_uint32 ContentLen, kal_uint8 *CustomSeed, kal_uint32 Level,
+ kal_uint8 *ResText);
+
+extern kal_bool SST_Get_NVRAM_Key(kal_uint32 *p_key, kal_uint32 *p_addr, kal_uint32 *p_len);
+
+extern void SSS_Init_Share_Crypto_Drv(void * cb_ts_record, void * cb_ts_info, kal_uint32 init_tbl);
+
+extern void SSS_Init_Crypto_Drv(void * cb_ts_record, void * cb_ts_info);
+
+/*****************************************************************************
+ * FUNCTION
+ * SST_NVRAM_Data_Access_Check
+ * DESCRIPTION
+ * This function is to check the access to sensive or secure NVRAM data item.
+ * It is for internal used for NVRAM and security.
+ * PARAMETERS
+ * LID: [IN] NVRAM LID
+ * rw: [IN] read or write access : 0 => read, 1 => write
+ * is_secure_data_access: [IN] Secure or normal access : 0 => normal, 1 => secure
+ * RETURNS
+ * unsigned 32 bits
+ * RETURN VALUES
+ * 0 : check pass
+ * otherwise : check failed, please must not allowed to read nvram if checking failed
+ *****************************************************************************/
+extern kal_uint32 SST_NVRAM_Data_Access_Check(nvram_lid_enum LID, kal_int32 rw, kal_bool is_secure_data_access, void * reserved_ptr);
+
+extern kal_int32 SST_Get_HRID(kal_uint32 * pRId, kal_uint32 check_buf_size);
+
+extern kal_int32 SST_Get_NVRAM_SW_Key(void * pNVKey, kal_uint32 nNVKeySize, void * pKeySeed, kal_uint32 nKeySeedSize);
+
+// SST "S"pecific "S"ecure "F"eature Initialiation
+extern void SST_SSF_Init(void);
+
+// SST "S"pecific "S"ecure "F"eature De-init
+extern void SST_SSF_Deinit(void);
+
+kal_int32 nvram_AES_cipher_encrypt(unsigned char const *_key, unsigned int key_len, unsigned char *src_buf, unsigned char *dst_buf, unsigned int data_len);
+
+kal_int32 nvram_AES_cipher_decrypt(unsigned char const *_key, unsigned int key_len, unsigned char *src_buf, unsigned char *dst_buf, unsigned int data_len);
+
+
+#endif //__SST_SECURE_H__
diff --git a/mcu/service/sst/include/SST_secure_exp.h b/mcu/service/sst/include/SST_secure_exp.h
new file mode 100644
index 0000000..9f2de54
--- /dev/null
+++ b/mcu/service/sst/include/SST_secure_exp.h
@@ -0,0 +1,147 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_secure_exp.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is header file for SST_secure_exp.c
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __SST_SECURE_EXP_H__
+#define __SST_SECURE_EXP_H__
+
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+
+#include "kal_general_types.h"
+#include "sst_interface.h"
+
+/*************************************************************************
+ * External global data declaration
+ *************************************************************************/
+
+/*************************************************************************
+ * External Function Declaration
+ *************************************************************************/
+
+/*************************************************************************
+ * Type definitions
+ *************************************************************************/
+
+/*************************************************************************
+ * Export API of SSS and SST
+ *************************************************************************/
+
+/*****************************************************************************
+ * FUNCTION
+ * SST_Exp_Is_Target_Rooted
+ *
+ * DESCRIPTION
+ * The function check if the device is rooted.
+ *
+ * PARAMETERS
+ * [INPUT] N/A
+ * [OUTPUT] N/A
+ *
+ * RETURNS
+ * KAL_TRUE : Device is rooted
+ * KAL_FALSE : Device is not rooted
+ *
+ * NOTES
+ * N/A
+ *
+ *****************************************************************************/
+extern kal_bool SST_Exp_Is_Target_Rooted(void);
+
+/*****************************************************************************
+ * FUNCTION
+ * SST_Get_Secure_Channel_Key
+ *
+ * DESCRIPTION
+ * To get an AP/MD shared key.
+ *
+ * PARAMETERS
+ * [INPUT/OUTPUT] key
+ * [INPUT] len: counted in byte. Must be 16 bytes now
+ *
+ * RETURNS
+ * N/A
+ *
+ * NOTES
+ * N/A
+ *
+ *****************************************************************************/
+extern void SST_Get_Secure_Channel_Key(kal_uint8 *key, kal_uint32 len);
+
+#endif //__SST_SECURE_EXP_H__
+
diff --git a/mcu/service/sst/include/SST_sla.h b/mcu/service/sst/include/SST_sla.h
new file mode 100644
index 0000000..fa3decb
--- /dev/null
+++ b/mcu/service/sst/include/SST_sla.h
@@ -0,0 +1,362 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_sla.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the necessary API needed by software LA.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _SST_SLA_
+#define _SST_SLA_
+
+#include "us_timer.h"
+#include "SST_Concurrent_utility.h"
+#include "kal_general_types.h"
+#include "swla_public.h"
+#include "system_profiler_public.h"
+
+//#define __LOW_RAM_SWLA__ //wrap with compile option to save overhead in official load
+
+#define MAX_ADDON_NAME_LENGTH (12)
+#define SA_CCCI_SM_NUM (30)
+#define SA_CCCI_SM_UNIT_SIZE (12) /* 3 words for ContextID, FRC, CoreID_TCID */
+
+/* Type Definition */
+typedef struct SA_LoggingNode_T
+{
+ /* Manadatory information structure member */
+ kal_uint32 jobID;
+ kal_uint32 USCNT;
+ kal_uint32 CoreIDTCID;
+} SA_LoggingNode;
+
+/* Type Definition */
+typedef struct SA_LoggingThread_T
+{
+ kal_uint32 ThreadID;
+ kal_uint32 time;
+ kal_uint32 CoreIDTCID;
+} SA_LoggingThread;
+
+typedef struct SA_AddonInfo_T
+{
+ SYSPROFILER_ADDON_TYPE addonType;
+ kal_uint32 log_sz;
+ kal_char ext_name[MAX_ADDON_NAME_LENGTH];
+ void (*SLA_AddonInfoInitFunc)(void);
+ kal_bool SA_SwapOutLogging;
+ void * SLA_AddonInfoLoggingFunc;
+} SA_AddonInfo;
+
+typedef struct SA_PMCAddonCounter_T
+{
+ kal_uint32 PMC0Counter;
+ kal_uint32 PMC1Counter;
+} SA_PMCAddonCounter;
+
+typedef struct _SA_ELM_LOG_T
+{
+ kal_uint32 start_frc;
+ kal_uint32 duration;
+ kal_uint32 r_trans;
+ kal_uint32 w_trans;
+ kal_uint32 r_latency;
+ kal_uint32 w_latency;
+ kal_uint32 r_avg_latency;
+ kal_uint32 w_avg_latency;
+} SA_ELM_LOG_T;
+
+typedef enum
+{
+ SLA_FILTER_IRQ_END = (1u << 0),
+ SLA_FILTER_NO_CTXSWITCH = (1u << 1),
+ SLA_FILTER_GIC_END = (1u << 2),
+ SLA_FILTER_NEST_BEGIN = (1u << 3),
+ SLA_FILTER_NEST_END = (1u << 4),
+ SLA_FITLER_SINGLE_LABEL = (1u << 5),
+ SLA_FILTER_BEGIN_POINT = (1u << 6),
+ SLA_FILTER_END_POINT = (1u << 7),
+ SLA_FILTER_VPE1_CHILD_BEGIN = (1u << 8),
+ SLA_FILTER_VPE1_CHILD_END = (1u << 9),
+ SLA_FILTER_CPU_FREQUENCY = (1u << 10),
+ SLA_FILTER_ALL = 0xFF
+} SA_FILTER_T;
+
+
+typedef enum
+{
+ SLA_STATE_STOP,
+ SLA_STATE_PAUSE,
+ SLA_STATE_RUNNING
+} SA_STATE;
+
+
+
+extern SA_STATE SA_LoggingState[];
+
+
+
+#define SLA_Current_IsRunning() SLA_IsRunning(kal_get_current_core_id())
+
+INLINE INLINE_ALWAYS static kal_bool SLA_IsRunning(kal_uint8 coreID)
+{
+ return (SA_LoggingState[coreID] == SLA_STATE_RUNNING);
+}
+
+INLINE INLINE_ALWAYS static kal_bool SLA_IsStop(kal_uint8 coreID)
+{
+ return (SA_LoggingState[coreID] == SLA_STATE_STOP);
+}
+
+
+
+/* Prototypes */
+void SLA_RAMLogging(kal_uint32 jobID, kal_uint8 coreID, kal_uint8 TCID, kal_bool EMMlogging) DECLARE_MIPS16;
+kal_bool SLA_Register(SYSPROFILER_ADDON_TYPE addonType, kal_uint32 addonSize, kal_char addonName[], void (*SLA_AddonInfoInitFunc)(void), void *SLA_AddonInfoLoggingFunc, kal_bool SA_SwapOutLogging);
+
+void SLA_RetreiveNode (SA_LoggingNode *NodePtr, kal_uint32 NodeAmount, kal_bool DummyFilterOn);
+kal_uint32 SLA_RetreiveNodeByVPETC(SA_LoggingNode *NodePtr, kal_uint32 NodeAmount, SA_FILTER_T DummyFilter, kal_uint32 VPEID, kal_uint32 TCID);
+SYSPROFILER_ERROR_CODE SLA_Enable_for_Core(kal_uint32* bufferStartAddress, kal_uint32 bufferSize, kal_uint8 coreID);
+SYSPROFILER_ERROR_CODE SLA_Disable_for_Core(kal_uint8 coreID);
+kal_uint32 SLA_HookLogging(kal_uint8 VPEID);
+void SLA_LoggingLISR(kal_uint32 ID, kal_uint8 VPEID) DECLARE_MIPS16;
+SYSPROFILER_ERROR_CODE SLA_RetreiveHeader(kal_uint8 **MADesc, kal_uint32 *szMADesc, kal_uint8 coreID) ;
+SYSPROFILER_ERROR_CODE SLA_RetreiveLoggingBuffer(kal_uint8 **startAddr, kal_uint32 *size, kal_uint8 **currPtr, kal_uint8 coreID) ;
+
+SYSPROFILER_ERROR_CODE SLA_Register_for_Core(SYSPROFILER_ADDON_TYPE addonType, kal_uint32 addonSize, kal_char addonName[], void (*SLA_AddonInfoInitFunc)(void), void *SLA_AddonInfoLoggingFunc, kal_bool SA_SwapOutLogging, kal_uint8 coreID) ;
+
+#if defined(__SWLA_SNAPSHOT_FEATURE__)
+SYSPROFILER_ERROR_CODE SLA_Buffer_Snapshot(SysProfiler_Snapshot_Core* info, kal_uint32* SLA_buff_addr, kal_uint32 SLA_buff_size, kal_uint32* dst_buffer_addr, kal_uint32 dst_buffer_size );
+#endif
+#if defined(__SYSTEM_PROFILER_ON__)
+void SLA_RetrieveELMInfo(void);
+#endif
+
+#endif /* _SST_SLA_ */
diff --git a/mcu/service/sst/include/SST_trc.h b/mcu/service/sst/include/SST_trc.h
new file mode 100644
index 0000000..87fe64b
--- /dev/null
+++ b/mcu/service/sst/include/SST_trc.h
@@ -0,0 +1,180 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * SST_trc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _SST_TRC_H
+#define _SST_TRC_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+#if !defined(GEN_FOR_PC) && !defined(__MAUI_BASIC__)
+#include"SST_trc_mod_sst_common_utmd.h"
+#endif
+#endif /* _SST_TRC_H */
diff --git a/mcu/service/sst/include/SST_trc_mod_sst_common_utmd.json b/mcu/service/sst/include/SST_trc_mod_sst_common_utmd.json
new file mode 100644
index 0000000..937eb4f
--- /dev/null
+++ b/mcu/service/sst/include/SST_trc_mod_sst_common_utmd.json
@@ -0,0 +1,7997 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_SST_COMMON",
+ "startGen": "Legacy",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "SST_NEWLINE": {
+ "apiType": "index",
+ "format": "",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_NO": {
+ "format": "[%d]:",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_4_HEX_VALUES": {
+ "apiType": "index",
+ "format": "0x%X << 0x%X << 0x%X << 0x%X <<",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_3_HEX_VALUES": {
+ "apiType": "index",
+ "format": "0x%X << 0x%X << 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_2_HEX_VALUES": {
+ "apiType": "index",
+ "format": "0x%X << 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_1_HEX_VALUES": {
+ "apiType": "index",
+ "format": "0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_NAME": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TITLE1": {
+ "apiType": "index",
+ "format": "System Stability Tracker (SST) V0.00 ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TITLE2": {
+ "apiType": "index",
+ "format": "=====================================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ENDING1": {
+ "apiType": "index",
+ "format": "End of SST!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ENDING2": {
+ "apiType": "index",
+ "format": "============!!!!!!!!!!!!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DESCRIPTION": {
+ "apiType": "index",
+ "format": "<<Descriptions>>",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BOOTMODE_FACTORY_BOOT": {
+ "apiType": "index",
+ "format": "Oh dear! system exception under META/FACTORY mode,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BOOTMODE_NORMAL": {
+ "apiType": "index",
+ "format": "Oh dear! system exception under NORMAL mode,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BOOTMODE_USBMS_BOOT": {
+ "apiType": "index",
+ "format": "Oh dear! system exception under USB BOOT mode,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RUNNING_TASK": {
+ "apiType": "index",
+ "format": "while processing TASK %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RUNNING_TASK_AT_VPE": {
+ "apiType": "index",
+ "format": "Task %s currently running at vpe %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RUNNING_HISR": {
+ "apiType": "index",
+ "format": "while processing HISR %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RUNNING_LISR": {
+ "apiType": "index",
+ "format": "while processing LISR IRQ%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RUNNING_INITIAL": {
+ "apiType": "index",
+ "format": "while in initial stage.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RUNNING_UNKNOWN": {
+ "apiType": "index",
+ "format": "at the mean time, system is processing neither task, HISR nor LISR, unknown state!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXCEPTION_ANALYSIS": {
+ "apiType": "index",
+ "format": "<<Detailed Information and Analysis>>",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXCEPTION_GUIDELINE": {
+ "apiType": "index",
+ "format": "<<Guideline>>",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_MEMORY_CORRUPTION": {
+ "apiType": "index",
+ "format": "Memory corruption!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_LOOKS_GOOD": {
+ "apiType": "index",
+ "format": "Everything looks good!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_CPU_EXCEPTIONS": {
+ "apiType": "index",
+ "format": "This is the CPU triggered exception, type %Mexception_type!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_UPDATE_OWNER": {
+ "apiType": "index",
+ "format": "SST_UpdateOwner %c%c%c%c%c%c%c%c, caller=0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_USEFUL_INFO": {
+ "apiType": "index",
+ "format": "<<Useful Information>>",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_VICTIM_TITLE1": {
+ "format": "Please note that other vpe(s) had simultaneous problems as well so please check following victims",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_VICTIM_TITLE2": {
+ "format": "to see if they affected to crashed vpe:",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_VICTIM_VPE_NUMBER": {
+ "format": "vpe%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE1_UNDEFINED": {
+ "apiType": "index",
+ "format": "Error code 0x%X and 0x%X are not defined in SST engine, Quit the SST engine. Bye-bye!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_CONSTRUCTION": {
+ "apiType": "index",
+ "format": "Error code 0x%X and 0x%X are under construction now! Quit the SST engine. Bye-bye!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_UNDEFINED_ERROR_CODE": {
+ "apiType": "index",
+ "format": "Undefined fatal error code of class %c%c%c%c%c, error code 1=0x%X, error code 2=0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DUMP_STACK": {
+ "apiType": "index",
+ "format": "Active call path from given stack pointer (0x%X) as above.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DUMP_PROBLEM_STACK": {
+ "apiType": "index",
+ "format": "Call path of problematic task %c%c%c%c%c%c%c%c as below.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DUMP_STACK_FAILED": {
+ "apiType": "index",
+ "format": "No reasonable call path retreivable from given stack pointer!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_IRREGULAR_STACK_POINTER": {
+ "apiType": "index",
+ "format": "The stack pointer was out of bounded range!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_IRREGULAR_STACK_POINTER_PRINT": {
+ "apiType": "index",
+ "format": "SST sp(0x%X) sp_start(0x%X) sp_end(0x%X)!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SUSPEND_DISALLOWED_P1": {
+ "apiType": "index",
+ "format": "Not allowed to suspend because of no active task",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_REFER_TO_ERROR_CODE": {
+ "apiType": "index",
+ "format": "Error code returned by RTOS %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DUMP_RECEIVER_STACK": {
+ "apiType": "index",
+ "format": "Call path of receiver task as below.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DUMP_SENDER_STACK": {
+ "apiType": "index",
+ "format": "Call path of sender task %c%c%c%c%c%c%c%c as below.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_JTAG_WB": {
+ "apiType": "index",
+ "format": "Please reproduce on JTAG, and set the write breakpoint at address 0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_JTAG_WBS": {
+ "apiType": "index",
+ "format": "Please reproduce on JTAG, and set the write breakpoint at any of the above error addresses!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of %c%c%c%c%c%c%c%c to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_MSGID": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of %Mmsg_type to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_MOD": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of %c%c%c%c%c%c%c%c module %Mmodule_type to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_FILE": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of file %s to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_LR": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of caller address 0x%08X to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_PC": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of code at 0x%08X to resolve the problem! (you can use CaDeFa to find owner)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_TASK": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of task %c%c%c%c%c%c%c%c to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_HISR": {
+ "format": "Please contact people in-charge of hisr %s to resolve the problem!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE3_OWNER_IRQ": {
+ "apiType": "index",
+ "format": "Please contact people in-charge of IRQ%d to resolve the problem!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_MAKE_SURE": {
+ "format": "Please contact owner of %c%c%c%c%c%c%c%c to make sure the procedure is correct!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE3_CALL_SST": {
+ "apiType": "index",
+ "format": "Please dump memory and let system service member to give you a hand!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_DUMP_MEMORY": {
+ "apiType": "index",
+ "format": "Serious error, please dump memory and let system service member to give you a hand!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_DUMP_MEMORY_PR": {
+ "apiType": "index",
+ "format": "Serious error, please dump memory!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_REMIND_DUMP_MEMORY": {
+ "apiType": "index",
+ "format": "Remember to dump memory!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_FOLLOW_RULE_CUSTOMIZATION": {
+ "apiType": "index",
+ "format": "Please stricly follow the rule for customization!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_SENDER_IS_OFFENDER": {
+ "apiType": "index",
+ "format": "Sender is offender, please saw above call path!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO": {
+ "apiType": "index",
+ "format": "Content of task_info_g[%03d] as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G1": {
+ "apiType": "index",
+ "format": " task_name_ptr = %c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G2": {
+ "apiType": "index",
+ "format": " task_qname_ptr = %c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G3": {
+ "apiType": "index",
+ "format": " task_priority = %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G4": {
+ "apiType": "index",
+ "format": " task_stack_size = %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G5": {
+ "apiType": "index",
+ "format": " task_entry_func = 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G6": {
+ "apiType": "index",
+ "format": " task_ext_qsize = %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G7": {
+ "apiType": "index",
+ "format": " task_int_qsize = %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G8_1": {
+ "apiType": "index",
+ "format": " task_internal_ram_stack = KAL_TRUE",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G8_2": {
+ "apiType": "index",
+ "format": " task_internal_ram_stack = KAL_FALSE",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G9": {
+ "apiType": "index",
+ "format": " task_id = 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G10": {
+ "apiType": "index",
+ "format": " task_ext_qid = 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G11": {
+ "apiType": "index",
+ "format": " task_int_qid_ptr = 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_STACK_ERROR": {
+ "apiType": "index",
+ "format": " ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Error (Address=0x%X)! Should not be 0!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_ENTRY_ERROR": {
+ "apiType": "index",
+ "format": " ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Error (Address=0x%X)! Should not be NULL!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ILM_STRUCT": {
+ "format": "Content of ILM structure relative to %Mmodule_type as below",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_ILM_STRUCT_SOURCE": {
+ "apiType": "index",
+ "format": " src_mod_id: %Mmodule_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ILM_STRUCT_DESTINATION": {
+ "apiType": "index",
+ "format": " dest_mod_id: %Mmodule_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ILM_STRUCT_SAP": {
+ "apiType": "index",
+ "format": " sap_id: %Msap_type",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "SST_ILM_STRUCT_MESSID": {
+ "apiType": "index",
+ "format": " msg_id: %Mmsg_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ILM_STRUCT_LOCAL": {
+ "apiType": "index",
+ "format": " local_para_ptr: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ILM_STRUCT_PEER": {
+ "apiType": "index",
+ "format": " peer_buff_ptr: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_INIT": {
+ "format": "",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE1_201_01": {
+ "apiType": "index",
+ "format": "In kal_create_task( ), dynamic memory allocation failed for task stack.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_201_02": {
+ "apiType": "index",
+ "format": "In kal_create_task( ), dynamic memory allocation failed for kal_task_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_201_04": {
+ "apiType": "index",
+ "format": "In kal_create_task( ), dynamic debug memory allocation failed for kal_task_stat_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_201_07": {
+ "apiType": "index",
+ "format": "In kal_create_task( ), dynamic internal memory allocation failed for task stack.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_203_01": {
+ "apiType": "index",
+ "format": "Zero stack size is provided in task creation.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_203_02": {
+ "apiType": "index",
+ "format": "NULL entry function is provided in task creation.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_203_22_": {
+ "apiType": "index",
+ "format": "In kal_create_task(), failure due to insufficient stack size (less than 240Bytes).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_203_25_": {
+ "apiType": "index",
+ "format": "In kal_create_task(), failure due to duplicated creation.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_207_TASKID_P1": {
+ "apiType": "index",
+ "format": "In kal_deque_msg (), stack overflow is detected at TCC_Suspend_Task(),",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_207_TASKID_P2": {
+ "apiType": "index",
+ "format": "where stack guard pattern 'STACKEND' had been corrupted, it becomes 0x%X 0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_209_TASKID_P1": {
+ "apiType": "index",
+ "format": "stack overflow is detected by MPU, please check ex_cp15_log",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20A_TASKID_P1": {
+ "apiType": "index",
+ "format": "stack overflow is detected by WATCHPOINT:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20A_TASKID_P2": {
+ "apiType": "index",
+ "format": "Stack overflow happened when PC was at 0x%08X and it tried to store to watch area 0x%08X-0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20A_TASKID_P3": {
+ "apiType": "index",
+ "format": "Stack overflow happened when EXL or ERL bit was set or during processor was in DEBUG mode",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20A_TASKID_P4": {
+ "apiType": "index",
+ "format": "This means EPC register does not point to offending address but to the address where EXL/ERL bit was cleared",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20A_TASKID_P5": {
+ "apiType": "index",
+ "format": "Stack overflow happened when a store to watch area 0x%08X-0x%08X some point before PC reached 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20B_TASKID_P0": {
+ "apiType": "index",
+ "format": "task/hisr operation error:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20B_TASKID_P1": {
+ "apiType": "index",
+ "format": "affinity should be resumed before set it again:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20B_TASKID_P2": {
+ "apiType": "index",
+ "format": "resume could not be called if its never set:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20B_TASKID_P3": {
+ "apiType": "index",
+ "format": "its not allow to set/resume affinity without configuration.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_20B_TASKID_P4": {
+ "apiType": "index",
+ "format": "affinity need to be resumed within %d minutes after setting.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_211_01": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), dynamic memory allocation failed for HISR's stack.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_211_02": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), dynamic memory allocation failed for kal_hisr_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_211_04": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), dynamic debug memory allocation failed for kal_hisr_stat_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_211_07": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), dynamic internal memory allocation failed for HISR's stack!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_213_01": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), zero stack size is provided!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_213_02": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), HISR entry function is NULL!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_213_03": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), illegal priority value is provided, only 0, 1 and 2 are valid!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_213_04": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), priority 0 is assigned to an HISR other than L1_HISR!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_213_05": {
+ "apiType": "index",
+ "format": "In kal_create_hisr( ), number of HISR exceeding maximal boundary %d!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_216_9__P1": {
+ "apiType": "index",
+ "format": "In kal_activate_hisr(), HISR control block corrupted or incorrect",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_21B": {
+ "apiType": "index",
+ "format": "In kal_init_hisr(), the parameter HISR index is not found in hisr_info[]!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_203_01": {
+ "apiType": "index",
+ "format": "Notice that, stack size is referenced from array task_info_g, its content as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_203_02": {
+ "apiType": "index",
+ "format": "Notice that, task's entry function is referenced from array task_info_g, its content as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_207_TASKID_SUB1_P1": {
+ "apiType": "index",
+ "format": "No reasonable call path within 128words started from stack guard pattern",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_207_TASKID_SUB1_P2": {
+ "apiType": "index",
+ "format": "pattern, perhaps unintentional corruption from somewhere.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_207_TASKID_SUB2_P1": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c sufferes from stack overflow, and its stack size is %dBytes.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_207_IRQID_SUB2_P1": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c sufferes from stack overflow, system stack size is %dBytes.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_207_TASKID_SUB2_P2": {
+ "apiType": "index",
+ "format": "Possible call path traced back from stack guard pattern as above (max %d words).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G_CORRUPTED_P1": {
+ "format": "Serious error, memory corruption at address 0x%X, and please refer",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE2_TASK_INFO_G_CORRUPTED_P2": {
+ "format": "to task_info_g[ ] below for more detailed.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE2_216_9_1_P1": {
+ "apiType": "index",
+ "format": "My dear, pointer used in activating HISR is corrupted, where tc_id is no longer 0x48495352!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_216_9_1_P2": {
+ "apiType": "index",
+ "format": "Content of HISR as below;",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_216_9_2": {
+ "apiType": "index",
+ "format": "HISR ID 0x48495352 is found, may fail at somewhere!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_21B": {
+ "apiType": "index",
+ "format": "kal_init_hisr() with invaild HISR index is called by caller address 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_203_22__P1": {
+ "apiType": "index",
+ "format": "Please contact people in charge of task %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_203_22__P2": {
+ "apiType": "index",
+ "format": "to provide stack size larger than 240B.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_203_25__P1": {
+ "apiType": "index",
+ "format": "Please contact people in charge of task %c%c%c%c%c for bug fixing. And, control",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_203_25__P2": {
+ "apiType": "index",
+ "format": "block of relative task control block as below,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_207_TASKID": {
+ "apiType": "index",
+ "format": "In case of reproducing, please set the write breakpoint at address 0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_21B_P1": {
+ "apiType": "index",
+ "format": "Please contact the owner in-charge of caller address 0x%08X to check",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_21B_P2": {
+ "apiType": "index",
+ "format": "whether this HISR should be initialized in this compile option!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_CREATED": {
+ "apiType": "index",
+ "format": "created : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_ID": {
+ "apiType": "index",
+ "format": "tc_id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_NAME": {
+ "apiType": "index",
+ "format": "name : %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_PRIORITY": {
+ "apiType": "index",
+ "format": "priority : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_SCHEDULED": {
+ "apiType": "index",
+ "format": "scheduled : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_TIMESLICE": {
+ "apiType": "index",
+ "format": "cur_time_slice : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_STACK_START": {
+ "apiType": "index",
+ "format": "stack_start : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_STACK_END": {
+ "apiType": "index",
+ "format": "stack_end : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_SP": {
+ "apiType": "index",
+ "format": "stack_pointer : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_STACK_SIZE": {
+ "apiType": "index",
+ "format": "stack_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_STACK_MIN": {
+ "apiType": "index",
+ "format": "stack_minimum : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_CURR_PROTECT": {
+ "apiType": "index",
+ "format": "current_protect : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_ACTIVE_NEXT": {
+ "apiType": "index",
+ "format": "active_next : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_ACTIVATION": {
+ "apiType": "index",
+ "format": "activation_count : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_ENTRY": {
+ "apiType": "index",
+ "format": "entry : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TC_HCB_AFFINITY": {
+ "apiType": "index",
+ "format": "affinity mask : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_READY": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in ready state, it is ready to execute",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_READY_OSC": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in ready state, it is ready to execute or running!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_PURE_SUSPEND": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in pure suspend state!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_SLEEP_SUSPEND": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in sleep suspend state!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_QUEUE_SUSPEND": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is waiting for queue message!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_SEMAPHORE_SUSPEND": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is waiting for semaphore or mutex!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_ENH_MUTEX_SUSPEND": {
+ "format": "%c%c%c%c%c%c%c%c is waiting for enh_mutex!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_TASK_EVENT_SUSPEND": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is waiting for event!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_PARTITION_SUSPEND": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in waiting for available partitoned pool!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_SCHEDULED": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is running at vpe %d at the moment",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_FINISH": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in finished state!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_TERMINATED": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in terminated state!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_UNKOWN": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is in unknown state (%d)!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_AFFINITY_SMP": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c is affined to SMP, currently runnign at vpe %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TASK_AFFINITY": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c affinity is %d (vpemask), currently runnign at vpe %d (vpemask %d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ITC_COMMON_ILM1": {
+ "apiType": "index",
+ "format": "Content of ILM* being processed as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ITC_COMMON_ILM2": {
+ "apiType": "index",
+ "format": "Content of ILM retrieved from module_ilm_g[%Mmodule_type] as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_301_01": {
+ "apiType": "index",
+ "format": "In kal_create_msg_q( ), dynamic memory allocation failed for kal_queue_type..",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_301_03": {
+ "apiType": "index",
+ "format": "In kal_create_msg_q( ), dynamic memory allocation failed for queue buffer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_301_04": {
+ "apiType": "index",
+ "format": "In kal_create_msg_q( ), dynamic debug memory allocation failed for kal_queue_stat_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_303_9999_P1": {
+ "apiType": "index",
+ "format": "NULL internal queue pointer is provided in msg_send_int_queue",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_303_6666_P1": {
+ "apiType": "index",
+ "format": "NULL external queue pointer is provided in stack_send_2_ext_q",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_305_01": {
+ "apiType": "index",
+ "format": "While calling kal_enque_msg( ), NULL external queue is provided.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_305_02": {
+ "apiType": "index",
+ "format": "While calling kal_enque_msg( ), source buffer pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_305_19__P1": {
+ "format": "In kal_enque_msg(), control block of destination queue was damaged, ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE1_305_19__P2": {
+ "apiType": "index",
+ "format": "which is no longer 0x51554555",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_305_24_": {
+ "apiType": "index",
+ "format": "In kal_enque_msg(), suspension style is expected, but there is no running task currently.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_305_8888": {
+ "apiType": "index",
+ "format": "External queue full is encountered while message delivery.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_305_FF": {
+ "apiType": "index",
+ "format": "In kal_enque_msg(), operation failed!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_306_7777": {
+ "apiType": "index",
+ "format": "Internal queue full is encountered while message delivery.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_306_9999": {
+ "apiType": "index",
+ "format": "ILM is sent to internal queue when the current task is not the receiver.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_306_9999_2": {
+ "apiType": "index",
+ "format": "Module %d does not belong to current task %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_306_ilmptr_1": {
+ "apiType": "index",
+ "format": "Cannot send to internal queue with msg_send_to_head()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_306_ilmptr_2": {
+ "apiType": "index",
+ "format": "Cannot send to external queue with msg_send_to_int_head()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_307_0": {
+ "apiType": "index",
+ "format": "when send ilm message, external queue pointer of the destination task should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_307_1": {
+ "apiType": "index",
+ "format": "when send ilm message, destination buffer pointer should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_307_19_": {
+ "apiType": "index",
+ "format": "In kal_enque_msg(), control block of destination queue was damaged,which is no longer 0x51554555.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_307_24_": {
+ "apiType": "index",
+ "format": "In kal_enque_msg(), suspension style is expected, but there is no running task currently.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_1": {
+ "apiType": "index",
+ "format": "In msg_receive_extq() or msg_receive_extq_for_stack(), the current task index is INDX_NIL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_2": {
+ "apiType": "index",
+ "format": "In msg_receive_extq() or msg_receive_extq_for_stack(), external queue ID fo current task should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_3": {
+ "apiType": "index",
+ "format": "In msg_receive_intq(), the current task index is INDX_NIL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_4": {
+ "apiType": "index",
+ "format": "In msg_receive_intq(), internal queue ID fo current task should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_6": {
+ "apiType": "index",
+ "format": "In msg_get_task_extq_messages() or msg_get_task_extq_capacity(), external queue ID fo current task should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_7": {
+ "apiType": "index",
+ "format": "In kal_deque_msg() or kal_deque_msg_for_stack(), external queue ID fo current task should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_30A_8": {
+ "apiType": "index",
+ "format": "In kal_deque_msg() or kal_deque_msg_for_stack(), destination buffer pointer should not be NULL",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_401_1": {
+ "apiType": "index",
+ "format": "In kal_create_mutex ( ), system memory allocation failed for data type kal_mutex_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_401_4": {
+ "apiType": "index",
+ "format": "In kal_create_mutex ( ), dynamic debug memory allocation failed for kal_internal_mutex_statistics.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_403_FF": {
+ "apiType": "index",
+ "format": "In kal_create_mutex ( ), NU_Create_Semaphore does not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_404_0": {
+ "apiType": "index",
+ "format": "In kal_take_mutex ( ), NULL pointer is provided for obtaining mutex",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_404_1": {
+ "apiType": "index",
+ "format": "In kal_take_mutex ( ), current task (mutex owner) takes mutex twice",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_404_21_": {
+ "apiType": "index",
+ "format": "In kal_take_mutex ( ),control block of semaphore may be corrupted or it is an illegal pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_404_24_": {
+ "apiType": "index",
+ "format": "In kal_take_mutex(), suspension style is expected, but there is no running task currently.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_405_0": {
+ "apiType": "index",
+ "format": "In kal_give_mutex ( ), NULL pointer is provided for giving mutex.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_405_MUID": {
+ "apiType": "index",
+ "format": "A MUTEX must be obtained and given by the same task.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_405_FF": {
+ "apiType": "index",
+ "format": "In kal_give_mutex ( ),control block of mutex may be corrupted or it is an illegal pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_411_1": {
+ "apiType": "index",
+ "format": "In kal_create_sem ( ), dynamic memory allocation failed for data type kal_sem_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_411_4": {
+ "apiType": "index",
+ "format": "In kal_create_sem ( ), dynamic debug memory allocation failed for kal_internal_sem_statistics.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_413_FF": {
+ "apiType": "index",
+ "format": "In kal_create_sem ( ), NU_Create_Semaphore not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_414_0": {
+ "apiType": "index",
+ "format": "In kal_take_sem ( ),NULL pointer is provid.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_414_21_": {
+ "apiType": "index",
+ "format": "In kal_take_sem ( ),control block of semaphore may be corrupted or it is an illegal pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_414_24_": {
+ "apiType": "index",
+ "format": "In kal_take_sem(), suspension style is expected, but there is no running task currently.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_415_0": {
+ "apiType": "index",
+ "format": "In kal_give_sem ( ), NULL pointer is provided for giving mutex.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_415_FF": {
+ "apiType": "index",
+ "format": "In kal_give_sem ( ),control block of semaphore may be corrupted or it is an illegal pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_421_1": {
+ "apiType": "index",
+ "format": "In kal_create_event_group ( ), dynamic memory allocation failed for data type kal_eventgrp_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_423_FF": {
+ "apiType": "index",
+ "format": "In kal_create_event_group ( ), NU_Create_Event_Group not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_424_21_": {
+ "apiType": "index",
+ "format": "In kal_set_eg_events ( ),control block of event group may be corrupted or it is an illegal pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_424_13_": {
+ "apiType": "index",
+ "format": "In kal_set_eg_events (), event group operation is undefined, it is neither NU_AND nor NU_OR.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_425_13_": {
+ "apiType": "index",
+ "format": "In kal_retrieve_eg_events ( ), operation is not supported, they are nether NU_AND, NU_AND_CONSUME, NU_OR nor NU_OR_CONSUME.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_425_24_": {
+ "apiType": "index",
+ "format": "In kal_retrieve_eg_events (), suspension style is expected, but there is no running task currently.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_431": {
+ "apiType": "index",
+ "format": "In allocate_ilm(), module ILM %Mmodule_type has not yet been delivered or duplicated!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_432": {
+ "apiType": "index",
+ "format": "In %s(), %c%c%c%c%c%c%c%c is trying to hold an ILM which has been either not allocated or already freed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_433": {
+ "apiType": "index",
+ "format": "Double free detected when releasing %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_434": {
+ "apiType": "index",
+ "format": "Inline ILM API used for non-inline ILM. Sap ID: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_43A_1": {
+ "apiType": "index",
+ "format": "In construct_peer_buff(), (pdu_len + header_len + tail_len) should larger than 0.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_43A_2": {
+ "apiType": "index",
+ "format": "In construct_local_para(), local_para_size should larger than sizeof(local_para_struct).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_43B_1": {
+ "apiType": "index",
+ "format": "When sehdning CC ILM, please make suse the ref_counf of peer_buff is 1 to avoid race condition.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_43B_2": {
+ "apiType": "index",
+ "format": "When sehdning CC ILM, please make suse the ref_counf of local_para is 1 to avoid race condition.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_441": {
+ "apiType": "index",
+ "format": "In stack_check_msgid_range(), message ID overflow is detected at %Mmsg_type!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_451_1": {
+ "apiType": "index",
+ "format": "In kal_create_enh_mutex ( ), system memory allocation failed for data type kal_int_enhmutex.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_454_1": {
+ "apiType": "index",
+ "format": "In kal_take_enh_mutex (), NULL pointer is provided for obtaining mutex.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_454_2": {
+ "apiType": "index",
+ "format": "In kal_take_enh_mutex (), control block of enhanced mutex may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_454_3": {
+ "apiType": "index",
+ "format": "In kal_take_enh_mutex (), caller context in HISR.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_454_4": {
+ "apiType": "index",
+ "format": "In kal_take_enh_mutex (), current task (enhanced mutex owner) takes enhanced mutex twice.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_454_24_": {
+ "apiType": "index",
+ "format": "In kal_take_enh_mutex (), suspension style is expected, but there is no running task currently.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_455_1": {
+ "apiType": "index",
+ "format": "In kal_give_enh_mutex (), NULL pointer is provided for giving mutex.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_455_2": {
+ "apiType": "index",
+ "format": "In kal_give_enh_mutex (), control block of enhanced mutex may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_455_MUID": {
+ "apiType": "index",
+ "format": "In kal_give_enh_mutex (), enhanced mutex must be obtained and given by the same task.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_455_FF": {
+ "apiType": "index",
+ "format": "In kal_give_enh_mutex (), unexpected error happened in OS, please check the error code 2.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_461_1": {
+ "apiType": "index",
+ "format": "In kal_create_spinlock(), system memory allocation failed for data type kal_spinlock_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_462_FF": {
+ "apiType": "index",
+ "format": "In kal_create_spinlock(), NU_Spinlock_Create not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_463_1": {
+ "apiType": "index",
+ "format": "In kal_take_spinlock(), NULL pointer is provided for obtaining spinlock.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_463_2": {
+ "apiType": "index",
+ "format": "In kal_take_spinlock(), NU_Spinlock_Try return error due to corruption in spinlock.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_464_1": {
+ "apiType": "index",
+ "format": "Current owner of spinlock(%s), tried to acquire same spinlock again",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_464_2": {
+ "apiType": "index",
+ "format": "First take was from 0x%08X. See call stack above for second take",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_465_1": {
+ "apiType": "index",
+ "format": "In kal_give_spinlock(), NULL pointer is provided for obtaining spinlock.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_465_2": {
+ "apiType": "index",
+ "format": "In kal_give_spinlock(), NU_Spinlock_Release return error due to corruption in spinlock.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_466_1": {
+ "apiType": "index",
+ "format": "Spinlock %s was being released by owner who did not own it.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_466_2": {
+ "apiType": "index",
+ "format": "Current context is 0x%08X:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_466_3": {
+ "apiType": "index",
+ "format": "Spinlock was taken from 0x%08X context:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_466_4": {
+ "apiType": "index",
+ "format": "Spinlock was not taken at the moment",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_467_1": {
+ "apiType": "index",
+ "format": "Code at 0x%08X tried to %s spinlock from HRT context which is not allowed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_469_1": {
+ "apiType": "index",
+ "format": "%s have tried to obtain Spinlock(0x%X) %s %d times in a row without succeeding",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_471_1": {
+ "apiType": "index",
+ "format": "In kal_create_internal_protect ( ), system memory allocation failed for data type kal_protect_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_472_FF": {
+ "apiType": "index",
+ "format": "In kal_create_internal_protect ( ), NU_Spinlock_Create not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_473_1": {
+ "apiType": "index",
+ "format": "In kal_take_internal_protect(), NULL pointer is provided for obtaining internal protect.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_473_2": {
+ "apiType": "index",
+ "format": "In kal_take_internal(), NU_Spinlock_Try return error due to corruption in internal protect.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_474_1": {
+ "apiType": "index",
+ "format": "Owner of internal protect named %s, tried to acquire same internal protect again",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_474_2": {
+ "apiType": "index",
+ "format": "First take was from 0x%08X and second take from 0x%08X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_475_1": {
+ "apiType": "index",
+ "format": "In kal_give_internal_protect(), NULL pointer is provided for obtaining internal protect.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_475_2": {
+ "apiType": "index",
+ "format": "In kal_give_internal_protect(), NU_Spinlock_Release return error due to corruption in internal protect.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_476_1": {
+ "apiType": "index",
+ "format": "Code at 0x%08X tried to release internal protect %s which was not owned by it.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_481_1": {
+ "apiType": "index",
+ "format": "Illegal wait_mode (%x) given to %s. Only KAL_NO_WAIT(0) and KAL_INFINITE_WAIT(1) are allowed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_482_1": {
+ "apiType": "index",
+ "format": "HWITC lock id %Mkal_itc_lock_id cannot be used with %s API.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_482_3": {
+ "apiType": "index",
+ "format": "HWITC lock id %d cannot be used with %s API.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_482_2": {
+ "apiType": "index",
+ "format": "HWITC lock id %Mkal_itc_lock_id was being released by owner who did not own it",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_483_1": {
+ "apiType": "index",
+ "format": "Current owner of HWITC lock id %Mkal_itc_lock_id, tried to acquire same HWITC lock again",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_486_1": {
+ "apiType": "index",
+ "format": "%s API was called interrupted enabled. Giant lock id was %Mkal_itc_lock_id",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_487_1": {
+ "apiType": "index",
+ "format": "Giant lock id %Mkal_itc_lock_id was being released from vpe%d even it was taken from vpe%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_API_ONLYTC2ORTC3": {
+ "apiType": "index",
+ "format": "%s was called from wrong tc%d. Its only allowed to be called from tc2 or tc3",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_API_ONLYTC1": {
+ "apiType": "index",
+ "format": "%s was called from wrong tc%d. Its only allowed to be called from tc1",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_493_1": {
+ "apiType": "index",
+ "format": "Illegal wq_id (%x) given to %s. Only KAL_Q1(1), KAL_Q1(2) and KAL_Q_MAX(3) are allowed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_493_2": {
+ "apiType": "index",
+ "format": "Illegal timeout (%x) given to kal_hrt_tc_checkpoint. Only KAL_NO_WAIT(0) and KAL_INFINITE_WAIT(1) are allowed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_494_2": {
+ "apiType": "index",
+ "format": "NULL func_ptr given to kal_hrt_tc_dispatch_work.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_496_1": {
+ "apiType": "index",
+ "format": "Workqueue %Mkal_workqueueid at core%d full.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_498_1": {
+ "apiType": "index",
+ "format": "kal_hrt_trigger_dummy_lisr was called from wrong TC: %d. Its only allowed to be called from TC1.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_49X_1": {
+ "apiType": "index",
+ "format": "This function was called from 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_499_1": {
+ "apiType": "index",
+ "format": "kal_hrt_trigger_dummy_lisr was called for wrong VPEs. Check vpe mask",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_49A_1": {
+ "apiType": "index",
+ "format": "kal_hrt_revoke_dummy_lisr was called from wrong TC: %d. Its only allowed to be called from TC1",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_49B_1": {
+ "apiType": "index",
+ "format": "kal_hrt_revoke_dummy_lisr was called for wrong VPEs. Check vpe mask",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_49C_1": {
+ "apiType": "index",
+ "format": "Dummy lisr lock id %Mkal_itc_lock_id was being released from vpe%d even it was taken from vpe%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_9999_P1": {
+ "apiType": "index",
+ "format": "My dear, %c%c%c%c%c%c%c%c is giving an illegal destination module ID for message delivery",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_9999_P2": {
+ "apiType": "index",
+ "format": "destination module ID %d is out of range (max:%d).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_9999_P3": {
+ "apiType": "index",
+ "format": "My dear, %c%c%c%c%c%c%c%c is sending message via module ID, who has no internal queue.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_9999_P4": {
+ "apiType": "index",
+ "format": "Please refer to information above for debugging!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_9999_P5": {
+ "apiType": "index",
+ "format": "My dear, %c%c%c%c%c%c%c%c is sending message via module ID, whose relative task is not existed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_9999_P6": {
+ "apiType": "index",
+ "format": "in current boot mode. Please refer to information above for debugging!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_QUEUE_ID": {
+ "apiType": "index",
+ "format": "Illegal or may be corrupted pointer used to enqueue message!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P1": {
+ "apiType": "index",
+ "format": "While sending message to %c%c%c%c%c%c%c%c, %c%c%c%c%c%c%c%c found that,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P2": {
+ "apiType": "index",
+ "format": "external queue of %c%c%c%c%c%c%c%c is full!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P3": {
+ "apiType": "index",
+ "format": "Following is its complete content:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P4": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c is in busy waiting, until fails to process message in external queue;",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P5": {
+ "apiType": "index",
+ "format": "Following is its complete content:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P6": {
+ "apiType": "index",
+ "format": "My dear, Task %c%c%c%c%c%c%c%c may be blocked by thread listed below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P7": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c Task may be blocked by this enhanced mutex",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P8": {
+ "apiType": "index",
+ "format": "The call stack of enhanced mutex owner: %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P9": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c Task may be blocked by this mutex",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P10": {
+ "apiType": "index",
+ "format": "The call stack of mutex owner: %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_8888_P11": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c Task may be blocked by this semaphore",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_QUEUE_LARGE_COUNT": {
+ "apiType": "index",
+ "format": "The Qneue size is larger than %d. We only parsing %d ILM in queue. Please reduce the queue size",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_QUEUE_MESS_COUNT": {
+ "apiType": "index",
+ "format": "There are totally %d entries with same content,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_303_7777_P1": {
+ "apiType": "index",
+ "format": "While %c%c%c%c%c%c%c%c is running, %Mmodule_type sends msg to %Mmodule_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_TIME_STAMP_0": {
+ "apiType": "index",
+ "format": "The exception frame No: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_TIME_STAMP_1": {
+ "apiType": "index",
+ "format": "The last 3 ILM taken frame No: %d, %d, %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_TIME_STAMP_2": {
+ "apiType": "index",
+ "format": "The last queue empty frame No %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_TIME_STAMP_3": {
+ "apiType": "index",
+ "format": "Receiver External Queue Size %d ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_TIME_STAMP_4": {
+ "apiType": "index",
+ "format": "The last frame No when Queue Contains %d, %d, %d ILMs %d, %d, %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_I": {
+ "apiType": "index",
+ "format": "fatal 0x305 case I: blocked by high priority thread, %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_II": {
+ "apiType": "index",
+ "format": "fatal 0x305 case II: receiver is suspended",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_III": {
+ "apiType": "index",
+ "format": "fatal 0x305 case III: sender sent too many ILMs in short time",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_III_Offender": {
+ "apiType": "index",
+ "format": "Offender %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_IV": {
+ "apiType": "index",
+ "format": "fatal 0x305 case IV: receiver traps in infinite loops",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_V": {
+ "apiType": "index",
+ "format": "fatal 0x305 case V: starvation of receiver ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_305_QUEUE_CASE_UNDEF": {
+ "apiType": "index",
+ "format": "fatal 0x305 case X: Complicated and can not be defined by Online SST",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_405_MUID": {
+ "apiType": "index",
+ "format": "Note that, mutex is now owned by %c%c%c%c%c%c%c%c, and could not be given by task %c%c%c%c%c%c%c%c.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_455_MUID": {
+ "apiType": "index",
+ "format": "Note that, enhanced mutex is now owned by %c%c%c%c%c%c%c%c, and could not be given by task %c%c%c%c%c%c%c%c.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB": {
+ "apiType": "index",
+ "format": "Content of queue control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_CREATED": {
+ "apiType": "index",
+ "format": " qu_created : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_ID": {
+ "apiType": "index",
+ "format": " qu_id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_NAME": {
+ "apiType": "index",
+ "format": " qu_name : %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_FIXED_SIZE": {
+ "apiType": "index",
+ "format": " qu_fixed_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_SUSP_F": {
+ "apiType": "index",
+ "format": " qu_fifo_suspend : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_SIZE": {
+ "apiType": "index",
+ "format": " qu_queue_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_MESS_COUNT": {
+ "apiType": "index",
+ "format": " qu_messages : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_MESS_SIZE": {
+ "apiType": "index",
+ "format": " qu_message_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_AVAIL": {
+ "apiType": "index",
+ "format": " qu_available : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_START_ADDR": {
+ "apiType": "index",
+ "format": " qu_start : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_END_ADDR": {
+ "apiType": "index",
+ "format": " qu_end : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_READ_PTR": {
+ "apiType": "index",
+ "format": " qu_read : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_WRITE_PTR": {
+ "apiType": "index",
+ "format": " qu_write : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_TASK_WAITING": {
+ "apiType": "index",
+ "format": " qu_tasks_waiting : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_URGENT_LIST": {
+ "apiType": "index",
+ "format": " qu_urgent_list : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_QU_QCB_SUSP_LIST": {
+ "apiType": "index",
+ "format": " qu_suspension_list : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB": {
+ "apiType": "index",
+ "format": "Content of semaphore control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_CREATED": {
+ "apiType": "index",
+ "format": " sm_created : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_ID": {
+ "apiType": "index",
+ "format": " sm_id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_NAME": {
+ "apiType": "index",
+ "format": " sm_name : %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_COUNT": {
+ "apiType": "index",
+ "format": " sm_semaphore_count : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_FIFO_SUS": {
+ "apiType": "index",
+ "format": " sm_fifo_suspend : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_TASKS_WAIT": {
+ "apiType": "index",
+ "format": " sm_tasks_waiting : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SM_SCB_SUSP_LIST": {
+ "apiType": "index",
+ "format": " sm_suspension_list : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB": {
+ "apiType": "index",
+ "format": "Content of event group control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB_CREATED": {
+ "apiType": "index",
+ "format": " ev_created : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB_ID": {
+ "apiType": "index",
+ "format": " ev_id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB_NAME": {
+ "apiType": "index",
+ "format": " ev_name : %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB_CUR_EVENTS": {
+ "apiType": "index",
+ "format": " ev_current_events : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB_TASKS_WAIT": {
+ "apiType": "index",
+ "format": " ev_tasks_waiting : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EV_GCB_SUSP_LIST": {
+ "apiType": "index",
+ "format": " ev_suspension_list : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EMTX_EMCB": {
+ "apiType": "index",
+ "format": "Content of enhanced mutex control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EMTX_EMCB_MAX_PRIO": {
+ "apiType": "index",
+ "format": " emtx_max_wprio : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EMTX_EMCB_SUSPEND_COUNT": {
+ "apiType": "index",
+ "format": " emtx_suspension_count : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EMTX_EMCB_OWNER_TASK_NAME": {
+ "apiType": "index",
+ "format": " owner task name : %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EMTX_EMCB_EMTX_NAME": {
+ "apiType": "index",
+ "format": " emtx_name : %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SL_SCB_TITLE": {
+ "apiType": "index",
+ "format": "Content of RTOS spinlock control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_TITLE": {
+ "apiType": "index",
+ "format": "Content of KAL spinlock control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_NAME": {
+ "apiType": "index",
+ "format": " name : %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SL_SCB_CREATED": {
+ "apiType": "index",
+ "format": " sl_created : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SL_SCB_ID": {
+ "apiType": "index",
+ "format": " sl_id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SL_SCB_LOCKCOUNT": {
+ "apiType": "index",
+ "format": " sl_lock_count : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_SL_SCB_LOCK": {
+ "apiType": "index",
+ "format": " sl_lock : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_INTERRUPT_MASK": {
+ "apiType": "index",
+ "format": " interrupt_mask : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_OWNER_CONTEXT": {
+ "apiType": "index",
+ "format": " owner_context : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_START_TIME": {
+ "apiType": "index",
+ "format": " spinlock_start_time : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_TAKER": {
+ "apiType": "index",
+ "format": " spinlock_taker address: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_MAX_HOLD_TIME": {
+ "apiType": "index",
+ "format": " max_spinlock_hold_time : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_MAX_TAKER": {
+ "apiType": "index",
+ "format": " max_spinlock_taker : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_SPINLOCK": {
+ "apiType": "index",
+ "format": " spinlock : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ISLID_USERNUMBER": {
+ "apiType": "index",
+ "format": " userNumber : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_CONTEXT_TASK": {
+ "apiType": "index",
+ "format": "Context 0x%08X is TASK %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_CONTEXT_HISR": {
+ "apiType": "index",
+ "format": "Context 0x%08X is HISR %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_CONTEXT_LISR": {
+ "apiType": "index",
+ "format": "Context 0x%08X is interrupt %d (nested count %d) at vpe%d, tc%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_TITLE": {
+ "apiType": "index",
+ "format": "Content of lock control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_ADDRESS": {
+ "apiType": "index",
+ "format": " address : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_IRQ_MASK": {
+ "apiType": "index",
+ "format": " irq mask : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_OWNER_CONTEXT": {
+ "apiType": "index",
+ "format": " owner context : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_ITC_START_TIME": {
+ "apiType": "index",
+ "format": " lock take timestamp : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_TAKER": {
+ "apiType": "index",
+ "format": " taker : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_MAX_ITC_HOLD_TIME": {
+ "apiType": "index",
+ "format": " max hold time : %d us",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HWITCID_MAX_ITC_TAKER": {
+ "apiType": "index",
+ "format": " max taker : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_LOCK_START_TIME": {
+ "format": " lock_start_time : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_LOCK_TAKER": {
+ "format": " lock_taker address: 0x%08X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_LOCK_MAX_HOLD_TIME": {
+ "format": " max_lock_hold_time : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_LOCK_MAX_TAKER": {
+ "format": " max_lock_taker : 0x%08X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_LOCK_LOCK": {
+ "apiType": "index",
+ "format": " lock : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TCWQ_TITLE": {
+ "format": "Content of TC Workqueue %Mkal_workqueueid at core %d:",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_TCWQ_NODE": {
+ "format": " func_ptr:0x%08X, func_param:0x%08X, func_index:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE2_SYSTEM_MEMORY": {
+ "apiType": "index",
+ "format": "Insufficient system memory, balanced free space is %dB!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_INTERNAL_SYSTEM_MEMORY": {
+ "apiType": "index",
+ "format": "Insufficient internal system memory, balanced free space is %dB!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_DEBUG__MEMORY": {
+ "apiType": "index",
+ "format": "Insufficient debug memory, balanced free space is %dB!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_INSUFFICEINT__MEMORY": {
+ "apiType": "index",
+ "format": "Please enlarge the memory size by %dB!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_800_01": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ) failed to create a partitioned memory pool with zero Bytes buffer entry.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_800_02": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ) failed to create a partitioned memory pool with zero entry. ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_800_03": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ) failed to add entry in pool_info_g[]. ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_801_01": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ), dynamic memory allocation failed for data type kal_internal_poolid of a partitioned memory",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_801_02": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ), dynamic memory allocation failed for data buffer of a partitioned memory",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_801_03": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ), dynamic memory allocation failed for statistical pool of a partitioned memory.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_801_04": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ), failed to allocate history buffer from debug memory.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_801_08": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ), temporary memory allocation failed while initializing buffer header and footer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_820_01": {
+ "apiType": "index",
+ "format": "In get_int_ctrl_buffer(), the buffer size to be allocated should not be zero.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_820_02": {
+ "apiType": "index",
+ "format": "In kal_get_buffer(), the filename of buffer allocator should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_821_SIZE": {
+ "apiType": "index",
+ "format": "In get_int_ctrl_buffer(), the desired buffer size is too large.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_821_01": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c wanna get a large buffer with size =0x%X .",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_822_SIZE": {
+ "apiType": "index",
+ "format": "In get_int_ctrl_buffer(), the pool ID of the desired buffer may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_823_SIZE": {
+ "apiType": "index",
+ "format": "In kal_get_buffer(), buffer entries have been fully allocated, run-out of free space.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_830_01": {
+ "apiType": "index",
+ "format": "In kal_release_buffer(), the filename of buffer allocator should not be NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_833_01": {
+ "apiType": "index",
+ "format": "In kal_release_buffer(), Ctrl Buff Entry 0x%X is double released.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_840_PTR_P1": {
+ "apiType": "index",
+ "format": "In kal_release_buffer(), it is detected that the buffer footer is corrupted, it is no longer ((buff_number << 16) | 0xF2F2).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_841_PTR": {
+ "apiType": "index",
+ "format": "In kal_release_buffer(), it is detected that buffer header is corrupted, it is no longer 0xF1F1F1F1.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_842_PTR_P1": {
+ "apiType": "index",
+ "format": "In kal_get_buffer(), it is detected that buffer footer is no longer ((buff_number << 16) | 0xF2F2). It was previously",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_842_PTR_P2": {
+ "apiType": "index",
+ "format": "successfully released and is now regarded as free entry. It may be corrupted during the free period.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_843_PTR_P1": {
+ "apiType": "index",
+ "format": "In kal_get_buffer(), it is detected that buffer header is no longer 0xF1F1F1F1. It was previously ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_843_PTR_P2": {
+ "apiType": "index",
+ "format": "successfully released and is now regarded as free entry. It may be corrupted during the free period.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_844_PTR_P1": {
+ "apiType": "index",
+ "format": "In kal_release_buffer(), it is detected that the extended buffer footer is corrupted ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_844_PTR_P2": {
+ "apiType": "index",
+ "format": "(appended at end of buffer size being requested), it is no longer 0xF2F2F2F2.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_852_01": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c gets a buffer by a NULL pointer along the call path.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_853_01": {
+ "apiType": "index",
+ "format": "%c%c%c%c%c%c%c%c releases a buffer by a NULL pointer along the call path.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_880_PTR_P1": {
+ "apiType": "index",
+ "format": "In kal_release_buffer(), buffer pointer to be released belongs to neither of the partitioned memory pool,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_880_PTR_P2": {
+ "apiType": "index",
+ "format": "indexed by pool ID retrieved from KAL header or by address range.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_881_PTR_P1": {
+ "apiType": "index",
+ "format": "In kal_get_buffer(), it is detected that buffer pool ID is incorrect in PM header. It was previously ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_881_PTR_P2": {
+ "apiType": "index",
+ "format": "successfully released and is now regarded as free entry. It may be corrupted during the free period.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_882_PTR_P0": {
+ "apiType": "index",
+ "format": "control buffer possible leakage, file name ptr=0x%X,\\n",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_882_PTR_P1": {
+ "apiType": "index",
+ "format": " owner_task = %c%c%c%c%c%c, module_id =%d, file_name =%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_882_PTR_P2": {
+ "apiType": "index",
+ "format": " , user_ptr =0x%X, line =%d, size=%d, allocate_time=%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_882_PTR_P3": {
+ "apiType": "index",
+ "format": "possible leakage: ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_882_PTR_P4": {
+ "apiType": "index",
+ "format": "whitelist in-used buffer: ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_890_01": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool( ), NU_Create_Partition_Pool() does not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_892_01": {
+ "apiType": "index",
+ "format": "In kal_create_buff_pool()/kal_get_buffer, NU_Allocate_Partition() does not return NU_SUCCESS.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_893_PTR": {
+ "apiType": "index",
+ "format": "a de-allocated, corrupted or illegal pointer in kal_release_buffer()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_BUFF_UNKNOWN": {
+ "apiType": "index",
+ "format": "It may be a corrupted or illegal pointer!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_NOT_MONITOR": {
+ "apiType": "index",
+ "format": "Control buffer is not monitored!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_NOT_ALIGNMENT": {
+ "apiType": "index",
+ "format": "User is processing with a non-alignment %dB buffer pointer, it is absolutely prohibited",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_INVALID_POINTER": {
+ "apiType": "index",
+ "format": "User is providing an illegal pointer 0x%08X, which is absolutely prohibited!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_POOL_INFO_G_CORRUPTED": {
+ "apiType": "index",
+ "format": "Data structure pool_info_g corrupted!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_BUFFER_CORRUPT_REASONS": {
+ "apiType": "index",
+ "format": "Buffer may be corrupted by the owner of current, previous or next buffer entry!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_800_OVERFLOW": {
+ "apiType": "index",
+ "format": "Partitioned memory pool runs out of free space!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_823_SIZE_NOT_MONITOR_P1": {
+ "apiType": "index",
+ "format": "My dear, buffer monitoring is not turned on at size %d,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_823_SIZE_NOT_MONITOR_P2": {
+ "apiType": "index",
+ "format": "system has no idea about history on buffer transaction!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_823_SIZE_MONITOR_P1": {
+ "apiType": "index",
+ "format": "There are totally %d entries at control buffer size %d (Bytes).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_823_SIZE_MONITOR_P2": {
+ "apiType": "index",
+ "format": "Owners distribution as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_823_SIZE_MONITOR_P3": {
+ "apiType": "index",
+ "format": "%s: Allocate %d entries at %s line %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_823_SIZE_MONITOR_P4": {
+ "apiType": "index",
+ "format": "Caller Address: 0x%08X Allocate %d entries",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_840_PTR": {
+ "apiType": "index",
+ "format": "Please refer to buffer header listed above, KAL footer 0xF2F2F2F2 is missing!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_841_PTR": {
+ "apiType": "index",
+ "format": "Please refer to buffer header listed above, KAL header 0xF1F1F1F1 is missing!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_844_PTR": {
+ "apiType": "index",
+ "format": "Please refer to buffer header listed above, KAL extended footer corrupted!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_880_PTR": {
+ "apiType": "index",
+ "format": "Please refer to buffer header listed above, KAL header pool ID corrupted!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_881_PTR": {
+ "apiType": "index",
+ "format": "Please refer to buffer header listed above, buffer pool ID value 0x%08X is incorrect, it should be 0x%08X!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_893_PTR_MONITOR_P1": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c is releasing a %dB buffer pointer 0x%X from file %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_893_PTR_MONITOR_P2": {
+ "apiType": "index",
+ "format": "line %d, but it had been deallocated!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_893_PTR_MONITOR_P3": {
+ "apiType": "index",
+ "format": "Please refer to history records for more detailed!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_893_PTR_UNMONITOR_P1": {
+ "apiType": "index",
+ "format": "Task %c%c%c%c%c%c%c%c is releasing a %dB buffer pointer 0x%X,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_893_PTR_UNMONITOR_P2": {
+ "apiType": "index",
+ "format": "but it had been deallocated!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_823_SIZE_NOT_MONITOR_P1": {
+ "apiType": "index",
+ "format": "Please turn on buffer monitoring and reproduce again!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_823_SIZE_NOT_MONITOR_P2": {
+ "apiType": "index",
+ "format": "Input string *035670766*001*65535# via MMI; as long as",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_823_SIZE_NOT_MONITOR_P3": {
+ "apiType": "index",
+ "format": "the value won't be saved to NVRAM, re-input is required",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_823_SIZE_NOT_MONITOR_P4": {
+ "apiType": "index",
+ "format": "each time power-on!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB": {
+ "apiType": "index",
+ "format": "Full content of partitioned memory control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_CREATED": {
+ "apiType": "index",
+ "format": " pm_created : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_ID": {
+ "apiType": "index",
+ "format": " pm_id : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_NAME": {
+ "apiType": "index",
+ "format": " pm_name : %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_START_ADDR": {
+ "apiType": "index",
+ "format": " pm_start_address : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_POOL_SIZE": {
+ "apiType": "index",
+ "format": " pm_pool_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_PART_SIZE": {
+ "apiType": "index",
+ "format": " pm_partition_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_AVAIL": {
+ "apiType": "index",
+ "format": " pm_available : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_ALLOCATED": {
+ "apiType": "index",
+ "format": " pm_allocated : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_AVAIL_LIST": {
+ "apiType": "index",
+ "format": " pm_available_list : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_FIFO_SUSPEND": {
+ "apiType": "index",
+ "format": " pm_fifo_suspend : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_TASK_WAIT": {
+ "apiType": "index",
+ "format": " pm_tasks_waiting : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PM_PCB_SUSP_LIST": {
+ "apiType": "index",
+ "format": " pm_suspension_list : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY": {
+ "apiType": "index",
+ "format": "Complete history nodes of current buffer pointer [%d]:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY_STATE": {
+ "apiType": "index",
+ "format": " buffer_state : %Mkal_buff_state",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY_TASK": {
+ "apiType": "index",
+ "format": " owner_task : %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY_FILE": {
+ "apiType": "index",
+ "format": " file_name : %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY_LINE": {
+ "apiType": "index",
+ "format": " line : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY_SIZE": {
+ "apiType": "index",
+ "format": " size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_HISTORY_LR": {
+ "apiType": "index",
+ "format": "Buffer Allocator Caller Address : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_CURRENT_BUFFER_HEADER": {
+ "apiType": "index",
+ "format": "Header and footer of current buffer pointer as below :",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PREV_BUFFER_HEADER": {
+ "apiType": "index",
+ "format": "Header and footer of previous buffer pointer as below :",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_NEXT_BUFFER_HEADER": {
+ "apiType": "index",
+ "format": "Header and footer of next buffer pointer as below :",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_HEADER_RTOS1": {
+ "apiType": "index",
+ "format": " RTOS header 1 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_HEADER_RTOS2": {
+ "apiType": "index",
+ "format": " RTOS header 2 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_HEADER_KAL1": {
+ "apiType": "index",
+ "format": " KAL header 1 (0xF1F1F1F1 originaly) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_HEADER_KAL2": {
+ "apiType": "index",
+ "format": " KAL header 2 (task ID) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_FOOTER_KAL_EXT": {
+ "apiType": "index",
+ "format": " KAL extended footer (0xF2F2F2F2 if monitoring) = 0x%02X%02X%02X%02X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_FOOTER_KAL_EXT_UNKNOWN": {
+ "apiType": "index",
+ "format": " KAL extended footer (0xF2F2F2F2 if monitoring) : unknown",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_BUFFER_FOOTER_KAL2": {
+ "apiType": "index",
+ "format": " KAL footer (0xF2F2 originally) = 0x%04X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_POOL_INFO_G": {
+ "apiType": "index",
+ "format": "Full content of pool_info_g as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_POOL_INFO_G_NO": {
+ "apiType": "index",
+ "format": " pool_info_g[%d]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_POOL_INFO_G_ID": {
+ "apiType": "index",
+ "format": " pool_id : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_POOL_INFO_G_START": {
+ "apiType": "index",
+ "format": " start_address : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_POOL_INFO_G_END": {
+ "apiType": "index",
+ "format": " end_address : 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_601_01": {
+ "apiType": "index",
+ "format": "In kal_create_timer ( ), dynamic memory allocation failed for data type kal_timer_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_601_02": {
+ "apiType": "index",
+ "format": "In stack_create_timer ( ), dynamic memory allocation failed for data type stack_timer_struct.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_601_04": {
+ "apiType": "index",
+ "format": "In kal_create_timer ( ), dynamic debug memory allocation failed for kal_timer_stat_type.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_602_FF": {
+ "apiType": "index",
+ "format": "Create timer failed!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_604_01": {
+ "apiType": "index",
+ "format": "Hi dear, system fails to set a NULL timer pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_604_02": {
+ "apiType": "index",
+ "format": "Hi dear, system fails to recover the clock at Timer HISR.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_604_FF": {
+ "apiType": "index",
+ "format": "In kal_set_timer (), timer reset is not success; please refer to timer control block if corruption.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_605_01": {
+ "apiType": "index",
+ "format": "Hi dear, system fails to cancel a NULL timer pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_605_FF": {
+ "apiType": "index",
+ "format": "In kal_cancel_timer (), timer control block may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_609_26_": {
+ "apiType": "index",
+ "format": "In kal_set_timer (), timer disable failed, please refer to timer control block if corruption.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_60A_FF": {
+ "apiType": "index",
+ "format": "In kal_timer_routine_wraper (), timer hisr callback function 0x%08X executes too long.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_60B_FF": {
+ "apiType": "index",
+ "format": "System fails for timer hisr executes too long, and longest callback function ptr is 0x%08X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_892_PTR_P0": {
+ "apiType": "index",
+ "format": "Event Scheduler or KAL Timer create failure, maybe created too much, top 3 redundant timer:\\n",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_892_PTR_P1": {
+ "apiType": "index",
+ "format": "Event Scheduler: type 1, KAL Timer: type 2\\n",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_892_PTR_P2": {
+ "apiType": "index",
+ "format": "name = %c%c%c%c%c%c%c%c, count =%d, type:%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_TIMER_FF_1": {
+ "apiType": "index",
+ "format": "Timer to be created is existed, could not duplicate it!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_TIMER_FF_2": {
+ "apiType": "index",
+ "format": "Timer control block is corrupted!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_60A_CALLBACK_EXECUTE_TIME_P11": {
+ "apiType": "index",
+ "format": "Callback execution time: %d, preempted time: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_60A_CALLBACK_EXECUTE_TIME_P12": {
+ "apiType": "index",
+ "format": "Callback execution time: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_60B_CALLBACK_EXECUTE_TIME_P1": {
+ "apiType": "index",
+ "format": "Callback execution time are as following (from latest to oldest):",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_60B_CALLBACK_EXECUTE_TIME_P21": {
+ "apiType": "index",
+ "format": "Callback ptr: 0x%08X, execution time: %d, preempted time: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_60B_CALLBACK_EXECUTE_TIME_P22": {
+ "apiType": "index",
+ "format": "Callback ptr: 0x%08X, execution time: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB": {
+ "apiType": "index",
+ "format": "Content of timer control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_CREATED": {
+ "apiType": "index",
+ "format": " created : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_ID": {
+ "apiType": "index",
+ "format": " id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_NAME": {
+ "apiType": "index",
+ "format": " name : %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_NAME_16": {
+ "apiType": "index",
+ "format": " name : %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_FUNC": {
+ "apiType": "index",
+ "format": " expiration_routine : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_EXP_ID": {
+ "apiType": "index",
+ "format": " expiration_id : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_ENABLED": {
+ "apiType": "index",
+ "format": " enabled : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_EXP_COUNT": {
+ "apiType": "index",
+ "format": " expirations : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_INIT_TIME": {
+ "apiType": "index",
+ "format": " initial_time : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_RESCHEDULE": {
+ "apiType": "index",
+ "format": " reschedule_time : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TM_APP_TCB_ACTUAL_LIST": {
+ "apiType": "index",
+ "format": " actual_timer : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_111_6": {
+ "apiType": "index",
+ "format": "The dynamic cacheable switch API caller passes the start address(0x%x) which is not in dynamic cacheable switch region. Please find the cache API caller by callstack to check the parameter.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_111_7": {
+ "apiType": "index",
+ "format": "The dynamic cacheable switch API caller passes the invalid switch attribute(0x%x). Please find the cache API caller by callstack to check the parameter.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_111_8": {
+ "apiType": "index",
+ "format": "This fatal error means passing the address which is not in dynamic cacheable switch region or invalid attribute. However, the recorded status is unexpected. Please dump memory and let system service member to give you a hand!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_112_1": {
+ "apiType": "index",
+ "format": "The cache API caller passes the start address(0x%x) which is not aligned to L1 cache line size(%d bytes). Please find the cache API caller by callstack to check the parameter.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_112_2": {
+ "apiType": "index",
+ "format": "The cache API caller passes the start address(0x%x) which is not aligned to L2 cache line size(%d bytes). Please find the cache API caller by callstack to check the parameter.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_112_8": {
+ "apiType": "index",
+ "format": "This fatal error means passing the start address which is not aligned to L1/L2 cache line size for cache APL. However, the recorded statusis unexpected. Please dump memory and let system service member to give you a hand!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_113_3": {
+ "apiType": "index",
+ "format": "The cache API caller passes the size(0x%x) which is not aligned to L1 cache line size(%d bytes). Please find the cache API caller by callstack to check the parameter.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_113_4": {
+ "apiType": "index",
+ "format": "The cache API caller passes the size(0x%x) which is not aligned to L2 cache line size(%d bytes). Please find the cache API callerto check the parameter.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_113_5": {
+ "apiType": "index",
+ "format": "The cache API caller passes the size(0x%x) which is larger than cache size for cache API in HRT domain. Please find the cacheAPI caller by callstack to check why he/she need this time consuming operation.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_113_8": {
+ "apiType": "index",
+ "format": "This fatal error means passing the size which is not aligned to L1/L2 cache line size or too large size for cache API. However, the recorded status is unexpected. Please dump memory and let system service member to give you a hand!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_114": {
+ "apiType": "index",
+ "format": "It illegal to invalidate l2cache lock area. Please ask owner of 0x%08x to check their cache API usage",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_133_1": {
+ "apiType": "index",
+ "format": "This fatal error means that offending VPE did not kick WDT so most likely it hang somewhere",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c01_00": {
+ "apiType": "index",
+ "format": "In kal_evshed_create_pool(), malloc failed for total memory required by evshed pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c01_01": {
+ "apiType": "index",
+ "format": "In evshed_create(), malloc failed for a stack timer required by an event scheduler.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c01_02": {
+ "apiType": "index",
+ "format": "In evshed_create(), malloc failed for an event scheduler.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c01_03": {
+ "apiType": "index",
+ "format": "In evshed_enable_protect_property(), malloc failed for an event scheduler protect.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c02_FF": {
+ "apiType": "index",
+ "format": "In kal_evshed_create_pool(), system fails to create partitioned-memory pool for an event scheduler.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c03_00": {
+ "apiType": "index",
+ "format": "In kal_evshed_get_mem(), memory size being requested is larger than partitioned size.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c03_FF": {
+ "apiType": "index",
+ "format": "In kal_evshed_get_mem(), system fails to get buffer from evshed_pool_id",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c04_FF": {
+ "apiType": "index",
+ "format": "In kal_evshed_free_mem(), system fails to free buffer to evshed_pool_id, ptr=0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c05_ID": {
+ "apiType": "index",
+ "format": "In evshed_cancel_event(), canceling event scheduler owned by others is absolutely prohibited, eventid=0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c06_FF": {
+ "apiType": "index",
+ "format": "In evshed_cancel_event(), parameter eventid is a null pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_c0a_FF": {
+ "apiType": "index",
+ "format": "In event scheduler APIs, multiple tasks are operating same ES without protect.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b02": {
+ "apiType": "index",
+ "format": "Dividend is zero now!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b03": {
+ "apiType": "index",
+ "format": "Oh No! Software abnormal reset is encountered.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b04": {
+ "apiType": "index",
+ "format": "Division by zero happened when PC was at 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b06": {
+ "apiType": "index",
+ "format": "Someone tried to execute out of ISPRAM. PC was at 0x%08X and RA was at 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b06_1": {
+ "apiType": "index",
+ "format": "PC == RA so probably return address was corrupted in stack",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b06_2": {
+ "apiType": "index",
+ "format": "ISPRAM at CORE%d is at range 0x%08X - 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b31": {
+ "apiType": "index",
+ "format": "IRQ is disabled over %d us !",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b35": {
+ "apiType": "index",
+ "format": "IRQ is disabled after leaving LISR %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b36": {
+ "apiType": "index",
+ "format": "IRQ is disabled after leaving HISR",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b37": {
+ "apiType": "index",
+ "format": "SaveAndSetIRQMask cannot be used from HRT vpe",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b38": {
+ "apiType": "index",
+ "format": "RestoreIRQMask cannot be used from HRT vpe",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b39": {
+ "apiType": "index",
+ "format": "Too big area for kal_memset",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b3a": {
+ "apiType": "index",
+ "format": "LISR or HISR calling kal_mem_set with >64KB size, context should not do this since performance consideration, owner please review.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b3f": {
+ "apiType": "index",
+ "format": "Interrupt cannot be disabled on Critical HRT domain",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b60": {
+ "apiType": "index",
+ "format": "HMU detected MD long time no response.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1501": {
+ "apiType": "index",
+ "format": "Customer had defined %d task IDs, violates the default value %d!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1502": {
+ "apiType": "index",
+ "format": "Customer had defined %d module IDs, violates the default value %d!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1503": {
+ "apiType": "index",
+ "format": "Customer had defined %d message IDs, violates the default value %d!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1504": {
+ "apiType": "index",
+ "format": "Customer had defined %d SAP IDs, violates the default value %d!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f00": {
+ "apiType": "index",
+ "format": "Triggering the same CMIF interrupt more than once with CMIF driver API is prohibited!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f01": {
+ "apiType": "index",
+ "format": "Triggering the same CUIF interrupt more than once with CUIF driver API is prohibited!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f10": {
+ "apiType": "index",
+ "format": "[For USIP]Exception occurs because the L1 user call DDL API to change bin mode but didn\u0092t call the activate API for usip!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f10_1": {
+ "apiType": "index",
+ "format": "[For RAKE]Exception occurs because the L1 user call DDL API to change bin mode but the rake status is not deactivate done!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f11": {
+ "apiType": "index",
+ "format": "Exception occurs because the DSP user is still busy but L1 user call the DDL API to change bin mode!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f12": {
+ "apiType": "index",
+ "format": "Exception occurs because the previous DDL doesn\u0092t finish but user call the DDL API to change bin mode again!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f13": {
+ "apiType": "index",
+ "format": "Exception occurs because the bin mode is incorrect!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f18": {
+ "apiType": "index",
+ "format": "[SleepFLowAPI] Target DSP need to deactivate before activate.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f19": {
+ "apiType": "index",
+ "format": "[SleepFLowAPI] Target DSP need to activate before deactivate.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2f1a": {
+ "apiType": "index",
+ "format": "[SleepFLowAPI] Target DSP need to check activate done before deactivate.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3000_00": {
+ "apiType": "index",
+ "format": "MD3 C2K exception, please find C2K 1st line support!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3200": {
+ "apiType": "index",
+ "format": "AP KE then triggers cross core exception, please find AP 1st line support!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3201": {
+ "apiType": "index",
+ "format": "AP WDTTO (CE) then triggers cross core exception, please find AP 1st line support!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_32XX_DEFAULT": {
+ "apiType": "index",
+ "format": "AP triggers cross core exception, please find AP 1st line support!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b04_OutOfRange": {
+ "apiType": "index",
+ "format": "IRQ number being serviced is out of range; it is an illegal IRQ!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b04_NOT_REG": {
+ "apiType": "index",
+ "format": "IRQ number %d is an un-registered interrupt!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b04_MEMORY_CORRUPTION": {
+ "apiType": "index",
+ "format": "Memory corruption at lisr_dispatch_tbl[%d]!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_b04_LISR_DISPATCH_TBL": {
+ "apiType": "index",
+ "format": "Content of lisr_dispatch_tbl[%d]:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_b04_LISR_DISPATCH_TBL_V": {
+ "apiType": "index",
+ "format": " lisr_dispatch_tbl.vector : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_b04_LISR_DISPATCH_TBL_H": {
+ "apiType": "index",
+ "format": " lisr_dispatch_tbl.lisr_handler : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_b04_LISR_DISPATCH_TBL_D": {
+ "apiType": "index",
+ "format": " lisr_dispatch_tbl.description : %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c03_POOL_MONITOR_P1": {
+ "apiType": "index",
+ "format": "There are totally %d entries with event scheduler buffer size %d (Bytes).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c03_POOL_MONITOR_P2": {
+ "apiType": "index",
+ "format": "Owners distribution as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c03_POOL_MONITOR_P3": {
+ "apiType": "index",
+ "format": "There are %d events which handler func addr is 0x%08X in event scheduler %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c03_POOL_MONITOR_P4": {
+ "apiType": "index",
+ "format": "which dest module is %Mmodule_type (task: %c%c%c%c%c%c%c%c).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c0a_DISPLAY_CONCURRENT_THREADS_1": {
+ "apiType": "index",
+ "format": "%s and %s threads are operating the same event scheduler simultaneously without protect!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c0a_DISPLAY_CONCURRENT_THREADS_2": {
+ "apiType": "index",
+ "format": "1. If concurrent operating is not expected, please owners of these two threads review the code flow.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_c0a_DISPLAY_CONCURRENT_THREADS_3": {
+ "apiType": "index",
+ "format": "2. If concurrency(only tasks) is expected, you may enable the protect/mutex feature of this ES.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_b31_irq_disabled_duration": {
+ "apiType": "index",
+ "format": "IRQ is disabled %d QBs: locked by caller address 0x%08X, unlocked by caller address 0x%08X!!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_swla": {
+ "apiType": "index",
+ "format": "SWLA entry %d: %s started at %u, exececuted for %uus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_swla_current": {
+ "apiType": "index",
+ "format": "SWLA entry 0: %s started at %u, exececuting currently",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_b60_swla_toprunner": {
+ "apiType": "index",
+ "format": "During the %uus before exception, %s exececuted for %uus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_TITLE": {
+ "apiType": "index",
+ "format": "CM2 error info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_MASK": {
+ "apiType": "index",
+ "format": "GCR_ERROR_MASK 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_CAUSE": {
+ "apiType": "index",
+ "format": "GCR_ERROR_CAUSE 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ADDR": {
+ "apiType": "index",
+ "format": "GCR_ERROR_ADDR 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_MULT": {
+ "apiType": "index",
+ "format": "GCR_ERROR_MULT 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_TYPE": {
+ "apiType": "index",
+ "format": "CM2 Error Type: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_UTYPE": {
+ "apiType": "index",
+ "format": "Unknown CM2 Error Type: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL": {
+ "apiType": "index",
+ "format": "ErrCtl 0x%08X:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL_LBE": {
+ "apiType": "index",
+ "format": "LBE bit of ErrCtl is set which indicates that most recent Data Bus Error was involved a load instruction",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL_WABE": {
+ "apiType": "index",
+ "format": "WABE bit of ErrCtl is set which indicates that the most recent Data Bus Error was due to a write allocate and that store data was lost",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL_WABE_LBE": {
+ "apiType": "index",
+ "format": "It is possible for both LBE and WABE to be set if the bus error was on a line being used for both loads and stores.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL_TCBIND_TBE": {
+ "apiType": "index",
+ "format": "TC%d has TBE bit (of TCBind) set which indicates load/store causing bus error was issued by TC%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL_TCBIND_TBE_GENERAL1": {
+ "apiType": "index",
+ "format": "Implementations may set the TBE bits of multiple TCs on a single DBE exception if multiple memory requests to the same memory location or cache linefrom the different TCs were merged.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ERRCTL_TCBIND_TBE_GENERAL2": {
+ "apiType": "index",
+ "format": "Implementations may generate bus error exceptions without setting a TBE bit if it is not possible to associate the failing transaction with a particular TC.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_SRCPORT": {
+ "apiType": "index",
+ "format": "Source port: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_TAGID": {
+ "apiType": "index",
+ "format": "Tag ID: %x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_OCPMCMD": {
+ "apiType": "index",
+ "format": "OCP MCmd: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_UOCPMCMD": {
+ "apiType": "index",
+ "format": "Unknown OCP MCmd: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_TARGET_REGION": {
+ "apiType": "index",
+ "format": "Target region: %Mcm2_error_target_region",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_CCA": {
+ "apiType": "index",
+ "format": "Cache coherency attribute: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_SC": {
+ "apiType": "index",
+ "format": "Request was from a Store Conditional",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_INTERVENTION_RESP": {
+ "apiType": "index",
+ "format": "Core%d intervention response: %Mcm2_error_intervetion_sresp",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_COHERENT_STATE": {
+ "apiType": "index",
+ "format": "Core%d coherent state: %Mcm2_error_coherent_state",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_ARRAY": {
+ "apiType": "index",
+ "format": "Array type: %Mcm2_error_array_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_INST": {
+ "apiType": "index",
+ "format": "Instruction associated with error: %Mcm2_error_instruction",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_SYNDROME": {
+ "apiType": "index",
+ "format": "Syndrome associated with Tag or WS way, or Syndrome associated with Data DWord: %x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_MULTIWAY": {
+ "apiType": "index",
+ "format": "Multi-way error for Tag or WS RAM",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_WAY": {
+ "apiType": "index",
+ "format": "Way[2:0] associated with the error: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_DWORD": {
+ "apiType": "index",
+ "format": "DWord[3:0] with error: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CM2ERROR_MULTIPLE": {
+ "apiType": "index",
+ "format": "Multiple Uncorrectable",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TLB_TITLE": {
+ "apiType": "index",
+ "format": "TLB <index>: EntryLo0, EntryLo1, PageMask, EntryHi",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TLB_DUMP": {
+ "apiType": "index",
+ "format": "TLB %d: 0x%08X, 0x%08X, 0x%08X, 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_MOD_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when a store happens to non-writable section like ROM or MCU RO area",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DATAACCESS_ERROR": {
+ "apiType": "index",
+ "format": "In this case, instruction at 0x%08X tried to %s 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_INSTRUCTIONFETCH_ERROR": {
+ "apiType": "index",
+ "format": "In this case instruction was tried to be fetched from 0x%08X. Last jump was from 0x%08X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_MISS_STORE_LOAD_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens in 2 occasion:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_MISS_STORE_LOAD_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": " 1. Access in to address which is mapped but no TLB entry matches and EXL bit is set (This is used protect empty areas in memory map)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_MISS_STORE_LOAD_EXCEPTION_EXPLANATION2": {
+ "apiType": "index",
+ "format": " 2. When core accesses core specific area of other core (CACHED_EXTSRAM_CORE0/1/2)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_MISS_STORE_LOAD_EXCEPTION_EXPLANATION3": {
+ "apiType": "index",
+ "format": "In this case, EXL bit was set so EPC register cannot be used. Please use PC monitor data, last jump 0x%08X and badvaddr 0x%08X to resolve this case",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_REFILL_STORE_LOAD_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when accessing address which is mapped but no TLB entry matches and EXL bit is not set (This is used protect empty areas in memory map)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_EXECUTE_INHIBIT_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when instruction fetch happens from area which is marked as execute inhibit",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_EXECUTE_INHIBIT_EXCEPTION_EXPLANATION2": {
+ "apiType": "index",
+ "format": "In this case return address was corrupted in stack and that caused jump to invalid area during function return",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_EXECUTE_INHIBIT_EXCEPTION_EXPLANATION3": {
+ "apiType": "index",
+ "format": "Last return address in stack is located at 0x%08X and the word there is 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_EXECUTE_INHIBIT_EXCEPTION_EXPLANATION4": {
+ "apiType": "index",
+ "format": "Hint: check stack from memory dump around 0x%08X address and try to understand how 0x%08X got there",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_TLB_READ_INHIBIT_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when instruction fetch or data read happens from area which is marked as read inhibit",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ADDRESS_ERROR_STORE_LOAD_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens because of unaligned access",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DATA_INSTR_BUS_ERROR_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when an %s access makes a bus request (due to a cache miss or an uncacheable reference) and that request terminates in an error.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_INSTR_BUS_ERROR_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "Instruction errors are precises",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DATA_BUS_ERROR_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "data bus errors can be imprecise or precise",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RESERVED_INSTRUCTION_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when a reserved or undefined major opcode or function field is executed",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RESERVED_INSTRUCTION_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "In this case PC pointed to 0x%08X. Unknown instruction was possibly 0x%08X. Last jump was from 0x%08X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RESERVED_INSTRUCTION_EXCEPTION_EXPLANATION2": {
+ "apiType": "index",
+ "format": "L1 cache lines: (NOTE saved during exception handling so not sure if contains valid code pointed by pc",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RESERVED_INSTRUCTION_EXCEPTION_EXPLANATION3": {
+ "apiType": "index",
+ "format": "L2 cache lines: (NOTE saved during exception handling so not sure if contains valid code pointed by pc",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RESERVED_INSTRUCTION_EXCEPTION_EXPLANATION_NOCODE": {
+ "apiType": "index",
+ "format": "In this case PC 0x%08X did not point to code region. Last jump was from 0x%08X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_INTEGER_OVERFLOW_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when selected integer instructions (add,addi, sub) result in a 2's complement overflow.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_INTEGER_OVERFLOW_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "In this case PC was at 0x%08X when overflow happened",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type happens when an instruction or data reference matches the address information stored in the WatchHi and WatchLo registers",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "This debugging facility can be used as sw breakpoints or data watchpoints. For example stack overflow can be implemented with this facility.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_EXPLANATION2": {
+ "apiType": "index",
+ "format": "In this case, PC was at 0x%08X when watch exception happened",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DEFERRED_WATCH_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "In this case deferred watch exception occured which means it occured during EXL or ERL bit was set or during processor was in DEBUG mode",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DEFERRED_WATCH_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "This means EPC register does not point to offending address",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_EXPLANATION3": {
+ "apiType": "index",
+ "format": "In this case there was %s watch area 0x%08X-0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_EXPLANATION4": {
+ "apiType": "index",
+ "format": "In this case watchpoint WatchLo%d was registered from 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_REGS_TITLE": {
+ "apiType": "index",
+ "format": "Watch hi and lo regs currently:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_WATCH_EXCEPTION_REGS": {
+ "apiType": "index",
+ "format": "WatchLo%d: 0x%08X, WatchHi%d: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_EXPLANATION": {
+ "apiType": "index",
+ "format": "%Mexception_type is caused by multithreading ASE instruction FORK or YIELD. Or by gating storage",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_EXPLANATION1": {
+ "apiType": "index",
+ "format": "In this case thread exception subtype was %Mthread_exception_codes",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_OVERFLOW": {
+ "apiType": "index",
+ "format": "%Mthread_exception_codes occured because a FORK insruction at 0x%08X could not allocate TC",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_UNDERFLOW": {
+ "apiType": "index",
+ "format": "%Mthread_exception_codes occured because YIELD instruction at 0x%08X leaved no dynamically allocatable TCs activated on a VPE.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_INVALID_QUALIFIER": {
+ "apiType": "index",
+ "format": "%Mthread_exception_codes occured because YIELD instruction at 0x%08X specified an invalid condition for resuming execution.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_GATING_STORAGE": {
+ "apiType": "index",
+ "format": "%Mthread_exception_codes occured at 0x%08X because implementation dependent logic associated with gating or inter-thread communication (ITC) storage requires software intervention.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_YIELD_SCHEDULER": {
+ "apiType": "index",
+ "format": "%Mthread_exception_codes occured because a valid YIELD at 0x%08X instruction would have caused a rescheduling of a TC, and the YIELD Intercept bit is set",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_GATING_STORAGE_SCHEDULER": {
+ "apiType": "index",
+ "format": "%Mthread_exception_codes occured at 0x%08X because a Gating Storage load or store would have blocked and caused a rescheduling of a TC, and the GS Intercept bit is set",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_UNKNOWN": {
+ "apiType": "index",
+ "format": "%Mexception_type is a reserved type. Please contact SS team. PC was at 0x%08X when this happened",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_VPECONTROL": {
+ "apiType": "index",
+ "format": "VPEControl 0x%08X => YSI %s and GSI %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_TCSTATUS": {
+ "apiType": "index",
+ "format": "TCStatus 0x%08X => DT %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_THREAD_EXCEPTION_YQMASK": {
+ "apiType": "index",
+ "format": "YQMask 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1700_01": {
+ "apiType": "index",
+ "format": "In kal_adm_create2(), the given flag set is invalid.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1700_02": {
+ "apiType": "index",
+ "format": "In kal_adm_create2(), the given sub-pool size array is invalid.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1710_01": {
+ "apiType": "index",
+ "format": "In kal_adm_delete(), the ADM pool to be deleted is invalid: the ADM pool is set as clean deletion, and there are still occupied ADM buffer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1720_01": {
+ "apiType": "index",
+ "format": "In __kal_adm_alloc(), allocation failed because there is no enough MTK cache channel.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1720_04": {
+ "apiType": "index",
+ "format": "In __kal_adm_alloc_core(), allocation failed because the given alignment value is not 4B aligned.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_172C_01": {
+ "apiType": "index",
+ "format": "In __kal_adm_realloc(), re-allocation failed and the flag indicating fatal is set.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_172C_04": {
+ "apiType": "index",
+ "format": "In __kal_adm_realloc(), re-allocation failed because the given alignment is not 4B aligned.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1730_01": {
+ "apiType": "index",
+ "format": "In __kal_adm_free(), de-allocation failed because the memory block to be freed does not belong to the ADM pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1730_02": {
+ "apiType": "index",
+ "format": "In __kal_adm_free(), de-allocation failed because prev or next pointers of the memory block to be freed is invalid; corruption may occurs.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1732_ADDR": {
+ "apiType": "index",
+ "format": "In __kal_adm_free(), de-allocation failed because the given memory block is freed before; it's a double free problem.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1740_ADDR": {
+ "apiType": "index",
+ "format": "In __kal_adm_free(), de-allocation failed because the footer stamp of the memory block to be freed is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1741_ADDR": {
+ "apiType": "index",
+ "format": "In __kal_adm_free(), de-allocation failed because the header stamp of the memory block to be freed is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1750_00": {
+ "apiType": "index",
+ "format": "The given ADM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1751_00": {
+ "apiType": "index",
+ "format": "In __kal_adm_delete(), the given ADM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1752_00": {
+ "apiType": "index",
+ "format": "In __kal_adm_alloc_core(), the given ADM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1753_00": {
+ "apiType": "index",
+ "format": "In __kal_adm_free(),the given ADM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1754_00": {
+ "apiType": "index",
+ "format": "In __kal_adm_realloc(), the given ADM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1760_ID": {
+ "apiType": "index",
+ "format": "The ADM ID of the given ADM control block is not valid (0x20101027).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1761_ID": {
+ "apiType": "index",
+ "format": "In __kal_adm_delete(), the ADM ID of the given ADM control block is not valid (0x20101027).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1762_ID": {
+ "apiType": "index",
+ "format": "In __kal_adm_alloc_core(), the ADM ID of the given ADM control block is not valid (0x20101027).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1763_ID": {
+ "apiType": "index",
+ "format": "In __kal_adm_free (), the ADM ID of the given ADM control block is not valid (0x20101027).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1764_ID": {
+ "apiType": "index",
+ "format": "In __kal_adm_realloc (), the ADM ID of the given ADM control block is not valid (0x20101027).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1770_TASK": {
+ "apiType": "index",
+ "format": "Fatal occurs because somebody is using the ADM pool at the same time; concurrency usage is forbidden.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1771_PTR": {
+ "apiType": "index",
+ "format": "In kal_adm_get_prev_block_ptr()/kal_adm_get_next_block_ptr(), the given ADM buffer pointer is not inside the ADM pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1781_ADDR": {
+ "apiType": "index",
+ "format": "In kal_adm_get_extheader(), it failed to get ext-header because the ADM pool is not configured as ext-header embedded.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1790_01": {
+ "apiType": "index",
+ "format": "In adm_mb_check(), first block is corrupt because its state is not ADM_INUSE or previous block is not NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1790_02": {
+ "apiType": "index",
+ "format": "In adm_mb_check(), check failed because prev or next pointers of the memory block to be freed is invalid; corruption may occurs.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1790_03": {
+ "apiType": "index",
+ "format": "In adm_mb_check(), last block is corrupt because its state is not ADM_INUSE or next block is not NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1700_01": {
+ "apiType": "index",
+ "format": "Invalidate flags in kal_adm_create2, please use KAL_ADM_*_FLAG",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1700_02_P1": {
+ "apiType": "index",
+ "format": "The subpool_size in kal_adm_create/kal_adm_create2 is invalid.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1700_02_P2": {
+ "apiType": "index",
+ "format": "Please check if it is NULL, or the elemnts are monotone increasing and end with {0xffffffff, 0}",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1710_01": {
+ "apiType": "index",
+ "format": "Some buffers in the ADM pool are not freed when deleting ADM.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1720_01_P1": {
+ "apiType": "index",
+ "format": "There's insufficient MTKL1Cache channle for cache memory setting.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1720_01_P2": {
+ "apiType": "index",
+ "format": "Please check no memory leakage for MTKL1Cache buffer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1720_04": {
+ "apiType": "index",
+ "format": "Alignment is not a multiple of 4, and please check your alignment requirement.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_172C_01_P1": {
+ "apiType": "index",
+ "format": "It's unable realloc new memory block for data.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_172C_01_P2": {
+ "apiType": "index",
+ "format": "The behavior is controlled by KAL_ADM_REALLOCFAIL_FATAL_FLAG specified on kal_adm_create2.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_172C_01_P3": {
+ "apiType": "index",
+ "format": "Please ensure you have enough memory when realloc new memory block,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_172C_01_P4": {
+ "apiType": "index",
+ "format": "maybe you need to read ADM_public_api.ppt about how to handle realloc failure",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_172C_04": {
+ "apiType": "index",
+ "format": "Alignment is not a multiple of 4, and please check your alignment requirement.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1730_01_P1": {
+ "apiType": "index",
+ "format": "In kal_adm_free(this_adm, ptr), the ptr is not in the range of this_adm pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1730_01_P2": {
+ "apiType": "index",
+ "format": "Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1730_02_P1": {
+ "apiType": "index",
+ "format": "In kal_adm_free(this_adm, ptr), the ADM internal header previous to ptr is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1730_02_P2": {
+ "apiType": "index",
+ "format": "Please check memory blocks around it, especially the previous one.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1732_ADDR": {
+ "apiType": "index",
+ "format": "Double free, or dangling pointer? Please check the last free.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1740_ADDR_P1": {
+ "apiType": "index",
+ "format": "In kal_adm_free(this_adm, ptr), the footer guard pattern is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1740_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please check memory blocks around it, especially the previous one.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1741_ADDR_P1": {
+ "apiType": "index",
+ "format": "In kal_adm_free(this_adm, ptr), the header guard pattern is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1741_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please check memory blocks around, especially the previous block.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1750_00": {
+ "apiType": "index",
+ "format": "You past a NULL ADM ID to ADM functions. Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1751_00": {
+ "apiType": "index",
+ "format": "You past a NULL ADM ID to kal_adm_delete. Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1752_00": {
+ "apiType": "index",
+ "format": "You past a NULL ADM ID to kal_adm_alloc_*. Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1753_00": {
+ "apiType": "index",
+ "format": "You past a NULL ADM ID to kal_adm_realloc. Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1754_00": {
+ "apiType": "index",
+ "format": "You past a NULL ADM ID to ADM functions. Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1760_ID_P1": {
+ "apiType": "index",
+ "format": "No signature is found; the first word pointed by ADM ID should be 0x20101027.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1760_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X. Please check whether the pointer is valid or corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1761_ID_P1": {
+ "apiType": "index",
+ "format": "No signature is found in kal_adm_delete(); the first word pointed by ADM ID should be 0x20101027, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1761_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X. Please check whether the pointer is valid or corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1762_ID_P1": {
+ "apiType": "index",
+ "format": "No signature is found in kal_adm_alloc_*(); the first word pointed by ADM ID should be 0x20101027, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1762_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X. Please check whether the pointer is valid or corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1763_ID_P1": {
+ "apiType": "index",
+ "format": "No signature is found in kal_adm_free(); the first word pointed by ADM ID should be 0x20101027, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1763_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X. Please check whether the pointer is valid or corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1764_ID_P1": {
+ "apiType": "index",
+ "format": "No signature is found in kal_adm_realloc(); the first word pointed by ADM ID should be 0x20101027, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1764_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X. Please check whether the pointer is valid or corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1770_TASK_P1": {
+ "apiType": "index",
+ "format": "Two or more tasks are operating at the same ADM pool (the other task index is %d).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1770_TASK_P2": {
+ "apiType": "index",
+ "format": "Please check current task & task %d activities.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1771_PTR": {
+ "apiType": "index",
+ "format": "The given pinter is invalid. Please check your input ADM buffer pointer.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1781_ADDR_P1": {
+ "apiType": "index",
+ "format": "This ADM pool has no extheader.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1781_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please specify KAL_ADM_EXTHEADER_FLAG in kal_adm_create2 if you want an extheader.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1800_01": {
+ "apiType": "index",
+ "format": "In kal_afm_create(), AFM pool creation failed because the configuration is un-recognizable.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1800_02": {
+ "apiType": "index",
+ "format": "In kal_afm_create(), AFM pool creation failed because the given array of sub-pool size or number is illegal.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1800_03": {
+ "apiType": "index",
+ "format": "In kal_afm_create(), AFM pool creation failed because the given pool size is not large enough to create required sub-pools.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1820_05": {
+ "apiType": "index",
+ "format": "In kal_afm_internal_alloc_dbg(), allocation failed because users wrongly call _c/_nc API on non-cache-aligned creation AFM pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1831_ADDR": {
+ "apiType": "index",
+ "format": "In kal_afm_free(), de-allocation failed because the given memory block is freed before; it's a double free problem.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1840_ADDR": {
+ "apiType": "index",
+ "format": "In kal_afm_free()/kal_afm_check_integrity(), fatal occurs because the footer stamp of the memory block is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1841_ADDR": {
+ "apiType": "index",
+ "format": "In kal_afm_free()/kal_afm_check_integrity(), fatal occurs because the header stamp of the memory block is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1842_ADDR": {
+ "apiType": "index",
+ "format": "In kal_afm_internal_alloc_dbg(), allocation failed because the footer stamp of the memory block is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1843_ADDR": {
+ "apiType": "index",
+ "format": "In kal_afm_internal_alloc_dbg(), allocation failed because the header stamp of the memory block is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1850_00": {
+ "apiType": "index",
+ "format": "In AFM function,the given AFM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1851_00": {
+ "apiType": "index",
+ "format": "In kal_afm_delete(), the given AFM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1852_00": {
+ "apiType": "index",
+ "format": "In kal_afm_internal_alloc_dbg(),the given AFM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1853_00": {
+ "apiType": "index",
+ "format": "In kal_afm_free(),the given AFM control block pointer is NULL.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1860_ID": {
+ "apiType": "index",
+ "format": "In AFM function, the AFM ID of the given AFM control block is not valid (0x20100104).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1861_ID": {
+ "apiType": "index",
+ "format": "In kal_afm_delete(), the AFM ID of the given AFM control block is not valid (0x20100104).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1862_ID": {
+ "apiType": "index",
+ "format": "In kal_afm_internal_alloc_dbg(), the AFM ID of the given AFM control block is not valid (0x20100104).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1863_ID": {
+ "apiType": "index",
+ "format": "In kal_afm_free(), the AFM ID of the given AFM control block is not valid (0x20100104).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1800_01": {
+ "apiType": "index",
+ "format": "Unknow options are supplied. Please check every bit in options is defined as AFM_OPT_*.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1800_02": {
+ "apiType": "index",
+ "format": "The subpool_size or subpool_nr is NULL, and you must supply correct subpool settings.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1800_03": {
+ "apiType": "index",
+ "format": "There's no enough memory to create AFM pool. Please give a bigger memory to this AFM pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1820_05_P1": {
+ "apiType": "index",
+ "format": "Don't request a cache-line aligned memory from non-cache-line aligned AFM pool,",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1820_05_P2": {
+ "apiType": "index",
+ "format": "or you need to change to cache-line aligned pool.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1831_ADDR": {
+ "apiType": "index",
+ "format": "double free or dangling pointer? Please check where the previous free operation locates.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1840_ADDR_P1": {
+ "apiType": "index",
+ "format": "In kal_afm_free(this_afm, ptr), the AFM guard pattern after ptr is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1840_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please check memory blocks around, especially the case ptr overwritten.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1841_ADDR_P1": {
+ "apiType": "index",
+ "format": "In kal_afm_free(this_afm, ptr), the AFM guard pattern before ptr is corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1841_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please check memory blocks around, especially the case previous block corrupts ptr's header.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1842_ADDR_P1": {
+ "apiType": "index",
+ "format": "In kal_afm_alloc_*(this_afm, size), the AFM head guard pattern at 0x%X is corrupted (it should be 0x03F3F3F3).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1842_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please check users of memory blocks around 0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1843_ADDR_P1": {
+ "apiType": "index",
+ "format": "In kal_afm_alloc_*(this_afm, size), the AFM foot guard pattern at 0x%X is corrupted (it should be 0x04F4F4F4).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1843_ADDR_P2": {
+ "apiType": "index",
+ "format": "Please check users of memory blocks around 0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1850_00": {
+ "apiType": "index",
+ "format": "You past a NULL AFM ID to AFM function, Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1851_00": {
+ "apiType": "index",
+ "format": "You past a NULL AFM ID to kal_afm_delete(). Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1852_00": {
+ "apiType": "index",
+ "format": "You past a NULL AFM ID to kal_afm_alloc_*(). Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1853_00": {
+ "apiType": "index",
+ "format": "You past a NULL AFM ID to kal_afm_free(), Please check your input.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1860_ID_P1": {
+ "apiType": "index",
+ "format": "No valid signature is found in AFM funciton; the first word pointed by AFM ID should be 0x20100104, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1860_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X, Please check the pointer is valid or corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1861_ID_P1": {
+ "apiType": "index",
+ "format": "No valid signature is found in kal_afm_delete(); the first word pointed by AFM ID should be 0x20100104, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1861_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X, Please check the pointer is valid or corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1862_ID_P1": {
+ "apiType": "index",
+ "format": "No valid signature is found in kal_afm_alloc_*(); the first word pointed by AFM ID should be 0x20100104, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1862_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X, Please check the pointer is valid or corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1863_ID_P1": {
+ "apiType": "index",
+ "format": "No valid signature is found in kal_afm_free(); the first word pointed by AFM ID should be 0x20100104, ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_1863_ID_P2": {
+ "apiType": "index",
+ "format": "but now it is 0x%X, Please check the pointer is valid or corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_00": {
+ "apiType": "index",
+ "format": "[DSM] check dsmgr.h/dsmgr.c for dsm_section_id/DSM_ACTION!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_01_01": {
+ "apiType": "index",
+ "format": "[DSM] LR=0x%x is located in DSM section!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_01_02": {
+ "apiType": "index",
+ "format": "[DSM] SP=0x%x is located in DSM section!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_03_01": {
+ "apiType": "index",
+ "format": "[DSM] print out dsm_id/dsm_tick/dsm_action in dsm_action_record[index]!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_03_02": {
+ "apiType": "index",
+ "format": "[DSM] index =%d, dsm_section_id: %Mdsm_section_id, dsm_tick =0x%x, DSM_ACTION: %MDSM_ACTION",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_04_01": {
+ "apiType": "index",
+ "format": "[DSM] print out section status!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_DSM_COMMON_04_02": {
+ "apiType": "index",
+ "format": "[DSM] dsm_section_id: %Mdsm_section_id, dsm_section_status: %Mdsm_section_status",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1900_01": {
+ "apiType": "index",
+ "format": "",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1909_P1": {
+ "apiType": "index",
+ "format": "Exception happened when PC was at DSM section, please check DSM related infomation",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1909_P2": {
+ "apiType": "index",
+ "format": "to see if correct DSM section was loaded when exception happened",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_1909_P3": {
+ "apiType": "index",
+ "format": "Here is info about the exception:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2100_rcuptr": {
+ "apiType": "index",
+ "format": "In rcu_create ( ), the address of RCU(0x%X) does not align to spinlock size.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2101_size": {
+ "apiType": "index",
+ "format": "In rcu_create ( ), the memory size(%d) allocated for RCU cannot be divisible by block size.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2102_rcuptr": {
+ "apiType": "index",
+ "format": "The conrtol block of RCU may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2103_buffptr": {
+ "apiType": "index",
+ "format": "In rcu_free_read_lock ( ), the reader count of RCU block(0x%X) wanted to free is 0.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2104_rcuptr": {
+ "apiType": "index",
+ "format": "In rcu_get_free_buff ( ), there is no available block to write in RCU(0x%X).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2105_rcuptr": {
+ "apiType": "index",
+ "format": "In rcu_get_read_lock ( ), there is no available block to read in RCU(0x%X).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2106_buffptr": {
+ "apiType": "index",
+ "format": "In rcu_commit_data ( ), the control block of RCU block may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2107_buffptr": {
+ "apiType": "index",
+ "format": "In rcu_free_read_lock ( ), the checksum of the RCU block is not correct.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2108_count_1": {
+ "apiType": "index",
+ "format": "In rcu_create ( ), the total allocated buffer in the RCU is smaller than 2.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2108_count_2": {
+ "apiType": "index",
+ "format": "The size provided for the RCU to create block is too small.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2109_buffptr": {
+ "apiType": "index",
+ "format": "The control block of RCU or the control block of RCU block may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_2107_buffptr_1_1": {
+ "apiType": "index",
+ "format": "The control block of RCU or the control block of RCU block may be corrupted.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_2107_buffptr_1_2": {
+ "apiType": "index",
+ "format": "The correct checksum of this RCU block is not available.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_2107_buffptr_2": {
+ "apiType": "index",
+ "format": "The correct checksum of the RCU block is 0x%X. The checksum in the RCU block is 0x%X.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2100_rcuptr": {
+ "apiType": "index",
+ "format": "Please use the kernel service macro to create RCU memory and pass it correctly.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2101_size": {
+ "apiType": "index",
+ "format": "Please check the total allocated size and block size parameter for RCU creation.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2103_buffptr": {
+ "apiType": "index",
+ "format": "This RCU block is freed totally previously. Please check the free buffer sequence.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2104_buffptr": {
+ "apiType": "index",
+ "format": "The RCU block is out of memory for writing. Please enlarge the RCU size.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2105_buffptr": {
+ "apiType": "index",
+ "format": "Please commit data before reading.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2107_buffptr": {
+ "apiType": "index",
+ "format": "Please check the usage of RCU block and do not corrupt the RCU block control block.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2108_count": {
+ "apiType": "index",
+ "format": "The size for RCU can only create %d block. The RCU restriction is more than 1 block.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE3_2109_buffptr": {
+ "apiType": "index",
+ "format": "Please check the usage of RCU block and do not corrupt the RCU block control block.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB": {
+ "apiType": "index",
+ "format": "Content of RCU control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_ID": {
+ "apiType": "index",
+ "format": " rcu_id : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_AVAIL_BUFF": {
+ "apiType": "index",
+ "format": " rcu_avail_buff : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_CURR_DATA": {
+ "apiType": "index",
+ "format": " rcu_curr_data : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_TOTAL_ALLOC_BUFF": {
+ "apiType": "index",
+ "format": " rcu_total_alloc_buff : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_TOTAL_AVAIL_BUFF": {
+ "apiType": "index",
+ "format": " rcu_total_avail_buff : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_BUFF_SIZE": {
+ "apiType": "index",
+ "format": " rcu_buff_size : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_SPINLOCK_ID": {
+ "apiType": "index",
+ "format": " rcu_spinlock : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_CB_LASTEST_COMMIT_MODID": {
+ "apiType": "index",
+ "format": " rcu_lastest_commit_modid : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB": {
+ "apiType": "index",
+ "format": "Content of RCU block control block as below:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_RCU_PTR": {
+ "apiType": "index",
+ "format": " rcu_ptr : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_NEXT_BUFF_PTR": {
+ "apiType": "index",
+ "format": " rcu_next : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_READER_COUNT": {
+ "apiType": "index",
+ "format": " rcu_reader_count : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_CHECKSUM": {
+ "apiType": "index",
+ "format": " rcu_checksum : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_DEBUG_PRE_BUFF_PTR": {
+ "apiType": "index",
+ "format": " rcu_debug_pre_buff : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_DEBUG_NEXT_BUFF_PTR": {
+ "apiType": "index",
+ "format": " rcu_debug_next_buff : 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_RCU_BLOCK_CB_BUFF_COUNT": {
+ "apiType": "index",
+ "format": " rcu_buff_count : %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_2302": {
+ "apiType": "index",
+ "format": "Remapping dest_mod_id from Global to Local failure, please find MD3 1st line support to check dest_mod_id 0x%x owner, src mod id is 0x%x, msg_id is 0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE2_2303": {
+ "format": "Remapping src_mod_id from Local to Global failure, owner please check. dest_mod_id 0x%x, src_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE2_2304": {
+ "format": "Remapping src_mod_id from Local to Global failure, owner please check. dest_mod_id 0x%x, src_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_PHASE2_2305": {
+ "apiType": "index",
+ "format": "Remapping dest_mod_id from Global to Local failure, please find MD3 1st line support to check dest_mod_id 0x%x owner, src mod id is 0x%x, msg_id is 0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2306_1": {
+ "apiType": "index",
+ "format": "In construct_cc_cached_peer_buff() or construct_cc_non_cached_peer_buff(), (pdu_len + header_len + tail_len) should larger than 0.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2306_2": {
+ "apiType": "index",
+ "format": "In construct_cc_cached_local_para() or construct_cc_non_cached_local_para(), local_para_size should larger than sizeof(local_para_struct).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2307": {
+ "apiType": "index",
+ "format": "External queue full is encountered while PS/L1 cross-core message (CC ILM) delivery. src_mod_id 0x%x, dest_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_2308": {
+ "apiType": "index",
+ "format": "External queue is NULL while PS/L1 cross-core message (CC ILM) delivery, please check why dest task in not running. src_mod_id 0x%x, dest_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3004": {
+ "apiType": "index",
+ "format": "External queue full is encountered while MD3->MD1 cross-core message (CC IRQ ILM) delivery. src_mod_id 0x%x, dest_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3005": {
+ "apiType": "index",
+ "format": "External queue is NULL while MD3->MD1 cross-core message (CC IRQ ILM) delivery, please check why dest task in not running. src_mod_id 0x%x, dest_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3006": {
+ "apiType": "index",
+ "format": "The local dest module id is not located in current (PS or L1 core), please check why such MD3->MD1 CC IRQ ILM will send to here. src_mod_id 0x%x, dest_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3007": {
+ "apiType": "index",
+ "format": "The src module id is not located in current (PS or L1 core), please correct the MD1->MD3 CC IRQ ILM content. src_mod_id 0x%x, dest_mod_id 0x%x, msg_id 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3107": {
+ "apiType": "index",
+ "format": "Watchdog interrupt occured. Following VPEs have not kicked WDT: ",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3107_VPES": {
+ "apiType": "index",
+ "format": "VPE%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3107_COULD_NOT_FIND_OFFENDER1": {
+ "apiType": "index",
+ "format": "Could not detect which vpe did not kick WDT",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3107_COULD_NOT_FIND_OFFENDER2": {
+ "apiType": "index",
+ "format": "Could not find offender. It is nested irq at vpe%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_PHASE1_3107_COULD_FIND_OFFENDER1": {
+ "apiType": "index",
+ "format": "Last context running at vpe%d is %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MDDBG_API_UT_ENABLE": {
+ "format": "mddbg_enableAll(%d) : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_DISABLE": {
+ "format": "mddbg_disable() : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_QUERY": {
+ "format": "mddbg_query() : %d, bp_cnt = %d, wp_cnt = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_ENABLE_BPS": {
+ "format": "mddbg_enable_bps() : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_DISABLE_BPS": {
+ "format": "mddbg_disable_bps() : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_SET_BP": {
+ "format": "mddbg_set_bp(0x%08X, %d) : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_ENABLE_WPS": {
+ "format": "mddbg_enable_wps() : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_DISABlE_WPS": {
+ "format": "mddbg_disable_wps() : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_SET_WP": {
+ "format": "mddbg_set_wp(0x%08X, %d, %d, %d) : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_SET_WP_RANGE": {
+ "format": "mddbg_set_wp_range(0x%08X, 0x%08X, %d, %d) : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_READ_MEM": {
+ "format": "Read Memory (0x%08X, %d) = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_WRITE_MEM": {
+ "format": "Write Memory (0x%08X) = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_SET_BP_PARAM": {
+ "apiType": "index",
+ "format": "[MDDBG]Breakpoint addr = 0x%08X, control = 0x%08X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_SET_BP_IDX": {
+ "format": "set_idx = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_API_UT_SET_WP_TEXT": {
+ "format": "wcr:0x%08X, wp_addr:0x%08X, byte_number:%d, access_type:%d, enable:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_WATCHDOG_RESET_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter Watchdog reset",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_WATCHDOG_RESET_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit Watchdog reset",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_WATCHDOG_RESET_EH_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON]%s Enter Watchdog reset",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_WATCHDOG_RESET_EH_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON]%s Exit Watchdog reset",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_WATCHDOG_DISABLE_ENTER": {
+ "format": "[EXC][COMMON] Enter Watchdog disable",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_WATCHDOG_DISABLE_EXIT": {
+ "format": "[EXC][COMMON] Exit Watchdog disable",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_FLUSH_LOGGING_PORT_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit dhl_flush_logging_port_for_exception()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_NE_FLUSH_LOGGING_PORT_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON][Nested] Exit dhl_flush_logging_port_for_exception()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_CCCI_HANDSHAKING_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ccci_exception_handshake()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_CCCI_HANDSHAKING_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ccci_exception_handshake()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_RESET_HARDWARE_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_reset_hw()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_RESET_HARDWARE_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_reset_hw()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_TL1_FORCESTALL_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter TL1_ForceStall()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_TL1_FORCESTALL_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit TL1_ForceStall()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_L1D_PAUSEDSP_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter L1D_PauseDSP()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_L1D_PAUSEDSP_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit L1D_PauseDSP()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_L1AUDIO_RESETDEVICE_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter L1Audio_ResetDevice()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_L1AUDIO_RESETDEVICE_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit L1Audio_ResetDevice()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_DUMP_SLAVE_LOG_ENTER": {
+ "format": "[EXC][COMMON] Enter dhl_cc_exception_dump_slave_log()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_DUMP_SLAVE_LOG_EXIT": {
+ "format": "[EXC][COMMON] Exit dhl_cc_exception_dump_slave_log()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_NE_DUMP_SLAVE_LOG_ENTER": {
+ "format": "[EXC][COMMON][Nested] Enter dhl_cc_exception_dump_slave_log()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_NE_DUMP_SLAVE_LOG_EXIT": {
+ "format": "[EXC][COMMON][Nested] Exit dhl_cc_exception_dump_slave_log()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_HS_ENTER": {
+ "format": "[EXC][COMMON] Enter ex_int_cc_handshake(%d)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_HS_EXIT": {
+ "format": "[EXC][COMMON] Exit ex_int_cc_handshake(%d)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_CADEFA_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_CADEFA_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_USIP_CADEFA_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_usip_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_USIP_CADEFA_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_usip_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_MD32_CADEFA_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_md32_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_MD32_CADEFA_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_md32_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SCQ_CADEFA_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_scq_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SCQ_CADEFA_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_scq_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SONIC_CADEFA_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_sonic_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SONIC_CADEFA_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_sonic_cadefa()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INVOKE_SST_ENGINE_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter INT_InvokeSSTEngine()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INVOKE_SST_ENGINE_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit INT_InvokeSSTEngine()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_EMM_WRITE_EX_RECORD_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter EMM_Write_ExceptRecord()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_EMM_WRITE_EX_RECORD_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit EMM_Write_ExceptRecord()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SWLA_PRINT_LOWRAM_ENTER": {
+ "format": "[EXC][COMMON] Enter SLA_Print_low_RAM_SWLA()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_SWLA_PRINT_LOWRAM_EXIT": {
+ "format": "[EXC][COMMON] Exit SLA_Print_low_RAM_SWLA()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_output_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_output_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_USIP_EXCEPTION_RECORD_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_output_usip_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_USIP_HS_FAILED": {
+ "apiType": "index",
+ "format": "usip HS failed [%d]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_USIP_EXCEPTION_RECORD_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_output_usip_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_MD32_EXCEPTION_RECORD_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_output_md32_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_MD32_HS_FAILED": {
+ "apiType": "index",
+ "format": "md32 HS failed [%d]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_MD32_EXCEPTION_RECORD_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_output_md32_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SONIC_EXCEPTION_RECORD_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_output_sonic_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SONIC_HS_FAILED": {
+ "apiType": "index",
+ "format": "sonic HS failed [%d]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_OUTPUT_SONIC_EXCEPTION_RECORD_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_output_sonic_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_PASS_CCCI_EXCINFO_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ccci_exception_info_passed()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_PASS_CCCI_EXCINFO_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ccci_exception_info_passed()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_FLC_DEBUG_INFO_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter flc2_debug_assert_callback()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_FLC_DEBUG_INFO_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit flc2_debug_assert_callback()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_RMPU_DEBUG_INFO_ENTER": {
+ "format": "[EXC][COMMON] Enter emimpu_dump_status()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_RMPU_DEBUG_INFO_EXIT": {
+ "format": "[EXC][COMMON] Exit emimpu_dump_status()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_INIT_FDD_TABLE_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter Initialize_FDD_tables()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_FDD_TABLE_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit Initialize_FDD_tables()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SAVE_EXCEPTION_RECORD_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_save_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SAVE_EXCEPTION_RECORD_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_save_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_FS_UNLOCK_ALL_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter FS_UnlockAll()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_FS_UNLOCK_ALL_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit FS_UnlockAll()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_FS_SHUTDOWN_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter FS_ShutDown()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_FS_SHUTDOWN_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit FS_ShutDown()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_NVRAM_WRITE_EXC_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter nvram_write_exception(%d, 0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_NVRAM_WRITE_EXC_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit nvram_write_exception()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_EMM_WRITE_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter EMM_Write_ExceptRecord()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_EMM_WRITE_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit EMM_Write_ExceptRecord()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_RESET_EXCSP_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter INT_ExceptionResetExcSP()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_RESET_EXCSP_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit INT_ExceptionResetExcSP()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_CLEAN_RES_PROT_ENTER": {
+ "format": "[EXC][COMMON] Enter ex_clean_res_prot()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_CLEAN_RES_PROT_EXIT": {
+ "format": "[EXC][COMMON] Exit ex_clean_res_prot()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_UNGUARD_STACKSPACE_ENTER": {
+ "format": "[EXC][COMMON] Enter kal_unguard_stack_space()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_UNGUARD_STACKSPACE_EXIT": {
+ "format": "[EXC][COMMON] Exit kal_unguard_stack_space()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_NESTED_PROCESS_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_nested_process()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_NESTED_PROCESS_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_nested_process()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_DUMP_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_init_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_DUMP_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_init_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_remove_sensitive_for_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_remove_sensitive_for_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_BBREG_DUMP_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_init_bbreg_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_BBREG_DUMP_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_init_bbreg_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_MINI_DUMP_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_init_mini_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_MINI_DUMP_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_init_mini_dump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_REAPPEAR_LOG_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_reappear_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_INIT_REAPPEAR_LOG_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_reappear_log()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_EX_REBOOT4MP_ENTER": {
+ "format": "[EXC][COMMON] Enter ex_reboot4mp()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_EX_REBOOT4MP_EXIT": {
+ "format": "[EXC][COMMON] Exit ex_reboot4mp()",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_SYSMEM_TO_BE_DUMPED": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] sys_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SYSMEM_TO_BE_DUMPED_FOR_MINI": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] sys_mem_xxx.bin to be dumped for mini [%d]: (0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SONICMEM_TO_BE_DUMPED": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] %ssonic_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SONICMEM_TO_BE_DUMPED_FOR_MINI": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] %ssonic_mem_xxx.bin to be dumped for mini [%d]: (0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SLAVE_SYSMEM_TO_BE_DUMPED": {
+ "format": "[EXC][COMMON] slave_sys_mem_0x%08x.bin to be dumped [%d]: (0x%x, 0x%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_DHLLOGGING_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter dhl_call_exception_custom_logging at %dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_DHLLOGGING_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit dhl_call_exception_custom_logging at %dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_HANDOVER2TST": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Handover to TST exception handler",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_READY2REBOOT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Ready to silent reboot",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_USER_CALLBACK_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter sensitive-removing callback, Index:%d, Taskname:%s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_USER_CALLBACK_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit sensitive-removing callback, Index:%d, Taskname:%s, Elapsedtime:%dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_CTRLBUFF_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter sensitive-removing: kal_clear_all_sensitive_buff_data()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_CTRLBUFF_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit sensitive-removing: kal_clear_all_sensitive_buff_data(), Elapsedtime:%dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_QBM_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter sensitive-removing: qbm_clear_all_sensitive_data()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_QBM_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit sensitive-removing: qbm_clear_all_sensitive_data(), Elapsedtime:%dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_FL2_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter sensitive-removing: fl2_ent_mask_peer_buff_for_miniDump()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_FL2_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit sensitive-removing: fl2_ent_mask_peer_buff_for_miniDump(), Elapsedtime:%dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_STACK_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter sensitive-removing stack, Index:%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_STACK_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit sensitive-removing stack, Index:%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_DETECT_ERROR": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] sensitive-removing, detect errror happened! Exception Count:%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_REMOVE_SENSITIVE_DEBUG_STACK_INFO": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit sensitive-removing stack,sp:0x%x, start:0x%x, size:0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SWITCH_WDT_PHASE2": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Do ex_switchWDT_phase2()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_COUNT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] BB register dump count: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_OWNER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] BB register dump owner: %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter BB register dump callback, address: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit BB register dump callback, address: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_SKIP": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Skip this dump",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_SKIP2": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Callback (0x%x) caused nested exception -> skip this dump",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_TO_BE_DUMPED": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] bb_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x, %d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_LARGE": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] bb_mem size is larger than %d KB: (base, len)=(0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_OVERLAP_SYS": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] bb_mem (0x%x, 0x%x) overlap sys_mem (0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_DUMP_TOP_NUM": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] top%d bb_mem (0x%x, 0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_L1CORE_BBREG_DUMP_OWNER": {
+ "format": "[EXC][COMMON][L1CORE] BB register dump owner: %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_L1CORE_BBREG_DUMP_TO_BE_DUMPED": {
+ "format": "[EXC][COMMON][L1CORE] bb_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x, %d)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_MINIDUMP_SYMBOL_OWNER": {
+ "format": "[EXC][COMMON][MINIDUMP] symbol/area owner: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MINIDUMP_SYMBOL_CLEAN": {
+ "format": "[EXC][COMMON][MINIDUMP] symbol/area cleaned: 0x%08x - 0x%08x, %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MINIDUMP_SYMBOL_NESTED": {
+ "format": "[EXC][COMMON][MINIDUMP] symbol/area 0x%08x - 0x%08x, %s, caused nested exception, SKIP it",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_HANDLE_DUMP_REGION_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter SST_HandleDumpRegion(addr=0x%08x, len=0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_HANDLE_DUMP_REGION_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit SST_HandleDumpRegion(addr=0x%08x, len=0x%x, operation result=%s)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_HANDLE_DUMP_REGION_OP_CACHED": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] SST_HandleDumpRegion: Do cache operation",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_HANDLE_DUMP_REGION_OP_TIMEOUT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON]Timeout(> %dus): Start: %dus, End= %dus, Duration = %dus",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_HANDLE_EMIMPU_OUTPUT_ADDR": {
+ "format": "[EXC][EMIMPU] MasterID:%x(%s) ViolationAddr:%x(%s)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SST_EXC_HANDLE_EMIMPU_OUTPUT_REGION": {
+ "apiType": "index",
+ "format": "[EXC][EMIMPU] Region:%d Domain:%d Out-of-Range:%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_BBREG_OUTPUT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON][BBREG_OUTPUT] address=0x%08x value=0%08x, sub_idx=%d, fill_cnt=%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_QUERY_BBREG_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON]ex_query_bbreg_info(buf_ptr=0%08x, start_idx=%d, num=%d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_QUERY_BBREG_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON]ex_query_bbreg_info() return fill_cnt=%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_QUERY_BBREG_SKIP": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] skip_cnt(%d)+traverser->num(%d)+prv_fill_cnt(%d) <= start_idx(%d) => skip_cnt=%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_COPY_BBREG_START_IDX": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] COPY_BBREG start idx=%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_QUERY_BBREG_UPDATE_SKIP": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] prv_fill_cnt: %d, this traverser->num: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_AFOUND_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_output_afound()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_AFOUND_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_output_afound()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SEC_CHANNEL_DEINIT_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter SST_SSF_Deinit()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_SEC_CHANNEL_DEINIT_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit SST_SSF_Deinit()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_LOG_ASSERT": {
+ "apiType": "index",
+ "format": "[%s(%s)] Assert fail: %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_LOG_FATAL_ERROR": {
+ "apiType": "index",
+ "format": "[%s(%s)] Fatal error: code1 0x%x, code2 0x%x, sp 0x%x, lr 0x%x, lisr level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_LOG_CTI": {
+ "apiType": "index",
+ "format": "[%s(%s)] Cross Trigger by other core",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_LOG_UNKNOWN": {
+ "apiType": "index",
+ "format": "[%s(%s)] Unknown exception",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_LOG_BYPASS_DUMP_INFO": {
+ "apiType": "index",
+ "format": "[%s] status 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_LOG_SYNCED_MASK": {
+ "apiType": "index",
+ "format": "USIP/SCQ16 sync mask 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SCQ16_COMMON_PM_INFO": {
+ "apiType": "index",
+ "format": "SCQ16 common pm checksum: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SCQ16_DDL_PM_INFO": {
+ "apiType": "index",
+ "format": "SCQ16 ddl pm checksum: %s, ddl_mode: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SCQ16_COMMON_PM_WITH_CHKSUM_INFO": {
+ "apiType": "index",
+ "format": "SCQ16 common pm checksum: %s, expected: 0x%X, current: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SCQ16_DDL_PM_WITH_CHKSUM_INFO": {
+ "apiType": "index",
+ "format": "SCQ16 ddl pm checksum: %s, ddl_mode: 0x%X, expected: 0x%X, current: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_COMMON_DOWNLOAD_NOT_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot common part not yet download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_COMMON_DOWNLOAD_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot common part download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_DDL_DOWNLOAD_NOT_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot ddl part not yet download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_DDL_DOWNLOAD_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot ddl part download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_FEC_TX_DDL_START": {
+ "format": "[DDL][FEC_TX-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_FEC_RX_DDL_START": {
+ "format": "[DDL][FEC_RX-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_BRP_DDL_START": {
+ "format": "[DDL][BRP-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_SCQ16_DDL_START": {
+ "format": "[DDL][SCQ16-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_INNER_DDL_START": {
+ "format": "[DDL][L2TCM-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_RAKE_DDL_START": {
+ "format": "[DDL][RAKE-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_SCQ16_DDL_START_GDMA": {
+ "format": "[DDL][SCQ16-TRIG_GDMA] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X, len: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_RAKE_DDL_START_GDMA": {
+ "format": "[DDL][RAKE-TRIG_GDMA] iA start gdma for rake ddl, idx: 0x%X, time: 0x%X, bin_mode: 0x%X, len: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_SET_INNER_DDL_PROTECT_DONE": {
+ "format": "[DDL][L2TCM-Done] idx: 0x%X, time: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_RAKE_DDL_DONE": {
+ "format": "[DDL][RAKE-Done] idx: 0x%X, time: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_GDMA_DONE": {
+ "format": "[DDL][SCQ16-GDMA-Done] idx: 0x%X, time: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_RAKE_DDL_LAST_MODE_IS_LTE": {
+ "format": "[DDL][RAKE] last mode is lte, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X, status: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_TRIG_CLR_INNER_DDL_PROTECT": {
+ "format": "[DDL][L2TCM] iA trigger to clear inner ddl protection, caller: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_CLR_INNER_DDL_PROTECT_DONE": {
+ "format": "[DDL][L2TCM] clear inner ddl protection done, re_call_rake_ddl_user: 0x%X, re_call_rake_ddl_mode:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_SEND_INT_TO_INNER_CLR_DDL_PROTECT": {
+ "format": "[DDL][L2TCM] iA send interrupt to usip-inner to clear inner ddl protection,caller: 0x%X, user_id: 0x%X, bin_mode: 0x%X, status: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_SEND_INT_TO_INNER_TO_SET_DDL_PROTECT": {
+ "format": "[DDL][L2TCM] iA send interrupt to usip-inner to set inner ddl protection, idx: 0x%X, time: 0x%X, bin_mode: 0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_DSP_GDMA_CB": {
+ "format": "[DDL] DSPGDMA_CB gdma done, gdma_who_use: 0x%X, gdma_who_wait:0x%X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "USIP_SCQ16_DDL_STATUS_BIN_MODE_INFO": {
+ "apiType": "index",
+ "format": "[DDL][%s] ddl_status: 0x%X, ddl_bin_mode: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "USIP_SCQ16_EX_REPORT_VU_STATUS": {
+ "apiType": "index",
+ "format": "[USIP(%s)] SCQ16_%d VU status, status %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "DSP_SLEEP_FLOW_ACTIVATE": {
+ "apiType": "index",
+ "format": "[DSP]DSP activate, thread %d, user %d, status 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "DSP_SLEEP_FLOW_DEACTIVATE": {
+ "apiType": "index",
+ "format": "[DSP]DSP deactivate, thread %d, user %d, status 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "DSP_SLEEP_FLOW_ACTIVATE_END": {
+ "apiType": "index",
+ "format": "[DSP]DSP activate end, return %d, thread %d, user %d, status 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "DSP_SLEEP_FLOW_DEACTIVATE_END": {
+ "apiType": "index",
+ "format": "[DSP]DSP deactivate end, return %d, thread %d, user %d, status 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "MD32_EX_LOG_ASSERT": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Assert fail: %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_UNDEF": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - undefined instruction: pc 0x%x, lr 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_ABORT": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - %s: pc 0x%x, address 0x%x, sp 0x%x, lr 0x%x, interrupt_level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_UND_IRQ": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - %s: 0x%x, interrupt_level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_UND_CMIF_IRQ": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - %s: isr_num %d, lr 0x%x, interrupt_level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_CTI": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - CTI Error",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_STACK_CORRUPT": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - %s: sp 0x%x, lr 0x%x, interrupt_level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_ECT": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error - ECT ERROR: code2 0x%x, lr 0x%x, interrupt_level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_DEFAULT": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Fatal error: code1 0x%x, code2 0x%x, sp 0x%x, lr 0x%x, interrupt_level %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_IN_SLEEP": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] Core is in sleep mode, so the exception flow is not active",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_WRONG_PATTERN": {
+ "apiType": "index",
+ "format": "[MD32(RAKE)] The CMIF Pattern is 0x%x, RAKE may not finish exception flow",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_EX_LOG_BIN_BUILD_INFO": {
+ "format": "[MD32(%s)] Project: %s Flavor: %s BuildTime: %s Label: %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MD32_EX_LOG_EX_FLOW_PROGRESS": {
+ "format": "[%s] [MD32(%s)] Exception flow status: %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MD32_EX_LOG_CMIF_REACHABLE": {
+ "apiType": "index",
+ "format": "CMIF status from L1 core is %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_COMMON_DOWNLOAD_NOT_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot common part not yet download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_DDL_DOWNLOAD_NOT_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot ddl part not yet download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_COMMON_DOWNLOAD_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot common part download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_DDL_DOWNLOAD_DONE_INFO": {
+ "apiType": "index",
+ "format": "[%s] first boot ddl part download done...",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MD32_DDL_STATUS_BIN_MODE_INFO": {
+ "apiType": "index",
+ "format": "[DDL][%s] ddl_status: 0x%X, ddl_bin_mode: 0x%X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_ASSERT": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Assert fail: %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_ASSERT_NO_E1_TO_E3": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Assert fail: %s - %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_CUSTOM_ASSERT_ADDR": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Assert fail (CUSTOM_ASSERT_ADDR): addr:0x%08x, %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_CUSTOM_ASSERT_ADDR_NO_E1_TO_E3": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Assert fail (CUSTOM_ASSERT_ADDR): addr:0x%08x, %s - %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_CUSTOM_ASSERT_MOFID": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Assert fail (CUSTOM_ASSERT_MOFID): mofid:%d mof_name:%s %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_CUSTOM_ASSERT_MOFID_NO_E1_TO_E3": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Assert fail (CUSTOM_ASSERT_MOFID): mofid:%d mof_name:%s %s - %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_FATAL_ERROR": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Fatal Error - code1 0x%x (%s), code2 0x%x. Version: %s BuildTime: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_DBGC_FATAL_ERROR": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Fatal Error - code1 0x%x (%s, source:%d), code2 0x%x. Version: %s BuildTime: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_CTI": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Cross Trigger by other core or thread",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_NONE": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] No run exception flow.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_UNKNOWN": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-1] Unknown exception",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_ASSERT": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Illegal Assertion: %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_ASSERT_NO_E1_TO_E3": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Illegal Assertion: %s - %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_CUSTOM_ASSERT_ADDR": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Illegal CUSTOM_ASSERT_ADDR: addr:0x%08x, %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_CUSTOM_ASSERT_ADDR_NO_E1_TO_E3": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Illegal CUSTOM_ASSERT_ADDR: addr:0x%08x, %s - %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_CUSTOM_ASSERT_MOFID": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Illegal CUSTOM_ASSERT_MOFID: mofid:%d mof_name:%s %s - %d 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_CUSTOM_ASSERT_MOFID_NO_E1_TO_E3": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Illegal CUSTOM_ASSERT_MOFID: mofid:%d mof_name:%s %s - %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_FATAL_ERROR": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Fatal Error - code1 0x%x (%s), code2 0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_NESTED_EX_LOG_UNKNOWN": {
+ "apiType": "index",
+ "format": "[%s(%d)] [EX-2] (Nested Exception) Unknown exception",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_BYPASS_DUMP_INFO": {
+ "apiType": "index",
+ "format": "[%s(%d)] status 0x%x, steps: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_SYNCED_MASK": {
+ "apiType": "index",
+ "format": "SONIC sync mask 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_LOG_FORCE_SYNCED_MASK": {
+ "apiType": "index",
+ "format": "SONIC FORCE sync mask 0x%x, SKIP force sync mask 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_SONIC_EX_DUMP_MSONIC_PHASE_STATUS": {
+ "apiType": "index",
+ "format": "[SONIC] phase2 dump curr_steps %d, status %x, current time:%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_UART_RING_BUFFER_START": {
+ "format": "[EXC][COMMON] Dump UART ring buffer data start (port:%MDCL_DEV_T)!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_UART_RING_BUFFER_END": {
+ "format": "[EXC][COMMON] Dump UART ring buffer data end (port:%MDCL_DEV_T)!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_START": {
+ "format": "[EXC][COMMON] Disable Lga buffer start!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DISABLE_LGA_BUF_UNDER_SS_END": {
+ "format": "[EXC][COMMON] Disable Lga buffer end!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CLEAN_UART_UNDER_SS_START": {
+ "format": "[EXC][COMMON] Clean up UART channel start (port:%MDCL_DEV_T)!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CLEAN_UART_UNDER_SS_END": {
+ "format": "[EXC][COMMON] Clean up UART channel end (port:%MDCL_DEV_T)!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_PS_BUF_START": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Dump PS Buf start!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_PS_BUF_END": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Dump PS Buf end!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_DISABLE_LGA_BUF_START": {
+ "format": "[EXC][ELT] Disable Lga buffer start!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DISABLE_LGA_BUF_END": {
+ "format": "[EXC][ELT] Disable Lga buffer end!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_REOPEN_PORT_START": {
+ "format": "[EXC][ELT] Reopen logging ports start!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_REOPEN_PORT_END": {
+ "format": "[EXC][ELT] Reopen logging ports end!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_OPEN_PORT_START": {
+ "format": "[EXC][ELT] open logging ports start! (Port:%MDCL_DEV_T)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_OPEN_PORT_END": {
+ "format": "[EXC][ELT] open logging ports end! (Port:%MDCL_DEV_T)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CLEAN_UART_START": {
+ "format": "[EXC][ELT] Clean up UART channel start! (Port:%MDCL_DEV_T)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CLEAN_UART_END": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Clean up UART channel end! (Port:%MDCL_DEV_T)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CLOSE_PORT_START": {
+ "format": "[EXC][ELT] close logging ports start! (Port:%MDCL_DEV_T)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CLOSE_PORT_END": {
+ "format": "[EXC][ELT] close logging ports end! (Port:%MDCL_DEV_T)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_CHANGE_L1_PORT": {
+ "format": "[EXC][ELT] Change L1 logging port from %MDCL_DEV_T to %MDCL_DEV_T !",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_NESTED_EX_DETECTED": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Detect nested exception! (times:%d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_SST_LOG_START": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Redump exception log start!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_SST_LOG_END": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Redump exception log end!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_DRV_EX_HANDLER_START": {
+ "format": "[EXC][ELT] Drv ex handler start!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DRV_EX_HANDLER_END": {
+ "format": "[EXC][ELT] Drv ex handler end!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_LGA_BUF_START": {
+ "format": "[EXC][ELT] Dump Lga buffer start!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_LGA_BUF_END": {
+ "format": "[EXC][ELT] Dump Lga buffer end!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_REDUMP_PS_BUF_START": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Redump PS buffer start!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_REDUMP_PS_BUF_END": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Redump PS buffer end!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_REDUMP_L1_BUF_START": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Redump L1 buffer start!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_REDUMP_L1_BUF_END": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Redump L1 buffer end!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "TST_EX_MSG_GET_ELT_CMD": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Get one PC exception command:%Mdhl_command_type !",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_GET_ELT_CMD_CHECKSUM_ERROR": {
+ "format": "[EXC][ELT] Get one PC exception command:%Mdhl_command_type, but the checksum is incorrect! Expected checksum: %x, Got checksum: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_QUERY_MEMORY_DEUMP_INFO": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Query %MDHL_MEM_TYPE(type) to dump, result = %d!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_DUMP_MEMORY_DETAIL_INFO": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Start dump %MDHL_MEM_TYPE(type) 0X%x(address) 0X%x(length)!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "TST_EX_MSG_QUERY_SWLA_DETAIL_INFO": {
+ "apiType": "index",
+ "format": "[EXC][ELT] Query SWLA dump 0X%x(address) 0X%x(length) 0X%x(ptr)!",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_PRINT_ENTER": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Enter ex_print_mpu_setting()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_PRINT_EXIT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Exit ex_print_mpu_setting()",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_MSG": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Start to print runtime MPU setting(before entering exception).",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_SEGMENT": {
+ "apiType": "index",
+ "format": "[EXC][COMMON][MPU] Segment %3d :RI=0x%x, WI=0x%x, XI=0x%x, CCA=0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_REGION": {
+ "apiType": "index",
+ "format": "[EXC][COMMON][MPU] Region %3d :baseAddr=0x%08x, SubRegionSize=0x%08x, Enable=0x%x, SubRegionCount=0x%x, RI=0x%x, WI=0x%x, XI=0x%x, CCA=0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_MSG_DIFF": {
+ "apiType": "index",
+ "format": "[EXC][COMMON] Start to print difference of MPU setting between entering and leaving exception flow.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_SEGMENT_DIFF": {
+ "apiType": "index",
+ "format": "[EXC][COMMON][MPU][Diff] Segment %3d :RI=0x%x, WI=0x%x, XI=0x%x, CCA=0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_EXC_MPU_DUMP_REGION_DIFF": {
+ "apiType": "index",
+ "format": "[EXC][COMMON][MPU][Diff] Region %3d :baseAddr=0x%08x, SubRegionSize=0x%08x, Enable=0x%x, SubRegionCount=0x%x, RI=0x%x, WI=0x%x, XI=0x%x, CCA=0x%x.",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_ELT_NV_EDITOR_CHK_TRACE" : {
+ "format": "[@SST2ELT] file_idx: %d, access_id: %d, para: %d, result: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "SST"
+}
diff --git a/mcu/service/sst/include/cc_ex_item.h b/mcu/service/sst/include/cc_ex_item.h
new file mode 100644
index 0000000..e1f66cd
--- /dev/null
+++ b/mcu/service/sst/include/cc_ex_item.h
@@ -0,0 +1,895 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cc_ex_item.h
+ *
+ * Description:
+ * ------------
+ * Header file for cross core exception handling
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _CC_EX_ITEM_H
+#define _CC_EX_ITEM_H
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_internal_def.h"
+#include "DVFS_drv_public.h"
+#else
+//NOTE: for exLogAnalyzer.exe only. Copy it here to avoid including DVFS_drv_public
+#define DVFS_DUMP_NUM 48 /* Note: This number should also sync to EE owner.(Kari Suvanto) */
+#endif /* __OFFLINE_EX_LOG_PARSER__ */
+#include "ex_item.h"
+#include "ex_public.h"
+#include "us_excep_hdlr_format.h"
+#include "md32_excep_hdlr.h"
+#include "vc_excep_hdlr_format.h"
+#if defined(__MD97__) || defined(__MD97P__)
+#include "ex_cs_excep_hdlr_format.h"
+#endif
+#include "busmpu.h"
+#include "drv_pcmon.h"
+#include "mpu_public.h"
+#include "sst_defs.h"
+
+/*******************************************************************************
+ * Compiler Option Definition
+ *******************************************************************************/
+
+
+/*******************************************************************************
+ * Constant Definition - ex record overview
+ *******************************************************************************/
+/* total: EX_CC_LOG_SIZE */
+/***************************
+* overview * =EX_CC_OVERVIEW_SIZE
+
+**************************** mcu main info total: EX_CORE_MAIN_SIZE
+* exlog * =EX_CORE_SIZE
+
+**************************** us total: EX_USIP_SCQ_CORE_SIZE
+* us hs status * =EX_USIP_HS_STATUS_SIZE
+* us exlog * =EX_USIP_SCQ_CORE_SIZE
+
+**************************** md32 total: EX_MD32_CORE_SIZE
+* md32 hs status * =EX_MD32_HS_STATUS_SIZE
+* md32 exlog * =EX_MD32_CORE_SIZE
+
+**************************** sonic total: EX_SONIC_CORE_SIZE
+* sonic hs status * =EX_SONIC_HS_STATUS_SIZE
+* sonic exlog * =EX_SONIC_CORE_SIZE
+
+**************************** mcu minor info total: EX_CORE_MINOR_SIZE
+* nested exlog * =EX_NESTED_LOG_SIZE
+* pcmon * =EX_PCMON_SIZE
+* nested pcmon * =EX_NESTED_PCMON_SIZE
+* bus err * =EX_BUS_ERR_SIZE
+* dsm info * =EX_DSM_SIZE
+* reserved * =EX_MINOR_INFO_RESERVED_SIZE(216)
+* step logging * =EX_STEP_LOG_SIZE
+
+
+****************************/
+// EX_CC_LOG_SIZE (7*1024) //defined in ex_public.h
+
+#define EX_CC_OVERVIEW_SIZE 640
+#define EX_AFOUND_MSG_SIZE 1024
+
+
+// EX_LOG_SIZE 2560 //2.5K //defined in ex_public.h - run out
+
+#define EX_USIP_SCQ_CORE_SIZE (USIP_SCQ16_TOTAL_THREAD_NUM*100)
+#define EX_MD32_CORE_SIZE 100
+#if defined(__MD97__) || defined(__MD97P__)
+#define EX_SONIC_CORE_SIZE (EX_SONIC_TOTAL_CORE_NUM*100)
+#else
+#define EX_SONIC_CORE_SIZE 0
+#endif
+#define EX_MCU_SYSINFO_SIZE (EX_CC_LOG_SIZE-EX_AFOUND_MSG_SIZE-EX_CC_OVERVIEW_SIZE-EX_LOG_SIZE-EX_USIP_SCQ_CORE_SIZE-EX_MD32_CORE_SIZE-EX_SONIC_CORE_SIZE)
+
+
+#define EX_PCMON_SIZE 64
+#define EX_BUS_ERR_SIZE 16
+//#define EX_STEP_LOG_SIZE (sizeof(EX_STEP_T)*TOTAL_VPE_COUNT)
+
+#define EX_USIP_HS_STATUS_SIZE sizeof(kal_uint32)
+#define EX_MD32_HS_STATUS_SIZE sizeof(kal_uint32)
+#if defined(__MD97__) || defined(__MD97P__)
+#define EX_SONIC_HS_STATUS_SIZE sizeof(kal_uint32)
+#endif
+
+
+#define DSM_STATUS_COUNT 3
+#define EX_PROFILING_SET_COUNT 13
+#define EX_USIP_SCQ_CORE_USED_SIZE (sizeof(USIP_SCQ_EXCEPTION_RECORD_T)+EX_USIP_HS_STATUS_SIZE)
+#define EX_MD32_CORE_USED_SIZE (sizeof(MD32_ExceptionLog_T) +EX_MD32_HS_STATUS_SIZE)
+#if defined(__MD97__) || defined(__MD97P__)
+#define EX_SONIC_CORE_USED_SIZE (sizeof(EX_SONIC_EXCEPTION_RECORD_T)+EX_SONIC_HS_STATUS_SIZE)
+#endif
+
+
+/************************* * SYNC TIME ***************************************/
+#define EX_OFFENDING_VPE_MORE_SYNC_TIME (200000) // 0.2s
+#define EX_SYNC_DSP_FLOW_TIME (5000000) // 5s
+#define EX_INT_SYNC_TIME (5000000) // 5s
+#define EX_US_SYNC_TIME (2000000) // 2s
+#define EX_MD32_SYNC_TIME (1000000) // 1s
+#if defined(__MD97__) || defined(__MD97P__)
+#define EX_SONIC_SYNC_TIME (2000000) // 2s
+#endif
+#define EX_SAP_SYNC_TIME (4000000) // 4s
+#define EX_OP_SYNC_TIME (1000000) // 1s
+/*******************************************************************************
+ * Enum Type Definition
+ *******************************************************************************/
+
+typedef enum ex_core_t
+{
+ EX_MCU = 0,
+ EX_USIP0_0,
+ EX_USIP0_1,
+ EX_USIP1_0,
+ EX_USIP1_1,
+ EX_SCQ_0,
+ EX_SCQ_1,
+#if defined(__MD97__) || defined(__MD97P__)
+ EX_SCQ_2,
+ EX_SCQ_3,
+#endif
+ EX_RAKE,
+#if defined(__MD97__) || defined(__MD97P__)
+ EX_SONIC_M0,
+ EX_SONIC_V0,
+#endif
+ EX_CORE_AMOUNT,
+} EX_CORE_T;
+
+typedef enum ex_coretype_t
+{
+ EX_CORETYPE_MCU = 0,
+ EX_CORETYPE_USIP_SCQ,
+ EX_CORETYPE_MD32,
+#if defined(__MD97__) || defined(__MD97P__)
+ EX_CORETYPE_SONIC
+#endif
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER)
+} EX_CORETYPE_T;
+#else
+} EX_CORETYPE_T_FORMAT;
+typedef kal_uint8 EX_CORETYPE_T;
+#endif /*__OFFLINE_EX_LOG_PARSER__*/
+
+
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+typedef enum ex_flowstep_t
+{
+ /*mcu*/
+ EX_FLOWSTEP_INIT_BEGIN = 0,
+ EX_FLOWSTEP_INIT_DONE,
+ EX_FLOWSTEP_MAINREASON_INIT_DONE,
+ EX_FLOWSTEP_COMM_DONE,
+ EX_FLOWSTEP_PROCESS_DONE,
+ EX_FLOWSTEP_REBOOT_DONE,
+ /*dsp*/
+ EX_FLOWSTEP_DSPINIT_BEGIN,
+ EX_FLOWSTEP_USIPINIT_DONE,
+ EX_FLOWSTEP_MD32INIT_DONE,
+#if defined(__MD97__) || defined(__MD97P__)
+ EX_FLOWSTEP_SONICINIT_DONE,
+#endif
+ EX_FLOWSTEP_DSPINIT_DONE,
+ /*stophw*/
+ EX_FLOWSTEP_STOPHW_BEGIN,
+ EX_FLOWSTEP_STOPHW_DONE,
+ EX_FLOWSTEP_END = EX_PROFILING_SET_COUNT, /*15*/
+#if !defined(_MSC_VER)
+} EX_FLOWSTEP_T;
+#else
+} EX_FLOWSTEP_T_;
+typedef kal_uint8 EX_FLOWSTEP_T;
+#endif
+
+
+typedef enum ex_sync
+{
+ NEVER_SYNCED = 0,
+ SYNC_SUCCESS = 1,
+ SYNC_FAIL = 2,
+ NO_NEED_TO_SYNC = 3,
+ NESTED_SYNC = 4,
+} EX_SYNC;
+
+#else
+#include "ex_item_types.h"
+#endif /*__OFFLINE_EX_LOG_PARSER__*/
+
+typedef enum ex_thin_modem_sync_pattern
+{
+ THIN_MODEM_EX_HS_AP_ENTER = 0xAAAAAAAA,
+ THIN_MODEM_EX_HS_AP_DONE = 0xBBBBBBBB,
+ THIN_MODEM_EX_HS_MD_ENTER = 0xCCCCCCCC,
+ THIN_MODEM_EX_HS_MD_DONE = 0xDDDDDDDD
+} EX_THIN_MODEM_SYNC_PATTERN;
+
+
+#if defined(__MTK_TARGET__) || defined(__OFFLINE_EX_LOG_PARSER__) || defined(KAL_ON_OSCAR)
+/*******************************************************************************
+ * Data Structure Definition
+ *******************************************************************************/
+PRAGMA_BEGIN_PACK_STRUCT
+/***************************** +Debug Structure+ *******************************/
+
+typedef struct _ex_brief_assertfail_t
+{
+ kal_char filepath[EX_ASSERTFAIL_FILEPATH_LEN]; /* length: 256 */
+ kal_uint32 linenumber; /* length: 4 */
+ kal_uint32 parameters[3]; /* length: 12 */
+ kal_uint32 lr; /* length: 4 */
+} EX_BRIEF_ASSERTFAIL_T;
+
+typedef struct _ex_brief_fatalerr_t
+{
+ kal_uint32 code1;
+ kal_uint32 code2;
+ kal_uint32 code3;
+ kal_char offender[EX_FATALERR_ANALYSIS_OWNER_LEN];
+ kal_bool is_cadefa_supported;
+ kal_bool is_filename_supported;
+ kal_uint8 error_section;
+ kal_uint8 is_valid_dispatch_arg;
+ kal_uint8 pad[4];
+ kal_uint32 error_status;
+ kal_uint32 error_sp;
+ kal_uint32 error_pc;
+ kal_uint32 error_lr;
+ kal_uint32 error_address;
+ kal_uint32 error_cause;
+ kal_char filename[sizeof(EX_BRIEF_ASSERTFAIL_T) - 52];
+} EX_BRIEF_FATALERR_T;
+
+typedef union
+{
+ EX_BRIEF_FATALERR_T fatalerr;
+ EX_BRIEF_ASSERTFAIL_T assert;
+} EX_MAINCONTENT_T;
+
+typedef struct _ex_brief_maininfo_t
+{
+ kal_uint16 ex_type; /* offset: 0x, length: 2 */
+ EX_CORETYPE_T ex_type_format; //0=mcu, 1=usip|scq, 2=md32, 3=sonic
+ EX_MAINCONTENT_TYPE_T maincontent_type; //0=assert, 1=fatal
+ kal_uint8 elm_status;
+ kal_uint8 system_info1; //ex_offending_vpe_id
+ kal_uint8 system_info2; //ex_offending_tc_id
+ kal_uint8 pad;
+ EX_MAINCONTENT_T content;
+} EX_BRIEF_MAININFO_T;
+
+typedef struct ex_step_t_s
+{
+ volatile kal_uint32 step;
+ volatile kal_uint32 timestamp;
+}EX_STEP_T;
+
+#define EX_MD32_CORE_NUM 1
+#define EX_USIP_CORE_NUM (USIP_CORE_NUMBER*USIP_THREAD_NUMBER)// 4
+#define EX_SCQ_CORE_NUM (SCQ16_MAXIMUM_NUM) // 2 or 4
+#if defined(__MD97__) || defined(__MD97P__)
+# define EX_SONIC_CORE_NUM (EX_SONIC_TOTAL_CORE_NUM)// 2
+# define EX_SONIC_OFFENDING_CORE_SIZE (sizeof(kal_uint8))
+#else
+# define EX_SONIC_CORE_NUM (0)
+# define EX_SONIC_OFFENDING_CORE_SIZE (0)
+#endif
+#define EX_CORE_NUM (1+EX_USIP_CORE_NUM+EX_SCQ_CORE_NUM+EX_MD32_CORE_NUM+EX_SONIC_CORE_NUM) //mcu+usip*N+scq*N+RAKE+sonic*N
+#define EX_CORE_NAME_MAX_SIZE 11
+typedef struct _ex_main_reason_t
+{
+ kal_char core_name[EX_CORE_NAME_MAX_SIZE];
+ kal_bool is_offender;
+} EX_MAIN_REASON_T;
+
+#define EX_OVERVIEW_PAD_COMPENSATE_SIZE (\
+ /*sizeof(overview_verno)*/sizeof(kal_uint32) + \
+ /*sizeof(core_num)*/sizeof(kal_uint32) + \
+ /*sizeof(main_reason)*/sizeof(EX_MAIN_REASON_T)* EX_CORE_NUM +\
+ /*sizeof(info)*/sizeof(EX_BRIEF_MAININFO_T) +\
+ /*sizeof(mips_vpe_num)*/sizeof(kal_uint32) + \
+ /*sizeof(ex_steplog)*/sizeof(EX_STEP_T)* TOTAL_VPE_COUNT +\
+ /*sizeof(ect_status)*/sizeof(kal_uint32) + \
+ /*sizeof(afound_buffer_offset)*/sizeof(kal_uint32)+ \
+ /*sizeof(afound_buffer_size)*/sizeof(kal_uint32) + \
+ /*sizeof(usip_scq_offending_core)*/sizeof(kal_uint8) + \
+ /*sizeof(sonic_offending_core)*/EX_SONIC_OFFENDING_CORE_SIZE + \
+ /*sizeof(mcu_exception_count)*/sizeof(kal_uint8)* TOTAL_VPE_COUNT + \
+ /*sizeof(core_offset)*/sizeof(kal_uint32)* EX_CORE_NUM \
+ )
+
+typedef struct _ex_overview_t
+{
+ kal_uint32 overview_verno; // 4
+ kal_uint32 core_num; // 4 //EX_CORE_NUM
+ EX_MAIN_REASON_T main_reason[EX_CORE_NUM]; // 96 = 12*EX_CORE_NUM
+ EX_BRIEF_MAININFO_T info; // 284
+ kal_uint32 mips_vpe_num; // 4
+ volatile EX_STEP_T ex_steplog[TOTAL_VPE_COUNT]; // 48 = 8*6
+ kal_uint32 ect_status; // 4 //offending vpe
+ kal_uint32 afound_buffer_offset;
+ kal_uint32 afound_buffer_size;
+ kal_uint8 usip_scq_offending_core; // 1 usip+scq
+#if defined(__MD97__) || defined(__MD97P__)
+ kal_uint8 sonic_offending_core; // 1
+#endif
+ kal_uint8 mcu_exception_count[TOTAL_VPE_COUNT]; // 6
+ kal_uint8 pad[EX_CC_OVERVIEW_SIZE-EX_OVERVIEW_PAD_COMPENSATE_SIZE]; // 97:29 = 512-(4+4+96+284+4+48+4+1+6+32), before 97: 29 = 512-(4+4+96+284+4+48+4+1+6+32)
+ kal_uint32 core_offset[EX_CORE_NUM]; // 32 = 4*8
+} EX_OVERVIEW_T;
+
+typedef struct ex_dsm_status_t_s
+{
+ kal_uint32 DSM_load_label;
+ kal_uint32 DSM_init_label;
+ kal_uint32 DSM_loading_label;
+ kal_uint32 DSM_unloading_label;
+}EX_DSM_T;
+
+typedef struct _ex_mculog_t
+{
+ EX_LOG_T ex_log;
+} EX_MCULOG_T;
+
+typedef struct _ex_usiplog_t
+{
+ volatile kal_uint32 ex_hs;
+ USIP_SCQ_EXCEPTION_RECORD_T ex_log;
+ kal_uint32 pad[(EX_USIP_SCQ_CORE_SIZE - EX_USIP_SCQ_CORE_USED_SIZE)/ sizeof(kal_uint32)];
+} EX_USLOG_T;
+
+typedef struct _ex_md32log_t
+{
+ volatile kal_uint32 ex_hs;
+ MD32_ExceptionLog_T ex_log;
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER) //NOTE: this pad is currently zero sized and visual studio cannot handle it
+ kal_uint32 pad[(EX_MD32_CORE_SIZE - EX_MD32_CORE_USED_SIZE)/ sizeof(kal_uint32)];
+#endif
+} EX_MD32LOG_T;
+
+#if defined(__MD97__) || defined(__MD97P__)
+typedef struct _ex_soniclog_t
+{
+ volatile kal_uint32 ex_hs;
+ EX_SONIC_EXCEPTION_RECORD_T ex_log;
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER) //NOTE: this pad is currently zero sized and visual studio cannot handle it
+ kal_uint32 pad[(EX_SONIC_CORE_SIZE - EX_SONIC_CORE_USED_SIZE)/ sizeof(kal_uint32)];
+#endif
+} EX_SONICLOG_T;
+#endif
+
+typedef struct _ex_busmpu_t
+{
+ busmpu_iocu_vio_data ex_busmpu_iocu_err;
+ busmpu_irq_status ex_busmpu_irq_sts;
+#if defined(EMIMPU_MD2AP_INFODUMP_ENABLE)
+ emimpu_vio_info ex_emimpu_vio_dump;
+#else
+ kal_uint32 reserved[8]; //to keep struct size same
+#endif
+} EX_BUSMPU_T;
+
+#define PLL_INFO_NUM 48
+
+#define EX_MCU_SYSINFO_USED_SIZE ( \
+ sizeof(kal_uint32)*(EX_PROFILING_SET_COUNT) + \
+ sizeof(kal_uint32)*3 + \
+ sizeof(kal_uint32)*TOTAL_VPE_COUNT*2 + \
+ sizeof(EX_DSM_T) + \
+ sizeof(EX_NE_LOG_T) + \
+ sizeof(PDAMON_EX_RAW_T) + \
+ sizeof(PDAMON_NEX_RAW_T) + \
+ EX_BUS_ERR_SIZE + \
+ sizeof(EX_BUSMPU_T) + \
+ sizeof(kal_uint32)*(PLL_INFO_NUM) + \
+ sizeof(kal_uint32)*(DVFS_DUMP_NUM) + \
+ (sizeof(_MPU_REG)*NBR_CORE))
+
+typedef struct _ex_mcu_sysinfo_t
+{
+ kal_uint32 ex_profiling_timestamp[EX_PROFILING_SET_COUNT];
+ kal_uint32 ex_GLBTS;
+ kal_uint32 ex_sst_dc_offshoot_vpeid;
+ kal_uint32 ex_sst_hw_offshoot_vpeid;
+ kal_uint32 ex_ISR_Executing[TOTAL_VPE_COUNT]; //GSAL_GE_ISR_Executing
+ kal_uint32 ex_ect_status[TOTAL_VPE_COUNT];
+ EX_DSM_T ex_dsm_status;
+ EX_NE_LOG_T ex_nested_log;
+ PDAMON_EX_RAW_T ex_pcmon;
+ PDAMON_NEX_RAW_T ex_nested_pcmon;
+ kal_uint32 ex_buserr[EX_BUS_ERR_SIZE / sizeof(kal_uint32)];
+ EX_BUSMPU_T ex_busmpuerr;
+ kal_uint32 ex_pll_info[PLL_INFO_NUM];
+ kal_uint32 ex_DVFS_data[DVFS_DUMP_NUM];
+ _MPU_REG ex_mpu[NBR_CORE];
+ kal_uint32 pad[(EX_MCU_SYSINFO_SIZE - EX_MCU_SYSINFO_USED_SIZE)/ sizeof(kal_uint32)];
+} EX_MCU_SYSINFO_T;
+
+
+typedef struct ex_fulllog_t
+{
+ EX_OVERVIEW_T overview;
+ char afound[EX_AFOUND_MSG_SIZE];
+ EX_MCULOG_T mcu;
+ EX_USLOG_T usip_scq;
+ EX_MD32LOG_T md32;
+#if defined(__MD97__) || defined(__MD97P__)
+ EX_SONICLOG_T sonic;
+#endif
+ EX_MCU_SYSINFO_T mcu_sysinfo;
+} EX_FULLLOG_T;
+
+typedef struct ex_dump_comm_t
+{
+ volatile kal_uint32 addr;
+ volatile kal_uint32 len;
+ volatile kal_uint32 op;
+} EX_DUMP_COMM_T;
+
+
+/***************************** -Debug Structure- *******************************/
+PRAGMA_END_PACK_STRUCT
+#endif /* __MTK_TARGET__ */
+/*******************************************************************************
+ * Global Definition
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Globally Exported variables
+ *******************************************************************************/
+#if defined(__MTK_TARGET__)
+extern EX_FULLLOG_T *ex_fulllog_ptr;
+extern EX_LOG_T *ex_log_ptr; // for OfflineSST
+extern USIP_SCQ_EXCEPTION_RECORD_T *usip_scq_ex_log_ptr;
+extern MD32_ExceptionLog_T *md32_ex_log_ptr;
+extern char *afound_ptr;
+#if defined(__MD97__) || defined(__MD97P__)
+extern EX_SONIC_EXCEPTION_RECORD_T *sonic_ex_log_ptr;
+#endif
+extern EX_NE_LOG_T *ex_nested_log_ptr;
+extern PDAMON_EX_RAW_T *ex_pcmon_ptr;
+extern PDAMON_NEX_RAW_T *ex_nested_pcmon_ptr;
+extern kal_uint32 *ex_buserr_ptr;
+extern EX_DSM_T *ex_dsm_ptr;
+extern EX_BUSMPU_T *ex_busmpuerr_ptr;
+extern kal_uint32 *ex_pll_info_ptr;
+extern kal_uint32 *ex_DVFS_data;
+extern _MPU_REG *ex_mpu_ptr;
+extern volatile kal_uint32 *ex_steplog_ptr;
+extern volatile kal_uint32 *ex_md32_hs_ptr;
+#if defined(__MD97__) || defined(__MD97P__)
+extern volatile kal_uint32 *ex_sonic_hs_ptr;
+#endif
+#endif /* __MTK_TARGET__ */
+ /*******************************************************************************
+ * Globally Exported functions
+ *******************************************************************************/
+extern kal_bool INT_IsEXT_CC_COMMDone();
+extern kal_bool SST_HandleDumpRegion(kal_uint32 **address, kal_uint32* length, kal_uint32* option);
+extern kal_uint32 ex_get_step_logging(kal_uint32 vpe, kal_bool bNested);
+extern void ex_unguard_l1core_tcm();
+extern kal_uint32 ex_get_value(kal_uint32* _ptr);
+extern void ex_init_overview();
+ extern void ex_init_usip();
+extern void ex_wait_init_usip();
+extern void ex_init_md32();
+extern void ex_wait_init_md32();
+#if defined (__HIF_CCCI_SUPPORT__) && defined(__CCCI_PRODUCT_TYPE_THIN_MODEM__)
+extern void ex_sync_with_thinmodem_sap();
+#endif
+#if defined(__MD97__) || defined(__MD97P__)
+extern void ex_init_sonic();
+extern void ex_wait_init_sonic();
+#endif
+extern kal_bool ex_is_ap_triggered_cross_core_error();
+extern kal_uint32 ex_GetECTStatus();
+extern void ex_output_usip_log();
+extern void ex_output_md32_log();
+extern void ex_output_sonic_log();
+extern void ex_usip_cadefa();
+extern void ex_md32_cadefa();
+#if defined(__MD97__) || defined(__MD97P__)
+extern void ex_sonic_cadefa();
+#endif
+extern void ex_detect_dsp_version_mismatched();
+extern void ex_query_cc_ex_reason(kal_uint32 ect_status, kal_char** reason, kal_char* local_sys_info_str, kal_uint32 len);
+extern void ex_query_ap_ex_reason(kal_uint32 code1, kal_uint32 code2, kal_char** reason);
+extern void ex_ondemand_op();
+extern void ex_init_dc_offshoot();
+extern void ex_init_hw_offshoot();
+extern void ex_init_mcu_sysinfo();
+extern void ex_set_value(kal_uint32* _ptr, kal_uint32 value);
+extern kal_uint32 ex_get_value(kal_uint32* _ptr);
+#if defined(__MTK_TARGET__)
+extern void ex_set_flowstep(EX_FLOWSTEP_T step);
+#endif /* __MTK_TARGET__ */
+extern kal_char* ex_get_dsp_build_date_time(EX_CORE_T dsp_core);
+extern kal_char* ex_get_usipscq_build_date_time(EX_CORE_T dsp_core);
+extern kal_char* ex_get_rake_build_date_time(EX_CORE_T dsp_core);
+extern kal_char* ex_get_sonic_build_date_time(EX_CORE_T dsp_core);
+#endif /* _CC_EX_ITEM_H */
+
+
diff --git a/mcu/service/sst/include/coresonic_access_ctrl.h b/mcu/service/sst/include/coresonic_access_ctrl.h
new file mode 100644
index 0000000..f07db52
--- /dev/null
+++ b/mcu/service/sst/include/coresonic_access_ctrl.h
@@ -0,0 +1,100 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * coresonic_access_ctrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef CORESONIC_ACCESS_CTRL_H
+#define CORESONIC_ACCESS_CTRL_H
+
+#include "reg_base.h"
+
+#if defined(MT6763)|| defined(MT6739) || defined(MT6771)
+#else
+ #error "Please define chip comple option for Coresonic PM, ICM access control address"
+#endif
+
+#define DSPBT_C2CRF_EN_OFFSET (0x34)
+
+#define MASK_PM_ICM_ACCESS_EN (0xF)
+#define PM_ICM_ACCESS_EN (0x5)
+#define PM_ICM_ACCESS_DIS (0xF)
+
+#define WRONG_CORESONIC_C2CRF_CTRL_STATE (1)
+#define WRONG_CORESONIC_PM_ICM_CTRL_STATE (2)
+
+// DSPBT_C2CRF register bits definition
+#define C2CRF_EN (0x1)
+
+typedef struct
+{
+ kal_uint32 m_dspbt_c2crf_en;
+ kal_uint32 m_dspbt_pm_icm_access;
+}coresonic_access_ctrl_addr;
+
+#endif /* CORESONIC_ACCESS_CTRL_H */
+
diff --git a/mcu/service/sst/include/coresonic_boot.h b/mcu/service/sst/include/coresonic_boot.h
new file mode 100644
index 0000000..e8091a0
--- /dev/null
+++ b/mcu/service/sst/include/coresonic_boot.h
@@ -0,0 +1,227 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * coresonic_boot.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef CORESONIC_BOOT_H
+#define CORESONIC_BOOT_H
+
+#include "coresonic_boot_public.h"
+#include "coresonic_access_ctrl_public.h"
+
+
+typedef enum
+{
+ PM=0,
+ ICM,
+ MAX_MEM_TYPE
+}DSP_MEM_TYPE;
+
+typedef enum
+{
+ SIGNAL_LOW=0,
+ SIGNAL_HIGH
+}DSP_COMP_SIGNAL;
+
+typedef enum
+{
+ CORENAME=0,
+ PROJECT,
+ FLAVOR,
+ LABEL,
+ BUILD_TIME
+}DSP_VERSION_INFO;
+
+#define CORESONIC_HRD_BEGIN_MAGIC_NUM1 (0x32524448)
+#define CORESONIC_HRD_BEGIN_MAGIC_NUM2 (0x4E474542)
+#define CORESONIC_HRD_END_MAGIC_NUM1 (0x32524448)
+#define CORESONIC_HRD_END_MAGIC_NUM2 (0x44424545)
+
+#define MAX_KEY_NUM (4)
+
+// error code definition
+#define EXE_OK (0)
+#define READ_CORESONIC_HDR_FAILED (1)
+#define READ_CORESONIC_PM_FAILED (2)
+#define READ_CORESONIC_ICM_FAILED (3)
+#define BOOT_CORESONIC_FAILED (4)
+#define WRONG_CORESONIC_HRD_CONTENT (5)
+#define RESET_DEFAULT_VALUE_TEST_FAILED (6)
+#define WRONG_PM_ICM_LENGTH (7)
+#define WRONG_BOOT_INC_SIZE (8)
+#define WRONG_PM_WRITE_CNT (9)
+#define WRONG_ICM_WRITE_CNT (10)
+#define CHECK_PM_CRC32_FAILED (11)
+#define CHECK_ICM_CRC32_FAILED (12)
+#define BT_COMP_SIGNAL_SHOULD_BE_LOW (13)
+#define BT_COMP_SIGNAL_SHOULD_BE_HIGH (14)
+#define SET_CORESONIC_BOOT_START_FAILED (15)
+//#define WRONG_CORESONIC_C2CRF_CTRL_STATE (16)
+//#define WRONG_CORESONIC_PM_ICM_CTRL_STATE (17)
+
+#define HW_READ(ptr) (*(ptr))
+#define HW_WRITE(ptr,data) (*(ptr) = (data))
+
+typedef struct
+{
+ kal_uint32 m_pm_addr;
+ kal_uint32 m_icm_addr;
+ kal_uint32 m_dspbt_ctrl;
+ kal_uint32 m_dspbt_status;
+ kal_uint32 m_dspbt_pm_length;
+ kal_uint32 m_dspbt_icm_length;
+ kal_uint32 m_dspbt_pm_icm_length;
+ kal_uint32 m_dspbt_inc_size;
+ kal_uint32 m_dspbt_pm_crc32;
+ kal_uint32 m_dspbt_icm_crc32;
+ kal_uint32 m_dspbt_pm_read_cnt;
+ kal_uint32 m_dspbt_pm_write_cnt;
+ kal_uint32 m_dspbt_icm_read_cnt;
+ kal_uint32 m_dspbt_icm_write_cnt;
+ kal_uint32 m_dspbt_dynamic_dl;
+// kal_uint32 m_dspbt_c2crf_en;
+// kal_uint32 m_dspbt_pm_icm_access;
+ kal_uint32 m_cidd_offset;
+ kal_uint32 m_cidd_length;
+ kal_uint32 m_cidd_crc;
+ kal_uint32 m_IsVersionMismatched;
+}coresonic_reg_addr;
+
+typedef struct
+{
+ kal_uint32 m_icm_base;
+ kal_uint32 m_struct_addr;
+}coresonic_dsp_version;
+
+typedef struct
+{
+ kal_uint32 m_core_id;
+ kal_uint32 m_pm_length;
+ kal_uint32 m_pm_checksum;
+ kal_uint32 m_icm_length;
+ kal_uint32 m_icm_checksum;
+}coresonic_dsp_hdr;
+
+typedef struct
+{
+ kal_uint32 m_begin_magic_num1;
+ kal_uint32 m_begin_magic_num2;
+ kal_uint32 m_attr;
+ kal_uint32 m_coresonic_core_num;
+ coresonic_dsp_hdr m_coresonic_core[MAX_CORESONIC_NUM];
+ kal_uint32 m_end_magic_num1;
+ kal_uint32 m_end_magic_num2;
+}coresonic_hdr;
+
+typedef struct
+{
+ kal_uint32 m_cidd_core_id;
+ kal_uint32 m_cidd_pm_length;
+ kal_uint32 m_cidd_pm_checksum;
+ kal_uint32 m_cidd_pm_offset;
+ kal_uint32 m_cidd_icm_length;
+ kal_uint32 m_cidd_icm_checksum;
+ kal_uint32 m_cidd_icm_offset;
+}cidd_coresonic_dsp_hdr;
+
+typedef struct
+{
+ kal_uint32 m_begin_magic_num1;
+ kal_uint32 m_begin_magic_num2;
+ kal_uint32 m_attr;
+ kal_uint32 m_coresonic_core_num;
+ coresonic_dsp_hdr m_coresonic_core[MAX_CORESONIC_NUM];
+ cidd_coresonic_dsp_hdr m_cidd_coresonic_core[MAX_CORESONIC_NUM];
+ kal_uint32 m_end_magic_num1;
+ kal_uint32 m_end_magic_num2;
+}coresonic_hdr_suprt_cidd;
+
+typedef struct dma_gpd_s {
+ kal_uint8 hwo:1;
+ kal_uint8 bdp:1;
+ kal_uint8 bps:1;
+ kal_uint8 resv1:4;
+ kal_uint8 ioc:1;
+ kal_uint8 cksum;
+ kal_uint16 alowbufLen:16;
+ kal_uint32 nextPtr;
+ kal_uint32 bufPtr;
+ kal_uint16 bufLen;
+ kal_uint8 extLen; // TGPD : ExtensionLength, RGPD : TransferredDataBufferLength[23:16]
+ kal_uint8 bufLen2; // TGPD : DataBufferLength[23:16], RGPD : AllowDataBufferLength[23:16]
+} dma_gpd_t;
+
+typedef enum
+{
+ NONE=0,
+ XOR_CIPHER_ENABLED=1,
+ XOR_CHECKSUM_ENABLED=2,
+ SW_CIDD_ENABLED=4
+}coresonic_image_attr;
+
+#endif /* CORESONIC_BOOT_H */
diff --git a/mcu/service/sst/include/coresonic_hw.h b/mcu/service/sst/include/coresonic_hw.h
new file mode 100644
index 0000000..ba828a8
--- /dev/null
+++ b/mcu/service/sst/include/coresonic_hw.h
@@ -0,0 +1,129 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * coresonic_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef CORESONIC_HW_H
+#define CORESONIC_HW_H
+
+// DSPBT register offset definition
+#define DSPBT_CTRL_OFFSET (0x0)
+#define DSPBT_STATUS_OFFSET (0x4)
+#define DSPBT_PM_LENGTH_OFFSET (0x8)
+#define DSPBT_ICM_LENGTH_OFFSET (0xC)
+#define DSPBT_PM_ICM_LENGTH_OFFSET (0x10)
+#define DSPBT_INC_SIZE_OFFSET (0x14)
+#define DSPBT_PM_CRC32_OFFSET (0x18)
+#define DSPBT_ICM_CRC32_OFFSET (0x1C)
+#define DSPBT_PM_READ_CNT_OFFSET (0x20)
+#define DSPBT_PM_WRITE_CNT_OFFSET (0x24)
+#define DSPBT_ICM_READ_CNT_OFFSET (0x28)
+#define DSPBT_ICM_WRITE_CNT_OFFSET (0x2C)
+#define DSPBT_DYNAMIC_DL_OFFSET (0x30)
+#define DSPBT_C2CRF_EN_OFFSET (0x34)
+
+// DSPBT_CTRL register bits definition
+#define MASK_DSPBT_EN (0x1)
+#define DSPBT_EN (0x1)
+
+#define MASK_CIPHER_EN (0x2)
+#define CIPHER_EN (0x2)
+#define CIPHER_DIS (0x0)
+
+#define MASK_CIPHER_KEY_LEVEL (0x4)
+#define BASIC_CIPHER (0x0)
+#define ADV_CIPHER (0x4)
+
+#define MASK_CIPHER_KEY_SEL (0x18)
+#define CIPHER_KEY0 (0)
+#define CIPHER_KEY1 (0x8)
+#define CIPHER_KEY2 (0x10)
+#define CIPHER_KEY3 (0x18)
+
+#define MASK_BOOT_MODE (0x20)
+#define AUTO_MODE (0)
+#define MANAUAL_MODE (0x20)
+
+#define MASK_MANUAL_BOOT_CONTROL (0x40)
+#define MANUAL_BOOT_CONTROL (0x40)
+
+// DSPBT_STATUS register bits definition
+#define BOOT_START (0x1)
+#define BOOT_DONE (0x2)
+
+// DSPBT_DYNAMIC_DL register bits definition
+#define DYNDL_EN (0x1)
+
+// COSIM download by testbench
+#if defined(MT6763) || defined(MT6771)
+#else
+ #error "Please define COSIM_TESTBENCH_SYNC_DLSTART and COSIM_TESTBENCH_SYNC_DLDONE."
+#endif
+
+#endif /* CORESONIC_HW_H */
+
diff --git a/mcu/service/sst/include/cs_excep_hdlr.h b/mcu/service/sst/include/cs_excep_hdlr.h
new file mode 100644
index 0000000..09180c0
--- /dev/null
+++ b/mcu/service/sst/include/cs_excep_hdlr.h
@@ -0,0 +1,210 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dsp_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * This file provides typedefs and definiton for PS index trace.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CS_EXCEP_HDLR_H__
+#define __CS_EXCEP_HDLR_H__
+
+#include "cs_ex_hdr_public.h"
+#include "cs_excep_hdlr_format.h"
+
+#if !defined(MT6763) && !defined(MT6739) && !defined(MT6771)
+#include "kal_general_types.h"
+#include "csdebug_pctrace_api.h"
+
+// ----------------- macro definition ---------------
+#define CS_PC_TRACE_SIZE (64*2)
+
+#define CS_EXCEPTION_SYNC_TIME (0x100000) // 100 subframes
+/* sync. information with DSP core */
+#define CS_EXCEPTION_EVENT_CTI (0x1) // !!CAUTION!! MUST sync. with DSP side CTI event bit definition
+
+#define CS_EXCEPTION_PC_TRACE (0x52544350)
+
+#define CS_EXCEPTION_INFO_STR_LEN (128)
+
+/* MEMORY DUMP INFO */
+#define CS_EXCEPTION_ADDR_MAP_ICC (0x20636369)
+
+#define CS_EXCEPTION_ADDR_MAP_IMC (0x20636D69)
+
+#define CS_EXCEPTION_ADDR_MAP_MPC (0x2063706D)
+
+#define CS_EXCEPTION_ADDR_MAP_ICM (0x204D4349)
+
+#define CS_EXCEPTION_ADDR_MAP_PM (0x20204D50)
+
+#define CS_EXCEPTION_ADDR_MAP_CRF (0x20465243)
+
+#define CS_EXCEPTION_ADDR_MAP_CSIF (0x46495343)
+
+#define CS_EXCEPTION_ADDR_MAP_SSIF0 (0x30305353)
+
+#define CS_EXCEPTION_ADDR_MAP_SSIF1 (0x31305353)
+
+#define CS_EXCEPTION_ADDR_MAP_SSIF2 (0x32305353)
+
+#define CS_EXCEPTION_ADDR_MAP_HEADER (0x594D454D)
+
+#define CS_EXCEPTION_ADDR_MAP_END (0x20444E45)
+
+#define CS_EXCEPTION_MEMY_DUMP_SIZE (14) // except PM
+
+#define CS_EXCEPTION_CTI_ERROR_CODE (0x0)
+
+// ----------------- Sync step logging Definition -------------------
+#define CS_SYNC_BEGIN (0xABCD0001)
+
+#define CS_SYNC_ICC (0xABCD00AA)
+#define CS_SYNC_IMC (0xABCD00BB)
+#define CS_SYNC_MPC (0xABCD00CC)
+
+#define CS_SYNC_END (0xABCDABCD)
+
+// ------------------ bus status dump --------------------------------
+#define DBG_MMUBUS_STATUS_CONFIG (8)
+#define DBG_MMUBUS_SEL_OFFSET (0x20)
+#define DBG_MMUBUS_STAT_OFFSET (0x90)
+
+#define DBG_SMI_DUMP_CNT (3)
+#define DBG_SMI_DUMP_SIZE (16)
+#define DBG_SMI_DUMP_START_OFFSET (0x400)
+
+#define L1_BASE_MADDR_MMUSYS_BASE (0xFE712000)
+#define L1_BASE_MADDR_MMUSMI_BASE (0xFE716000)
+
+#define DBG_MMUBUS_NAME (0x20554D4D)
+#define DBG_SMI_NAME (0x20494D53)
+
+
+// ----------------- data type Definition -------------------
+typedef struct {
+ unsigned long dump_header;
+ //unsigned long pctrace_dump_data[CS_CORE_NUMBER][CS_PC_TRACE_SIZE];
+ PCTRACE_BUFFER pctrace_dump_data;
+} DSP_ASSERT_PC_TRACE_DUMP_T;
+
+typedef enum
+{
+ CoreSonic_ICC_FAIL_BIT_MASK = (1<<0),
+ CoreSonic_IMC_FAIL_BIT_MASK = (1<<1),
+ CoreSonic_MPC_FAIL_BIT_MASK = (1<<2)
+} CoreSonic_EX_CORE_BIT_MASK_TYPE;
+
+
+typedef struct {
+ unsigned long core_name;
+ unsigned long addr_name;
+ unsigned long addr_base;
+ unsigned long addr_size;
+} DSP_MEMORY_ADDR_SET_T;
+
+typedef struct {
+ unsigned long mem_header;
+ DSP_MEMORY_ADDR_SET_T mem_addr_set[CS_EXCEPTION_MEMY_DUMP_SIZE];
+ DSP_MEMORY_ADDR_SET_T mem_pm_addr_set[CS_CORE_NUMBER];
+ unsigned long mem_end;
+
+} DSP_MEMORY_ADDR_DUMP_T;
+
+typedef struct {
+
+ unsigned long dbg_mmubus_name;
+ unsigned long dbg_mmubus_status_rdata[DBG_MMUBUS_STATUS_CONFIG];
+
+ unsigned long dbg_smi_name;
+ unsigned long dbg_smi_register_status[DBG_SMI_DUMP_CNT][DBG_SMI_DUMP_SIZE];
+
+} DSP_DBG_BUS_STATUS_T;
+#endif
+
+// ----------------- function declaration -------------------
+extern void INT_GetSonicBBMemoryInfo(void);
+
+extern void INT_GetSonicDumpMemoryInfo(kal_uint32 **info, kal_uint32 *count);
+
+extern kal_bool INT_SyncSonicExceptionInfo(void);
+
+extern void INT_GetSonicExceptionRecord(CORESONIC_EXCEPTION_RECORD_T *record);
+
+extern kal_bool INT_EnableSonicMemoryDump(void);
+
+extern void INT_GetSonicBBMemoryInfo(void);
+
+
+extern kal_bool Sonic_IsSyncFinished(void);
+
+extern kal_bool Sonic_RequestEMIFlush(void);
+
+extern kal_bool Sonic_AckEMIFlushFinish(void);
+
+extern void Exception_Bring_Up_Init_ICC(void);
+
+extern void Exception_Bring_Up_Init_IMC(void);
+
+extern void Exception_Bring_Up_Init_MPC(void);
+
+extern kal_char* INT_GetCSCoreName(kal_uint32 core_index);
+
+extern kal_uint32 INT_GetSonicFailCore(void);
+extern kal_uint32 INT_GetSonicFailCoreIndex(void);
+
+#endif /* __CS_EXCEP_HDLR_H__ */
diff --git a/mcu/service/sst/include/cs_excep_hdlr_format.h b/mcu/service/sst/include/cs_excep_hdlr_format.h
new file mode 100644
index 0000000..d7defec
--- /dev/null
+++ b/mcu/service/sst/include/cs_excep_hdlr_format.h
@@ -0,0 +1,132 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dsp_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * This file provides typedefs and definiton for PS index trace.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CS_EXCEP_HDLR_FORMAT_H__
+#define __CS_EXCEP_HDLR_FORMAT_H__
+
+// ----------------- macro definition ---------------
+#define CS_CORE_NUMBER (3)
+// ----------------- data type Definition -------------------
+typedef enum {
+ CS_EXCEPTION_ASSERTION = 0x45584300,
+ CS_EXCEPTION_FATAL_ERROR,
+ CS_EXCEPTION_CTI_EVENT,
+ CS_EXCEPTION_UNKNOWN
+} CS_EXCEPTION_TYPE_T;
+
+#if defined(__GNUC__)
+typedef struct __attribute__((packed)) {
+#else
+#pragma pack(1)
+typedef struct {
+#endif // __GNUC__
+ unsigned int line_num;
+ unsigned int para1;
+ unsigned int para2;
+ unsigned int para3;
+ unsigned char file_name[64];
+} ASSERTION_INFO_T;
+#if !defined(__GNUC__)
+#pragma pack()
+#endif // __GNUC__
+
+#if defined(__GNUC__)
+typedef struct __attribute__((packed)) {
+#else
+#pragma pack(1)
+typedef struct {
+#endif // __GNUC__
+ unsigned int error_status;
+ unsigned int error_pc;
+ unsigned int error_lr;
+ unsigned int error_address;
+ unsigned int error_code1;
+ unsigned int error_code2;
+} FATAL_ERROR_INFO_T;
+#if !defined(__GNUC__)
+#pragma pack()
+#endif // __GNUC__
+
+#if defined(__GNUC__)
+typedef struct __attribute__((packed)) {
+#else
+#pragma pack(1)
+typedef struct {
+#endif
+ CS_EXCEPTION_TYPE_T except_type;
+ unsigned int except_stat;
+ union {
+ ASSERTION_INFO_T assert;
+ FATAL_ERROR_INFO_T fatal;
+ }except_content;
+} CORESONIC_EXCEPTION_INFO_T;
+#if !defined(__GNUC__)
+#pragma pack()
+#endif // __GNUC__
+
+typedef struct {
+ unsigned int core_num;
+ CORESONIC_EXCEPTION_INFO_T core_error[CS_CORE_NUMBER];
+} CORESONIC_EXCEPTION_RECORD_T;
+
+
+#endif /* __CS_EXCEP_HDLR_FORMAT_H__ */
\ No newline at end of file
diff --git a/mcu/service/sst/include/cs_trc.h b/mcu/service/sst/include/cs_trc.h
new file mode 100644
index 0000000..e60d91d
--- /dev/null
+++ b/mcu/service/sst/include/cs_trc.h
@@ -0,0 +1,108 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cs_trc.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _CS_TRC_H
+#define _CS_TRC_H
+
+ TRC_MSG(CS_EX_LOG_ASSERT, "[SONIC(%s)] Assert fail: %s -%d 0x%x, 0x%x, 0x%x")
+ TRC_MSG(CS_EX_LOG_FATAL, "[SONIC(%s)] Fatal error : code1:0x%x code2:0x%x ,Caller Address: 0x%x Product: %s Version: %s BuildTime: %s")
+ TRC_MSG(CS_EX_LOG_EXC, "[SONIC(%s)] EXCEPTION : Error_type: %s pc:0x%x lr:0x%x addr:0x%x status:0x%x")
+
+ TRC_MSG(CS_EX_LOG_PAS_DETAIL_FATAL, "[SONIC(%s)] Fatal error Detail : [Passive] error_type: %s code1:0x%x code2:0x%x pc:0x%x address:0x%x status:0x%x")
+ TRC_MSG(CS_EX_LOG_POS_DETAIL_FATAL, "[SONIC(%s)] Fatal error Detail : [Positive] code1:0x%x code2:0x%x File: %s Line: %d Para: 0x%x")
+
+ TRC_MSG(CS_EX_LOG_DEFAULT, "[SONIC(%s)] Fatal error: CTI!! (0x%x)")
+ TRC_MSG(CS_EX_LOG_BIN_BUILD_INFO, "[SONIC(%s)] Project: %s Flavor: %s BuildTime: %s Label: %s")
+
+ TRC_MSG(CS_EX_LOG_REQEMI_SYNC_FAIL, "[DSP-Coresonic] [RequestEMIFlush] SYNC flow is not finished!!! (0x%x, 0x%x, 0x%x, 0x%x)")
+ TRC_MSG(CS_EX_LOG_ACTEMI_SYNC_FAIL, "[DSP-Coresonic] [AckEMIFlushFinish] SYNC flow is not finished!!! (0x%x, 0x%x, 0x%x, 0x%x)")
+ TRC_MSG(CS_EX_LOG_DUMP_SYNC_FAIL, "[DSP-Coresonic] [INT_DumpSonicExceptionInfo] SYNC flow is not finished!!! (0x%x, 0x%x, 0x%x, 0x%x)")
+
+ TRC_MSG(CS_EX_LOG_SYNC_HS_STATUS, "[DSP-Coresonic] [INT_SyncSonicExceptionInfo] CSIF HS result: booted: 0x%x, csif_rdy: 0x%x, hs time : 0x%x")
+ TRC_MSG(CS_EX_LOG_REQEMI_HS_STATUS, "[DSP-Coresonic] [RequestEMIFlush] CSIF HS result: booted: 0x%x, csif_rdy: 0x%x, hs time : 0x%x")
+ TRC_MSG(CS_EX_LOG_ACTEMI_HS_STATUS, "[DSP-Coresonic] [AckEMIFlushFinish] CSIF HS result: booted: 0x%x, pm_wait: 0x%x, hs time : 0x%x")
+ TRC_MSG(CS_EX_LOG_REQEMI_HS_FAIL, "[SONIC(%s)] [RequestEMIFlush] CSIF HS fail (0x%x), and log may be lost")
+ TRC_MSG(CS_EX_LOG_ACTEMI_HS_FAIL, "[SONIC(%s)] [AckEMIFlushFinish] CSIF HS fail (0x%x), and log may be lost, sleep_cmd: 0x%x")
+
+ TRC_MSG(CS_EX_LOG_SYNC_FAIL_WARNING, "Modem Warning: [DSP-Coresonic] WARNING: SYNC flow is not finished!!! (0x%x, 0x%x, 0x%x)")
+
+#endif //_CS_TRC_H
+
diff --git a/mcu/service/sst/include/dsp_boot_internal.h b/mcu/service/sst/include/dsp_boot_internal.h
new file mode 100644
index 0000000..1c35b44
--- /dev/null
+++ b/mcu/service/sst/include/dsp_boot_internal.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dsp_boot_internal.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DSP_BOOT_INTERNAL_H
+#define DSP_BOOT_INTERNAL_H
+#include "dsp_boot.h"
+
+/* MD32 */
+extern kal_int32 MD32_Init();
+extern kal_int32 MD32_Load(DSP_TYPE md32_type);
+extern kal_int32 MD32_Ungate(DSP_TYPE md32_type);
+
+/* SonicCore */
+extern kal_int32 SC_Init();
+extern kal_int32 SC_Load(DSP_TYPE sc_type);
+extern kal_int32 SC_Ungate(DSP_TYPE sc_type);
+
+kal_int32 (*dsp_init[DSP_TYPE_END/DSP_TYPE_INTERVAL])(void) = { \
+ MD32_Init, \
+ SC_Init \
+};
+
+kal_int32 (*dsp_load[DSP_TYPE_END/DSP_TYPE_INTERVAL])(DSP_TYPE) = { \
+ MD32_Load, \
+ SC_Load \
+};
+
+kal_int32 (*dsp_ungate[DSP_TYPE_END/DSP_TYPE_INTERVAL])(DSP_TYPE) = { \
+ MD32_Ungate, \
+ SC_Ungate \
+};
+
+#endif
\ No newline at end of file
diff --git a/mcu/service/sst/include/dsp_cache.h b/mcu/service/sst/include/dsp_cache.h
new file mode 100644
index 0000000..cd5f60c
--- /dev/null
+++ b/mcu/service/sst/include/dsp_cache.h
@@ -0,0 +1,97 @@
+#ifndef __SVC_EX_USIP_CACHE_DUMP_H__
+#define __SVC_EX_USIP_CACHE_DUMP_H__
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+#include "dsp_cache_public.h"
+
+/*******************************************************************************
+ * USIP APB Definition
+ *******************************************************************************/
+
+#if defined(__MD97__)
+ #define USIP0_APB_BASE BASE_MADDR_USIP0_0_USIP0
+ #define USIP1_APB_BASE BASE_MADDR_USIP1_0_USIP1
+ #define USIP_APB_DBG_EN_OFFSET 0x0
+ #define USIP_APB_MODE_SEL_OFFSET 0x4
+ #define USIP_APB_DBG_INST_OFFSET 0x10
+ #define USIP_APB_DBG_EXECUTE_OFFSET 0x14
+ #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18
+ #define USIP_APB_DBG_WRITE_OFFSET 0x1c
+ #define USIP_APB_DBG_STATUS_OFFSET 0x20
+
+ #define USIP_APB_DBG_ATTACH_INST 0x900
+ #define USIP_APB_DBG_REQ_INST 0x811
+ #define USIP_APB_DBG_STATUS_INST 0x803
+ #define USIP_APB_DBG_ADDR_INST 0x801
+ #define USIP_APB_DBG_PM_LOAD_INST 0x840
+ #define USIP_APB_DBG_INSTR_INST 0x802
+ #define USIP_APB_DBG_RESUME_INST 0x812
+
+ #define USIP_CACHE_ALIGN 0x20
+#elif defined(__MD97P__)
+ #define USIP0_APB_BASE BASE_MADDR_USIP0_USIP0
+ #define USIP1_APB_BASE BASE_MADDR_USIP1_USIP1
+ #define USIP_APB_DBG_EN_OFFSET 0x0
+ #define USIP_APB_MODE_SEL_OFFSET 0x4
+ #define USIP_APB_DBG_INST_OFFSET 0x10
+ #define USIP_APB_DBG_EXECUTE_OFFSET 0x14
+ #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18
+ #define USIP_APB_DBG_WRITE_OFFSET 0x1c
+ #define USIP_APB_DBG_STATUS_OFFSET 0x20
+
+ #define USIP_APB_DBG_ATTACH_INST 0x900
+ #define USIP_APB_DBG_REQ_INST 0x811
+ #define USIP_APB_DBG_STATUS_INST 0x803
+ #define USIP_APB_DBG_ADDR_INST 0x801
+ #define USIP_APB_DBG_PM_LOAD_INST 0x840
+ #define USIP_APB_DBG_INSTR_INST 0x802
+ #define USIP_APB_DBG_RESUME_INST 0x812
+
+ #define USIP_CACHE_ALIGN 0x20
+#else
+ #error "undefined platform"
+#endif
+
+/*******************************************************************************
+ * Enum
+ *******************************************************************************/
+typedef enum {
+ EX_IABT_NONE = 0xA0000000,
+ EX_READ_USIP_IABT_PC_DONE = 0xA0000001,
+ EX_READ_USIP_IABT_PATTERN_DONE = 0xA0000010,
+ EX_ENABLE_USIP_DBG_MODE_GET_ICACHE_CONTENT_START = 0xA0000020,
+ EX_ENABLE_USIP_DBG_MODE_START = 0xA0000030,
+ EX_ENABLE_USIP_DBG_MODE_DONE = 0xA0000040,
+ EX_USIP_ICAHCE_READ_START = 0xA0000050,
+ EX_USIP_ICAHCE_READ_DONE = 0xA0000060,
+ EX_USIP_RESUME_DONE = 0xA0000070
+} EX_USIP_ICACHE_RELATED_Step_Logging_t;
+
+/*******************************************************************************
+ * Macro
+ *******************************************************************************/
+#define EX_USIP_ICACHE_LOGGING_SYNC_TIMEOUT 2000000
+#define EX_USIP_ICACHE_LOGGING_STEP_SET(sts) ex_usip_icache_logging_step = (sts)
+
+
+#if defined(__MD97__) && defined(__MTK_TARGET__)
+
+#define MCORE_CLKCTRL_ADDR 0xA40A0040
+#define VCORE_CLKCTRL_ADDR 0xA50A0040
+
+#define MCORE_DCACHE_0_CLK_ON 0x10
+#define MCORE_DCACHE_1_CLK_ON 0x20
+#define MCORE_DCACHE_2_CLK_ON 0x40
+#define MCORE_DCACHE_3_CLK_ON 0x80
+
+#define VCORE_DCACHE_0_CLK_ON 0x1
+#define VCORE_DCACHE_1_CLK_ON 0x2
+#define VCORE_DCACHE_2_CLK_ON 0x4
+#define VCORE_DCACHE_3_CLK_ON 0x8
+
+extern void nr_bb_reg_init(void);
+
+#endif //defined(__MD97__) && defined(__MTK_TARGET__)
+
+#endif
diff --git a/mcu/service/sst/include/dsp_cipher.h b/mcu/service/sst/include/dsp_cipher.h
new file mode 100644
index 0000000..a51b0ae
--- /dev/null
+++ b/mcu/service/sst/include/dsp_cipher.h
@@ -0,0 +1,93 @@
+#ifndef DSP_CIPHER_H
+#define DSP_CIPHER_H
+
+#include "kal_public_api.h"
+#include "sync_data.h"
+#include "reg_base.h"
+#define DSP_CIPHER_REG(ptr) (*(volatile kal_uint32*)(ptr))
+#define CIPHER_MAGIC 0xABCDABCD
+
+#if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6779) || defined(MT6297) || defined(MT6885) || defined(MT6873) ||defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877) || defined(__MD97P__)
+ //rake - DE: Ethan Qian (Petrus_rakesys_global_con), shijie wu
+ #define MD32_RAKE_GLOBAL_CON BASE_MADDR_RAKESYS_GLOBAL_CON
+ #define MD32_RAKE_PM_CRC (0x50)
+ #define MD32_RAKE_DM_CRC (0x54)
+
+ #if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6779)
+ #define MD32_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_MDRX_P2P_TX
+ #define SCQ_GLOBAL_CON_base BASE_MADDR_BRAM_SCQ_GLOBAL_CON
+ #elif defined(MT6297) || defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877) || defined(__MD97P__)
+ // AOCR - DE: Vincent Hu (MT6297_mdrxao_config), mercury: matthew yin
+ #define MD32_MDRXAO_MEM_CONFIG BASE_MADDR_MODEML1_AO_U_MDRXAO_CONFIG
+
+ // scq16 - DE: Playpony (MT6297_md32scq_global_con), mercury: PJ HSU
+ #define SCQ_GLOBAL_CON_base BASE_MADDR_INR0_SCQ_GLOBAL_CON
+
+ // sonic-mCore - Alex Tang
+ #if defined(MT6297)
+ #define MCORE_AO_CR_base BASE_MADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_CR
+ #elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ #define MCORE_AO_CR_base BASE_MADDR_MODEML1_AO_U_MCORE_PAR_AO_CR
+ #endif
+
+ // sonic-vCore
+ #define VCORE_AO_CR_base BASE_MADDR_VCOREAO_VCOREHRAM_PAR_AO_CR
+
+ // sonic
+ #define MCORE_CIPHER_CFG 0x0
+ #define MCORE_CIPHER_LOCK_CFG 0x4
+ #define VCORE_CIPHER_CFG 0x58
+ #define VCORE_CIPHER_LOCK_CFG 0x5C
+ #define CIPHER_KEY_SEL_OFFSET 0x4
+ #define CIPHER_EN_MASK 0x1
+ #else
+ #error "need to define address for new chip"
+ #endif
+
+ // scq16 - DE: Playpony (MT6297_md32scq_global_con), mercury: PJ HSU
+ #define SCQ_PM_CRC32_OFFSET 0x20
+ #define SCQ_DM_CRC32_OFFSET 0x24
+ // AOCR - DE: Vincent Hu (MT6297_mdrxao_config), mercury: matthew yin
+ #define MD32_RAKE_PM_CIPHER_EN 0xB0
+ #define MD32_RAKE_PM_CIPHER_LOCK 0xB4
+ #define MD32_SCQ_PM_CIPHER_EN 0xC0
+ #define MD32_SCQ_PM_CIPHER_LOCK 0xC4
+
+#else
+ #error "need to define address for new chip"
+#endif
+
+
+// rake
+extern void set_rake_pm_checksum(kal_uint32 pm_chksum);
+extern void set_rake_dm_checksum(kal_uint32 dm_chksum);
+extern kal_uint32 get_rake_pm_checksum();
+extern kal_uint32 get_rake_dm_checksum();
+extern void set_rake_cipher_en();
+extern void set_rake_cipher_lock();
+extern kal_uint32 get_rake_cipher_en();
+extern kal_uint32 get_rake_cipher_lock();
+extern void rake_cipher_en_check();
+
+// scq16
+extern void set_scq16_pm_checksum(kal_uint32 pm_chksum);
+extern void set_scq16_dm_checksum(kal_uint32 dm_chksum);
+extern kal_uint32 get_scq16_pm_checksum();
+extern kal_uint32 get_scq16_dm_checksum();
+extern void set_scq16_cipher_en();
+extern void set_scq16_cipher_lock();
+extern kal_uint32 get_scq16_cipher_en();
+extern kal_uint32 get_scq16_cipher_lock();
+extern void scq16_cipher_en_check();
+
+// sonic
+extern void set_mcore_cipher_en(kal_uint32 en_val, kal_uint32 key_sel);
+extern void set_mcore_cipher_lock();
+extern kal_uint32 get_mcore_cipher_en();
+extern kal_uint32 get_mcore_cipher_key();
+extern void set_vcore_cipher_en(kal_uint32 en_val, kal_uint32 key_sel);
+extern void set_vcore_cipher_lock();
+extern kal_uint32 get_vcore_cipher_en();
+extern kal_uint32 get_vcore_cipher_key();
+
+#endif /* DSP_CIPHER_H */
diff --git a/mcu/service/sst/include/dsp_control.h b/mcu/service/sst/include/dsp_control.h
new file mode 100644
index 0000000..f32128d
--- /dev/null
+++ b/mcu/service/sst/include/dsp_control.h
@@ -0,0 +1,401 @@
+#ifndef _DSP_CONTROL_H_
+#define _DSP_CONTROL_H_
+
+#if defined(__MD97__) || defined(__MD97P__)
+
+#include "kal_public_api.h"
+#include "dsp_control_public.h"
+#include "dsp_module_based_api_public.h"
+#include "usip_api_public.h"
+#include "rake_api_public.h"
+#include "reg_base.h"
+
+#include "dsp_header_define_cuif_inner_brp.h"
+#include "dsp_header_define_cuif_fec_wbrp.h"
+#include "dsp_header_define_cuif_speech.h"
+#include "dsp_header_define_cmif.h"
+
+/************************************/
+/************* Common ***************/
+/************************************/
+/***** Function Utility *****/
+typedef enum{
+ DSP_CTRL_FALSE,
+ DSP_CTRL_TRUE
+} DSP_CTRL_FALSE_TRUE;
+
+typedef struct{
+ kal_uint32 usip_pc;
+ kal_uint32 usip_status;
+ kal_uint32 usip_tbuf_pointer;
+ kal_uint32 usip_halt;
+} DSP_CTRL_PWR_CHECK_MEMBER;
+
+/***** Pattern Macro *****/
+#define DSP_DEACTIVE_DONE 0x62933926
+#define DSP_DEACTIVE_INIT 0x0
+#define ALL_USER_ARE_DEACTIVE DSP_CTRL_FALSE
+#define DSP_CTRL_ENABLE_CORE_INIT_VALUE 0xECECECEC
+#define DUTY_USER_INIT_PATTERN 0x10101010
+#define FIRSTBOOT_CHECK_CUIF_CONNECT_CNT_PATTERN 0x1F
+#define API_CALL_STATUS_INIT_PATTERN 0x0
+
+// uSIP debug ctrl(SW/HW CLK)
+#define USIP_TH0_PERI_CK_DIS 0x4
+#define USIP_TH0_FORCE_CK_DIS 0xC
+#define USIP_TH0_PERI_CK 0x1
+#define USIP_TH0_FORCE_CK 0xFF
+#define USIP_TH0_PERI_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_PERI_CK_DIS)
+#define USIP_TH0_FORCE_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_FORCE_CK_DIS)
+
+/***** DCM IDLE MASK*****/
+#define USIP_MASK_L1_DCM_IDLE 0x48
+#define USIP_DCM_MASK 0x793
+#define USIP_DCM_MASK_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_MASK_L1_DCM_IDLE)
+
+/***** HW Signal Access Macro *****/
+#define USIP_STATUS_CG_CHECK_MASK 0x00000001
+#define USIP_STATUS_WAITE_CHECK_MASK 0x000F0000
+#define USIP_STATUS_PWR_CHECK_BIT_OFFSET 0x00000100
+
+// SCq16 PWR CTRL COMMON
+#define BASE_SCQ16_0_CR BASE_MADDR_BRAM_SCQ0_VU_CR
+#define BASE_SCQ16_1_CR BASE_MADDR_BRAM_SCQ1_VU_CR
+#define SCQ16_MD32_WAITE_OFFSET 0x24
+#define SCQ16_CORE_FETCH_OFFSET 0x0
+
+// SCq16_0 PWR CTRL
+#define SCQ16_0_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_0_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_0_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_CORE_FETCH_OFFSET))
+
+// SCq16_1 PWR CTRL
+#define SCQ16_1_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_1_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_1_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_CORE_FETCH_OFFSET))
+
+// uSIP PWR CTRL COMMON
+#define USIP_MON_PC_OFFSET 0x20010
+#define USIP_MON_TBUF_WPTR_OFFSET 0x20014
+#define USIP_STATUS_OFFSET 0x20018
+
+// uSIP0 PWR CTRL
+#define USIP0_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP0_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP0_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
+#define USIP0_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
+
+#define USIP0_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+#define USIP0_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+
+// uSIP1 PWR CTRL
+#define USIP1_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP1_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP1_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
+#define USIP1_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
+
+#define USIP1_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+#define USIP1_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+
+// RAKE BOOTSLAVE
+#define RAKE_BOOTSLAVE_OFFSET 0xC
+#define RAKE_BOOTSLAVE_ADDR ((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
+#define RAKE_BOOTSLAVE *((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
+
+// USIP sram type setting
+
+#define USIP_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF))
+#define USIP_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF))
+#define USIP_SRAM_TYPE_MASK 0x3
+
+
+//SCQ sram type setting
+#define SCQ_SRAM_TYPE_OFFSET 0x4
+#define SCQ_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
+#define SCQ_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
+#define SCQ_SRAM_TYPE_MASK 0x7FF
+
+//RAKE sram type setting
+#define RAKE_SRAM_TYPE_OFFSET 0x10
+#define RAKE_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
+#define RAKE_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
+#define RAKE_SRAM_TYPE_MASK 0xFF
+/***** Function Macro *****/
+
+/***** Enum *****/
+typedef enum{
+ DSP_CTRL_ABORT,
+ DSP_CTRL_DORMANT
+} DSP_CTRL_IRQ_TYPE;
+
+typedef enum{
+ DSP_CTRL_ACTIVATE_ACTION = 0x0,
+ DSP_CTRL_ACTIVATE_ACTION_AFTER_HWITC = 0x1,
+ DSP_CTRL_ACTIVATE_CHECK_ACTION = 0x4,
+ DSP_CTRL_DEACTIVATE_ACTION = 0x8,
+ DSP_CTRL_DEACTIVATE_ACTION_AFTER_HWITC = 0x9,
+ DSP_CTRL_DEACTIVATE_CHECK_ACTION = 0xC,
+ DSP_CTRL_ACTION_NUM = 0x4
+} DSP_CTRL_ACTION_CODE;
+
+#define DSP_CTRL_ACTIVATE_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_ACTION)
+#define DSP_CTRL_ACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_CHECK_ACTION)
+#define DSP_CTRL_DEACTIVATE_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_ACTION)
+#define DSP_CTRL_DEACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_CHECK_ACTION)
+
+
+#define USIP_TH0_PERI_CK_EN_OFFSET (0x0)
+#define USIP_TH0_PERI_CK_DIS_OFFSET (0x4)
+#define USIP_TH0_FORCE_CK_EN_OFFSET (0x8)
+#define USIP_TH0_FORCE_CK_DIS_OFFSET (0xC)
+
+
+/************************************/
+/************* uSIP *****************/
+/************************************/
+
+/*****cosim only API****/
+void usip_boot(void);
+void usip_power_aware(void);
+void usip_peripheral_clock_enable(kal_uint32);
+void usip_peripheral_clock_disable(kal_uint32);
+void usip_peripheral_clock_force_enable(kal_uint32);
+void usip_peripheral_clock_force_disable(kal_uint32);
+
+DSP_CONTROL_STATUS usip0_thread0_boot_done_check(void);
+DSP_CONTROL_STATUS usip0_thread1_boot_done_check(void);
+DSP_CONTROL_STATUS usip1_thread0_boot_done_check(void);
+
+void rake_ungate(void);
+DSP_CONTROL_STATUS rake_boot_done_check(void);
+
+
+
+/************************************/
+/************* RAKE *****************/
+/************************************/
+#define RAKE_CMIF_BASE_ADDR BASE_MADDR_RAKESYS_CMIF
+#define RAKE_WFI_MASK_OFFSET 0x4
+
+/***** Common API *****/
+
+
+
+
+/************************************/
+/********* module-based APIs ********/
+/************************************/
+#undef L1_MODULE_REGISTER
+#define L1_MODULE_REGISTER(name, wfi, firmware, cb) extern void cb(void);
+
+ #include "L1_module_registration.h"
+
+#undef L1_MODULE_REGISTER
+
+void usip_activate_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION, kal_uint32);
+void rake_activate_by_module(L1_MODULE_REGISTRATION, kal_uint32);
+DSP_CONTROL_STATUS usip_activate_done_check_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION);
+DSP_CONTROL_STATUS rake_activate_done_check_by_module(L1_MODULE_REGISTRATION);
+void usip_deactivate_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION, kal_uint32);
+void rake_deactivate_by_module(L1_MODULE_REGISTRATION, kal_uint32);
+DSP_CONTROL_STATUS usip_deactivate_done_check_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION);
+DSP_CONTROL_STATUS rake_deactivate_done_check_by_module(L1_MODULE_REGISTRATION);
+DSP_CONTROL_IDLE_FLAG_STATUS usip_check_idle_flag_by_module(DSP_CDIF_CORE_ENUM, DSP_FIRMWARE_REGISTRATION);
+DSP_CONTROL_IDLE_FLAG_STATUS rake_check_idle_flag_by_module(DSP_CDIF_CORE_ENUM, DSP_FIRMWARE_REGISTRATION);
+void execute_deactivate_irq_cb(L1_MODULE_REGISTRATION);
+
+void dsp_firstboot_activate_by_module(kal_uint32);
+void dsp_activate_by_module(kal_uint32);
+DSP_CONTROL_STATUS dsp_activate_done_check_by_module(kal_uint32);
+void dsp_deactivate_by_module(kal_uint32);
+DSP_CONTROL_STATUS dsp_deactivate_done_check_by_module(kal_uint32);
+kal_uint32 dsp_check_idle_flag_by_module(kal_uint32);
+kal_uint32 dsp_check_idle_flag_by_firmware(kal_uint32);
+
+#else //defined(__MD97__) || defined(__MD97P__)
+/************************************__MD95__*********************************/
+
+#include "kal_public_api.h"
+#include "dsp_control_public.h"
+#include "usip_api_public.h"
+#include "rake_api_public.h"
+#include "reg_base.h"
+
+#include "dsp_header_define_cuif_inner_brp.h"
+#include "dsp_header_define_cuif_fec_wbrp.h"
+#include "dsp_header_define_cuif_speech.h"
+#include "dsp_header_define_cmif.h"
+
+/************************************/
+/************* Common ***************/
+/************************************/
+/***** Function Utility *****/
+typedef enum{
+ DSP_CTRL_FALSE,
+ DSP_CTRL_TRUE
+} DSP_CTRL_FALSE_TRUE;
+
+typedef struct{
+ kal_uint32 usip_pc;
+ kal_uint32 usip_status;
+ kal_uint32 usip_tbuf_pointer;
+ kal_uint32 usip_halt;
+} DSP_CTRL_PWR_CHECK_MEMBER;
+
+/***** Pattern Macro *****/
+#define DSP_DEACTIVE_DONE 0x62933926
+#define DSP_DEACTIVE_INIT 0x0
+#define ALL_USER_ARE_DEACTIVE DSP_CTRL_FALSE
+#define DSP_CTRL_ENABLE_CORE_INIT_VALUE 0xECECECEC
+#define DUTY_USER_INIT_PATTERN 0x10101010
+#define FIRSTBOOT_CHECK_CUIF_CONNECT_CNT_PATTERN 0x1F
+#define API_CALL_STATUS_INIT_PATTERN 0x0
+
+// uSIP debug ctrl(SW/HW CLK)
+#define USIP_TH0_PERI_CK_DIS 0x4
+#define USIP_TH0_FORCE_CK_DIS 0xC
+#define USIP_TH0_FORCE_CK_EN 0x8
+#define USIP_TH0_PERI_CK 0x1
+#define USIP_TH0_FORCE_CK 0xFF
+#define USIP_DISABLE_ALL_FORCE_ON_CK 0xFFFF
+#define USIP_ENABLE_FORCE_ON_CK 0xFC1C
+#define USIP_TH0_PERI_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_PERI_CK_DIS)
+#define USIP_TH0_FORCE_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_FORCE_CK_DIS)
+#define USIP_ENABLE_FORCE_ON_CK_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_FORCE_CK_EN)
+
+/***** DCM IDLE MASK*****/
+#define USIP_MASK_L1_DCM_IDLE 0x48
+#if defined(__MD93__)
+#define USIP_DCM_MASK 0x19f
+#elif defined(__MD95__)
+#define USIP_DCM_MASK 0x193
+#else
+#error "not support chip!! Please porting for it!!"
+#endif
+#define USIP_DCM_MASK_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_MASK_L1_DCM_IDLE)
+
+/***** HW Signal Access Macro *****/
+#define USIP_STATUS_CG_CHECK_MASK 0x00000001
+#define USIP_STATUS_WAITE_CHECK_MASK 0x000F0000
+#define USIP_STATUS_PWR_CHECK_BIT_OFFSET 0x00000100
+
+// SCq16 PWR CTRL COMMON
+#define BASE_SCQ16_0_CR BASE_MADDR_BRAM_SCQ0_VU_CR
+#define BASE_SCQ16_1_CR BASE_MADDR_BRAM_SCQ1_VU_CR
+#define SCQ16_MD32_WAITE_OFFSET 0x24
+#define SCQ16_CORE_FETCH_OFFSET 0x0
+
+// SCq16_0 PWR CTRL
+#define SCQ16_0_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_0_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_0_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_CORE_FETCH_OFFSET))
+
+// SCq16_1 PWR CTRL
+#define SCQ16_1_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_1_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
+#define SCQ16_1_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_CORE_FETCH_OFFSET))
+
+// uSIP PWR CTRL COMMON
+#define USIP_MON_PC_OFFSET 0x20010
+#define USIP_MON_TBUF_WPTR_OFFSET 0x20014
+#define USIP_STATUS_OFFSET 0x20018
+
+// uSIP0 PWR CTRL
+#define USIP0_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP0_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP0_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
+#define USIP0_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
+
+#define USIP0_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+#define USIP0_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+
+// uSIP1 PWR CTRL
+#define USIP1_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP1_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
+#define USIP1_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
+#define USIP1_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
+
+#define USIP1_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+#define USIP1_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
+
+// RAKE BOOTSLAVE
+#define RAKE_BOOTSLAVE_OFFSET 0xC
+#define RAKE_BOOTSLAVE_ADDR ((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
+#define RAKE_BOOTSLAVE *((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
+
+// USIP sram type setting
+#define USIP_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDPERI_USIP0_MEM_CONFIG))
+#define USIP_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MDPERI_USIP0_MEM_CONFIG))
+#define USIP_SRAM_TYPE_MASK 0x3
+
+//SCQ sram type setting
+#define SCQ_SRAM_TYPE_OFFSET 0x4
+#define SCQ_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
+#define SCQ_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
+#define SCQ_SRAM_TYPE_MASK 0x7FF
+
+//RAKE sram type setting
+#define RAKE_SRAM_TYPE_OFFSET 0x10
+#define RAKE_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
+#define RAKE_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
+#define RAKE_SRAM_TYPE_MASK 0xFF
+/***** Function Macro *****/
+
+/***** Enum *****/
+typedef enum{
+ DSP_CTRL_ABORT,
+ DSP_CTRL_DORMANT
+} DSP_CTRL_IRQ_TYPE;
+
+typedef enum{
+ DSP_CTRL_ACTIVATE_ACTION = 0x0,
+ DSP_CTRL_ACTIVATE_ACTION_AFTER_HWITC = 0x1,
+ DSP_CTRL_ACTIVATE_CHECK_ACTION = 0x4,
+ DSP_CTRL_DEACTIVATE_ACTION = 0x8,
+ DSP_CTRL_DEACTIVATE_ACTION_AFTER_HWITC = 0x9,
+ DSP_CTRL_DEACTIVATE_CHECK_ACTION = 0xC,
+ DSP_CTRL_ACTION_NUM = 0x4
+} DSP_CTRL_ACTION_CODE;
+
+#define DSP_CTRL_ACTIVATE_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_ACTION)
+#define DSP_CTRL_ACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_CHECK_ACTION)
+#define DSP_CTRL_DEACTIVATE_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_ACTION)
+#define DSP_CTRL_DEACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_CHECK_ACTION)
+
+/************************************/
+/************* uSIP *****************/
+/************************************/
+
+/***** Common API *****/
+DSP_CONTROL_IDLE_FLAG_STATUS usip_check_idle_flag(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***** Activate Relatives *****/
+void usip_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+/***** Deactivate Relatives *****/
+void usip_deactivate(DSP_CDIF_CORE_ENUM, kal_uint32);
+USIP_CONTROL_STATUS usip_deactive_done_check(DSP_CDIF_CORE_ENUM, kal_uint32);
+
+
+/************************************/
+/************* RAKE *****************/
+/************************************/
+#define RAKE_CMIF_BASE_ADDR BASE_MADDR_RAKESYS_CMIF
+#define RAKE_WFI_MASK_OFFSET 0x4
+
+/***** Common API *****/
+DSP_CONTROL_IDLE_FLAG_STATUS rake_check_idle_flag(RAKE_API_USER);
+
+/***** Activate Relatives *****/
+void rake_activate(RAKE_API_USER);
+
+/***** Deactivate Relatives *****/
+void rake_deactivate(RAKE_API_USER, CMIFZI_CTRL);
+RAKE_CONTROL_STATUS rake_deactive_done_check(RAKE_API_USER);
+
+/* Check Boot Done API*/
+RAKE_BOOTDONECHECK_RETVALUE RAKE_BootDoneCheck(RAKE_API_USER);
+
+#endif //defined(__MD97__) || defined(__MD97P__)
+#endif
+
diff --git a/mcu/service/sst/include/dsp_dbg_ctrl.h b/mcu/service/sst/include/dsp_dbg_ctrl.h
new file mode 100644
index 0000000..17a89d2
--- /dev/null
+++ b/mcu/service/sst/include/dsp_dbg_ctrl.h
@@ -0,0 +1,47 @@
+#ifndef __SVC_DSP_DEBUG_CONTROL_H__
+#define __SVC_DSP_DEBUG_CONTROL_H__
+
+#include "drv_comm.h"
+#include "reg_base.h"
+
+/*******************************************************************************
+ * SCQ DBG APB CR Definition
+ *******************************************************************************/
+#if defined(__MD93__) || defined(__MD95__)
+#define SCQ0_APB_BASE (BASE_MADDR_MDPERI_MD_DBGSYS2 + 0xC000)
+#define SCQ1_APB_BASE (BASE_MADDR_MDPERI_MD_DBGSYS2 + 0xD000)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define SCQ0_APB_BASE (BASE_MADDR_VDSP_1_MD32SCQ)
+#define SCQ1_APB_BASE (BASE_MADDR_VDSP_2_MD32SCQ)
+#define SCQ2_APB_BASE (BASE_MADDR_VDSP_3_MD32SCQ)
+#define SCQ3_APB_BASE (BASE_MADDR_VDSP_4_MD32SCQ)
+#else
+ #error "Unsupported project!!"
+#endif
+
+/*******************************************************************************
+ * MACRO Definition
+ *******************************************************************************/
+#define SCQ_APB_DBG_EN_OFFSET 0x0
+#define SCQ_APB_MODE_SEL_OFFSET 0x4
+#define SCQ_APB_DBG_INST_OFFSET 0x10
+#define SCQ_APB_DBG_EXECUTE_OFFSET 0x14
+
+#if defined(__MD93__) || defined(__MD95__)
+#define SCQ_APB_DBG_STATUS_OFFSET 0x20
+#elif defined (__MD97__) || defined(__MD97P__)
+#define SCQ_APB_DBG_STATUS_OFFSET 0x24
+#else
+ #error "Unsupported project!!"
+#endif
+
+#define SCQ_APB_DBG_ATTACH_INST 0x900
+#define SCQ_APB_DBG_REQ_INST 0x811
+#define SCQ_APB_DBG_STATUS_INST 0x803
+#define SCQ_APB_DBG_RESUME_INST 0x812
+
+#if defined(__SCQ16_SUPPORT_CTI_RESTART__)
+ /* TODO: Add code for 97 CTI restart when HW ready */
+#endif
+
+#endif
diff --git a/mcu/service/sst/include/dsp_dbgc.h b/mcu/service/sst/include/dsp_dbgc.h
new file mode 100644
index 0000000..73cd52e
--- /dev/null
+++ b/mcu/service/sst/include/dsp_dbgc.h
@@ -0,0 +1,24 @@
+#ifndef __DSP_DBGC_H__
+#define __DSP_DBGC_H__
+
+
+#if defined(__MD97__)
+#include "kal_public_api.h"
+#include "sync_data.h"
+#include "reg_base.h"
+
+#define DSP_DBGC_REG(ptr) (*(volatile kal_uint32*)(ptr))
+
+#define DBGC_BASE (BASE_MADDR_MCORE0_DBGC)
+#define DBGC_IDLE_SIGNAL_SET_REG (DBGC_BASE + 0x1C4)
+#define DBGC_IDLE_SIGNAL_CLR_REG (DBGC_BASE + 0x1C8)
+#define DBGC_IDLE_SIGNAL_STATUS_REG (DBGC_BASE + 0x1CC)
+#define DSP_MCORE_THREAD_NUMBER (0x4)
+
+
+#else /* Not MD97 */
+
+// let it empty, because only MD97 has the DBGC module
+#endif
+
+#endif /* __DSP_DBGC_H__ */
diff --git a/mcu/service/sst/include/dsp_eintc.h b/mcu/service/sst/include/dsp_eintc.h
new file mode 100644
index 0000000..8ab4451
--- /dev/null
+++ b/mcu/service/sst/include/dsp_eintc.h
@@ -0,0 +1,21 @@
+#ifndef DSP_EINTC_H
+#define DSP_EINTC_H
+
+#include "kal_public_api.h"
+#include "sync_data.h"
+#include "reg_base.h"
+#define DSP_EINTC_REG(ptr) (*(volatile kal_uint32*)(ptr))
+
+#if defined(MT6297) || defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ #define EINTC_BASE BASE_MADDR_MCORE0_EINTC
+ #define EINTC_SET_IDLE_SIGNAL 0x1C4
+ #define EINTC_CLR_IDLE_SIGNAL 0x1C8
+ #define EINTC_IDLE_SIGNAL_STATUS 0x1CC
+ #define DSP_MCORE_THREAD_NUMBER 0x4
+#elif defined(__MD95__)
+#else
+ #error "need to define address for new chip"
+#endif
+
+
+#endif /* DSP_EINTC_H */
diff --git a/mcu/service/sst/include/dsp_excep_def.h b/mcu/service/sst/include/dsp_excep_def.h
new file mode 100644
index 0000000..5246a32
--- /dev/null
+++ b/mcu/service/sst/include/dsp_excep_def.h
@@ -0,0 +1,25 @@
+#ifndef __DSP_EXCEP_DEF_H__
+#define __DSP_EXCEP_DEF_H__
+
+#if defined(MT6771) || defined(MT6295M) || defined(MT3967) || defined(MT6779) || defined(MT6297) || defined(MT6885) || defined(__MD97__) || defined(__MD97P__)
+typedef enum{
+ DSP_COMMON_REGION,
+ BRP_LTE_ROCODE,
+ BRP_FDD_ROCODE,
+ FEC_TX_C2K_ROCODE,
+ FEC_TX_WCDMA_ROCODE,
+ FEC_TX_LTE_ROCODE,
+ FEC_RX_C2K_ROCODE,
+ FEC_RX_WCDMA_ROCODE,
+ SCQ16_LTE_ROCODE,
+ SCQ16_FDD_ROCODE,
+ SCQ16_TDD_ROCODE,
+ SCQ16_C2K_ROCODE,
+ RAKE_FDD_ROCODE,
+ RAKE_C2K_ROCODE
+}DSP_EX_DDL_MODE;
+#else
+ #error "Undefined project name..."
+#endif
+
+#endif /* __DSP_EXCEP_DEF_H__ */
diff --git a/mcu/service/sst/include/dsp_file.h b/mcu/service/sst/include/dsp_file.h
new file mode 100644
index 0000000..d76721b
--- /dev/null
+++ b/mcu/service/sst/include/dsp_file.h
@@ -0,0 +1,142 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dsp_file.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files.
+ *******************************************************************************/
+#ifndef DSP_FILE_H
+#define DSP_FILE_H
+//#include "md32_file.h"
+#include "md32_bin_info.h"
+
+
+
+
+
+
+
+#ifndef __DSP_PBP__
+#include "kal_general_types.h"
+
+kal_uint32 dsp_fread(kal_uint32 *buf, kal_uint32 off, kal_uint32 len, DSP_TYPE type);
+kal_uint32 dsp_fwrite(kal_uint32 *buf, kal_uint32 off, kal_uint32 len, DSP_TYPE type);
+kal_uint32 *get_dsp_ptr(kal_uint32 off, DSP_TYPE type);
+kal_uint32 dsp_chksum(kal_uint32 off, kal_uint32 len, DSP_TYPE type);
+kal_uint32 cal_chksum(kal_uint32 base, kal_uint32 len);
+kal_bool dsp_exst();
+kal_uint32 get_msonic_ex_log_addr();
+kal_uint32 get_vsonic_ex_log_addr();
+
+/* if the following enum changes, we need to sync with DE */
+typedef enum{
+ BRP_PM,
+ BRP_DM,
+ DFE_PM,
+ DFE_DM,
+ RAKE_PM,
+ RAKE_DM,
+
+ ICC_PM = 0x1000,
+ ICC_ICM,
+ IMC_PM,
+ IMC_ICM,
+ MPC_PM,
+ MPC_ICM,
+} DSP_DEST_MEM;
+
+/* if the following enum changes, we need to change the file name index mapping table file */
+typedef enum{
+ BRP_PM_DAT,
+ BRP_DM_DAT,
+ DFE_PM_DAT,
+ DFE_DM_DAT,
+ RAKE_PM_DAT,
+ RAKE_DM_DAT,
+ BRP_COM_PM_DAT,
+ BRP_COM_DM_DAT,
+ BRP_FDD_PM_DAT,
+ BRP_FDD_DM_DAT,
+ BRP_TDD_PM_DAT,
+ BRP_TDD_DM_DAT,
+ BRP_LTE_PM_DAT,
+ BRP_LTE_DM_DAT,
+
+ ICC_PM_DAT = 0x1000,
+ ICC_ICM_DAT,
+ IMC_PM_DAT,
+ IMC_ICM_DAT,
+ MPC_PM_DAT,
+ MPC_ICM_DAT,
+} DSP_HEX_FILE_IDX;
+
+kal_uint32 dsp_backdoor_download(DSP_DEST_MEM dest, kal_uint32 offset, \
+ DSP_HEX_FILE_IDX file_index);
+
+
+#endif /* DSP_PBP */
+
+#endif /* DSP_FILE_H */
diff --git a/mcu/service/sst/include/ex_BEE_trc.h b/mcu/service/sst/include/ex_BEE_trc.h
new file mode 100644
index 0000000..c899ce9
--- /dev/null
+++ b/mcu/service/sst/include/ex_BEE_trc.h
@@ -0,0 +1,388 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_handler_trc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines exception debugging trace.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+ TRC_MSG(SST_EXC_WATCHDOG_RESET_ENTER, "[EXC][COMMON] Enter Watchdog reset")
+ TRC_MSG(SST_EXC_WATCHDOG_RESET_EXIT, "[EXC][COMMON] Exit Watchdog reset")
+
+ TRC_MSG(SST_EXC_WATCHDOG_RESET_EH_ENTER, "[EXC][COMMON]%s Enter Watchdog reset")
+ TRC_MSG(SST_EXC_WATCHDOG_RESET_EH_EXIT, "[EXC][COMMON]%s Exit Watchdog reset")
+
+ TRC_MSG(SST_EXC_WATCHDOG_DISABLE_ENTER, "[EXC][COMMON] Enter Watchdog disable")
+ TRC_MSG(SST_EXC_WATCHDOG_DISABLE_EXIT, "[EXC][COMMON] Exit Watchdog disable")
+
+ TRC_MSG(SST_EXC_FLUSH_LOGGING_PORT_EXIT, "[EXC][COMMON] Exit dhl_flush_logging_port_for_exception()")
+ TRC_MSG(SST_EXC_NE_FLUSH_LOGGING_PORT_EXIT, "[EXC][COMMON][Nested] Exit dhl_flush_logging_port_for_exception()")
+
+ TRC_MSG(SST_EXC_CCCI_HANDSHAKING_ENTER, "[EXC][COMMON] Enter ccci_exception_handshake()")
+ TRC_MSG(SST_EXC_CCCI_HANDSHAKING_EXIT, "[EXC][COMMON] Exit ccci_exception_handshake()")
+
+ TRC_MSG(SST_EXC_RESET_HARDWARE_ENTER, "[EXC][COMMON] Enter ex_reset_hw()")
+ TRC_MSG(SST_EXC_RESET_HARDWARE_EXIT, "[EXC][COMMON] Exit ex_reset_hw()")
+
+ TRC_MSG(SST_EXC_TL1_FORCESTALL_ENTER, "[EXC][COMMON] Enter TL1_ForceStall()")
+ TRC_MSG(SST_EXC_TL1_FORCESTALL_EXIT, "[EXC][COMMON] Exit TL1_ForceStall()")
+
+ TRC_MSG(SST_EXC_L1D_PAUSEDSP_ENTER, "[EXC][COMMON] Enter L1D_PauseDSP()")
+ TRC_MSG(SST_EXC_L1D_PAUSEDSP_EXIT, "[EXC][COMMON] Exit L1D_PauseDSP()")
+
+ TRC_MSG(SST_EXC_L1AUDIO_RESETDEVICE_ENTER, "[EXC][COMMON] Enter L1Audio_ResetDevice()")
+ TRC_MSG(SST_EXC_L1AUDIO_RESETDEVICE_EXIT, "[EXC][COMMON] Exit L1Audio_ResetDevice()")
+
+ TRC_MSG(SST_EXC_DUMP_SLAVE_LOG_ENTER, "[EXC][COMMON] Enter dhl_cc_exception_dump_slave_log()")
+ TRC_MSG(SST_EXC_DUMP_SLAVE_LOG_EXIT, "[EXC][COMMON] Exit dhl_cc_exception_dump_slave_log()")
+ TRC_MSG(SST_EXC_NE_DUMP_SLAVE_LOG_ENTER, "[EXC][COMMON][Nested] Enter dhl_cc_exception_dump_slave_log()")
+ TRC_MSG(SST_EXC_NE_DUMP_SLAVE_LOG_EXIT, "[EXC][COMMON][Nested] Exit dhl_cc_exception_dump_slave_log()")
+
+ TRC_MSG(SST_EXC_HS_ENTER, "[EXC][COMMON] Enter ex_int_cc_handshake(%d)")
+ TRC_MSG(SST_EXC_HS_EXIT, "[EXC][COMMON] Exit ex_int_cc_handshake(%d)")
+
+ TRC_MSG(SST_EXC_OUTPUT_CADEFA_ENTER, "[EXC][COMMON] Enter ex_cadefa()")
+ TRC_MSG(SST_EXC_OUTPUT_CADEFA_EXIT, "[EXC][COMMON] Exit ex_cadefa()")
+
+ TRC_MSG(SST_EXC_OUTPUT_USIP_CADEFA_ENTER, "[EXC][COMMON] Enter ex_usip_cadefa()")
+ TRC_MSG(SST_EXC_OUTPUT_USIP_CADEFA_EXIT, "[EXC][COMMON] Exit ex_usip_cadefa()")
+
+ TRC_MSG(SST_EXC_OUTPUT_MD32_CADEFA_ENTER, "[EXC][COMMON] Enter ex_md32_cadefa()")
+ TRC_MSG(SST_EXC_OUTPUT_MD32_CADEFA_EXIT, "[EXC][COMMON] Exit ex_md32_cadefa()")
+
+ TRC_MSG(SST_EXC_OUTPUT_SCQ_CADEFA_ENTER, "[EXC][COMMON] Enter ex_scq_cadefa()")
+ TRC_MSG(SST_EXC_OUTPUT_SCQ_CADEFA_EXIT, "[EXC][COMMON] Exit ex_scq_cadefa()")
+
+ TRC_MSG(SST_EXC_OUTPUT_SONIC_CADEFA_ENTER, "[EXC][COMMON] Enter ex_sonic_cadefa()")
+ TRC_MSG(SST_EXC_OUTPUT_SONIC_CADEFA_EXIT, "[EXC][COMMON] Exit ex_sonic_cadefa()")
+
+ TRC_MSG(SST_EXC_INVOKE_SST_ENGINE_ENTER, "[EXC][COMMON] Enter INT_InvokeSSTEngine()")
+ TRC_MSG(SST_EXC_INVOKE_SST_ENGINE_EXIT, "[EXC][COMMON] Exit INT_InvokeSSTEngine()")
+
+ TRC_MSG(SST_EXC_EMM_WRITE_EX_RECORD_ENTER, "[EXC][COMMON] Enter EMM_Write_ExceptRecord()")
+ TRC_MSG(SST_EXC_EMM_WRITE_EX_RECORD_EXIT, "[EXC][COMMON] Exit EMM_Write_ExceptRecord()")
+
+ TRC_MSG(SST_EXC_SWLA_PRINT_LOWRAM_ENTER, "[EXC][COMMON] Enter SLA_Print_low_RAM_SWLA()")
+ TRC_MSG(SST_EXC_SWLA_PRINT_LOWRAM_EXIT, "[EXC][COMMON] Exit SLA_Print_low_RAM_SWLA()")
+
+ TRC_MSG(SST_EXC_OUTPUT_EXCEPTION_RECORD_ENTER, "[EXC][COMMON] Enter ex_output_log()")
+ TRC_MSG(SST_EXC_OUTPUT_EXCEPTION_RECORD_EXIT, "[EXC][COMMON] Exit ex_output_log()")
+
+ TRC_MSG(SST_EXC_OUTPUT_USIP_EXCEPTION_RECORD_ENTER, "[EXC][COMMON] Enter ex_output_usip_log()")
+ TRC_MSG(SST_EXC_OUTPUT_USIP_HS_FAILED, "usip HS failed [%d]")
+ TRC_MSG(SST_EXC_OUTPUT_USIP_EXCEPTION_RECORD_EXIT, "[EXC][COMMON] Exit ex_output_usip_log()")
+
+ TRC_MSG(SST_EXC_OUTPUT_MD32_EXCEPTION_RECORD_ENTER, "[EXC][COMMON] Enter ex_output_md32_log()")
+ TRC_MSG(SST_EXC_OUTPUT_MD32_HS_FAILED, "md32 HS failed [%d]")
+ TRC_MSG(SST_EXC_OUTPUT_MD32_EXCEPTION_RECORD_EXIT, "[EXC][COMMON] Exit ex_output_md32_log()")
+
+ TRC_MSG(SST_EXC_OUTPUT_SONIC_EXCEPTION_RECORD_ENTER, "[EXC][COMMON] Enter ex_output_sonic_log()")
+ TRC_MSG(SST_EXC_OUTPUT_SONIC_HS_FAILED, "sonic HS failed [%d]")
+ TRC_MSG(SST_EXC_OUTPUT_SONIC_EXCEPTION_RECORD_EXIT, "[EXC][COMMON] Exit ex_output_sonic_log()")
+
+ TRC_MSG(SST_EXC_PASS_CCCI_EXCINFO_ENTER, "[EXC][COMMON] Enter ccci_exception_info_passed()")
+ TRC_MSG(SST_EXC_PASS_CCCI_EXCINFO_EXIT, "[EXC][COMMON] Exit ccci_exception_info_passed()")
+
+ TRC_MSG(SST_EXC_FLC_DEBUG_INFO_ENTER, "[EXC][COMMON] Enter flc2_debug_assert_callback()")
+ TRC_MSG(SST_EXC_FLC_DEBUG_INFO_EXIT, "[EXC][COMMON] Exit flc2_debug_assert_callback()")
+
+ TRC_MSG(SST_EXC_RMPU_DEBUG_INFO_ENTER, "[EXC][COMMON] Enter emimpu_dump_status()")
+ TRC_MSG(SST_EXC_RMPU_DEBUG_INFO_EXIT, "[EXC][COMMON] Exit emimpu_dump_status()")
+
+ TRC_MSG(SST_EXC_INIT_FDD_TABLE_ENTER, "[EXC][COMMON] Enter Initialize_FDD_tables()")
+ TRC_MSG(SST_EXC_INIT_FDD_TABLE_EXIT, "[EXC][COMMON] Exit Initialize_FDD_tables()")
+
+ TRC_MSG(SST_EXC_SAVE_EXCEPTION_RECORD_ENTER, "[EXC][COMMON] Enter ex_save_log()")
+ TRC_MSG(SST_EXC_SAVE_EXCEPTION_RECORD_EXIT, "[EXC][COMMON] Exit ex_save_log()")
+
+ TRC_MSG(SST_EXC_FS_UNLOCK_ALL_ENTER, "[EXC][COMMON] Enter FS_UnlockAll()")
+ TRC_MSG(SST_EXC_FS_UNLOCK_ALL_EXIT, "[EXC][COMMON] Exit FS_UnlockAll()")
+
+ TRC_MSG(SST_EXC_FS_SHUTDOWN_ENTER, "[EXC][COMMON] Enter FS_ShutDown()")
+ TRC_MSG(SST_EXC_FS_SHUTDOWN_EXIT, "[EXC][COMMON] Exit FS_ShutDown()")
+
+ TRC_MSG(SST_EXC_NVRAM_WRITE_EXC_ENTER, "[EXC][COMMON] Enter nvram_write_exception(%d, 0x%x, 0x%x)")
+ TRC_MSG(SST_EXC_NVRAM_WRITE_EXC_EXIT, "[EXC][COMMON] Exit nvram_write_exception()")
+
+ TRC_MSG(SST_EXC_EMM_WRITE_ENTER, "[EXC][COMMON] Enter EMM_Write_ExceptRecord()")
+ TRC_MSG(SST_EXC_EMM_WRITE_EXIT, "[EXC][COMMON] Exit EMM_Write_ExceptRecord()")
+
+ TRC_MSG(SST_EXC_RESET_EXCSP_ENTER, "[EXC][COMMON] Enter INT_ExceptionResetExcSP()")
+ TRC_MSG(SST_EXC_RESET_EXCSP_EXIT, "[EXC][COMMON] Exit INT_ExceptionResetExcSP()")
+
+ TRC_MSG(SST_EXC_CLEAN_RES_PROT_ENTER, "[EXC][COMMON] Enter ex_clean_res_prot()")
+ TRC_MSG(SST_EXC_CLEAN_RES_PROT_EXIT, "[EXC][COMMON] Exit ex_clean_res_prot()")
+
+ TRC_MSG(SST_EXC_UNGUARD_STACKSPACE_ENTER, "[EXC][COMMON] Enter kal_unguard_stack_space()")
+ TRC_MSG(SST_EXC_UNGUARD_STACKSPACE_EXIT, "[EXC][COMMON] Exit kal_unguard_stack_space()")
+
+ TRC_MSG(SST_EXC_NESTED_PROCESS_ENTER, "[EXC][COMMON] Enter ex_nested_process()")
+ TRC_MSG(SST_EXC_NESTED_PROCESS_EXIT, "[EXC][COMMON] Exit ex_nested_process()")
+
+ TRC_MSG(SST_EXC_INIT_DUMP_ENTER, "[EXC][COMMON] Enter ex_init_dump()")
+ TRC_MSG(SST_EXC_INIT_DUMP_EXIT, "[EXC][COMMON] Exit ex_init_dump()")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_ENTER, "[EXC][COMMON] Enter ex_remove_sensitive_for_dump()")
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_EXIT, "[EXC][COMMON] Exit ex_remove_sensitive_for_dump()")
+
+ TRC_MSG(SST_EXC_INIT_BBREG_DUMP_ENTER, "[EXC][COMMON] Enter ex_init_bbreg_dump()")
+ TRC_MSG(SST_EXC_INIT_BBREG_DUMP_EXIT, "[EXC][COMMON] Exit ex_init_bbreg_dump()")
+
+ TRC_MSG(SST_EXC_INIT_MINI_DUMP_ENTER, "[EXC][COMMON] Enter ex_init_mini_dump()")
+ TRC_MSG(SST_EXC_INIT_MINI_DUMP_EXIT, "[EXC][COMMON] Exit ex_init_mini_dump()")
+
+ TRC_MSG(SST_EXC_INIT_REAPPEAR_LOG_ENTER, "[EXC][COMMON] Enter ex_reappear_log()")
+ TRC_MSG(SST_EXC_INIT_REAPPEAR_LOG_EXIT, "[EXC][COMMON] Exit ex_reappear_log()")
+
+ TRC_MSG(SST_EXC_EX_REBOOT4MP_ENTER, "[EXC][COMMON] Enter ex_reboot4mp()")
+ TRC_MSG(SST_EXC_EX_REBOOT4MP_EXIT, "[EXC][COMMON] Exit ex_reboot4mp()")
+
+ TRC_MSG(SST_EXC_SYSMEM_TO_BE_DUMPED, "[EXC][COMMON] sys_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x)")
+ TRC_MSG(SST_EXC_SYSMEM_TO_BE_DUMPED_FOR_MINI, "[EXC][COMMON] sys_mem_xxx.bin to be dumped for mini [%d]: (0x%x, 0x%x)")
+ TRC_MSG(SST_EXC_SLAVE_SYSMEM_TO_BE_DUMPED, "[EXC][COMMON] slave_sys_mem_0x%08x.bin to be dumped [%d]: (0x%x, 0x%x)")
+
+ TRC_MSG(SST_EXC_DHLLOGGING_ENTER, "[EXC][COMMON] Enter dhl_call_exception_custom_logging at %dus")
+ TRC_MSG(SST_EXC_DHLLOGGING_EXIT, "[EXC][COMMON] Exit dhl_call_exception_custom_logging at %dus")
+ TRC_MSG(SST_EXC_HANDOVER2TST, "[EXC][COMMON] Handover to TST exception handler")
+
+ TRC_MSG(SST_EXC_READY2REBOOT, "[EXC][COMMON] Ready to silent reboot")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_USER_CALLBACK_ENTER, "[EXC][COMMON] Enter sensitive-removing callback, Index:%d, Taskname:%s")
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_USER_CALLBACK_EXIT, "[EXC][COMMON] Exit sensitive-removing callback, Index:%d, Taskname:%s, Elapsedtime:%dus")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_CTRLBUFF_ENTER, "[EXC][COMMON] Enter sensitive-removing: kal_clear_all_sensitive_buff_data()")
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_CTRLBUFF_EXIT, "[EXC][COMMON] Exit sensitive-removing: kal_clear_all_sensitive_buff_data(), Elapsedtime:%dus")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_QBM_ENTER, "[EXC][COMMON] Enter sensitive-removing: qbm_clear_all_sensitive_data()")
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_QBM_EXIT, "[EXC][COMMON] Exit sensitive-removing: qbm_clear_all_sensitive_data(), Elapsedtime:%dus")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_FL2_ENTER, "[EXC][COMMON] Enter sensitive-removing: fl2_ent_mask_peer_buff_for_miniDump()")
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_FL2_EXIT, "[EXC][COMMON] Exit sensitive-removing: fl2_ent_mask_peer_buff_for_miniDump(), Elapsedtime:%dus")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_STACK_ENTER, "[EXC][COMMON] Enter sensitive-removing stack, Index:%d")
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_STACK_EXIT, "[EXC][COMMON] Exit sensitive-removing stack, Index:%d")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_DETECT_ERROR, "[EXC][COMMON] sensitive-removing, detect errror happened! Exception Count:%d")
+
+ TRC_MSG(SST_EXC_REMOVE_SENSITIVE_DEBUG_STACK_INFO, "[EXC][COMMON] Exit sensitive-removing stack,sp:0x%x, start:0x%x, size:0x%x")
+
+ TRC_MSG(SST_EXC_SWITCH_WDT_PHASE2, "[EXC][COMMON] Do ex_switchWDT_phase2()")
+
+ TRC_MSG(SST_EXC_BBREG_DUMP_COUNT, "[EXC][COMMON] BB register dump count: %d")
+ TRC_MSG(SST_EXC_BBREG_DUMP_OWNER, "[EXC][COMMON] BB register dump owner: %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c")
+ TRC_MSG(SST_EXC_BBREG_DUMP_CALLBACK_FUNC_ENTER, "[EXC][COMMON] Enter BB register dump callback, address: 0x%x")
+ TRC_MSG(SST_EXC_BBREG_DUMP_CALLBACK_FUNC_EXIT, "[EXC][COMMON] Exit BB register dump callback, address: 0x%x")
+ TRC_MSG(SST_EXC_BBREG_DUMP_SKIP, "[EXC][COMMON] Skip this dump")
+ TRC_MSG(SST_EXC_BBREG_DUMP_SKIP2, "[EXC][COMMON] Callback (0x%x) caused nested exception -> skip this dump")
+ TRC_MSG(SST_EXC_BBREG_DUMP_TO_BE_DUMPED, "[EXC][COMMON] bb_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x, %d)")
+ TRC_MSG(SST_EXC_BBREG_DUMP_LARGE, "[EXC][COMMON] bb_mem size is larger than %d KB: (base, len)=(0x%x, 0x%x)")
+ TRC_MSG(SST_EXC_BBREG_DUMP_OVERLAP_SYS, "[EXC][COMMON] bb_mem (0x%x, 0x%x) overlap sys_mem (0x%x, 0x%x)")
+ TRC_MSG(SST_EXC_BBREG_DUMP_TOP_NUM, "[EXC][COMMON] top%d bb_mem (0x%x, 0x%x)")
+
+ TRC_MSG(SST_EXC_MINIDUMP_SYMBOL_OWNER, "[EXC][COMMON][MINIDUMP] symbol/area owner: %s")
+ TRC_MSG(SST_EXC_MINIDUMP_SYMBOL_CLEAN, "[EXC][COMMON][MINIDUMP] symbol/area cleaned: 0x%08x - 0x%08x, %s")
+ TRC_MSG(SST_EXC_MINIDUMP_SYMBOL_NESTED, "[EXC][COMMON][MINIDUMP] symbol/area 0x%08x - 0x%08x, %s, caused nested exception, SKIP it")
+
+ TRC_MSG(SST_EXC_L1CORE_BBREG_DUMP_OWNER, "[EXC][COMMON][L1CORE] BB register dump owner: %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c")
+ TRC_MSG(SST_EXC_L1CORE_BBREG_DUMP_TO_BE_DUMPED, "[EXC][COMMON][L1CORE] bb_mem_xxx.bin to be dumped [%d]: (0x%x, 0x%x, %d)")
+
+ TRC_MSG(SST_EXC_HANDLE_DUMP_REGION_ENTER, "[EXC][COMMON] Enter SST_HandleDumpRegion(addr=0x%08x, len=0x%x)")
+ TRC_MSG(SST_EXC_HANDLE_DUMP_REGION_EXIT, "[EXC][COMMON] Exit SST_HandleDumpRegion(addr=0x%08x, len=0x%x, operation result=%s)")
+ TRC_MSG(SST_EXC_HANDLE_DUMP_REGION_OP_CACHED, "[EXC][COMMON] SST_HandleDumpRegion: Do cache operation")
+ TRC_MSG(SST_EXC_HANDLE_DUMP_REGION_OP_TIMEOUT, "[EXC][COMMON]Timeout(> %dus): Start: %dus, End= %dus, Duration = %dus")
+
+ TRC_MSG(SST_EXC_HANDLE_EMIMPU_OUTPUT_ADDR, "[EXC][EMIMPU] MasterID:%x(%s) ViolationAddr:%x(%s)")
+ TRC_MSG(SST_EXC_HANDLE_EMIMPU_OUTPUT_REGION, "[EXC][EMIMPU] Region:%d Domain:%d Out-of-Range:%d")
+
+ TRC_MSG(SST_EXC_BBREG_OUTPUT, "[EXC][COMMON][BBREG_OUTPUT] address=0x%08x value=0%08x, sub_idx=%d, fill_cnt=%d")
+ TRC_MSG(SST_EXC_QUERY_BBREG_ENTER, "[EXC][COMMON]ex_query_bbreg_info(buf_ptr=0%08x, start_idx=%d, num=%d)")
+ TRC_MSG(SST_EXC_QUERY_BBREG_EXIT, "[EXC][COMMON]ex_query_bbreg_info() return fill_cnt=%d")
+ TRC_MSG(SST_EXC_QUERY_BBREG_SKIP, "[EXC][COMMON] skip_cnt(%d)+traverser->num(%d)+prv_fill_cnt(%d) <= start_idx(%d) => skip_cnt=%d")
+ TRC_MSG(SST_EXC_COPY_BBREG_START_IDX, "[EXC][COMMON] COPY_BBREG start idx=%d")
+ TRC_MSG(SST_EXC_QUERY_BBREG_UPDATE_SKIP, "[EXC][COMMON] prv_fill_cnt: %d, this traverser->num: %d")
+
+ TRC_MSG(SST_EXC_AFOUND_ENTER, "[EXC][COMMON] Enter ex_output_afound()")
+ TRC_MSG(SST_EXC_AFOUND_EXIT, "[EXC][COMMON] Exit ex_output_afound()")
+
+ TRC_MSG(SST_EXC_SEC_CHANNEL_DEINIT_ENTER, "[EXC][COMMON] Enter SST_SSF_Deinit()")
+ TRC_MSG(SST_EXC_SEC_CHANNEL_DEINIT_EXIT, "[EXC][COMMON] Exit SST_SSF_Deinit()")
+
diff --git a/mcu/service/sst/include/ex_cs_excep_hdlr.h b/mcu/service/sst/include/ex_cs_excep_hdlr.h
new file mode 100644
index 0000000..d891ef3
--- /dev/null
+++ b/mcu/service/sst/include/ex_cs_excep_hdlr.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_cs_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ * This file provides sonic related APIs
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __EX_CS_EXCEP_HDLR_H__
+#define __EX_CS_EXCEP_HDLR_H__
+
+#include "ex_cs_excep_hdlr_format.h"
+
+#include "reg_base.h" /* for BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1*/
+
+#include "dsp_file_public.h" /* DSP_DUMP_CORE_TYPE */
+
+#include "ex_public.h" /* for EX_TRACE_TYPE */
+
+
+
+/*
+ * if define MCU_ACCESS_SONIC_EVEN_HS_FAIL, MCU will keep accessing MCU/Sonic EX SHM
+ * even if MCU/Sonic fail to sync.
+ */
+#define MCU_ACCESS_SONIC_EVEN_HS_FAIL (1)
+
+
+typedef enum
+{
+ SONIC_M0_FAIL_BIT_MASK = (1<<0),
+ SONIC_V0_FAIL_BIT_MASK = (1<<1),
+} EX_SONIC_CORE_BIT_MASK_TYPE;
+
+
+// ----------------- macro definition ---------------
+/* Please use EX_SONIC_SYNC_TIME in cc_ex_item.h */
+//#define EX_SONIC_EX_SYNC_TIMEOUT 0x200000
+
+
+
+// ----------------- data type Definition -------------------
+
+
+
+
+// ----------------- function declaration -------------------
+
+kal_bool INT_SyncExSonicExceptionInfo(void);
+void INT_GetExSonicExceptionRecord(EX_SONIC_EXCEPTION_RECORD_T *record_ptr);
+void INT_GetExSonicFailCoreMask(kal_uint32 *fail_core_mask, kal_uint32 *fail_thread_mask);
+void INT_GetExSonicFailCoreIndex(kal_uint32 *fail_core_index, kal_uint32 *fail_thread_index);
+void INT_GetExSonicDumpMemoryInfo(DSP_DUMP_CORE_TYPE core_type, kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+void INT_GetExSonicDebugDumpMemoryInfo(DSP_DUMP_CORE_TYPE core_type, kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+kal_uint32 INT_GetNRDSPMCUViewMappingInfo(DSP_DUMP_CORE_TYPE core_type, kal_uint32 addr);
+kal_char* INT_GetExSonicCoreName(kal_uint32 core_index);
+void INT_DumpExSonicExceptionInfo(EX_TRACE_TYPE trace_type, kal_char* sys_info_str, kal_uint32 len);
+
+
+
+
+#endif /* __EX_CS_EXCEP_HDLR_H__ */
diff --git a/mcu/service/sst/include/ex_cs_excep_hdlr_format.h b/mcu/service/sst/include/ex_cs_excep_hdlr_format.h
new file mode 100644
index 0000000..0f256df
--- /dev/null
+++ b/mcu/service/sst/include/ex_cs_excep_hdlr_format.h
@@ -0,0 +1,189 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_cs_excep_hdlr_format.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ * This file provides sonic related APIs
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __EX_CS_EXCEP_HDLR_FORMAT_H__
+#define __EX_CS_EXCEP_HDLR_FORMAT_H__
+
+
+//#include "sonic_ex_common_def.h"
+
+
+
+// ----------------- macro definition ---------------
+#define EX_SONIC_MSONIC_CORE_NUM (1)
+#define EX_SONIC_VSONIC_CORE_NUM (1)
+#define EX_SONIC_TOTAL_CORE_NUM (EX_SONIC_MSONIC_CORE_NUM + EX_SONIC_VSONIC_CORE_NUM)
+
+
+#if defined(MT6297)
+#define EX_SONIC_PER_MSONIC_THREAD_NUM (4)
+#define EX_SONIC_PER_VSONIC_THREAD_NUM (4)
+#define EX_SONIC_MAX_MSONIC_VSONIC_THREAD_NUM (4) /* max(EX_SONIC_PER_MSONIC_THREAD_NUM, EX_SONIC_PER_VSONIC_THREAD_NUM) */
+#elif defined(MT6885) || defined(CHIP10992)
+#define EX_SONIC_PER_MSONIC_THREAD_NUM (4)
+#define EX_SONIC_PER_VSONIC_THREAD_NUM (3)
+#define EX_SONIC_MAX_MSONIC_VSONIC_THREAD_NUM (4) /* max(EX_SONIC_PER_MSONIC_THREAD_NUM, EX_SONIC_PER_VSONIC_THREAD_NUM) */
+#elif defined(MT6833) || defined(__PALMER_SIMULATION__) || defined(MT6877) /* "defined(__PALMER_SIMULATION__)" is before "defined(MT6853)" */
+#define EX_SONIC_PER_MSONIC_THREAD_NUM (3)
+#define EX_SONIC_PER_VSONIC_THREAD_NUM (2)
+#define EX_SONIC_MAX_MSONIC_VSONIC_THREAD_NUM (3) /* max(EX_SONIC_PER_MSONIC_THREAD_NUM, EX_SONIC_PER_VSONIC_THREAD_NUM) */
+#elif defined(MT6873) || defined(MT6853)
+#define EX_SONIC_PER_MSONIC_THREAD_NUM (4)
+#define EX_SONIC_PER_VSONIC_THREAD_NUM (2)
+#define EX_SONIC_MAX_MSONIC_VSONIC_THREAD_NUM (4) /* max(EX_SONIC_PER_MSONIC_THREAD_NUM, EX_SONIC_PER_VSONIC_THREAD_NUM) */
+#else
+#error "please do new project CPU info porting"
+#endif
+#define EX_SONIC_MSONIC_THREAD_NUM (EX_SONIC_MSONIC_CORE_NUM * EX_SONIC_PER_MSONIC_THREAD_NUM)
+#define EX_SONIC_VSONIC_THREAD_NUM (EX_SONIC_VSONIC_CORE_NUM * EX_SONIC_PER_VSONIC_THREAD_NUM)
+#define EX_SONIC_TOTAL_THREAD_NUM (EX_SONIC_MSONIC_THREAD_NUM + EX_SONIC_VSONIC_THREAD_NUM)
+
+#define EX_SONIC_EX_LOG_SIZE (sizeof(EX_SonicLog))
+
+#define EX_SONIC_INVALID_IDX ((kal_uint32)0xFF)
+
+
+
+#if defined(MT6297)
+#define EX_SONIC_SHM_ADDR ((kal_uint32)BASE_MADDR_MCOREPERI_INFRA_MML1_MCORESYS_SHDM1)
+#elif defined(MT6885)|| defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(__PALMER_SIMULATION__) || defined(MT6877) || defined(CHIP10992)
+#define EX_SONIC_SHM_ADDR ((kal_uint32)BASE_MADDR_MCOREPERI_INFRA_L2TCM0)
+#else
+#error "not support chip!"
+#endif
+
+
+#define EX_SONIC_NO_FAIL_CORE_THREAD (0xFFFFFFFF)
+
+#define EX_SONIC_ASSERTION_INFO_FILE_NAME_LEN (56)
+
+#define EX_SONIC_MOF_NAME_LEN (4)
+#define EX_SONIC_INVALID_MOF_NAME "NULL"
+
+// ----------------- data type Definition -------------------
+
+typedef enum{
+ EX_SONIC_EXCEPTION_NONE = 0,
+ EX_SONIC_EXCEPTION_ASSERT_LINE,
+ EX_SONIC_EXCEPTION_ASSERT_EXT,
+ EX_SONIC_EXCEPTION_FATAL_ERROR,
+ EX_SONIC_EXCEPTION_CTI,
+ EX_SONIC_EXCEPTION_CUSTOM_ASSERT_ADDR,
+ EX_SONIC_EXCEPTION_CUSTOM_ASSERT_MOFID,
+ EX_SONIC_EXCEPTION_CUSTOM_ASSERT_MODID,
+ EX_SONIC_EXCEPTION_UNKNOWN = 0xEEEEEEEE,
+ EX_SONIC_EXCEPTION_END = 0xFFFFFFFF
+}EX_SONIC_EXCEPTION_TYPE_T;
+
+
+typedef enum{
+ EX_SONIC_FAIL_CORE_NONE = 0,
+ EX_SONIC_FAIL_CORE_M0,
+ EX_SONIC_FAIL_CORE_V0,
+ EX_SONIC_FAIL_CORE_END = 0xFFFFFFFF
+}EX_SonicFailCore;
+
+/* max 100 bytes, plz check EX_SONIC_CORE_SIZE */
+typedef struct {
+ unsigned int line_num;
+ unsigned int para1;
+ unsigned int para2;
+ unsigned int para3;
+ unsigned char file_name[EX_SONIC_ASSERTION_INFO_FILE_NAME_LEN];
+ char *filepath_ptr;
+ unsigned int custom_param;
+ unsigned char mof_name[4];
+ unsigned int lr;
+} EX_SONIC_ASSERTION_INFO_T;
+
+
+typedef struct {
+ unsigned int error_code1;
+ unsigned int error_code2;
+ unsigned int offending_address;
+} EX_SONIC_FATAL_ERROR_INFO_T;
+
+
+typedef struct {
+ EX_SONIC_EXCEPTION_TYPE_T except_type;
+ unsigned int except_stat;
+ union {
+ EX_SONIC_ASSERTION_INFO_T assert;
+ EX_SONIC_FATAL_ERROR_INFO_T fatal;
+ }except_content;
+} EX_SONIC_EXCEPTION_INFO_T;
+
+
+/* note we use core # rather than thread # */
+typedef struct {
+ unsigned int core_num;
+ EX_SONIC_EXCEPTION_INFO_T core_error[EX_SONIC_TOTAL_CORE_NUM];
+} EX_SONIC_EXCEPTION_RECORD_T;
+
+
+
+// ----------------- function declaration -------------------
+
+
+
+
+#endif /* __EX_CS_EXCEP_HDLR_FORMAT_H__ */
diff --git a/mcu/service/sst/include/ex_cs_excep_internal_api.h b/mcu/service/sst/include/ex_cs_excep_internal_api.h
new file mode 100644
index 0000000..4e366d2
--- /dev/null
+++ b/mcu/service/sst/include/ex_cs_excep_internal_api.h
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_cs_excep_internal_api.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ * This file provides sonic related APIs (SST module only)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __EX_CS_EXCEP_INTERNAL_API_H__
+#define __EX_CS_EXCEP_INTERNAL_API_H__
+
+#include "sonic_ex_common_def.h"
+
+
+// ----------------- macro definition ---------------
+
+// ----------------- data type Definition -------------------
+
+// ----------------- function declaration -------------------
+EX_SonicLog * ex_sonic_get_ex_log_ptr_by_sonic_thread_index(kal_uint32 sonic_thread_idx);
+
+
+
+#endif /* __EX_CS_EXCEP_INTERNAL_API_H__ */
diff --git a/mcu/service/sst/include/ex_item.h b/mcu/service/sst/include/ex_item.h
new file mode 100644
index 0000000..390f0d7
--- /dev/null
+++ b/mcu/service/sst/include/ex_item.h
@@ -0,0 +1,1671 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_item.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Header file for exception handling
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _EX_ITEM_H
+#define _EX_ITEM_H
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#include "kal_general_types.h"
+#include "reg_base.h"
+#include "intrCtrl.h"
+#include "kal_public_defs.h"
+#include "ex_public.h"
+#include "SST_mem_utility.h"
+#if defined(__MIPS_MMU_EXIST__)
+#include "mips_mmu.h"
+#endif
+#include "mpu_public.h"
+#else
+#include "ex_item_types.h"
+#include "cpu_info.h"
+#endif /*__OFFLINE_EX_LOG_PARSER__*/
+
+/*******************************************************************************
+ * Enum Type Definition
+ *******************************************************************************/
+
+
+/* exception enter category */
+typedef enum
+{
+ EXCEPTION_ENTER_CATEGORY_NO_EXCEPTION = 0,
+ EXCEPTION_ENTER_CATEGORY_TLBREFILL,
+ EXCEPTION_ENTER_CATEGORY_CACHEERR,
+ EXCEPTION_ENTER_CATEGORY_GENERAL,
+ EXCEPTION_ENTER_CATEGORY_NMI,
+ EXCEPTION_ENTER_CATEGORY_CTI,
+ EXCEPTION_ENTER_CATEGORY_DORMANT,
+ EXCEPTION_ENTER_CATEGORY_EXCEPTION_IN_ASM_BOOT,
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER)
+} exception_enter_category;
+#else
+} exception_enter_category_format;
+typedef kal_uint8 exception_enter_category;
+#endif
+
+typedef enum
+{
+ /* mips exception codes in cause[exccode] */
+ INTERRUPT_EXCEPTION = 0x0,
+ TLB_MOD_EXCEPTION = 0x1,
+ TLB_MISS_LOAD_EXCEPTION = 0x2,
+ TLB_MISS_STORE_EXCEPTION = 0x3,
+ ADDRESS_ERROR_LOAD_EXCEPTION = 0x4,
+ ADDRESS_ERROR_STORE_EXCEPTION = 0x5,
+ INSTR_BUS_ERROR = 0x6,
+ DATA_BUS_ERROR = 0x7,
+ SYSTEM_CALL_EXCEPTION = 0x8,
+ BREAKPOINT_EXCEPTION = 0x9,
+ RESERVED_INSTRUCTION_EXCEPTION = 0xA,
+ COPROCESSORS_UNUSABLE_EXCEPTION = 0xB,
+ INTEGER_OVERFLOW_EXCEPTION = 0xC,
+ TRAP_EXCEPTION = 0xD,
+ MSA_FLOATING_POINT_EXCEPTION = 0xE,
+ FLOATING_POINT_EXCEPTION = 0xF,
+ COPROCESSOR_2_IS_1_EXCEPTION = 0x10,
+ COR_EXTEND_UNUSABLE_EXCEPTION = 0x11,
+ COPROCESSOR_2_EXCEPTION = 0x12,
+ TLB_READ_INHIBIT_EXCEPTION = 0x13,
+ TLB_EXECUTE_INHIBIT_EXCEPTION = 0x14,
+ MSA_UNUSABLE_EXCEPTION = 0x15,
+ MDMX_EXCEPTION = 0x16,
+ WATCH_EXCEPTION = 0x17,
+ MCHECK_EXCEPTION = 0x18,
+ THREAD_EXCEPTION = 0x19,
+ DSP_UNUSABLE_EXCEPTION = 0x1A,
+ RESERVED_27_EXCEPTION = 0x1B,
+ RESERVED_28_EXCEPTION = 0x1C,
+ MPU_NOT_ALLOW_EXCEPTION = 0x1D,
+ CACHE_ERROR_EXCEPTION_DBG_MODE = 0x1E,
+ RESERVED_31_EXCEPTION = 0x1F,
+
+ /* exception types for nmi and cache error exception vectors */
+ NMI_EXCEPTION = 0x20,
+ CACHE_ERROR_EXCEPTION = 0x21,
+
+ /* These are used to replace TLB_MISS_LOAD/STORE_EXCEPTION
+ * codes when using tlb refill exception vector.
+ * TLB_MISS_LOAD/STORE_EXCEPTION code is used for tlb invalid */
+ TLB_REFILL_LOAD_EXCEPTION = 0x22,
+ TLB_REFILL_STORE_EXCEPTION = 0x23,
+
+ END_CPU_EXCEPTION_TYPE = 0x2F,
+
+ STACKACCESS_EXCEPTION = 0x30,
+ SYS_FATALERR_EXT_TASK_EXCEPTION = 0x31,
+ SYS_FATALERR_EXT_BUF_EXCEPTION = 0x32,
+ /* Assertion */
+ ASSERT_FAIL_EXCEPTION = 0x50,
+ ASSERT_DUMP_EXTENDED_RECORD = 0x51,
+ ASSERT_FAIL_NATIVE = 0x52,
+ ASSERT_CUSTOM_ADDR = 0x53,
+ ASSERT_CUSTOM_MODID = 0x54,
+ ASSERT_CUSTOM_MOFID = 0x55,
+ /* cross core triggered */
+ CC_INVALID_EXCEPTION = 0x60,
+// CC_CS_EXCEPTION = 0x61,
+ CC_MD32_EXCEPTION = 0x62,
+// CC_C2K_EXCEPTION = 0x63,
+// CC_VC_EXCEPTION = 0x64,
+ CC_USIP_EXCEPTION = 0x65,
+ CC_SCQ_EXCEPTION = 0x66,
+ CC_SONIC_EXCEPTION = 0x67,
+ /* HW triggered */
+ EMI_MPU_VIOLATION_EXCEPTION = 0x70,
+
+ AP_EXCEPTION = 0x80,
+
+ NUM_EXCEPTION,
+ END_EXCEPTION_TYPE = 0xFFFF
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER)
+} exception_type;
+#else
+} exception_type_format;
+typedef kal_uint16 exception_type;
+#endif
+
+typedef enum ex_maincontent_type_t
+{
+ EX_MAINCONTENT_TYPE_ASSERT = 0,
+ EX_MAINCONTENT_TYPE_FATAL,
+ EX_MAINCONTENT_TYPE_CUSTOM_ASSERT
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER)
+} EX_MAINCONTENT_TYPE_T;
+#else
+} EX_MAINCONTENT_TYPE_T_FORMAT;
+typedef kal_uint8 EX_MAINCONTENT_TYPE_T;
+#endif /*__OFFLINE_EX_LOG_PARSER__*/
+
+
+
+#define INTSRAM_CODE_CORRUPT "ISPRAM"
+#define DYNINTSRAM_CODE_CORRUPT "DYNISPRAM"
+#define VECTOR_TABLE_CORRUPT "INTVECT"
+#define L2SRAM_C_CODE_CORRUPT "C_L2SRAM"
+#define L2SRAM_NC_CODE_CORRUPT "NC_L2SRAM"
+#define LOCK_WAITED_TOO_LONG_CORRUPT "WAITLOCK"
+#define POSSIBLE_DEADLOCK_CORRUPT "DEADLOCK"
+#define LOCK_HELD_TOO_LONG_CORRUPT "HELDLOCK"
+#define CACHE_CORRUPT "CACHECOR"
+#define L2CACHE_LOCK_CORRUPT "L2$LOCK"
+#define DYNL2CACHE_LOCK_CORRUPT "DYNL2$L"
+#define MPU_CORRUPT "MPU"
+typedef enum
+{
+ Healthy = 0,
+ ISPRAMCorrupted = 1,
+ ISPRAMDynamicRegionCorrupted = 2,
+ SystemStackCorrupted = 3,
+ TaskStackCorrupted = 4,
+ HISRStackCorrupted = 5,
+ VectorTableCorrupted = 6,
+ L2SRAMCachedCorrupted = 7,
+ L2SRAMNonCachedCorrupted = 8,
+ SharedInternalSRAMCorrupted = 9,
+ LockWaitedTooLongCorrupted = 10,
+ PossibleDeadlockCorrupted = 11,
+ LockHeldTooLongCorrupted = 12,
+ CacheCorrupted = 13,
+ L2CacheLockCorrupted = 14,
+ DynamicL2CacheLockCorrupted = 15,
+ MPUCorrupted = 16,
+ StackFrameCorrupted = 17,
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER)
+} EX_DIAGNOSIS_T;
+#else
+} EX_DIAGNOSIS_T_FORMAT;
+typedef kal_uint8 EX_DIAGNOSIS_T;
+#endif
+
+typedef enum
+{
+ EX_AUTO_STEP = 0,
+ EX_BEGIN = 0,
+
+ // exception enter part
+ EX_SAVE_MDCIRQ_STATUS_BEFORE_CTI = 0x1,
+ EX_TRIGGER_CTI = 0x2,
+ EX_SAVE_MDCIRQ_STATUS_AFTER_CTI = 0x3,
+ EX_BACKUP_EX_REGISTERS = 0x4,
+ EX_STOP_SLA = 0x5,
+ EX_SSS_PF_EXCP = 0x6,
+ EX_RESTORE_IRQ_MASK_BACKUP = 0x7,
+ EX_SWITCH_WDT_PHASE1 = 0x8,
+ EX_SAVE_CORE_CONTEXT = 0x9,
+ EX_UPDATE_NON_OFFENDING_CONTEXT = 0xA,
+ EX_KICK_WDT = 0xB,
+ EX_DUMP_MPU = 0xC,
+ EX_SET_EX_MPU = 0xD,
+ EX_WAIT_FOR_OTHER_CORES = 0xE,
+ EX_MDCIRQ_MASK_ALL = 0xF,
+ EX_HANDLE_WATCH_REG = 0x10,
+ EX_CHANGE_DI_TC = 0x11,
+ EX_HALT_OTHER_TC_CLEAR_EXL = 0x12,
+ EX_RELEASE_OS_LOCKS = 0x13,
+ EX_BACKUP_EX_COUNT = 0x14,
+ EX_ENTER_EXCEPTION_SETUP_DONE = 0x15,
+ EX_ENTER_EXCEPTION_PHASE2 = 0x16,
+ EX_SAVE_OFFENDING_CACHE_LINES = 0x17,
+ EX_CM2_REGION_DUMP = 0x18,
+ EX_ENTER_EXCEPTION_PHASE3 = 0x19,
+ EX_GET_BREAK_CODE = 0x1A,
+
+ //exception handling part
+ EX_KAL_ASSERT_HANDLER = 0x30,
+ EX_KAL_FATAL_ERROR_HANDLER_INT = 0x31,
+ EX_KAL_EXCEPTION_HANDLER = 0x32,
+ EX_KAL_ECT_QUERY = 0x33,
+ EX_KAL_CTI_HANDLER = 0x34,
+ EX_EXCEPTION_HANDLER = 0x35,
+
+ //system data collection part
+ EX_INIT_PCMON = 0x40,
+ EX_KICK_WDT2 = 0x41,
+ EX_GET_PDAMON = 0x42,
+ EX_WRITE_OFFENDING_PCMON_TO_EMM = 0x43,
+ EX_KICK_WDT16 = 0x44,
+ EX_INIT_BUSMON = 0x45,
+ EX_START_PDAMON = 0x46,
+ EX_INIT_EX_OVERVIEW = 0x47,
+ EX_PREPARE_PARAM = 0x48,
+ EX_INIT_LOG = 0x49,
+ EX_KICK_WDT3 = 0x4A,
+ EX_INIT_MCU_SYSINFO = 0x4B,
+ EX_BUSDRV_GET_DUMP_INFO = 0x4C,
+ EX_KICK_WDT4 = 0x4D,
+ EX_DUMP_BUSMPU_ERR = 0x4E,
+ EX_DUMP_BUSMPU_IRQ_STS = 0x4F,
+ EX_KICK_WDT5 = 0x50,
+ EX_INIT_DSM = 0x51,
+ EX_KICK_WDT6 = 0x52,
+ EX_INIT_MPU = 0x53,
+ EX_KICK_WDT7 = 0x54,
+ EX_WAIT_USIP = 0x55,
+ EX_WAIT_MD32 = 0x56,
+ EX_WAIT_SONIC = 0x57,
+ EX_WAIT_SAP = 0x58,
+ EX_INIT_DONE = 0x59,
+
+ //writing data to exrecord & shm
+ EX_POST_INIT_EXRECORD = 0x70,
+ //autosteps
+ EX_DEFINE_MAIN_REASON_DONE = 0x7A,
+ EX_COPY_DVFS_EX_DATA = 0x7B,
+ EX_HW_DATA_SAVE_DONE = 0x7C,
+ EX_POST_INIT_EXRECORD_DONE = 0x7D,
+
+ // external communication
+ EX_CC_EXT_COMM = 0x100,
+ EX_CC_EXT_COMM_OPEN_PORT = 0x110,
+ EX_CC_EXT_COMM_OPEN_PORT_DONE = 0x13F,
+ EX_CC_EXT_COMM_CCCI_HANDSHAKE = 0x140,
+ //autosteps
+ EX_CC_EXT_COMM_CCCI_HANDSHAKE_DONE = 0x16F,
+ EX_CC_EXT_COMM_OUTPUT_META = 0x170,
+ //autosteps
+ EX_CC_EXT_COMM_OUTPUT_META_DONE = 0x180,
+ EX_CC_EXT_COMM_FLUSH_PORT = 0x181,
+ //autosteps
+ EX_CC_EXT_COMM_FLUSH_PORT_PART1 = 0x190,
+ EX_CC_EXT_COMM_FLUSH_PORT_PART2 = 0x1A0,
+ EX_CC_EXT_COMM_FLUSH_PORT_PART3 = 0x1B0,
+ EX_CC_EXT_COMM_FLUSH_PORT_PART4 = 0x1C0,
+ EX_CC_EXT_COMM_FLUSH_PORT_PART5 = 0x1D0,
+ //autosteps
+ EX_CC_EXT_COMM_FLUSH_PORT_DONE = 0x1E0,
+ EX_CC_EXT_COMM_DONE = 0x1FF,
+
+ // process
+ EX_PROCESS = 0x200,
+ EX_L1_AUDIO_RESET_DEVICE = 0x201,
+ EX_L1D_PAUSE_DSP = 0x202,
+ EX_KICK_WDT14 = 0x203,
+ EX_TL1_FORCE_STALL = 0x204,
+ EX_KICK_WDT15 = 0x205,
+ EX_MSG_OUTPUT = 0x206,
+ EX_OUTPUT_LOG = 0x207,
+ EX_USIP_CADEFA = 0x208,
+ EX_MD32_CADEFA = 0x209,
+ EX_SONIC_CADEFA = 0x20A,
+ EX_SONIC_CADEFA_DONE = 0x20B,
+ EX_OUTPUT_USIP_LOG = 0x20C,
+ EX_OUTPUT_MD32_LOG = 0x20D,
+ EX_OUTPUT_SONIC_LOG = 0x20E,
+ EX_OUTPUT_SONIC_LOG_DONE = 0x20F,
+ EX_FLC2DEBUG_ASSERT_CALLBACK = 0x210,
+ EX_FLC2DEBUG_ASSERT_CALLBACK_DONE = 0x211,
+ EX_DHL_CALL_EXCEPTION_CUSTOM_LOGGING = 0x212,
+ EX_DHL_CALL_EXCEPTION_CUSTOM_LOGGING_DONE = 0x213,
+ EX_INFO_SAVE = 0x214,
+ INITIALIZE_FDD_TABLES = 0x215,
+ INITIALIZE_FDD_TABLES_DONE = 0x216,
+ EX_SAVE_LOG = 0x217,
+ EX_SAVE_LOG_DONE = 0x218,
+ EX_PROCESS_DONE = 0x240,
+
+
+ // 1st non-offending vpe
+ EX_START_DSP_COMMUNICATION = 0x300,
+ EX_INIT_DSP = 0x301,
+ EX_INIT_USIP = 0x302,
+ //autosteps
+ EX_KICK_WDT8 = 0x30C,
+ EX_INIT_USIP_DONE = 0x30D,
+ EX_INIT_MD32 = 0x30E,
+ //autosteps
+ EX_KICK_WDT9 = 0x318,
+ EX_INIT_MD32_DONE = 0x319,
+ EX_INIT_SONIC = 0x31A,
+ //autosteps
+ EX_KICK_WDT10 = 0x324,
+ EX_INIT_SONIC_DONE = 0x325,
+ EX_INIT_DSP_DONE = 0x326,
+
+ // 2nd non-offending vpe
+ EX_START_HW_COMMUNICATION = 0x400,
+ EX_INIT_STOP_HW = 0x401,
+ EX_ASM_STOP = 0x402,
+ EX_ASM_STOP_DONE = 0x403,
+ EX_DIGIRF_MIPI_PATH_STOP = 0x404,
+ EX_DIGIRF_MIPI_PATH_STOP_DONE = 0x405,
+ EX_SCC_STOP = 0x406,
+ EX_SCC_STOP_DONE = 0x407,
+ EX_HW_DUMP = 0x408,
+ EX_DVFS_EX_DATA_READ = 0x409,
+ EX_HW_DUMP_DONE = 0x40A,
+ EX_DSP_EX_INIT = 0x40B,
+ EX_DSP_EX_INIT_DONE = 0x40C,
+ EX_INIT_STOP_HW_DONE = 0x40B,
+
+ // rest of the non-offending vpe
+ EX_START_INT_OFFSHOOT = 0x450,
+
+ // nested exception specific steps
+ EX_NESTED_LOG_INIT = 0x500,
+ EX_NESTED_PDAMON_INIT = 0x501,
+ EX_START_NESTED_PDAMON = 0x502,
+ EX_START_NESTED_PDAMON_DONE = 0x503,
+ EX_NESTED_PROCESS = 0x504,
+ EX_NESTED_PROCESS_DONE = 0x505,
+
+ // reboot
+ EX_EX_REBOOT = 0x600,
+ EX_REMOVE_SENSITIVE_FOR_DUMP = 0x601,
+ EX_KICK_WDT11 = 0x602,
+ EX_SSF_DEINIT = 0x603,
+ EX_RESET_EXCP_SP = 0x604,
+ EX_WRITE_EXRECORD = 0x605,
+
+ // reboot mp (silent reboot)
+ EX_EX_REBOOT_MP = 0x700,
+ EX_CCCI_INFO_PASSED_4MP = 0x780,
+ //autosteps
+ EX_CCCI_INFO_PASSED_4MP_DONE = 0x790,
+
+
+ EX_EX_REBOOT_MP_DONE = 0x606,
+ EX_INIT_DUMP = 0x607,
+ EX_KICK_WDT12 = 0x608,
+ EX_CCCI_INFO_PASSED = 0x609,
+ //autosteps
+ EX_CCCI_INFO_PASSED_DONE = 0x619,
+ EX_KICK_WDT13 = 0x61A,
+ EX_SWITCH_WDT_PHASE2 = 0x61B,
+ EX_CHECK_ELT_TRACES = 0x61C,
+#if defined(CHIP10992)
+ EX_CLEAN_CACHE_BEFORE_HANDOVER = 0x61D,
+ EX_CLEAN_CACHE_BEFORE_ON_DEMAND = 0x61E,
+#endif
+ //Ex flow complete step for silent reboot
+ EX_HANDOVER_MP = 0x7EF,
+
+ //Ex flow complete step for memdump
+ EX_HANDOVER = 0x7FF,
+
+ //Ex flow complete step for non-offending vpes
+ EX_ON_DEMAND = 0x7FF,
+
+ EX_RESET_HANDOVER = 0x8EF,
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__) && !defined(_MSC_VER)
+} exception_flow_index;
+#else
+} exception_flow_index_format;
+typedef kal_uint16 exception_flow_index;
+#endif
+
+typedef enum {
+ AFOUND_NO_OUTPUT = 0x0,
+ AFOUND_TO_TRACE = 0x1,
+ AFOUND_TO_EXRECORD = 0x2
+} afound_output_types;
+
+/*******************************************************************************
+ * Constant Definition - Common
+ *******************************************************************************/
+/* structure usage */
+#define EX_UNIT_NAME_LEN 8
+#define NBR_TC_PER_CORE (SYS_MCU_NUM_TC/SYS_MCU_NUM_CORE)
+#define NBR_VPE_PER_CORE (SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE)
+#define NBR_CORE (SYS_MCU_NUM_CORE)
+#define TOTAL_VPE_COUNT (SYS_MCU_NUM_VPE)
+#define TOTAL_VICTIM_VPE_COUNT (TOTAL_VPE_COUNT - 1)
+
+#define SST_GET_VPE_ID(core,tc) ((core)*NBR_VPE_PER_CORE + (tc)/(NBR_TC_PER_CORE/NBR_VPE_PER_CORE))
+
+/* Use real vpe count for these*/
+#define EX_WAIT_VPE_MASK ((1 << SYS_MCU_NUM_VPE) - 1)
+#define EXCEPTION_ENTER_MASK ((1 << SYS_MCU_NUM_VPE) - 1)
+/* This is hardcoded to max nbr of tlbs in interaptiv.
+ * Can be reduced to match correct count of tlbs in hw if we know tlbs wont increase after that */
+#define NUMBER_OF_TLBS 64
+
+#if defined(__MIPS_I7200__)
+#define NBR_OF_WATCH_REGS 8
+#define NBR_OF_KSCRATCH_REGS 6
+#else
+#define NBR_OF_WATCH_REGS 4
+#define NBR_OF_KSCRATCH_REGS 3
+#endif
+
+
+/*******************************************************************************
+ * Data Structure Definition - Common
+ *******************************************************************************/
+/*******************************************************************************
+ * Macro API Definition - Common
+ *******************************************************************************/
+#define EX_GET_COREID_BY_VPEID(VPEID) (VPEID/NBR_VPE_PER_CORE)
+#define EX_GET_COREVPEID_BY_VPEID(VPEID) (VPEID % NBR_VPE_PER_CORE)
+#if defined(__MD97__) || defined(__MD97P__)
+/* For Gen97 Shaolin Configuration: 6 TCs per Core. (2:2:2) */
+#define EX_GET_MAINTC_BY_VPEID(VPEID) (EX_GET_COREVPEID_BY_VPEID(VPEID) * 2)
+#else
+#error No config yet
+#endif
+/***************************** -structure start- *******************************/
+//PRAGMA_BEGIN_PACK_STRUCT
+/* Exception header, used to track the exception type */
+typedef struct ex_exception_record_header_t
+{
+ exception_type ex_type; /* offset: 0x, length: 2 */
+ kal_uint8 ex_offending_vpe_id; /* offset: 0x, length: 1 */
+ kal_uint8 ex_offending_tc_id; /* offset: 0x, length: 1 */
+ kal_uint8 ex_nvram; /* offset: +0x, length: 1 - for nvram */
+ kal_uint8 ex_serial_num; /* offset: +0x, length: 1 - for nvram */
+ boot_mode_type boot_mode; /* offset: +0x, length: 1 - normal mode/meta mode... */
+ kal_uint8 boot_status; /* offset: +0x, length: 1 - early stage or not */
+ kal_uint32 ex_total_core; /* offset: 0x, length: 4 - how many cores in mcu */
+} EX_HEADER_T;
+
+/* SW load information */
+#define EX_SWLABEL_LEN 32
+#define EX_SWPRJ_LEN 32
+#define EX_SWFLAVOR_LEN 32
+#define EX_SWBUILDTIME_LEN 16
+typedef struct ex_sw_loadinfo_t
+{
+ kal_char sw_label[EX_SWLABEL_LEN];
+ kal_char sw_project_name[EX_SWPRJ_LEN];
+ kal_char sw_flavor[EX_SWFLAVOR_LEN];
+ kal_char sw_buildtime[EX_SWBUILDTIME_LEN];
+} EX_LOADINFO_T;
+
+
+/* First Offender information */
+typedef struct _ex_timestamp_struct
+{
+ kal_uint32 USCNT; /* offset: +0x, length: 4 */ /* us counter saved exception occuring time */
+ kal_uint32 frameno; /* offset: +0x, length: 4 */ /* frameno saved exception occuring time */
+} ex_timestamp_struct;
+typedef struct _ex_basic_offending_info_t
+{
+ ex_timestamp_struct ex_timestamp; /* offset: +0x, length: */
+ kal_char execution_unit[EX_UNIT_NAME_LEN]; /* offset: +0x, length: */
+ kal_uint32 processing_lisr; /* offset: +0x, length: */
+ kal_uint32 stack_ptr; /* offset: +0x, length: */
+ kal_uint32 lr; /* offset: +0x, length: */
+ kal_uint32 pc; /* offset: +0x, length: */
+ kal_uint8 tc_status; /* offset: +0x, length: */
+ kal_uint8 pad[3]; /* offset: +0x, length: */
+} EX_BASIC_OFFENDING_INFO_T;
+
+/* Environment information */
+typedef struct ex_diagnosis_info_t
+{ /* Diagnosis information for Healthy Check */
+ kal_char healthy_check_owner[EX_UNIT_NAME_LEN]; /* offset: +0x, length: 8 */
+ EX_DIAGNOSIS_T corrupted_owner; /* offset: +0x, length: 1 */
+ kal_uint8 ELM_status; /* offset: +0x, length: 1 */
+ kal_uint8 pad[2]; /* offset: +0x, length: 2 */
+} EX_DIAGNOSISINFO_T;
+typedef struct ex_environment_info_t
+{
+ kal_uint32 interrupt_mask[2]; /* offset: +0x, length: 8 */
+ EX_DIAGNOSISINFO_T diagnosis; /* offset: +0x, length: 12 */
+ kal_uint32 force_dump; /* offset: +0x, length: 4 */
+} EX_ENVINFO_T;
+
+
+/*******************************************************************************
+ * Data Structure Definition - general cpu info
+ *******************************************************************************/
+typedef struct _ex_gpr_reg_t
+{
+ kal_uint32 ZERO;
+ kal_uint32 AT;
+ kal_uint32 V0;
+ kal_uint32 V1;
+ kal_uint32 A0;
+ kal_uint32 A1;
+ kal_uint32 A2;
+ kal_uint32 A3;
+ kal_uint32 T0;
+ kal_uint32 T1;
+ kal_uint32 T2;
+ kal_uint32 T3;
+ kal_uint32 T4;
+ kal_uint32 T5;
+ kal_uint32 T6;
+ kal_uint32 T7;
+ kal_uint32 S0;
+ kal_uint32 S1;
+ kal_uint32 S2;
+ kal_uint32 S3;
+ kal_uint32 S4;
+ kal_uint32 S5;
+ kal_uint32 S6;
+ kal_uint32 S7;
+ kal_uint32 T8;
+ kal_uint32 T9;
+ kal_uint32 K0;
+ kal_uint32 K1;
+ kal_uint32 GP;
+ kal_uint32 SP;
+ kal_uint32 FP_OR_S8;
+ kal_uint32 RA;
+} EX_GPR_REG_T;
+
+/* NOTE: if changing this struct, please chagne SAVE_EX_CPU_REG_T @ ex_hdlr_gcc.S macro as well */
+typedef struct _ex_cpu_reg_t
+{
+ EX_GPR_REG_T GPR;
+ kal_uint32 hi;
+ kal_uint32 lo;
+ kal_uint32 status;
+ kal_uint32 cause;
+ kal_uint32 EPC;
+ kal_uint32 ErrorEPC;
+ kal_uint32 BadVAddr;
+ kal_uint32 Count;
+ kal_uint32 VPEControl;
+ kal_uint32 Context;
+ kal_uint32 ContextConfig;
+ kal_uint32 EntryHi;
+ kal_uint32 ErrCtl;
+#if defined(__MIPS_I7200__)
+ kal_uint32 BadInstr;
+ kal_uint32 BadInstrX;
+#endif
+} EX_CPU_REG_T;
+
+// Dormant Save
+typedef struct _ex_min_cpu_reg_t
+{
+ kal_uint32 RA;
+ kal_uint32 status;
+ kal_uint32 EPC;
+ kal_uint32 cause;
+ kal_uint32 SP;
+ kal_uint32 BadVAddr;
+ kal_uint32 reserved0;
+ kal_uint32 reserved1;
+} EX_CPU_MIN_REG_T;
+
+typedef struct _ex_tc_reg_t
+{
+ EX_GPR_REG_T GPR;
+ kal_uint32 hi;
+ kal_uint32 lo;
+ /* Thread Context per-TC */
+ kal_uint32 TCStatus;
+ kal_uint32 TCBind;
+ kal_uint32 TCRestart;
+ kal_uint32 TCHalt;
+ kal_uint32 TCContext;
+ kal_uint32 TCSchedule;
+#if defined(__MIPS_IA__)
+ kal_uint32 TCScheFBack;
+ kal_uint32 TCOpt;
+#endif
+ kal_uint32 UserLocal;
+ kal_uint32 LLAddr;
+ kal_uint32 EntryHi;
+ kal_uint32 Status;
+#if defined(__MIPS_I7200__)
+ kal_uint32 BatchCacheOpStatus;
+#endif
+#if defined(__MIPS_IA__)
+ kal_uint32 PerfCtl0;
+ kal_uint32 PerfCtl1;
+
+#endif
+ kal_uint32 PerfCnt0;
+ kal_uint32 PerfCnt1;
+#if defined(__MIPS_I7200__)
+ kal_uint32 PerfCnt2;
+ kal_uint32 PerfCnt3;
+#endif
+} EX_TC_REG_T;
+
+typedef struct _ex_vpe_reg_t
+{
+ /* Thread Context per-VPE */
+ kal_uint32 SRSConf0;
+ kal_uint32 SRSCtl;
+ kal_uint32 SRSMap;
+
+ /* Configuration and Status */
+ kal_uint32 Config;
+ kal_uint32 Config2;
+ kal_uint32 Config5;
+ kal_uint32 Config7;
+ kal_uint32 EBase;
+ kal_uint32 IntCtl;
+
+ /*TLB Management */
+ kal_uint32 Index;
+ kal_uint32 EntryLo0;
+ kal_uint32 EntryLo1;
+ kal_uint32 Context;
+ kal_uint32 ContextConfig;
+ kal_uint32 PageMask;
+ kal_uint32 PageGrain;
+ kal_uint32 Wired;
+ kal_uint32 BadVAddr;
+
+ /* Memory Segmentation */
+ kal_uint32 SegCtl0;
+ kal_uint32 SegCtl1;
+ kal_uint32 SegCtl2;
+
+ /* Exception Control */
+ kal_uint32 Cause;
+ kal_uint32 EPC;
+ kal_uint32 ErrorEPC;
+#if defined(__MIPS_I7200__)
+ kal_uint32 BadInstr;
+ kal_uint32 BadInstrX;
+ kal_uint32 BEVVA;
+#endif
+
+ /* Timer */
+ kal_uint32 Count;
+ kal_uint32 Compare;
+
+ /* Cache Management */
+ kal_uint32 ITagLo;
+ kal_uint32 IDataLo;
+ kal_uint32 IDataHi;
+ kal_uint32 DTagLo;
+ kal_uint32 DTagHi;
+ kal_uint32 DDataLo;
+#if defined(__MIPS_IA__)
+ kal_uint32 L23TagLo;
+ kal_uint32 L23DataLo;
+ kal_uint32 L23DataHi;
+#endif
+ kal_uint32 ErrCtl;
+ kal_uint32 CacheErr;
+
+ /* VPE Management per-VPE */
+ kal_uint32 VPEControl;
+ kal_uint32 VPEConf0;
+ kal_uint32 VPEConf1;
+#if defined(__MIPS_IA__)
+ kal_uint32 VPESchedule;
+ kal_uint32 VPEScheFBack;
+#endif
+ kal_uint32 VPEOpt;
+
+
+ /* Performance Monitoring */
+ /* Debug and Trace */
+ kal_uint32 Debug;
+ kal_uint32 DEPC;
+ kal_uint32 WatchLo[NBR_OF_WATCH_REGS];
+ kal_uint32 WatchHi[NBR_OF_WATCH_REGS];
+ kal_uint32 YQMask;
+#if defined(__MIPS_I7200__)
+ kal_uint32 KScratch[NBR_OF_KSCRATCH_REGS];
+#endif
+}EX_VPE_REG_T;
+
+typedef struct _ex_cm2_error_info_t
+{
+ kal_uint32 ErrorMask;
+ kal_uint32 ErrorCause;
+ kal_uint32 ErrorAddr;
+ kal_uint32 ErrorMult;
+} EX_CM2_ERROR_INFO_T;
+
+typedef struct _ex_core_reg_t
+{
+ /* VPE Management per-CORE */
+ kal_uint32 MVPControl;
+ kal_uint32 MVPConf0;
+ kal_uint32 MVPConf1;
+ kal_uint32 CDMMBase;
+#if defined(__MIPS_I7200__)
+ kal_uint32 BatchCacheOpControl;
+ kal_uint32 SRAMCoreControl;
+#endif
+ EX_VPE_REG_T vperegs[NBR_VPE_PER_CORE];
+ EX_TC_REG_T tcregs[NBR_TC_PER_CORE];
+} EX_CORE_REG_T;
+
+typedef struct _ex_core_info_t
+{
+ /* VPE Management per-CORE */
+ kal_uint32 MVPControl;
+ kal_uint32 MVPConf0;
+ kal_uint32 MVPConf1;
+ kal_uint32 CDMMBase;
+#if defined(__MIPS_I7200__)
+ kal_uint32 BatchCacheOpControl;
+ kal_uint32 SRAMCoreControl;
+#endif
+} EX_CORE_INFO_T;
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#define EX_CACHE_LINES_SAVED 4
+typedef struct _ex_interaptiv_t
+{
+ EX_CORE_REG_T coreregs[NBR_CORE];
+ EX_CM2_ERROR_INFO_T cm2_error_info;
+ void *cm2_reg_dump;
+ /* struct CPC_State? */
+ /* struct GIC_State? */
+ /* struct ITC_State? */
+
+ struct l1_icache_line offending_l1_icache_data[EX_CACHE_LINES_SAVED];
+ struct l2_cache_line offending_l2_icache_data[EX_CACHE_LINES_SAVED];
+#if defined(__MIPS_MMU_EXIST__)
+ MIPS_MMU_INFO_T tlbs[SYS_MCU_NUM_VPE][NUMBER_OF_TLBS];
+#endif
+} EX_INTERAPTIV_T;
+#endif /* !__OFFLINE_EX_LOG_PARSER__ */
+
+typedef struct _ex_info_t
+{
+ EX_CPU_REG_T *SST_Exception_Regs;
+ kal_uint32 SST_Exception_Timestamp;
+ kal_uint32 SST_Exception_GLB_Timestamp;
+ exception_enter_category ExceptionEnterCategory;
+ kal_uint16 global_exception_flag;
+ kal_uint8 vpeid;
+ kal_uint8 tcid;
+} EX_INFO_T;
+
+
+/*******************************************************************************
+ * Data Structure Definition - FULL_OFFENDING_INFO for the 1st offender
+ *******************************************************************************/
+#define EX_STACK_DUMP_LEN 7
+typedef struct _ex_full_offending_info_t
+{
+ EX_TC_REG_T tc_info;
+ EX_VPE_REG_T vpe_info;
+ EX_CORE_INFO_T core_info;
+ exception_enter_category ex_enter_category;
+ kal_uint8 pad[3];
+ kal_uint32 stack_dump[EX_STACK_DUMP_LEN];
+} EX_FULL_OFFENDING_INFO_T;
+
+/*******************************************************************************
+ * Data Structure Definition - VICTIM_INFO
+ *******************************************************************************/
+typedef struct _ex_victim_info_t
+{
+ kal_uint8 vpeid;
+ kal_uint8 tcid;
+ exception_enter_category ex_enter_category;
+ kal_uint16 global_exception_flag;
+ kal_uint32 sst_exception_timestamp;
+ kal_uint32 offendingPC;
+ EX_CPU_REG_T cpu_info;
+} EX_VICTIM_INFO_T;
+
+typedef struct _ex_ne_info_t
+{
+ exception_enter_category ex_enter_category;
+ kal_uint16 global_exception_flag;
+ kal_uint32 sst_exception_timestamp;
+ kal_uint32 offendingPC;
+ EX_CPU_REG_T cpu_info;
+} EX_NE_INFO_T;
+
+/*******************************************************************************
+ * Data Structure Definition - Fatal Error in general
+ *******************************************************************************/
+
+#define EX_FATALERR_ANALYSIS_OWNER_LEN 8
+#define EX_FATALERR_ANALYSIS_CORE_LEN 7
+#define EX_FATALERR_DESCRIPTION_PARAM_LEN 16
+#define EX_FATALERR_ANALYSIS_PARAM_LEN 40
+#define EX_FATALERR_GUIDELINE_PARAM_LEN 16
+
+typedef struct ex_fatalerror_code_t
+{
+ kal_uint32 code1;
+ kal_uint32 code2;
+ kal_uint32 code3;
+} EX_FATALERR_CODE_T;
+
+typedef struct ex_analysis_t
+{
+ kal_char offender[EX_UNIT_NAME_LEN];
+ kal_bool is_cadefa_supported;
+ kal_uint8 pad[7];
+
+ // TODO: remove
+ kal_uint32 trace;
+ kal_uint8 param[EX_FATALERR_ANALYSIS_PARAM_LEN];
+} EX_ANALYSIS_T;
+
+typedef struct ex_description_t
+{
+ kal_uint32 trace;
+ kal_uint8 param[EX_FATALERR_DESCRIPTION_PARAM_LEN];
+} EX_DESCRIPTION_T;
+
+typedef struct ex_guideline_t
+{
+ kal_uint32 trace;
+ kal_uint8 param[EX_FATALERR_GUIDELINE_PARAM_LEN];
+} EX_GUIDELINE_T;
+
+
+/*******************************************************************************
+ * Data Structure Definition - Fatal Error extended
+ *******************************************************************************/
+
+#define EX_CTRLBUFF_SRCFILE_LEN 32 /* filename */
+typedef struct
+{
+ kal_char ex_his_owner[EX_UNIT_NAME_LEN]; /* control buffer owner */
+ kal_char ex_his_source[EX_CTRLBUFF_SRCFILE_LEN]; /* source file */
+ kal_uint32 ex_his_line; /* line number */
+ kal_uint32 ex_his_count; /* number of identical entries */
+} EX_CTRLBUFF_HISTORY_T;
+
+typedef struct
+{
+ kal_uint32 ex_buf_RTOS_header1; /* RTOS overhead 1, 0: allocated, else next pointer */
+ kal_uint32 ex_buf_RTOS_header2; /* RTOS overhead 2, pointer to its control block */
+ kal_uint32 ex_buf_KAL_header1; /* KAL overhead 1, header (0xF1F1F1F1) */
+ kal_uint32 ex_buf_KAL_header2; /* KAL overhead 2, task ID */
+ kal_uint32 ex_buf_KAL_header3; /* KAL overhead 3, pointer to its control block) */
+ kal_uint32 ex_buf_poolID; /* Buffer pointer */
+ kal_uint32 ex_buf_KAL_footer1; /* KAL footer: 0xF2F2F2F2 */
+ kal_uint32 ex_buf_KAL_footer2; /* KAL footer appended after size requested */
+} EX_CTRLBUFF_COMMON_T;
+
+typedef struct
+{
+ kal_char ex_buf_source[EX_CTRLBUFF_SRCFILE_LEN]; /* Source file name */
+ kal_uint32 ex_buf_line; /* line number */
+} EX_CTRLBUFF_OWNER_T;
+
+typedef union
+{
+ EX_CTRLBUFF_HISTORY_T history; /* length: 32 */
+ EX_CTRLBUFF_COMMON_T common; /* length: 32 */
+} EX_CTRLBUFF_INFO_T;
+
+typedef struct
+{
+ kal_uint32 ex_ctrlbuf_size; /* offset: +0x13C, length: 4 */ /* control buffer size per entry */
+ kal_uint32 ex_ctrlbuf_num; /* offset: +0x140, length: 4 */ /* total number of entries */
+ EX_CTRLBUFF_INFO_T ex_ctrlbuf_top; /* offset: +0x144, length: 32 */ /* top occupation history node */
+ EX_CTRLBUFF_INFO_T ex_ctrlbuf_second; /* offset: +0x164, length: 32 */ /* second occupation history node */
+ EX_CTRLBUFF_INFO_T ex_ctrlbuf_third; /* offset: +0x184, length: 32 */ /* third occupation history node */
+ EX_CTRLBUFF_OWNER_T ex_monitor[3]; /* offset: +0x1A4, length: 48 */
+ kal_uint32 ex_reserved[2]; /* offset: +0x1D4, length: 16 */ /* reserved */
+} EX_CTRLBUFF_T;
+
+typedef struct
+{
+ module_type ex_his_module; /* module ID */
+ kal_uint8 ex_his_source[EX_UNIT_NAME_LEN]; /* timer name */
+ kal_uint32 ex_his_hf; /* es buffer handling function */
+ kal_uint32 ex_his_count; /* number of identical entries */
+} EX_ESBUFF_HISTORY_T;
+
+typedef struct
+{
+ kal_uint32 ex_esbuf_size; /* offset: +0x13C, length: 4 */ /* event scheduler buffer size per entry */
+ kal_uint32 ex_esbuf_num; /* offset: +0x140, length: 4 */ /* total number of entries */
+ EX_ESBUFF_HISTORY_T ex_esbuf_top; /* offset: +0x144, length: 20 */ /* top occupation history node */
+ EX_ESBUFF_HISTORY_T ex_esbuf_second; /* offset: +0x158, length: 20 */ /* second occupation history node */
+ EX_ESBUFF_HISTORY_T ex_esbuf_third; /* offset: +0x16C, length: 20 */ /* third occupation history node */
+} EX_ESBUFF_T;
+
+typedef struct
+{
+ kal_uint16 ex_q_src_mod; /* source module ID */
+ kal_uint8 ex_q_count; /* total number of identical message */
+ kal_uint8 ex_q_config_entry; /* total number of entries */
+ kal_uint16 ex_q_msg_id; /* message ID */
+ kal_uint16 ex_q_cur_mes_no; /* tatal number of messages left in queue */
+} EX_QUEUE_T;
+
+typedef struct
+{
+ kal_char ex_task_name[EX_UNIT_NAME_LEN]; /* task name */
+ kal_char ex_task_stack_gp[8]; /* guard pattern:STACK_END */
+ kal_uint32 ex_task_cur_status; /* task current status, eg. RUNNING, READY etc */
+ EX_QUEUE_T ex_task_external_q; /* task external queue */
+ EX_QUEUE_T ex_task_internal_q; /* task internal queue */
+ kal_uint32 ex_reserved; /* reserved */
+} EX_TASKINFO_T;
+
+
+
+/*******************************************************************************
+ * Constant Definition and Exported Type - Fatal Error
+ *******************************************************************************/
+
+#define EX_MAX_TASK_DUMP 4
+#define EX_QUEUE_TRACK 20
+typedef struct ex_fatalerror_t
+{
+ EX_FATALERR_CODE_T error_code; /* offset: +0x, length: */
+ EX_ANALYSIS_T analysis; /* offset: +0x, length: */
+
+ union
+ {
+ EX_CTRLBUFF_T ctrl_buff; /* offset: +0x, length: */
+ EX_ESBUFF_T es_buff; /* offset: +0x, length: */
+ EX_TASKINFO_T task_info[EX_MAX_TASK_DUMP]; /* offset: +0x, length: */
+ } info;
+
+ kal_uint32 ext_queue_pending_cnt;
+ kal_uint32 ext_queue_pending[EX_QUEUE_TRACK];
+ EX_DESCRIPTION_T description; /* offset: +0x, length: */
+ EX_GUIDELINE_T guideline; /* offset: +0x, length: */
+} EX_FATALERR_T;
+
+typedef struct ex_nested_fatalerror_t
+{
+ EX_FATALERR_CODE_T error_code; /* offset: +0x, length: */
+} EX_NE_FATALERR_T;
+
+
+/*******************************************************************************
+ * Constant Definition and Exported Type - Assert Failure
+ *******************************************************************************/
+#define EX_HEADER_SIZE sizeof(EX_HEADER_T)
+#define EX_SWVER_LEN sizeof(EX_LOADINFO_T)
+#define EX_ENVINFO_SIZE sizeof(EX_ENVINFO_T)
+#define EX_BASIC_OFFENDING_INFO_SIZE sizeof(EX_BASIC_OFFENDING_INFO_T)
+#define EX_FULL_OFFENDING_INFO_SIZE sizeof(EX_FULL_OFFENDING_INFO_T)
+#define EX_TOTAL_VICTIM_INFO_SIZE ((sizeof(EX_VICTIM_INFO_T))*TOTAL_VICTIM_VPE_COUNT)
+
+#define EX_ASSERTFAIL_FILEPATH_LEN 256
+#define EX_ASSERTFAIL_FILENAME_LEN 64
+#define EX_GUARD_LEN 4
+#define EX_ASSERTFAIL_SIZE EX_ASSERTFAIL_FILEPATH_LEN + \
+ EX_ASSERTFAIL_FILENAME_LEN + \
+ sizeof(kal_uint32) * 4 + \
+ EX_GUARD_LEN
+
+
+#define EX_ASSERTFAIL_DUMP_LEN ((EX_LOG_SIZE - (EX_HEADER_SIZE + EX_SWVER_LEN + \
+ EX_BASIC_OFFENDING_INFO_SIZE + EX_ENVINFO_SIZE + \
+ EX_FULL_OFFENDING_INFO_SIZE + \
+ EX_ASSERTFAIL_SIZE + EX_TOTAL_VICTIM_INFO_SIZE)) & ~(4-1))
+
+
+typedef struct ex_assert_fail_t
+{
+ kal_char filepath[EX_ASSERTFAIL_FILEPATH_LEN];
+ kal_char filename[EX_ASSERTFAIL_FILENAME_LEN]; /* offset: +0xD8, length: 64 */
+ kal_uint32 linenumber; /* offset: +0xF0, length: 4 */
+ kal_uint32 parameters[3]; /* offset: +0xF4, length: 12 */
+ kal_uint8 dump[EX_ASSERTFAIL_DUMP_LEN]; /* offset: +0x100, length: 244 */
+ kal_uint32 custom_param; /* offset: +0x1FC, length: 4 */
+} EX_ASSERTFAIL_T;
+
+typedef struct ex_nested_assert_fail_t
+{
+ kal_char filename[EX_ASSERTFAIL_FILENAME_LEN]; /* length: 64 */
+ kal_uint32 linenumber; /* length: 4 */
+} EX_NE_ASSERTFAIL_T;
+
+
+/*******************************************************************************
+ * Globally Exported Data Structure
+ *******************************************************************************/
+typedef union
+{
+ EX_FATALERR_T fatalerr;
+ EX_ASSERTFAIL_T assert;
+} EX_CONTENT_T;
+
+typedef union
+{
+ EX_NE_FATALERR_T fatalerr;
+ EX_NE_ASSERTFAIL_T assert;
+} EX_NE_CONTENT_T;
+
+/* Standard strutcure of an exception log */
+typedef struct ex_exception_log_t
+{
+ EX_HEADER_T header; /* offset: +0x0 length: */
+ EX_LOADINFO_T load_info; /* offset: +0x, length: */
+ EX_BASIC_OFFENDING_INFO_T basic_info;
+ EX_ENVINFO_T envinfo; /* offset: , length: */
+ EX_FULL_OFFENDING_INFO_T full_info;
+ EX_CONTENT_T content; /* offset: , length: */
+ EX_VICTIM_INFO_T victim_info[TOTAL_VICTIM_VPE_COUNT];
+} EX_LOG_T;
+
+typedef struct ex_nested_exception_log_t
+{
+ exception_type ex_type;
+ EX_NE_INFO_T info;
+ EX_NE_CONTENT_T content;
+} EX_NE_LOG_T;
+
+/* parameter to ex_init_log */
+typedef struct
+{
+ exception_type type;
+ kal_bool ext;
+ kal_uint32 *code1;
+ kal_uint32 *code2;
+ kal_uint32 *code3;
+ kal_uint32 e1;
+ kal_uint32 e2;
+ kal_uint32 e3;
+ ASSERT_DUMP_PARAM_T *dump_param;
+ kal_uint32 custom_param;
+} EX_INIT_LOG_PARAM_T;
+
+/*******************************************************************************
+ * ELT nvram reading format
+ *******************************************************************************/
+/*==========================================*/
+/* NOTE: The structure is frozen; offset of content should be FIXED. */
+/*==========================================*/
+/* TODO */
+
+
+/***************************** -structure end- *******************************/
+//PRAGMA_END_PACK_STRUCT
+/*******************************************************************************
+ * Globally Exported macro
+ *******************************************************************************/
+#define EX_LOG_DESCRIPTION_PARAM ex_log_ptr->content.fatalerr.description.param
+#define EX_LOG_ANALYSIS_PARAM ex_log_ptr->content.fatalerr.analysis.param
+#define EX_LOG_ANALYSIS_OWNER ex_log_ptr->content.fatalerr.analysis.offender
+#define EX_LOG_ANALYSIS_CADEFA ex_log_ptr->content.fatalerr.analysis.is_cadefa_supported
+#define EX_LOG_GUIDELINE_PARAM ex_log_ptr->content.fatalerr.guideline.param
+#if !defined(__MTK_TARGET__) || (defined(__MTK_TARGET__) && defined(DRV_DEBUG))
+#define SET_EX_STEP(x)
+#define GET_EX_STEP()
+#define GET_NE_STEP()
+#define GET_EX_STEP_BY_VPE(vpe)
+#define GET_NE_STEP_BY_VPE(vpe)
+#define SET_HS(core, status)
+#define GET_HS(core)
+#else
+#define SET_EX_STEP(x) ex_set_step_logging(x)
+#define GET_EX_STEP() ex_get_step_logging(kal_get_current_vpe_id(), KAL_FALSE)
+#define GET_NE_STEP() ex_get_step_logging(kal_get_current_vpe_id(), KAL_TRUE)
+#define GET_EX_STEP_BY_VPE(vpe) ex_get_step_logging((kal_uint32)vpe, KAL_FALSE)
+#define GET_NE_STEP_BY_VPE(vpe) ex_get_step_logging((kal_uint32)vpe, KAL_TRUE)
+#define SET_HS(core, status) ex_set_value((kal_uint32*)ex_##core##_hs_ptr, status)
+#define GET_HS(core) ex_get_value((kal_uint32*)ex_##core##_hs_ptr)
+#endif /* !defined(__MTK_TARGET__) || (defined(__MTK_TARGET__) && defined(DRV_DEBUG)) */
+
+
+/*******************************************************************************
+ * Globally Exported Function Prorotype
+ *******************************************************************************/
+
+extern void ex_init_log();
+extern kal_uint32 ex_get_corenum();
+extern void ex_init_nested_log(kal_uint32 ex_category);
+extern void ex_post_init_log();
+extern void ex_define_main_reason();
+extern void ex_save_log();
+extern void ex_output_log(void);
+extern kal_int8 ex_init_ctrl_buff_log(kal_uint32 *target_ptr, kal_uint32 code1, kal_uint32 code2, kal_char **offender_source_file_full_name);
+extern kal_int8 ex_init_es_buff_log(kal_uint32 *target_ptr);
+extern void ex_memory_dump_init(void);
+extern void ex_output_loadinfo(kal_bool is_meta);
+extern kal_bool ex_isNested(void);
+extern kal_uint32* INT_GetExlog(void);
+extern kal_bool ex_IsSupport_OnlineSST_For_GAT(kal_int32 code1);
+extern void ex_output_afound(afound_output_types output_types);
+
+#ifdef __MTK_TARGET__
+extern void ex_reset_hw(void);
+extern void ex_reboot(void);
+
+extern void ex_init_step_logging(void);
+extern void ex_set_step_logging(kal_uint16 start_step);
+extern void ex_fire_extern_step_logging(kal_uint32 info);
+extern kal_bool INT_IsAnyCore_Enter_Exception();
+extern void INT_EnterExceptionForOtherCore();
+extern kal_uint32 sst_get_main_exception_vpe(void);
+extern kal_uint32 sst_get_main_exception_core(void);
+
+extern kal_bool ex_init_pcmon();
+extern kal_bool ex_init_nested_pcmon();
+extern void ex_init_dsm();
+extern void ex_hw_dump();
+extern void ex_hw_data_save();
+extern void KickWDT();
+extern void ex_switchWDT_phase1();
+
+#if defined(__TST_MODULE__)
+extern void ex_reappear_log(void);
+extern void ex_cadefa(kal_bool bypass_nested, kal_bool is_meta);
+extern void ex_cadefa_common(kal_bool bypass_nested, kal_bool bLocalCore, EX_LOG_T * log_ptr);
+extern void ex_output_for_meta(void);
+#else
+#define ex_reappear_log()
+#define ex_cadefa(bypass_nested, kal_meta)
+#define ex_cadefa_common(bypass_nested, bLocalCore, log_ptr)
+#define ex_output_for_meta()
+#endif /* __TST_MODULE__ */
+
+#endif /* __MTK_TARGET__ */
+
+#ifdef __STACK_ALIGN_MPU__
+kal_uint32 ex_stack_overflow_check_by_mpu(void);
+#endif
+
+extern kal_uint8 sst_increment_exception_count();
+extern void ex_backup_exception_count();
+/*******************************************************************************
+ * Globally Exported variables
+ *******************************************************************************/
+extern EX_LOG_T *ex_log_ptr;
+#if defined(__MTK_TARGET__)
+extern kal_atomic_int32 SST_occupied_core_op_atomic[];
+extern kal_uint32 sst_dc_offshoot_vpeid;
+extern kal_uint32 sst_hw_offshoot_vpeid;
+extern kal_uint32 INT_Exception_Type;
+extern kal_uint32 sst_offending_coreid;
+extern kal_uint32 sst_offending_vpeid;
+extern kal_uint32 sst_offending_tcid;
+extern kal_uint32 INT_Exception_GLBTS;
+
+extern void sst_snprintf(char *s, kal_uint32 size, const char *template, ...);
+#else
+#define sst_snprintf kal_snprintf
+#endif /* __MTK_TARGET__ */
+
+
+#endif /* _EX_ITEM_H */
+
+
diff --git a/mcu/service/sst/include/ex_mem_manager.h b/mcu/service/sst/include/ex_mem_manager.h
new file mode 100644
index 0000000..76bb58b
--- /dev/null
+++ b/mcu/service/sst/include/ex_mem_manager.h
@@ -0,0 +1,344 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_memory_manager.h
+ *
+ * Project:
+ * --------
+ * Moly
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ *
+ * removed!
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+ * removed!
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+ * removed!
+ *
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+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __EX_MEM_MANAGER_H__
+#define __EX_MEM_MANAGER_H__
+
+
+
+
+#if !defined(__ASSEMBLER__)
+#include "ex_mem_manager_public.h"
+
+/*******************************************************************************
+ * Define data structure.
+ *******************************************************************************/
+typedef enum {
+ EMM_QUERY_FAIL = 0x1,
+ EMM_CHECK_FAIL = 0x2,
+ EMM_NO_CCCI_FAIL = 0x4,
+ EMM_PERMISSION_FAIL = 0x8,
+ EMM_UNSUPPORTED_SRC_TYPE_FAIL = 0x10,
+ EMM_CHECK_SUCCESS = 0x80,
+} EMM_QUERY_RESULT;
+
+typedef enum {
+ EMM_BUF_INMD_FROM_AP = 0x1,
+ EMM_BUF_EXMD_STATIC,
+ EMM_BUF_MAX,
+} EMM_BUF_SOURCE;
+
+#define EMM_MINIMUM_SIZE (sizeof(kal_uint32))
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define EMM_EXRECORD_LEN (1024*10)
+/*EMM BOOTUPSTARTUPTRACE_START 76 bytes from EMM Debug info start*/
+#define EMM_BOOTUPTRACE_START (EMM_EXRECORD_LEN+76)
+
+#define EMM_DBGINFO_LEN 1024
+#define EMM_USERDIRINFO_LEN (3*1024)
+#define EMM_BOOTUPTRACE_LEN (3*1024)
+
+#define EMM_IDLETASK_SIZE (352/EMM_MINIMUM_SIZE)
+#define EMM_SLP_SIZE (68/EMM_MINIMUM_SIZE)
+#define EMM_DORMANT_SIZE (96/EMM_MINIMUM_SIZE)
+#define EMM_ELM_SIZE (300/EMM_MINIMUM_SIZE)
+#define EMM_BUS_SIZE (8*12/EMM_MINIMUM_SIZE)
+#define EMM_SWLA_SIZE (1440/EMM_MINIMUM_SIZE)
+#define EMM_NVRAM_DBG_SIZE (616/EMM_MINIMUM_SIZE)
+#else
+#error No config yet
+#endif
+
+
+#define EMM_INFO_TOTAL_LEN (EMM_DBGINFO_LEN+EMM_USERDIRINFO_LEN)
+
+
+/* dont use SYS_MCU_NUM_CORE SYS_MCU_NUM_VPE here because there might different
+ * value for different variant in same generation. use here max value
+ * for this generation */
+#if defined(__MD97__) || defined(__MD97P__)
+#define EMM_CORENUM 4
+#define EMM_VPENUM 3 // per core
+#else
+#error No config yet
+#endif
+
+
+#define EMM_BLOCKNUM (EMM_CORENUM)
+#define EMM_BOOTUPTRACE_BLOCKLEN (((EMM_BOOTUPTRACE_LEN/EMM_BLOCKNUM)>>2)<<2)
+
+#define EMM_EXRECORD_WORDLEN (EMM_EXRECORD_LEN/EMM_MINIMUM_SIZE)
+#define EMM_BOOTUPTRACE_BLOCKWORDLEN (EMM_BOOTUPTRACE_BLOCKLEN/EMM_MINIMUM_SIZE)
+#define EMM_DBGINFO_WORDLEN (EMM_DBGINFO_LEN/EMM_MINIMUM_SIZE)
+#define EMM_USERDIRINFO_WORDLEN (EMM_USERDIRINFO_LEN/EMM_MINIMUM_SIZE)
+
+
+#define EMM_INDICATOR 0x12345678 /* magic num */
+
+#define EMM_DIRINFO_GUARD_PATTERN_START(_index) ((0xEDEC << 16) | _index)
+#define EMM_DIRINFO_GUARD_PATTERN_END(_index) ((0xCEDE << 16) | _index)
+
+#define EMM_HS2_TRACE_START_PATTERN 0x48533230
+
+typedef struct _EMM_INFO {
+ EMM_BUF_SOURCE bufSourceType;
+ kal_uint32 u32Mainbuf_Addr;
+ kal_uint32 bufLen;
+
+ kal_uint32 *pexRecord;
+ kal_uint32 exRecordLen;
+
+ kal_uint32 *pBootupTraceInfo[EMM_BLOCKNUM];
+ kal_uint32 BootupTraceWordLen[EMM_BLOCKNUM];
+
+ kal_uint32 *pdbgInfo;
+ kal_uint32 dbgInfoWordLen;
+
+ kal_uint32 *pUserDirInfo; //user direct info
+ kal_uint32 userDirInfoWordLen; //user direct info
+
+ kal_uint8 bootTraceFinish;
+ kal_uint8 resultFail;
+} EMM_INFO;
+
+typedef struct {
+ kal_uint32 magic_number;
+ kal_uint32 last_write_index[EMM_CORENUM*EMM_VPENUM];
+ kal_uint32 last_write_vpe;
+ kal_uint32 reserved[2]; // make header 16 byte alignment for better looks
+ kal_uint32 log[EMM_INDEX_MAX];
+} EMM_DBGINFO_STRUC;
+
+typedef struct _EMM_BUF_CONTENT {
+ kal_uint32 exRecord[EMM_EXRECORD_WORDLEN];
+ kal_uint32 dbgInfo[EMM_DBGINFO_WORDLEN];
+} EMM_BUF_CONTENT;
+
+typedef struct _EMM_SWLA_PAIR {
+ kal_char name[4];
+ kal_uint32 timestamp;
+ kal_uint8 core_id;
+ kal_uint8 tc_id;
+ kal_uint8 reserved[2];
+} EMM_SWLA_PAIR;
+
+#if defined (__HIF_CCCI_SUPPORT__) && defined(__CCCI_PRODUCT_TYPE_THIN_MODEM__)
+typedef enum _SAP_SHM_QUERY_RESULT {
+ SAP_SHM_EXRECORD_QUERY_FAIL = 0x1,
+ SAP_SHM_EXRECORD_CHECKING_FAIL = 0x2,
+ SAP_SHM_MEMDUMP_QUERY_FAIL = 0x4,
+ SAP_SHM_MEMDUMP_CHECKING_FAIL = 0x8
+} SAP_SHM_QUERY_RESULT;
+
+typedef struct _SAP_SHM {
+ kal_uint32 ex_addr; // small ap exception record @ SHM
+ kal_uint32 ex_size;
+ kal_uint32 mem_addr; // small ap 64 MB memory
+ kal_uint32 mem_size;
+ SAP_SHM_QUERY_RESULT resultFail;
+} SAP_SHM;
+
+#define THIN_MODEM_SHM_SAP_EX_STATUS_OFFSET 8
+#define THIN_MODEM_SHM_MD_EX_STATUS_OFFSET 12
+extern SAP_SHM sap_shm;
+#endif
+
+#define EMM_BUS_SYSINFO_PAD_COMPENSATE_SIZE (\
+ /*sizeof(pattern)*/ EMM_MINIMUM_SIZE + \
+ /*sizeof(last_write_index)*/ EMM_MINIMUM_SIZE * (EMM_CORENUM*EMM_VPENUM) + \
+ /*sizeof(last_write_vpe)*/ EMM_MINIMUM_SIZE + \
+ /*sizeof(reserved[2])*/ EMM_MINIMUM_SIZE * 2 + \
+ /*sizeof(EMM_SYSINFO)*/ EMM_MINIMUM_SIZE * EMM_INDEX_MAX \
+ )
+
+typedef struct _EMM_BUF_SYSINFO {
+ kal_uint32 pattern;
+ kal_uint32 last_write_index[EMM_CORENUM*EMM_VPENUM];
+ kal_uint32 last_write_vpe;
+ kal_uint32 reserved[2];
+ kal_uint32 EMM_SYSINFO[EMM_INDEX_MAX];
+ kal_uint32 pad[(EMM_DBGINFO_LEN - EMM_BUS_SYSINFO_PAD_COMPENSATE_SIZE)/EMM_MINIMUM_SIZE];
+ kal_uint32 EDE_IDLETASK_HEAD;
+ kal_uint32 EDE_IDLETASK_STEP[EMM_IDLETASK_SIZE];
+ kal_uint32 EDE_IDLETASK_TAIL;
+ kal_uint32 EDE_SLP_HEAD;
+ kal_uint32 EDE_SLP_STEP[EMM_SLP_SIZE];
+ kal_uint32 EDE_SLP_TAIL;
+ kal_uint32 EDE_DOR_HEAD;
+ kal_uint32 EDE_DOR_STEP[EMM_DORMANT_SIZE];
+ kal_uint32 EDE_DOR_TAIL;
+ kal_uint32 EDE_ELM_HEAD;
+ kal_uint32 EDE_ELM_STEP[EMM_ELM_SIZE];
+ kal_uint32 EDE_ELM_TAIL;
+ kal_uint32 EDE_BUS_HEAD;
+ kal_uint32 EDE_BUS_STEP[EMM_BUS_SIZE];
+ kal_uint32 EDE_BUS_TAIL;
+ kal_uint32 EDE_SWLA_HEAD;
+ EMM_SWLA_PAIR EDE_SWLA[EMM_CORENUM][EMM_SWLA_SIZE*EMM_MINIMUM_SIZE/sizeof(EMM_SWLA_PAIR)/EMM_CORENUM];
+ kal_uint32 EDE_SWLA_TAIL;
+ kal_uint32 EDE_NVRAM_DBG_HEAD;
+ kal_uint32 EDE_NVRAM_DBG[EMM_NVRAM_DBG_SIZE];
+ kal_uint32 EDE_NVRAM_DBG_TAIL;
+} EMM_SYSINFO_STRUC;
+
+#endif /* __ASSEMBLER__ */
+#endif /* __EX_MEM_MANAGER_H__ */
+
diff --git a/mcu/service/sst/include/ex_trc.h b/mcu/service/sst/include/ex_trc.h
new file mode 100644
index 0000000..d7439c5
--- /dev/null
+++ b/mcu/service/sst/include/ex_trc.h
@@ -0,0 +1,336 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_trc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _EX_TRC_H
+#define _EX_TRC_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+#if !defined(GEN_FOR_PC) && !defined(__MAUI_BASIC__)
+#include"ex_trc_mod_ex_log_utmd.h"
+#endif
+#endif /* _EX_TRC_H */
diff --git a/mcu/service/sst/include/ex_trc_mod_ex_log_utmd.json b/mcu/service/sst/include/ex_trc_mod_ex_log_utmd.json
new file mode 100644
index 0000000..8ff00d7
--- /dev/null
+++ b/mcu/service/sst/include/ex_trc_mod_ex_log_utmd.json
@@ -0,0 +1,1734 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_EX_LOG",
+ "startGen": "Legacy",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "EX_LOG_SPLIT_ENV_INFO": {
+ "apiType": "index",
+ "format": "========================= Basic Environment Info ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_FACTORY_BOOT": {
+ "apiType": "index",
+ "format": "boot mode: factory mode",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_NORMAL_BOOT": {
+ "apiType": "index",
+ "format": "boot mode: normal mode",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_USBMS_BOOT": {
+ "apiType": "index",
+ "format": "boot mode: USBMS mode",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_UNKNOWN_BOOT_MODE": {
+ "apiType": "index",
+ "format": "boot mode: unknown mode",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_EARLY_STAGE": {
+ "apiType": "index",
+ "format": "- under init stage(early stage)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_UNDER_SCHEDULING": {
+ "apiType": "index",
+ "format": "- under scheduling",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_TOTAL_CORE_NUM": {
+ "apiType": "index",
+ "format": "total core num: %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SW_VER": {
+ "apiType": "index",
+ "format": "software version: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SW_PROJECT": {
+ "apiType": "index",
+ "format": "software project: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SW_BUILDTIME": {
+ "apiType": "index",
+ "format": "build time: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SPLIT_BASIC_OFFENDING_INFO": {
+ "apiType": "index",
+ "format": "========================= Basic offending VPE info ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_OFFENDING_INFO": {
+ "apiType": "index",
+ "format": "Offending VPE: %u, Offending TC: %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TYPE_EX_TYPE": {
+ "apiType": "index",
+ "format": "Exception type: %Mexception_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_TIMESTAMP": {
+ "apiType": "index",
+ "format": "exception timestamp: USCNT = 0x%08X, GLB_TS = 0x%08X, frameno = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_EXECUTIONUNIT": {
+ "apiType": "index",
+ "format": "execution unit: %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_STACIPOINTER": {
+ "apiType": "index",
+ "format": "stack pointer: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_LR": {
+ "apiType": "index",
+ "format": "lr: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_PC": {
+ "apiType": "index",
+ "format": "offending pc: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_TC_STATUS": {
+ "apiType": "index",
+ "format": "task status: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BASIC_PROCESSING_LISR": {
+ "apiType": "index",
+ "format": "processing_lisr: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SPLIT_SYS_ENV_INFO": {
+ "apiType": "index",
+ "format": "========================= System Environment Info ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_INTERRUPT_MASK": {
+ "apiType": "index",
+ "format": "interrupt mask: 0x%08X 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_ELM_STATUS": {
+ "apiType": "index",
+ "format": "ELM status: %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_HEALTH_CHECK_TITLE": {
+ "apiType": "index",
+ "format": "[System Healthy Check]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_HEALTHY": {
+ "apiType": "index",
+ "format": "diagnosis: healthy",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_INTSRAMCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: ISPRAM corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_SHAREDINTSRAMCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: shared internal SRAM corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_L2SRAMCCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: cached L2SRAM corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_L2SRAMNCCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: non-cached L2SRAM corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_SYSSTACKCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: system stack corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_TASKSTACKCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: task stack corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_HISRSTACKCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: HISR stack corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_VECTORTABLECORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: Interrupt Vector corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_LOCKWAITEDTOOLONG": {
+ "apiType": "index",
+ "format": "diagnosis: some lock has been waited too long",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_CACHECORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: instruction cache corruption",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_CACHECORRUPT_2": {
+ "apiType": "index",
+ "format": "Please note that it might be cross core access if corruption address is in ispram",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_DEADLOCK": {
+ "apiType": "index",
+ "format": "diagnosis: System deadlocked",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_HELDTOOLONG": {
+ "apiType": "index",
+ "format": "diagnosis: some lock has been held too long",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_L2CACHELOCKCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: Static L2Cache lock area corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_DYNAMICL2CACHELOCKCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: Dynamic L2Cache lock area corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_MPUCORRUPT": {
+ "apiType": "index",
+ "format": "diagnosis: MPU settings corrupted",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_MPUCORRUPT_SEGMENT": {
+ "apiType": "index",
+ "format": "First corrupted segment is %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_MPUCORRUPT_REGION": {
+ "apiType": "index",
+ "format": "First corrupted region is %d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DIAGNOSIS_OWNER": {
+ "apiType": "index",
+ "format": "owner: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DEADLOCK_OUTPUT_OWNER_SL": {
+ "apiType": "index",
+ "format": " %dus: spinlock(0x%x) %s obtained by %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DEADLOCK_OUTPUT_OWNER_ITC": {
+ "apiType": "index",
+ "format": " %dus: HW ITC(0x%x) %Mkal_itc_lock_id obtained by %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DEADLOCK_OUTPUT_LOCK_SL": {
+ "apiType": "index",
+ "format": " %dus: %s started waiting spinlock(0x%x) %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_DEADLOCK_OUTPUT_LOCK_ITC": {
+ "apiType": "index",
+ "format": " %dus: %s started waiting HW ITC(0x%x) %Mkal_itc_lock_id",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_HELDLOCK_OUTPUT_LOCK_SL": {
+ "apiType": "index",
+ "format": " %s has been holding spinlock(0x%x) %s for %dus when exception occured",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_HELDLOCK_OUTPUT_LOCK_ITC": {
+ "apiType": "index",
+ "format": " %s has been holding HW ITC(0x%x) %Mkal_itc_lock_id for %dus when exception occured",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_WAITLOCK_OUTPUT_LOCK_SL": {
+ "apiType": "index",
+ "format": " %s has been waiting spinlock(0x%x) %s for %dus when exception occured",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DIAGINFO_WAITLOCK_OUTPUT_LOCK_ITC": {
+ "apiType": "index",
+ "format": " %s has been waiting HW ITC(0x%x) %Mkal_itc_lock_id for %dus when exception occured",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SPLIT_OFFENDING_VPE_ANALYSIS": {
+ "apiType": "index",
+ "format": "========================= Offending VPE Analysis ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_FILENAME": {
+ "apiType": "index",
+ "format": "filename: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_FULLPATH": {
+ "apiType": "index",
+ "format": "path: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_LINE": {
+ "apiType": "index",
+ "format": "line: %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_EXT1": {
+ "apiType": "index",
+ "format": "ext1: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_EXT2": {
+ "apiType": "index",
+ "format": "ext2: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_EXT3": {
+ "apiType": "index",
+ "format": "ext3: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_ADDR": {
+ "apiType": "index",
+ "format": "offending address: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_MODID": {
+ "apiType": "index",
+ "format": "offending module id: %Mmodule_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_MOFID": {
+ "apiType": "index",
+ "format": "offending module id: %Mmof_index_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_DUMP_TITLE": {
+ "apiType": "index",
+ "format": "dump:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ASSERT_DUMP": {
+ "apiType": "index",
+ "format": " 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FATALERR_MSG": {
+ "apiType": "index",
+ "format": "[%d] fatal error (0x%x): %Mkal_error_str - %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FATALERR_ERROR_CODE1": {
+ "apiType": "index",
+ "format": "fatal error code 1: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FATALERR_ERROR_CODE2": {
+ "apiType": "index",
+ "format": "fatal error code 2: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FATALERR_ERROR_CODE3": {
+ "apiType": "index",
+ "format": "fatal error code 3: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CC_EX_MSG": {
+ "format": "[%d] Cross Triggered Exception by %s : ect status(0x%08X)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_SIZE": {
+ "apiType": "index",
+ "format": "ctrl buff size = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_NUM": {
+ "apiType": "index",
+ "format": "# of ctrl buff entries = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_TOP": {
+ "apiType": "index",
+ "format": "top occupier",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_PREV": {
+ "apiType": "index",
+ "format": "previous buffer pointer",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_RTOS_HEADER1": {
+ "apiType": "index",
+ "format": " RTOS header 1 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_RTOS_HEADER2": {
+ "apiType": "index",
+ "format": " RTOS header 2 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_KAL_HEADER1": {
+ "apiType": "index",
+ "format": " KAL header 1 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_KAL_HEADER2": {
+ "apiType": "index",
+ "format": " KAL header 2 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_KAL_HEADER3": {
+ "apiType": "index",
+ "format": " KAL header 3 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_BUFF_POOLID": {
+ "apiType": "index",
+ "format": " buffer pool id = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_KAL_FOOTER1": {
+ "apiType": "index",
+ "format": " kal footer 1 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_KAL_FOOTER2": {
+ "apiType": "index",
+ "format": " kal footer 2 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_FILENAME": {
+ "apiType": "index",
+ "format": " source = %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_LR": {
+ "apiType": "index",
+ "format": " Caller Address = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_COMMON_LINE": {
+ "apiType": "index",
+ "format": " line = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_HISTORY_OWNER": {
+ "apiType": "index",
+ "format": " owner = %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_HISTORY_FILENAME": {
+ "apiType": "index",
+ "format": " filename = %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_HISTORY_LINE": {
+ "apiType": "index",
+ "format": " line = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_HISTORY_LR": {
+ "apiType": "index",
+ "format": " Caller Address = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_HISTORY_COUNT": {
+ "apiType": "index",
+ "format": " count = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_SECOND": {
+ "apiType": "index",
+ "format": "second occupier",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_CURR": {
+ "apiType": "index",
+ "format": "current buffer pointer",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_THIRD": {
+ "apiType": "index",
+ "format": "third occupier",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CTRLBUF_NEXT": {
+ "apiType": "index",
+ "format": "next buffer pointer",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_SIZE": {
+ "apiType": "index",
+ "format": "es buff size = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_NUM": {
+ "apiType": "index",
+ "format": "# of es buff entries = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_HISTORY_TIMERNAME": {
+ "apiType": "index",
+ "format": " event scheduler name = %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_HISTORY_MODULEID": {
+ "apiType": "index",
+ "format": " dest module id = %Mmodule_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_HISTORY_HANDLEFUNC": {
+ "apiType": "index",
+ "format": " handler function address = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_HISTORY_COUNT": {
+ "apiType": "index",
+ "format": " count = %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_TOP": {
+ "apiType": "index",
+ "format": "top occupier",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_SECOND": {
+ "apiType": "index",
+ "format": "second occupier",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ESBUF_THIRD": {
+ "apiType": "index",
+ "format": "third occupier",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_NAME": {
+ "apiType": "index",
+ "format": "TaskName = %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_STACK_GP": {
+ "apiType": "index",
+ "format": "TaskStackGuardPattern = %c%c%c%c%c%c%c%c",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_STATUS": {
+ "apiType": "index",
+ "format": "task current status = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_EXTQ": {
+ "apiType": "index",
+ "format": "task external queue",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_Q_SRC_MOD_ID": {
+ "apiType": "index",
+ "format": " src mod id = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_Q_QCOUNT": {
+ "apiType": "index",
+ "format": " # of identical msg = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_Q_MSG_ID": {
+ "apiType": "index",
+ "format": " msg id = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_Q_CUR_MSG_NO": {
+ "apiType": "index",
+ "format": " # of pending msg = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_Q_CONFIG_ENTRY": {
+ "apiType": "index",
+ "format": " # of queue entries = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TASK_INFO_INTQ": {
+ "apiType": "index",
+ "format": "task internal queue",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_EXT_Q_PENDING_CNT": {
+ "apiType": "index",
+ "format": "number of messages in the external queue: %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_EXT_Q_PENDING_TITLE": {
+ "apiType": "index",
+ "format": "messages in the external queue:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_ENVINFO_EXT_Q_PENDING": {
+ "apiType": "index",
+ "format": " %Mmsg_type",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SPLIT_FULL_OFFENDING_INFO": {
+ "apiType": "index",
+ "format": "========================= Detailed Offending VPE Info ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FULL_OFFENDING_INFO_ENTRY_TYPE": {
+ "apiType": "index",
+ "format": "Entry Type = %Mexception_enter_category",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_GPR_REG_TITLE": {
+ "apiType": "index",
+ "format": "[CPU Register Info] (MIPS o32/p32 Name)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_1": {
+ "apiType": "index",
+ "format": "R0 (ZERO) = 0x%08X, R1 (AT) = 0x%08X, R2 (V0/T4)= 0x%08X, R3 (V1/T5)= 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_2": {
+ "apiType": "index",
+ "format": "R4 (A0) = 0x%08X, R5 (A1) = 0x%08X, R6 (A2) = 0x%08X, R7 (A3) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_3": {
+ "apiType": "index",
+ "format": "R8 (T0/A4)= 0x%08X, R9 (T1/A5)= 0x%08X, R10(T2/A6)= 0x%08X, R11(T3/A7)= 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_4": {
+ "apiType": "index",
+ "format": "R12(T4/T0)= 0x%08X, R13(T5/T1)= 0x%08X, R14(T6/T2)= 0x%08X, R15(T7/T3)= 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_5": {
+ "apiType": "index",
+ "format": "R16(S0) = 0x%08X, R17(S1) = 0x%08X, R18(S2) = 0x%08X, R19(S3) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_6": {
+ "apiType": "index",
+ "format": "R20(S4) = 0x%08X, R21(S5) = 0x%08X, R22(S6) = 0x%08X, R23(S7) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_7": {
+ "apiType": "index",
+ "format": "R24(T8) = 0x%08X, R25(T9) = 0x%08X, R26(K0) = 0x%08X, R27(K1) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CPU_REG_8": {
+ "apiType": "index",
+ "format": "R28(GP) = 0x%08X, R29(SP) = 0x%08X, R30(S8) = 0x%08X, R31(RA) = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_HILO": {
+ "apiType": "index",
+ "format": "HI = 0x%08X, LO = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_EXCTRL_REG_TITLE": {
+ "apiType": "index",
+ "format": "[Exception Control Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_EXCTRL": {
+ "apiType": "index",
+ "format": "Cause = 0x%08X, EPC = 0x%08X, ErrorEPC = 0x%08X, (Status = 0x%08X)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_EXCBAD": {
+ "apiType": "index",
+ "format": "BadInstr = 0x%08X, BadInstrX = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CFG_STATUS_REG_TITLE": {
+ "apiType": "index",
+ "format": "[Configuration and Status Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CFG1": {
+ "apiType": "index",
+ "format": "EBase = 0x%08X, Status = 0x%08X, IntCtrl = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CFG2": {
+ "apiType": "index",
+ "format": "Config = 0x%08X, Config2 = 0x%08X, Config5 = 0x%08X, Config7 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TC_REG_TITLE": {
+ "apiType": "index",
+ "format": "[Thread Context Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TC1": {
+ "apiType": "index",
+ "format": "TCStatus = 0x%08X, TCBind = 0x%08X, TCRestart = 0x%08X, TCHalt = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TC2": {
+ "apiType": "index",
+ "format": "TCContext = 0x%08X, TCSchedule = 0x%08X, TCScheFBack= 0x%08X, TCOpt = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TC3": {
+ "apiType": "index",
+ "format": "SRSConf0 = 0x%08X, SRSCtl = 0x%08X, SRSMap = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_VPE_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[VPE Management Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_VPE1": {
+ "apiType": "index",
+ "format": "VPEControl = 0x%08X, VPEConf0 = 0x%08X, VPEConf1 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_VPE2": {
+ "apiType": "index",
+ "format": "VPESchedule= 0x%08X, VPEScheFBack= 0x%08X, VPEOpt = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_VPE3": {
+ "apiType": "index",
+ "format": "MVPControl = 0x%08X, MVPConf0 = 0x%08X, MVPConf1 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_VPE4": {
+ "apiType": "index",
+ "format": "VPEControl = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TLB_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[TLB Management Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TLB1": {
+ "apiType": "index",
+ "format": "Index = 0x%08X, EntryLo0 = 0x%08X, EntryLo1 = 0x%08X, EntryHi = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TLB2": {
+ "apiType": "index",
+ "format": "Context = 0x%08X, ContextConfig= 0x%08X, PageMask = 0x%08X, PageGrain = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TLB3": {
+ "apiType": "index",
+ "format": "Wired = 0x%08X, BadVAddr = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TLB4": {
+ "apiType": "index",
+ "format": "EntryHi = 0x%08X, Context = 0x%08X, ContextConfig = 0x%08X, BadVAddr = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_MEMSEG_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[Memory Segmentation Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_MEMSEG": {
+ "apiType": "index",
+ "format": "SegCtl0 = 0x%08X, SegCtl1 = 0x%08X, SegCtl2 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_CACHEMGT_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[Cache Management Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CMGT1": {
+ "apiType": "index",
+ "format": "ITagLo = 0x%08X, IDataLo = 0x%08X, IDataHi = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CMGT2": {
+ "apiType": "index",
+ "format": "DTagLo = 0x%08X, DTagHi = 0x%08X, DDataLo = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CMGT3": {
+ "apiType": "index",
+ "format": "L23TagLo = 0x%08X, L23DataLo = 0x%08X, L23DataHi = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CMGT4": {
+ "apiType": "index",
+ "format": "ErrCtl = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_CMGT5": {
+ "apiType": "index",
+ "format": "BCOpCtl = 0x%08X, BCOpStatus= 0x%08X, CoreCtrl = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TIMER_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[Timer Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_TIMER": {
+ "apiType": "index",
+ "format": "Count = 0x%08X, Compare = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_COUNT": {
+ "apiType": "index",
+ "format": "Count = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DBGTRC_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[Debug and Trace Register Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_DBGTRC1": {
+ "apiType": "index",
+ "format": "WatchLo0 = 0x%08X, WatchLo1 = 0x%08X, WatchLo2 = 0x%08X, WatchLo3 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_DBGTRC2": {
+ "apiType": "index",
+ "format": "WatchHi0 = 0x%08X, WatchHi1 = 0x%08X, WatchHi2 = 0x%08X, WatchHi3 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_DBGTRC3": {
+ "apiType": "index",
+ "format": "Debug = 0x%08X, DEPC = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_DBGTRC4": {
+ "apiType": "index",
+ "format": "WatchLo4 = 0x%08X, WatchLo5 = 0x%08X, WatchLo6 = 0x%08X, WatchLo7 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_DBGTRC5": {
+ "apiType": "index",
+ "format": "WatchHi4 = 0x%08X, WatchHi5 = 0x%08X, WatchHi6 = 0x%08X, WatchHi7 = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_UMOD_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[User Mode Support Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_UMOD": {
+ "apiType": "index",
+ "format": "YQMask = 0x%08X, LLAddr = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_MMAP_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[Memory Mapped Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_REG_MMAP": {
+ "apiType": "index",
+ "format": "CDMMBase = 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_STACKDUMP_INFO_TITLE": {
+ "apiType": "index",
+ "format": "[Stack Info]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FULLINFO_STACKDUMP_TITLE": {
+ "apiType": "index",
+ "format": "stack dump:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_FULLINFO_STACKDUMP": {
+ "apiType": "index",
+ "format": " [ADDR:0x%08X]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SPLIT_VICTIM_VPE_INFO": {
+ "apiType": "index",
+ "format": "========================= Victim VPE Info ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_VICTIM_BASIC_INFO": {
+ "apiType": "index",
+ "format": "Victim VPE: %u, TC: %u, order: 0x%x, USCNT: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TYPE_EX_ENTER_TYPE": {
+ "apiType": "index",
+ "format": "Exception type: %Mexception_enter_category",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TYPE_EX_ENTER_TYPE_NMI": {
+ "apiType": "index",
+ "format": "Please note!! This vpe could not receive CTI interrupt so most likely it had interrupt disabled for long time",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_TYPE_EX_ENTER_TYPE_GEN_REFILL": {
+ "apiType": "index",
+ "format": "Please note!! This vpe had simultaneous exception",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_NEWLINE": {
+ "apiType": "index",
+ "format": "",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_L1_TIMING_CHECK_ASSERT1": {
+ "format": "L1 timing check fail.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "EX_LOG_L1_TIMING_CHECK_ASSERT2": {
+ "format": "Use the stack dump to find out who disables IRQ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_HIT_BP": {
+ "format": "BreakPoint(0x%08X) is hit",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_HIT_WP_TBC": {
+ "format": "WritePoint(Unknown) is hit at address 0x%08X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_HIT_WP": {
+ "format": "WritePoint(0x%08X) is hit at address 0x%08X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDDBG_HIT_Debug": {
+ "format": "[%d]0x%08X, 0x%08X, 0x%08X",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "EX_LOG_SPLIT_EXTEND_INFO": {
+ "apiType": "index",
+ "format": "========================= Extra Info ===========================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_TITLE": {
+ "apiType": "index",
+ "format": "PCMON Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PIPED_PCPAIR_TITLE": {
+ "apiType": "index",
+ "format": "Piped IA:[PC, TC, FRC]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PIPED_PCPAIR": {
+ "apiType": "index",
+ "format": "(PC)[ADDR:0x%08X], TC: %u, FRC: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PCPAIR_TITLE": {
+ "apiType": "index",
+ "format": "PC History:[PC->PC, FRC, TAG]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PCPAIR": {
+ "apiType": "index",
+ "format": "(PC)[ADDR:0x%08X] -> (PC)[ADDR:0x%08X], FRC: 0x%08X, TAG: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PIPED_PDPAIR_TITLE": {
+ "apiType": "index",
+ "format": "Piped DA:[PC, Data Address, TC, FRC]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PIPED_PDPAIR": {
+ "apiType": "index",
+ "format": "(PC)[ADDR:0x%08X], (DATA ADDR)0x%08X, TC: %u, FRC: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PDPAIR_TITLE": {
+ "apiType": "index",
+ "format": "DC History:[PC, Data Address, FRC, TAG]",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PCMON_PDPAIR": {
+ "apiType": "index",
+ "format": "(PC)[ADDR:0x%08X], (DATA ADDR)0x%08X, FRC: 0x%08X, TAG: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BUSERR_TITLE": {
+ "apiType": "index",
+ "format": "Bus Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BUSERR_VALUE": {
+ "apiType": "index",
+ "format": " 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BUSMPUERR_TITLE": {
+ "apiType": "index",
+ "format": "Bus MPU Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BUSMPUERR_IOCU_VIO_ADDR": {
+ "apiType": "index",
+ "format": " IOCU_VIO_ADDR: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_BUSMPUERR_IRQSTS_VIO_MPU": {
+ "apiType": "index",
+ "format": " %s: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_EMIMPUERR_MCU_TITLE": {
+ "apiType": "index",
+ "format": "EMI MPU Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_EMIMPUERR_MCU": {
+ "apiType": "index",
+ "format": " %s: 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PLLINFO_TITLE": {
+ "apiType": "index",
+ "format": "PLL Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_PLLINFO_VAR": {
+ "apiType": "index",
+ "format": " %s: 0x%08X (%d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DVFS_TITLE": {
+ "apiType": "index",
+ "format": "DVFS Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DVFS_VAR": {
+ "apiType": "index",
+ "format": " %s: 0x%08X (%d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_MDMPU_TITLE": {
+ "apiType": "index",
+ "format": "MDMPU Info:",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_MDMPU_VAR1": {
+ "apiType": "index",
+ "format": " coreid=%d, ASCR= 0x%08X, CONFIG= 0x%08X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_MDMPU_VAR2": {
+ "apiType": "index",
+ "format": " RI= 0x%02X, WI= 0x%02X, XI= 0x%02X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_MDMPU_VAR3": {
+ "apiType": "index",
+ "format": " Enable= 0x%02X, MATCH= 0x%02X, NUM= 0x%02X",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_SPLIT": {
+ "apiType": "index",
+ "format": "======================================================================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "EX_LOG_DUMMY": {
+ "apiType": "index",
+ "format": "",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_Separator": {
+ "apiType": "index",
+ "format": "******************************************",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_Label": {
+ "apiType": "index",
+ "format": "Label: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_SWVersion": {
+ "apiType": "index",
+ "format": "SWVersion: %s %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_BuildTime": {
+ "apiType": "index",
+ "format": "BuildTime: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_DSPBuildTime": {
+ "apiType": "index",
+ "format": "DSP_BuildTime: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_ExceptionSource": {
+ "apiType": "index",
+ "format": "ExceptionSource: %s%s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_ExceptionCategory": {
+ "apiType": "index",
+ "format": "ExceptionCategory: %MEX_MAINCONTENT_TYPE_T",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_BriefException": {
+ "apiType": "index",
+ "format": "BriefException: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_ExceptionTimestamp": {
+ "apiType": "index",
+ "format": "ExceptionTimestamp: %u",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_HandlingOrder": {
+ "apiType": "index",
+ "format": "HandlingOrder: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_1_OffendingFile": {
+ "apiType": "index",
+ "format": "1_OffendingFile: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_2_OffendingAddress": {
+ "apiType": "index",
+ "format": "2_OffendingAddress: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_3_Offender": {
+ "apiType": "index",
+ "format": "3_Offender: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_4_Helper": {
+ "apiType": "index",
+ "format": "4_Helper: (%s)Default_%s%s1stLine",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_5_ExtraInfo": {
+ "apiType": "index",
+ "format": "5_ExtraInfo: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "SST_AFOUND_6_ModuleOwner": {
+ "apiType": "index",
+ "format": "6_ModuleOwner: %s",
+ "traceClass": "TRACE_ERROR"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "EX_LOG"
+}
diff --git a/mcu/service/sst/include/md32_boot.h b/mcu/service/sst/include/md32_boot.h
new file mode 100644
index 0000000..4068a53
--- /dev/null
+++ b/mcu/service/sst/include/md32_boot.h
@@ -0,0 +1,196 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * md32_boot.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef MD32_BOOT_H
+#define MD32_BOOT_H
+
+#include "md32_boot_public.h"
+#include "md32_file.h"
+#include "reg_base.h"
+#include "dsp_control_public.h"
+#define REG_WRITE32(addr, val) do{*((volatile kal_uint32 *)(addr)) = val;}while(0)
+#define REG_READ32(var, addr) do{var = *((volatile kal_uint32 *)(addr));}while(0)
+#define MD32_LOADER_REG(ptr) (*(volatile kal_uint32*)(ptr))
+
+/* MD32 core sys */
+//#define MD32_RAKE_SYS (BASE_MADDR_RAKE)
+#define MD32_NUM 1
+
+/* platform dependent setting*/
+#if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6779) || defined(__MD97__) || defined(__MD97P__)
+#define MD32_MAGIC_KEY (0x62930000)
+#else
+#error "Unknown Platform!!"
+#endif
+
+/* MD32 offset */
+#define MD32_PM (0x00380000)
+#define MD32_DM (0x003E0000)
+#define MD32_CMIF (0x00358000)
+#define MD32_BTSLV (0x35100C)
+#define MD32_DBG_EN (0x351010)
+#define MD32_DMP_EN (0x35101C)
+#define MD32_PERI_CTRL (0x351000)
+
+#define MD32_RAKE_PM BASE_MADDR_RAKESYS_PM
+#define MD32_RAKE_DM BASE_MADDR_RAKESYS_RAKE_DM_ARB
+
+#define MD32_RAKE_BTSLV (0x35100C)
+#define MD32_RAKE_POWER (0x351004)
+#define MD32_RAKE_PM_CRC (0x50)
+#define MD32_RAKE_DM_CRC (0x54)
+
+#define MD32_USIP0_TH0_BTSLV (0x400)
+#define MD32_USIP0_TH1_BTSLV (0x404)
+#define MD32_USIP1_TH0_BTSLV (0x408)
+#define MD32_USIP1_TH1_BTSLV (0x40C)
+
+#if defined(MT6763)|| defined(MT6739) || defined(MT6771) || defined(MT6295M) || defined(MT6765) || defined(MT6761) || defined(MT3967) || defined(MT6779) || defined(__MD97__) || defined(__MD97P__)
+ #define MD32_RAKE_SYS BASE_MADDR_RAKESYS_RAKE_INST_DEC
+ #define MD32_RAKE_GLOBAL_CON BASE_MADDR_RAKESYS_GLOBAL_CON
+
+ #define MD32_USIP_SYS BASE_MADDR_MDMCU_USIP_CROSS_CORE_CTRL
+
+ #define MD32_KB (1024)
+ #define RAKE_PM_SZ (96 * MD32_KB)
+ #define RAKE_DM_SZ (48 * MD32_KB)
+ #define RAKE_CMIF_SZ (8 * MD32_KB)
+
+#else
+#error "Unknown Platform!!"
+#endif
+
+#if defined(__MD32_PM_PROTECT_SUPPORT__)
+#define MD32_PM_PROTECT_EN_OFF (0x351020)
+#define MD32_PM_PROTECT_BNK_OFF (0x351024)
+#define MD32_PM_PROTECT_INSTR_OFF (0x351028)
+#define MD32_UDF_INST_VAL (0x00F400F4)
+#endif /* __MD32_PM_PROTECT_SUPPORT__ */
+
+/* MD32 setting */
+#define MD32_PERI_CTRL_MAGIC (0x80A180A1)
+#define MD32_DFE_MEM_BNK_SZ (16 * 1024)
+#define MD32_BRP_MEM_BNK_SZ ( 8 * 1024)
+#define MD32_ENABLE (MD32_MAGIC_KEY | 0x1)
+#define MD32_DISABLE (MD32_MAGIC_KEY | 0x0)
+
+/* Timestamp for GDMA callback function internal operation */
+struct gdma_cb_timestamp {
+ unsigned long start;
+ unsigned long hwitc_start_end;
+ unsigned long who_use_gdma;
+ unsigned long who_wait_gdma;
+ unsigned long activeate_LISR_before;
+ unsigned long activeate_LISR_end;
+ unsigned long hwitc_end_before;
+ unsigned long hwitc_end_end;
+ unsigned long end;
+};
+
+/* Timestamp of GDMA DDL callback function internal operation */
+struct gdma_cb_ddl_timestamp {
+ unsigned long start;
+ unsigned long who_use_gdma;
+ unsigned long check;
+ unsigned long config;
+ unsigned long ddl;
+ unsigned long data_sync;
+ unsigned long gdma_set_config;
+ unsigned long gdma_start_cmd;
+ unsigned long enablc_clk;
+ unsigned long send_interrupt;
+ unsigned long end;
+};
+
+typedef enum
+{
+ LOADER_SRAM_TYPE_PM = 0,
+ LOADER_SRAM_TYPE_DM = 1,
+} LOADER_SRAM_TYPE;
+
+typedef struct {
+ unsigned long dump_en;
+ unsigned long gate_status;
+ unsigned long golden_pm_crc;
+ unsigned long golden_dm_crc;
+ unsigned long reg_pm_crc;
+ unsigned long reg_dm_crc;
+ unsigned long ori_pm_crc;
+ unsigned long ori_pm;
+ unsigned long ori_dm_crc;
+ unsigned long ori_dm;
+ unsigned long new_pm_crc;
+ unsigned long new_pm;
+ unsigned long new_dm_crc;
+ unsigned long new_dm;
+ unsigned long end_pm;
+ unsigned long end_dm;
+ DDL_MODE ddl_mode;
+ LOADER_SRAM_TYPE sram_type;
+
+} CRC_DBG_Info_T;
+#endif /* MD32_BOOT_H */
+
diff --git a/mcu/service/sst/include/md32_excep_hdlr.h b/mcu/service/sst/include/md32_excep_hdlr.h
new file mode 100644
index 0000000..e8b39a7
--- /dev/null
+++ b/mcu/service/sst/include/md32_excep_hdlr.h
@@ -0,0 +1,189 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * md32_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * This file provides typedefs and definiton for PS index trace.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MD32_EXCEP_HDLR_H__
+#define __MD32_EXCEP_HDLR_H__
+
+#if !defined(__OFFLINE_EX_LOG_PARSER__)
+#include "md32_boot.h"
+#include "kal_general_types.h"
+#endif /*__OFFLINE_EX_LOG_PARSER__*/
+#include "ex_public.h"
+
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#define MD32_NUM_CORES 1
+#define MD32_EX_FILENAME_SIZE 64
+#define MD32_EX_CORE_NAME_SIZE 10
+#define MD32_EX_ASSERT_LINE_TYPE_NUMBER 0x1
+#define MD32_EX_ASSERT_EXT_TYPE_NUMBER 0x2
+#define MD32_EX_FATAL_ERROR_TYPE_NUMBER 0x3
+#define MD32_EX_FATAL_ERROR_EXT_TYPE_NUMBER 0x4
+#define MD32_EX_FILL_FINISH_PATTERN 0xFD32FD32
+#define MD32_EX_INIT_PATTERN 0x62935566
+//#define MD32_EXCEPTION_SYNC_TIME 0x100000 // please use EX_MD32_SYNC_TIME in cc_ex_item.h
+#define MD32_EXCEPTION_FLOW_HANDSHAKE_SYNC_TIME 0x10000
+#define MD32_EXCEPTION_PCORE_WAIT_L1CORE_REPORT_TIME 0x100000
+#define MD32_MPU_MAX_REGION_SIZE 8
+#define MOS_EX_TRACE_BUFFER_SIZE 64
+
+/*******************************************************************************
+ * CMIF Exception record structure for MD32
+ *******************************************************************************/
+typedef enum{
+ MD32_EX_NONE,
+ MD32_ASSERT_LINE = MD32_EX_ASSERT_LINE_TYPE_NUMBER,
+ MD32_ASSERT_EXT = MD32_EX_ASSERT_EXT_TYPE_NUMBER,
+ MD32_FATAL_ERROR = MD32_EX_FATAL_ERROR_TYPE_NUMBER,
+ MD32_CTI_EXCEPTION = MD32_EX_FATAL_ERROR_EXT_TYPE_NUMBER,
+ MD32_EX_END=0xff
+}MD32_EX_TYPE;
+
+typedef struct{
+ kal_uint32 line_num;
+ kal_uint32 para1;
+ kal_uint32 para2;
+ kal_uint32 para3;
+ char* filepath_ptr;
+ kal_char file_name[MD32_EX_FILENAME_SIZE];
+}MD32_EX_CMIF_AssertLog;
+
+typedef struct{
+ kal_uint32 error_status; //is ex_code[0]
+ kal_uint32 error_pc; //is ex_code[1]
+ kal_uint32 error_lr; //is lr
+ kal_uint32 error_address; //is daabtad
+ kal_uint32 error_code1; //is ex_code[0]
+ kal_uint32 error_code2; //is ex_code[1]
+ kal_uint8 error_section;
+}MD32_EX_CMIF_FatalErrorLog;
+
+typedef union{
+ MD32_EX_CMIF_AssertLog assert;
+ MD32_EX_CMIF_FatalErrorLog fatal;
+}MD32_EX_CMIF_AssertFatalErrorLog;
+
+typedef struct {
+ MD32_EX_TYPE except_type; //type
+ kal_uint32 except_stat; //exception flow's status
+ MD32_EX_CMIF_AssertFatalErrorLog except_content; //assert or exception log
+}MD32_ExceptionLogCore_T;
+
+/** Causion: The total log size for 3* MD32s is 392 bytes.
+ It means there are 128 bytes for each MD32s core */
+typedef struct {
+ kal_uint32 core_num;
+ MD32_ExceptionLogCore_T core_error;
+}MD32_ExceptionLog_T;
+
+typedef enum{
+ MD32_BRP_FAIL_BIT_MASK = (1 << 0),
+ MD32_DFE_FAIL_BIT_MASK = (1 << 1),
+ MD32_DFE1_FAIL_BIT_MASK = (1 << 2),
+ MD32_RAKE_FAIL_BIT_MASK = (1 << 3)
+}MD32_EX_CORE_BIT_MASK_TYPE;
+
+/*Below are md32_ex_hdlr_trace.c*/
+typedef struct{
+ kal_uint32 finish_fill;
+ kal_uint32 boot_rdy;
+ kal_uint32 ex_flow_progress;
+}MD32_EX_FLOW_TYPE;
+
+typedef enum{
+ MD32_EX_ABNORMAL_RESET = 0x1,
+ MD32_EX_INSTRUCTION_ABORT = 0x10,
+ MD32_EX_UNDEFINED_INSTRUCTION_ABORT = 0x13,
+ MD32_EX_DATA_ABORT = 0x30,
+ MD32_EX_MPU_PERMISSION_ERROR = 0x32,
+ MD32_EX_UNALIGNED_MEMORY_ACCESS = 0x33,
+ MD32_EX_DIVIDED_BY_ZERO = 0x34,
+ MD32_EX_HARDWARE_LOOP_OVERFLOW = 0x35,
+ MD32_EX_PMU_EXCEPTION = 0xE0,
+ MD32_EX_CTI_EXCETPION = 0x120,
+ MD32_EX_MOS_INTERNAL_ERROR = 0x200,
+ MD32_EX_MOS_VIC_UNREGISTER_INTERRUPT = 0x201,
+ MD32_EX_MOS_CIRQ_UNREGISTER_INTERRUPT = 0x202,
+ MD32_EX_MOS_CHECK_STACK_GUARD_PATTERN_FAIL = 0x203,
+ MD32_EX_MOS_CMIF_UNREGISTER_INTERRUPT = 0x204,
+ MD32_EX_MOS_ERROR_ECT = 0x300
+}MD32_EX_ERROR_CODE_TYPE;
+
+
+/*******************************************************************************
+ * Function delcation
+ *******************************************************************************/
+extern void INT_GetMD32ExceptionRecord(MD32_ExceptionLog_T *record);
+extern void INT_GetMD32DumpMemoryInfo(kal_uint32 **info, unsigned short *count, kal_uint8* region_config);
+extern kal_bool INT_SyncMD32ExceptionInfo(void);
+extern void INT_EnableMD32MemoryDump(void);
+extern void INT_DumpMD32ExceptionInfo(EX_TRACE_TYPE trace_type/*0=cadefa*/, kal_char* sys_info_str, kal_uint32 len);
+extern kal_bool MD32_IsSyncFinished(void);
+extern void MD32_SetSyncFinished(void);
+extern void INT_GetMD32ExceptionHandshakeInit(void);
+extern void INT_GetMD32BBMemoryInfo(void);
+extern kal_char* INT_GetMD32CoreName(void);
+
+
+#endif /* __MD32_EXCEP_HDLR_H__ */
+
diff --git a/mcu/service/sst/include/md32_file.h b/mcu/service/sst/include/md32_file.h
new file mode 100644
index 0000000..b2939aa
--- /dev/null
+++ b/mcu/service/sst/include/md32_file.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * md32_file.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef MD32_FILE_H
+#define MD32_FILE_H
+#include "md32_boot_public.h"
+
+
+#endif /* MD32_FILE_H */
diff --git a/mcu/service/sst/include/md32_trc.h b/mcu/service/sst/include/md32_trc.h
new file mode 100644
index 0000000..41b4480
--- /dev/null
+++ b/mcu/service/sst/include/md32_trc.h
@@ -0,0 +1,118 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * md32_trc.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+ TRC_MSG(MD32_EX_LOG_ASSERT, "[MD32(RAKE)] Assert fail: %s - %d 0x%x 0x%x 0x%x")
+ TRC_MSG(MD32_EX_LOG_UNDEF, "[MD32(RAKE)] Fatal error - undefined instruction: pc 0x%x, lr 0x%x")
+ TRC_MSG(MD32_EX_LOG_ABORT, "[MD32(RAKE)] Fatal error - %s: pc 0x%x, address 0x%x, sp 0x%x, lr 0x%x, interrupt_level %d")
+ TRC_MSG(MD32_EX_LOG_UND_IRQ, "[MD32(RAKE)] Fatal error - %s: 0x%x, interrupt_level %d")
+ TRC_MSG(MD32_EX_LOG_UND_CMIF_IRQ, "[MD32(RAKE)] Fatal error - %s: isr_num %d, lr 0x%x, interrupt_level %d")
+ TRC_MSG(MD32_EX_LOG_CTI, "[MD32(RAKE)] Fatal error - CTI Error")
+ TRC_MSG(MD32_EX_LOG_STACK_CORRUPT, "[MD32(RAKE)] Fatal error - %s: sp 0x%x, lr 0x%x, interrupt_level %d")
+ TRC_MSG(MD32_EX_LOG_ECT, "[MD32(RAKE)] Fatal error - ECT ERROR: code2 0x%x, lr 0x%x, interrupt_level %d")
+ TRC_MSG(MD32_EX_LOG_DEFAULT, "[MD32(RAKE)] Fatal error: code1 0x%x, code2 0x%x, sp 0x%x, lr 0x%x, interrupt_level %d")
+
+ TRC_MSG(MD32_EX_LOG_IN_SLEEP, "[MD32(RAKE)] Core is in sleep mode, so the exception flow is not active")
+ TRC_MSG(MD32_EX_LOG_WRONG_PATTERN, "[MD32(RAKE)] The CMIF Pattern is 0x%x, RAKE may not finish exception flow")
+ TRC_MSG(MD32_EX_LOG_BIN_BUILD_INFO, "[MD32(%s)] Project: %s Flavor: %s BuildTime: %s Label: %s")
+
+ TRC_MSG(MD32_EX_LOG_EX_FLOW_PROGRESS, "[%s] [MD32(%s)] Exception flow status: %s")
+
+ TRC_MSG(MD32_EX_LOG_CMIF_REACHABLE, "CMIF status from L1 core is %s")
+
+ TRC_MSG(MD32_COMMON_DOWNLOAD_NOT_DONE_INFO, "[%s] first boot common part not yet download done...")
+ TRC_MSG(MD32_DDL_DOWNLOAD_NOT_DONE_INFO, "[%s] first boot ddl part not yet download done...")
+ TRC_MSG(MD32_COMMON_DOWNLOAD_DONE_INFO, "[%s] first boot common part download done...")
+ TRC_MSG(MD32_DDL_DOWNLOAD_DONE_INFO, "[%s] first boot ddl part download done...")
+ TRC_MSG(MD32_DDL_STATUS_BIN_MODE_INFO, "[DDL][%s] ddl_status: 0x%X, ddl_bin_mode: 0x%X")
+
+
diff --git a/mcu/service/sst/include/md32_user_init.h b/mcu/service/sst/include/md32_user_init.h
new file mode 100644
index 0000000..0105f9c
--- /dev/null
+++ b/mcu/service/sst/include/md32_user_init.h
@@ -0,0 +1,7 @@
+#ifndef MD32_USER_INIT_H
+#define MD32_USER_INIT_H
+#include "kal_public_api.h"
+
+kal_uint32 MD32_User_Init(void);
+
+#endif /* MD32_USER_INIT_H */
\ No newline at end of file
diff --git a/mcu/service/sst/include/md_boot_check.h b/mcu/service/sst/include/md_boot_check.h
new file mode 100644
index 0000000..48eabe3
--- /dev/null
+++ b/mcu/service/sst/include/md_boot_check.h
@@ -0,0 +1,14 @@
+
+#ifndef _MD_BOOT_CHECK_H
+#define _MD_BOOT_CHECK_H
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "kal_public_api.h"
+
+extern volatile kal_uint32 md_boot_check_val;
+extern volatile kal_uint32 md_boot_check_val2;
+
+void check_md_boot_mode(void);
+
+#endif /* !_MD_BOOT_CHECK_H */
diff --git a/mcu/service/sst/include/mddbg.h b/mcu/service/sst/include/mddbg.h
new file mode 100644
index 0000000..10ba279
--- /dev/null
+++ b/mcu/service/sst/include/mddbg.h
@@ -0,0 +1,216 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mddbg.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Modem debugging related implementation
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __SST_MDDBG__
+#define __SST_MDDBG__
+
+#include "mddbg_public.h"
+
+#if !defined(DISABLE_MDDBG_FUNCTION)
+#include "kal_public_api.h"
+#include "ex_item.h"
+#endif
+
+
+#if defined(__MIPS_IA__) || defined(__MIPS_I7200__)
+#if defined(__MD93__)
+#define IRQ_MDDBG_CODE IRQ_SW_LISR22_CODE
+#endif
+#if defined(__MD95__)|| defined(__MD97__)|| defined(__MD97P__)
+#define IRQ_MDDBG_CODE IRQ_SW_LISR27_CODE
+#endif
+#endif
+
+#define MAX_CONFIG_VPE_NUM CONFIG_MAX_VPE
+
+#if defined(___MIPS_IA__) || defined(__MD95__)
+ #define MAX_BP_NUM 2
+ #define MAX_WP_NUM 1
+#elif defined(__MIPS_I7200__) || defined(__MD97__)|| defined(__MD97P__)
+ #define MAX_BP_NUM 4
+ #define MAX_WP_NUM 3
+#else
+ #error "incompatible architecture"
+#endif
+
+#if !defined(DISABLE_MDDBG_FUNCTION)
+/* MDDBG Flags */
+#define MDDBG_CTRL_BY_ICE (1UL<< 0)
+#define MDDBG_CTRL_BY_TARGET (1UL<< 1)
+#define MDDBG_CTRL_INIT_VAL (1UL<<30)
+#define MDDBG_MODE_M2H (1UL<<29)
+#define MDDBG_MODE_COND_CHECK (1UL<<28)
+#define MDDBG_MODE_LOG_ONLY (1UL<<27)
+#define MDDBG_MODE_TASK_INIT_SET (1UL<<26)
+
+
+enum mddbg_def_db{
+ MDDBG_VAR_COUNT=16U,
+ MDDBG_CONDITION_BUFFER=128U,
+ MDDBG_BP_MASK_OFFSET=0U,
+ MDDBG_WP_MASK_OFFSET=8U,
+ /* ILM Comands, bit15-0 are reserved for BP/WP */
+ MDDBG_CMD_SETBP = 1U<<31,
+ MDDBG_CMD_SETWP = 1U<<30,
+ MDDBG_CMD_REMOVEBP = 1U<<29,
+ MDDBG_CMD_REMOVEWP = 1U<<28,
+ MDDBG_CMD_MONITOR = 1U<<27,
+ MDDBG_CMD_M2H = 1U<<26,
+ MDDBG_CMD_LOG = 1U<<25, /* Output log, the MONITOR must be 1 */
+ MDDBG_CMD_QUERY = 1U<<24, /* Query Status */
+#if defined(__MIPS_I7200__)
+ MDDBG_CMD_VERSION = 1,
+#endif
+ CHIP_BP_CNT=MAX_BP_NUM,
+ CHIP_WP_CNT=MAX_WP_NUM,
+#if defined(__MIPS_I7200__)
+ MDDBG_CORES_PER_MODULE = 3,
+#endif
+ CHIP_CORE_CNT = CONFIG_MAX_VPE, /*VPE Num*/
+
+};
+
+
+typedef struct mddbg_req{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+ kal_uint32 cmd; //setting flags, which kinds of parameter is enabled, enable/disable/query
+ kal_uint32 proc_idx;
+ kal_uint32 bpAddr[CHIP_BP_CNT];
+ kal_uint32 bpMask[CHIP_BP_CNT];
+ kal_uint32 wpAddr[CHIP_WP_CNT];
+ kal_uint32 wpMask[CHIP_WP_CNT];
+ kal_uint32 wpType[CHIP_WP_CNT];
+ kal_uint32 var[MDDBG_VAR_COUNT];
+}mddbg_req_struct;
+
+typedef struct mddbg_response{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+ kal_uint32 cmd; //setting flags, which kinds of parameter is enabled, enable/disable/query
+ kal_uint32 proc_idx;
+ kal_uint32 bpAddr[CHIP_BP_CNT];
+ kal_uint32 bpMask[CHIP_BP_CNT];
+ kal_uint32 wpAddr[CHIP_WP_CNT];
+ kal_uint32 wpMask[CHIP_WP_CNT];
+ kal_uint32 wpType[CHIP_WP_CNT];
+ kal_uint32 var[MDDBG_VAR_COUNT];
+}mddbg_response_struct;
+
+extern void mddbg_backup(void);
+extern void mddbg_restore(void);
+extern void mddbg_init(void);
+
+#endif /* !DISABLE_MDDBG_FUNCTION */
+
+typedef struct mddbg_bp_config_t{
+ kal_uint32 addr;
+ kal_uint32 addr_mask;
+ kal_uint32 return_addr;
+}mddbg_bp_config_t;
+
+typedef struct mddbg_wp_config_t{
+ kal_uint32 addr;
+ kal_uint32 addr_mask;
+ kal_uint32 type;
+ kal_uint32 return_addr;
+}mddbg_wp_config_t;
+
+
+void mddbg_isr_lisr(void);
+
+
+#endif /* __SST_MDDBG__ */
+
diff --git a/mcu/service/sst/include/mddbg_trc.h b/mcu/service/sst/include/mddbg_trc.h
new file mode 100644
index 0000000..dae1cbf
--- /dev/null
+++ b/mcu/service/sst/include/mddbg_trc.h
@@ -0,0 +1,106 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cs_trc.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _MDDBG_TRC_H
+#define _MDDBG_TRC_H
+
+
+ /* Set Watchpoint, Breakpoint via ELT inject message function */
+/* TRC_MSG(MDDBG_HIT_BP, "BreakPoint(0x%08X) is hit")
+ TRC_MSG(MDDBG_HIT_WP_TBC, "WritePoint(Unknown) is hit at address 0x%08X")
+ TRC_MSG(MDDBG_HIT_WP, "WritePoint(0x%08X) is hit at address 0x%08X")
+ TRC_MSG(MDDBG_HIT_Debug, "[%d]0x%08X, 0x%08X, 0x%08X")
+*/
+ TRC_MSG(MDDBG_API_UT_ENABLE, "mddbg_enableAll(%d) : %d")
+ TRC_MSG(MDDBG_API_UT_DISABLE, "mddbg_disable() : %d")
+ TRC_MSG(MDDBG_API_UT_QUERY, "mddbg_query() : %d, bp_cnt = %d, wp_cnt = %d")
+ TRC_MSG(MDDBG_API_UT_ENABLE_BPS, "mddbg_enable_bps() : %d")
+ TRC_MSG(MDDBG_API_UT_DISABLE_BPS, "mddbg_disable_bps() : %d")
+ TRC_MSG(MDDBG_API_UT_SET_BP, "mddbg_set_bp(0x%08X, %d) : %d")
+ TRC_MSG(MDDBG_API_UT_ENABLE_WPS, "mddbg_enable_wps() : %d")
+ TRC_MSG(MDDBG_API_UT_DISABlE_WPS, "mddbg_disable_wps() : %d")
+ TRC_MSG(MDDBG_API_UT_SET_WP, "mddbg_set_wp(0x%08X, %d, %d, %d) : %d")
+ TRC_MSG(MDDBG_API_UT_SET_WP_RANGE, "mddbg_set_wp_range(0x%08X, 0x%08X, %d, %d) : %d")
+ TRC_MSG(MDDBG_API_UT_READ_MEM, "Read Memory (0x%08X, %d) = %d")
+ TRC_MSG(MDDBG_API_UT_WRITE_MEM, "Write Memory (0x%08X) = %d")
+ TRC_MSG(MDDBG_API_UT_SET_BP_PARAM, "[MDDBG]Breakpoint addr = 0x%08X, control = 0x%08X")
+ TRC_MSG(MDDBG_API_UT_SET_BP_IDX, "set_idx = %d")
+ TRC_MSG(MDDBG_API_UT_SET_WP_TEXT, "wcr:0x%08X, wp_addr:0x%08X, byte_number:%d, access_type:%d, enable:%d")
+
+
+#endif /* _MDDBG_TRC_H */
+
diff --git a/mcu/service/sst/include/memoryTest.h b/mcu/service/sst/include/memoryTest.h
new file mode 100644
index 0000000..50d20c4
--- /dev/null
+++ b/mcu/service/sst/include/memoryTest.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ex_item.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Header file for exception handling
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _MEMORY_TEST_H
+#define _MEMORY_TEST_H
+
+/************************************
+ *
+ * High-level feature options.
+ *
+ ***********************************/
+
+#define EMI_PERFORMANCE_TEST
+
+
+/************************************
+ *
+ * Definition
+ *
+ ***********************************/
+// EMI_PERFORMANCE_TEST_SIZE must >= EMI_STABILITY_TEST_SIZE
+
+#if defined(MT6268)
+
+#define EMI_PERFORMANCE_TEST_SIZE 512
+#define EMI_STABILITY_TEST_SIZE 256
+
+#elif defined(MT6238) || defined(MT6239) || defined(MT6235B) /* MT6276 || MT6256 || MT6268 */
+
+#define EMI_PERFORMANCE_TEST_SIZE 512
+#define EMI_STABILITY_TEST_SIZE 256
+
+#elif defined(MT6253L) || defined(MT6253T) || defined(MT6268A) || defined(MT6270A) /* MT6276 || MT6256 || MT6268 */
+
+#define EMI_PERFORMANCE_TEST_SIZE 256
+#define EMI_STABILITY_TEST_SIZE 256
+
+#else /* MT6276 || MT6256 || MT6268 */
+
+/**
+ * MT6225 || MT6268T || MT6268H || MT6223 || MT6223P
+ */
+
+#define EMI_PERFORMANCE_TEST_SIZE (KEY_STREAM_LEN)
+#define EMI_STABILITY_TEST_SIZE 128
+
+#endif /* MT6276 || MT6256 || MT6268 */
+
+
+/************************************
+ *
+ * Enum
+ *
+ ***********************************/
+
+typedef enum ADV_RAM_TEST_OPTION
+{
+ ADV_RAM_TEST_OPTION_TEST_DURATION
+}ADV_RAM_TEST_OPTION_T;
+
+
+
+#endif /* _MEMORY_TEST_H */
+
+
diff --git a/mcu/service/sst/include/sonic_control.h b/mcu/service/sst/include/sonic_control.h
new file mode 100644
index 0000000..cbde45e
--- /dev/null
+++ b/mcu/service/sst/include/sonic_control.h
@@ -0,0 +1,57 @@
+#ifndef _SONIC_CONTROL_H_
+#define _SONIC_CONTROL_H_
+
+#include "kal_public_api.h"
+#include "sonic_control_public.h"
+#include "reg_base.h"
+#include "dsp_header_define_csif_memory.h"
+#include "btdma_public.h"
+#include "csif_l1core_public_api.h"
+#include "dsp_public_dbgc.h"
+#if defined(__MD97P__)
+//ToDo: Add idle signal to deactivate mcore
+#else
+#include "dsp_public_eintc.h"
+#endif
+
+/********************************/
+/* Structure/Enum Define */
+/********************************/
+typedef enum{
+ SONIC_THREAD0,
+ SONIC_THREAD1,
+ SONIC_THREAD2,
+#if (!(defined(MT6853) && defined(__PALMER_SIMULATION__)) && !(defined(MT6833) || defined(MT6877)))
+ SONIC_THREAD3,
+#endif
+ SONIC_THREAD_NUM
+} THREAD_SONIC_ENUM;
+
+typedef struct{
+ kal_uint32 thread0 : 1;
+ kal_uint32 thread1 : 1;
+ kal_uint32 thread2 : 1;
+ kal_uint32 thread3 : 1;
+} THREAD_BITWISE_STRUCT;
+
+typedef struct{
+ kal_uint32 start_frc;
+ kal_uint32 end_frc;
+} TIME_RECORD_STRUCT;
+
+
+/********************************/
+/* Function extern */
+/********************************/
+
+extern void sonic_activate_by_btdma_ungate(void);
+extern void sonic_activate_by_release_idle(kal_uint32 th_bitmap);
+extern kal_uint32 sonic_activate(kal_uint32 th_bitmap);
+extern void sonic_deactivate(kal_uint32 th_bitmap);
+extern kal_uint32 sonic_check_activate_done(kal_uint32 th_bitmap);
+extern kal_uint32 sonic_check_deactivate_done(kal_uint32 th_bitmap);
+void sonic_deactivate_cb_n0(CSIF_ID_STATUS_t*);
+extern void sonic_clear_WFI_mask(void);
+extern kal_uint32 sonic_check_idle_flag_by_module(kal_uint32 thread_id, kal_uint32 user_id);
+
+#endif /*_SONIC_CONTROL_H_*/
diff --git a/mcu/service/sst/include/spv_api.h b/mcu/service/sst/include/spv_api.h
new file mode 100644
index 0000000..3e866a5
--- /dev/null
+++ b/mcu/service/sst/include/spv_api.h
@@ -0,0 +1,1014 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ * spv_api.h
+ *
+ * Project:
+ * -----------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * SPV Related API Code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 16 2020 yunciou.lin
+ * [MOLY00546717] [MT6833] [Palmer] feature check-in: SPV option & disable emimpu for palmer bringup.
+ * [Palmer] feature check-in:
+ * SPV option &
+ * disable emimpu for palmer bringup.
+ *
+ * 02 07 2020 chia-fu.lee
+ * [MOLY00475722] [VMOLY][MT6853] Mouton call for check in
+ *
+ * [SSS] Trace feature support on sampling mode
+ *
+ * 01 21 2020 justin.chen
+ * [MOLY00475722] [VMOLY][MT6853] Mouton call for check in
+ * . Update SPV related file.
+ *
+ * 12 26 2019 justin.chen
+ * [MOLY00462986] [MT6885] elm driver development
+ * .Update MT6873 force latency API.
+ *
+ * 12 26 2019 gway.lo
+ * [MOLY00462986] [MT6885] elm driver development
+ * 1. word count threshold change api
+ * 2. toggle elm on/off api
+ *
+ * 12 24 2019 gway.lo
+ * [MOLY00462986] [MT6885] elm driver development
+ *
+ * enable Margaux ELM 2nd assert
+ *
+ * 12 06 2019 chia-fu.lee
+ * [MOLY00460633] [MT6885][Petrus][MP1][SQC][CTC][FT][NSA][5G FT][China][Shanghai][Extension FT][MDST][CAT]md1:(MCU_core0,vpe1,tc2(VPE1)) [ASSERT] file:mcu/l1/ul1/ul1d_public/ul1_bb_error_check.c line:108
+ *
+ * Rollback debugging patch for UL1 HRT fail issue
+ *
+ * 11 12 2019 chia-fu.lee
+ * [MOLY00458740] [MT6885][Petrus][MP1][SQC][CTC][FT][NSA][5G FT][China][Suzhou][Extension FT][MDST][CAT]file:mcu/l1/ul1/ul1d_public/ul1_bb_error_check.c line:108
+ *
+ * EWSP0000059818
+ * SSS debugging patch
+ *
+ * 11 07 2019 gway.lo
+ * [MOLY00457526] [MT6873] driver porting
+ * disable elm assert mode and porting emi force latency api on MT6873
+ *
+ * 09 19 2019 gway.lo
+ * [MOLY00403390] [MT6297] ELM driver development
+ * petrus force emi latency
+ *
+ * 09 19 2019 chia-fu.lee
+ * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time
+ *
+ * Rollback debug patch for IRQ0xF5 issue
+ *
+ * 08 26 2019 chia-fu.lee
+ * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time
+ *
+ * Fixed Mercury(MD97P) build error.
+ *
+ * 08 26 2019 chia-fu.lee
+ * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time
+ * SSS Profiling
+ *
+ * 05 27 2019 gway.lo
+ * [MOLY00408920] [MT6297] SPV long time profile update
+ * long time profile feature update
+ *
+ * 04 12 2019 gway.lo
+ * [MOLY00398406] [MT6297] SS SPV AMIF profile feature
+ * AMIF profiling feature
+ *
+ * 01 14 2019 chia-fu.lee
+ * [MOLY00378963] [SystemService][MT6297] SWLA and CM2 counter / SSS PMU Profiling Development
+ *
+ * SSS PMU Profiling API
+ *
+ * 12 18 2018 gway.lo
+ * [MOLY00367306] [MT6297][SPV] basic profiling code check-in
+ * fix build error
+ *
+ * 12 18 2018 gway.lo
+ * [MOLY00367306] [MT6297][SPV] basic profiling code check-in
+ * force emi latenct, long time profiling
+ *
+ * 07 16 2018 chia-fu.lee
+ * [MOLY00338914] [SPV][Gen95] EBM in BW runtime profiling
+ *
+ * .
+ *
+ * 05 21 2018 chia-fu.lee
+ * [MOLY00327212] [Gen95][L2C LOCK]Remove Static L2 Cache Lock input sections
+ *
+ * [UMOLYE] SPV service Remove Static L2 Cache Lock input sections
+ *
+ * 04 02 2018 chin-chieh.hung
+ * [MOLY00309439] Eiger SPV utilities support
+ * Update EBM driver for Gen95
+ *
+ * 03 19 2018 chia-fu.lee
+ * [MOLY00313462] [Gen95] SPV_SVC porting
+ * SPV_SVC modification support write latency information
+ *
+ * 03 14 2018 chia-fu.lee
+ * [MOLY00313462] [Gen95] SPV_SVC porting
+ *
+ * Modify ELM part
+ *
+ * 03 13 2018 chin-chieh.hung
+ * [MOLY00309439] Eiger SPV utilities support
+ * Disable EMI latency count by 26Mhz
+ *
+ * 03 08 2018 peng-chih.wang
+ * [MOLY00312351] [System Service] Add M4 force latency and AT cmd for Gen95 PS SPV
+ * Eiger PS SPV -- porting force M4 latency and AT cmd.
+ *
+ * 02 23 2018 chin-chieh.hung
+ * [MOLY00309439] Eiger SPV utilities support
+ * Add Gen95 SPV utilities - Force Latency / EBM counter
+ *
+ * 09 07 2017 yen-chun.liu
+ * [MOLY00274402] [Gen93] SPV profiling utility
+ * BW/latency profiling code v2.
+ *
+ * 09 07 2017 yen-chun.liu
+ * [MOLY00274402] [Gen93] SPV profiling utility
+ * BW/latency runtime profiling.
+ *
+ * 07 24 2017 wellken.chen
+ * [MOLY00265986] [SPVSVC] Add spv service 1st version related
+ *
+ * 06 02 2017 linson.du
+ * [MOLY00254730] [Gen93]: ELM driver update for EMI latency issue
+ * ELM driver update for SPV usage.
+ *
+ * 07 14 2015 wellken.chen
+ * [MOLY00128710] [Jade][SPV] Refine SPV API realted code
+ *
+ *
+ *
+ *
+ *
+ ****************************************************************************/
+
+
+#ifndef __SPV_API_H_
+#define __SPV_API_H_
+
+#include "reg_base.h"
+#include "kal_general_types.h"
+#include "elm.h"
+
+#if defined(__FORCE_EMI_LATENCY_ENABLE__)
+#if defined(MT6763)||defined(MT3967) //use AP EMI
+
+#define SPV_MADDR_MEMAPB (0xC0219000)
+
+#define EMI_CONE (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x20)
+#define EMI_DRCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x78)
+#define EMI_ARBD (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x118)
+#define EMI_ARBE (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x120)
+#define EMI_SLCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x158)
+#define EMI_CONM (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x60)
+#define EMI_TESTB (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0xE8)
+
+#if !defined(__SPV_EBM_DRIVER__)
+#define EMI_BMEN (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x400)
+#define EMI_BCNT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x408)
+
+#define EMI_TSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x418)
+#define EMI_WSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x428)
+#define EMI_BACT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x430)
+#define EMI_BSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x438)
+#define EMI_MSEL (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x440)
+#define EMI_TSCT2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x448)
+#define EMI_WSCT2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x458)
+#define EMI_BMEN2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x4E8)
+
+
+#define EMI_TTYPE1 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x500)
+#define EMI_TTYPE2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x508)
+#define EMI_TTYPE3 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x510)
+#define EMI_TTYPE4 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x518)
+#define EMI_TTYPE5 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x520)
+#define EMI_TTYPE6 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x528)
+#define EMI_TTYPE7 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x53C)
+#endif //!defined(__SPV_EBM_DRIVER__)
+
+#if defined(MT3967) //use AP EMI
+
+#define EMI_FORCE_LATENCY(r, w) \
+ do {\
+ *EMI_CONE |= 1;\
+ *EMI_DRCT = 0x23110000;\
+ *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\
+ *EMI_SLCT = 0x1F011700;\
+ *EMI_CONM = 0xff000500;\
+ } while (0)
+
+#else
+
+//psmcu ultra
+#define SPV_PSMCU_QOS_CTL ((volatile kal_uint32 *)(BASE_MADDR_MDPERIMISC + 0xF0))
+
+#define EMI_FORCE_LATENCY(r, w) \
+ do {\
+ while (*SPV_PSMCU_QOS_CTL & 0x11) {*SPV_PSMCU_QOS_CTL &= ~(0x11);}\
+ *EMI_DRCT = 0x23110000;\
+ *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\
+ *EMI_SLCT = 0x1F011700;\
+ *EMI_CONM = 0xff000500;\
+ } while (0)
+
+#define EMI_FORCE_M4_LATENCY(r, w) \
+ do {\
+ while (*SPV_PSMCU_QOS_CTL & 0x11) {*SPV_PSMCU_QOS_CTL &= ~(0x11);}\
+ *EMI_DRCT = 0x23110000;\
+ *EMI_ARBE = 0x00003000 | (r<<16) | (w<<24);\
+ *EMI_SLCT = 0x1F011700;\
+ *EMI_CONM = 0xff000500;\
+ } while (0)
+#endif
+
+#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
+ do {\
+ *EMI_TESTB |= (1<<11);\
+ } while(0)
+
+#elif defined(MT6297)
+
+#define SPV_MADDR_MEMAPB (0xC0219000)
+
+#define EMI_CONE (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x20 )
+#define EMI_DRCT (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x78 )
+#define EMI_CONM (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x60 )
+#define EMI_TESTB (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xE8 )
+#define EMI_ARBD (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x118)
+#define EMI_ARBE_2ND (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x124)
+#define EMI_SLCT (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x158)
+#define EMI_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x710)
+#define EMI_BWLMTA (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x890)
+#define EMI_BWLMTF_2ND (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x8E4)
+#define EMI_BWLMTF_5TH (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x934)
+#define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD04)
+#define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD08)
+#define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD0C)
+#define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD10)
+#define EMI_QOS_MDR_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD14)
+#define EMI_QOS_MDR_SHF1 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD18)
+#define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD2C)
+#define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD30)
+
+#define EMI_FORCE_LATENCY(r, w) \
+ do {\
+ *EMI_CONE |= 1;\
+ *EMI_DRCT = 0x23110000;\
+ *EMI_SHF0 &= 0xFFFFFFF0; \
+ *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\
+ *EMI_ARBE_2ND = (*EMI_ARBE_2ND & 0x0000FFFF) | (r<<16) | (w<<24);\
+ *EMI_SLCT = 0x1F011700;\
+ *EMI_CONM = 0xff000500;\
+ \
+ *EMI_BWLMTA |= (0x01UL<< 3); \
+ *EMI_BWLMTA &= ~(0x01UL<<11); \
+ *EMI_BWLMTA &= ~(0x01UL<<27); \
+ *EMI_BWLMTF_2ND &= 0xFFFF0000UL; \
+ *EMI_BWLMTF_5TH &= 0xFFFF0000UL; \
+ *EMI_QOS_MDR_SHF0 = (*EMI_QOS_MDR_SHF0 & (0xFFF00000UL)) | (r&0xFF)<<8 | (r&0xFF); \
+ *EMI_QOS_MDR_SHF1 = (*EMI_QOS_MDR_SHF1 & (0xFFF00000UL)) | (r&0xFF)<<8 | (r&0xFF); \
+ *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0 & (0xFFF00000UL)) | (w&0xFF)<<8 | (w&0xFF); \
+ *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1 & (0xFFF00000UL)) | (w&0xFF)<<8 | (w&0xFF); \
+ *EMI_QOS_MDR_BE0A = 0x00000000; \
+ *EMI_QOS_MDR_BE0B = 0x00000000; \
+ *EMI_QOS_MDR_BE1A = 0x00000000; \
+ *EMI_QOS_MDR_BE1B = 0x00000000; \
+ } while (0)
+
+
+#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
+ do {\
+ *EMI_TESTB |= (1<<11);\
+ } while(0)
+
+#define FORCE_MD_ULTRA(p) \
+ do {\
+ if(p==0){\
+ DRV_ClrReg32(BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG+0x1C,(0xF<<16)); \
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\
+ DRV_WriteReg32(BASE_MADDR_MCOREPERI_INFRA_DSPSL2C+0x658, 0x0);\
+ }else{\
+ DRV_SetReg32(BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG+0x1C,(0xF<<16)); \
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0xEF);\
+ DRV_WriteReg32(BASE_MADDR_MCOREPERI_INFRA_DSPSL2C+0x658, 0x2AAAA);\
+ }\
+ } while(0)
+#elif defined(MT6885) || defined(MT6880)
+
+#define EMI_N_ARBE_2ND (volatile kal_uint32*)(0xC0219124)
+#define EMI_N_ARBD (volatile kal_uint32*)(0xC0219118)
+#define EMI_N_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC0219D14)
+#define EMI_N_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC0219D18)
+
+#define EMI_S_ARBE_2ND (volatile kal_uint32*)(0xC021D124)
+#define EMI_S_ARBD (volatile kal_uint32*)(0xC021D118)
+#define EMI_S_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC021DD14)
+#define EMI_S_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC021DD18)
+
+#define EMI_CH0_TESTB (volatile kal_uint32*)(0xC0235048)
+#define EMI_CH1_TESTB (volatile kal_uint32*)(0xC0245048)
+#define EMI_CH2_TESTB (volatile kal_uint32*)(0xC0255048)
+#define EMI_CH3_TESTB (volatile kal_uint32*)(0xC0265048)
+
+
+/***********************/
+
+#define EMI_TESTC (volatile kal_uint32*)(0xc02190f0)
+#define EMI_TESTC_S (volatile kal_uint32*)(0xc021d0f0)
+
+#define EMI_CONH_2ND (volatile kal_uint32*)(0xc021903c)
+#define EMI_CONH_2ND_S (volatile kal_uint32*)(0xc021d03c)
+
+#define EMI_BWLMTE_4TH (volatile kal_uint32*)(0xc0219920)
+#define EMI_BWLMTE_4TH_S (volatile kal_uint32*)(0xc021d920)
+
+#define EMI_BWLMTF_4TH (volatile kal_uint32*)(0xc0219924)
+#define EMI_BWLMTF_4TH_S (volatile kal_uint32*)(0xc021d924)
+
+#define EMI_BWLMTE_5TH (volatile kal_uint32*)(0xc0219930)
+#define EMI_BWLMTE_5TH_S (volatile kal_uint32*)(0xc021d930)
+#define EMI_BWLMTF_5TH (volatile kal_uint32*)(0xc0219934)
+#define EMI_BWLMTF_5TH_S (volatile kal_uint32*)(0xc021d934)
+#define EMI_BWLMTG_5TH (volatile kal_uint32*)(0xc0219938)
+#define EMI_BWLMTG_5TH_S (volatile kal_uint32*)(0xc021d938)
+
+#define EMI_BWLMTE (volatile kal_uint32*)(0xc02198A0)
+#define EMI_BWLMTE_S (volatile kal_uint32*)(0xc021d8A0)
+#define EMI_BWLMTF (volatile kal_uint32*)(0xc02198A4)
+#define EMI_BWLMTF_S (volatile kal_uint32*)(0xc021d8A4)
+
+#define EMI_BWLMTE_2ND (volatile kal_uint32*)(0xc02198E0)
+#define EMI_BWLMTE_2ND_S (volatile kal_uint32*)(0xc021d8E0)
+#define EMI_BWLMTF_2ND (volatile kal_uint32*)(0xc02198E4)
+#define EMI_BWLMTF_2ND_S (volatile kal_uint32*)(0xc021d8E4)
+#define EMI_BWLMTG_2ND (volatile kal_uint32*)(0xc02198E8)
+#define EMI_BWLMTG_2ND_S (volatile kal_uint32*)(0xc021d8E8)
+
+#define EMI_MDCT (volatile kal_uint32*)(0xc0219078)
+#define EMI_MDCT_S (volatile kal_uint32*)(0xc021d078)
+
+#define EMI_THRO_PRD2 (volatile kal_uint32*)(0xC021985C)
+#define EMI_THRO_PRD2_S (volatile kal_uint32*)(0xC021D85C)
+
+#define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(0xC0219D04)
+#define EMI_QOS_MDR_BE0A_S (volatile kal_uint32*)(0xC021DD04)
+#define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(0xC0219D08)
+#define EMI_QOS_MDR_BE0B_S (volatile kal_uint32*)(0xC021DD08)
+#define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(0xC0219D0C)
+#define EMI_QOS_MDR_BE1A_S (volatile kal_uint32*)(0xC021DD0C)
+#define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(0xC0219D10)
+#define EMI_QOS_MDR_BE1B_S (volatile kal_uint32*)(0xC021DD10)
+
+#define EMI_QOS_MDW_BE0A (volatile kal_uint32*)(0xC0219D1C)
+#define EMI_QOS_MDW_BE0A_S (volatile kal_uint32*)(0xC021DD1C)
+#define EMI_QOS_MDW_BE0B (volatile kal_uint32*)(0xC0219D20)
+#define EMI_QOS_MDW_BE0B_S (volatile kal_uint32*)(0xC021DD20)
+#define EMI_QOS_MDW_BE1A (volatile kal_uint32*)(0xC0219D24)
+#define EMI_QOS_MDW_BE1A_S (volatile kal_uint32*)(0xC021DD24)
+#define EMI_QOS_MDW_BE1B (volatile kal_uint32*)(0xC0219D28)
+#define EMI_QOS_MDW_BE1B_S (volatile kal_uint32*)(0xC021DD28)
+
+#define EMI_QOS_MDHWR_BE0A (volatile kal_uint32*)(0xC0219D98)
+#define EMI_QOS_MDHWR_BE0A_S (volatile kal_uint32*)(0xC021DD98)
+#define EMI_QOS_MDHWR_BE0B (volatile kal_uint32*)(0xC0219D9C)
+#define EMI_QOS_MDHWR_BE0B_S (volatile kal_uint32*)(0xC021DD9C)
+#define EMI_QOS_MDHWR_BE1A (volatile kal_uint32*)(0xC0219DA0)
+#define EMI_QOS_MDHWR_BE1A_S (volatile kal_uint32*)(0xC021DDA0)
+#define EMI_QOS_MDHWR_BE1B (volatile kal_uint32*)(0xC0219DA4)
+#define EMI_QOS_MDHWR_BE1B_S (volatile kal_uint32*)(0xC021DDA4)
+
+#define EMI_QOS_MDHWW_BE0A (volatile kal_uint32*)(0xC0219DAC)
+#define EMI_QOS_MDHWW_BE0A_S (volatile kal_uint32*)(0xC021DDAC)
+#define EMI_QOS_MDHWW_BE0B (volatile kal_uint32*)(0xC0219DB0)
+#define EMI_QOS_MDHWW_BE0B_S (volatile kal_uint32*)(0xC021DDB0)
+#define EMI_QOS_MDHWW_BE1A (volatile kal_uint32*)(0xC0219DB4)
+#define EMI_QOS_MDHWW_BE1A_S (volatile kal_uint32*)(0xC021DDB4)
+#define EMI_QOS_MDHWW_BE1B (volatile kal_uint32*)(0xC0219DB8)
+#define EMI_QOS_MDHWW_BE1B_S (volatile kal_uint32*)(0xC021DDB8)
+
+#define EMI_CONE (volatile kal_uint32*)(0xc0219020)
+#define EMI_CONE_S (volatile kal_uint32*)(0xc021d020)
+
+#define CH0_EMI_CONC (volatile kal_uint32*)(0xC0235010)
+#define CH1_EMI_CONC (volatile kal_uint32*)(0xC0245010)
+#define CH2_EMI_CONC (volatile kal_uint32*)(0xC0255010)
+#define CH3_EMI_CONC (volatile kal_uint32*)(0xC0265010)
+
+#define EMI_QOS_CTRL1 (volatile kal_uint32*)(0xc0219DF4)
+#define EMI_QOS_CTRL1_S (volatile kal_uint32*)(0xc021dDF4)
+
+#define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(0xc0219D2C)
+#define EMI_QOS_MDW_SHF0_S (volatile kal_uint32*)(0xc021dD2C)
+#define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(0xc0219D30)
+#define EMI_QOS_MDW_SHF1_S (volatile kal_uint32*)(0xc021dD30)
+
+/***********************/
+#define EMI_FORCE_LATENCY(r, w) \
+ do {\
+ *EMI_TESTC |= 1<<19;\
+ *EMI_TESTC_S |= 1<<19;\
+ *EMI_CONH_2ND |= 1<<9;\
+ *EMI_CONH_2ND_S |= 1<<9;\
+ *EMI_BWLMTE_4TH = 0xFFFFFFFF;\
+ *EMI_BWLMTE_4TH_S = 0xFFFFFFFF;\
+ *EMI_BWLMTF_4TH |= 0xFFFF;\
+ *EMI_BWLMTF_4TH_S |= 0xFFFF;\
+ *EMI_BWLMTE_5TH = 0xFFFFFFFF;\
+ *EMI_BWLMTE_5TH_S = 0xFFFFFFFF;\
+ *EMI_BWLMTF_5TH = 0xFFFFFFFF;\
+ *EMI_BWLMTF_5TH_S = 0xFFFFFFFF;\
+ *EMI_BWLMTG_5TH = 0xFFFFFFFF;\
+ *EMI_BWLMTG_5TH_S = 0xFFFFFFFF;\
+ *EMI_BWLMTE = 0xFF00FFFF;\
+ *EMI_BWLMTE_S = 0xFF00FFFF;\
+ *EMI_BWLMTF |= 0xFFFF;\
+ *EMI_BWLMTF_S |= 0xFFFF;\
+ *EMI_BWLMTE_2ND = 0xFFFFFFFF;\
+ *EMI_BWLMTE_2ND_S = 0xFFFFFFFF;\
+ *EMI_BWLMTF_2ND = 0xFFFF0000;\
+ *EMI_BWLMTF_2ND_S = 0xFFFF0000;\
+ *EMI_BWLMTG_2ND = 0xFFFFFFFF;\
+ *EMI_BWLMTG_2ND_S = 0xFFFFFFFF;\
+ *EMI_N_ARBD |= 1<<13;\
+ *EMI_S_ARBD |= 1<<13;\
+ *EMI_N_ARBD &= ~(1<<14);\
+ *EMI_S_ARBD &= ~(1<<14);\
+ *EMI_MDCT &= ~((1<<1)|(1<<3));\
+ *EMI_MDCT_S &= ~((1<<1)|(1<<3));\
+ *EMI_THRO_PRD2 |= (7<<24) | (7<<28);\
+ *EMI_THRO_PRD2_S |= (7<<24) | (7<<28);\
+ \
+ *EMI_QOS_MDR_BE0A = 0;\
+ *EMI_QOS_MDR_BE0B = 0;\
+ *EMI_QOS_MDR_BE1A = 0;\
+ *EMI_QOS_MDR_BE1B = 0;\
+ *EMI_QOS_MDW_BE0A = 0;\
+ *EMI_QOS_MDW_BE0B = 0;\
+ *EMI_QOS_MDW_BE1A = 0;\
+ *EMI_QOS_MDW_BE1B = 0;\
+ *EMI_QOS_MDR_BE0A_S = 0;\
+ *EMI_QOS_MDR_BE0B_S = 0;\
+ *EMI_QOS_MDR_BE1A_S = 0;\
+ *EMI_QOS_MDR_BE1B_S = 0;\
+ *EMI_QOS_MDW_BE0A_S = 0;\
+ *EMI_QOS_MDW_BE0B_S = 0;\
+ *EMI_QOS_MDW_BE1A_S = 0;\
+ *EMI_QOS_MDW_BE1B_S = 0;\
+ \
+ *EMI_QOS_MDHWR_BE0A = 0;\
+ *EMI_QOS_MDHWR_BE0B = 0;\
+ *EMI_QOS_MDHWR_BE1A = 0;\
+ *EMI_QOS_MDHWR_BE1B = 0;\
+ *EMI_QOS_MDHWW_BE0A = 0;\
+ *EMI_QOS_MDHWW_BE0B = 0;\
+ *EMI_QOS_MDHWW_BE1A = 0;\
+ *EMI_QOS_MDHWW_BE1B = 0;\
+ *EMI_QOS_MDHWR_BE0A_S = 0;\
+ *EMI_QOS_MDHWR_BE0B_S = 0;\
+ *EMI_QOS_MDHWR_BE1A_S = 0;\
+ *EMI_QOS_MDHWR_BE1B_S = 0;\
+ *EMI_QOS_MDHWW_BE0A_S = 0;\
+ *EMI_QOS_MDHWW_BE0B_S = 0;\
+ *EMI_QOS_MDHWW_BE1A_S = 0;\
+ *EMI_QOS_MDHWW_BE1B_S = 0;\
+ \
+ *EMI_N_ARBD = (*EMI_N_ARBD&0x00FFFFFF) | (w<<24);\
+ *EMI_N_ARBE_2ND = (*EMI_N_ARBE_2ND&0x00FFFFFF) | (w<<24);\
+ *EMI_S_ARBD = (*EMI_S_ARBD&0x00FFFFFF) | (w<<24);\
+ *EMI_S_ARBE_2ND = (*EMI_S_ARBE_2ND&0x00FFFFFF) | (w<<24);\
+ \
+ *EMI_CONE |= 1 ;\
+ *EMI_CONE_S |= 1 ;\
+ \
+ *CH0_EMI_CONC |= (1<<5) ;\
+ *CH1_EMI_CONC |= (1<<5) ;\
+ *CH2_EMI_CONC |= (1<<5) ;\
+ *CH3_EMI_CONC |= (1<<5) ;\
+ \
+ *EMI_QOS_CTRL1 &= ~((0x1<<11)|(0x1<<27));\
+ *EMI_QOS_CTRL1_S &= ~((0x1<<11)|(0x1<<27));\
+ \
+ *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0&0xffffff00) | w;\
+ *EMI_QOS_MDW_SHF0_S = (*EMI_QOS_MDW_SHF0_S&0xffffff00) | w;\
+ *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1&0xffffff00) | w;\
+ *EMI_QOS_MDW_SHF1_S = (*EMI_QOS_MDW_SHF1_S&0xffffff00) | w;\
+ \
+ *EMI_N_ARBE_2ND = (*EMI_N_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\
+ *EMI_N_ARBD = (*EMI_N_ARBD & 0xFF00FFFF) | (r<<16) ;\
+ *EMI_N_QOS_MDR_SHF0 = (*EMI_N_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\
+ *EMI_N_QOS_MDR_SHF1 = (*EMI_N_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\
+ \
+ *EMI_S_ARBE_2ND = (*EMI_S_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\
+ *EMI_S_ARBD = (*EMI_S_ARBD & 0xFF00FFFF) | (r<<16) ;\
+ *EMI_S_QOS_MDR_SHF0 = (*EMI_S_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\
+ *EMI_S_QOS_MDR_SHF1 = (*EMI_S_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\
+ \
+ *EMI_CH0_TESTB |= ((1<<6)|(1<<13)) ; \
+ *EMI_CH1_TESTB |= ((1<<6)|(1<<13)) ; \
+ *EMI_CH2_TESTB |= ((1<<6)|(1<<13)) ; \
+ *EMI_CH3_TESTB |= ((1<<6)|(1<<13)) ; \
+ } while (0)
+
+#define EMI_AGING_26M() \
+ do {\
+ *EMI_CONE &= ~(1<<0) ;\
+ *EMI_CONE_S &= ~(1<<0) ;\
+ *CH0_EMI_CONC &= ~(1<<5) ;\
+ *CH1_EMI_CONC &= ~(1<<5) ;\
+ *CH2_EMI_CONC &= ~(1<<5) ;\
+ *CH3_EMI_CONC &= ~(1<<5) ;\
+ } while (0)
+
+#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
+ do {\
+ *EMI_CH0_TESTB |= (1<<11) ; \
+ *EMI_CH1_TESTB |= (1<<11) ; \
+ *EMI_CH2_TESTB |= (1<<11) ; \
+ *EMI_CH3_TESTB |= (1<<11) ; \
+ } while(0)
+
+#define FORCE_MD_ULTRA(p) \
+ do {\
+ if(p==0){\
+ DRV_ClrReg32(0xa0060064,(0xf << 8)); \
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x0);\
+ DRV_WriteReg32(0xa4c00000+0x8658, 0x0);\
+ }else{\
+ DRV_SetReg32(0xa0060064,(0xf << 8)); \
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x7EF);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x7E00000);\
+ DRV_WriteReg32(0xa4c00000+0x8658, 0x2AAAA);\
+ }\
+ } while(0)
+
+#elif defined(MT6873) || defined(MT6853) || defined(MT6833)
+
+#define EMI_ARBE_2ND (volatile kal_uint32*)(0xC0219124)
+#define EMI_ARBD (volatile kal_uint32*)(0xC0219118)
+#define EMI_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC0219D14)
+#define EMI_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC0219D18)
+
+#define EMI_CH0_TESTB (volatile kal_uint32*)(0xC0235048)
+#define EMI_CH1_TESTB (volatile kal_uint32*)(0xC0245048)
+
+
+/***********************/
+
+#define EMI_TESTC (volatile kal_uint32*)(0xc02190f0)
+#define EMI_CONH_2ND (volatile kal_uint32*)(0xc021903c)
+#define EMI_BWLMTE_4TH (volatile kal_uint32*)(0xc0219920)
+#define EMI_BWLMTF_4TH (volatile kal_uint32*)(0xc0219924)
+
+#define EMI_BWLMTE_5TH (volatile kal_uint32*)(0xc0219930)
+#define EMI_BWLMTF_5TH (volatile kal_uint32*)(0xc0219934)
+#define EMI_BWLMTG_5TH (volatile kal_uint32*)(0xc0219938)
+
+#define EMI_BWLMTE (volatile kal_uint32*)(0xc02198A0)
+#define EMI_BWLMTF (volatile kal_uint32*)(0xc02198A4)
+
+#define EMI_BWLMTE_2ND (volatile kal_uint32*)(0xc02198E0)
+#define EMI_BWLMTF_2ND (volatile kal_uint32*)(0xc02198E4)
+#define EMI_BWLMTG_2ND (volatile kal_uint32*)(0xc02198E8)
+
+#define EMI_MDCT (volatile kal_uint32*)(0xc0219078)
+
+#define EMI_THRO_PRD2 (volatile kal_uint32*)(0xC021985C)
+
+#define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(0xC0219D04)
+#define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(0xC0219D08)
+#define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(0xC0219D0C)
+#define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(0xC0219D10)
+
+#define EMI_QOS_MDW_BE0A (volatile kal_uint32*)(0xC0219D1C)
+#define EMI_QOS_MDW_BE0B (volatile kal_uint32*)(0xC0219D20)
+#define EMI_QOS_MDW_BE1A (volatile kal_uint32*)(0xC0219D24)
+#define EMI_QOS_MDW_BE1B (volatile kal_uint32*)(0xC0219D28)
+
+#define EMI_QOS_MDHWR_BE0A (volatile kal_uint32*)(0xC0219D98)
+#define EMI_QOS_MDHWR_BE0B (volatile kal_uint32*)(0xC0219D9C)
+#define EMI_QOS_MDHWR_BE1A (volatile kal_uint32*)(0xC0219DA0)
+#define EMI_QOS_MDHWR_BE1B (volatile kal_uint32*)(0xC0219DA4)
+
+#define EMI_QOS_MDHWW_BE0A (volatile kal_uint32*)(0xC0219DAC)
+#define EMI_QOS_MDHWW_BE0B (volatile kal_uint32*)(0xC0219DB0)
+#define EMI_QOS_MDHWW_BE1A (volatile kal_uint32*)(0xC0219DB4)
+#define EMI_QOS_MDHWW_BE1B (volatile kal_uint32*)(0xC0219DB8)
+
+#define EMI_CONE (volatile kal_uint32*)(0xc0219020)
+
+#define CH0_EMI_CONC (volatile kal_uint32*)(0xC0235010)
+#define CH1_EMI_CONC (volatile kal_uint32*)(0xC0245010)
+
+#define EMI_QOS_CTRL1 (volatile kal_uint32*)(0xc0219DF4)
+
+#define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(0xc0219D2C)
+#define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(0xc0219D30)
+
+/***********************/
+#define EMI_FORCE_LATENCY(r, w) \
+ do {\
+ *EMI_TESTC |= 1<<19;\
+ *EMI_CONH_2ND |= 1<<9;\
+ *EMI_BWLMTE_4TH = 0xFFFFFFFF;\
+ *EMI_BWLMTF_4TH |= 0xFFFF;\
+ *EMI_BWLMTE_5TH = 0xFFFFFFFF;\
+ *EMI_BWLMTF_5TH = 0xFFFFFFFF;\
+ *EMI_BWLMTG_5TH = 0xFFFFFFFF;\
+ *EMI_BWLMTE = 0xFF00FFFF;\
+ *EMI_BWLMTF |= 0xFFFF;\
+ *EMI_BWLMTE_2ND = 0xFFFFFFFF;\
+ *EMI_BWLMTF_2ND = 0xFFFF0000;\
+ *EMI_BWLMTG_2ND = 0xFFFFFFFF;\
+ *EMI_ARBD |= 1<<13;\
+ *EMI_ARBD &= ~(1<<14);\
+ *EMI_MDCT &= ~((1<<1)|(1<<3));\
+ *EMI_THRO_PRD2 |= (7<<24) | (7<<28);\
+ \
+ *EMI_QOS_MDR_BE0A = 0;\
+ *EMI_QOS_MDR_BE0B = 0;\
+ *EMI_QOS_MDR_BE1A = 0;\
+ *EMI_QOS_MDR_BE1B = 0;\
+ *EMI_QOS_MDW_BE0A = 0;\
+ *EMI_QOS_MDW_BE0B = 0;\
+ *EMI_QOS_MDW_BE1A = 0;\
+ *EMI_QOS_MDW_BE1B = 0;\
+ \
+ *EMI_QOS_MDHWR_BE0A = 0;\
+ *EMI_QOS_MDHWR_BE0B = 0;\
+ *EMI_QOS_MDHWR_BE1A = 0;\
+ *EMI_QOS_MDHWR_BE1B = 0;\
+ *EMI_QOS_MDHWW_BE0A = 0;\
+ *EMI_QOS_MDHWW_BE0B = 0;\
+ *EMI_QOS_MDHWW_BE1A = 0;\
+ *EMI_QOS_MDHWW_BE1B = 0;\
+ \
+ *EMI_ARBD = (*EMI_ARBD&0x00FFFFFF) | (w<<24);\
+ *EMI_ARBE_2ND = (*EMI_ARBE_2ND&0x00FFFFFF) | (w<<24);\
+ \
+ *EMI_CONE |= 1 ;\
+ \
+ *CH0_EMI_CONC |= (1<<5) ;\
+ *CH1_EMI_CONC |= (1<<5) ;\
+ \
+ *EMI_QOS_CTRL1 &= ~((0x1<<11)|(0x1<<27));\
+ \
+ *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0&0xffffff00) | w;\
+ *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1&0xffffff00) | w;\
+ \
+ *EMI_ARBE_2ND = (*EMI_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\
+ *EMI_ARBD = (*EMI_ARBD & 0xFF00FFFF) | (r<<16) ;\
+ *EMI_QOS_MDR_SHF0 = (*EMI_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\
+ *EMI_QOS_MDR_SHF1 = (*EMI_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\
+ \
+ *EMI_CH0_TESTB |= ((1<<6)|(1<<13)) ; \
+ *EMI_CH1_TESTB |= ((1<<6)|(1<<13)) ; \
+ } while (0)
+
+#define EMI_AGING_26M() \
+ do {\
+ *EMI_CONE &= ~(1<<0) ;\
+ *CH0_EMI_CONC &= ~(1<<5) ;\
+ *CH1_EMI_CONC &= ~(1<<5) ;\
+ } while (0)
+
+
+#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
+ do {\
+ *EMI_CH0_TESTB |= (1<<11) ; \
+ *EMI_CH1_TESTB |= (1<<11) ; \
+ } while(0)
+
+#define FORCE_MD_ULTRA(p) \
+ do {\
+ if(p==0){\
+ DRV_ClrReg32(0xa0060064,(0xf << 8)); \
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x0);\
+ DRV_WriteReg32(0xa4c00000+0x8658, 0x0);\
+ }else{\
+ DRV_SetReg32(0xa0060064,(0xf << 8)); \
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x7EF);\
+ DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x7E00000);\
+ DRV_WriteReg32(0xa4c00000+0x8658, 0x2AAAA);\
+ }\
+ } while(0)
+
+#else
+ #error "No support force emi latency on this project"
+#endif
+
+#endif //__FORCE_EMI_LATENCY_ENABLE__
+
+
+//for spv_service.c
+typedef struct _ELM_BW_LOG_T
+{
+ kal_uint32 m3_r_word_count;
+ kal_uint32 m3_w_word_count;
+ kal_uint32 m4_r_word_count;
+ kal_uint32 m4_w_word_count;
+} ELM_BW_LOG_T;
+
+typedef struct __SPVSVC_MON {
+ kal_uint32 apb_Reliable;
+ kal_uint32 apb_CurIsWorst;
+ kal_uint32 apb_Duration;
+ kal_uint32 apb_Avg_RLat;
+ kal_uint32 apb_Avg_WLat;
+ kal_uint32 apb_Worst_AvgRLat;
+ kal_uint32 apb_Worst_AvgWLat;
+ kal_uint32 apb_Total_RCnt;
+ kal_uint32 apb_Total_WCnt;
+ kal_uint32 apb_Dummy0;
+
+ kal_uint32 cm2_Reliable;
+ kal_uint32 cm2_CurIsWorst;
+ kal_uint32 cm2_Duration;
+ kal_uint32 cm2_Avg_UC_RW;
+ kal_uint32 cm2_Avg_L2Cache_RW;
+ kal_uint32 cm2_Worst_AvgUC_RW;
+ kal_uint32 cm2_Worst_AvgL2Cache_RW;
+ kal_uint32 cm2_Total_UC_RW;
+ kal_uint32 cm2_Total_L2Cache_RW;
+ kal_uint32 cm2_Dummy0;
+
+ //might use union?
+ kal_uint32 elm_Reliable;
+ kal_uint32 elm_CurIsWorst;
+ kal_uint32 elm_Duration;
+ kal_uint32 elm_Avg_RLat;
+ kal_uint32 elm_Avg_WLat;
+ kal_uint32 elm_Worst_AvgRLat;
+ kal_uint32 elm_Worst_AvgWLat;
+ kal_uint32 elm_Total_RCnt;
+ kal_uint32 elm_Total_WCnt;
+ kal_uint32 elm_Dummy0;
+
+} SPVSVC_MON;
+
+kal_bool SPVSVC_Monitor_Get(SPVSVC_MON *pCnts);
+extern kal_bool SPVSVC_Monitor_LogClear(void);
+
+#if defined(__BW_RUNTIME_PF__)
+
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+#define __MD_ELM_TLW__
+#endif
+#define WRAP_MAX 0xFFFFFFFF
+#define DIFF_WRAP_TYPE(start, end) (((end) >= (start))? (((end) - (start))): ((WRAP_MAX - (start) + (end) + 1)))
+
+#if defined(__MD_ELM_TLW__)
+
+typedef struct _ELM_PROFILING_LOG_T
+{
+ kal_uint32 m3_r_transaction;
+ kal_uint32 m3_r_word_count;
+ kal_uint32 m3_r_latency;
+ kal_uint32 m3_w_transaction;
+ kal_uint32 m3_w_word_count;
+ kal_uint32 m3_w_latency;
+ kal_uint32 m4_r_transaction;
+ kal_uint32 m4_r_word_count;
+ kal_uint32 m4_r_latency;
+ kal_uint32 m4_w_transaction;
+ kal_uint32 m4_w_word_count;
+ kal_uint32 m4_w_latency;
+#if defined(MT6297)
+ kal_uint32 m4b_r_transaction;
+ kal_uint32 m4b_r_word_count;
+ kal_uint32 m4b_r_latency;
+ kal_uint32 m4b_w_transaction;
+ kal_uint32 m4b_w_word_count;
+ kal_uint32 m4b_w_latency;
+#endif
+} ELM_PROFILING_LOG_T;
+
+#define ELM_GET_M3_BW_LOG(c, l) do { \
+ ELM_GET_WC_CNT(ELM_RD, (c), &((l).m3_r_word_count));\
+ ELM_GET_WC_CNT(ELM_WR, (c), &((l).m3_w_word_count));\
+ } while (0)
+
+#define ELM_GET_M4_BW_LOG(c, l) do { \
+ ELM_INFRA_GET_WC_CNT(ELM_RD, (c), &((l).m4_r_word_count));\
+ ELM_INFRA_GET_WC_CNT(ELM_WR, (c), &((l).m4_w_word_count));\
+ } while (0)
+
+#define ELM_GET_M3_LATENCY_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m3_r_transaction));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m3_r_latency));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m3_w_transaction));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m3_w_latency));\
+ } while (0)
+
+#define ELM_GET_M4_LATENCY_LOG(c, l) do { \
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4_r_transaction));\
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4_r_latency));\
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4_w_transaction));\
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4_w_latency));\
+ } while (0)
+
+#if defined(MT6297)
+#define ELM_GET_M4B_LATENCY_LOG(c, l) do { \
+ ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4b_r_transaction));\
+ ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4b_r_latency));\
+ ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4b_w_transaction));\
+ ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4b_w_latency));\
+ } while (0)
+#define ELM_GET_M4B_BW_LOG(c, l) do { \
+ ELM_INFRA_B_GET_WC_CNT(ELM_RD, (c), &((l).m4b_r_word_count));\
+ ELM_INFRA_B_GET_WC_CNT(ELM_WR, (c), &((l).m4b_w_word_count));\
+ } while (0)
+#endif
+
+#else
+
+typedef struct _ELM_PROFILING_LOG_T
+{
+ kal_uint32 m3_r_transaction;
+ kal_uint32 m3_r_word_count;
+ kal_uint32 m3_r_latency;
+ kal_uint32 m3_w_word_count;
+ kal_uint32 m4_r_transaction;
+ kal_uint32 m4_r_word_count;
+ kal_uint32 m4_r_latency;
+ kal_uint32 m4_w_word_count;
+} ELM_PROFILING_LOG_T;
+
+#define ELM_GET_M3_BW_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m3_r_word_count));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m3_w_word_count));\
+ } while (0)
+
+#define ELM_GET_M4_BW_LOG(c, l) do { \
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4_r_word_count));\
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4_w_word_count));\
+ } while (0)
+
+#define ELM_GET_M3_LATENCY_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m3_r_transaction));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m3_r_latency));\
+ } while (0)
+
+#define ELM_GET_M4_LATENCY_LOG(c, l) do { \
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4_r_transaction));\
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4_r_latency));\
+ } while (0)
+
+#endif /* __MD_ELM_TLW__ */
+
+
+kal_bool SPVSVC_BW_PF(kal_uint32 core_id);
+void SPVSVC_BW_Max_Print(void);
+void SPVSVC_BW_Max_Clear(void);
+void SPVSVC_BW_Threshold_Print(void);
+
+extern volatile kal_uint32 RECORD_AP_DVFSRC;
+extern volatile kal_uint32 BW_index;
+extern kal_uint32 BW_Cor_Duration[] ;
+extern kal_uint32 BW_Cor_Duration_Low[] ;
+extern kal_uint32 BW_Cor_Duration_High[] ;
+
+extern volatile kal_uint32 BW_Cor_Duration_core[] ;
+
+extern volatile kal_uint32 BW_Cor_Enable;
+
+extern volatile kal_uint32 BW_M3_Worst_core[];
+extern volatile kal_uint32 BW_M3_Worst_Dur_core[];
+extern volatile kal_uint32 BW_M4_Worst_core[] ;
+extern volatile kal_uint32 BW_M4_Worst_Dur_core[];
+extern volatile kal_uint32 BW_M3M4_Worst_core[];
+extern volatile kal_uint32 BW_M3M4_Worst_Dur_core[];
+
+
+extern volatile kal_uint32 BW_Dur_Low_core[] ;
+extern volatile kal_uint32 BW_Dur_High_core[];
+
+extern volatile kal_uint32 BW_Cor_Raw_Data_Print_Enable;
+
+extern volatile kal_uint32 BW_Transaction_Low_core[];
+
+extern volatile kal_uint32 BW_M3_Assertion_core[];
+extern volatile kal_uint32 BW_M4_Assertion_core[];
+extern volatile kal_uint32 BW_M3M4_Assertion_core[];
+extern volatile kal_uint32 Latency_M3_Read_Assertion_core[];
+extern volatile kal_uint32 Latency_M4_Read_Assertion_core[];
+#if defined(__MD_ELM_TLW__)
+extern volatile kal_uint32 Latency_M3_Write_Assertion_core[];
+extern volatile kal_uint32 Latency_M4_Write_Assertion_core[];
+#endif
+
+extern void SPV_IdleTask0( task_entry_struct * task_entry_ptr );
+extern void SPV_IdleTask1( task_entry_struct * task_entry_ptr );
+extern void SPV_IdleTask2( task_entry_struct * task_entry_ptr );
+extern void SPV_IdleTask3( task_entry_struct * task_entry_ptr );
+
+#endif /* defined(__BW_RUNTIME_PF__) */
+
+#if 0 // official load profiling
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+void SSS_PF_INIT(void);
+void SSS_CORE_PMU_PF_WriteRecord(kal_uint32 flag);
+void SSS_CORE_PMU_PF_START(void);
+void SSS_CORE_PMU_PF_END(void);
+#if defined(__SPV_SSS_PF__)
+#if defined(__SPV_SSS_CORE_PMU_PF__)
+ #if defined(__MIPS16__)
+ #if defined(__GNUC__)
+ #define SSS_MIPS32_ISA __attribute__((nomips16))
+ #endif
+ #endif
+
+#ifndef SSS_MIPS32_ISA
+#define SSS_MIPS32_ISA
+#endif
+
+#define SSS_MIPS32_INLINE INLINE SSS_MIPS32_ISA
+#define STATIC_INLINE \
+ __attribute__((always_inline)) SSS_MIPS32_ISA static
+
+#if defined(__MD95__)
+#define MAX_CORE_PMU_NUM_PER_VPE 8 // 2 pmu counters per TC, 4 TCs per-core => 2*4 = 8
+#elif defined(__MD97__) || defined(__MD97P__)
+#define MAX_CORE_PMU_NUM_PER_VPE 12 // 4 pmu counters per VPE, 3 VPEs per-core => 4*3 = 12
+#endif
+
+typedef struct {
+ kal_int32 core_pmu_enable_return_state;
+ kal_int32 core_pmu_disable_return_state;
+ kal_int32 core_pmu_dump_return_state;
+ kal_uint32 frc_start;
+ kal_uint32 frc_end;
+ kal_uint32 cpu_cycle_start;
+ kal_uint32 core_pmu[MAX_CORE_PMU_NUM_PER_VPE];
+ kal_uint32 cpu_cycle_end;
+} SSS_CORE_PMU_PF_RECORD;
+
+#endif /* __SPV_SSS_CORE_PMU_PF__ */
+#endif /* __SPV_SSS_PF__ */
+
+#endif //__SPV_API_H_
+
diff --git a/mcu/service/sst/include/spv_service.h b/mcu/service/sst/include/spv_service.h
new file mode 100644
index 0000000..ce3e1a4
--- /dev/null
+++ b/mcu/service/sst/include/spv_service.h
@@ -0,0 +1,23 @@
+#ifndef __SPV_SERVICE_H__
+#define __SPV_SERVICE_H__
+
+#define SPV_MEM_DEBUG_RECORD_NUM 16
+#define SPV_MEM_DEBUG_PROFILE_THRESHOLD 32*1024
+
+#if !defined(__MAUI_BASIC__)
+#define __SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION__
+#endif
+
+#if defined(__SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION__)
+#define SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION_WINDOW 1000
+void spv_mpb_m3_bw_warn_cb(kal_uint32 frc, kal_uint32 window, kal_uint32 bw);
+#endif
+
+typedef struct mem_debug {
+ kal_uint32 retaddr;
+ kal_uint32 size;
+ kal_uint32 start_frc;
+ kal_uint32 end_frc;
+} mem_debug_t;
+
+#endif
diff --git a/mcu/service/sst/include/sst_defs.h b/mcu/service/sst/include/sst_defs.h
new file mode 100644
index 0000000..22464e6
--- /dev/null
+++ b/mcu/service/sst/include/sst_defs.h
@@ -0,0 +1,30 @@
+#ifndef _SST_DEFS_H
+#define _SST_DEFS_H
+
+#include "reg_base.h"
+#include <ex_mem_manager.h>
+
+#define EX_STACK_SIZE (8*1024)
+#define EX_DOR_EXCP_AREA_SIZE_PER_VPE (4*8) /*sizeof(EX_CPU_MIN_REG_T)*/
+
+
+#if defined(BASE_MADDR_PCCIF0_MD)
+#define BASE_MADDR_CCIF0_MD_REG_BASE BASE_MADDR_PCCIF0_MD
+#elif defined(BASE_MADDR_CCIF0_MD)
+#define BASE_MADDR_CCIF0_MD_REG_BASE BASE_MADDR_CCIF0_MD
+#else
+//TO FIX: #error "no ccif base define!!" __MD97__
+#define BASE_MADDR_CCIF0_MD_REG_BASE 0x0
+#endif
+
+//information from ccif owner: 0x100-> CCIF SRAM offset, 512-> SRAM size, 72-> last 72 bytes reserved for bootup trace
+#define MDCCIF_BOOTTRC_DATA (BASE_MADDR_CCIF0_MD_REG_BASE + 0x100 + 512 - 72)
+
+#define g_EMM_MAIN_BUFF_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*15)
+#define g_EMM_MAIN_BUFF_MAGIC 0x7274626E
+
+#define g_EMM_MAIN_BUFF_ADDR_PTR (MDCCIF_BOOTTRC_DATA + 0x4*16)
+#define g_EMM_MAIN_BUFF_SIZE_PTR (MDCCIF_BOOTTRC_DATA + 0x4*17)
+
+#define HS1_BOOT_TRACE_OFFSET EMM_EXRECORD_LEN
+#endif /* _SST_DEFS_H */
diff --git a/mcu/service/sst/include/sw_version.h b/mcu/service/sst/include/sw_version.h
new file mode 100644
index 0000000..4a5b2b6
--- /dev/null
+++ b/mcu/service/sst/include/sw_version.h
@@ -0,0 +1,8 @@
+#ifndef __SW_VERSION_H__
+#define __SW_VERSION_H__
+
+#include "sw_version_def_public.h"
+void ss_3gpp_sw_version_init(void);
+SW_VERSION_DEF_ENUM sw_version_query(void);
+
+#endif
diff --git a/mcu/service/sst/include/swtr.h b/mcu/service/sst/include/swtr.h
new file mode 100644
index 0000000..8942119
--- /dev/null
+++ b/mcu/service/sst/include/swtr.h
@@ -0,0 +1,197 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * swtr.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef SWTR_H
+#define SWTR_H
+
+#include "kal_public_api.h"
+#include "system_profiler_public.h"
+
+
+
+typedef struct ST_AddonInfo_T
+{
+ SYSPROFILER_ADDON_TYPE addonType;
+ kal_uint32 log_sz;
+ kal_char ext_name[12];
+ void (*ST_AddonInfoInitFunc)(void);
+ kal_bool ST_SwapOutLogging;
+ kal_uint8 *(*ST_AddonInfoLoggingFunc)(void);
+} ST_AddonInfo;
+
+/* Type Definition */
+typedef struct ST_LoggingNode_T
+{
+ kal_uint32 jobID;
+ kal_uint32 USCNT;
+ kal_uint32 CoreIDTCID;
+ kal_uint32 PC;
+} ST_LoggingNode;
+
+extern kal_uint8* ST_memory[];
+extern kal_uint32 ST_MALMO_ASM_ChangeContextID(kal_uint8);
+
+#define ST_Current_IsRunning() ST_IsRunning(kal_get_current_core_id())
+#define SWTR_IS_RUNNING(coreID) ( ST_memory[coreID] != NULL )
+
+
+INLINE INLINE_ALWAYS static kal_bool ST_IsRunning(kal_uint8 coreID)
+{
+ return SWTR_IS_RUNNING(coreID);
+}
+
+
+#if defined(__SYSTEM_PROFILER_ON__)
+SYSPROFILER_ADDON_TYPE ST_MALMO_ASM_Register( SYSPROFILER_ADDON_TYPE addonType, kal_uint8 coreID);
+#endif
+kal_bool ST_IsRunning(kal_uint8 coreID);
+SYSPROFILER_ERROR_CODE ST_Register_for_Core(SYSPROFILER_ADDON_TYPE addonType, kal_uint32 addonSize, kal_char addonName[], void (*ST_AddonInfoInitFunc)(void), kal_uint8* (*ST_AddonInfoLoggingFunc)(void), kal_bool ST_SwapOutLogging, kal_uint8 coreID) ;
+SYSPROFILER_ERROR_CODE ST_RetreiveLoggingBuffer(kal_uint8 **startAddr, kal_uint32 *size, kal_uint8 **currPtr, kal_uint8 coreID) ;
+SYSPROFILER_ERROR_CODE ST_RetrieveHeader(kal_uint8 **MADesc, kal_uint32 *szMADesc, kal_uint8 coreID) ;
+SYSPROFILER_ERROR_CODE ST_init_and_running_for_Core( kal_uint32 samplingRate, kal_uint32* bufferStartAddress, kal_uint32 bufferSize, kal_uint8 coreID);
+SYSPROFILER_ERROR_CODE ST_stop_for_Core(kal_uint8 coreID);
+
+#endif /* SWTR_H */
+
diff --git a/mcu/service/sst/include/us_excep_hdlr.h b/mcu/service/sst/include/us_excep_hdlr.h
new file mode 100644
index 0000000..01be875
--- /dev/null
+++ b/mcu/service/sst/include/us_excep_hdlr.h
@@ -0,0 +1,157 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * us_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * This file provides typedefs and definiton for PS index trace.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __US_EXCEP_HDLR_H__
+#define __US_EXCEP_HDLR_H__
+
+#include "usip_ex_common_def.h"
+#include "scq16_ex_common_def.h"
+#include "us_excep_hdlr_format.h"
+
+#include "kal_general_types.h"
+#include "ex_public.h"
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#define USIP_SCQ16_EX_SYNC_TIMEOUT 2000000 /* 2s, only for VRF. USIP,SCQ16: Please use EX_US_SYNC_TIME in cc_ex_item.h */
+#define USIP_SCQ16_EX_INIT_PATTERN 0x62935566
+#define USIP_SCQ16_SECTION_BUFFER_SIZE 256
+#if defined(MT6763) || defined(MT6739) || defined(MT6771) || defined(MT6765)
+ #define USIP0_APB_BASE 0xA0084000
+ #define USIP1_APB_BASE 0xA0085000
+ #define USIP_APB_DBG_EN_OFFSET 0x0
+ #define USIP_APB_MODE_SEL_OFFSET 0x4
+ #define USIP_APB_DBG_INST_OFFSET 0x10
+ #define USIP_APB_DBG_EXECUTE_OFFSET 0x14
+ #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18
+ #define USIP_APB_DBG_WRITE_OFFSET 0x1c
+ #define USIP_APB_DBG_STATUS_OFFSET 0x20
+
+ #define USIP_APB_DBG_ATTACH_INST 0x900
+ #define USIP_APB_DBG_REQ_INST 0x811
+ #define USIP_APB_DBG_STATUS_INST 0x803
+ #define USIP_APB_DBG_ADDR_INST 0x801
+ #define USIP_APB_DBG_PM_LOAD_INST 0x840
+ #define USIP_APB_DBG_INSTR_INST 0x802
+ #define USIP_APB_DBG_RESUME_INST 0x812
+
+ #define USIP_CACHE_ALIGN 0x20
+
+#endif
+
+typedef enum
+{
+ EX_STATUS_USIP0_0,
+ EX_STATUS_USIP0_1,
+ EX_STATUS_USIP1_0,
+ EX_STATUS_USIP1_1,
+ EX_STATUS_SCQ16_0,
+ EX_STATUS_SCQ16_1,
+#if !defined(__MD97_IS_2CORES__)
+/* H3 FPGA doesn't have scq16_2 and scq16_3 */
+ EX_STATUS_SCQ16_2,
+ EX_STATUS_SCQ16_3,
+#endif
+ EX_STATUS_USIP_SCQ16_CORE_NUM,
+ EX_STATUS_USIP_SCQ16_CORE_END = 0x6293beef
+} USIP_SCQ16_EX_STATUS_CORE_TYPE;
+
+
+typedef enum
+{
+ USIP0_0_FAIL_BIT_MASK = (1<<0),
+ USIP0_1_FAIL_BIT_MASK = (1<<1),
+ USIP1_0_FAIL_BIT_MASK = (1<<2),
+ USIP1_1_FAIL_BIT_MASK = (1<<3),
+ SCQ0_FAIL_BIT_MASK = (1<<4),
+ SCQ1_FAIL_BIT_MASK = (1<<5),
+ SCQ2_FAIL_BIT_MASK = (1<<6),
+ SCQ3_FAIL_BIT_MASK = (1<<7),
+} USIP_SCQ16_EX_CORE_BIT_MASK_TYPE;
+
+// ----------------- function declaration -------------------
+
+extern kal_bool INT_SyncUsipScqExceptionInfo(void);
+
+extern void INT_GetUsipScqExceptionRecord(USIP_SCQ_EXCEPTION_RECORD_T *record);
+
+extern kal_uint32 INT_GetUsipScqFailCore(void); //0~3: Usip, 4~5: Scq
+
+extern void INT_DumpUsipScqExceptionInfo(EX_TRACE_TYPE trace_type/*0=cadefa*/, kal_char* sys_info_str, kal_uint32 len);
+
+extern kal_char* INT_GetUsipScqCoreName(kal_uint32 core_index); //0~3: Usip, 4~5: Scq
+
+extern kal_uint32 INT_GetUsipScqFailCoreIndex(void);
+
+extern void INT_GetUsipScq16ExceptionHandshakeInit(void);
+
+extern void INT_GetUsipScq16BBMemoryInfo(void);
+
+extern void INT_GetUsip0DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+extern void INT_GetUsip1DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+extern void INT_GetScq160DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+extern void INT_GetScq161DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+extern void INT_GetScq162DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+extern void INT_GetScq163DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+extern void INT_GetVrfDumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
+
+#endif /* __US_EXCEP_HDLR_H__ */
diff --git a/mcu/service/sst/include/us_excep_hdlr_format.h b/mcu/service/sst/include/us_excep_hdlr_format.h
new file mode 100644
index 0000000..3593ed0
--- /dev/null
+++ b/mcu/service/sst/include/us_excep_hdlr_format.h
@@ -0,0 +1,153 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * usip_excep_hdlr_format.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * This file provides typedefs and definiton for .
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __USIP_EXCEP_HDLR_FORMAT_H__
+#define __USIP_EXCEP_HDLR_FORMAT_H__
+
+// ----------------- macro definition ---------------
+//SCQ16_MAX_NUM is defined in usip_ex_common_def.h so it could not be referenced by REL_SUB_L4
+#if defined(__MD97__) || defined(__MD97P__)
+#define SCQ16_MAXIMUM_NUM (4) //this is a maximum core number of SCQ16. unique value per generation
+#else
+#define SCQ16_MAXIMUM_NUM (2)
+#endif
+#define USIP_CORE_NUMBER (2)
+#define USIP_THREAD_NUMBER (2)
+#define USIP_TOTAL_THREAD_NUMBER (USIP_CORE_NUMBER * USIP_THREAD_NUMBER)
+#if defined(__MD95__)
+#define SCQ16_CORE_NUMBER (2)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define SCQ16_CORE_NUMBER (4)
+#endif
+#define USIP_SCQ16_TOTAL_THREAD_NUM (USIP_TOTAL_THREAD_NUMBER+SCQ16_CORE_NUMBER)
+// ----------------- data type Definition -------------------
+typedef enum {
+ USIP_SCQ16_EXCEPTION_ASSERTION = 0x45584300,
+ USIP_SCQ16_EXCEPTION_FATAL_ERROR,
+ USIP_SCQ16_EXCEPTION_CTI_EVENT,
+ USIP_SCQ16_EXCEPTION_UNKNOWN
+} USIP_SCQ16_EXCEPTION_TYPE_T;
+
+#if defined(__GNUC__)
+typedef struct __attribute__((packed)) {
+#else
+#pragma pack(1)
+typedef struct {
+#endif // __GNUC__
+ unsigned int line_num;
+ unsigned int para1;
+ unsigned int para2;
+ unsigned int para3;
+ char* filepath_ptr;
+ unsigned char file_name[64];
+} ASSERTION_INFO_T;
+#if !defined(__GNUC__)
+#pragma pack()
+#endif // __GNUC__
+
+#if defined(__GNUC__)
+typedef struct __attribute__((packed)) {
+#else
+#pragma pack(1)
+typedef struct {
+#endif // __GNUC__
+ unsigned int error_status;
+ unsigned int error_pc;
+ unsigned int error_lr;
+ unsigned int error_address;
+ unsigned int error_code1;
+ unsigned int error_code2;
+ unsigned char error_section;
+} FATAL_ERROR_INFO_T;
+#if !defined(__GNUC__)
+#pragma pack()
+#endif // __GNUC__
+
+#if defined(__GNUC__)
+typedef struct __attribute__((packed)) {
+#else
+#pragma pack(1)
+typedef struct {
+#endif
+#if !defined(_MSC_VER)
+ USIP_SCQ16_EXCEPTION_TYPE_T except_type;
+#else
+ kal_uint8 except_type;
+#endif
+ unsigned int except_stat;
+ union {
+ ASSERTION_INFO_T assert;
+ FATAL_ERROR_INFO_T fatal;
+ }except_content;
+} USIP_SCQ_EXCEPTION_INFO_T;
+#if !defined(__GNUC__)
+#pragma pack()
+#endif // __GNUC__
+
+typedef struct {
+ unsigned int core_num;
+ USIP_SCQ_EXCEPTION_INFO_T core_error[USIP_SCQ16_TOTAL_THREAD_NUM];
+} USIP_SCQ_EXCEPTION_RECORD_T;
+
+
+#endif /* __USIP_EXCEP_HDLR_FORMAT_H__ */
+
diff --git a/mcu/service/sst/include/us_trc.h b/mcu/service/sst/include/us_trc.h
new file mode 100644
index 0000000..f034c1f
--- /dev/null
+++ b/mcu/service/sst/include/us_trc.h
@@ -0,0 +1,136 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * us_trc.h
+ *
+ * Project:
+ * --------
+ * UMOLYA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _US_TRC_H
+#define _US_TRC_H
+
+ TRC_MSG(USIP_SCQ16_EX_LOG_ASSERT, "[%s(%s)] Assert fail: %s - %d 0x%x 0x%x 0x%x")
+ TRC_MSG(USIP_SCQ16_EX_LOG_FATAL_ERROR, "[%s(%s)] Fatal error: code1 0x%x, code2 0x%x, sp 0x%x, lr 0x%x, lisr level %d")
+ TRC_MSG(USIP_SCQ16_EX_LOG_CTI, "[%s(%s)] Cross Trigger by other core")
+ TRC_MSG(USIP_SCQ16_EX_LOG_UNKNOWN, "[%s(%s)] Unknown exception")
+
+ TRC_MSG(USIP_SCQ16_EX_LOG_BYPASS_DUMP_INFO, "[%s] status 0x%x")
+
+ TRC_MSG(USIP_SCQ16_EX_LOG_SYNCED_MASK, "USIP/SCQ16 sync mask 0x%x")
+
+ TRC_MSG(USIP_SCQ16_COMMON_DOWNLOAD_NOT_DONE_INFO, "[%s] first boot common part not yet download done...")
+ TRC_MSG(USIP_SCQ16_COMMON_DOWNLOAD_DONE_INFO, "[%s] first boot common part download done...")
+ TRC_MSG(USIP_SCQ16_DDL_DOWNLOAD_NOT_DONE_INFO, "[%s] first boot ddl part not yet download done...")
+ TRC_MSG(USIP_SCQ16_DDL_DOWNLOAD_DONE_INFO, "[%s] first boot ddl part download done...")
+ TRC_MSG(USIP_SCQ16_FEC_TX_DDL_START, "[DDL][FEC_TX-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_FEC_RX_DDL_START, "[DDL][FEC_RX-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_BRP_DDL_START, "[DDL][BRP-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_SCQ16_DDL_START, "[DDL][SCQ16-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_INNER_DDL_START, "[DDL][L2TCM-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_RAKE_DDL_START, "[DDL][RAKE-START] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X")
+
+ TRC_MSG(USIP_SCQ16_SCQ16_DDL_START_GDMA, "[DDL][SCQ16-TRIG_GDMA] idx: 0x%X, time: 0x%X, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X, len: 0x%X")
+ TRC_MSG(USIP_SCQ16_RAKE_DDL_START_GDMA, "[DDL][RAKE-TRIG_GDMA] iA start gdma for rake ddl, idx: 0x%X, time: 0x%X, bin_mode: 0x%X, len: 0x%X")
+
+ TRC_MSG(USIP_SCQ16_SET_INNER_DDL_PROTECT_DONE, "[DDL][L2TCM-Done] idx: 0x%X, time: 0x%X")
+ TRC_MSG(USIP_SCQ16_RAKE_DDL_DONE, "[DDL][RAKE-Done] idx: 0x%X, time: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_GDMA_DONE, "[DDL][SCQ16-GDMA-Done] idx: 0x%X, time: 0x%X, bin_mode: 0x%X")
+
+ TRC_MSG(USIP_SCQ16_RAKE_DDL_LAST_MODE_IS_LTE, "[DDL][RAKE] last mode is lte, caller 0x%X, user_id: 0x%X, bin_mode: 0x%X, status: 0x%X")
+ TRC_MSG(USIP_SCQ16_TRIG_CLR_INNER_DDL_PROTECT, "[DDL][L2TCM] iA trigger to clear inner ddl protection, caller: 0x%X")
+ TRC_MSG(USIP_SCQ16_CLR_INNER_DDL_PROTECT_DONE, "[DDL][L2TCM] clear inner ddl protection done, re_call_rake_ddl_user: 0x%X, re_call_rake_ddl_mode:0x%X")
+ TRC_MSG(USIP_SCQ16_SEND_INT_TO_INNER_CLR_DDL_PROTECT, "[DDL][L2TCM] iA send interrupt to usip-inner to clear inner ddl protection,caller: 0x%X, user_id: 0x%X, bin_mode: 0x%X, status: 0x%X")
+ TRC_MSG(USIP_SCQ16_SEND_INT_TO_INNER_TO_SET_DDL_PROTECT, "[DDL][L2TCM] iA send interrupt to usip-inner to set inner ddl protection, idx: 0x%X, time: 0x%X, bin_mode: 0x%X")
+ TRC_MSG(USIP_SCQ16_DSP_GDMA_CB, "[DDL] DSPGDMA_CB gdma done, gdma_who_use: 0x%X, gdma_who_wait:0x%X")
+
+ TRC_MSG(USIP_SCQ16_DDL_STATUS_BIN_MODE_INFO, "[DDL][%s] ddl_status: 0x%X, ddl_bin_mode: 0x%X")
+
+ TRC_MSG(USIP_SCQ16_EX_REPORT_VU_STATUS, "[USIP(%s)] SCQ16_%d VU status, status %s")
+
+ TRC_MSG(DSP_SLEEP_FLOW_ACTIVATE, "[DSP]DSP activate, thread %d, user %d, status 0x%x")
+ TRC_MSG(DSP_SLEEP_FLOW_DEACTIVATE, "[DSP]DSP deactivate, thread %d, user %d, status 0x%x")
+ TRC_MSG(DSP_SLEEP_FLOW_ACTIVATE_END, "[DSP]DSP activate end, return %d, thread %d, user %d, status 0x%x")
+ TRC_MSG(DSP_SLEEP_FLOW_DEACTIVATE_END, "[DSP]DSP deactivate end, return %d, thread %d, user %d, status 0x%x")
+#endif //_US_TRC_H
+
diff --git a/mcu/service/sst/include/vc_excep_hdlr.h b/mcu/service/sst/include/vc_excep_hdlr.h
new file mode 100644
index 0000000..a7abdcf
--- /dev/null
+++ b/mcu/service/sst/include/vc_excep_hdlr.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * vc_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * The extern exception functions for VoLTE core Linux
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ * removed!
+ * removed!
+ * removed!
+ *
+ ****************************************************************************/
+
+#ifndef __VC_EXCEP_HDLR_H__
+#define __VC_EXCEP_HDLR_H__
+
+#include "kal_general_types.h"
+#include "vc_excep_hdlr_format.h"
+
+//------------------------------------------------------------------
+//
+// macros
+//
+// the synchronization time, 3 seconds
+#define VC_EXCEPTION_SYNC_TIME (3 * 1000 * 1000)
+//------------------------------------------------------------------
+
+
+//------------------------------------------------------------------
+//
+// extern functions
+//
+/* sync function */
+extern kal_bool INT_SyncVCExceptionInfo(void);
+/* get exception record */
+extern void INT_GetVCExceptionRecord(VC_EXCEPTION_RECORD_T *record);
+/* dump exception info */
+extern void INT_DumpVCExceptionInfo(kal_uint32 trace_type /*0=cadefa*/, kal_char* sys_info_str, kal_uint32 len);
+//------------------------------------------------------------------
+
+#endif /* __VCC_EXCEP_HDLR_H__ */
diff --git a/mcu/service/sst/include/vc_excep_hdlr_format.h b/mcu/service/sst/include/vc_excep_hdlr_format.h
new file mode 100644
index 0000000..f97e009
--- /dev/null
+++ b/mcu/service/sst/include/vc_excep_hdlr_format.h
@@ -0,0 +1,143 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * vc_excep_hdlr.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * The format of exception record for VoLTE core Linux.
+ * It will be copied from Bach.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __VC_EXCEP_HDLR_FORMAT_H__
+#define __VC_EXCEP_HDLR_FORMAT_H__
+
+//------------------------------------------------------------------
+//
+// macros
+//
+#define VC_EXCEPTION_RECORD_T duos_excp_rec_t
+
+//------------------------------------------------------------------
+//
+// enums
+//
+enum {
+ VC_EX_STATUS_INIT = 0,
+ VC_EX_STATUS_INIT_DONE,
+ VC_EX_STATUS_TRIGGER_CTI,
+ VC_EX_STATUS_SAVE_EX_INFO,
+ VC_EX_STATUS_SAVE_EX_DONE,
+ VC_EX_STATUS_SAVE_SW_VERSION,
+ VC_EX_STATUS_SAVE_SW_VERSION_DONE,
+ VC_EX_STATUS_CACHE_FLUSH,
+ VC_EX_STATUS_CACHE_FLUSH_DONE,
+ VC_EX_STATUS_READY,
+ VC_EX_STATUS_END,
+};
+
+enum {
+ VC_EX_REASON_ECT = 1,
+ VC_EX_REASON_NMI,
+ VC_EX_REASON_BUG,
+ VC_EX_REASON_BUG_ON,
+ VC_EX_REASON_DIE_KERNEL,
+ VC_EX_REASON_PANIC,
+ VC_EX_REASON_END,
+};
+//------------------------------------------------------------------
+
+
+//------------------------------------------------------------------
+//
+// structures
+//
+// error table
+typedef struct{
+ unsigned int err_code;
+ const char *err_msg;
+} duos_linux_err_tab_t;
+
+// assert table
+typedef struct{
+ unsigned int line_num;
+ unsigned int para1;
+ unsigned int para2;
+ unsigned int para3;
+ char file_name[64];
+}duos_excp_assert_tlb;
+
+// fatal table
+typedef struct{
+ unsigned int error_status;
+ unsigned int error_pc;
+ unsigned int error_lr;
+ unsigned int error_address;
+ unsigned int error_code1;
+ unsigned int error_code2;
+}duos_excp_fatal_tlb;
+
+// exception record
+typedef struct{
+ unsigned int except_type;
+ unsigned int except_stat;
+ union{
+ duos_excp_assert_tlb assert;
+ duos_excp_fatal_tlb fatal;
+ } except_content;
+}duos_excp_rec_t;
+//------------------------------------------------------------------
+
+#endif /* __VC_EXCEP_HDLR_FORMAT_H__ */
diff --git a/mcu/service/sst/include/vc_trc.h b/mcu/service/sst/include/vc_trc.h
new file mode 100644
index 0000000..857a72b
--- /dev/null
+++ b/mcu/service/sst/include/vc_trc.h
@@ -0,0 +1,78 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * vc_trc.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target (VoLTE core Linux).
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ ****************************************************************************/
+#ifndef __VC_TRC_H__
+#define __VC_TRC_H__
+
+ TRC_MSG(VC_EX_LOG_ASSERT, "[VC] %s fail: %s -%d 0x%x, 0x%x, 0x%x")
+ TRC_MSG(VC_EX_LOG_FATAL, "[VC] %s fail: stat 0x%x, pc 0x%x, lr 0x%x, addr 0x%x, 0x%x, 0x%x")
+
+#endif /* __VC_TRC_H__ */
+