[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/service/sst/include/dsp_cache.h b/mcu/service/sst/include/dsp_cache.h
new file mode 100644
index 0000000..cd5f60c
--- /dev/null
+++ b/mcu/service/sst/include/dsp_cache.h
@@ -0,0 +1,97 @@
+#ifndef __SVC_EX_USIP_CACHE_DUMP_H__
+#define __SVC_EX_USIP_CACHE_DUMP_H__
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+#include "dsp_cache_public.h"
+
+/*******************************************************************************
+ * USIP APB Definition
+ *******************************************************************************/
+
+#if defined(__MD97__)
+ #define USIP0_APB_BASE BASE_MADDR_USIP0_0_USIP0
+ #define USIP1_APB_BASE BASE_MADDR_USIP1_0_USIP1
+ #define USIP_APB_DBG_EN_OFFSET 0x0
+ #define USIP_APB_MODE_SEL_OFFSET 0x4
+ #define USIP_APB_DBG_INST_OFFSET 0x10
+ #define USIP_APB_DBG_EXECUTE_OFFSET 0x14
+ #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18
+ #define USIP_APB_DBG_WRITE_OFFSET 0x1c
+ #define USIP_APB_DBG_STATUS_OFFSET 0x20
+
+ #define USIP_APB_DBG_ATTACH_INST 0x900
+ #define USIP_APB_DBG_REQ_INST 0x811
+ #define USIP_APB_DBG_STATUS_INST 0x803
+ #define USIP_APB_DBG_ADDR_INST 0x801
+ #define USIP_APB_DBG_PM_LOAD_INST 0x840
+ #define USIP_APB_DBG_INSTR_INST 0x802
+ #define USIP_APB_DBG_RESUME_INST 0x812
+
+ #define USIP_CACHE_ALIGN 0x20
+#elif defined(__MD97P__)
+ #define USIP0_APB_BASE BASE_MADDR_USIP0_USIP0
+ #define USIP1_APB_BASE BASE_MADDR_USIP1_USIP1
+ #define USIP_APB_DBG_EN_OFFSET 0x0
+ #define USIP_APB_MODE_SEL_OFFSET 0x4
+ #define USIP_APB_DBG_INST_OFFSET 0x10
+ #define USIP_APB_DBG_EXECUTE_OFFSET 0x14
+ #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18
+ #define USIP_APB_DBG_WRITE_OFFSET 0x1c
+ #define USIP_APB_DBG_STATUS_OFFSET 0x20
+
+ #define USIP_APB_DBG_ATTACH_INST 0x900
+ #define USIP_APB_DBG_REQ_INST 0x811
+ #define USIP_APB_DBG_STATUS_INST 0x803
+ #define USIP_APB_DBG_ADDR_INST 0x801
+ #define USIP_APB_DBG_PM_LOAD_INST 0x840
+ #define USIP_APB_DBG_INSTR_INST 0x802
+ #define USIP_APB_DBG_RESUME_INST 0x812
+
+ #define USIP_CACHE_ALIGN 0x20
+#else
+ #error "undefined platform"
+#endif
+
+/*******************************************************************************
+ * Enum
+ *******************************************************************************/
+typedef enum {
+ EX_IABT_NONE = 0xA0000000,
+ EX_READ_USIP_IABT_PC_DONE = 0xA0000001,
+ EX_READ_USIP_IABT_PATTERN_DONE = 0xA0000010,
+ EX_ENABLE_USIP_DBG_MODE_GET_ICACHE_CONTENT_START = 0xA0000020,
+ EX_ENABLE_USIP_DBG_MODE_START = 0xA0000030,
+ EX_ENABLE_USIP_DBG_MODE_DONE = 0xA0000040,
+ EX_USIP_ICAHCE_READ_START = 0xA0000050,
+ EX_USIP_ICAHCE_READ_DONE = 0xA0000060,
+ EX_USIP_RESUME_DONE = 0xA0000070
+} EX_USIP_ICACHE_RELATED_Step_Logging_t;
+
+/*******************************************************************************
+ * Macro
+ *******************************************************************************/
+#define EX_USIP_ICACHE_LOGGING_SYNC_TIMEOUT 2000000
+#define EX_USIP_ICACHE_LOGGING_STEP_SET(sts) ex_usip_icache_logging_step = (sts)
+
+
+#if defined(__MD97__) && defined(__MTK_TARGET__)
+
+#define MCORE_CLKCTRL_ADDR 0xA40A0040
+#define VCORE_CLKCTRL_ADDR 0xA50A0040
+
+#define MCORE_DCACHE_0_CLK_ON 0x10
+#define MCORE_DCACHE_1_CLK_ON 0x20
+#define MCORE_DCACHE_2_CLK_ON 0x40
+#define MCORE_DCACHE_3_CLK_ON 0x80
+
+#define VCORE_DCACHE_0_CLK_ON 0x1
+#define VCORE_DCACHE_1_CLK_ON 0x2
+#define VCORE_DCACHE_2_CLK_ON 0x4
+#define VCORE_DCACHE_3_CLK_ON 0x8
+
+extern void nr_bb_reg_init(void);
+
+#endif //defined(__MD97__) && defined(__MTK_TARGET__)
+
+#endif